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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.76 98.70 96.89 99.01 89.36 98.59 95.56 99.21


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T117 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.42434481 Oct 15 11:39:46 AM UTC 24 Oct 15 11:39:55 AM UTC 24 613427436 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.3415860430 Oct 15 11:39:52 AM UTC 24 Oct 15 11:39:56 AM UTC 24 132182338 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3763932006 Oct 15 11:39:50 AM UTC 24 Oct 15 11:39:56 AM UTC 24 214287050 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3893729261 Oct 15 11:39:51 AM UTC 24 Oct 15 11:39:56 AM UTC 24 118377457 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.394539219 Oct 15 11:39:51 AM UTC 24 Oct 15 11:39:56 AM UTC 24 111600972 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.192052669 Oct 15 11:39:54 AM UTC 24 Oct 15 11:39:56 AM UTC 24 25201646 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3770952940 Oct 15 11:39:54 AM UTC 24 Oct 15 11:39:57 AM UTC 24 24118422 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2795220652 Oct 15 11:39:51 AM UTC 24 Oct 15 11:39:57 AM UTC 24 344112059 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2873160190 Oct 15 11:39:54 AM UTC 24 Oct 15 11:39:57 AM UTC 24 69105939 ps
T1039 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2431473224 Oct 15 11:39:55 AM UTC 24 Oct 15 11:39:57 AM UTC 24 100120275 ps
T1040 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.2758122950 Oct 15 11:39:55 AM UTC 24 Oct 15 11:39:57 AM UTC 24 50810748 ps
T1041 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1675658917 Oct 15 11:39:55 AM UTC 24 Oct 15 11:39:58 AM UTC 24 20187107 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3312211716 Oct 15 11:39:55 AM UTC 24 Oct 15 11:39:58 AM UTC 24 280907107 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2475579739 Oct 15 11:39:55 AM UTC 24 Oct 15 11:39:58 AM UTC 24 182363993 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2224058325 Oct 15 11:39:54 AM UTC 24 Oct 15 11:39:58 AM UTC 24 235938327 ps
T1042 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.201242 Oct 15 11:39:54 AM UTC 24 Oct 15 11:39:59 AM UTC 24 638826809 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1959612165 Oct 15 11:39:56 AM UTC 24 Oct 15 11:40:00 AM UTC 24 71801314 ps
T1043 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.2352532298 Oct 15 11:39:58 AM UTC 24 Oct 15 11:40:00 AM UTC 24 22155583 ps
T1044 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1688563751 Oct 15 11:39:48 AM UTC 24 Oct 15 11:40:00 AM UTC 24 1207966423 ps
T1045 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3838729545 Oct 15 11:39:56 AM UTC 24 Oct 15 11:40:01 AM UTC 24 309973748 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4165734180 Oct 15 11:39:58 AM UTC 24 Oct 15 11:40:01 AM UTC 24 77906710 ps
T1046 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1526639877 Oct 15 11:39:59 AM UTC 24 Oct 15 11:40:01 AM UTC 24 14162872 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2753785654 Oct 15 11:39:58 AM UTC 24 Oct 15 11:40:01 AM UTC 24 97053167 ps
T1047 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.4206925783 Oct 15 11:39:58 AM UTC 24 Oct 15 11:40:01 AM UTC 24 203877638 ps
T1048 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.669342433 Oct 15 11:39:58 AM UTC 24 Oct 15 11:40:01 AM UTC 24 98140360 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.2911505005 Oct 15 11:39:58 AM UTC 24 Oct 15 11:40:02 AM UTC 24 303622871 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1691286425 Oct 15 11:39:59 AM UTC 24 Oct 15 11:40:02 AM UTC 24 269225885 ps
T1049 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1526543883 Oct 15 11:40:01 AM UTC 24 Oct 15 11:40:03 AM UTC 24 48627139 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1963151120 Oct 15 11:39:59 AM UTC 24 Oct 15 11:40:03 AM UTC 24 94508519 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1564297793 Oct 15 11:39:55 AM UTC 24 Oct 15 11:40:04 AM UTC 24 108162973 ps
T1050 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3453986202 Oct 15 11:40:01 AM UTC 24 Oct 15 11:40:04 AM UTC 24 39381018 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.893397377 Oct 15 11:39:59 AM UTC 24 Oct 15 11:40:04 AM UTC 24 100516043 ps
T1051 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1264208568 Oct 15 11:40:02 AM UTC 24 Oct 15 11:40:04 AM UTC 24 11938499 ps
T1052 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3936534730 Oct 15 11:39:50 AM UTC 24 Oct 15 11:40:05 AM UTC 24 1259265773 ps
T1053 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4173115378 Oct 15 11:40:01 AM UTC 24 Oct 15 11:40:05 AM UTC 24 183395889 ps
T1054 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.938934298 Oct 15 11:40:02 AM UTC 24 Oct 15 11:40:05 AM UTC 24 56977911 ps
T1055 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.594229995 Oct 15 11:40:02 AM UTC 24 Oct 15 11:40:05 AM UTC 24 590847200 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2994409329 Oct 15 11:40:02 AM UTC 24 Oct 15 11:40:06 AM UTC 24 28812046 ps
T1056 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.242355869 Oct 15 11:40:04 AM UTC 24 Oct 15 11:40:06 AM UTC 24 15981707 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3749052854 Oct 15 11:39:48 AM UTC 24 Oct 15 11:40:06 AM UTC 24 652653548 ps
T1057 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2064457602 Oct 15 11:40:03 AM UTC 24 Oct 15 11:40:06 AM UTC 24 192150786 ps
T1058 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2365372058 Oct 15 11:40:03 AM UTC 24 Oct 15 11:40:07 AM UTC 24 63278448 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.982032822 Oct 15 11:39:50 AM UTC 24 Oct 15 11:40:07 AM UTC 24 2457396326 ps
T1059 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1894174330 Oct 15 11:39:59 AM UTC 24 Oct 15 11:40:08 AM UTC 24 597935901 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.2702047316 Oct 15 11:40:01 AM UTC 24 Oct 15 11:40:08 AM UTC 24 206272010 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.4054950866 Oct 15 11:40:05 AM UTC 24 Oct 15 11:40:08 AM UTC 24 31803436 ps
T1060 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3836273086 Oct 15 11:40:06 AM UTC 24 Oct 15 11:40:08 AM UTC 24 14690784 ps
T1061 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2714337325 Oct 15 11:40:05 AM UTC 24 Oct 15 11:40:08 AM UTC 24 105861799 ps
T1062 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3189030045 Oct 15 11:40:05 AM UTC 24 Oct 15 11:40:09 AM UTC 24 283963342 ps
T1063 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1586258875 Oct 15 11:39:54 AM UTC 24 Oct 15 11:40:10 AM UTC 24 2461424064 ps
T1064 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2474593585 Oct 15 11:40:06 AM UTC 24 Oct 15 11:40:10 AM UTC 24 165499951 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4141468426 Oct 15 11:40:06 AM UTC 24 Oct 15 11:40:10 AM UTC 24 409017968 ps
T1065 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2258632783 Oct 15 11:40:05 AM UTC 24 Oct 15 11:40:11 AM UTC 24 303287423 ps
T1066 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.577247805 Oct 15 11:40:06 AM UTC 24 Oct 15 11:40:11 AM UTC 24 316336929 ps
T1067 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1863817887 Oct 15 11:40:06 AM UTC 24 Oct 15 11:40:12 AM UTC 24 470946567 ps
T1068 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2302910131 Oct 15 11:40:09 AM UTC 24 Oct 15 11:40:12 AM UTC 24 14377939 ps
T1069 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.962191408 Oct 15 11:39:49 AM UTC 24 Oct 15 11:40:12 AM UTC 24 4833658624 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3250036061 Oct 15 11:40:01 AM UTC 24 Oct 15 11:40:12 AM UTC 24 1441352796 ps
T1070 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.417508908 Oct 15 11:39:51 AM UTC 24 Oct 15 11:40:13 AM UTC 24 362719264 ps
T1071 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.1607256684 Oct 15 11:39:51 AM UTC 24 Oct 15 11:40:13 AM UTC 24 925043910 ps
T1072 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1846194268 Oct 15 11:39:48 AM UTC 24 Oct 15 11:40:13 AM UTC 24 914418902 ps
T1073 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1732861572 Oct 15 11:40:09 AM UTC 24 Oct 15 11:40:13 AM UTC 24 266882667 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1351135405 Oct 15 11:39:51 AM UTC 24 Oct 15 11:40:13 AM UTC 24 3714628344 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3517610074 Oct 15 11:39:58 AM UTC 24 Oct 15 11:40:14 AM UTC 24 3811680800 ps
T1074 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4137379932 Oct 15 11:40:09 AM UTC 24 Oct 15 11:40:14 AM UTC 24 86413343 ps
T1075 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1159195908 Oct 15 11:40:09 AM UTC 24 Oct 15 11:40:14 AM UTC 24 53892255 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3451927235 Oct 15 11:40:02 AM UTC 24 Oct 15 11:40:14 AM UTC 24 813415785 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.548923929 Oct 15 11:40:06 AM UTC 24 Oct 15 11:40:17 AM UTC 24 845607512 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.4016038601 Oct 15 11:40:05 AM UTC 24 Oct 15 11:40:17 AM UTC 24 390270843 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2855218180 Oct 15 11:40:04 AM UTC 24 Oct 15 11:40:17 AM UTC 24 627865020 ps
T1076 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.77507957 Oct 15 11:39:56 AM UTC 24 Oct 15 11:40:20 AM UTC 24 4503695323 ps
T1077 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2102240122 Oct 15 11:39:54 AM UTC 24 Oct 15 11:40:21 AM UTC 24 1801920123 ps
T1078 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2777985942 Oct 15 11:40:13 AM UTC 24 Oct 15 11:40:22 AM UTC 24 12764603 ps
T1079 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2256212701 Oct 15 11:40:13 AM UTC 24 Oct 15 11:40:22 AM UTC 24 35647723 ps
T1080 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1112129466 Oct 15 11:40:10 AM UTC 24 Oct 15 11:40:22 AM UTC 24 13872756 ps
T1081 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.1265117873 Oct 15 11:40:21 AM UTC 24 Oct 15 11:40:23 AM UTC 24 19294152 ps
T1082 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.3147903508 Oct 15 11:40:08 AM UTC 24 Oct 15 11:40:23 AM UTC 24 14469792 ps
T1083 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.197740521 Oct 15 11:40:10 AM UTC 24 Oct 15 11:40:23 AM UTC 24 462927453 ps
T1084 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4075793305 Oct 15 11:40:18 AM UTC 24 Oct 15 11:40:23 AM UTC 24 79428594 ps
T1085 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1635993592 Oct 15 11:40:08 AM UTC 24 Oct 15 11:40:23 AM UTC 24 30140162 ps
T1086 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.746753245 Oct 15 11:40:09 AM UTC 24 Oct 15 11:40:24 AM UTC 24 40655014 ps
T1087 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.288586939 Oct 15 11:40:13 AM UTC 24 Oct 15 11:40:24 AM UTC 24 61269885 ps
T1088 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.433804758 Oct 15 11:40:08 AM UTC 24 Oct 15 11:40:25 AM UTC 24 83726793 ps
T1089 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4119239386 Oct 15 11:40:10 AM UTC 24 Oct 15 11:40:25 AM UTC 24 606118126 ps
T1090 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1446019533 Oct 15 11:40:18 AM UTC 24 Oct 15 11:40:25 AM UTC 24 3306042074 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.4007898238 Oct 15 11:40:18 AM UTC 24 Oct 15 11:40:26 AM UTC 24 248299055 ps
T1091 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3863322675 Oct 15 11:39:56 AM UTC 24 Oct 15 11:40:28 AM UTC 24 4886607179 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1005141971 Oct 15 11:40:08 AM UTC 24 Oct 15 11:40:29 AM UTC 24 4920530325 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.958245157 Oct 15 11:40:12 AM UTC 24 Oct 15 11:40:31 AM UTC 24 115563817 ps
T1092 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.827032572 Oct 15 11:40:19 AM UTC 24 Oct 15 11:40:32 AM UTC 24 208702075 ps
T1093 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2732975371 Oct 15 11:40:29 AM UTC 24 Oct 15 11:40:32 AM UTC 24 14193302 ps
T1094 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.701789308 Oct 15 11:40:23 AM UTC 24 Oct 15 11:40:33 AM UTC 24 260585108 ps
T1095 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.2380034704 Oct 15 11:40:23 AM UTC 24 Oct 15 11:40:33 AM UTC 24 101377120 ps
T1096 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1013639583 Oct 15 11:40:27 AM UTC 24 Oct 15 11:40:35 AM UTC 24 214290598 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.642738897 Oct 15 11:40:09 AM UTC 24 Oct 15 11:40:36 AM UTC 24 1155605483 ps
T1097 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.573821152 Oct 15 11:40:34 AM UTC 24 Oct 15 11:40:36 AM UTC 24 17553952 ps
T1098 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3250618356 Oct 15 11:40:34 AM UTC 24 Oct 15 11:40:37 AM UTC 24 13448615 ps
T1099 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2732100285 Oct 15 11:40:22 AM UTC 24 Oct 15 11:40:38 AM UTC 24 81474755 ps
T1100 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.779040472 Oct 15 11:40:22 AM UTC 24 Oct 15 11:40:40 AM UTC 24 224268521 ps
T1101 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1583444163 Oct 15 11:40:33 AM UTC 24 Oct 15 11:40:41 AM UTC 24 23352109 ps
T1102 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3814091229 Oct 15 11:40:33 AM UTC 24 Oct 15 11:40:41 AM UTC 24 44238868 ps
T1103 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.1231814931 Oct 15 11:40:33 AM UTC 24 Oct 15 11:40:41 AM UTC 24 35724734 ps
T1104 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.3056589269 Oct 15 11:40:37 AM UTC 24 Oct 15 11:40:41 AM UTC 24 13440514 ps
T1105 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.1215172627 Oct 15 11:40:37 AM UTC 24 Oct 15 11:40:41 AM UTC 24 43343726 ps
T1106 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.190750493 Oct 15 11:40:39 AM UTC 24 Oct 15 11:40:42 AM UTC 24 103303842 ps
T1107 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1307564847 Oct 15 11:40:29 AM UTC 24 Oct 15 11:40:42 AM UTC 24 14925301 ps
T1108 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3325439349 Oct 15 11:40:38 AM UTC 24 Oct 15 11:40:43 AM UTC 24 18945648 ps
T1109 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.4193406484 Oct 15 11:40:41 AM UTC 24 Oct 15 11:40:43 AM UTC 24 14254318 ps
T1110 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2325572105 Oct 15 11:40:38 AM UTC 24 Oct 15 11:40:43 AM UTC 24 51875219 ps
T1111 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1397932828 Oct 15 11:40:42 AM UTC 24 Oct 15 11:40:47 AM UTC 24 37696946 ps
T1112 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1482339553 Oct 15 11:40:42 AM UTC 24 Oct 15 11:40:47 AM UTC 24 23432581 ps
T1113 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2787044408 Oct 15 11:40:42 AM UTC 24 Oct 15 11:40:47 AM UTC 24 22189084 ps
T1114 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.2009122089 Oct 15 11:40:42 AM UTC 24 Oct 15 11:40:47 AM UTC 24 14520955 ps
T1115 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.1383159115 Oct 15 11:40:42 AM UTC 24 Oct 15 11:40:47 AM UTC 24 22844540 ps
T1116 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.1832419653 Oct 15 11:40:42 AM UTC 24 Oct 15 11:40:47 AM UTC 24 35321437 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1397567273 Oct 15 11:40:23 AM UTC 24 Oct 15 11:40:48 AM UTC 24 1672343890 ps
T1117 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.1209479806 Oct 15 11:40:43 AM UTC 24 Oct 15 11:40:52 AM UTC 24 40942986 ps
T1118 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1182722596 Oct 15 11:40:47 AM UTC 24 Oct 15 11:40:52 AM UTC 24 13339150 ps
T1119 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.3552428740 Oct 15 11:40:47 AM UTC 24 Oct 15 11:40:52 AM UTC 24 13524375 ps
T1120 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3579067369 Oct 15 11:40:43 AM UTC 24 Oct 15 11:40:52 AM UTC 24 18985571 ps
T1121 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2779180398 Oct 15 11:40:47 AM UTC 24 Oct 15 11:40:52 AM UTC 24 42449611 ps
T1122 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3413534234 Oct 15 11:40:43 AM UTC 24 Oct 15 11:40:52 AM UTC 24 48779054 ps
T1123 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.3367519716 Oct 15 11:40:43 AM UTC 24 Oct 15 11:40:53 AM UTC 24 67876221 ps
T1124 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.785291413 Oct 15 11:40:47 AM UTC 24 Oct 15 11:40:53 AM UTC 24 240644212 ps
T1125 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3791870996 Oct 15 11:40:47 AM UTC 24 Oct 15 11:40:53 AM UTC 24 44005641 ps
T1126 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3962356632 Oct 15 11:40:36 AM UTC 24 Oct 15 11:40:55 AM UTC 24 44082555 ps
T1127 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1092190410 Oct 15 11:40:46 AM UTC 24 Oct 15 11:40:57 AM UTC 24 13674074 ps
T1128 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.421268858 Oct 15 11:40:26 AM UTC 24 Oct 15 11:40:59 AM UTC 24 651878138 ps
T1129 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2962880802 Oct 15 11:40:26 AM UTC 24 Oct 15 11:40:59 AM UTC 24 42313611 ps
T1130 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3278416162 Oct 15 11:40:16 AM UTC 24 Oct 15 11:41:00 AM UTC 24 295122868 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2892528515
Short name T9
Test name
Test status
Simulation time 452550423 ps
CPU time 4.65 seconds
Started Oct 15 12:27:51 PM UTC 24
Finished Oct 15 12:27:57 PM UTC 24
Peak memory 234668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892528515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2892528515
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.1616095665
Short name T22
Test name
Test status
Simulation time 5720303348 ps
CPU time 16.3 seconds
Started Oct 15 12:28:13 PM UTC 24
Finished Oct 15 12:28:31 PM UTC 24
Peak memory 229576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616095665 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.1616095665
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.1584479325
Short name T20
Test name
Test status
Simulation time 430159793 ps
CPU time 9.11 seconds
Started Oct 15 12:28:04 PM UTC 24
Finished Oct 15 12:28:14 PM UTC 24
Peak memory 244964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584479325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1584479325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.2451184998
Short name T36
Test name
Test status
Simulation time 67738416353 ps
CPU time 245.11 seconds
Started Oct 15 12:27:53 PM UTC 24
Finished Oct 15 12:32:01 PM UTC 24
Peak memory 275812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451184998 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.2451184998
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.531022117
Short name T50
Test name
Test status
Simulation time 22228754727 ps
CPU time 79.37 seconds
Started Oct 15 12:27:53 PM UTC 24
Finished Oct 15 12:29:14 PM UTC 24
Peak memory 263564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531022117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.531022117
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3555516657
Short name T69
Test name
Test status
Simulation time 29630176478 ps
CPU time 254.53 seconds
Started Oct 15 12:29:55 PM UTC 24
Finished Oct 15 12:34:13 PM UTC 24
Peak memory 294544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555516657 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.3555516657
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3893729261
Short name T128
Test name
Test status
Simulation time 118377457 ps
CPU time 3.79 seconds
Started Oct 15 11:39:51 AM UTC 24
Finished Oct 15 11:39:56 AM UTC 24
Peak memory 228004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3893729261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.spi_device_csr_mem_rw_with_rand_reset.3893729261
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3120411050
Short name T2
Test name
Test status
Simulation time 15966840 ps
CPU time 1.2 seconds
Started Oct 15 12:27:49 PM UTC 24
Finished Oct 15 12:27:52 PM UTC 24
Peak memory 225464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120411050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3120411050
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.2865604861
Short name T97
Test name
Test status
Simulation time 34512179905 ps
CPU time 412.98 seconds
Started Oct 15 12:30:42 PM UTC 24
Finished Oct 15 12:37:40 PM UTC 24
Peak memory 294500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865604861 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.2865604861
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.363790188
Short name T62
Test name
Test status
Simulation time 16335595995 ps
CPU time 86.59 seconds
Started Oct 15 12:28:43 PM UTC 24
Finished Oct 15 12:30:11 PM UTC 24
Peak memory 277908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363790188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.363790188
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2933425232
Short name T12
Test name
Test status
Simulation time 232600046 ps
CPU time 6.13 seconds
Started Oct 15 12:27:52 PM UTC 24
Finished Oct 15 12:28:00 PM UTC 24
Peak memory 231072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933425232 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.2933425232
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3419062740
Short name T8
Test name
Test status
Simulation time 41607171 ps
CPU time 1.47 seconds
Started Oct 15 12:27:54 PM UTC 24
Finished Oct 15 12:27:56 PM UTC 24
Peak memory 256900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419062740 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3419062740
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.2476926945
Short name T178
Test name
Test status
Simulation time 27108038832 ps
CPU time 336.08 seconds
Started Oct 15 12:27:53 PM UTC 24
Finished Oct 15 12:33:33 PM UTC 24
Peak memory 261532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476926945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.2476926945
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2524620855
Short name T185
Test name
Test status
Simulation time 4637751805 ps
CPU time 82.06 seconds
Started Oct 15 12:36:17 PM UTC 24
Finished Oct 15 12:37:41 PM UTC 24
Peak memory 261468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524620855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.2524620855
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2531092830
Short name T48
Test name
Test status
Simulation time 27576986590 ps
CPU time 88.83 seconds
Started Oct 15 12:30:41 PM UTC 24
Finished Oct 15 12:32:12 PM UTC 24
Peak memory 277860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531092830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2531092830
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2907569564
Short name T219
Test name
Test status
Simulation time 22379980306 ps
CPU time 196.27 seconds
Started Oct 15 12:34:09 PM UTC 24
Finished Oct 15 12:37:29 PM UTC 24
Peak memory 278156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907569564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2907569564
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1031707287
Short name T180
Test name
Test status
Simulation time 11185519287 ps
CPU time 150.94 seconds
Started Oct 15 12:34:00 PM UTC 24
Finished Oct 15 12:36:34 PM UTC 24
Peak memory 284004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031707287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.1031707287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3977282607
Short name T26
Test name
Test status
Simulation time 3061027114 ps
CPU time 14.97 seconds
Started Oct 15 12:27:49 PM UTC 24
Finished Oct 15 12:28:06 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977282607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3977282607
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3517610074
Short name T281
Test name
Test status
Simulation time 3811680800 ps
CPU time 14.73 seconds
Started Oct 15 11:39:58 AM UTC 24
Finished Oct 15 11:40:14 AM UTC 24
Peak memory 225732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517610074 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.3517610074
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2133681630
Short name T262
Test name
Test status
Simulation time 27455314035 ps
CPU time 387.24 seconds
Started Oct 15 12:37:57 PM UTC 24
Finished Oct 15 12:44:30 PM UTC 24
Peak memory 298660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133681630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2133681630
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.2883328969
Short name T74
Test name
Test status
Simulation time 105724499573 ps
CPU time 533.19 seconds
Started Oct 15 12:36:27 PM UTC 24
Finished Oct 15 12:45:27 PM UTC 24
Peak memory 267988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883328969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.2883328969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3058219855
Short name T98
Test name
Test status
Simulation time 80461986 ps
CPU time 1.46 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:39:50 AM UTC 24
Peak memory 214460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058219855 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.3058219855
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2224058325
Short name T123
Test name
Test status
Simulation time 235938327 ps
CPU time 3.57 seconds
Started Oct 15 11:39:54 AM UTC 24
Finished Oct 15 11:39:58 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224058325 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2224058325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.852986230
Short name T200
Test name
Test status
Simulation time 8847850084 ps
CPU time 125.12 seconds
Started Oct 15 12:34:29 PM UTC 24
Finished Oct 15 12:36:37 PM UTC 24
Peak memory 265636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852986230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.852986230
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3306058777
Short name T317
Test name
Test status
Simulation time 104947187963 ps
CPU time 220.21 seconds
Started Oct 15 12:31:19 PM UTC 24
Finished Oct 15 12:35:02 PM UTC 24
Peak memory 261520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306058777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.3306058777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.1785978364
Short name T4
Test name
Test status
Simulation time 27704554 ps
CPU time 1.74 seconds
Started Oct 15 12:27:49 PM UTC 24
Finished Oct 15 12:27:52 PM UTC 24
Peak memory 228940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785978364 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_parity.1785978364
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3995370254
Short name T95
Test name
Test status
Simulation time 17496567313 ps
CPU time 208.82 seconds
Started Oct 15 12:29:54 PM UTC 24
Finished Oct 15 12:33:26 PM UTC 24
Peak memory 263584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995370254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3995370254
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.3972265633
Short name T256
Test name
Test status
Simulation time 361475242123 ps
CPU time 437.2 seconds
Started Oct 15 12:38:29 PM UTC 24
Finished Oct 15 12:45:52 PM UTC 24
Peak memory 294248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972265633 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.3972265633
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.199081456
Short name T208
Test name
Test status
Simulation time 414138245177 ps
CPU time 535.55 seconds
Started Oct 15 12:29:13 PM UTC 24
Finished Oct 15 12:38:15 PM UTC 24
Peak memory 261532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199081456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.199081456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.3326116361
Short name T267
Test name
Test status
Simulation time 286875631692 ps
CPU time 696.38 seconds
Started Oct 15 12:32:12 PM UTC 24
Finished Oct 15 12:43:57 PM UTC 24
Peak memory 294440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326116361 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.3326116361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.2524176009
Short name T40
Test name
Test status
Simulation time 711849609 ps
CPU time 8.86 seconds
Started Oct 15 12:28:06 PM UTC 24
Finished Oct 15 12:28:16 PM UTC 24
Peak memory 234728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524176009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2524176009
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3147516282
Short name T32
Test name
Test status
Simulation time 2779660869 ps
CPU time 37.12 seconds
Started Oct 15 12:27:58 PM UTC 24
Finished Oct 15 12:28:37 PM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147516282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3147516282
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.3758184588
Short name T230
Test name
Test status
Simulation time 221888148161 ps
CPU time 342.03 seconds
Started Oct 15 12:34:38 PM UTC 24
Finished Oct 15 12:40:25 PM UTC 24
Peak memory 265832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758184588 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.3758184588
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1732197307
Short name T96
Test name
Test status
Simulation time 17723834126 ps
CPU time 126.95 seconds
Started Oct 15 12:31:17 PM UTC 24
Finished Oct 15 12:33:27 PM UTC 24
Peak memory 267656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732197307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1732197307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3954347743
Short name T7
Test name
Test status
Simulation time 42792854 ps
CPU time 1.14 seconds
Started Oct 15 12:27:54 PM UTC 24
Finished Oct 15 12:27:56 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954347743 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3954347743
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.2903688736
Short name T121
Test name
Test status
Simulation time 8520225095 ps
CPU time 112.28 seconds
Started Oct 15 12:27:51 PM UTC 24
Finished Oct 15 12:29:46 PM UTC 24
Peak memory 234840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903688736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2903688736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3349804265
Short name T271
Test name
Test status
Simulation time 49201682912 ps
CPU time 366.96 seconds
Started Oct 15 12:48:00 PM UTC 24
Finished Oct 15 12:54:12 PM UTC 24
Peak memory 267620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349804265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.3349804265
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.4167946192
Short name T198
Test name
Test status
Simulation time 1422753229 ps
CPU time 50.74 seconds
Started Oct 15 12:33:38 PM UTC 24
Finished Oct 15 12:34:30 PM UTC 24
Peak memory 261396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167946192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.4167946192
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3763932006
Short name T120
Test name
Test status
Simulation time 214287050 ps
CPU time 5.16 seconds
Started Oct 15 11:39:50 AM UTC 24
Finished Oct 15 11:39:56 AM UTC 24
Peak memory 226184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763932006 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3763932006
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1397567273
Short name T283
Test name
Test status
Simulation time 1672343890 ps
CPU time 16.91 seconds
Started Oct 15 11:40:23 AM UTC 24
Finished Oct 15 11:40:48 AM UTC 24
Peak memory 228208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397567273 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.1397567273
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.2840688870
Short name T280
Test name
Test status
Simulation time 49036360224 ps
CPU time 409.65 seconds
Started Oct 15 12:35:44 PM UTC 24
Finished Oct 15 12:42:39 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840688870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2840688870
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.1405632123
Short name T42
Test name
Test status
Simulation time 149929959896 ps
CPU time 673.18 seconds
Started Oct 15 12:35:53 PM UTC 24
Finished Oct 15 12:47:14 PM UTC 24
Peak memory 284008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405632123 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.1405632123
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3749052854
Short name T119
Test name
Test status
Simulation time 652653548 ps
CPU time 16.81 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:40:06 AM UTC 24
Peak memory 229992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749052854 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.3749052854
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.2302922800
Short name T45
Test name
Test status
Simulation time 7521846541 ps
CPU time 51.67 seconds
Started Oct 15 12:27:49 PM UTC 24
Finished Oct 15 12:28:43 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302922800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2302922800
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1786038184
Short name T63
Test name
Test status
Simulation time 9005586645 ps
CPU time 120.52 seconds
Started Oct 15 12:28:10 PM UTC 24
Finished Oct 15 12:30:13 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786038184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.1786038184
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.2166949181
Short name T303
Test name
Test status
Simulation time 189093943298 ps
CPU time 446.94 seconds
Started Oct 15 12:37:34 PM UTC 24
Finished Oct 15 12:45:06 PM UTC 24
Peak memory 277800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166949181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2166949181
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.3779734783
Short name T167
Test name
Test status
Simulation time 19515310726 ps
CPU time 258.86 seconds
Started Oct 15 12:37:58 PM UTC 24
Finished Oct 15 12:42:21 PM UTC 24
Peak memory 267684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779734783 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.3779734783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.102364317
Short name T43
Test name
Test status
Simulation time 154706904221 ps
CPU time 624.68 seconds
Started Oct 15 12:40:22 PM UTC 24
Finished Oct 15 12:50:55 PM UTC 24
Peak memory 267940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102364317 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.102364317
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.1580635994
Short name T348
Test name
Test status
Simulation time 104831788 ps
CPU time 7.29 seconds
Started Oct 15 12:41:12 PM UTC 24
Finished Oct 15 12:41:20 PM UTC 24
Peak memory 244952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580635994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1580635994
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1388647856
Short name T296
Test name
Test status
Simulation time 13956488299 ps
CPU time 119.98 seconds
Started Oct 15 12:43:20 PM UTC 24
Finished Oct 15 12:45:22 PM UTC 24
Peak memory 263568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388647856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1388647856
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.2209692402
Short name T194
Test name
Test status
Simulation time 163573936 ps
CPU time 3.03 seconds
Started Oct 15 12:30:25 PM UTC 24
Finished Oct 15 12:30:29 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209692402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2209692402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2474593585
Short name T1064
Test name
Test status
Simulation time 165499951 ps
CPU time 2.73 seconds
Started Oct 15 11:40:06 AM UTC 24
Finished Oct 15 11:40:10 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474593585 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.2474593585
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2368417356
Short name T310
Test name
Test status
Simulation time 426350829586 ps
CPU time 223.36 seconds
Started Oct 15 12:36:23 PM UTC 24
Finished Oct 15 12:40:09 PM UTC 24
Peak memory 263760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368417356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2368417356
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.4024235423
Short name T274
Test name
Test status
Simulation time 389214178464 ps
CPU time 415.6 seconds
Started Oct 15 12:36:29 PM UTC 24
Finished Oct 15 12:43:29 PM UTC 24
Peak memory 263528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024235423 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.4024235423
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.3822117043
Short name T349
Test name
Test status
Simulation time 1916674165 ps
CPU time 24.57 seconds
Started Oct 15 12:37:29 PM UTC 24
Finished Oct 15 12:37:55 PM UTC 24
Peak memory 244896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822117043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3822117043
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.233738818
Short name T213
Test name
Test status
Simulation time 4548664725 ps
CPU time 112.49 seconds
Started Oct 15 12:38:26 PM UTC 24
Finished Oct 15 12:40:21 PM UTC 24
Peak memory 279884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233738818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.233738818
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.2333449718
Short name T259
Test name
Test status
Simulation time 88250969631 ps
CPU time 701.64 seconds
Started Oct 15 12:39:58 PM UTC 24
Finished Oct 15 12:51:48 PM UTC 24
Peak memory 294248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333449718 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.2333449718
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.1624028750
Short name T342
Test name
Test status
Simulation time 18673699476 ps
CPU time 85.53 seconds
Started Oct 15 12:40:38 PM UTC 24
Finished Oct 15 12:42:06 PM UTC 24
Peak memory 267616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624028750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1624028750
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2549832494
Short name T100
Test name
Test status
Simulation time 33050133 ps
CPU time 1.08 seconds
Started Oct 15 11:39:51 AM UTC 24
Finished Oct 15 11:39:53 AM UTC 24
Peak memory 214972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549832494 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.2549832494
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1846194268
Short name T1072
Test name
Test status
Simulation time 914418902 ps
CPU time 23.72 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:40:13 AM UTC 24
Peak memory 225372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846194268 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.1846194268
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1688563751
Short name T1044
Test name
Test status
Simulation time 1207966423 ps
CPU time 10.99 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:40:00 AM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688563751 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.1688563751
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3520234634
Short name T124
Test name
Test status
Simulation time 321711554 ps
CPU time 4.42 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:39:53 AM UTC 24
Peak memory 230088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3520234634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.spi_device_csr_mem_rw_with_rand_reset.3520234634
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.347705132
Short name T160
Test name
Test status
Simulation time 36110193 ps
CPU time 1.31 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:39:50 AM UTC 24
Peak memory 226204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347705132 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.347705132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3777957311
Short name T1031
Test name
Test status
Simulation time 49261999 ps
CPU time 0.91 seconds
Started Oct 15 11:39:46 AM UTC 24
Finished Oct 15 11:39:48 AM UTC 24
Peak memory 213536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777957311 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3777957311
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3284579333
Short name T133
Test name
Test status
Simulation time 38812377 ps
CPU time 1.61 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:39:50 AM UTC 24
Peak memory 224684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284579333 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.3284579333
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1985087332
Short name T1032
Test name
Test status
Simulation time 38755164 ps
CPU time 0.81 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:39:49 AM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985087332 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.1985087332
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1996249132
Short name T153
Test name
Test status
Simulation time 254454719 ps
CPU time 3.78 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:39:53 AM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996249132 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.1996249132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.712477283
Short name T114
Test name
Test status
Simulation time 65523004 ps
CPU time 2.07 seconds
Started Oct 15 11:39:46 AM UTC 24
Finished Oct 15 11:39:49 AM UTC 24
Peak memory 227988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712477283 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.712477283
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.42434481
Short name T117
Test name
Test status
Simulation time 613427436 ps
CPU time 7.93 seconds
Started Oct 15 11:39:46 AM UTC 24
Finished Oct 15 11:39:55 AM UTC 24
Peak memory 227940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42434481 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.42434481
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3936534730
Short name T1052
Test name
Test status
Simulation time 1259265773 ps
CPU time 14.19 seconds
Started Oct 15 11:39:50 AM UTC 24
Finished Oct 15 11:40:05 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936534730 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.3936534730
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.962191408
Short name T1069
Test name
Test status
Simulation time 4833658624 ps
CPU time 21.67 seconds
Started Oct 15 11:39:49 AM UTC 24
Finished Oct 15 11:40:12 AM UTC 24
Peak memory 215592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962191408 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.962191408
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4271503436
Short name T99
Test name
Test status
Simulation time 37174511 ps
CPU time 1.62 seconds
Started Oct 15 11:39:49 AM UTC 24
Finished Oct 15 11:39:52 AM UTC 24
Peak memory 214460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271503436 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.4271503436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4057337090
Short name T131
Test name
Test status
Simulation time 154657440 ps
CPU time 3.91 seconds
Started Oct 15 11:39:50 AM UTC 24
Finished Oct 15 11:39:54 AM UTC 24
Peak memory 228164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4057337090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.spi_device_csr_mem_rw_with_rand_reset.4057337090
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3972113723
Short name T136
Test name
Test status
Simulation time 700562279 ps
CPU time 2.3 seconds
Started Oct 15 11:39:49 AM UTC 24
Finished Oct 15 11:39:53 AM UTC 24
Peak memory 225804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972113723 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3972113723
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3793660244
Short name T1033
Test name
Test status
Simulation time 41778481 ps
CPU time 0.79 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:39:50 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793660244 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3793660244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4072377958
Short name T134
Test name
Test status
Simulation time 61204503 ps
CPU time 1.63 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:39:51 AM UTC 24
Peak memory 224680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072377958 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.4072377958
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3758480169
Short name T1034
Test name
Test status
Simulation time 15648805 ps
CPU time 0.92 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:39:50 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758480169 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.3758480169
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2432391788
Short name T154
Test name
Test status
Simulation time 49531048 ps
CPU time 2.83 seconds
Started Oct 15 11:39:50 AM UTC 24
Finished Oct 15 11:39:53 AM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432391788 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.2432391788
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2852215689
Short name T116
Test name
Test status
Simulation time 207042648 ps
CPU time 3.59 seconds
Started Oct 15 11:39:48 AM UTC 24
Finished Oct 15 11:39:53 AM UTC 24
Peak memory 225992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852215689 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2852215689
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1863817887
Short name T1067
Test name
Test status
Simulation time 470946567 ps
CPU time 1.69 seconds
Started Oct 15 11:40:06 AM UTC 24
Finished Oct 15 11:40:12 AM UTC 24
Peak memory 226784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1863817887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.spi_device_csr_mem_rw_with_rand_reset.1863817887
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4141468426
Short name T142
Test name
Test status
Simulation time 409017968 ps
CPU time 3.24 seconds
Started Oct 15 11:40:06 AM UTC 24
Finished Oct 15 11:40:10 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141468426 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.4141468426
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3836273086
Short name T1060
Test name
Test status
Simulation time 14690784 ps
CPU time 1.13 seconds
Started Oct 15 11:40:06 AM UTC 24
Finished Oct 15 11:40:08 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836273086 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.3836273086
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.577247805
Short name T1066
Test name
Test status
Simulation time 316336929 ps
CPU time 3.69 seconds
Started Oct 15 11:40:06 AM UTC 24
Finished Oct 15 11:40:11 AM UTC 24
Peak memory 226020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577247805 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.577247805
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2258632783
Short name T1065
Test name
Test status
Simulation time 303287423 ps
CPU time 4.84 seconds
Started Oct 15 11:40:05 AM UTC 24
Finished Oct 15 11:40:11 AM UTC 24
Peak memory 225952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258632783 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.2258632783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.4016038601
Short name T288
Test name
Test status
Simulation time 390270843 ps
CPU time 11.2 seconds
Started Oct 15 11:40:05 AM UTC 24
Finished Oct 15 11:40:17 AM UTC 24
Peak memory 226096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016038601 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.4016038601
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.433804758
Short name T1088
Test name
Test status
Simulation time 83726793 ps
CPU time 2.47 seconds
Started Oct 15 11:40:08 AM UTC 24
Finished Oct 15 11:40:25 AM UTC 24
Peak memory 227932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=433804758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.spi_device_csr_mem_rw_with_rand_reset.433804758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1635993592
Short name T1085
Test name
Test status
Simulation time 30140162 ps
CPU time 1.66 seconds
Started Oct 15 11:40:08 AM UTC 24
Finished Oct 15 11:40:23 AM UTC 24
Peak memory 224696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635993592 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.1635993592
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.3147903508
Short name T1082
Test name
Test status
Simulation time 14469792 ps
CPU time 1.14 seconds
Started Oct 15 11:40:08 AM UTC 24
Finished Oct 15 11:40:23 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147903508 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.3147903508
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.548923929
Short name T291
Test name
Test status
Simulation time 845607512 ps
CPU time 6.77 seconds
Started Oct 15 11:40:06 AM UTC 24
Finished Oct 15 11:40:17 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548923929 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.548923929
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.746753245
Short name T1086
Test name
Test status
Simulation time 40655014 ps
CPU time 2.43 seconds
Started Oct 15 11:40:09 AM UTC 24
Finished Oct 15 11:40:24 AM UTC 24
Peak memory 228072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=746753245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.spi_device_csr_mem_rw_with_rand_reset.746753245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4137379932
Short name T1074
Test name
Test status
Simulation time 86413343 ps
CPU time 2.67 seconds
Started Oct 15 11:40:09 AM UTC 24
Finished Oct 15 11:40:14 AM UTC 24
Peak memory 226136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137379932 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.4137379932
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2302910131
Short name T1068
Test name
Test status
Simulation time 14377939 ps
CPU time 0.82 seconds
Started Oct 15 11:40:09 AM UTC 24
Finished Oct 15 11:40:12 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302910131 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.2302910131
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1159195908
Short name T1075
Test name
Test status
Simulation time 53892255 ps
CPU time 2.64 seconds
Started Oct 15 11:40:09 AM UTC 24
Finished Oct 15 11:40:14 AM UTC 24
Peak memory 225852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159195908 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.1159195908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1005141971
Short name T289
Test name
Test status
Simulation time 4920530325 ps
CPU time 6.52 seconds
Started Oct 15 11:40:08 AM UTC 24
Finished Oct 15 11:40:29 AM UTC 24
Peak memory 225908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005141971 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.1005141971
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.197740521
Short name T1083
Test name
Test status
Simulation time 462927453 ps
CPU time 1.23 seconds
Started Oct 15 11:40:10 AM UTC 24
Finished Oct 15 11:40:23 AM UTC 24
Peak memory 214400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197740521 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.197740521
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1112129466
Short name T1080
Test name
Test status
Simulation time 13872756 ps
CPU time 0.9 seconds
Started Oct 15 11:40:10 AM UTC 24
Finished Oct 15 11:40:22 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112129466 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.1112129466
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4119239386
Short name T1089
Test name
Test status
Simulation time 606118126 ps
CPU time 3.35 seconds
Started Oct 15 11:40:10 AM UTC 24
Finished Oct 15 11:40:25 AM UTC 24
Peak memory 225788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119239386 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.4119239386
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1732861572
Short name T1073
Test name
Test status
Simulation time 266882667 ps
CPU time 1.93 seconds
Started Oct 15 11:40:09 AM UTC 24
Finished Oct 15 11:40:13 AM UTC 24
Peak memory 224740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732861572 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.1732861572
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.642738897
Short name T282
Test name
Test status
Simulation time 1155605483 ps
CPU time 14.22 seconds
Started Oct 15 11:40:09 AM UTC 24
Finished Oct 15 11:40:36 AM UTC 24
Peak memory 227928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642738897 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.642738897
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2256212701
Short name T1079
Test name
Test status
Simulation time 35647723 ps
CPU time 1.22 seconds
Started Oct 15 11:40:13 AM UTC 24
Finished Oct 15 11:40:22 AM UTC 24
Peak memory 214444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256212701 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.2256212701
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2777985942
Short name T1078
Test name
Test status
Simulation time 12764603 ps
CPU time 0.65 seconds
Started Oct 15 11:40:13 AM UTC 24
Finished Oct 15 11:40:22 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777985942 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.2777985942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.288586939
Short name T1087
Test name
Test status
Simulation time 61269885 ps
CPU time 3.46 seconds
Started Oct 15 11:40:13 AM UTC 24
Finished Oct 15 11:40:24 AM UTC 24
Peak memory 225808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288586939 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.288586939
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.958245157
Short name T292
Test name
Test status
Simulation time 115563817 ps
CPU time 5.56 seconds
Started Oct 15 11:40:12 AM UTC 24
Finished Oct 15 11:40:31 AM UTC 24
Peak memory 227924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958245157 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.958245157
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1446019533
Short name T1090
Test name
Test status
Simulation time 3306042074 ps
CPU time 3.41 seconds
Started Oct 15 11:40:18 AM UTC 24
Finished Oct 15 11:40:25 AM UTC 24
Peak memory 228192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1446019533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.spi_device_csr_mem_rw_with_rand_reset.1446019533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3278416162
Short name T1130
Test name
Test status
Simulation time 295122868 ps
CPU time 2.14 seconds
Started Oct 15 11:40:16 AM UTC 24
Finished Oct 15 11:41:00 AM UTC 24
Peak memory 226064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278416162 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.3278416162
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4075793305
Short name T1084
Test name
Test status
Simulation time 79428594 ps
CPU time 1.46 seconds
Started Oct 15 11:40:18 AM UTC 24
Finished Oct 15 11:40:23 AM UTC 24
Peak memory 225436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075793305 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.4075793305
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.701789308
Short name T1094
Test name
Test status
Simulation time 260585108 ps
CPU time 1.51 seconds
Started Oct 15 11:40:23 AM UTC 24
Finished Oct 15 11:40:33 AM UTC 24
Peak memory 224732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=701789308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.spi_device_csr_mem_rw_with_rand_reset.701789308
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2732100285
Short name T1099
Test name
Test status
Simulation time 81474755 ps
CPU time 1.79 seconds
Started Oct 15 11:40:22 AM UTC 24
Finished Oct 15 11:40:38 AM UTC 24
Peak memory 214400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732100285 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.2732100285
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.1265117873
Short name T1081
Test name
Test status
Simulation time 19294152 ps
CPU time 0.67 seconds
Started Oct 15 11:40:21 AM UTC 24
Finished Oct 15 11:40:23 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265117873 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.1265117873
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.779040472
Short name T1100
Test name
Test status
Simulation time 224268521 ps
CPU time 3.76 seconds
Started Oct 15 11:40:22 AM UTC 24
Finished Oct 15 11:40:40 AM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779040472 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.779040472
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.4007898238
Short name T130
Test name
Test status
Simulation time 248299055 ps
CPU time 4.2 seconds
Started Oct 15 11:40:18 AM UTC 24
Finished Oct 15 11:40:26 AM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007898238 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.4007898238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.827032572
Short name T1092
Test name
Test status
Simulation time 208702075 ps
CPU time 11.04 seconds
Started Oct 15 11:40:19 AM UTC 24
Finished Oct 15 11:40:32 AM UTC 24
Peak memory 226124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827032572 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.827032572
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.2380034704
Short name T1095
Test name
Test status
Simulation time 101377120 ps
CPU time 1.54 seconds
Started Oct 15 11:40:23 AM UTC 24
Finished Oct 15 11:40:33 AM UTC 24
Peak memory 224952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380034704 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.2380034704
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1013639583
Short name T1096
Test name
Test status
Simulation time 214290598 ps
CPU time 3.16 seconds
Started Oct 15 11:40:27 AM UTC 24
Finished Oct 15 11:40:35 AM UTC 24
Peak memory 227940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1013639583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.spi_device_csr_mem_rw_with_rand_reset.1013639583
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.421268858
Short name T1128
Test name
Test status
Simulation time 651878138 ps
CPU time 3.14 seconds
Started Oct 15 11:40:26 AM UTC 24
Finished Oct 15 11:40:59 AM UTC 24
Peak memory 215432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421268858 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.421268858
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2962880802
Short name T1129
Test name
Test status
Simulation time 42313611 ps
CPU time 3.15 seconds
Started Oct 15 11:40:26 AM UTC 24
Finished Oct 15 11:40:59 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962880802 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.2962880802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.1607256684
Short name T1071
Test name
Test status
Simulation time 925043910 ps
CPU time 20.35 seconds
Started Oct 15 11:39:51 AM UTC 24
Finished Oct 15 11:40:13 AM UTC 24
Peak memory 225948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607256684 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.1607256684
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.417508908
Short name T1070
Test name
Test status
Simulation time 362719264 ps
CPU time 20.29 seconds
Started Oct 15 11:39:51 AM UTC 24
Finished Oct 15 11:40:13 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417508908 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.417508908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1404690062
Short name T137
Test name
Test status
Simulation time 161741100 ps
CPU time 1.74 seconds
Started Oct 15 11:39:51 AM UTC 24
Finished Oct 15 11:39:54 AM UTC 24
Peak memory 214400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404690062 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1404690062
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2294189486
Short name T1035
Test name
Test status
Simulation time 28964863 ps
CPU time 0.99 seconds
Started Oct 15 11:39:50 AM UTC 24
Finished Oct 15 11:39:52 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294189486 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2294189486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1569705872
Short name T135
Test name
Test status
Simulation time 29444421 ps
CPU time 1.78 seconds
Started Oct 15 11:39:50 AM UTC 24
Finished Oct 15 11:39:53 AM UTC 24
Peak memory 224680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569705872 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.1569705872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.803643285
Short name T1036
Test name
Test status
Simulation time 35049555 ps
CPU time 1.01 seconds
Started Oct 15 11:39:50 AM UTC 24
Finished Oct 15 11:39:52 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803643285 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.803643285
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.394539219
Short name T155
Test name
Test status
Simulation time 111600972 ps
CPU time 3.84 seconds
Started Oct 15 11:39:51 AM UTC 24
Finished Oct 15 11:39:56 AM UTC 24
Peak memory 225796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394539219 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.394539219
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.982032822
Short name T284
Test name
Test status
Simulation time 2457396326 ps
CPU time 16.31 seconds
Started Oct 15 11:39:50 AM UTC 24
Finished Oct 15 11:40:07 AM UTC 24
Peak memory 228000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982032822 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.982032822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2732975371
Short name T1093
Test name
Test status
Simulation time 14193302 ps
CPU time 0.63 seconds
Started Oct 15 11:40:29 AM UTC 24
Finished Oct 15 11:40:32 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732975371 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.2732975371
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1307564847
Short name T1107
Test name
Test status
Simulation time 14925301 ps
CPU time 0.62 seconds
Started Oct 15 11:40:29 AM UTC 24
Finished Oct 15 11:40:42 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307564847 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.1307564847
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3814091229
Short name T1102
Test name
Test status
Simulation time 44238868 ps
CPU time 0.64 seconds
Started Oct 15 11:40:33 AM UTC 24
Finished Oct 15 11:40:41 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814091229 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.3814091229
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1583444163
Short name T1101
Test name
Test status
Simulation time 23352109 ps
CPU time 0.61 seconds
Started Oct 15 11:40:33 AM UTC 24
Finished Oct 15 11:40:41 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583444163 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.1583444163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.1231814931
Short name T1103
Test name
Test status
Simulation time 35724734 ps
CPU time 0.63 seconds
Started Oct 15 11:40:33 AM UTC 24
Finished Oct 15 11:40:41 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231814931 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.1231814931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.573821152
Short name T1097
Test name
Test status
Simulation time 17553952 ps
CPU time 0.6 seconds
Started Oct 15 11:40:34 AM UTC 24
Finished Oct 15 11:40:36 AM UTC 24
Peak memory 212484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573821152 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.573821152
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3250618356
Short name T1098
Test name
Test status
Simulation time 13448615 ps
CPU time 0.62 seconds
Started Oct 15 11:40:34 AM UTC 24
Finished Oct 15 11:40:37 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250618356 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.3250618356
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3962356632
Short name T1126
Test name
Test status
Simulation time 44082555 ps
CPU time 0.69 seconds
Started Oct 15 11:40:36 AM UTC 24
Finished Oct 15 11:40:55 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962356632 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.3962356632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.1215172627
Short name T1105
Test name
Test status
Simulation time 43343726 ps
CPU time 0.64 seconds
Started Oct 15 11:40:37 AM UTC 24
Finished Oct 15 11:40:41 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215172627 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.1215172627
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.3056589269
Short name T1104
Test name
Test status
Simulation time 13440514 ps
CPU time 0.61 seconds
Started Oct 15 11:40:37 AM UTC 24
Finished Oct 15 11:40:41 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056589269 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.3056589269
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1586258875
Short name T1063
Test name
Test status
Simulation time 2461424064 ps
CPU time 15.01 seconds
Started Oct 15 11:39:54 AM UTC 24
Finished Oct 15 11:40:10 AM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586258875 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.1586258875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2102240122
Short name T1077
Test name
Test status
Simulation time 1801920123 ps
CPU time 26.29 seconds
Started Oct 15 11:39:54 AM UTC 24
Finished Oct 15 11:40:21 AM UTC 24
Peak memory 217696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102240122 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.2102240122
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3770952940
Short name T101
Test name
Test status
Simulation time 24118422 ps
CPU time 1.97 seconds
Started Oct 15 11:39:54 AM UTC 24
Finished Oct 15 11:39:57 AM UTC 24
Peak memory 227264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770952940 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.3770952940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.192052669
Short name T132
Test name
Test status
Simulation time 25201646 ps
CPU time 1.64 seconds
Started Oct 15 11:39:54 AM UTC 24
Finished Oct 15 11:39:56 AM UTC 24
Peak memory 226808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=192052669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.spi_device_csr_mem_rw_with_rand_reset.192052669
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2873160190
Short name T139
Test name
Test status
Simulation time 69105939 ps
CPU time 2.4 seconds
Started Oct 15 11:39:54 AM UTC 24
Finished Oct 15 11:39:57 AM UTC 24
Peak memory 225808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873160190 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2873160190
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.3835948422
Short name T1038
Test name
Test status
Simulation time 37515716 ps
CPU time 1.1 seconds
Started Oct 15 11:39:52 AM UTC 24
Finished Oct 15 11:39:54 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835948422 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3835948422
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.3415860430
Short name T138
Test name
Test status
Simulation time 132182338 ps
CPU time 2.37 seconds
Started Oct 15 11:39:52 AM UTC 24
Finished Oct 15 11:39:56 AM UTC 24
Peak memory 226124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415860430 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.3415860430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.3541484208
Short name T1037
Test name
Test status
Simulation time 23946626 ps
CPU time 0.99 seconds
Started Oct 15 11:39:52 AM UTC 24
Finished Oct 15 11:39:54 AM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541484208 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.3541484208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.201242
Short name T1042
Test name
Test status
Simulation time 638826809 ps
CPU time 4.35 seconds
Started Oct 15 11:39:54 AM UTC 24
Finished Oct 15 11:39:59 AM UTC 24
Peak memory 225980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201242 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.201242
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2795220652
Short name T125
Test name
Test status
Simulation time 344112059 ps
CPU time 4.44 seconds
Started Oct 15 11:39:51 AM UTC 24
Finished Oct 15 11:39:57 AM UTC 24
Peak memory 225956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795220652 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2795220652
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1351135405
Short name T285
Test name
Test status
Simulation time 3714628344 ps
CPU time 20.82 seconds
Started Oct 15 11:39:51 AM UTC 24
Finished Oct 15 11:40:13 AM UTC 24
Peak memory 232148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351135405 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.1351135405
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2325572105
Short name T1110
Test name
Test status
Simulation time 51875219 ps
CPU time 0.66 seconds
Started Oct 15 11:40:38 AM UTC 24
Finished Oct 15 11:40:43 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325572105 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.2325572105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3325439349
Short name T1108
Test name
Test status
Simulation time 18945648 ps
CPU time 0.69 seconds
Started Oct 15 11:40:38 AM UTC 24
Finished Oct 15 11:40:43 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325439349 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.3325439349
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.190750493
Short name T1106
Test name
Test status
Simulation time 103303842 ps
CPU time 0.59 seconds
Started Oct 15 11:40:39 AM UTC 24
Finished Oct 15 11:40:42 AM UTC 24
Peak memory 212500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190750493 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.190750493
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.4193406484
Short name T1109
Test name
Test status
Simulation time 14254318 ps
CPU time 0.64 seconds
Started Oct 15 11:40:41 AM UTC 24
Finished Oct 15 11:40:43 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193406484 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.4193406484
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2787044408
Short name T1113
Test name
Test status
Simulation time 22189084 ps
CPU time 0.7 seconds
Started Oct 15 11:40:42 AM UTC 24
Finished Oct 15 11:40:47 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787044408 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.2787044408
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.1383159115
Short name T1115
Test name
Test status
Simulation time 22844540 ps
CPU time 0.79 seconds
Started Oct 15 11:40:42 AM UTC 24
Finished Oct 15 11:40:47 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383159115 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.1383159115
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1482339553
Short name T1112
Test name
Test status
Simulation time 23432581 ps
CPU time 0.65 seconds
Started Oct 15 11:40:42 AM UTC 24
Finished Oct 15 11:40:47 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482339553 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.1482339553
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.2009122089
Short name T1114
Test name
Test status
Simulation time 14520955 ps
CPU time 0.74 seconds
Started Oct 15 11:40:42 AM UTC 24
Finished Oct 15 11:40:47 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009122089 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.2009122089
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1397932828
Short name T1111
Test name
Test status
Simulation time 37696946 ps
CPU time 0.64 seconds
Started Oct 15 11:40:42 AM UTC 24
Finished Oct 15 11:40:47 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397932828 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.1397932828
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.1832419653
Short name T1116
Test name
Test status
Simulation time 35321437 ps
CPU time 0.64 seconds
Started Oct 15 11:40:42 AM UTC 24
Finished Oct 15 11:40:47 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832419653 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.1832419653
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.77507957
Short name T1076
Test name
Test status
Simulation time 4503695323 ps
CPU time 22.59 seconds
Started Oct 15 11:39:56 AM UTC 24
Finished Oct 15 11:40:20 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77507957 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.77507957
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3863322675
Short name T1091
Test name
Test status
Simulation time 4886607179 ps
CPU time 30.6 seconds
Started Oct 15 11:39:56 AM UTC 24
Finished Oct 15 11:40:28 AM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863322675 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.3863322675
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3312211716
Short name T102
Test name
Test status
Simulation time 280907107 ps
CPU time 1.77 seconds
Started Oct 15 11:39:55 AM UTC 24
Finished Oct 15 11:39:58 AM UTC 24
Peak memory 214928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312211716 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.3312211716
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3838729545
Short name T1045
Test name
Test status
Simulation time 309973748 ps
CPU time 3.02 seconds
Started Oct 15 11:39:56 AM UTC 24
Finished Oct 15 11:40:01 AM UTC 24
Peak memory 228132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3838729545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.spi_device_csr_mem_rw_with_rand_reset.3838729545
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1675658917
Short name T1041
Test name
Test status
Simulation time 20187107 ps
CPU time 1.27 seconds
Started Oct 15 11:39:55 AM UTC 24
Finished Oct 15 11:39:58 AM UTC 24
Peak memory 214400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675658917 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1675658917
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.2758122950
Short name T1040
Test name
Test status
Simulation time 50810748 ps
CPU time 1.12 seconds
Started Oct 15 11:39:55 AM UTC 24
Finished Oct 15 11:39:57 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758122950 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2758122950
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2475579739
Short name T143
Test name
Test status
Simulation time 182363993 ps
CPU time 2.22 seconds
Started Oct 15 11:39:55 AM UTC 24
Finished Oct 15 11:39:58 AM UTC 24
Peak memory 225804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475579739 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.2475579739
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2431473224
Short name T1039
Test name
Test status
Simulation time 100120275 ps
CPU time 0.93 seconds
Started Oct 15 11:39:55 AM UTC 24
Finished Oct 15 11:39:57 AM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431473224 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.2431473224
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1959612165
Short name T161
Test name
Test status
Simulation time 71801314 ps
CPU time 2.28 seconds
Started Oct 15 11:39:56 AM UTC 24
Finished Oct 15 11:40:00 AM UTC 24
Peak memory 227932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959612165 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.1959612165
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1564297793
Short name T118
Test name
Test status
Simulation time 108162973 ps
CPU time 7.52 seconds
Started Oct 15 11:39:55 AM UTC 24
Finished Oct 15 11:40:04 AM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564297793 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.1564297793
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3413534234
Short name T1122
Test name
Test status
Simulation time 48779054 ps
CPU time 0.66 seconds
Started Oct 15 11:40:43 AM UTC 24
Finished Oct 15 11:40:52 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413534234 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.3413534234
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.1209479806
Short name T1117
Test name
Test status
Simulation time 40942986 ps
CPU time 0.63 seconds
Started Oct 15 11:40:43 AM UTC 24
Finished Oct 15 11:40:52 AM UTC 24
Peak memory 212328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209479806 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.1209479806
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3579067369
Short name T1120
Test name
Test status
Simulation time 18985571 ps
CPU time 0.69 seconds
Started Oct 15 11:40:43 AM UTC 24
Finished Oct 15 11:40:52 AM UTC 24
Peak memory 212328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579067369 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.3579067369
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.3367519716
Short name T1123
Test name
Test status
Simulation time 67876221 ps
CPU time 0.76 seconds
Started Oct 15 11:40:43 AM UTC 24
Finished Oct 15 11:40:53 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367519716 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.3367519716
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1092190410
Short name T1127
Test name
Test status
Simulation time 13674074 ps
CPU time 0.73 seconds
Started Oct 15 11:40:46 AM UTC 24
Finished Oct 15 11:40:57 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092190410 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.1092190410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1182722596
Short name T1118
Test name
Test status
Simulation time 13339150 ps
CPU time 0.69 seconds
Started Oct 15 11:40:47 AM UTC 24
Finished Oct 15 11:40:52 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182722596 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.1182722596
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2779180398
Short name T1121
Test name
Test status
Simulation time 42449611 ps
CPU time 0.65 seconds
Started Oct 15 11:40:47 AM UTC 24
Finished Oct 15 11:40:52 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779180398 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.2779180398
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.3552428740
Short name T1119
Test name
Test status
Simulation time 13524375 ps
CPU time 0.68 seconds
Started Oct 15 11:40:47 AM UTC 24
Finished Oct 15 11:40:52 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552428740 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.3552428740
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3791870996
Short name T1125
Test name
Test status
Simulation time 44005641 ps
CPU time 0.87 seconds
Started Oct 15 11:40:47 AM UTC 24
Finished Oct 15 11:40:53 AM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791870996 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.3791870996
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.785291413
Short name T1124
Test name
Test status
Simulation time 240644212 ps
CPU time 0.74 seconds
Started Oct 15 11:40:47 AM UTC 24
Finished Oct 15 11:40:53 AM UTC 24
Peak memory 212484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785291413 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.785291413
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.669342433
Short name T1048
Test name
Test status
Simulation time 98140360 ps
CPU time 2.37 seconds
Started Oct 15 11:39:58 AM UTC 24
Finished Oct 15 11:40:01 AM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=669342433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.spi_device_csr_mem_rw_with_rand_reset.669342433
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.4206925783
Short name T1047
Test name
Test status
Simulation time 203877638 ps
CPU time 2.49 seconds
Started Oct 15 11:39:58 AM UTC 24
Finished Oct 15 11:40:01 AM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206925783 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4206925783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.2352532298
Short name T1043
Test name
Test status
Simulation time 22155583 ps
CPU time 0.97 seconds
Started Oct 15 11:39:58 AM UTC 24
Finished Oct 15 11:40:00 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352532298 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2352532298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4165734180
Short name T165
Test name
Test status
Simulation time 77906710 ps
CPU time 2.12 seconds
Started Oct 15 11:39:58 AM UTC 24
Finished Oct 15 11:40:01 AM UTC 24
Peak memory 226108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165734180 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.4165734180
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.2911505005
Short name T126
Test name
Test status
Simulation time 303622871 ps
CPU time 3.12 seconds
Started Oct 15 11:39:58 AM UTC 24
Finished Oct 15 11:40:02 AM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911505005 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2911505005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.893397377
Short name T164
Test name
Test status
Simulation time 100516043 ps
CPU time 3.38 seconds
Started Oct 15 11:39:59 AM UTC 24
Finished Oct 15 11:40:04 AM UTC 24
Peak memory 227992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=893397377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.spi_device_csr_mem_rw_with_rand_reset.893397377
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1963151120
Short name T163
Test name
Test status
Simulation time 94508519 ps
CPU time 2.83 seconds
Started Oct 15 11:39:59 AM UTC 24
Finished Oct 15 11:40:03 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963151120 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1963151120
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1526639877
Short name T1046
Test name
Test status
Simulation time 14162872 ps
CPU time 1.08 seconds
Started Oct 15 11:39:59 AM UTC 24
Finished Oct 15 11:40:01 AM UTC 24
Peak memory 212024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526639877 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1526639877
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1691286425
Short name T162
Test name
Test status
Simulation time 269225885 ps
CPU time 2.13 seconds
Started Oct 15 11:39:59 AM UTC 24
Finished Oct 15 11:40:02 AM UTC 24
Peak memory 225868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691286425 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.1691286425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2753785654
Short name T129
Test name
Test status
Simulation time 97053167 ps
CPU time 2.33 seconds
Started Oct 15 11:39:58 AM UTC 24
Finished Oct 15 11:40:01 AM UTC 24
Peak memory 228004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753785654 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2753785654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1894174330
Short name T1059
Test name
Test status
Simulation time 597935901 ps
CPU time 7.46 seconds
Started Oct 15 11:39:59 AM UTC 24
Finished Oct 15 11:40:08 AM UTC 24
Peak memory 225492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894174330 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.1894174330
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.594229995
Short name T1055
Test name
Test status
Simulation time 590847200 ps
CPU time 2.5 seconds
Started Oct 15 11:40:02 AM UTC 24
Finished Oct 15 11:40:05 AM UTC 24
Peak memory 228136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=594229995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.spi_device_csr_mem_rw_with_rand_reset.594229995
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3453986202
Short name T1050
Test name
Test status
Simulation time 39381018 ps
CPU time 1.71 seconds
Started Oct 15 11:40:01 AM UTC 24
Finished Oct 15 11:40:04 AM UTC 24
Peak memory 224640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453986202 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3453986202
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1526543883
Short name T1049
Test name
Test status
Simulation time 48627139 ps
CPU time 1.04 seconds
Started Oct 15 11:40:01 AM UTC 24
Finished Oct 15 11:40:03 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526543883 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1526543883
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4173115378
Short name T1053
Test name
Test status
Simulation time 183395889 ps
CPU time 3 seconds
Started Oct 15 11:40:01 AM UTC 24
Finished Oct 15 11:40:05 AM UTC 24
Peak memory 225920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173115378 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.4173115378
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.2702047316
Short name T127
Test name
Test status
Simulation time 206272010 ps
CPU time 6.02 seconds
Started Oct 15 11:40:01 AM UTC 24
Finished Oct 15 11:40:08 AM UTC 24
Peak memory 228136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702047316 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2702047316
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3250036061
Short name T287
Test name
Test status
Simulation time 1441352796 ps
CPU time 10.68 seconds
Started Oct 15 11:40:01 AM UTC 24
Finished Oct 15 11:40:12 AM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250036061 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.3250036061
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2064457602
Short name T1057
Test name
Test status
Simulation time 192150786 ps
CPU time 1.77 seconds
Started Oct 15 11:40:03 AM UTC 24
Finished Oct 15 11:40:06 AM UTC 24
Peak memory 224732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2064457602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.spi_device_csr_mem_rw_with_rand_reset.2064457602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2994409329
Short name T140
Test name
Test status
Simulation time 28812046 ps
CPU time 2.37 seconds
Started Oct 15 11:40:02 AM UTC 24
Finished Oct 15 11:40:06 AM UTC 24
Peak memory 215784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994409329 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2994409329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1264208568
Short name T1051
Test name
Test status
Simulation time 11938499 ps
CPU time 0.94 seconds
Started Oct 15 11:40:02 AM UTC 24
Finished Oct 15 11:40:04 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264208568 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1264208568
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.938934298
Short name T1054
Test name
Test status
Simulation time 56977911 ps
CPU time 2.19 seconds
Started Oct 15 11:40:02 AM UTC 24
Finished Oct 15 11:40:05 AM UTC 24
Peak memory 226180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938934298 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.938934298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3290793977
Short name T115
Test name
Test status
Simulation time 592210075 ps
CPU time 4 seconds
Started Oct 15 11:40:02 AM UTC 24
Finished Oct 15 11:40:07 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290793977 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3290793977
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3451927235
Short name T286
Test name
Test status
Simulation time 813415785 ps
CPU time 11.11 seconds
Started Oct 15 11:40:02 AM UTC 24
Finished Oct 15 11:40:14 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451927235 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.3451927235
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3189030045
Short name T1062
Test name
Test status
Simulation time 283963342 ps
CPU time 2.77 seconds
Started Oct 15 11:40:05 AM UTC 24
Finished Oct 15 11:40:09 AM UTC 24
Peak memory 230144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3189030045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.spi_device_csr_mem_rw_with_rand_reset.3189030045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.4054950866
Short name T141
Test name
Test status
Simulation time 31803436 ps
CPU time 2.19 seconds
Started Oct 15 11:40:05 AM UTC 24
Finished Oct 15 11:40:08 AM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054950866 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4054950866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.242355869
Short name T1056
Test name
Test status
Simulation time 15981707 ps
CPU time 1.14 seconds
Started Oct 15 11:40:04 AM UTC 24
Finished Oct 15 11:40:06 AM UTC 24
Peak memory 212440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242355869 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.242355869
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2714337325
Short name T1061
Test name
Test status
Simulation time 105861799 ps
CPU time 2.65 seconds
Started Oct 15 11:40:05 AM UTC 24
Finished Oct 15 11:40:08 AM UTC 24
Peak memory 225868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714337325 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.2714337325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2365372058
Short name T1058
Test name
Test status
Simulation time 63278448 ps
CPU time 2.29 seconds
Started Oct 15 11:40:03 AM UTC 24
Finished Oct 15 11:40:07 AM UTC 24
Peak memory 226184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365372058 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2365372058
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2855218180
Short name T290
Test name
Test status
Simulation time 627865020 ps
CPU time 12.82 seconds
Started Oct 15 11:40:04 AM UTC 24
Finished Oct 15 11:40:17 AM UTC 24
Peak memory 228060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855218180 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.2855218180
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1733258705
Short name T1
Test name
Test status
Simulation time 23473674 ps
CPU time 1.24 seconds
Started Oct 15 12:27:49 PM UTC 24
Finished Oct 15 12:27:52 PM UTC 24
Peak memory 215360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733258705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1733258705
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.4055339372
Short name T55
Test name
Test status
Simulation time 11983880457 ps
CPU time 30.19 seconds
Started Oct 15 12:27:52 PM UTC 24
Finished Oct 15 12:28:24 PM UTC 24
Peak memory 234856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055339372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4055339372
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3630126452
Short name T15
Test name
Test status
Simulation time 1103532083 ps
CPU time 10.15 seconds
Started Oct 15 12:27:51 PM UTC 24
Finished Oct 15 12:28:03 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630126452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3630126452
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3737211499
Short name T86
Test name
Test status
Simulation time 154084587234 ps
CPU time 188.44 seconds
Started Oct 15 12:27:51 PM UTC 24
Finished Oct 15 12:31:03 PM UTC 24
Peak memory 261480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737211499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.3737211499
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.3644886008
Short name T16
Test name
Test status
Simulation time 2146475504 ps
CPU time 12.35 seconds
Started Oct 15 12:27:51 PM UTC 24
Finished Oct 15 12:28:05 PM UTC 24
Peak memory 234628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644886008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3644886008
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.1944098221
Short name T10
Test name
Test status
Simulation time 8628243408 ps
CPU time 5.41 seconds
Started Oct 15 12:27:51 PM UTC 24
Finished Oct 15 12:27:58 PM UTC 24
Peak memory 235008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944098221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.1944098221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.4200655194
Short name T17
Test name
Test status
Simulation time 1168180097 ps
CPU time 12.7 seconds
Started Oct 15 12:27:51 PM UTC 24
Finished Oct 15 12:28:05 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200655194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4200655194
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3688913255
Short name T5
Test name
Test status
Simulation time 21698274 ps
CPU time 1.72 seconds
Started Oct 15 12:27:50 PM UTC 24
Finished Oct 15 12:27:53 PM UTC 24
Peak memory 226512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688913255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3688913255
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.560143950
Short name T3
Test name
Test status
Simulation time 313993602 ps
CPU time 1.19 seconds
Started Oct 15 12:27:49 PM UTC 24
Finished Oct 15 12:27:52 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560143950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.560143950
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.2315542881
Short name T6
Test name
Test status
Simulation time 297305479 ps
CPU time 3.59 seconds
Started Oct 15 12:27:51 PM UTC 24
Finished Oct 15 12:27:56 PM UTC 24
Peak memory 234672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315542881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2315542881
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/0.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.3991129163
Short name T93
Test name
Test status
Simulation time 23748905 ps
CPU time 1.06 seconds
Started Oct 15 12:28:15 PM UTC 24
Finished Oct 15 12:28:17 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991129163 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3991129163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.857877928
Short name T19
Test name
Test status
Simulation time 611681534 ps
CPU time 5.03 seconds
Started Oct 15 12:28:04 PM UTC 24
Finished Oct 15 12:28:10 PM UTC 24
Peak memory 234672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857877928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.857877928
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.2089120797
Short name T11
Test name
Test status
Simulation time 18309182 ps
CPU time 1.13 seconds
Started Oct 15 12:27:57 PM UTC 24
Finished Oct 15 12:27:59 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089120797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2089120797
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.3493979486
Short name T67
Test name
Test status
Simulation time 36494538914 ps
CPU time 153.73 seconds
Started Oct 15 12:28:07 PM UTC 24
Finished Oct 15 12:30:43 PM UTC 24
Peak memory 263476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493979486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3493979486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.172557043
Short name T207
Test name
Test status
Simulation time 204128411220 ps
CPU time 510.11 seconds
Started Oct 15 12:28:08 PM UTC 24
Finished Oct 15 12:36:45 PM UTC 24
Peak memory 261708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172557043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.172557043
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1796001578
Short name T113
Test name
Test status
Simulation time 65681597658 ps
CPU time 380.78 seconds
Started Oct 15 12:28:06 PM UTC 24
Finished Oct 15 12:34:32 PM UTC 24
Peak memory 283940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796001578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.1796001578
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1775706249
Short name T39
Test name
Test status
Simulation time 2205398977 ps
CPU time 12.44 seconds
Started Oct 15 12:28:01 PM UTC 24
Finished Oct 15 12:28:15 PM UTC 24
Peak memory 245040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775706249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1775706249
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.369071340
Short name T88
Test name
Test status
Simulation time 3864692520 ps
CPU time 22.16 seconds
Started Oct 15 12:28:02 PM UTC 24
Finished Oct 15 12:28:25 PM UTC 24
Peak memory 245016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369071340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.369071340
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.147338493
Short name T25
Test name
Test status
Simulation time 96814890 ps
CPU time 1.5 seconds
Started Oct 15 12:27:57 PM UTC 24
Finished Oct 15 12:27:59 PM UTC 24
Peak memory 228996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147338493 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.147338493
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.891283323
Short name T18
Test name
Test status
Simulation time 645054359 ps
CPU time 5.3 seconds
Started Oct 15 12:28:00 PM UTC 24
Finished Oct 15 12:28:07 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891283323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.891283323
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1579038301
Short name T72
Test name
Test status
Simulation time 208115716 ps
CPU time 3.44 seconds
Started Oct 15 12:28:00 PM UTC 24
Finished Oct 15 12:28:05 PM UTC 24
Peak memory 233200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579038301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1579038301
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2931172113
Short name T46
Test name
Test status
Simulation time 4278406410 ps
CPU time 12.78 seconds
Started Oct 15 12:28:06 PM UTC 24
Finished Oct 15 12:28:20 PM UTC 24
Peak memory 231464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931172113 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.2931172113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.4291026248
Short name T21
Test name
Test status
Simulation time 148362987 ps
CPU time 2 seconds
Started Oct 15 12:28:14 PM UTC 24
Finished Oct 15 12:28:17 PM UTC 24
Peak memory 256924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291026248 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4291026248
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.867659952
Short name T13
Test name
Test status
Simulation time 128300833 ps
CPU time 2.89 seconds
Started Oct 15 12:27:57 PM UTC 24
Finished Oct 15 12:28:01 PM UTC 24
Peak memory 217048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867659952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.867659952
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.263389916
Short name T14
Test name
Test status
Simulation time 269094544 ps
CPU time 1.21 seconds
Started Oct 15 12:28:00 PM UTC 24
Finished Oct 15 12:28:02 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263389916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.263389916
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.1185882538
Short name T38
Test name
Test status
Simulation time 11779386 ps
CPU time 1.08 seconds
Started Oct 15 12:27:58 PM UTC 24
Finished Oct 15 12:28:00 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185882538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1185882538
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/1.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.2842527181
Short name T423
Test name
Test status
Simulation time 38401207 ps
CPU time 1.17 seconds
Started Oct 15 12:34:14 PM UTC 24
Finished Oct 15 12:34:17 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842527181 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.2842527181
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.756785498
Short name T418
Test name
Test status
Simulation time 31917190 ps
CPU time 2.85 seconds
Started Oct 15 12:33:56 PM UTC 24
Finished Oct 15 12:34:00 PM UTC 24
Peak memory 244580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756785498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.756785498
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.3218147506
Short name T412
Test name
Test status
Simulation time 56751939 ps
CPU time 1.18 seconds
Started Oct 15 12:33:44 PM UTC 24
Finished Oct 15 12:33:46 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218147506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3218147506
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1385608383
Short name T420
Test name
Test status
Simulation time 16597184 ps
CPU time 1.24 seconds
Started Oct 15 12:34:08 PM UTC 24
Finished Oct 15 12:34:10 PM UTC 24
Peak memory 225168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385608383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1385608383
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.290352413
Short name T192
Test name
Test status
Simulation time 9177842575 ps
CPU time 47.48 seconds
Started Oct 15 12:34:09 PM UTC 24
Finished Oct 15 12:34:58 PM UTC 24
Peak memory 245144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290352413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.290352413
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.3767890624
Short name T428
Test name
Test status
Simulation time 3326286232 ps
CPU time 33.41 seconds
Started Oct 15 12:33:57 PM UTC 24
Finished Oct 15 12:34:33 PM UTC 24
Peak memory 234788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767890624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3767890624
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.548235107
Short name T416
Test name
Test status
Simulation time 106985312 ps
CPU time 2.42 seconds
Started Oct 15 12:33:51 PM UTC 24
Finished Oct 15 12:33:55 PM UTC 24
Peak memory 244836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548235107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.548235107
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.3086782834
Short name T436
Test name
Test status
Simulation time 5275510012 ps
CPU time 52.73 seconds
Started Oct 15 12:33:56 PM UTC 24
Finished Oct 15 12:34:51 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086782834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3086782834
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.2594709744
Short name T413
Test name
Test status
Simulation time 42272764 ps
CPU time 1.49 seconds
Started Oct 15 12:33:44 PM UTC 24
Finished Oct 15 12:33:47 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594709744 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mem_parity.2594709744
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.559816037
Short name T417
Test name
Test status
Simulation time 83909740 ps
CPU time 3.02 seconds
Started Oct 15 12:33:51 PM UTC 24
Finished Oct 15 12:33:55 PM UTC 24
Peak memory 234688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559816037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.559816037
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.4172688707
Short name T298
Test name
Test status
Simulation time 3093533961 ps
CPU time 16.07 seconds
Started Oct 15 12:33:51 PM UTC 24
Finished Oct 15 12:34:08 PM UTC 24
Peak memory 235060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172688707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4172688707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3807284734
Short name T419
Test name
Test status
Simulation time 87529117 ps
CPU time 5.46 seconds
Started Oct 15 12:34:02 PM UTC 24
Finished Oct 15 12:34:08 PM UTC 24
Peak memory 233220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807284734 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.3807284734
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.800683561
Short name T166
Test name
Test status
Simulation time 3374615763 ps
CPU time 65.16 seconds
Started Oct 15 12:34:11 PM UTC 24
Finished Oct 15 12:35:18 PM UTC 24
Peak memory 261732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800683561 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.800683561
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.3765055951
Short name T355
Test name
Test status
Simulation time 1708374601 ps
CPU time 26.81 seconds
Started Oct 15 12:33:46 PM UTC 24
Finished Oct 15 12:34:15 PM UTC 24
Peak memory 227244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765055951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3765055951
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.2137201899
Short name T421
Test name
Test status
Simulation time 5649311550 ps
CPU time 26.63 seconds
Started Oct 15 12:33:45 PM UTC 24
Finished Oct 15 12:34:13 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137201899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2137201899
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.692854688
Short name T414
Test name
Test status
Simulation time 13173263 ps
CPU time 1.12 seconds
Started Oct 15 12:33:48 PM UTC 24
Finished Oct 15 12:33:50 PM UTC 24
Peak memory 213536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692854688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.692854688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1210191730
Short name T415
Test name
Test status
Simulation time 36475058 ps
CPU time 1.08 seconds
Started Oct 15 12:33:48 PM UTC 24
Finished Oct 15 12:33:50 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210191730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1210191730
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.2017972069
Short name T205
Test name
Test status
Simulation time 324374983 ps
CPU time 8.96 seconds
Started Oct 15 12:33:56 PM UTC 24
Finished Oct 15 12:34:07 PM UTC 24
Peak memory 245160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017972069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2017972069
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/10.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.793545306
Short name T430
Test name
Test status
Simulation time 32975191 ps
CPU time 1.1 seconds
Started Oct 15 12:34:43 PM UTC 24
Finished Oct 15 12:34:45 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793545306 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.793545306
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.3949357150
Short name T441
Test name
Test status
Simulation time 4616002595 ps
CPU time 37.57 seconds
Started Oct 15 12:34:26 PM UTC 24
Finished Oct 15 12:35:05 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949357150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3949357150
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.1076344622
Short name T422
Test name
Test status
Simulation time 26466176 ps
CPU time 1.17 seconds
Started Oct 15 12:34:15 PM UTC 24
Finished Oct 15 12:34:17 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076344622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1076344622
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.3663572954
Short name T315
Test name
Test status
Simulation time 89730177861 ps
CPU time 185.39 seconds
Started Oct 15 12:34:33 PM UTC 24
Finished Oct 15 12:37:41 PM UTC 24
Peak memory 267556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663572954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3663572954
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.916473123
Short name T184
Test name
Test status
Simulation time 3992270271 ps
CPU time 111.88 seconds
Started Oct 15 12:34:34 PM UTC 24
Finished Oct 15 12:36:28 PM UTC 24
Peak memory 267684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916473123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.916473123
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2983754207
Short name T316
Test name
Test status
Simulation time 4900284730 ps
CPU time 98.58 seconds
Started Oct 15 12:34:36 PM UTC 24
Finished Oct 15 12:36:17 PM UTC 24
Peak memory 267596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983754207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.2983754207
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.4155817893
Short name T429
Test name
Test status
Simulation time 286591161 ps
CPU time 6.74 seconds
Started Oct 15 12:34:27 PM UTC 24
Finished Oct 15 12:34:35 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155817893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4155817893
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.2380778410
Short name T221
Test name
Test status
Simulation time 483632629 ps
CPU time 4.55 seconds
Started Oct 15 12:34:23 PM UTC 24
Finished Oct 15 12:34:28 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380778410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2380778410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.3624998509
Short name T238
Test name
Test status
Simulation time 358644808 ps
CPU time 11.92 seconds
Started Oct 15 12:34:24 PM UTC 24
Finished Oct 15 12:34:37 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624998509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3624998509
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.331541227
Short name T424
Test name
Test status
Simulation time 63134936 ps
CPU time 1.63 seconds
Started Oct 15 12:34:16 PM UTC 24
Finished Oct 15 12:34:18 PM UTC 24
Peak memory 228936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331541227 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mem_parity.331541227
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.483519244
Short name T427
Test name
Test status
Simulation time 28988651 ps
CPU time 2.93 seconds
Started Oct 15 12:34:21 PM UTC 24
Finished Oct 15 12:34:26 PM UTC 24
Peak memory 233164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483519244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.483519244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2880584631
Short name T426
Test name
Test status
Simulation time 55239899 ps
CPU time 2.92 seconds
Started Oct 15 12:34:20 PM UTC 24
Finished Oct 15 12:34:24 PM UTC 24
Peak memory 233196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880584631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2880584631
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3793780748
Short name T431
Test name
Test status
Simulation time 2779784011 ps
CPU time 12.78 seconds
Started Oct 15 12:34:31 PM UTC 24
Finished Oct 15 12:34:45 PM UTC 24
Peak memory 233348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793780748 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.3793780748
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.1826611042
Short name T353
Test name
Test status
Simulation time 4475421025 ps
CPU time 42.64 seconds
Started Oct 15 12:34:18 PM UTC 24
Finished Oct 15 12:35:02 PM UTC 24
Peak memory 227120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826611042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1826611042
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3180989629
Short name T432
Test name
Test status
Simulation time 11379409406 ps
CPU time 30.17 seconds
Started Oct 15 12:34:16 PM UTC 24
Finished Oct 15 12:34:47 PM UTC 24
Peak memory 227628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180989629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3180989629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.1427509367
Short name T367
Test name
Test status
Simulation time 181167292 ps
CPU time 4.55 seconds
Started Oct 15 12:34:19 PM UTC 24
Finished Oct 15 12:34:25 PM UTC 24
Peak memory 227240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427509367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1427509367
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.3741640823
Short name T425
Test name
Test status
Simulation time 39287277 ps
CPU time 1.18 seconds
Started Oct 15 12:34:18 PM UTC 24
Finished Oct 15 12:34:20 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741640823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3741640823
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.1360620393
Short name T243
Test name
Test status
Simulation time 1512489736 ps
CPU time 15.67 seconds
Started Oct 15 12:34:25 PM UTC 24
Finished Oct 15 12:34:42 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360620393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1360620393
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/11.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.3269094791
Short name T444
Test name
Test status
Simulation time 15663856 ps
CPU time 1.21 seconds
Started Oct 15 12:35:18 PM UTC 24
Finished Oct 15 12:35:21 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269094791 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.3269094791
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.4241086258
Short name T445
Test name
Test status
Simulation time 4337600816 ps
CPU time 20.35 seconds
Started Oct 15 12:35:00 PM UTC 24
Finished Oct 15 12:35:22 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241086258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4241086258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.1484989854
Short name T433
Test name
Test status
Simulation time 32478139 ps
CPU time 1.21 seconds
Started Oct 15 12:34:46 PM UTC 24
Finished Oct 15 12:34:49 PM UTC 24
Peak memory 213336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484989854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1484989854
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.1220068365
Short name T273
Test name
Test status
Simulation time 175353622685 ps
CPU time 414.14 seconds
Started Oct 15 12:35:06 PM UTC 24
Finished Oct 15 12:42:06 PM UTC 24
Peak memory 267616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220068365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1220068365
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2373431266
Short name T354
Test name
Test status
Simulation time 2702038816 ps
CPU time 28.48 seconds
Started Oct 15 12:35:06 PM UTC 24
Finished Oct 15 12:35:36 PM UTC 24
Peak memory 245304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373431266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2373431266
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1982327583
Short name T319
Test name
Test status
Simulation time 24968752723 ps
CPU time 226.82 seconds
Started Oct 15 12:35:13 PM UTC 24
Finished Oct 15 12:39:03 PM UTC 24
Peak memory 245320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982327583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.1982327583
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.2181349118
Short name T449
Test name
Test status
Simulation time 3460264361 ps
CPU time 25.85 seconds
Started Oct 15 12:35:03 PM UTC 24
Finished Oct 15 12:35:30 PM UTC 24
Peak memory 235044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181349118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2181349118
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.2954028167
Short name T220
Test name
Test status
Simulation time 32723293181 ps
CPU time 262.9 seconds
Started Oct 15 12:35:04 PM UTC 24
Finished Oct 15 12:39:31 PM UTC 24
Peak memory 273704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954028167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.2954028167
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2229353163
Short name T439
Test name
Test status
Simulation time 66052169 ps
CPU time 3.1 seconds
Started Oct 15 12:34:55 PM UTC 24
Finished Oct 15 12:34:59 PM UTC 24
Peak memory 244580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229353163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2229353163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.1753511128
Short name T340
Test name
Test status
Simulation time 4768863556 ps
CPU time 39.91 seconds
Started Oct 15 12:34:59 PM UTC 24
Finished Oct 15 12:35:41 PM UTC 24
Peak memory 245092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753511128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1753511128
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.2436540350
Short name T434
Test name
Test status
Simulation time 29893587 ps
CPU time 1.5 seconds
Started Oct 15 12:34:46 PM UTC 24
Finished Oct 15 12:34:49 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436540350 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mem_parity.2436540350
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3727568698
Short name T226
Test name
Test status
Simulation time 24888817228 ps
CPU time 31.85 seconds
Started Oct 15 12:34:53 PM UTC 24
Finished Oct 15 12:35:26 PM UTC 24
Peak memory 251192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727568698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.3727568698
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.3851193353
Short name T325
Test name
Test status
Simulation time 23327918694 ps
CPU time 20.22 seconds
Started Oct 15 12:34:52 PM UTC 24
Finished Oct 15 12:35:13 PM UTC 24
Peak memory 234784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851193353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3851193353
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.111443781
Short name T442
Test name
Test status
Simulation time 230680905 ps
CPU time 7.43 seconds
Started Oct 15 12:35:04 PM UTC 24
Finished Oct 15 12:35:13 PM UTC 24
Peak memory 233228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111443781 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.111443781
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.2671712509
Short name T352
Test name
Test status
Simulation time 12132218227 ps
CPU time 102.85 seconds
Started Oct 15 12:35:14 PM UTC 24
Finished Oct 15 12:36:59 PM UTC 24
Peak memory 261732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671712509 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.2671712509
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.2115722645
Short name T360
Test name
Test status
Simulation time 3752637117 ps
CPU time 26.5 seconds
Started Oct 15 12:34:50 PM UTC 24
Finished Oct 15 12:35:17 PM UTC 24
Peak memory 227480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115722645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2115722645
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.3617988115
Short name T435
Test name
Test status
Simulation time 15176473 ps
CPU time 1.16 seconds
Started Oct 15 12:34:49 PM UTC 24
Finished Oct 15 12:34:51 PM UTC 24
Peak memory 213472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617988115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3617988115
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.3347022674
Short name T438
Test name
Test status
Simulation time 45446417 ps
CPU time 1.29 seconds
Started Oct 15 12:34:52 PM UTC 24
Finished Oct 15 12:34:54 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347022674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3347022674
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3158723252
Short name T437
Test name
Test status
Simulation time 232775197 ps
CPU time 1.33 seconds
Started Oct 15 12:34:50 PM UTC 24
Finished Oct 15 12:34:52 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158723252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3158723252
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.194578294
Short name T440
Test name
Test status
Simulation time 131831718 ps
CPU time 3.26 seconds
Started Oct 15 12:35:00 PM UTC 24
Finished Oct 15 12:35:05 PM UTC 24
Peak memory 234564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194578294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.194578294
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/12.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.2503483776
Short name T454
Test name
Test status
Simulation time 36384246 ps
CPU time 1.07 seconds
Started Oct 15 12:35:55 PM UTC 24
Finished Oct 15 12:35:57 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503483776 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.2503483776
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.116185314
Short name T227
Test name
Test status
Simulation time 2241089012 ps
CPU time 5.51 seconds
Started Oct 15 12:35:37 PM UTC 24
Finished Oct 15 12:35:43 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116185314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.116185314
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.2155344261
Short name T443
Test name
Test status
Simulation time 87725069 ps
CPU time 1.16 seconds
Started Oct 15 12:35:18 PM UTC 24
Finished Oct 15 12:35:21 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155344261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2155344261
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1012188922
Short name T186
Test name
Test status
Simulation time 18172865949 ps
CPU time 50.27 seconds
Started Oct 15 12:35:49 PM UTC 24
Finished Oct 15 12:36:41 PM UTC 24
Peak memory 233644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012188922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1012188922
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2062872962
Short name T574
Test name
Test status
Simulation time 298670286541 ps
CPU time 260.65 seconds
Started Oct 15 12:35:51 PM UTC 24
Finished Oct 15 12:40:15 PM UTC 24
Peak memory 267532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062872962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.2062872962
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.3343384995
Short name T453
Test name
Test status
Simulation time 518549710 ps
CPU time 13.91 seconds
Started Oct 15 12:35:37 PM UTC 24
Finished Oct 15 12:35:52 PM UTC 24
Peak memory 234648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343384995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3343384995
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2929388007
Short name T206
Test name
Test status
Simulation time 73749695630 ps
CPU time 168.71 seconds
Started Oct 15 12:35:42 PM UTC 24
Finished Oct 15 12:38:34 PM UTC 24
Peak memory 267556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929388007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.2929388007
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.2220363162
Short name T314
Test name
Test status
Simulation time 566971929 ps
CPU time 3.93 seconds
Started Oct 15 12:35:32 PM UTC 24
Finished Oct 15 12:35:36 PM UTC 24
Peak memory 234780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220363162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2220363162
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.1644896119
Short name T328
Test name
Test status
Simulation time 22857618007 ps
CPU time 56.21 seconds
Started Oct 15 12:35:32 PM UTC 24
Finished Oct 15 12:36:29 PM UTC 24
Peak memory 234852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644896119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1644896119
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.1570479502
Short name T446
Test name
Test status
Simulation time 26500851 ps
CPU time 1.39 seconds
Started Oct 15 12:35:22 PM UTC 24
Finished Oct 15 12:35:24 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570479502 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mem_parity.1570479502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2435104579
Short name T223
Test name
Test status
Simulation time 128658202 ps
CPU time 4.37 seconds
Started Oct 15 12:35:29 PM UTC 24
Finished Oct 15 12:35:35 PM UTC 24
Peak memory 234672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435104579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.2435104579
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.1995594555
Short name T335
Test name
Test status
Simulation time 6855776767 ps
CPU time 24.63 seconds
Started Oct 15 12:35:28 PM UTC 24
Finished Oct 15 12:35:54 PM UTC 24
Peak memory 245340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995594555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1995594555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.4245619816
Short name T452
Test name
Test status
Simulation time 388989744 ps
CPU time 5.31 seconds
Started Oct 15 12:35:43 PM UTC 24
Finished Oct 15 12:35:50 PM UTC 24
Peak memory 233504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245619816 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.4245619816
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.2325588116
Short name T362
Test name
Test status
Simulation time 16808858821 ps
CPU time 30.01 seconds
Started Oct 15 12:35:23 PM UTC 24
Finished Oct 15 12:35:54 PM UTC 24
Peak memory 227628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325588116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2325588116
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.878619947
Short name T448
Test name
Test status
Simulation time 1463814293 ps
CPU time 5.26 seconds
Started Oct 15 12:35:22 PM UTC 24
Finished Oct 15 12:35:28 PM UTC 24
Peak memory 227344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878619947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.878619947
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.3184350328
Short name T450
Test name
Test status
Simulation time 82168127 ps
CPU time 2.77 seconds
Started Oct 15 12:35:27 PM UTC 24
Finished Oct 15 12:35:31 PM UTC 24
Peak memory 227296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184350328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3184350328
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2966501292
Short name T447
Test name
Test status
Simulation time 361952505 ps
CPU time 1.21 seconds
Started Oct 15 12:35:25 PM UTC 24
Finished Oct 15 12:35:27 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966501292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2966501292
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.1923332366
Short name T236
Test name
Test status
Simulation time 8193139685 ps
CPU time 17.61 seconds
Started Oct 15 12:35:36 PM UTC 24
Finished Oct 15 12:35:54 PM UTC 24
Peak memory 244976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923332366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1923332366
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/13.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.2704605907
Short name T463
Test name
Test status
Simulation time 17525362 ps
CPU time 1.18 seconds
Started Oct 15 12:36:30 PM UTC 24
Finished Oct 15 12:36:32 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704605907 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.2704605907
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.4050222166
Short name T461
Test name
Test status
Simulation time 58349789 ps
CPU time 2.21 seconds
Started Oct 15 12:36:16 PM UTC 24
Finished Oct 15 12:36:19 PM UTC 24
Peak memory 244572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050222166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4050222166
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.2109163453
Short name T455
Test name
Test status
Simulation time 22243276 ps
CPU time 1.23 seconds
Started Oct 15 12:35:55 PM UTC 24
Finished Oct 15 12:35:57 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109163453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2109163453
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.3952624663
Short name T476
Test name
Test status
Simulation time 1744533726 ps
CPU time 36.75 seconds
Started Oct 15 12:36:23 PM UTC 24
Finished Oct 15 12:37:01 PM UTC 24
Peak memory 261340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952624663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3952624663
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.2026056712
Short name T346
Test name
Test status
Simulation time 3250052235 ps
CPU time 37.5 seconds
Started Oct 15 12:36:17 PM UTC 24
Finished Oct 15 12:36:56 PM UTC 24
Peak memory 251424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026056712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2026056712
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.2566742963
Short name T193
Test name
Test status
Simulation time 418891989 ps
CPU time 10.72 seconds
Started Oct 15 12:36:05 PM UTC 24
Finished Oct 15 12:36:17 PM UTC 24
Peak memory 234660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566742963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2566742963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.2595613584
Short name T234
Test name
Test status
Simulation time 3841861014 ps
CPU time 25.73 seconds
Started Oct 15 12:36:06 PM UTC 24
Finished Oct 15 12:36:33 PM UTC 24
Peak memory 251240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595613584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2595613584
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.1808651179
Short name T456
Test name
Test status
Simulation time 55712072 ps
CPU time 1.54 seconds
Started Oct 15 12:35:56 PM UTC 24
Finished Oct 15 12:35:59 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808651179 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mem_parity.1808651179
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2460787345
Short name T228
Test name
Test status
Simulation time 1947785003 ps
CPU time 9.01 seconds
Started Oct 15 12:36:05 PM UTC 24
Finished Oct 15 12:36:15 PM UTC 24
Peak memory 234656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460787345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.2460787345
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3208912895
Short name T299
Test name
Test status
Simulation time 4390393977 ps
CPU time 9.03 seconds
Started Oct 15 12:36:03 PM UTC 24
Finished Oct 15 12:36:13 PM UTC 24
Peak memory 245044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208912895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3208912895
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3392098136
Short name T462
Test name
Test status
Simulation time 431038120 ps
CPU time 4.96 seconds
Started Oct 15 12:36:20 PM UTC 24
Finished Oct 15 12:36:26 PM UTC 24
Peak memory 231172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392098136 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.3392098136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.2200661619
Short name T458
Test name
Test status
Simulation time 516751165 ps
CPU time 4.6 seconds
Started Oct 15 12:35:58 PM UTC 24
Finished Oct 15 12:36:04 PM UTC 24
Peak memory 227544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200661619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2200661619
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.3204584339
Short name T460
Test name
Test status
Simulation time 718271554 ps
CPU time 5.49 seconds
Started Oct 15 12:35:58 PM UTC 24
Finished Oct 15 12:36:05 PM UTC 24
Peak memory 227240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204584339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3204584339
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.1684964716
Short name T459
Test name
Test status
Simulation time 79802707 ps
CPU time 1.58 seconds
Started Oct 15 12:36:01 PM UTC 24
Finished Oct 15 12:36:04 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684964716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1684964716
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.297405380
Short name T457
Test name
Test status
Simulation time 15390233 ps
CPU time 1.17 seconds
Started Oct 15 12:35:59 PM UTC 24
Finished Oct 15 12:36:01 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297405380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.297405380
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.1503232123
Short name T334
Test name
Test status
Simulation time 2792927554 ps
CPU time 7.06 seconds
Started Oct 15 12:36:14 PM UTC 24
Finished Oct 15 12:36:22 PM UTC 24
Peak memory 245044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503232123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1503232123
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/14.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.3978777980
Short name T475
Test name
Test status
Simulation time 26568065 ps
CPU time 1.16 seconds
Started Oct 15 12:36:58 PM UTC 24
Finished Oct 15 12:37:00 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978777980 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.3978777980
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.21337596
Short name T473
Test name
Test status
Simulation time 750802526 ps
CPU time 11.47 seconds
Started Oct 15 12:36:44 PM UTC 24
Finished Oct 15 12:36:57 PM UTC 24
Peak memory 234936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21337596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.21337596
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.1279448783
Short name T464
Test name
Test status
Simulation time 16768780 ps
CPU time 1.15 seconds
Started Oct 15 12:36:33 PM UTC 24
Finished Oct 15 12:36:35 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279448783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1279448783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.1364160216
Short name T471
Test name
Test status
Simulation time 92187304 ps
CPU time 1.24 seconds
Started Oct 15 12:36:48 PM UTC 24
Finished Oct 15 12:36:50 PM UTC 24
Peak memory 225168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364160216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1364160216
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1058534765
Short name T202
Test name
Test status
Simulation time 14613445423 ps
CPU time 178.23 seconds
Started Oct 15 12:36:51 PM UTC 24
Finished Oct 15 12:39:52 PM UTC 24
Peak memory 284080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058534765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1058534765
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.3186871796
Short name T492
Test name
Test status
Simulation time 11072964358 ps
CPU time 33.87 seconds
Started Oct 15 12:36:53 PM UTC 24
Finished Oct 15 12:37:28 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186871796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.3186871796
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.4173667679
Short name T472
Test name
Test status
Simulation time 230711177 ps
CPU time 4.94 seconds
Started Oct 15 12:36:45 PM UTC 24
Finished Oct 15 12:36:51 PM UTC 24
Peak memory 244964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173667679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4173667679
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1830271461
Short name T255
Test name
Test status
Simulation time 1118452703 ps
CPU time 28.04 seconds
Started Oct 15 12:36:45 PM UTC 24
Finished Oct 15 12:37:15 PM UTC 24
Peak memory 249056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830271461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.1830271461
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.2991057086
Short name T217
Test name
Test status
Simulation time 14234608782 ps
CPU time 17.95 seconds
Started Oct 15 12:36:40 PM UTC 24
Finished Oct 15 12:36:59 PM UTC 24
Peak memory 234996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991057086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2991057086
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.1561615775
Short name T586
Test name
Test status
Simulation time 209575090861 ps
CPU time 227.76 seconds
Started Oct 15 12:36:41 PM UTC 24
Finished Oct 15 12:40:32 PM UTC 24
Peak memory 247456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561615775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1561615775
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.1763425845
Short name T465
Test name
Test status
Simulation time 48737655 ps
CPU time 1.41 seconds
Started Oct 15 12:36:34 PM UTC 24
Finished Oct 15 12:36:37 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763425845 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.1763425845
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3154336445
Short name T336
Test name
Test status
Simulation time 563350563 ps
CPU time 6.29 seconds
Started Oct 15 12:36:39 PM UTC 24
Finished Oct 15 12:36:46 PM UTC 24
Peak memory 234312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154336445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.3154336445
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.3387720704
Short name T313
Test name
Test status
Simulation time 4255851442 ps
CPU time 24.74 seconds
Started Oct 15 12:36:39 PM UTC 24
Finished Oct 15 12:37:05 PM UTC 24
Peak memory 249180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387720704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3387720704
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.1704408078
Short name T479
Test name
Test status
Simulation time 1655665378 ps
CPU time 15.18 seconds
Started Oct 15 12:36:46 PM UTC 24
Finished Oct 15 12:37:03 PM UTC 24
Peak memory 233348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704408078 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.1704408078
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.2024315774
Short name T474
Test name
Test status
Simulation time 56403993 ps
CPU time 1.55 seconds
Started Oct 15 12:36:57 PM UTC 24
Finished Oct 15 12:36:59 PM UTC 24
Peak memory 216348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024315774 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.2024315774
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.1924478306
Short name T466
Test name
Test status
Simulation time 42119125 ps
CPU time 1.09 seconds
Started Oct 15 12:36:35 PM UTC 24
Finished Oct 15 12:36:38 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924478306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1924478306
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.4216883815
Short name T469
Test name
Test status
Simulation time 8056831458 ps
CPU time 8.49 seconds
Started Oct 15 12:36:34 PM UTC 24
Finished Oct 15 12:36:44 PM UTC 24
Peak memory 227624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216883815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4216883815
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.3462014561
Short name T468
Test name
Test status
Simulation time 22428448 ps
CPU time 1.61 seconds
Started Oct 15 12:36:37 PM UTC 24
Finished Oct 15 12:36:40 PM UTC 24
Peak memory 216060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462014561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3462014561
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.1359705221
Short name T467
Test name
Test status
Simulation time 23791583 ps
CPU time 1.21 seconds
Started Oct 15 12:36:36 PM UTC 24
Finished Oct 15 12:36:39 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359705221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1359705221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.2663489905
Short name T470
Test name
Test status
Simulation time 59807236 ps
CPU time 2.85 seconds
Started Oct 15 12:36:42 PM UTC 24
Finished Oct 15 12:36:46 PM UTC 24
Peak memory 234392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663489905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2663489905
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/15.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.833607599
Short name T485
Test name
Test status
Simulation time 41216391 ps
CPU time 1.11 seconds
Started Oct 15 12:37:16 PM UTC 24
Finished Oct 15 12:37:18 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833607599 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.833607599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.1481426870
Short name T225
Test name
Test status
Simulation time 736068881 ps
CPU time 6.94 seconds
Started Oct 15 12:37:05 PM UTC 24
Finished Oct 15 12:37:13 PM UTC 24
Peak memory 234408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481426870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1481426870
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.1664562239
Short name T477
Test name
Test status
Simulation time 31376840 ps
CPU time 1.1 seconds
Started Oct 15 12:37:00 PM UTC 24
Finished Oct 15 12:37:02 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664562239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1664562239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.271162326
Short name T276
Test name
Test status
Simulation time 89236360503 ps
CPU time 226.35 seconds
Started Oct 15 12:37:10 PM UTC 24
Finished Oct 15 12:41:00 PM UTC 24
Peak memory 265832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271162326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.271162326
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3023071473
Short name T214
Test name
Test status
Simulation time 16031992078 ps
CPU time 190.65 seconds
Started Oct 15 12:37:11 PM UTC 24
Finished Oct 15 12:40:25 PM UTC 24
Peak memory 261788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023071473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3023071473
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2688480778
Short name T1001
Test name
Test status
Simulation time 188194523768 ps
CPU time 916.43 seconds
Started Oct 15 12:37:13 PM UTC 24
Finished Oct 15 12:52:41 PM UTC 24
Peak memory 294488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688480778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2688480778
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.2726177136
Short name T502
Test name
Test status
Simulation time 4948421588 ps
CPU time 45.8 seconds
Started Oct 15 12:37:05 PM UTC 24
Finished Oct 15 12:37:52 PM UTC 24
Peak memory 245288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726177136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2726177136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.1698913471
Short name T306
Test name
Test status
Simulation time 636190880 ps
CPU time 15.52 seconds
Started Oct 15 12:37:06 PM UTC 24
Finished Oct 15 12:37:22 PM UTC 24
Peak memory 245220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698913471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.1698913471
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.3652705399
Short name T331
Test name
Test status
Simulation time 1803185162 ps
CPU time 16.95 seconds
Started Oct 15 12:37:03 PM UTC 24
Finished Oct 15 12:37:21 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652705399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3652705399
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.1171195222
Short name T190
Test name
Test status
Simulation time 324785837 ps
CPU time 9.89 seconds
Started Oct 15 12:37:03 PM UTC 24
Finished Oct 15 12:37:14 PM UTC 24
Peak memory 251036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171195222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1171195222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.1260813243
Short name T478
Test name
Test status
Simulation time 89635284 ps
CPU time 1.38 seconds
Started Oct 15 12:37:00 PM UTC 24
Finished Oct 15 12:37:03 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260813243 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.1260813243
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.471754419
Short name T487
Test name
Test status
Simulation time 1434830309 ps
CPU time 13.61 seconds
Started Oct 15 12:37:03 PM UTC 24
Finished Oct 15 12:37:18 PM UTC 24
Peak memory 251316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471754419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.471754419
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.3455078835
Short name T201
Test name
Test status
Simulation time 339153250 ps
CPU time 6.37 seconds
Started Oct 15 12:37:03 PM UTC 24
Finished Oct 15 12:37:11 PM UTC 24
Peak memory 234672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455078835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3455078835
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.1865946763
Short name T484
Test name
Test status
Simulation time 226363690 ps
CPU time 6.97 seconds
Started Oct 15 12:37:07 PM UTC 24
Finished Oct 15 12:37:15 PM UTC 24
Peak memory 233236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865946763 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.1865946763
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.3836803321
Short name T523
Test name
Test status
Simulation time 12601487245 ps
CPU time 79.15 seconds
Started Oct 15 12:37:16 PM UTC 24
Finished Oct 15 12:38:37 PM UTC 24
Peak memory 283996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836803321 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.3836803321
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.391757938
Short name T361
Test name
Test status
Simulation time 7316887388 ps
CPU time 12.74 seconds
Started Oct 15 12:37:02 PM UTC 24
Finished Oct 15 12:37:15 PM UTC 24
Peak memory 227672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391757938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.391757938
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.458293273
Short name T482
Test name
Test status
Simulation time 1200658509 ps
CPU time 4.56 seconds
Started Oct 15 12:37:00 PM UTC 24
Finished Oct 15 12:37:06 PM UTC 24
Peak memory 216788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458293273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.458293273
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.3309119923
Short name T481
Test name
Test status
Simulation time 39096835 ps
CPU time 1.33 seconds
Started Oct 15 12:37:02 PM UTC 24
Finished Oct 15 12:37:04 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309119923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3309119923
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.947502563
Short name T480
Test name
Test status
Simulation time 19198471 ps
CPU time 1.19 seconds
Started Oct 15 12:37:02 PM UTC 24
Finished Oct 15 12:37:04 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947502563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.947502563
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.1829701552
Short name T483
Test name
Test status
Simulation time 257715675 ps
CPU time 3.18 seconds
Started Oct 15 12:37:05 PM UTC 24
Finished Oct 15 12:37:09 PM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829701552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1829701552
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/16.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.3980891340
Short name T496
Test name
Test status
Simulation time 12267940 ps
CPU time 1.11 seconds
Started Oct 15 12:37:41 PM UTC 24
Finished Oct 15 12:37:43 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980891340 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.3980891340
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.3634109633
Short name T108
Test name
Test status
Simulation time 414649943 ps
CPU time 5.51 seconds
Started Oct 15 12:37:29 PM UTC 24
Finished Oct 15 12:37:36 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634109633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3634109633
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.2737636929
Short name T486
Test name
Test status
Simulation time 34955003 ps
CPU time 1.2 seconds
Started Oct 15 12:37:16 PM UTC 24
Finished Oct 15 12:37:18 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737636929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2737636929
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.1459148091
Short name T222
Test name
Test status
Simulation time 6888389407 ps
CPU time 40.12 seconds
Started Oct 15 12:37:37 PM UTC 24
Finished Oct 15 12:38:18 PM UTC 24
Peak memory 251492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459148091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1459148091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.3027142912
Short name T359
Test name
Test status
Simulation time 3610261545 ps
CPU time 66.69 seconds
Started Oct 15 12:37:39 PM UTC 24
Finished Oct 15 12:38:47 PM UTC 24
Peak memory 263520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027142912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.3027142912
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.3872341096
Short name T339
Test name
Test status
Simulation time 27180300911 ps
CPU time 59.77 seconds
Started Oct 15 12:37:30 PM UTC 24
Finished Oct 15 12:38:32 PM UTC 24
Peak memory 235044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872341096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.3872341096
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.1772556559
Short name T203
Test name
Test status
Simulation time 1073137914 ps
CPU time 13.01 seconds
Started Oct 15 12:37:24 PM UTC 24
Finished Oct 15 12:37:38 PM UTC 24
Peak memory 244916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772556559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1772556559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.2751286961
Short name T329
Test name
Test status
Simulation time 2958025307 ps
CPU time 29.42 seconds
Started Oct 15 12:37:25 PM UTC 24
Finished Oct 15 12:37:56 PM UTC 24
Peak memory 234592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751286961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2751286961
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.2597816728
Short name T488
Test name
Test status
Simulation time 266159859 ps
CPU time 1.66 seconds
Started Oct 15 12:37:17 PM UTC 24
Finished Oct 15 12:37:20 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597816728 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.2597816728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.3122049392
Short name T245
Test name
Test status
Simulation time 723128692 ps
CPU time 4.67 seconds
Started Oct 15 12:37:23 PM UTC 24
Finished Oct 15 12:37:28 PM UTC 24
Peak memory 244904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122049392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.3122049392
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.748036478
Short name T187
Test name
Test status
Simulation time 999181678 ps
CPU time 8.64 seconds
Started Oct 15 12:37:23 PM UTC 24
Finished Oct 15 12:37:32 PM UTC 24
Peak memory 234676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748036478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.748036478
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.3735536952
Short name T499
Test name
Test status
Simulation time 965527288 ps
CPU time 14.9 seconds
Started Oct 15 12:37:31 PM UTC 24
Finished Oct 15 12:37:48 PM UTC 24
Peak memory 233132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735536952 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.3735536952
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.3448861081
Short name T494
Test name
Test status
Simulation time 182692406 ps
CPU time 1.66 seconds
Started Oct 15 12:37:40 PM UTC 24
Finished Oct 15 12:37:43 PM UTC 24
Peak memory 216448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448861081 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.3448861081
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.1177701340
Short name T491
Test name
Test status
Simulation time 680458945 ps
CPU time 3.74 seconds
Started Oct 15 12:37:19 PM UTC 24
Finished Oct 15 12:37:24 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177701340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1177701340
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2716583805
Short name T493
Test name
Test status
Simulation time 6711760232 ps
CPU time 18.44 seconds
Started Oct 15 12:37:19 PM UTC 24
Finished Oct 15 12:37:39 PM UTC 24
Peak memory 227712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716583805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2716583805
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.918122442
Short name T490
Test name
Test status
Simulation time 147514576 ps
CPU time 2.13 seconds
Started Oct 15 12:37:20 PM UTC 24
Finished Oct 15 12:37:24 PM UTC 24
Peak memory 227236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918122442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.918122442
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.2926102263
Short name T489
Test name
Test status
Simulation time 44476289 ps
CPU time 1.19 seconds
Started Oct 15 12:37:19 PM UTC 24
Finished Oct 15 12:37:21 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926102263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2926102263
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.727821786
Short name T312
Test name
Test status
Simulation time 3024413078 ps
CPU time 16.04 seconds
Started Oct 15 12:37:25 PM UTC 24
Finished Oct 15 12:37:42 PM UTC 24
Peak memory 245048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727821786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.727821786
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/17.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.1977921895
Short name T508
Test name
Test status
Simulation time 45730453 ps
CPU time 1.14 seconds
Started Oct 15 12:38:00 PM UTC 24
Finished Oct 15 12:38:02 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977921895 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.1977921895
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.1141484488
Short name T505
Test name
Test status
Simulation time 1126767161 ps
CPU time 4.34 seconds
Started Oct 15 12:37:52 PM UTC 24
Finished Oct 15 12:37:57 PM UTC 24
Peak memory 244968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141484488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1141484488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.3518525217
Short name T495
Test name
Test status
Simulation time 49180680 ps
CPU time 1.06 seconds
Started Oct 15 12:37:41 PM UTC 24
Finished Oct 15 12:37:43 PM UTC 24
Peak memory 213404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518525217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3518525217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.167210961
Short name T506
Test name
Test status
Simulation time 22928864 ps
CPU time 1.22 seconds
Started Oct 15 12:37:56 PM UTC 24
Finished Oct 15 12:37:58 PM UTC 24
Peak memory 225172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167210961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.167210961
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1979172192
Short name T563
Test name
Test status
Simulation time 8846546790 ps
CPU time 118.93 seconds
Started Oct 15 12:37:57 PM UTC 24
Finished Oct 15 12:39:59 PM UTC 24
Peak memory 261468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979172192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.1979172192
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.650813440
Short name T510
Test name
Test status
Simulation time 2905325167 ps
CPU time 10.15 seconds
Started Oct 15 12:37:53 PM UTC 24
Finished Oct 15 12:38:04 PM UTC 24
Peak memory 245032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650813440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.650813440
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.915218762
Short name T653
Test name
Test status
Simulation time 26451957722 ps
CPU time 303.79 seconds
Started Oct 15 12:37:55 PM UTC 24
Finished Oct 15 12:43:03 PM UTC 24
Peak memory 261416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915218762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.915218762
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.1945631424
Short name T332
Test name
Test status
Simulation time 297415439 ps
CPU time 7.16 seconds
Started Oct 15 12:37:48 PM UTC 24
Finished Oct 15 12:37:57 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945631424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1945631424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.3738430207
Short name T308
Test name
Test status
Simulation time 1645308091 ps
CPU time 17.79 seconds
Started Oct 15 12:37:48 PM UTC 24
Finished Oct 15 12:38:07 PM UTC 24
Peak memory 261556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738430207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3738430207
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.1193568941
Short name T497
Test name
Test status
Simulation time 29588690 ps
CPU time 1.57 seconds
Started Oct 15 12:37:42 PM UTC 24
Finished Oct 15 12:37:45 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193568941 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mem_parity.1193568941
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.3752532460
Short name T501
Test name
Test status
Simulation time 30634707 ps
CPU time 2.92 seconds
Started Oct 15 12:37:47 PM UTC 24
Finished Oct 15 12:37:51 PM UTC 24
Peak memory 244644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752532460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.3752532460
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.3541990592
Short name T504
Test name
Test status
Simulation time 333499247 ps
CPU time 7.66 seconds
Started Oct 15 12:37:46 PM UTC 24
Finished Oct 15 12:37:55 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541990592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3541990592
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1103795169
Short name T516
Test name
Test status
Simulation time 7467818110 ps
CPU time 19.63 seconds
Started Oct 15 12:37:56 PM UTC 24
Finished Oct 15 12:38:17 PM UTC 24
Peak memory 231124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103795169 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.1103795169
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.929539216
Short name T515
Test name
Test status
Simulation time 3884687287 ps
CPU time 27.8 seconds
Started Oct 15 12:37:44 PM UTC 24
Finished Oct 15 12:38:13 PM UTC 24
Peak memory 227628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929539216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.929539216
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3127225539
Short name T507
Test name
Test status
Simulation time 14882288300 ps
CPU time 14.26 seconds
Started Oct 15 12:37:44 PM UTC 24
Finished Oct 15 12:37:59 PM UTC 24
Peak memory 229524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127225539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3127225539
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.3356794620
Short name T500
Test name
Test status
Simulation time 657779404 ps
CPU time 2.48 seconds
Started Oct 15 12:37:45 PM UTC 24
Finished Oct 15 12:37:48 PM UTC 24
Peak memory 227244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356794620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3356794620
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1523139349
Short name T498
Test name
Test status
Simulation time 30592187 ps
CPU time 1.32 seconds
Started Oct 15 12:37:44 PM UTC 24
Finished Oct 15 12:37:46 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523139349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1523139349
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.332217420
Short name T503
Test name
Test status
Simulation time 255057773 ps
CPU time 3.32 seconds
Started Oct 15 12:37:50 PM UTC 24
Finished Oct 15 12:37:54 PM UTC 24
Peak memory 245176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332217420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.332217420
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/18.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.1071005035
Short name T521
Test name
Test status
Simulation time 21466411 ps
CPU time 1.11 seconds
Started Oct 15 12:38:33 PM UTC 24
Finished Oct 15 12:38:35 PM UTC 24
Peak memory 213248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071005035 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.1071005035
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.2884087842
Short name T519
Test name
Test status
Simulation time 605835773 ps
CPU time 10.5 seconds
Started Oct 15 12:38:16 PM UTC 24
Finished Oct 15 12:38:28 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884087842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2884087842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.3102011661
Short name T509
Test name
Test status
Simulation time 124193174 ps
CPU time 1.17 seconds
Started Oct 15 12:38:00 PM UTC 24
Finished Oct 15 12:38:02 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102011661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3102011661
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.3910568541
Short name T240
Test name
Test status
Simulation time 19461677573 ps
CPU time 165.98 seconds
Started Oct 15 12:38:25 PM UTC 24
Finished Oct 15 12:41:14 PM UTC 24
Peak memory 275812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910568541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3910568541
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1994063404
Short name T539
Test name
Test status
Simulation time 10153681158 ps
CPU time 28.59 seconds
Started Oct 15 12:38:27 PM UTC 24
Finished Oct 15 12:38:57 PM UTC 24
Peak memory 229472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994063404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.1994063404
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.1050865271
Short name T517
Test name
Test status
Simulation time 57329983 ps
CPU time 3.18 seconds
Started Oct 15 12:38:18 PM UTC 24
Finished Oct 15 12:38:23 PM UTC 24
Peak memory 234668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050865271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1050865271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1786695435
Short name T250
Test name
Test status
Simulation time 3018466184 ps
CPU time 77.28 seconds
Started Oct 15 12:38:20 PM UTC 24
Finished Oct 15 12:39:39 PM UTC 24
Peak memory 261468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786695435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.1786695435
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.1380921049
Short name T528
Test name
Test status
Simulation time 4506215525 ps
CPU time 30.89 seconds
Started Oct 15 12:38:13 PM UTC 24
Finished Oct 15 12:38:45 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380921049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1380921049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.1723211788
Short name T341
Test name
Test status
Simulation time 2872804529 ps
CPU time 17 seconds
Started Oct 15 12:38:14 PM UTC 24
Finished Oct 15 12:38:32 PM UTC 24
Peak memory 245092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723211788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1723211788
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.4117015143
Short name T511
Test name
Test status
Simulation time 56191012 ps
CPU time 1.57 seconds
Started Oct 15 12:38:03 PM UTC 24
Finished Oct 15 12:38:06 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117015143 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mem_parity.4117015143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.627834337
Short name T518
Test name
Test status
Simulation time 811643191 ps
CPU time 14.25 seconds
Started Oct 15 12:38:10 PM UTC 24
Finished Oct 15 12:38:25 PM UTC 24
Peak memory 261300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627834337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.627834337
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.2110788091
Short name T327
Test name
Test status
Simulation time 2344837106 ps
CPU time 15.48 seconds
Started Oct 15 12:38:10 PM UTC 24
Finished Oct 15 12:38:26 PM UTC 24
Peak memory 234800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110788091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2110788091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1185078994
Short name T526
Test name
Test status
Simulation time 981607654 ps
CPU time 17.39 seconds
Started Oct 15 12:38:24 PM UTC 24
Finished Oct 15 12:38:43 PM UTC 24
Peak memory 231128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185078994 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.1185078994
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.1885109903
Short name T533
Test name
Test status
Simulation time 34590878309 ps
CPU time 42.99 seconds
Started Oct 15 12:38:05 PM UTC 24
Finished Oct 15 12:38:50 PM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885109903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1885109903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.745705948
Short name T514
Test name
Test status
Simulation time 23710625363 ps
CPU time 8.68 seconds
Started Oct 15 12:38:03 PM UTC 24
Finished Oct 15 12:38:13 PM UTC 24
Peak memory 229436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745705948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.745705948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.3068354298
Short name T513
Test name
Test status
Simulation time 67103306 ps
CPU time 2.03 seconds
Started Oct 15 12:38:08 PM UTC 24
Finished Oct 15 12:38:12 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068354298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3068354298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.1207906986
Short name T512
Test name
Test status
Simulation time 464365590 ps
CPU time 1.39 seconds
Started Oct 15 12:38:06 PM UTC 24
Finished Oct 15 12:38:09 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207906986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1207906986
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.1644623236
Short name T520
Test name
Test status
Simulation time 2372398058 ps
CPU time 18.49 seconds
Started Oct 15 12:38:14 PM UTC 24
Finished Oct 15 12:38:34 PM UTC 24
Peak memory 245288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644623236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1644623236
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/19.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.2023606469
Short name T94
Test name
Test status
Simulation time 16179656 ps
CPU time 1.17 seconds
Started Oct 15 12:28:47 PM UTC 24
Finished Oct 15 12:28:49 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023606469 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2023606469
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3100354086
Short name T103
Test name
Test status
Simulation time 147919976 ps
CPU time 4.88 seconds
Started Oct 15 12:28:31 PM UTC 24
Finished Oct 15 12:28:37 PM UTC 24
Peak memory 244896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100354086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3100354086
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2193729811
Short name T27
Test name
Test status
Simulation time 84790205 ps
CPU time 1.08 seconds
Started Oct 15 12:28:16 PM UTC 24
Finished Oct 15 12:28:19 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193729811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2193729811
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.1126037731
Short name T49
Test name
Test status
Simulation time 27020389249 ps
CPU time 219.7 seconds
Started Oct 15 12:28:38 PM UTC 24
Finished Oct 15 12:32:21 PM UTC 24
Peak memory 273712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126037731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1126037731
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1961547906
Short name T51
Test name
Test status
Simulation time 10628352401 ps
CPU time 110.02 seconds
Started Oct 15 12:28:39 PM UTC 24
Finished Oct 15 12:30:31 PM UTC 24
Peak memory 267680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961547906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1961547906
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.207301345
Short name T53
Test name
Test status
Simulation time 3144281572 ps
CPU time 10.4 seconds
Started Oct 15 12:28:33 PM UTC 24
Finished Oct 15 12:28:44 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207301345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.207301345
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2553149113
Short name T293
Test name
Test status
Simulation time 122846603570 ps
CPU time 379.83 seconds
Started Oct 15 12:28:35 PM UTC 24
Finished Oct 15 12:35:00 PM UTC 24
Peak memory 265772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553149113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.2553149113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.2621391345
Short name T106
Test name
Test status
Simulation time 17739958842 ps
CPU time 26.25 seconds
Started Oct 15 12:28:25 PM UTC 24
Finished Oct 15 12:28:53 PM UTC 24
Peak memory 234860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621391345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2621391345
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.471559481
Short name T109
Test name
Test status
Simulation time 51660433142 ps
CPU time 116.28 seconds
Started Oct 15 12:28:26 PM UTC 24
Finished Oct 15 12:30:25 PM UTC 24
Peak memory 244980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471559481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.471559481
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.610735545
Short name T44
Test name
Test status
Simulation time 35266864 ps
CPU time 1.7 seconds
Started Oct 15 12:28:19 PM UTC 24
Finished Oct 15 12:28:21 PM UTC 24
Peak memory 228996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610735545 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_parity.610735545
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3219004228
Short name T56
Test name
Test status
Simulation time 286645386 ps
CPU time 7.55 seconds
Started Oct 15 12:28:25 PM UTC 24
Finished Oct 15 12:28:34 PM UTC 24
Peak memory 251068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219004228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.3219004228
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1438334698
Short name T64
Test name
Test status
Simulation time 242010629 ps
CPU time 4.47 seconds
Started Oct 15 12:28:24 PM UTC 24
Finished Oct 15 12:28:30 PM UTC 24
Peak memory 234976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438334698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1438334698
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2519713505
Short name T47
Test name
Test status
Simulation time 154296547 ps
CPU time 6.41 seconds
Started Oct 15 12:28:35 PM UTC 24
Finished Oct 15 12:28:42 PM UTC 24
Peak memory 233508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519713505 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.2519713505
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.2439607259
Short name T24
Test name
Test status
Simulation time 39593730 ps
CPU time 1.64 seconds
Started Oct 15 12:28:45 PM UTC 24
Finished Oct 15 12:28:48 PM UTC 24
Peak memory 256916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439607259 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2439607259
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.3213070227
Short name T23
Test name
Test status
Simulation time 39944505 ps
CPU time 1.49 seconds
Started Oct 15 12:28:44 PM UTC 24
Finished Oct 15 12:28:47 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213070227 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.3213070227
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.4132849831
Short name T30
Test name
Test status
Simulation time 612913111 ps
CPU time 10.01 seconds
Started Oct 15 12:28:20 PM UTC 24
Finished Oct 15 12:28:31 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132849831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4132849831
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3545677186
Short name T31
Test name
Test status
Simulation time 3080621086 ps
CPU time 13.65 seconds
Started Oct 15 12:28:19 PM UTC 24
Finished Oct 15 12:28:33 PM UTC 24
Peak memory 227364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545677186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3545677186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1379983380
Short name T29
Test name
Test status
Simulation time 37026130 ps
CPU time 1.65 seconds
Started Oct 15 12:28:22 PM UTC 24
Finished Oct 15 12:28:25 PM UTC 24
Peak memory 216056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379983380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1379983380
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2289971671
Short name T28
Test name
Test status
Simulation time 33231385 ps
CPU time 1.24 seconds
Started Oct 15 12:28:21 PM UTC 24
Finished Oct 15 12:28:23 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289971671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2289971671
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.283938177
Short name T60
Test name
Test status
Simulation time 3516506989 ps
CPU time 15.43 seconds
Started Oct 15 12:28:30 PM UTC 24
Finished Oct 15 12:28:47 PM UTC 24
Peak memory 235116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283938177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.283938177
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/2.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.315132405
Short name T537
Test name
Test status
Simulation time 12798781 ps
CPU time 1.08 seconds
Started Oct 15 12:38:52 PM UTC 24
Finished Oct 15 12:38:54 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315132405 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.315132405
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.2563579683
Short name T536
Test name
Test status
Simulation time 1261915460 ps
CPU time 6.97 seconds
Started Oct 15 12:38:46 PM UTC 24
Finished Oct 15 12:38:54 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563579683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2563579683
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.1122727118
Short name T522
Test name
Test status
Simulation time 14693646 ps
CPU time 1.08 seconds
Started Oct 15 12:38:33 PM UTC 24
Finished Oct 15 12:38:35 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122727118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1122727118
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.927961258
Short name T551
Test name
Test status
Simulation time 20155451539 ps
CPU time 43.74 seconds
Started Oct 15 12:38:48 PM UTC 24
Finished Oct 15 12:39:34 PM UTC 24
Peak memory 251428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927961258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.927961258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3463142359
Short name T626
Test name
Test status
Simulation time 18699743926 ps
CPU time 198.14 seconds
Started Oct 15 12:38:48 PM UTC 24
Finished Oct 15 12:42:10 PM UTC 24
Peak memory 277900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463142359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3463142359
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.912875802
Short name T279
Test name
Test status
Simulation time 39967122992 ps
CPU time 432.13 seconds
Started Oct 15 12:38:49 PM UTC 24
Finished Oct 15 12:46:06 PM UTC 24
Peak memory 265568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912875802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.912875802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.4272058676
Short name T548
Test name
Test status
Simulation time 2818603209 ps
CPU time 35.83 seconds
Started Oct 15 12:38:46 PM UTC 24
Finished Oct 15 12:39:23 PM UTC 24
Peak memory 261408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272058676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4272058676
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1851937196
Short name T268
Test name
Test status
Simulation time 64280350975 ps
CPU time 400.93 seconds
Started Oct 15 12:38:47 PM UTC 24
Finished Oct 15 12:45:33 PM UTC 24
Peak memory 281892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851937196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.1851937196
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.1956842992
Short name T529
Test name
Test status
Simulation time 595961915 ps
CPU time 3.42 seconds
Started Oct 15 12:38:41 PM UTC 24
Finished Oct 15 12:38:45 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956842992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1956842992
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.2321131760
Short name T531
Test name
Test status
Simulation time 62930568 ps
CPU time 2.7 seconds
Started Oct 15 12:38:43 PM UTC 24
Finished Oct 15 12:38:47 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321131760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2321131760
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.1802198788
Short name T527
Test name
Test status
Simulation time 128424892 ps
CPU time 3.08 seconds
Started Oct 15 12:38:39 PM UTC 24
Finished Oct 15 12:38:43 PM UTC 24
Peak memory 244640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802198788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.1802198788
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.4192485405
Short name T530
Test name
Test status
Simulation time 1372413580 ps
CPU time 7 seconds
Started Oct 15 12:38:38 PM UTC 24
Finished Oct 15 12:38:46 PM UTC 24
Peak memory 247260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192485405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4192485405
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3084240805
Short name T535
Test name
Test status
Simulation time 295170475 ps
CPU time 3.62 seconds
Started Oct 15 12:38:47 PM UTC 24
Finished Oct 15 12:38:52 PM UTC 24
Peak memory 231132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084240805 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.3084240805
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.2104426400
Short name T633
Test name
Test status
Simulation time 19900112275 ps
CPU time 207.68 seconds
Started Oct 15 12:38:51 PM UTC 24
Finished Oct 15 12:42:22 PM UTC 24
Peak memory 261536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104426400 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.2104426400
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.4073349661
Short name T544
Test name
Test status
Simulation time 1491789338 ps
CPU time 32.79 seconds
Started Oct 15 12:38:35 PM UTC 24
Finished Oct 15 12:39:09 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073349661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4073349661
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.2316950016
Short name T532
Test name
Test status
Simulation time 1800058162 ps
CPU time 11.48 seconds
Started Oct 15 12:38:35 PM UTC 24
Finished Oct 15 12:38:48 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316950016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2316950016
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.126838130
Short name T525
Test name
Test status
Simulation time 98496377 ps
CPU time 2.18 seconds
Started Oct 15 12:38:36 PM UTC 24
Finished Oct 15 12:38:40 PM UTC 24
Peak memory 227276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126838130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.126838130
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1646738025
Short name T524
Test name
Test status
Simulation time 48496564 ps
CPU time 0.95 seconds
Started Oct 15 12:38:36 PM UTC 24
Finished Oct 15 12:38:38 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646738025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1646738025
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.3937809878
Short name T534
Test name
Test status
Simulation time 10198127455 ps
CPU time 5.03 seconds
Started Oct 15 12:38:44 PM UTC 24
Finished Oct 15 12:38:50 PM UTC 24
Peak memory 251172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937809878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3937809878
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/20.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.3115580953
Short name T552
Test name
Test status
Simulation time 13749612 ps
CPU time 1.12 seconds
Started Oct 15 12:39:31 PM UTC 24
Finished Oct 15 12:39:34 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115580953 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.3115580953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.3207508780
Short name T547
Test name
Test status
Simulation time 83163839 ps
CPU time 3.44 seconds
Started Oct 15 12:39:14 PM UTC 24
Finished Oct 15 12:39:18 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207508780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3207508780
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.445546973
Short name T538
Test name
Test status
Simulation time 66283673 ps
CPU time 1.21 seconds
Started Oct 15 12:38:53 PM UTC 24
Finished Oct 15 12:38:55 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445546973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.445546973
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.1295410804
Short name T264
Test name
Test status
Simulation time 41497092512 ps
CPU time 311.3 seconds
Started Oct 15 12:39:21 PM UTC 24
Finished Oct 15 12:44:36 PM UTC 24
Peak memory 265504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295410804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1295410804
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1650530592
Short name T294
Test name
Test status
Simulation time 3301984406 ps
CPU time 31.87 seconds
Started Oct 15 12:39:24 PM UTC 24
Finished Oct 15 12:39:57 PM UTC 24
Peak memory 235104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650530592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1650530592
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.113773074
Short name T578
Test name
Test status
Simulation time 3369444632 ps
CPU time 56.24 seconds
Started Oct 15 12:39:26 PM UTC 24
Finished Oct 15 12:40:24 PM UTC 24
Peak memory 261516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113773074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.113773074
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.2113114863
Short name T555
Test name
Test status
Simulation time 1305213631 ps
CPU time 23.3 seconds
Started Oct 15 12:39:17 PM UTC 24
Finished Oct 15 12:39:42 PM UTC 24
Peak memory 234972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113114863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2113114863
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3240491000
Short name T559
Test name
Test status
Simulation time 4417961810 ps
CPU time 31.58 seconds
Started Oct 15 12:39:19 PM UTC 24
Finished Oct 15 12:39:52 PM UTC 24
Peak memory 249124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240491000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.3240491000
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.4287965054
Short name T543
Test name
Test status
Simulation time 83081717 ps
CPU time 3.57 seconds
Started Oct 15 12:39:04 PM UTC 24
Finished Oct 15 12:39:09 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287965054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4287965054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.3651427314
Short name T330
Test name
Test status
Simulation time 650833075 ps
CPU time 18.85 seconds
Started Oct 15 12:39:10 PM UTC 24
Finished Oct 15 12:39:30 PM UTC 24
Peak memory 234724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651427314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3651427314
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.299727753
Short name T338
Test name
Test status
Simulation time 47989434421 ps
CPU time 33.13 seconds
Started Oct 15 12:39:03 PM UTC 24
Finished Oct 15 12:39:38 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299727753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.299727753
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.2456173365
Short name T550
Test name
Test status
Simulation time 40514382606 ps
CPU time 30.64 seconds
Started Oct 15 12:39:00 PM UTC 24
Finished Oct 15 12:39:32 PM UTC 24
Peak memory 251440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456173365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2456173365
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.277778070
Short name T549
Test name
Test status
Simulation time 1437692558 ps
CPU time 4.8 seconds
Started Oct 15 12:39:19 PM UTC 24
Finished Oct 15 12:39:25 PM UTC 24
Peak memory 233372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277778070 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.277778070
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.479430842
Short name T604
Test name
Test status
Simulation time 10536804740 ps
CPU time 108.59 seconds
Started Oct 15 12:39:30 PM UTC 24
Finished Oct 15 12:41:21 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479430842 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.479430842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.369953694
Short name T545
Test name
Test status
Simulation time 2897048255 ps
CPU time 16.68 seconds
Started Oct 15 12:38:55 PM UTC 24
Finished Oct 15 12:39:13 PM UTC 24
Peak memory 227404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369953694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.369953694
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2657584066
Short name T546
Test name
Test status
Simulation time 8290485576 ps
CPU time 20.48 seconds
Started Oct 15 12:38:54 PM UTC 24
Finished Oct 15 12:39:16 PM UTC 24
Peak memory 227440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657584066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2657584066
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.1460410778
Short name T542
Test name
Test status
Simulation time 770486532 ps
CPU time 2.72 seconds
Started Oct 15 12:38:58 PM UTC 24
Finished Oct 15 12:39:02 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460410778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1460410778
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.3091055235
Short name T540
Test name
Test status
Simulation time 106647208 ps
CPU time 1.34 seconds
Started Oct 15 12:38:57 PM UTC 24
Finished Oct 15 12:38:59 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091055235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3091055235
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.2488882083
Short name T324
Test name
Test status
Simulation time 680729635 ps
CPU time 7.44 seconds
Started Oct 15 12:39:11 PM UTC 24
Finished Oct 15 12:39:19 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488882083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2488882083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/21.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.3764249416
Short name T566
Test name
Test status
Simulation time 12836520 ps
CPU time 1.14 seconds
Started Oct 15 12:40:00 PM UTC 24
Finished Oct 15 12:40:03 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764249416 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.3764249416
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.3784591793
Short name T561
Test name
Test status
Simulation time 128580077 ps
CPU time 2.9 seconds
Started Oct 15 12:39:50 PM UTC 24
Finished Oct 15 12:39:54 PM UTC 24
Peak memory 234848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784591793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3784591793
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.1464313408
Short name T553
Test name
Test status
Simulation time 23773161 ps
CPU time 1.29 seconds
Started Oct 15 12:39:33 PM UTC 24
Finished Oct 15 12:39:35 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464313408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1464313408
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.2388712327
Short name T247
Test name
Test status
Simulation time 9471988346 ps
CPU time 97.09 seconds
Started Oct 15 12:39:55 PM UTC 24
Finished Oct 15 12:41:34 PM UTC 24
Peak memory 263460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388712327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2388712327
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2732959403
Short name T215
Test name
Test status
Simulation time 20275587313 ps
CPU time 251.79 seconds
Started Oct 15 12:39:56 PM UTC 24
Finished Oct 15 12:44:12 PM UTC 24
Peak memory 273764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732959403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2732959403
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.1866309329
Short name T621
Test name
Test status
Simulation time 38464677761 ps
CPU time 121.58 seconds
Started Oct 15 12:39:56 PM UTC 24
Finished Oct 15 12:42:00 PM UTC 24
Peak memory 251216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866309329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.1866309329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.579437961
Short name T564
Test name
Test status
Simulation time 72307439 ps
CPU time 6.68 seconds
Started Oct 15 12:39:53 PM UTC 24
Finished Oct 15 12:40:00 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579437961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.579437961
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.297881447
Short name T591
Test name
Test status
Simulation time 6953386195 ps
CPU time 52.55 seconds
Started Oct 15 12:39:54 PM UTC 24
Finished Oct 15 12:40:48 PM UTC 24
Peak memory 265768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297881447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.297881447
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.2639291437
Short name T558
Test name
Test status
Simulation time 176109286 ps
CPU time 7.36 seconds
Started Oct 15 12:39:43 PM UTC 24
Finished Oct 15 12:39:52 PM UTC 24
Peak memory 245160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639291437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2639291437
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.413139256
Short name T569
Test name
Test status
Simulation time 4759182727 ps
CPU time 19.18 seconds
Started Oct 15 12:39:46 PM UTC 24
Finished Oct 15 12:40:07 PM UTC 24
Peak memory 234848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413139256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.413139256
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.896663331
Short name T188
Test name
Test status
Simulation time 11984556335 ps
CPU time 12.84 seconds
Started Oct 15 12:39:41 PM UTC 24
Finished Oct 15 12:39:55 PM UTC 24
Peak memory 234808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896663331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.896663331
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.2128795729
Short name T557
Test name
Test status
Simulation time 277655613 ps
CPU time 4.15 seconds
Started Oct 15 12:39:39 PM UTC 24
Finished Oct 15 12:39:45 PM UTC 24
Peak memory 234912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128795729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2128795729
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.238043210
Short name T576
Test name
Test status
Simulation time 1401531437 ps
CPU time 22.63 seconds
Started Oct 15 12:39:54 PM UTC 24
Finished Oct 15 12:40:18 PM UTC 24
Peak memory 233256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238043210 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.238043210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.1534114523
Short name T364
Test name
Test status
Simulation time 2061225489 ps
CPU time 25.89 seconds
Started Oct 15 12:39:35 PM UTC 24
Finished Oct 15 12:40:02 PM UTC 24
Peak memory 231364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534114523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1534114523
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.4170869949
Short name T562
Test name
Test status
Simulation time 4346334416 ps
CPU time 18.49 seconds
Started Oct 15 12:39:35 PM UTC 24
Finished Oct 15 12:39:55 PM UTC 24
Peak memory 227448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170869949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4170869949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.4108833281
Short name T556
Test name
Test status
Simulation time 544937767 ps
CPU time 4.69 seconds
Started Oct 15 12:39:38 PM UTC 24
Finished Oct 15 12:39:45 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108833281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4108833281
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3289266784
Short name T554
Test name
Test status
Simulation time 62431975 ps
CPU time 1.32 seconds
Started Oct 15 12:39:36 PM UTC 24
Finished Oct 15 12:39:39 PM UTC 24
Peak memory 216516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289266784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3289266784
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.1413839715
Short name T565
Test name
Test status
Simulation time 4002534497 ps
CPU time 14.04 seconds
Started Oct 15 12:39:46 PM UTC 24
Finished Oct 15 12:40:02 PM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413839715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1413839715
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/22.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.1206430087
Short name T581
Test name
Test status
Simulation time 12995082 ps
CPU time 1.12 seconds
Started Oct 15 12:40:25 PM UTC 24
Finished Oct 15 12:40:28 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206430087 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.1206430087
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.2399178419
Short name T577
Test name
Test status
Simulation time 174622679 ps
CPU time 3.58 seconds
Started Oct 15 12:40:15 PM UTC 24
Finished Oct 15 12:40:19 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399178419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2399178419
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.2928681615
Short name T567
Test name
Test status
Simulation time 23700912 ps
CPU time 1.21 seconds
Started Oct 15 12:40:01 PM UTC 24
Finished Oct 15 12:40:04 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928681615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2928681615
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.517019454
Short name T322
Test name
Test status
Simulation time 3159295925 ps
CPU time 24.09 seconds
Started Oct 15 12:40:16 PM UTC 24
Finished Oct 15 12:40:42 PM UTC 24
Peak memory 251228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517019454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.517019454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.1365410858
Short name T618
Test name
Test status
Simulation time 8960706349 ps
CPU time 92.88 seconds
Started Oct 15 12:40:19 PM UTC 24
Finished Oct 15 12:41:54 PM UTC 24
Peak memory 261480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365410858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1365410858
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.2760326325
Short name T602
Test name
Test status
Simulation time 3122714668 ps
CPU time 54.3 seconds
Started Oct 15 12:40:21 PM UTC 24
Finished Oct 15 12:41:17 PM UTC 24
Peak memory 261536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760326325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.2760326325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.4097339693
Short name T347
Test name
Test status
Simulation time 1077764030 ps
CPU time 20.51 seconds
Started Oct 15 12:40:16 PM UTC 24
Finished Oct 15 12:40:38 PM UTC 24
Peak memory 261288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097339693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4097339693
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.2571585127
Short name T323
Test name
Test status
Simulation time 8266823836 ps
CPU time 69.45 seconds
Started Oct 15 12:40:16 PM UTC 24
Finished Oct 15 12:41:27 PM UTC 24
Peak memory 265504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571585127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.2571585127
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.1095456576
Short name T575
Test name
Test status
Simulation time 355669178 ps
CPU time 5.1 seconds
Started Oct 15 12:40:09 PM UTC 24
Finished Oct 15 12:40:15 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095456576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1095456576
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.2476319824
Short name T580
Test name
Test status
Simulation time 3752911982 ps
CPU time 12.79 seconds
Started Oct 15 12:40:11 PM UTC 24
Finished Oct 15 12:40:25 PM UTC 24
Peak memory 229488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476319824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2476319824
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.3549653388
Short name T309
Test name
Test status
Simulation time 1237757569 ps
CPU time 5.4 seconds
Started Oct 15 12:40:08 PM UTC 24
Finished Oct 15 12:40:15 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549653388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.3549653388
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.3902067830
Short name T326
Test name
Test status
Simulation time 325587530 ps
CPU time 5.79 seconds
Started Oct 15 12:40:07 PM UTC 24
Finished Oct 15 12:40:14 PM UTC 24
Peak memory 245168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902067830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3902067830
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2421816004
Short name T579
Test name
Test status
Simulation time 1584582876 ps
CPU time 6.97 seconds
Started Oct 15 12:40:16 PM UTC 24
Finished Oct 15 12:40:24 PM UTC 24
Peak memory 231020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421816004 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.2421816004
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.1142644685
Short name T584
Test name
Test status
Simulation time 3042191753 ps
CPU time 25.57 seconds
Started Oct 15 12:40:03 PM UTC 24
Finished Oct 15 12:40:31 PM UTC 24
Peak memory 227420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142644685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1142644685
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.2078927885
Short name T571
Test name
Test status
Simulation time 463408947 ps
CPU time 4.02 seconds
Started Oct 15 12:40:03 PM UTC 24
Finished Oct 15 12:40:09 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078927885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2078927885
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.1759527013
Short name T572
Test name
Test status
Simulation time 407529976 ps
CPU time 3.88 seconds
Started Oct 15 12:40:05 PM UTC 24
Finished Oct 15 12:40:10 PM UTC 24
Peak memory 227236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759527013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1759527013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.49477208
Short name T568
Test name
Test status
Simulation time 26236653 ps
CPU time 1.1 seconds
Started Oct 15 12:40:04 PM UTC 24
Finished Oct 15 12:40:06 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49477208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.49477208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.554062717
Short name T573
Test name
Test status
Simulation time 113055865 ps
CPU time 2.88 seconds
Started Oct 15 12:40:11 PM UTC 24
Finished Oct 15 12:40:15 PM UTC 24
Peak memory 234624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554062717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.554062717
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/23.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.1478534292
Short name T560
Test name
Test status
Simulation time 41031371 ps
CPU time 1.08 seconds
Started Oct 15 12:40:45 PM UTC 24
Finished Oct 15 12:40:48 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478534292 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.1478534292
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3395151452
Short name T590
Test name
Test status
Simulation time 145767791 ps
CPU time 4.52 seconds
Started Oct 15 12:40:35 PM UTC 24
Finished Oct 15 12:40:41 PM UTC 24
Peak memory 234680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395151452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3395151452
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.3958908291
Short name T582
Test name
Test status
Simulation time 26233373 ps
CPU time 1.2 seconds
Started Oct 15 12:40:25 PM UTC 24
Finished Oct 15 12:40:28 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958908291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3958908291
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.3491676502
Short name T197
Test name
Test status
Simulation time 28029053983 ps
CPU time 231.83 seconds
Started Oct 15 12:40:42 PM UTC 24
Finished Oct 15 12:44:37 PM UTC 24
Peak memory 261668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491676502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3491676502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3914949250
Short name T651
Test name
Test status
Simulation time 6716348810 ps
CPU time 135.23 seconds
Started Oct 15 12:40:43 PM UTC 24
Finished Oct 15 12:43:01 PM UTC 24
Peak memory 267680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914949250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3914949250
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.2939930691
Short name T75
Test name
Test status
Simulation time 63829273183 ps
CPU time 448.92 seconds
Started Oct 15 12:40:43 PM UTC 24
Finished Oct 15 12:48:18 PM UTC 24
Peak memory 277912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939930691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.2939930691
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1335372919
Short name T617
Test name
Test status
Simulation time 14994912966 ps
CPU time 70.02 seconds
Started Oct 15 12:40:39 PM UTC 24
Finished Oct 15 12:41:51 PM UTC 24
Peak memory 263460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335372919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.1335372919
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.3476004171
Short name T570
Test name
Test status
Simulation time 2299460825 ps
CPU time 9.87 seconds
Started Oct 15 12:40:31 PM UTC 24
Finished Oct 15 12:40:42 PM UTC 24
Peak memory 245040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476004171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3476004171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.3016376970
Short name T541
Test name
Test status
Simulation time 1920642614 ps
CPU time 8.33 seconds
Started Oct 15 12:40:33 PM UTC 24
Finished Oct 15 12:40:42 PM UTC 24
Peak memory 234608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016376970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3016376970
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.358244905
Short name T277
Test name
Test status
Simulation time 11438347609 ps
CPU time 12.79 seconds
Started Oct 15 12:40:30 PM UTC 24
Finished Oct 15 12:40:44 PM UTC 24
Peak memory 251172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358244905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.358244905
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.686544880
Short name T587
Test name
Test status
Simulation time 231205319 ps
CPU time 3.61 seconds
Started Oct 15 12:40:29 PM UTC 24
Finished Oct 15 12:40:34 PM UTC 24
Peak memory 245052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686544880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.686544880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.1543820623
Short name T595
Test name
Test status
Simulation time 1566961857 ps
CPU time 13.05 seconds
Started Oct 15 12:40:42 PM UTC 24
Finished Oct 15 12:40:56 PM UTC 24
Peak memory 233484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543820623 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.1543820623
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.1251591050
Short name T41
Test name
Test status
Simulation time 7509569527 ps
CPU time 103.57 seconds
Started Oct 15 12:40:43 PM UTC 24
Finished Oct 15 12:42:29 PM UTC 24
Peak memory 251432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251591050 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.1251591050
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.1983028199
Short name T592
Test name
Test status
Simulation time 58040120901 ps
CPU time 22.57 seconds
Started Oct 15 12:40:27 PM UTC 24
Finished Oct 15 12:40:51 PM UTC 24
Peak memory 227692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983028199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1983028199
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1241440320
Short name T589
Test name
Test status
Simulation time 6058887311 ps
CPU time 13.29 seconds
Started Oct 15 12:40:25 PM UTC 24
Finished Oct 15 12:40:40 PM UTC 24
Peak memory 227712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241440320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1241440320
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.2662859955
Short name T585
Test name
Test status
Simulation time 263756469 ps
CPU time 1.15 seconds
Started Oct 15 12:40:29 PM UTC 24
Finished Oct 15 12:40:31 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662859955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2662859955
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.3877958193
Short name T583
Test name
Test status
Simulation time 43994827 ps
CPU time 1.37 seconds
Started Oct 15 12:40:27 PM UTC 24
Finished Oct 15 12:40:29 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877958193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3877958193
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.403067570
Short name T588
Test name
Test status
Simulation time 114913452 ps
CPU time 3.13 seconds
Started Oct 15 12:40:33 PM UTC 24
Finished Oct 15 12:40:37 PM UTC 24
Peak memory 234596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403067570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.403067570
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/24.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.2740978558
Short name T607
Test name
Test status
Simulation time 66973300 ps
CPU time 1.01 seconds
Started Oct 15 12:41:23 PM UTC 24
Finished Oct 15 12:41:25 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740978558 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.2740978558
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.1129554513
Short name T601
Test name
Test status
Simulation time 105781986 ps
CPU time 3.28 seconds
Started Oct 15 12:41:08 PM UTC 24
Finished Oct 15 12:41:12 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129554513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1129554513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.429357448
Short name T593
Test name
Test status
Simulation time 21397224 ps
CPU time 1.1 seconds
Started Oct 15 12:40:49 PM UTC 24
Finished Oct 15 12:40:51 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429357448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.429357448
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.1279335448
Short name T643
Test name
Test status
Simulation time 9768963089 ps
CPU time 78.88 seconds
Started Oct 15 12:41:18 PM UTC 24
Finished Oct 15 12:42:38 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279335448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1279335448
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3180340816
Short name T253
Test name
Test status
Simulation time 7127803827 ps
CPU time 123.21 seconds
Started Oct 15 12:41:19 PM UTC 24
Finished Oct 15 12:43:24 PM UTC 24
Peak memory 265572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180340816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3180340816
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.2337272225
Short name T644
Test name
Test status
Simulation time 47443097491 ps
CPU time 77.08 seconds
Started Oct 15 12:41:21 PM UTC 24
Finished Oct 15 12:42:40 PM UTC 24
Peak memory 244564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337272225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.2337272225
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2174077155
Short name T275
Test name
Test status
Simulation time 24985044770 ps
CPU time 88.13 seconds
Started Oct 15 12:41:13 PM UTC 24
Finished Oct 15 12:42:43 PM UTC 24
Peak memory 265572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174077155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.2174077155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.3214438421
Short name T599
Test name
Test status
Simulation time 110321739 ps
CPU time 3.35 seconds
Started Oct 15 12:41:02 PM UTC 24
Finished Oct 15 12:41:07 PM UTC 24
Peak memory 244964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214438421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3214438421
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.3244663361
Short name T603
Test name
Test status
Simulation time 878379801 ps
CPU time 10.82 seconds
Started Oct 15 12:41:05 PM UTC 24
Finished Oct 15 12:41:17 PM UTC 24
Peak memory 263332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244663361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3244663361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1356853840
Short name T606
Test name
Test status
Simulation time 34548393582 ps
CPU time 21.19 seconds
Started Oct 15 12:41:01 PM UTC 24
Finished Oct 15 12:41:24 PM UTC 24
Peak memory 235124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356853840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.1356853840
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2547044316
Short name T598
Test name
Test status
Simulation time 3880911832 ps
CPU time 8.7 seconds
Started Oct 15 12:40:57 PM UTC 24
Finished Oct 15 12:41:07 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547044316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2547044316
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.1650983058
Short name T605
Test name
Test status
Simulation time 172141810 ps
CPU time 6.28 seconds
Started Oct 15 12:41:14 PM UTC 24
Finished Oct 15 12:41:22 PM UTC 24
Peak memory 231072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650983058 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.1650983058
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.1537005975
Short name T73
Test name
Test status
Simulation time 13086588866 ps
CPU time 198.46 seconds
Started Oct 15 12:41:22 PM UTC 24
Finished Oct 15 12:44:44 PM UTC 24
Peak memory 261472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537005975 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.1537005975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.983831021
Short name T600
Test name
Test status
Simulation time 4712490006 ps
CPU time 17.52 seconds
Started Oct 15 12:40:52 PM UTC 24
Finished Oct 15 12:41:11 PM UTC 24
Peak memory 229464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983831021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.983831021
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.2107793474
Short name T597
Test name
Test status
Simulation time 1614386157 ps
CPU time 14.99 seconds
Started Oct 15 12:40:49 PM UTC 24
Finished Oct 15 12:41:05 PM UTC 24
Peak memory 227276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107793474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2107793474
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.3832941187
Short name T596
Test name
Test status
Simulation time 541628115 ps
CPU time 5.01 seconds
Started Oct 15 12:40:55 PM UTC 24
Finished Oct 15 12:41:02 PM UTC 24
Peak memory 227592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832941187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3832941187
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.2921100975
Short name T594
Test name
Test status
Simulation time 42164297 ps
CPU time 1.37 seconds
Started Oct 15 12:40:52 PM UTC 24
Finished Oct 15 12:40:55 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921100975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2921100975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.209104111
Short name T609
Test name
Test status
Simulation time 2047646371 ps
CPU time 21.47 seconds
Started Oct 15 12:41:08 PM UTC 24
Finished Oct 15 12:41:31 PM UTC 24
Peak memory 244852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209104111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.209104111
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/25.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.2974363090
Short name T622
Test name
Test status
Simulation time 11202773 ps
CPU time 1.12 seconds
Started Oct 15 12:42:00 PM UTC 24
Finished Oct 15 12:42:03 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974363090 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.2974363090
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1619171165
Short name T624
Test name
Test status
Simulation time 1553128767 ps
CPU time 20.79 seconds
Started Oct 15 12:41:43 PM UTC 24
Finished Oct 15 12:42:06 PM UTC 24
Peak memory 245220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619171165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1619171165
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.1475943825
Short name T608
Test name
Test status
Simulation time 14336484 ps
CPU time 1.16 seconds
Started Oct 15 12:41:24 PM UTC 24
Finished Oct 15 12:41:27 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475943825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1475943825
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.618912606
Short name T812
Test name
Test status
Simulation time 123657117536 ps
CPU time 335.71 seconds
Started Oct 15 12:41:52 PM UTC 24
Finished Oct 15 12:47:33 PM UTC 24
Peak memory 267556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618912606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.618912606
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3627816953
Short name T337
Test name
Test status
Simulation time 17573548979 ps
CPU time 70.85 seconds
Started Oct 15 12:41:52 PM UTC 24
Finished Oct 15 12:43:05 PM UTC 24
Peak memory 251512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627816953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3627816953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2912029051
Short name T625
Test name
Test status
Simulation time 5787780837 ps
CPU time 13.68 seconds
Started Oct 15 12:41:55 PM UTC 24
Finished Oct 15 12:42:10 PM UTC 24
Peak memory 229472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912029051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.2912029051
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.250367336
Short name T616
Test name
Test status
Simulation time 278851064 ps
CPU time 3.57 seconds
Started Oct 15 12:41:46 PM UTC 24
Finished Oct 15 12:41:51 PM UTC 24
Peak memory 234676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250367336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.250367336
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.189318805
Short name T620
Test name
Test status
Simulation time 833236083 ps
CPU time 10.15 seconds
Started Oct 15 12:41:48 PM UTC 24
Finished Oct 15 12:41:59 PM UTC 24
Peak memory 249000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189318805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.189318805
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.1690419101
Short name T305
Test name
Test status
Simulation time 520953078 ps
CPU time 9.91 seconds
Started Oct 15 12:41:36 PM UTC 24
Finished Oct 15 12:41:47 PM UTC 24
Peak memory 234660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690419101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1690419101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.4177195490
Short name T632
Test name
Test status
Simulation time 22445836318 ps
CPU time 40.5 seconds
Started Oct 15 12:41:36 PM UTC 24
Finished Oct 15 12:42:18 PM UTC 24
Peak memory 251176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177195490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4177195490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.539921139
Short name T613
Test name
Test status
Simulation time 1030042118 ps
CPU time 6.17 seconds
Started Oct 15 12:41:35 PM UTC 24
Finished Oct 15 12:41:42 PM UTC 24
Peak memory 244856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539921139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.539921139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.590926045
Short name T300
Test name
Test status
Simulation time 5344072224 ps
CPU time 11.04 seconds
Started Oct 15 12:41:33 PM UTC 24
Finished Oct 15 12:41:45 PM UTC 24
Peak memory 245024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590926045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.590926045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.3013660965
Short name T619
Test name
Test status
Simulation time 682096923 ps
CPU time 6.12 seconds
Started Oct 15 12:41:51 PM UTC 24
Finished Oct 15 12:41:58 PM UTC 24
Peak memory 231328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013660965 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.3013660965
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.1549132929
Short name T249
Test name
Test status
Simulation time 16487071641 ps
CPU time 103.69 seconds
Started Oct 15 12:41:59 PM UTC 24
Finished Oct 15 12:43:45 PM UTC 24
Peak memory 261480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549132929 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.1549132929
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.3024587820
Short name T614
Test name
Test status
Simulation time 850322592 ps
CPU time 13.58 seconds
Started Oct 15 12:41:28 PM UTC 24
Finished Oct 15 12:41:43 PM UTC 24
Peak memory 227244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024587820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3024587820
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1580790602
Short name T611
Test name
Test status
Simulation time 14431440062 ps
CPU time 7.25 seconds
Started Oct 15 12:41:27 PM UTC 24
Finished Oct 15 12:41:35 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580790602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1580790602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.1037910850
Short name T612
Test name
Test status
Simulation time 2438621013 ps
CPU time 3.17 seconds
Started Oct 15 12:41:31 PM UTC 24
Finished Oct 15 12:41:36 PM UTC 24
Peak memory 227628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037910850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1037910850
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.1948434989
Short name T610
Test name
Test status
Simulation time 21913397 ps
CPU time 1.16 seconds
Started Oct 15 12:41:29 PM UTC 24
Finished Oct 15 12:41:31 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948434989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1948434989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.572302602
Short name T615
Test name
Test status
Simulation time 342316809 ps
CPU time 5.36 seconds
Started Oct 15 12:41:43 PM UTC 24
Finished Oct 15 12:41:50 PM UTC 24
Peak memory 245224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572302602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.572302602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/26.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.1339322317
Short name T636
Test name
Test status
Simulation time 13929841 ps
CPU time 1.13 seconds
Started Oct 15 12:42:26 PM UTC 24
Finished Oct 15 12:42:29 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339322317 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.1339322317
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.710236139
Short name T631
Test name
Test status
Simulation time 163598030 ps
CPU time 3.23 seconds
Started Oct 15 12:42:13 PM UTC 24
Finished Oct 15 12:42:17 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710236139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.710236139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.3868506294
Short name T623
Test name
Test status
Simulation time 85342723 ps
CPU time 1.16 seconds
Started Oct 15 12:42:01 PM UTC 24
Finished Oct 15 12:42:04 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868506294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3868506294
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.3095790401
Short name T674
Test name
Test status
Simulation time 4524651473 ps
CPU time 70.9 seconds
Started Oct 15 12:42:22 PM UTC 24
Finished Oct 15 12:43:34 PM UTC 24
Peak memory 261420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095790401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3095790401
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1256907969
Short name T231
Test name
Test status
Simulation time 4501893664 ps
CPU time 86.61 seconds
Started Oct 15 12:42:22 PM UTC 24
Finished Oct 15 12:43:50 PM UTC 24
Peak memory 261856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256907969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1256907969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.265698530
Short name T76
Test name
Test status
Simulation time 77097181832 ps
CPU time 421.44 seconds
Started Oct 15 12:42:23 PM UTC 24
Finished Oct 15 12:49:30 PM UTC 24
Peak memory 283996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265698530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.265698530
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.2501823044
Short name T635
Test name
Test status
Simulation time 152142892 ps
CPU time 7.9 seconds
Started Oct 15 12:42:18 PM UTC 24
Finished Oct 15 12:42:27 PM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501823044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2501823044
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3320571426
Short name T671
Test name
Test status
Simulation time 14965481808 ps
CPU time 72.36 seconds
Started Oct 15 12:42:18 PM UTC 24
Finished Oct 15 12:43:32 PM UTC 24
Peak memory 261404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320571426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.3320571426
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.3709731365
Short name T630
Test name
Test status
Simulation time 1581040136 ps
CPU time 5.29 seconds
Started Oct 15 12:42:11 PM UTC 24
Finished Oct 15 12:42:17 PM UTC 24
Peak memory 234980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709731365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3709731365
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.2437301024
Short name T670
Test name
Test status
Simulation time 18709371176 ps
CPU time 78.26 seconds
Started Oct 15 12:42:11 PM UTC 24
Finished Oct 15 12:43:31 PM UTC 24
Peak memory 250980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437301024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2437301024
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.1308028038
Short name T269
Test name
Test status
Simulation time 8319275343 ps
CPU time 9 seconds
Started Oct 15 12:42:11 PM UTC 24
Finished Oct 15 12:42:21 PM UTC 24
Peak memory 247072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308028038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.1308028038
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3697271118
Short name T241
Test name
Test status
Simulation time 9423169013 ps
CPU time 18.21 seconds
Started Oct 15 12:42:07 PM UTC 24
Finished Oct 15 12:42:26 PM UTC 24
Peak memory 245344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697271118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3697271118
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.1692769425
Short name T640
Test name
Test status
Simulation time 3416808236 ps
CPU time 13.27 seconds
Started Oct 15 12:42:19 PM UTC 24
Finished Oct 15 12:42:34 PM UTC 24
Peak memory 233288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692769425 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.1692769425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1496940746
Short name T634
Test name
Test status
Simulation time 49500266 ps
CPU time 1.62 seconds
Started Oct 15 12:42:23 PM UTC 24
Finished Oct 15 12:42:26 PM UTC 24
Peak memory 216348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496940746 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.1496940746
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.3665003379
Short name T629
Test name
Test status
Simulation time 3224933666 ps
CPU time 5.7 seconds
Started Oct 15 12:42:05 PM UTC 24
Finished Oct 15 12:42:12 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665003379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3665003379
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.4203747310
Short name T639
Test name
Test status
Simulation time 33644936303 ps
CPU time 28.1 seconds
Started Oct 15 12:42:03 PM UTC 24
Finished Oct 15 12:42:33 PM UTC 24
Peak memory 227592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203747310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4203747310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3676957434
Short name T628
Test name
Test status
Simulation time 169963759 ps
CPU time 1.72 seconds
Started Oct 15 12:42:07 PM UTC 24
Finished Oct 15 12:42:10 PM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676957434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3676957434
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.835699649
Short name T627
Test name
Test status
Simulation time 94095377 ps
CPU time 1.6 seconds
Started Oct 15 12:42:07 PM UTC 24
Finished Oct 15 12:42:10 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835699649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.835699649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.3978779523
Short name T304
Test name
Test status
Simulation time 7651602099 ps
CPU time 9.68 seconds
Started Oct 15 12:42:11 PM UTC 24
Finished Oct 15 12:42:22 PM UTC 24
Peak memory 245092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978779523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3978779523
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/27.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.2237525329
Short name T654
Test name
Test status
Simulation time 32811725 ps
CPU time 1.07 seconds
Started Oct 15 12:43:01 PM UTC 24
Finished Oct 15 12:43:03 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237525329 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.2237525329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.3614457361
Short name T645
Test name
Test status
Simulation time 257853869 ps
CPU time 4.86 seconds
Started Oct 15 12:42:39 PM UTC 24
Finished Oct 15 12:42:45 PM UTC 24
Peak memory 244772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614457361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3614457361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.2285015487
Short name T637
Test name
Test status
Simulation time 127575021 ps
CPU time 1.16 seconds
Started Oct 15 12:42:27 PM UTC 24
Finished Oct 15 12:42:30 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285015487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2285015487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.895170575
Short name T668
Test name
Test status
Simulation time 17515762317 ps
CPU time 42.48 seconds
Started Oct 15 12:42:46 PM UTC 24
Finished Oct 15 12:43:30 PM UTC 24
Peak memory 249120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895170575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.895170575
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.666674608
Short name T1010
Test name
Test status
Simulation time 65867399024 ps
CPU time 617.41 seconds
Started Oct 15 12:42:51 PM UTC 24
Finished Oct 15 12:53:16 PM UTC 24
Peak memory 277832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666674608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.666674608
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1846341300
Short name T780
Test name
Test status
Simulation time 36665175961 ps
CPU time 199.75 seconds
Started Oct 15 12:42:57 PM UTC 24
Finished Oct 15 12:46:21 PM UTC 24
Peak memory 261788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846341300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.1846341300
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.228751044
Short name T656
Test name
Test status
Simulation time 7585171232 ps
CPU time 22.69 seconds
Started Oct 15 12:42:40 PM UTC 24
Finished Oct 15 12:43:05 PM UTC 24
Peak memory 245244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228751044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.228751044
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.866419425
Short name T254
Test name
Test status
Simulation time 4995121225 ps
CPU time 111.22 seconds
Started Oct 15 12:42:41 PM UTC 24
Finished Oct 15 12:44:34 PM UTC 24
Peak memory 283940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866419425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.866419425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.2792937581
Short name T647
Test name
Test status
Simulation time 8049729082 ps
CPU time 20.01 seconds
Started Oct 15 12:42:35 PM UTC 24
Finished Oct 15 12:42:56 PM UTC 24
Peak memory 235000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792937581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2792937581
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.2592087845
Short name T652
Test name
Test status
Simulation time 2194362898 ps
CPU time 24.94 seconds
Started Oct 15 12:42:35 PM UTC 24
Finished Oct 15 12:43:01 PM UTC 24
Peak memory 247160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592087845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2592087845
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3912306901
Short name T257
Test name
Test status
Simulation time 9725631016 ps
CPU time 35.37 seconds
Started Oct 15 12:42:35 PM UTC 24
Finished Oct 15 12:43:12 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912306901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.3912306901
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.432534274
Short name T642
Test name
Test status
Simulation time 432086294 ps
CPU time 3.63 seconds
Started Oct 15 12:42:33 PM UTC 24
Finished Oct 15 12:42:38 PM UTC 24
Peak memory 234728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432534274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.432534274
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.605392599
Short name T648
Test name
Test status
Simulation time 1341316396 ps
CPU time 12.85 seconds
Started Oct 15 12:42:45 PM UTC 24
Finished Oct 15 12:42:59 PM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605392599 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.605392599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.4272653235
Short name T263
Test name
Test status
Simulation time 12308664996 ps
CPU time 172.4 seconds
Started Oct 15 12:43:00 PM UTC 24
Finished Oct 15 12:45:55 PM UTC 24
Peak memory 280284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272653235 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.4272653235
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.816653518
Short name T649
Test name
Test status
Simulation time 2089077557 ps
CPU time 28.61 seconds
Started Oct 15 12:42:30 PM UTC 24
Finished Oct 15 12:43:00 PM UTC 24
Peak memory 231356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816653518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.816653518
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.2570328553
Short name T646
Test name
Test status
Simulation time 2567654519 ps
CPU time 19.94 seconds
Started Oct 15 12:42:29 PM UTC 24
Finished Oct 15 12:42:50 PM UTC 24
Peak memory 227716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570328553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2570328553
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.4063106602
Short name T641
Test name
Test status
Simulation time 103173716 ps
CPU time 1.56 seconds
Started Oct 15 12:42:31 PM UTC 24
Finished Oct 15 12:42:34 PM UTC 24
Peak memory 216060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063106602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4063106602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.486943369
Short name T638
Test name
Test status
Simulation time 15061491 ps
CPU time 1.15 seconds
Started Oct 15 12:42:30 PM UTC 24
Finished Oct 15 12:42:32 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486943369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.486943369
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.1243766863
Short name T650
Test name
Test status
Simulation time 5417816146 ps
CPU time 20.42 seconds
Started Oct 15 12:42:39 PM UTC 24
Finished Oct 15 12:43:01 PM UTC 24
Peak memory 250968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243766863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1243766863
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/28.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.1761907383
Short name T666
Test name
Test status
Simulation time 41271337 ps
CPU time 1.1 seconds
Started Oct 15 12:43:25 PM UTC 24
Finished Oct 15 12:43:28 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761907383 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.1761907383
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1517950335
Short name T676
Test name
Test status
Simulation time 18033848306 ps
CPU time 25.36 seconds
Started Oct 15 12:43:08 PM UTC 24
Finished Oct 15 12:43:34 PM UTC 24
Peak memory 245040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517950335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1517950335
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.3993804415
Short name T657
Test name
Test status
Simulation time 33016595 ps
CPU time 1.23 seconds
Started Oct 15 12:43:02 PM UTC 24
Finished Oct 15 12:43:05 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993804415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3993804415
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.3682407412
Short name T682
Test name
Test status
Simulation time 2227585517 ps
CPU time 31.18 seconds
Started Oct 15 12:43:18 PM UTC 24
Finished Oct 15 12:43:50 PM UTC 24
Peak memory 249376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682407412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3682407412
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.3741950996
Short name T733
Test name
Test status
Simulation time 28495006967 ps
CPU time 131.14 seconds
Started Oct 15 12:43:21 PM UTC 24
Finished Oct 15 12:45:35 PM UTC 24
Peak memory 267604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741950996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.3741950996
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.2180028929
Short name T665
Test name
Test status
Simulation time 1366019166 ps
CPU time 8.39 seconds
Started Oct 15 12:43:12 PM UTC 24
Finished Oct 15 12:43:22 PM UTC 24
Peak memory 251364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180028929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2180028929
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3765125725
Short name T953
Test name
Test status
Simulation time 55708572054 ps
CPU time 465.1 seconds
Started Oct 15 12:43:12 PM UTC 24
Finished Oct 15 12:51:03 PM UTC 24
Peak memory 277800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765125725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.3765125725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.954245940
Short name T196
Test name
Test status
Simulation time 9276465845 ps
CPU time 17.64 seconds
Started Oct 15 12:43:06 PM UTC 24
Finished Oct 15 12:43:25 PM UTC 24
Peak memory 244188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954245940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.954245940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.3257098359
Short name T661
Test name
Test status
Simulation time 250117051 ps
CPU time 3.78 seconds
Started Oct 15 12:43:07 PM UTC 24
Finished Oct 15 12:43:11 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257098359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3257098359
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.4138825646
Short name T662
Test name
Test status
Simulation time 581888347 ps
CPU time 8.59 seconds
Started Oct 15 12:43:06 PM UTC 24
Finished Oct 15 12:43:16 PM UTC 24
Peak memory 234620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138825646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.4138825646
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2597302303
Short name T663
Test name
Test status
Simulation time 974361698 ps
CPU time 12.33 seconds
Started Oct 15 12:43:05 PM UTC 24
Finished Oct 15 12:43:18 PM UTC 24
Peak memory 231464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597302303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2597302303
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.3168256136
Short name T664
Test name
Test status
Simulation time 1306808921 ps
CPU time 5.69 seconds
Started Oct 15 12:43:13 PM UTC 24
Finished Oct 15 12:43:20 PM UTC 24
Peak memory 233544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168256136 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.3168256136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.3706046220
Short name T168
Test name
Test status
Simulation time 1486693405 ps
CPU time 23.99 seconds
Started Oct 15 12:43:23 PM UTC 24
Finished Oct 15 12:43:48 PM UTC 24
Peak memory 251168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706046220 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.3706046220
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.2594829792
Short name T669
Test name
Test status
Simulation time 7484444268 ps
CPU time 26.62 seconds
Started Oct 15 12:43:02 PM UTC 24
Finished Oct 15 12:43:30 PM UTC 24
Peak memory 231768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594829792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2594829792
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.4159308892
Short name T655
Test name
Test status
Simulation time 11346294 ps
CPU time 1.09 seconds
Started Oct 15 12:43:02 PM UTC 24
Finished Oct 15 12:43:04 PM UTC 24
Peak memory 213472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159308892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4159308892
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.3301856946
Short name T659
Test name
Test status
Simulation time 38215382 ps
CPU time 1.71 seconds
Started Oct 15 12:43:04 PM UTC 24
Finished Oct 15 12:43:06 PM UTC 24
Peak memory 216256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301856946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3301856946
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2081983645
Short name T658
Test name
Test status
Simulation time 39885578 ps
CPU time 1.17 seconds
Started Oct 15 12:43:04 PM UTC 24
Finished Oct 15 12:43:06 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081983645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2081983645
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.1776457248
Short name T660
Test name
Test status
Simulation time 58777996 ps
CPU time 3.26 seconds
Started Oct 15 12:43:07 PM UTC 24
Finished Oct 15 12:43:11 PM UTC 24
Peak memory 234344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776457248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1776457248
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/29.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.649859865
Short name T372
Test name
Test status
Simulation time 12371360 ps
CPU time 1.01 seconds
Started Oct 15 12:29:21 PM UTC 24
Finished Oct 15 12:29:23 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649859865 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.649859865
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.3717307650
Short name T92
Test name
Test status
Simulation time 272374548 ps
CPU time 4.1 seconds
Started Oct 15 12:29:01 PM UTC 24
Finished Oct 15 12:29:06 PM UTC 24
Peak memory 245108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717307650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3717307650
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.2667768129
Short name T369
Test name
Test status
Simulation time 12196593 ps
CPU time 1.21 seconds
Started Oct 15 12:28:48 PM UTC 24
Finished Oct 15 12:28:51 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667768129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2667768129
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.2043603147
Short name T87
Test name
Test status
Simulation time 10678806582 ps
CPU time 122.17 seconds
Started Oct 15 12:29:12 PM UTC 24
Finished Oct 15 12:31:16 PM UTC 24
Peak memory 249460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043603147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2043603147
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.631542848
Short name T52
Test name
Test status
Simulation time 19149125562 ps
CPU time 78.14 seconds
Started Oct 15 12:29:15 PM UTC 24
Finished Oct 15 12:30:35 PM UTC 24
Peak memory 261736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631542848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.631542848
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.2877509171
Short name T54
Test name
Test status
Simulation time 153249461 ps
CPU time 6.31 seconds
Started Oct 15 12:29:02 PM UTC 24
Finished Oct 15 12:29:10 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877509171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2877509171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1126267242
Short name T216
Test name
Test status
Simulation time 53394688294 ps
CPU time 450.61 seconds
Started Oct 15 12:29:07 PM UTC 24
Finished Oct 15 12:36:44 PM UTC 24
Peak memory 277804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126267242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.1126267242
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.3617560690
Short name T91
Test name
Test status
Simulation time 99571707 ps
CPU time 4.71 seconds
Started Oct 15 12:28:55 PM UTC 24
Finished Oct 15 12:29:01 PM UTC 24
Peak memory 244912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617560690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3617560690
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.3297810991
Short name T175
Test name
Test status
Simulation time 8123127366 ps
CPU time 39.68 seconds
Started Oct 15 12:28:59 PM UTC 24
Finished Oct 15 12:29:41 PM UTC 24
Peak memory 245084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297810991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3297810991
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.2523136513
Short name T370
Test name
Test status
Simulation time 227377082 ps
CPU time 1.77 seconds
Started Oct 15 12:28:48 PM UTC 24
Finished Oct 15 12:28:51 PM UTC 24
Peak memory 228880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523136513 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_parity.2523136513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1113219697
Short name T61
Test name
Test status
Simulation time 4299704730 ps
CPU time 24.05 seconds
Started Oct 15 12:28:55 PM UTC 24
Finished Oct 15 12:29:20 PM UTC 24
Peak memory 251192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113219697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.1113219697
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2249881128
Short name T183
Test name
Test status
Simulation time 225588696 ps
CPU time 3.74 seconds
Started Oct 15 12:28:54 PM UTC 24
Finished Oct 15 12:28:59 PM UTC 24
Peak memory 234956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249881128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2249881128
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.4056478295
Short name T156
Test name
Test status
Simulation time 103184612 ps
CPU time 5.86 seconds
Started Oct 15 12:29:11 PM UTC 24
Finished Oct 15 12:29:17 PM UTC 24
Peak memory 231144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056478295 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.4056478295
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.3330312416
Short name T34
Test name
Test status
Simulation time 120334733 ps
CPU time 1.72 seconds
Started Oct 15 12:29:19 PM UTC 24
Finished Oct 15 12:29:22 PM UTC 24
Peak memory 256900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330312416 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3330312416
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.3167682111
Short name T33
Test name
Test status
Simulation time 184974445 ps
CPU time 1.48 seconds
Started Oct 15 12:29:19 PM UTC 24
Finished Oct 15 12:29:22 PM UTC 24
Peak memory 226396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167682111 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.3167682111
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.616464516
Short name T71
Test name
Test status
Simulation time 14041468105 ps
CPU time 25.75 seconds
Started Oct 15 12:28:51 PM UTC 24
Finished Oct 15 12:29:18 PM UTC 24
Peak memory 231504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616464516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.616464516
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1318866837
Short name T371
Test name
Test status
Simulation time 755537342 ps
CPU time 10.47 seconds
Started Oct 15 12:28:49 PM UTC 24
Finished Oct 15 12:29:01 PM UTC 24
Peak memory 227628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318866837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1318866837
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.4000114596
Short name T70
Test name
Test status
Simulation time 105261588 ps
CPU time 6.42 seconds
Started Oct 15 12:28:52 PM UTC 24
Finished Oct 15 12:28:59 PM UTC 24
Peak memory 227304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000114596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4000114596
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3629046609
Short name T105
Test name
Test status
Simulation time 43649646 ps
CPU time 1.28 seconds
Started Oct 15 12:28:52 PM UTC 24
Finished Oct 15 12:28:54 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629046609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3629046609
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.561194536
Short name T65
Test name
Test status
Simulation time 3112840938 ps
CPU time 9.66 seconds
Started Oct 15 12:29:00 PM UTC 24
Finished Oct 15 12:29:11 PM UTC 24
Peak memory 245032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561194536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.561194536
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/3.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.2973914568
Short name T681
Test name
Test status
Simulation time 12117913 ps
CPU time 1.1 seconds
Started Oct 15 12:43:48 PM UTC 24
Finished Oct 15 12:43:50 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973914568 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.2973914568
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.3439297182
Short name T295
Test name
Test status
Simulation time 170331021 ps
CPU time 3.32 seconds
Started Oct 15 12:43:36 PM UTC 24
Finished Oct 15 12:43:41 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439297182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3439297182
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.2885748498
Short name T667
Test name
Test status
Simulation time 29237737 ps
CPU time 1.16 seconds
Started Oct 15 12:43:26 PM UTC 24
Finished Oct 15 12:43:29 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885748498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2885748498
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.128285703
Short name T717
Test name
Test status
Simulation time 27082992785 ps
CPU time 83.63 seconds
Started Oct 15 12:43:44 PM UTC 24
Finished Oct 15 12:45:10 PM UTC 24
Peak memory 261672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128285703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.128285703
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2082184513
Short name T78
Test name
Test status
Simulation time 4103573050 ps
CPU time 59.06 seconds
Started Oct 15 12:43:45 PM UTC 24
Finished Oct 15 12:44:46 PM UTC 24
Peak memory 251300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082184513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2082184513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3888493593
Short name T761
Test name
Test status
Simulation time 216169863855 ps
CPU time 135.58 seconds
Started Oct 15 12:43:46 PM UTC 24
Finished Oct 15 12:46:05 PM UTC 24
Peak memory 265548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888493593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.3888493593
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.772578030
Short name T679
Test name
Test status
Simulation time 177248583 ps
CPU time 7.08 seconds
Started Oct 15 12:43:36 PM UTC 24
Finished Oct 15 12:43:44 PM UTC 24
Peak memory 234916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772578030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.772578030
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2842719974
Short name T278
Test name
Test status
Simulation time 48620098777 ps
CPU time 43.24 seconds
Started Oct 15 12:43:40 PM UTC 24
Finished Oct 15 12:44:24 PM UTC 24
Peak memory 261416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842719974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.2842719974
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.502162759
Short name T678
Test name
Test status
Simulation time 2742026116 ps
CPU time 8.46 seconds
Started Oct 15 12:43:34 PM UTC 24
Finished Oct 15 12:43:43 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502162759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.502162759
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.3591750765
Short name T692
Test name
Test status
Simulation time 5380059949 ps
CPU time 26.6 seconds
Started Oct 15 12:43:35 PM UTC 24
Finished Oct 15 12:44:03 PM UTC 24
Peak memory 235068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591750765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3591750765
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1730799411
Short name T680
Test name
Test status
Simulation time 7666814317 ps
CPU time 12.35 seconds
Started Oct 15 12:43:32 PM UTC 24
Finished Oct 15 12:43:46 PM UTC 24
Peak memory 245084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730799411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.1730799411
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.4162715115
Short name T701
Test name
Test status
Simulation time 30027998287 ps
CPU time 49.67 seconds
Started Oct 15 12:43:31 PM UTC 24
Finished Oct 15 12:44:23 PM UTC 24
Peak memory 251228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162715115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4162715115
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.2687129483
Short name T686
Test name
Test status
Simulation time 2054584515 ps
CPU time 11.08 seconds
Started Oct 15 12:43:42 PM UTC 24
Finished Oct 15 12:43:54 PM UTC 24
Peak memory 233224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687129483 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.2687129483
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.4187031635
Short name T864
Test name
Test status
Simulation time 400415275747 ps
CPU time 286.98 seconds
Started Oct 15 12:43:48 PM UTC 24
Finished Oct 15 12:48:38 PM UTC 24
Peak memory 261536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187031635 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.4187031635
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.982284736
Short name T677
Test name
Test status
Simulation time 2322549751 ps
CPU time 6.95 seconds
Started Oct 15 12:43:30 PM UTC 24
Finished Oct 15 12:43:38 PM UTC 24
Peak memory 229720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982284736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.982284736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3724487329
Short name T684
Test name
Test status
Simulation time 2959205418 ps
CPU time 22.71 seconds
Started Oct 15 12:43:29 PM UTC 24
Finished Oct 15 12:43:53 PM UTC 24
Peak memory 227412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724487329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3724487329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.1650800842
Short name T673
Test name
Test status
Simulation time 30219145 ps
CPU time 1.88 seconds
Started Oct 15 12:43:31 PM UTC 24
Finished Oct 15 12:43:34 PM UTC 24
Peak memory 226532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650800842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1650800842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1514881885
Short name T672
Test name
Test status
Simulation time 189399346 ps
CPU time 1.24 seconds
Started Oct 15 12:43:31 PM UTC 24
Finished Oct 15 12:43:34 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514881885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1514881885
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.217978197
Short name T307
Test name
Test status
Simulation time 1086556138 ps
CPU time 10.38 seconds
Started Oct 15 12:43:35 PM UTC 24
Finished Oct 15 12:43:46 PM UTC 24
Peak memory 261288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217978197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.217978197
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/30.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.881588668
Short name T696
Test name
Test status
Simulation time 77229767 ps
CPU time 1.13 seconds
Started Oct 15 12:44:14 PM UTC 24
Finished Oct 15 12:44:17 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881588668 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.881588668
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.1721982335
Short name T690
Test name
Test status
Simulation time 183605813 ps
CPU time 2.31 seconds
Started Oct 15 12:43:58 PM UTC 24
Finished Oct 15 12:44:02 PM UTC 24
Peak memory 234416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721982335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1721982335
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.3990756383
Short name T683
Test name
Test status
Simulation time 19336410 ps
CPU time 1.2 seconds
Started Oct 15 12:43:50 PM UTC 24
Finished Oct 15 12:43:52 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990756383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3990756383
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.125099124
Short name T85
Test name
Test status
Simulation time 2887704980 ps
CPU time 54.32 seconds
Started Oct 15 12:44:04 PM UTC 24
Finished Oct 15 12:45:01 PM UTC 24
Peak memory 261472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125099124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.125099124
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.298931753
Short name T706
Test name
Test status
Simulation time 14641691499 ps
CPU time 24.52 seconds
Started Oct 15 12:44:06 PM UTC 24
Finished Oct 15 12:44:32 PM UTC 24
Peak memory 247088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298931753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.298931753
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.3286459766
Short name T755
Test name
Test status
Simulation time 39183675770 ps
CPU time 102.3 seconds
Started Oct 15 12:44:13 PM UTC 24
Finished Oct 15 12:45:58 PM UTC 24
Peak memory 261648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286459766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.3286459766
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.1521395414
Short name T693
Test name
Test status
Simulation time 76692296 ps
CPU time 4.25 seconds
Started Oct 15 12:44:00 PM UTC 24
Finished Oct 15 12:44:05 PM UTC 24
Peak memory 234672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521395414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1521395414
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.752624192
Short name T736
Test name
Test status
Simulation time 8946500782 ps
CPU time 91.23 seconds
Started Oct 15 12:44:03 PM UTC 24
Finished Oct 15 12:45:37 PM UTC 24
Peak memory 245092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752624192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.752624192
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.1596060673
Short name T689
Test name
Test status
Simulation time 566289383 ps
CPU time 3.06 seconds
Started Oct 15 12:43:55 PM UTC 24
Finished Oct 15 12:43:59 PM UTC 24
Peak memory 234920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596060673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1596060673
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.652374016
Short name T695
Test name
Test status
Simulation time 6931876793 ps
CPU time 15.97 seconds
Started Oct 15 12:43:56 PM UTC 24
Finished Oct 15 12:44:13 PM UTC 24
Peak memory 245156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652374016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.652374016
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.2373830777
Short name T697
Test name
Test status
Simulation time 3333111718 ps
CPU time 22.52 seconds
Started Oct 15 12:43:55 PM UTC 24
Finished Oct 15 12:44:19 PM UTC 24
Peak memory 234740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373830777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.2373830777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2168692054
Short name T691
Test name
Test status
Simulation time 362256373 ps
CPU time 7.67 seconds
Started Oct 15 12:43:54 PM UTC 24
Finished Oct 15 12:44:02 PM UTC 24
Peak memory 244912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168692054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2168692054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.396268568
Short name T698
Test name
Test status
Simulation time 1025817338 ps
CPU time 14.62 seconds
Started Oct 15 12:44:03 PM UTC 24
Finished Oct 15 12:44:19 PM UTC 24
Peak memory 231180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396268568 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.396268568
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.1969201805
Short name T707
Test name
Test status
Simulation time 2987303833 ps
CPU time 18.82 seconds
Started Oct 15 12:44:13 PM UTC 24
Finished Oct 15 12:44:33 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969201805 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.1969201805
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.84135371
Short name T694
Test name
Test status
Simulation time 10755364596 ps
CPU time 19.22 seconds
Started Oct 15 12:43:51 PM UTC 24
Finished Oct 15 12:44:12 PM UTC 24
Peak memory 231772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84135371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.84135371
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.2161591662
Short name T687
Test name
Test status
Simulation time 122171859 ps
CPU time 2.96 seconds
Started Oct 15 12:43:51 PM UTC 24
Finished Oct 15 12:43:55 PM UTC 24
Peak memory 217040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161591662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2161591662
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.1712412387
Short name T688
Test name
Test status
Simulation time 79146445 ps
CPU time 1.1 seconds
Started Oct 15 12:43:54 PM UTC 24
Finished Oct 15 12:43:56 PM UTC 24
Peak memory 213472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712412387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1712412387
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.1303877625
Short name T685
Test name
Test status
Simulation time 59515800 ps
CPU time 1.48 seconds
Started Oct 15 12:43:51 PM UTC 24
Finished Oct 15 12:43:54 PM UTC 24
Peak memory 216516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303877625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1303877625
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.2110822189
Short name T703
Test name
Test status
Simulation time 2940672782 ps
CPU time 31.83 seconds
Started Oct 15 12:43:56 PM UTC 24
Finished Oct 15 12:44:29 PM UTC 24
Peak memory 245048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110822189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2110822189
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/31.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.333115194
Short name T675
Test name
Test status
Simulation time 44299330 ps
CPU time 0.92 seconds
Started Oct 15 12:44:38 PM UTC 24
Finished Oct 15 12:44:40 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333115194 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.333115194
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.845053320
Short name T709
Test name
Test status
Simulation time 566255420 ps
CPU time 4.22 seconds
Started Oct 15 12:44:31 PM UTC 24
Finished Oct 15 12:44:36 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845053320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.845053320
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.3195028931
Short name T699
Test name
Test status
Simulation time 17209663 ps
CPU time 1.17 seconds
Started Oct 15 12:44:18 PM UTC 24
Finished Oct 15 12:44:20 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195028931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3195028931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.2318650759
Short name T895
Test name
Test status
Simulation time 278658761129 ps
CPU time 278.16 seconds
Started Oct 15 12:44:35 PM UTC 24
Finished Oct 15 12:49:17 PM UTC 24
Peak memory 261472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318650759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2318650759
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1921346874
Short name T747
Test name
Test status
Simulation time 17746788677 ps
CPU time 72.61 seconds
Started Oct 15 12:44:36 PM UTC 24
Finished Oct 15 12:45:51 PM UTC 24
Peak memory 263584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921346874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1921346874
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.3861453339
Short name T730
Test name
Test status
Simulation time 2319565829 ps
CPU time 50.86 seconds
Started Oct 15 12:44:38 PM UTC 24
Finished Oct 15 12:45:30 PM UTC 24
Peak memory 267056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861453339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.3861453339
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.2302650739
Short name T723
Test name
Test status
Simulation time 9021866355 ps
CPU time 45.35 seconds
Started Oct 15 12:44:33 PM UTC 24
Finished Oct 15 12:45:19 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302650739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2302650739
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1028776998
Short name T752
Test name
Test status
Simulation time 12255777703 ps
CPU time 82 seconds
Started Oct 15 12:44:33 PM UTC 24
Finished Oct 15 12:45:57 PM UTC 24
Peak memory 244988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028776998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.1028776998
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.3644735864
Short name T705
Test name
Test status
Simulation time 1635402413 ps
CPU time 5.08 seconds
Started Oct 15 12:44:25 PM UTC 24
Finished Oct 15 12:44:31 PM UTC 24
Peak memory 234604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644735864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3644735864
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.2738524632
Short name T743
Test name
Test status
Simulation time 27929284559 ps
CPU time 70.39 seconds
Started Oct 15 12:44:31 PM UTC 24
Finished Oct 15 12:45:43 PM UTC 24
Peak memory 251428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738524632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2738524632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.1315770327
Short name T710
Test name
Test status
Simulation time 868115575 ps
CPU time 13.44 seconds
Started Oct 15 12:44:25 PM UTC 24
Finished Oct 15 12:44:40 PM UTC 24
Peak memory 244848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315770327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.1315770327
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.3227816644
Short name T711
Test name
Test status
Simulation time 2142568328 ps
CPU time 14.93 seconds
Started Oct 15 12:44:24 PM UTC 24
Finished Oct 15 12:44:40 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227816644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3227816644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.2975160460
Short name T712
Test name
Test status
Simulation time 148614473 ps
CPU time 6.33 seconds
Started Oct 15 12:44:34 PM UTC 24
Finished Oct 15 12:44:41 PM UTC 24
Peak memory 233224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975160460 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.2975160460
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.1716572497
Short name T169
Test name
Test status
Simulation time 11605482872 ps
CPU time 52.79 seconds
Started Oct 15 12:44:38 PM UTC 24
Finished Oct 15 12:45:32 PM UTC 24
Peak memory 261796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716572497 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.1716572497
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.1623601579
Short name T700
Test name
Test status
Simulation time 62858582 ps
CPU time 1.13 seconds
Started Oct 15 12:44:20 PM UTC 24
Finished Oct 15 12:44:22 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623601579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1623601579
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.1772546708
Short name T708
Test name
Test status
Simulation time 1912041263 ps
CPU time 14.25 seconds
Started Oct 15 12:44:20 PM UTC 24
Finished Oct 15 12:44:36 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772546708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1772546708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.2784714761
Short name T704
Test name
Test status
Simulation time 897394629 ps
CPU time 4.57 seconds
Started Oct 15 12:44:24 PM UTC 24
Finished Oct 15 12:44:29 PM UTC 24
Peak memory 227204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784714761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2784714761
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2186599880
Short name T702
Test name
Test status
Simulation time 144849660 ps
CPU time 1.34 seconds
Started Oct 15 12:44:21 PM UTC 24
Finished Oct 15 12:44:24 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186599880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2186599880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.225199267
Short name T718
Test name
Test status
Simulation time 27543388212 ps
CPU time 37.69 seconds
Started Oct 15 12:44:31 PM UTC 24
Finished Oct 15 12:45:10 PM UTC 24
Peak memory 234748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225199267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.225199267
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/32.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.4122382632
Short name T719
Test name
Test status
Simulation time 43493180 ps
CPU time 1.11 seconds
Started Oct 15 12:45:09 PM UTC 24
Finished Oct 15 12:45:11 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122382632 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.4122382632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1208976001
Short name T715
Test name
Test status
Simulation time 2465364796 ps
CPU time 7.44 seconds
Started Oct 15 12:44:56 PM UTC 24
Finished Oct 15 12:45:04 PM UTC 24
Peak memory 234788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208976001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1208976001
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.3635215521
Short name T713
Test name
Test status
Simulation time 27530230 ps
CPU time 1.11 seconds
Started Oct 15 12:44:41 PM UTC 24
Finished Oct 15 12:44:44 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635215521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3635215521
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2410395540
Short name T1014
Test name
Test status
Simulation time 279909392374 ps
CPU time 527.64 seconds
Started Oct 15 12:45:02 PM UTC 24
Finished Oct 15 12:53:56 PM UTC 24
Peak memory 265564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410395540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2410395540
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.764267179
Short name T833
Test name
Test status
Simulation time 8288879841 ps
CPU time 175.02 seconds
Started Oct 15 12:45:03 PM UTC 24
Finished Oct 15 12:48:01 PM UTC 24
Peak memory 275796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764267179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.764267179
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.218964862
Short name T813
Test name
Test status
Simulation time 5015166547 ps
CPU time 145.37 seconds
Started Oct 15 12:45:05 PM UTC 24
Finished Oct 15 12:47:33 PM UTC 24
Peak memory 279900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218964862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.218964862
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.3368642482
Short name T714
Test name
Test status
Simulation time 121175285 ps
CPU time 5.3 seconds
Started Oct 15 12:44:56 PM UTC 24
Finished Oct 15 12:45:02 PM UTC 24
Peak memory 234912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368642482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3368642482
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.1143606840
Short name T765
Test name
Test status
Simulation time 3588654164 ps
CPU time 67.23 seconds
Started Oct 15 12:44:58 PM UTC 24
Finished Oct 15 12:46:07 PM UTC 24
Peak memory 261532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143606840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.1143606840
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.3287047184
Short name T83
Test name
Test status
Simulation time 2311624343 ps
CPU time 9.51 seconds
Started Oct 15 12:44:47 PM UTC 24
Finished Oct 15 12:44:58 PM UTC 24
Peak memory 244892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287047184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3287047184
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.1191616517
Short name T750
Test name
Test status
Simulation time 5945745728 ps
CPU time 60.61 seconds
Started Oct 15 12:44:52 PM UTC 24
Finished Oct 15 12:45:55 PM UTC 24
Peak memory 245300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191616517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1191616517
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.4120769874
Short name T79
Test name
Test status
Simulation time 97176708 ps
CPU time 3.12 seconds
Started Oct 15 12:44:47 PM UTC 24
Finished Oct 15 12:44:51 PM UTC 24
Peak memory 244352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120769874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.4120769874
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3601591005
Short name T80
Test name
Test status
Simulation time 469662901 ps
CPU time 5 seconds
Started Oct 15 12:44:45 PM UTC 24
Finished Oct 15 12:44:52 PM UTC 24
Peak memory 244956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601591005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3601591005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.3722661156
Short name T720
Test name
Test status
Simulation time 4556865707 ps
CPU time 11.43 seconds
Started Oct 15 12:45:00 PM UTC 24
Finished Oct 15 12:45:13 PM UTC 24
Peak memory 231256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722661156 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.3722661156
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.3110779008
Short name T152
Test name
Test status
Simulation time 1972085799483 ps
CPU time 960.61 seconds
Started Oct 15 12:45:07 PM UTC 24
Finished Oct 15 01:01:19 PM UTC 24
Peak memory 294236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110779008 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.3110779008
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.909609097
Short name T81
Test name
Test status
Simulation time 5292441180 ps
CPU time 12.38 seconds
Started Oct 15 12:44:42 PM UTC 24
Finished Oct 15 12:44:55 PM UTC 24
Peak memory 227412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909609097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.909609097
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.1086151527
Short name T84
Test name
Test status
Simulation time 1981329723 ps
CPU time 17.08 seconds
Started Oct 15 12:44:41 PM UTC 24
Finished Oct 15 12:45:00 PM UTC 24
Peak memory 227268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086151527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1086151527
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.2502302143
Short name T82
Test name
Test status
Simulation time 552426893 ps
CPU time 9.81 seconds
Started Oct 15 12:44:44 PM UTC 24
Finished Oct 15 12:44:55 PM UTC 24
Peak memory 227244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502302143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2502302143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.3772081417
Short name T77
Test name
Test status
Simulation time 30325804 ps
CPU time 1.22 seconds
Started Oct 15 12:44:43 PM UTC 24
Finished Oct 15 12:44:45 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772081417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3772081417
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.2870370481
Short name T716
Test name
Test status
Simulation time 2341405587 ps
CPU time 14.31 seconds
Started Oct 15 12:44:52 PM UTC 24
Finished Oct 15 12:45:08 PM UTC 24
Peak memory 251236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870370481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2870370481
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/33.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.2702803245
Short name T735
Test name
Test status
Simulation time 10846562 ps
CPU time 1.08 seconds
Started Oct 15 12:45:34 PM UTC 24
Finished Oct 15 12:45:37 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702803245 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.2702803245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3924884460
Short name T731
Test name
Test status
Simulation time 147495024 ps
CPU time 2.6 seconds
Started Oct 15 12:45:27 PM UTC 24
Finished Oct 15 12:45:31 PM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924884460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3924884460
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.2720275081
Short name T721
Test name
Test status
Simulation time 84102201 ps
CPU time 1.1 seconds
Started Oct 15 12:45:11 PM UTC 24
Finished Oct 15 12:45:13 PM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720275081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2720275081
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.3129259600
Short name T818
Test name
Test status
Simulation time 25323406866 ps
CPU time 131.98 seconds
Started Oct 15 12:45:31 PM UTC 24
Finished Oct 15 12:47:46 PM UTC 24
Peak memory 278116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129259600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3129259600
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.660099625
Short name T751
Test name
Test status
Simulation time 1092789142 ps
CPU time 21.95 seconds
Started Oct 15 12:45:33 PM UTC 24
Finished Oct 15 12:45:56 PM UTC 24
Peak memory 234724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660099625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.660099625
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.154386726
Short name T266
Test name
Test status
Simulation time 8447692066 ps
CPU time 138.48 seconds
Started Oct 15 12:45:33 PM UTC 24
Finished Oct 15 12:47:54 PM UTC 24
Peak memory 279908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154386726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.154386726
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.1611096052
Short name T343
Test name
Test status
Simulation time 13755932025 ps
CPU time 69.17 seconds
Started Oct 15 12:45:29 PM UTC 24
Finished Oct 15 12:46:40 PM UTC 24
Peak memory 261404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611096052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1611096052
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.350907355
Short name T831
Test name
Test status
Simulation time 34290874593 ps
CPU time 147.9 seconds
Started Oct 15 12:45:30 PM UTC 24
Finished Oct 15 12:48:01 PM UTC 24
Peak memory 279908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350907355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.350907355
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.2401827227
Short name T727
Test name
Test status
Simulation time 136831009 ps
CPU time 5.08 seconds
Started Oct 15 12:45:21 PM UTC 24
Finished Oct 15 12:45:27 PM UTC 24
Peak memory 245232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401827227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2401827227
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.1950656643
Short name T732
Test name
Test status
Simulation time 2567486248 ps
CPU time 9.99 seconds
Started Oct 15 12:45:23 PM UTC 24
Finished Oct 15 12:45:34 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950656643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1950656643
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.3553882127
Short name T729
Test name
Test status
Simulation time 759607395 ps
CPU time 6.85 seconds
Started Oct 15 12:45:21 PM UTC 24
Finished Oct 15 12:45:29 PM UTC 24
Peak memory 234620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553882127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.3553882127
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.273924222
Short name T741
Test name
Test status
Simulation time 4308596478 ps
CPU time 22.72 seconds
Started Oct 15 12:45:17 PM UTC 24
Finished Oct 15 12:45:41 PM UTC 24
Peak memory 245348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273924222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.273924222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.907464628
Short name T734
Test name
Test status
Simulation time 73531440 ps
CPU time 4.37 seconds
Started Oct 15 12:45:30 PM UTC 24
Finished Oct 15 12:45:35 PM UTC 24
Peak memory 229348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907464628 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.907464628
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.1096791433
Short name T261
Test name
Test status
Simulation time 69171514811 ps
CPU time 356.66 seconds
Started Oct 15 12:45:34 PM UTC 24
Finished Oct 15 12:51:36 PM UTC 24
Peak memory 284060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096791433 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.1096791433
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.479270436
Short name T742
Test name
Test status
Simulation time 15878699829 ps
CPU time 29.95 seconds
Started Oct 15 12:45:11 PM UTC 24
Finished Oct 15 12:45:43 PM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479270436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.479270436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3516405615
Short name T724
Test name
Test status
Simulation time 913444585 ps
CPU time 7.21 seconds
Started Oct 15 12:45:11 PM UTC 24
Finished Oct 15 12:45:20 PM UTC 24
Peak memory 227016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516405615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3516405615
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.836003437
Short name T726
Test name
Test status
Simulation time 479866613 ps
CPU time 6.51 seconds
Started Oct 15 12:45:15 PM UTC 24
Finished Oct 15 12:45:23 PM UTC 24
Peak memory 227236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836003437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.836003437
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.548350381
Short name T722
Test name
Test status
Simulation time 172346003 ps
CPU time 1.5 seconds
Started Oct 15 12:45:14 PM UTC 24
Finished Oct 15 12:45:16 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548350381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.548350381
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.1148737751
Short name T728
Test name
Test status
Simulation time 208004333 ps
CPU time 3.15 seconds
Started Oct 15 12:45:24 PM UTC 24
Finished Oct 15 12:45:29 PM UTC 24
Peak memory 233796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148737751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1148737751
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/34.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.2348448737
Short name T754
Test name
Test status
Simulation time 21000432 ps
CPU time 1 seconds
Started Oct 15 12:45:55 PM UTC 24
Finished Oct 15 12:45:57 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348448737 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.2348448737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.3763497961
Short name T748
Test name
Test status
Simulation time 692663028 ps
CPU time 5.96 seconds
Started Oct 15 12:45:44 PM UTC 24
Finished Oct 15 12:45:51 PM UTC 24
Peak memory 244848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763497961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3763497961
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.3734402203
Short name T737
Test name
Test status
Simulation time 13701067 ps
CPU time 1.16 seconds
Started Oct 15 12:45:36 PM UTC 24
Finished Oct 15 12:45:38 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734402203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3734402203
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.3796501196
Short name T935
Test name
Test status
Simulation time 198727556049 ps
CPU time 276.54 seconds
Started Oct 15 12:45:49 PM UTC 24
Finished Oct 15 12:50:29 PM UTC 24
Peak memory 267560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796501196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3796501196
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.3088783789
Short name T822
Test name
Test status
Simulation time 19105390682 ps
CPU time 116.05 seconds
Started Oct 15 12:45:51 PM UTC 24
Finished Oct 15 12:47:50 PM UTC 24
Peak memory 278116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088783789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3088783789
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.3897986719
Short name T799
Test name
Test status
Simulation time 17570144007 ps
CPU time 68.19 seconds
Started Oct 15 12:45:53 PM UTC 24
Finished Oct 15 12:47:03 PM UTC 24
Peak memory 261452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897986719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.3897986719
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.1213697928
Short name T753
Test name
Test status
Simulation time 1430057039 ps
CPU time 11.26 seconds
Started Oct 15 12:45:44 PM UTC 24
Finished Oct 15 12:45:57 PM UTC 24
Peak memory 244920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213697928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1213697928
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2441773963
Short name T767
Test name
Test status
Simulation time 2998468439 ps
CPU time 25.78 seconds
Started Oct 15 12:45:44 PM UTC 24
Finished Oct 15 12:46:12 PM UTC 24
Peak memory 251164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441773963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.2441773963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.1907705056
Short name T760
Test name
Test status
Simulation time 11076009374 ps
CPU time 17.79 seconds
Started Oct 15 12:45:41 PM UTC 24
Finished Oct 15 12:46:00 PM UTC 24
Peak memory 245280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907705056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1907705056
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.1428713441
Short name T746
Test name
Test status
Simulation time 233270081 ps
CPU time 3.97 seconds
Started Oct 15 12:45:43 PM UTC 24
Finished Oct 15 12:45:48 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428713441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1428713441
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.1942809828
Short name T762
Test name
Test status
Simulation time 31112242200 ps
CPU time 23.59 seconds
Started Oct 15 12:45:41 PM UTC 24
Finished Oct 15 12:46:06 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942809828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.1942809828
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2043951521
Short name T745
Test name
Test status
Simulation time 548885035 ps
CPU time 4.5 seconds
Started Oct 15 12:45:40 PM UTC 24
Finished Oct 15 12:45:46 PM UTC 24
Peak memory 234676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043951521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2043951521
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.3796996488
Short name T757
Test name
Test status
Simulation time 17083323586 ps
CPU time 11.24 seconds
Started Oct 15 12:45:47 PM UTC 24
Finished Oct 15 12:45:59 PM UTC 24
Peak memory 231560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796996488 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.3796996488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.1965015175
Short name T929
Test name
Test status
Simulation time 65564473576 ps
CPU time 260.71 seconds
Started Oct 15 12:45:53 PM UTC 24
Finished Oct 15 12:50:17 PM UTC 24
Peak memory 265572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965015175 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.1965015175
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.977032228
Short name T738
Test name
Test status
Simulation time 34683079 ps
CPU time 1.12 seconds
Started Oct 15 12:45:37 PM UTC 24
Finished Oct 15 12:45:39 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977032228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.977032228
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.4294136561
Short name T739
Test name
Test status
Simulation time 514479639 ps
CPU time 2.23 seconds
Started Oct 15 12:45:36 PM UTC 24
Finished Oct 15 12:45:39 PM UTC 24
Peak memory 217044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294136561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4294136561
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.262488060
Short name T744
Test name
Test status
Simulation time 68696834 ps
CPU time 4.09 seconds
Started Oct 15 12:45:38 PM UTC 24
Finished Oct 15 12:45:44 PM UTC 24
Peak memory 227604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262488060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.262488060
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2467430232
Short name T740
Test name
Test status
Simulation time 35570420 ps
CPU time 1.16 seconds
Started Oct 15 12:45:38 PM UTC 24
Finished Oct 15 12:45:41 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467430232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2467430232
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.3575197555
Short name T749
Test name
Test status
Simulation time 1342639693 ps
CPU time 10.13 seconds
Started Oct 15 12:45:43 PM UTC 24
Finished Oct 15 12:45:54 PM UTC 24
Peak memory 234876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575197555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3575197555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/35.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.434570777
Short name T768
Test name
Test status
Simulation time 44588266 ps
CPU time 1.13 seconds
Started Oct 15 12:46:10 PM UTC 24
Finished Oct 15 12:46:12 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434570777 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.434570777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.2151465186
Short name T763
Test name
Test status
Simulation time 217926864 ps
CPU time 3.41 seconds
Started Oct 15 12:46:02 PM UTC 24
Finished Oct 15 12:46:06 PM UTC 24
Peak memory 234648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151465186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2151465186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.1914945990
Short name T756
Test name
Test status
Simulation time 39584643 ps
CPU time 1.08 seconds
Started Oct 15 12:45:56 PM UTC 24
Finished Oct 15 12:45:58 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914945990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1914945990
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.3279170244
Short name T773
Test name
Test status
Simulation time 241731931 ps
CPU time 6.85 seconds
Started Oct 15 12:46:08 PM UTC 24
Finished Oct 15 12:46:16 PM UTC 24
Peak memory 251296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279170244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3279170244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3413923183
Short name T1019
Test name
Test status
Simulation time 208453156340 ps
CPU time 491.39 seconds
Started Oct 15 12:46:08 PM UTC 24
Finished Oct 15 12:54:25 PM UTC 24
Peak memory 267680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413923183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3413923183
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2353216809
Short name T854
Test name
Test status
Simulation time 132066375942 ps
CPU time 136.62 seconds
Started Oct 15 12:46:08 PM UTC 24
Finished Oct 15 12:48:27 PM UTC 24
Peak memory 261448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353216809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.2353216809
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.3927878227
Short name T774
Test name
Test status
Simulation time 2446444549 ps
CPU time 13.43 seconds
Started Oct 15 12:46:02 PM UTC 24
Finished Oct 15 12:46:17 PM UTC 24
Peak memory 265764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927878227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3927878227
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.115578551
Short name T941
Test name
Test status
Simulation time 30634749688 ps
CPU time 269.11 seconds
Started Oct 15 12:46:06 PM UTC 24
Finished Oct 15 12:50:39 PM UTC 24
Peak memory 265500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115578551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.115578551
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.1411657519
Short name T764
Test name
Test status
Simulation time 1170329815 ps
CPU time 6.05 seconds
Started Oct 15 12:46:00 PM UTC 24
Finished Oct 15 12:46:07 PM UTC 24
Peak memory 234852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411657519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1411657519
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.752475225
Short name T837
Test name
Test status
Simulation time 171160615388 ps
CPU time 123.82 seconds
Started Oct 15 12:46:02 PM UTC 24
Finished Oct 15 12:48:08 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752475225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.752475225
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.3427096217
Short name T779
Test name
Test status
Simulation time 12664180508 ps
CPU time 18.51 seconds
Started Oct 15 12:46:00 PM UTC 24
Finished Oct 15 12:46:19 PM UTC 24
Peak memory 245044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427096217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.3427096217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2344488287
Short name T769
Test name
Test status
Simulation time 18031298976 ps
CPU time 13.85 seconds
Started Oct 15 12:45:58 PM UTC 24
Finished Oct 15 12:46:13 PM UTC 24
Peak memory 251164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344488287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2344488287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.8358094
Short name T770
Test name
Test status
Simulation time 878888142 ps
CPU time 4.58 seconds
Started Oct 15 12:46:08 PM UTC 24
Finished Oct 15 12:46:13 PM UTC 24
Peak memory 231188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8358094 -assert nopostproc +UVM_TESTNAME=spi_device_base
_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.8358094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.1947740469
Short name T260
Test name
Test status
Simulation time 229647684310 ps
CPU time 695.09 seconds
Started Oct 15 12:46:10 PM UTC 24
Finished Oct 15 12:57:53 PM UTC 24
Peak memory 281828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947740469 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.1947740469
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.1997474791
Short name T775
Test name
Test status
Simulation time 1153817945 ps
CPU time 18.12 seconds
Started Oct 15 12:45:58 PM UTC 24
Finished Oct 15 12:46:17 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997474791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1997474791
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.1935768113
Short name T766
Test name
Test status
Simulation time 2516751526 ps
CPU time 10.2 seconds
Started Oct 15 12:45:56 PM UTC 24
Finished Oct 15 12:46:08 PM UTC 24
Peak memory 227336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935768113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1935768113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.2443647423
Short name T759
Test name
Test status
Simulation time 107056305 ps
CPU time 1.19 seconds
Started Oct 15 12:45:58 PM UTC 24
Finished Oct 15 12:46:00 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443647423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2443647423
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.3565184642
Short name T758
Test name
Test status
Simulation time 99879379 ps
CPU time 1.16 seconds
Started Oct 15 12:45:58 PM UTC 24
Finished Oct 15 12:46:00 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565184642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3565184642
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.1549323051
Short name T772
Test name
Test status
Simulation time 9271743854 ps
CPU time 11.94 seconds
Started Oct 15 12:46:02 PM UTC 24
Finished Oct 15 12:46:15 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549323051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1549323051
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/36.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.875390586
Short name T787
Test name
Test status
Simulation time 47869430 ps
CPU time 1.08 seconds
Started Oct 15 12:46:38 PM UTC 24
Finished Oct 15 12:46:40 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875390586 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.875390586
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.1710541855
Short name T781
Test name
Test status
Simulation time 986677886 ps
CPU time 3.13 seconds
Started Oct 15 12:46:20 PM UTC 24
Finished Oct 15 12:46:24 PM UTC 24
Peak memory 234880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710541855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1710541855
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.1592011330
Short name T771
Test name
Test status
Simulation time 41791199 ps
CPU time 1.07 seconds
Started Oct 15 12:46:12 PM UTC 24
Finished Oct 15 12:46:14 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592011330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1592011330
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.3370254984
Short name T804
Test name
Test status
Simulation time 2240096566 ps
CPU time 49.61 seconds
Started Oct 15 12:46:25 PM UTC 24
Finished Oct 15 12:47:16 PM UTC 24
Peak memory 263584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370254984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3370254984
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.162674151
Short name T1030
Test name
Test status
Simulation time 82559580525 ps
CPU time 731.32 seconds
Started Oct 15 12:46:29 PM UTC 24
Finished Oct 15 12:58:49 PM UTC 24
Peak memory 279944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162674151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.162674151
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3914922788
Short name T841
Test name
Test status
Simulation time 110639803758 ps
CPU time 97 seconds
Started Oct 15 12:46:31 PM UTC 24
Finished Oct 15 12:48:10 PM UTC 24
Peak memory 263564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914922788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.3914922788
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.252919410
Short name T792
Test name
Test status
Simulation time 3814402389 ps
CPU time 27.23 seconds
Started Oct 15 12:46:20 PM UTC 24
Finished Oct 15 12:46:48 PM UTC 24
Peak memory 251228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252919410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.252919410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1052440903
Short name T272
Test name
Test status
Simulation time 15242961495 ps
CPU time 93.96 seconds
Started Oct 15 12:46:21 PM UTC 24
Finished Oct 15 12:47:57 PM UTC 24
Peak memory 277792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052440903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.1052440903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.2741417804
Short name T791
Test name
Test status
Simulation time 4808064728 ps
CPU time 28.95 seconds
Started Oct 15 12:46:18 PM UTC 24
Finished Oct 15 12:46:48 PM UTC 24
Peak memory 235040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741417804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2741417804
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.944633536
Short name T784
Test name
Test status
Simulation time 4426033782 ps
CPU time 13.86 seconds
Started Oct 15 12:46:20 PM UTC 24
Finished Oct 15 12:46:35 PM UTC 24
Peak memory 249124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944633536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.944633536
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2917361506
Short name T786
Test name
Test status
Simulation time 11572638140 ps
CPU time 18.99 seconds
Started Oct 15 12:46:17 PM UTC 24
Finished Oct 15 12:46:37 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917361506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.2917361506
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.768764688
Short name T782
Test name
Test status
Simulation time 1329112445 ps
CPU time 9.82 seconds
Started Oct 15 12:46:17 PM UTC 24
Finished Oct 15 12:46:27 PM UTC 24
Peak memory 234620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768764688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.768764688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1563666234
Short name T783
Test name
Test status
Simulation time 106463792 ps
CPU time 6.14 seconds
Started Oct 15 12:46:22 PM UTC 24
Finished Oct 15 12:46:30 PM UTC 24
Peak memory 233224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563666234 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1563666234
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.256171302
Short name T171
Test name
Test status
Simulation time 71338903 ps
CPU time 1.48 seconds
Started Oct 15 12:46:35 PM UTC 24
Finished Oct 15 12:46:38 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256171302 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.256171302
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.4066086197
Short name T797
Test name
Test status
Simulation time 6248446534 ps
CPU time 42.34 seconds
Started Oct 15 12:46:15 PM UTC 24
Finished Oct 15 12:46:59 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066086197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4066086197
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2083394550
Short name T777
Test name
Test status
Simulation time 944149154 ps
CPU time 3.48 seconds
Started Oct 15 12:46:13 PM UTC 24
Finished Oct 15 12:46:18 PM UTC 24
Peak memory 227276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083394550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2083394550
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.426074138
Short name T778
Test name
Test status
Simulation time 78643828 ps
CPU time 2.18 seconds
Started Oct 15 12:46:15 PM UTC 24
Finished Oct 15 12:46:18 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426074138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.426074138
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.4172175406
Short name T776
Test name
Test status
Simulation time 325169151 ps
CPU time 1.51 seconds
Started Oct 15 12:46:15 PM UTC 24
Finished Oct 15 12:46:18 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172175406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4172175406
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.452687009
Short name T785
Test name
Test status
Simulation time 6167934191 ps
CPU time 15.97 seconds
Started Oct 15 12:46:20 PM UTC 24
Finished Oct 15 12:46:37 PM UTC 24
Peak memory 249124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452687009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.452687009
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/37.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.959200616
Short name T802
Test name
Test status
Simulation time 30359891 ps
CPU time 1.12 seconds
Started Oct 15 12:47:11 PM UTC 24
Finished Oct 15 12:47:13 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959200616 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.959200616
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1628619973
Short name T800
Test name
Test status
Simulation time 308464335 ps
CPU time 6.73 seconds
Started Oct 15 12:46:57 PM UTC 24
Finished Oct 15 12:47:05 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628619973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1628619973
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.1947849634
Short name T788
Test name
Test status
Simulation time 33263299 ps
CPU time 1.15 seconds
Started Oct 15 12:46:38 PM UTC 24
Finished Oct 15 12:46:40 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947849634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1947849634
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.2782252932
Short name T867
Test name
Test status
Simulation time 51282668641 ps
CPU time 100.33 seconds
Started Oct 15 12:47:00 PM UTC 24
Finished Oct 15 12:48:43 PM UTC 24
Peak memory 261416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782252932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2782252932
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2747279956
Short name T829
Test name
Test status
Simulation time 2403467776 ps
CPU time 53.34 seconds
Started Oct 15 12:47:03 PM UTC 24
Finished Oct 15 12:47:59 PM UTC 24
Peak memory 261788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747279956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2747279956
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.967415898
Short name T820
Test name
Test status
Simulation time 1069942129 ps
CPU time 42.9 seconds
Started Oct 15 12:47:04 PM UTC 24
Finished Oct 15 12:47:48 PM UTC 24
Peak memory 261260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967415898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.967415898
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.1128717132
Short name T845
Test name
Test status
Simulation time 3738885956 ps
CPU time 72.87 seconds
Started Oct 15 12:46:58 PM UTC 24
Finished Oct 15 12:48:13 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128717132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1128717132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.473546725
Short name T798
Test name
Test status
Simulation time 22842349 ps
CPU time 1.18 seconds
Started Oct 15 12:47:00 PM UTC 24
Finished Oct 15 12:47:02 PM UTC 24
Peak memory 225164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473546725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.473546725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.1612923863
Short name T810
Test name
Test status
Simulation time 4339996370 ps
CPU time 37.31 seconds
Started Oct 15 12:46:50 PM UTC 24
Finished Oct 15 12:47:28 PM UTC 24
Peak memory 245040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612923863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1612923863
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.2675703163
Short name T796
Test name
Test status
Simulation time 1166980106 ps
CPU time 8.14 seconds
Started Oct 15 12:46:50 PM UTC 24
Finished Oct 15 12:46:59 PM UTC 24
Peak memory 234936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675703163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2675703163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.650680477
Short name T265
Test name
Test status
Simulation time 23718006579 ps
CPU time 10.47 seconds
Started Oct 15 12:46:45 PM UTC 24
Finished Oct 15 12:46:57 PM UTC 24
Peak memory 245032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650680477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.650680477
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.1097610247
Short name T794
Test name
Test status
Simulation time 220509981 ps
CPU time 9.18 seconds
Started Oct 15 12:46:45 PM UTC 24
Finished Oct 15 12:46:56 PM UTC 24
Peak memory 251100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097610247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1097610247
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.582108296
Short name T801
Test name
Test status
Simulation time 1024339950 ps
CPU time 8.76 seconds
Started Oct 15 12:47:00 PM UTC 24
Finished Oct 15 12:47:10 PM UTC 24
Peak memory 233024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582108296 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.582108296
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2781209497
Short name T1023
Test name
Test status
Simulation time 52591168841 ps
CPU time 479 seconds
Started Oct 15 12:47:07 PM UTC 24
Finished Oct 15 12:55:12 PM UTC 24
Peak memory 263776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781209497 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.2781209497
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.3895725957
Short name T803
Test name
Test status
Simulation time 16148153830 ps
CPU time 30.66 seconds
Started Oct 15 12:46:42 PM UTC 24
Finished Oct 15 12:47:14 PM UTC 24
Peak memory 227360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895725957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3895725957
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.2202055289
Short name T793
Test name
Test status
Simulation time 1970971442 ps
CPU time 11.21 seconds
Started Oct 15 12:46:39 PM UTC 24
Finished Oct 15 12:46:51 PM UTC 24
Peak memory 227244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202055289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2202055289
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.211750728
Short name T790
Test name
Test status
Simulation time 148320331 ps
CPU time 1.88 seconds
Started Oct 15 12:46:42 PM UTC 24
Finished Oct 15 12:46:45 PM UTC 24
Peak memory 216264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211750728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.211750728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2475465328
Short name T789
Test name
Test status
Simulation time 85852007 ps
CPU time 1.31 seconds
Started Oct 15 12:46:42 PM UTC 24
Finished Oct 15 12:46:44 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475465328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2475465328
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.3886135702
Short name T795
Test name
Test status
Simulation time 1405049416 ps
CPU time 5.36 seconds
Started Oct 15 12:46:52 PM UTC 24
Finished Oct 15 12:46:58 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886135702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3886135702
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/38.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.2273499743
Short name T821
Test name
Test status
Simulation time 14298759 ps
CPU time 1.12 seconds
Started Oct 15 12:47:47 PM UTC 24
Finished Oct 15 12:47:49 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273499743 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.2273499743
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.1352129818
Short name T814
Test name
Test status
Simulation time 28950954 ps
CPU time 2.95 seconds
Started Oct 15 12:47:32 PM UTC 24
Finished Oct 15 12:47:36 PM UTC 24
Peak memory 234724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352129818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1352129818
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.4244493076
Short name T806
Test name
Test status
Simulation time 29420767 ps
CPU time 1.16 seconds
Started Oct 15 12:47:15 PM UTC 24
Finished Oct 15 12:47:17 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244493076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4244493076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.3271709395
Short name T851
Test name
Test status
Simulation time 1250267730 ps
CPU time 44 seconds
Started Oct 15 12:47:38 PM UTC 24
Finished Oct 15 12:48:24 PM UTC 24
Peak memory 265384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271709395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3271709395
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.120665582
Short name T817
Test name
Test status
Simulation time 86347791 ps
CPU time 1.3 seconds
Started Oct 15 12:47:42 PM UTC 24
Finished Oct 15 12:47:44 PM UTC 24
Peak memory 227064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120665582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.120665582
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3051702566
Short name T876
Test name
Test status
Simulation time 3811100816 ps
CPU time 73.83 seconds
Started Oct 15 12:47:42 PM UTC 24
Finished Oct 15 12:48:57 PM UTC 24
Peak memory 261664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051702566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.3051702566
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.3962721758
Short name T815
Test name
Test status
Simulation time 58918660 ps
CPU time 3.12 seconds
Started Oct 15 12:47:33 PM UTC 24
Finished Oct 15 12:47:37 PM UTC 24
Peak memory 244904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962721758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3962721758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.2562634225
Short name T839
Test name
Test status
Simulation time 2913540067 ps
CPU time 33.01 seconds
Started Oct 15 12:47:35 PM UTC 24
Finished Oct 15 12:48:09 PM UTC 24
Peak memory 234856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562634225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.2562634225
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.1086250897
Short name T811
Test name
Test status
Simulation time 311974302 ps
CPU time 5.8 seconds
Started Oct 15 12:47:24 PM UTC 24
Finished Oct 15 12:47:31 PM UTC 24
Peak memory 234608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086250897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1086250897
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.2842793258
Short name T816
Test name
Test status
Simulation time 857735161 ps
CPU time 9.91 seconds
Started Oct 15 12:47:30 PM UTC 24
Finished Oct 15 12:47:41 PM UTC 24
Peak memory 244916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842793258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2842793258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.1215797418
Short name T258
Test name
Test status
Simulation time 38746927325 ps
CPU time 19.1 seconds
Started Oct 15 12:47:20 PM UTC 24
Finished Oct 15 12:47:40 PM UTC 24
Peak memory 245092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215797418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.1215797418
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1537469866
Short name T809
Test name
Test status
Simulation time 234713763 ps
CPU time 8.63 seconds
Started Oct 15 12:47:19 PM UTC 24
Finished Oct 15 12:47:28 PM UTC 24
Peak memory 234668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537469866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1537469866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2467236356
Short name T824
Test name
Test status
Simulation time 7850682373 ps
CPU time 13.04 seconds
Started Oct 15 12:47:37 PM UTC 24
Finished Oct 15 12:47:51 PM UTC 24
Peak memory 231204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467236356 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.2467236356
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2137605003
Short name T1003
Test name
Test status
Simulation time 23998450865 ps
CPU time 294.89 seconds
Started Oct 15 12:47:45 PM UTC 24
Finished Oct 15 12:52:44 PM UTC 24
Peak memory 278244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137605003 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.2137605003
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.2918397217
Short name T827
Test name
Test status
Simulation time 2071583372 ps
CPU time 39.72 seconds
Started Oct 15 12:47:15 PM UTC 24
Finished Oct 15 12:47:56 PM UTC 24
Peak memory 231340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918397217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2918397217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.1177206887
Short name T805
Test name
Test status
Simulation time 34659248 ps
CPU time 1.11 seconds
Started Oct 15 12:47:15 PM UTC 24
Finished Oct 15 12:47:17 PM UTC 24
Peak memory 213472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177206887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1177206887
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.3301979354
Short name T808
Test name
Test status
Simulation time 917002171 ps
CPU time 3.56 seconds
Started Oct 15 12:47:19 PM UTC 24
Finished Oct 15 12:47:23 PM UTC 24
Peak memory 227412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301979354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3301979354
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2566829536
Short name T807
Test name
Test status
Simulation time 13290467 ps
CPU time 1.13 seconds
Started Oct 15 12:47:17 PM UTC 24
Finished Oct 15 12:47:19 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566829536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2566829536
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.1935455124
Short name T819
Test name
Test status
Simulation time 3243434512 ps
CPU time 16.98 seconds
Started Oct 15 12:47:30 PM UTC 24
Finished Oct 15 12:47:48 PM UTC 24
Peak memory 244988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935455124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1935455124
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/39.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.3219788478
Short name T380
Test name
Test status
Simulation time 62188238 ps
CPU time 0.96 seconds
Started Oct 15 12:30:04 PM UTC 24
Finished Oct 15 12:30:06 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219788478 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3219788478
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.4224408029
Short name T232
Test name
Test status
Simulation time 290112969 ps
CPU time 4.83 seconds
Started Oct 15 12:29:41 PM UTC 24
Finished Oct 15 12:29:47 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224408029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4224408029
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.260245507
Short name T373
Test name
Test status
Simulation time 51508276 ps
CPU time 0.94 seconds
Started Oct 15 12:29:22 PM UTC 24
Finished Oct 15 12:29:24 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260245507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.260245507
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.3990125013
Short name T451
Test name
Test status
Simulation time 42673313973 ps
CPU time 356.5 seconds
Started Oct 15 12:29:47 PM UTC 24
Finished Oct 15 12:35:49 PM UTC 24
Peak memory 267564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990125013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3990125013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.4107934510
Short name T150
Test name
Test status
Simulation time 11630738766 ps
CPU time 153.69 seconds
Started Oct 15 12:29:54 PM UTC 24
Finished Oct 15 12:32:30 PM UTC 24
Peak memory 261536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107934510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.4107934510
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2744649618
Short name T122
Test name
Test status
Simulation time 177523044 ps
CPU time 7.36 seconds
Started Oct 15 12:29:44 PM UTC 24
Finished Oct 15 12:29:53 PM UTC 24
Peak memory 251296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744649618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2744649618
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3509876241
Short name T229
Test name
Test status
Simulation time 52418980333 ps
CPU time 459.98 seconds
Started Oct 15 12:29:44 PM UTC 24
Finished Oct 15 12:37:30 PM UTC 24
Peak memory 261604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509876241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.3509876241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.1554387894
Short name T90
Test name
Test status
Simulation time 916524249 ps
CPU time 6.04 seconds
Started Oct 15 12:29:36 PM UTC 24
Finished Oct 15 12:29:43 PM UTC 24
Peak memory 244912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554387894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1554387894
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.3619501983
Short name T379
Test name
Test status
Simulation time 1137459353 ps
CPU time 5.24 seconds
Started Oct 15 12:29:37 PM UTC 24
Finished Oct 15 12:29:43 PM UTC 24
Peak memory 234972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619501983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3619501983
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1773355494
Short name T374
Test name
Test status
Simulation time 117144691 ps
CPU time 1.68 seconds
Started Oct 15 12:29:23 PM UTC 24
Finished Oct 15 12:29:26 PM UTC 24
Peak memory 228940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773355494 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_parity.1773355494
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.227983623
Short name T377
Test name
Test status
Simulation time 247215375 ps
CPU time 2.76 seconds
Started Oct 15 12:29:33 PM UTC 24
Finished Oct 15 12:29:37 PM UTC 24
Peak memory 234536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227983623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.227983623
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.3085660928
Short name T110
Test name
Test status
Simulation time 126512217 ps
CPU time 4.47 seconds
Started Oct 15 12:29:30 PM UTC 24
Finished Oct 15 12:29:35 PM UTC 24
Peak memory 234792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085660928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3085660928
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.750656571
Short name T157
Test name
Test status
Simulation time 169348656 ps
CPU time 6.41 seconds
Started Oct 15 12:29:46 PM UTC 24
Finished Oct 15 12:29:54 PM UTC 24
Peak memory 233224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750656571 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.750656571
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.3737473427
Short name T35
Test name
Test status
Simulation time 91934757 ps
CPU time 1.55 seconds
Started Oct 15 12:30:01 PM UTC 24
Finished Oct 15 12:30:03 PM UTC 24
Peak memory 256900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737473427 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3737473427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.1492331080
Short name T375
Test name
Test status
Simulation time 38199103 ps
CPU time 1.08 seconds
Started Oct 15 12:29:25 PM UTC 24
Finished Oct 15 12:29:27 PM UTC 24
Peak memory 213532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492331080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1492331080
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2295345041
Short name T378
Test name
Test status
Simulation time 1425538581 ps
CPU time 12.47 seconds
Started Oct 15 12:29:24 PM UTC 24
Finished Oct 15 12:29:38 PM UTC 24
Peak memory 227568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295345041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2295345041
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.3465502811
Short name T89
Test name
Test status
Simulation time 385864721 ps
CPU time 2.57 seconds
Started Oct 15 12:29:29 PM UTC 24
Finished Oct 15 12:29:32 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465502811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3465502811
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.706977335
Short name T376
Test name
Test status
Simulation time 19411141 ps
CPU time 1.2 seconds
Started Oct 15 12:29:27 PM UTC 24
Finished Oct 15 12:29:29 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706977335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.706977335
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.3028371486
Short name T57
Test name
Test status
Simulation time 2176816517 ps
CPU time 12.87 seconds
Started Oct 15 12:29:39 PM UTC 24
Finished Oct 15 12:29:53 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028371486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3028371486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/4.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.98272605
Short name T836
Test name
Test status
Simulation time 20255982 ps
CPU time 1.08 seconds
Started Oct 15 12:48:04 PM UTC 24
Finished Oct 15 12:48:06 PM UTC 24
Peak memory 216200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98272605 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.98272605
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1164831307
Short name T725
Test name
Test status
Simulation time 3037321012 ps
CPU time 7.02 seconds
Started Oct 15 12:47:57 PM UTC 24
Finished Oct 15 12:48:05 PM UTC 24
Peak memory 234868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164831307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1164831307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.3636192210
Short name T823
Test name
Test status
Simulation time 16972406 ps
CPU time 1.18 seconds
Started Oct 15 12:47:48 PM UTC 24
Finished Oct 15 12:47:51 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636192210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3636192210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.3056053258
Short name T945
Test name
Test status
Simulation time 10820176060 ps
CPU time 164.46 seconds
Started Oct 15 12:48:03 PM UTC 24
Finished Oct 15 12:50:50 PM UTC 24
Peak memory 263732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056053258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3056053258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3532064627
Short name T990
Test name
Test status
Simulation time 35591249606 ps
CPU time 253.6 seconds
Started Oct 15 12:48:03 PM UTC 24
Finished Oct 15 12:52:20 PM UTC 24
Peak memory 277836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532064627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3532064627
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1811617855
Short name T873
Test name
Test status
Simulation time 10566411904 ps
CPU time 48.96 seconds
Started Oct 15 12:48:03 PM UTC 24
Finished Oct 15 12:48:53 PM UTC 24
Peak memory 263468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811617855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.1811617855
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.1106177977
Short name T846
Test name
Test status
Simulation time 14583430780 ps
CPU time 18.81 seconds
Started Oct 15 12:47:58 PM UTC 24
Finished Oct 15 12:48:18 PM UTC 24
Peak memory 235040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106177977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1106177977
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.1477105264
Short name T830
Test name
Test status
Simulation time 34149766 ps
CPU time 3.07 seconds
Started Oct 15 12:47:56 PM UTC 24
Finished Oct 15 12:48:00 PM UTC 24
Peak memory 244892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477105264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1477105264
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.3542178834
Short name T834
Test name
Test status
Simulation time 189919805 ps
CPU time 5.07 seconds
Started Oct 15 12:47:56 PM UTC 24
Finished Oct 15 12:48:02 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542178834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3542178834
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.873556470
Short name T835
Test name
Test status
Simulation time 895124662 ps
CPU time 8.15 seconds
Started Oct 15 12:47:54 PM UTC 24
Finished Oct 15 12:48:03 PM UTC 24
Peak memory 244964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873556470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.873556470
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2131050737
Short name T828
Test name
Test status
Simulation time 143700186 ps
CPU time 2.78 seconds
Started Oct 15 12:47:53 PM UTC 24
Finished Oct 15 12:47:57 PM UTC 24
Peak memory 234540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131050737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2131050737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.1088058984
Short name T838
Test name
Test status
Simulation time 326759475 ps
CPU time 6 seconds
Started Oct 15 12:48:01 PM UTC 24
Finished Oct 15 12:48:08 PM UTC 24
Peak memory 233176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088058984 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.1088058984
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.1607012618
Short name T170
Test name
Test status
Simulation time 57827757 ps
CPU time 1.19 seconds
Started Oct 15 12:48:03 PM UTC 24
Finished Oct 15 12:48:05 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607012618 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.1607012618
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.839737446
Short name T853
Test name
Test status
Simulation time 6278621834 ps
CPU time 34.39 seconds
Started Oct 15 12:47:50 PM UTC 24
Finished Oct 15 12:48:26 PM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839737446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.839737446
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.4206635955
Short name T842
Test name
Test status
Simulation time 8084724803 ps
CPU time 20.24 seconds
Started Oct 15 12:47:50 PM UTC 24
Finished Oct 15 12:48:11 PM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206635955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4206635955
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.1829301540
Short name T826
Test name
Test status
Simulation time 277260193 ps
CPU time 1.66 seconds
Started Oct 15 12:47:51 PM UTC 24
Finished Oct 15 12:47:54 PM UTC 24
Peak memory 216060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829301540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1829301540
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.3426519379
Short name T825
Test name
Test status
Simulation time 108517867 ps
CPU time 1.14 seconds
Started Oct 15 12:47:51 PM UTC 24
Finished Oct 15 12:47:54 PM UTC 24
Peak memory 216308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426519379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3426519379
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.3800015961
Short name T832
Test name
Test status
Simulation time 34514150 ps
CPU time 2.99 seconds
Started Oct 15 12:47:57 PM UTC 24
Finished Oct 15 12:48:01 PM UTC 24
Peak memory 234512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800015961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3800015961
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/40.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.229116187
Short name T855
Test name
Test status
Simulation time 30187087 ps
CPU time 1.12 seconds
Started Oct 15 12:48:25 PM UTC 24
Finished Oct 15 12:48:28 PM UTC 24
Peak memory 216196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229116187 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.229116187
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2903411363
Short name T857
Test name
Test status
Simulation time 3568920859 ps
CPU time 14.15 seconds
Started Oct 15 12:48:14 PM UTC 24
Finished Oct 15 12:48:30 PM UTC 24
Peak memory 251444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903411363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2903411363
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.2986578766
Short name T840
Test name
Test status
Simulation time 14156327 ps
CPU time 1.19 seconds
Started Oct 15 12:48:07 PM UTC 24
Finished Oct 15 12:48:09 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986578766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2986578766
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.2780770304
Short name T861
Test name
Test status
Simulation time 4187836745 ps
CPU time 15.78 seconds
Started Oct 15 12:48:19 PM UTC 24
Finished Oct 15 12:48:36 PM UTC 24
Peak memory 234792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780770304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2780770304
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1599119137
Short name T902
Test name
Test status
Simulation time 6470390304 ps
CPU time 66.68 seconds
Started Oct 15 12:48:21 PM UTC 24
Finished Oct 15 12:49:30 PM UTC 24
Peak memory 261472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599119137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1599119137
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.770293003
Short name T1011
Test name
Test status
Simulation time 22534495464 ps
CPU time 293.88 seconds
Started Oct 15 12:48:23 PM UTC 24
Finished Oct 15 12:53:21 PM UTC 24
Peak memory 283992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770293003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.770293003
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.2986426641
Short name T889
Test name
Test status
Simulation time 21749178746 ps
CPU time 55.29 seconds
Started Oct 15 12:48:15 PM UTC 24
Finished Oct 15 12:49:12 PM UTC 24
Peak memory 249076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986426641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2986426641
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2112599590
Short name T863
Test name
Test status
Simulation time 1312151006 ps
CPU time 17.61 seconds
Started Oct 15 12:48:19 PM UTC 24
Finished Oct 15 12:48:38 PM UTC 24
Peak memory 245160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112599590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.2112599590
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.732826388
Short name T847
Test name
Test status
Simulation time 643284555 ps
CPU time 5.59 seconds
Started Oct 15 12:48:11 PM UTC 24
Finished Oct 15 12:48:19 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732826388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.732826388
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.256319019
Short name T866
Test name
Test status
Simulation time 4930927290 ps
CPU time 28.14 seconds
Started Oct 15 12:48:13 PM UTC 24
Finished Oct 15 12:48:43 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256319019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.256319019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.276727443
Short name T862
Test name
Test status
Simulation time 28465532321 ps
CPU time 25 seconds
Started Oct 15 12:48:10 PM UTC 24
Finished Oct 15 12:48:37 PM UTC 24
Peak memory 235004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276727443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.276727443
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.240675826
Short name T850
Test name
Test status
Simulation time 5743436848 ps
CPU time 11.7 seconds
Started Oct 15 12:48:10 PM UTC 24
Finished Oct 15 12:48:23 PM UTC 24
Peak memory 245032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240675826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.240675826
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2347498135
Short name T859
Test name
Test status
Simulation time 2069811612 ps
CPU time 12.95 seconds
Started Oct 15 12:48:19 PM UTC 24
Finished Oct 15 12:48:33 PM UTC 24
Peak memory 233700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347498135 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.2347498135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.4117616412
Short name T1020
Test name
Test status
Simulation time 36370695248 ps
CPU time 377.58 seconds
Started Oct 15 12:48:24 PM UTC 24
Finished Oct 15 12:54:47 PM UTC 24
Peak memory 277860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117616412 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.4117616412
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.3426894106
Short name T848
Test name
Test status
Simulation time 5254713319 ps
CPU time 11.16 seconds
Started Oct 15 12:48:08 PM UTC 24
Finished Oct 15 12:48:20 PM UTC 24
Peak memory 227432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426894106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3426894106
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2715298047
Short name T852
Test name
Test status
Simulation time 12774922887 ps
CPU time 16.36 seconds
Started Oct 15 12:48:07 PM UTC 24
Finished Oct 15 12:48:24 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715298047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2715298047
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.3787569344
Short name T844
Test name
Test status
Simulation time 126636671 ps
CPU time 1.4 seconds
Started Oct 15 12:48:10 PM UTC 24
Finished Oct 15 12:48:13 PM UTC 24
Peak memory 216212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787569344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3787569344
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.838171880
Short name T843
Test name
Test status
Simulation time 132376882 ps
CPU time 1.31 seconds
Started Oct 15 12:48:10 PM UTC 24
Finished Oct 15 12:48:13 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838171880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.838171880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.2544716437
Short name T849
Test name
Test status
Simulation time 1082557736 ps
CPU time 6 seconds
Started Oct 15 12:48:14 PM UTC 24
Finished Oct 15 12:48:22 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544716437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2544716437
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/41.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.1236164735
Short name T872
Test name
Test status
Simulation time 40438313 ps
CPU time 1.09 seconds
Started Oct 15 12:48:50 PM UTC 24
Finished Oct 15 12:48:52 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236164735 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.1236164735
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.2855661485
Short name T868
Test name
Test status
Simulation time 222906396 ps
CPU time 5.73 seconds
Started Oct 15 12:48:38 PM UTC 24
Finished Oct 15 12:48:45 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855661485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2855661485
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.3527256596
Short name T856
Test name
Test status
Simulation time 18407345 ps
CPU time 1.15 seconds
Started Oct 15 12:48:25 PM UTC 24
Finished Oct 15 12:48:28 PM UTC 24
Peak memory 213468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527256596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3527256596
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.1185522678
Short name T1004
Test name
Test status
Simulation time 143566353528 ps
CPU time 254.84 seconds
Started Oct 15 12:48:44 PM UTC 24
Finished Oct 15 12:53:03 PM UTC 24
Peak memory 261736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185522678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1185522678
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.1721723470
Short name T1028
Test name
Test status
Simulation time 64518826740 ps
CPU time 551.35 seconds
Started Oct 15 12:48:44 PM UTC 24
Finished Oct 15 12:58:03 PM UTC 24
Peak memory 277852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721723470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1721723470
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.85468074
Short name T950
Test name
Test status
Simulation time 13201392843 ps
CPU time 127.73 seconds
Started Oct 15 12:48:46 PM UTC 24
Finished Oct 15 12:50:56 PM UTC 24
Peak memory 267940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85468074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.85468074
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3428310487
Short name T880
Test name
Test status
Simulation time 1242941906 ps
CPU time 18.67 seconds
Started Oct 15 12:48:40 PM UTC 24
Finished Oct 15 12:49:00 PM UTC 24
Peak memory 244956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428310487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3428310487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.2689731942
Short name T930
Test name
Test status
Simulation time 9434356589 ps
CPU time 97.18 seconds
Started Oct 15 12:48:40 PM UTC 24
Finished Oct 15 12:50:19 PM UTC 24
Peak memory 261412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689731942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.2689731942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.1598645857
Short name T877
Test name
Test status
Simulation time 2918188463 ps
CPU time 21.37 seconds
Started Oct 15 12:48:34 PM UTC 24
Finished Oct 15 12:48:57 PM UTC 24
Peak memory 245300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598645857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1598645857
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.2709236612
Short name T883
Test name
Test status
Simulation time 2199955422 ps
CPU time 26.66 seconds
Started Oct 15 12:48:36 PM UTC 24
Finished Oct 15 12:49:04 PM UTC 24
Peak memory 251172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709236612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2709236612
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1070177601
Short name T879
Test name
Test status
Simulation time 32464431097 ps
CPU time 25.02 seconds
Started Oct 15 12:48:33 PM UTC 24
Finished Oct 15 12:48:59 PM UTC 24
Peak memory 263656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070177601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.1070177601
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.221616040
Short name T865
Test name
Test status
Simulation time 2568647730 ps
CPU time 10.11 seconds
Started Oct 15 12:48:31 PM UTC 24
Finished Oct 15 12:48:42 PM UTC 24
Peak memory 245348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221616040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.221616040
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2785572195
Short name T870
Test name
Test status
Simulation time 630243257 ps
CPU time 5.24 seconds
Started Oct 15 12:48:43 PM UTC 24
Finished Oct 15 12:48:49 PM UTC 24
Peak memory 231136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785572195 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.2785572195
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.2499037975
Short name T871
Test name
Test status
Simulation time 106867399 ps
CPU time 1.46 seconds
Started Oct 15 12:48:49 PM UTC 24
Finished Oct 15 12:48:52 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499037975 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.2499037975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.99240163
Short name T898
Test name
Test status
Simulation time 9107408822 ps
CPU time 52.23 seconds
Started Oct 15 12:48:28 PM UTC 24
Finished Oct 15 12:49:22 PM UTC 24
Peak memory 227484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99240163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.99240163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1688951325
Short name T869
Test name
Test status
Simulation time 104574997901 ps
CPU time 20.01 seconds
Started Oct 15 12:48:27 PM UTC 24
Finished Oct 15 12:48:48 PM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688951325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1688951325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.1387540336
Short name T860
Test name
Test status
Simulation time 176834638 ps
CPU time 4.28 seconds
Started Oct 15 12:48:30 PM UTC 24
Finished Oct 15 12:48:35 PM UTC 24
Peak memory 227348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387540336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1387540336
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3517091979
Short name T858
Test name
Test status
Simulation time 89162199 ps
CPU time 1.19 seconds
Started Oct 15 12:48:29 PM UTC 24
Finished Oct 15 12:48:32 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517091979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3517091979
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.1721463433
Short name T875
Test name
Test status
Simulation time 4504250618 ps
CPU time 18.69 seconds
Started Oct 15 12:48:37 PM UTC 24
Finished Oct 15 12:48:57 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721463433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1721463433
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/42.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.4224889972
Short name T892
Test name
Test status
Simulation time 14308897 ps
CPU time 1.09 seconds
Started Oct 15 12:49:13 PM UTC 24
Finished Oct 15 12:49:15 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224889972 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.4224889972
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1427243890
Short name T887
Test name
Test status
Simulation time 488907248 ps
CPU time 5.73 seconds
Started Oct 15 12:49:04 PM UTC 24
Finished Oct 15 12:49:11 PM UTC 24
Peak memory 244888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427243890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1427243890
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.2906588922
Short name T874
Test name
Test status
Simulation time 51109584 ps
CPU time 1.21 seconds
Started Oct 15 12:48:53 PM UTC 24
Finished Oct 15 12:48:55 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906588922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2906588922
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.1973751940
Short name T918
Test name
Test status
Simulation time 3549301606 ps
CPU time 45.38 seconds
Started Oct 15 12:49:07 PM UTC 24
Finished Oct 15 12:49:54 PM UTC 24
Peak memory 251232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973751940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1973751940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.867209953
Short name T995
Test name
Test status
Simulation time 22485009045 ps
CPU time 197.44 seconds
Started Oct 15 12:49:09 PM UTC 24
Finished Oct 15 12:52:30 PM UTC 24
Peak memory 261796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867209953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.867209953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3701652681
Short name T151
Test name
Test status
Simulation time 3484461303 ps
CPU time 102.77 seconds
Started Oct 15 12:49:12 PM UTC 24
Finished Oct 15 12:50:57 PM UTC 24
Peak memory 275860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701652681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.3701652681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.1930677173
Short name T905
Test name
Test status
Simulation time 3152656752 ps
CPU time 27.4 seconds
Started Oct 15 12:49:04 PM UTC 24
Finished Oct 15 12:49:33 PM UTC 24
Peak memory 245024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930677173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1930677173
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2899331484
Short name T947
Test name
Test status
Simulation time 4913349074 ps
CPU time 104.24 seconds
Started Oct 15 12:49:06 PM UTC 24
Finished Oct 15 12:50:52 PM UTC 24
Peak memory 261732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899331484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.2899331484
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.3441419904
Short name T884
Test name
Test status
Simulation time 1244960249 ps
CPU time 5.26 seconds
Started Oct 15 12:48:58 PM UTC 24
Finished Oct 15 12:49:05 PM UTC 24
Peak memory 244912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441419904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3441419904
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.1876923669
Short name T899
Test name
Test status
Simulation time 3278617954 ps
CPU time 20.29 seconds
Started Oct 15 12:49:01 PM UTC 24
Finished Oct 15 12:49:22 PM UTC 24
Peak memory 247036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876923669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1876923669
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3099915730
Short name T886
Test name
Test status
Simulation time 951776558 ps
CPU time 8.38 seconds
Started Oct 15 12:48:58 PM UTC 24
Finished Oct 15 12:49:08 PM UTC 24
Peak memory 234516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099915730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.3099915730
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3582770746
Short name T888
Test name
Test status
Simulation time 2752506069 ps
CPU time 12.1 seconds
Started Oct 15 12:48:58 PM UTC 24
Finished Oct 15 12:49:12 PM UTC 24
Peak memory 251292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582770746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3582770746
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2098185945
Short name T891
Test name
Test status
Simulation time 1361284896 ps
CPU time 8.28 seconds
Started Oct 15 12:49:06 PM UTC 24
Finished Oct 15 12:49:15 PM UTC 24
Peak memory 233224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098185945 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.2098185945
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.4105576806
Short name T893
Test name
Test status
Simulation time 40930575 ps
CPU time 1.53 seconds
Started Oct 15 12:49:13 PM UTC 24
Finished Oct 15 12:49:16 PM UTC 24
Peak memory 216328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105576806 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.4105576806
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.745436382
Short name T882
Test name
Test status
Simulation time 1338130801 ps
CPU time 6.57 seconds
Started Oct 15 12:48:55 PM UTC 24
Finished Oct 15 12:49:03 PM UTC 24
Peak memory 227296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745436382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.745436382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1087520176
Short name T885
Test name
Test status
Simulation time 1117092431 ps
CPU time 10.94 seconds
Started Oct 15 12:48:54 PM UTC 24
Finished Oct 15 12:49:06 PM UTC 24
Peak memory 227520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087520176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1087520176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.752849712
Short name T881
Test name
Test status
Simulation time 72221760 ps
CPU time 3.55 seconds
Started Oct 15 12:48:58 PM UTC 24
Finished Oct 15 12:49:03 PM UTC 24
Peak memory 227244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752849712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.752849712
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3762376222
Short name T878
Test name
Test status
Simulation time 229974984 ps
CPU time 1.19 seconds
Started Oct 15 12:48:55 PM UTC 24
Finished Oct 15 12:48:58 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762376222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3762376222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.2478490099
Short name T890
Test name
Test status
Simulation time 1226774055 ps
CPU time 11.57 seconds
Started Oct 15 12:49:01 PM UTC 24
Finished Oct 15 12:49:14 PM UTC 24
Peak memory 244860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478490099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2478490099
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/43.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.3449362573
Short name T909
Test name
Test status
Simulation time 12840694 ps
CPU time 1.13 seconds
Started Oct 15 12:49:39 PM UTC 24
Finished Oct 15 12:49:42 PM UTC 24
Peak memory 211404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449362573 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.3449362573
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3788030490
Short name T907
Test name
Test status
Simulation time 364856816 ps
CPU time 7.55 seconds
Started Oct 15 12:49:29 PM UTC 24
Finished Oct 15 12:49:38 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788030490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3788030490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.1842362494
Short name T894
Test name
Test status
Simulation time 57996474 ps
CPU time 1.18 seconds
Started Oct 15 12:49:14 PM UTC 24
Finished Oct 15 12:49:17 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842362494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1842362494
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.417202992
Short name T912
Test name
Test status
Simulation time 273934449 ps
CPU time 8.75 seconds
Started Oct 15 12:49:32 PM UTC 24
Finished Oct 15 12:49:43 PM UTC 24
Peak memory 251108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417202992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.417202992
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1153021089
Short name T1021
Test name
Test status
Simulation time 132521207492 ps
CPU time 309.99 seconds
Started Oct 15 12:49:32 PM UTC 24
Finished Oct 15 12:54:47 PM UTC 24
Peak memory 276112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153021089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1153021089
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.592043902
Short name T979
Test name
Test status
Simulation time 48031192787 ps
CPU time 142.91 seconds
Started Oct 15 12:49:34 PM UTC 24
Finished Oct 15 12:51:59 PM UTC 24
Peak memory 277912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592043902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.592043902
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.987528489
Short name T916
Test name
Test status
Simulation time 2653362539 ps
CPU time 17.75 seconds
Started Oct 15 12:49:30 PM UTC 24
Finished Oct 15 12:49:49 PM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987528489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.987528489
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2388062434
Short name T1013
Test name
Test status
Simulation time 108851306541 ps
CPU time 242.68 seconds
Started Oct 15 12:49:32 PM UTC 24
Finished Oct 15 12:53:39 PM UTC 24
Peak memory 265768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388062434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.2388062434
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.1162648416
Short name T901
Test name
Test status
Simulation time 575694339 ps
CPU time 7.29 seconds
Started Oct 15 12:49:21 PM UTC 24
Finished Oct 15 12:49:29 PM UTC 24
Peak memory 234784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162648416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1162648416
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.1240773478
Short name T911
Test name
Test status
Simulation time 2707719296 ps
CPU time 16.95 seconds
Started Oct 15 12:49:24 PM UTC 24
Finished Oct 15 12:49:42 PM UTC 24
Peak memory 261480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240773478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1240773478
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.38233778
Short name T908
Test name
Test status
Simulation time 10377239995 ps
CPU time 15.88 seconds
Started Oct 15 12:49:21 PM UTC 24
Finished Oct 15 12:49:38 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38233778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.38233778
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.3326523456
Short name T904
Test name
Test status
Simulation time 2491207102 ps
CPU time 11.16 seconds
Started Oct 15 12:49:19 PM UTC 24
Finished Oct 15 12:49:31 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326523456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3326523456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3769477094
Short name T913
Test name
Test status
Simulation time 1300220142 ps
CPU time 9.36 seconds
Started Oct 15 12:49:32 PM UTC 24
Finished Oct 15 12:49:43 PM UTC 24
Peak memory 231328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769477094 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.3769477094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.420006908
Short name T1000
Test name
Test status
Simulation time 34173934684 ps
CPU time 180.79 seconds
Started Oct 15 12:49:36 PM UTC 24
Finished Oct 15 12:52:40 PM UTC 24
Peak memory 283980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420006908 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.420006908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.1845646430
Short name T906
Test name
Test status
Simulation time 13540884683 ps
CPU time 17.99 seconds
Started Oct 15 12:49:16 PM UTC 24
Finished Oct 15 12:49:35 PM UTC 24
Peak memory 227432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845646430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1845646430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1316229358
Short name T903
Test name
Test status
Simulation time 6012634590 ps
CPU time 13.43 seconds
Started Oct 15 12:49:16 PM UTC 24
Finished Oct 15 12:49:30 PM UTC 24
Peak memory 227468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316229358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1316229358
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.3007365866
Short name T897
Test name
Test status
Simulation time 197924891 ps
CPU time 1.42 seconds
Started Oct 15 12:49:17 PM UTC 24
Finished Oct 15 12:49:20 PM UTC 24
Peak memory 226476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007365866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3007365866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.3245166822
Short name T896
Test name
Test status
Simulation time 123477944 ps
CPU time 1.19 seconds
Started Oct 15 12:49:17 PM UTC 24
Finished Oct 15 12:49:19 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245166822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3245166822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.3757559731
Short name T900
Test name
Test status
Simulation time 171502857 ps
CPU time 3.05 seconds
Started Oct 15 12:49:24 PM UTC 24
Finished Oct 15 12:49:28 PM UTC 24
Peak memory 234076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757559731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3757559731
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/44.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.1339408755
Short name T927
Test name
Test status
Simulation time 114053817 ps
CPU time 1.08 seconds
Started Oct 15 12:50:07 PM UTC 24
Finished Oct 15 12:50:09 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339408755 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.1339408755
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1780647749
Short name T921
Test name
Test status
Simulation time 356598997 ps
CPU time 3.44 seconds
Started Oct 15 12:49:55 PM UTC 24
Finished Oct 15 12:50:00 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780647749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1780647749
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.1339737752
Short name T910
Test name
Test status
Simulation time 39228777 ps
CPU time 1.16 seconds
Started Oct 15 12:49:39 PM UTC 24
Finished Oct 15 12:49:42 PM UTC 24
Peak memory 213468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339737752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1339737752
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3022052361
Short name T1009
Test name
Test status
Simulation time 42826896618 ps
CPU time 191.51 seconds
Started Oct 15 12:50:00 PM UTC 24
Finished Oct 15 12:53:15 PM UTC 24
Peak memory 261544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022052361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3022052361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1543292737
Short name T1018
Test name
Test status
Simulation time 19201552420 ps
CPU time 259.68 seconds
Started Oct 15 12:50:02 PM UTC 24
Finished Oct 15 12:54:25 PM UTC 24
Peak memory 267724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543292737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1543292737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.889057816
Short name T955
Test name
Test status
Simulation time 9126998307 ps
CPU time 60.86 seconds
Started Oct 15 12:50:03 PM UTC 24
Finished Oct 15 12:51:05 PM UTC 24
Peak memory 263516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889057816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.889057816
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.614859688
Short name T924
Test name
Test status
Simulation time 234086112 ps
CPU time 5.29 seconds
Started Oct 15 12:49:58 PM UTC 24
Finished Oct 15 12:50:04 PM UTC 24
Peak memory 251104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614859688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.614859688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.4156359299
Short name T961
Test name
Test status
Simulation time 11909304811 ps
CPU time 81.25 seconds
Started Oct 15 12:49:58 PM UTC 24
Finished Oct 15 12:51:21 PM UTC 24
Peak memory 265704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156359299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.4156359299
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.3565493578
Short name T919
Test name
Test status
Simulation time 208886930 ps
CPU time 5.39 seconds
Started Oct 15 12:49:49 PM UTC 24
Finished Oct 15 12:49:56 PM UTC 24
Peak memory 234976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565493578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3565493578
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.3666787679
Short name T923
Test name
Test status
Simulation time 3096292556 ps
CPU time 10.26 seconds
Started Oct 15 12:49:51 PM UTC 24
Finished Oct 15 12:50:02 PM UTC 24
Peak memory 245284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666787679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3666787679
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.428866518
Short name T925
Test name
Test status
Simulation time 2310189796 ps
CPU time 16.46 seconds
Started Oct 15 12:49:47 PM UTC 24
Finished Oct 15 12:50:05 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428866518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.428866518
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3041382155
Short name T917
Test name
Test status
Simulation time 1156840411 ps
CPU time 6.26 seconds
Started Oct 15 12:49:45 PM UTC 24
Finished Oct 15 12:49:52 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041382155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3041382155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2230450284
Short name T926
Test name
Test status
Simulation time 2709280718 ps
CPU time 5.87 seconds
Started Oct 15 12:49:59 PM UTC 24
Finished Oct 15 12:50:06 PM UTC 24
Peak memory 233564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230450284 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.2230450284
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.3820535681
Short name T1025
Test name
Test status
Simulation time 56972444751 ps
CPU time 422.37 seconds
Started Oct 15 12:50:05 PM UTC 24
Finished Oct 15 12:57:13 PM UTC 24
Peak memory 261480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820535681 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.3820535681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.1618686781
Short name T920
Test name
Test status
Simulation time 1702628084 ps
CPU time 13.34 seconds
Started Oct 15 12:49:43 PM UTC 24
Finished Oct 15 12:49:58 PM UTC 24
Peak memory 227244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618686781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1618686781
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3104579949
Short name T922
Test name
Test status
Simulation time 5192778796 ps
CPU time 15.52 seconds
Started Oct 15 12:49:43 PM UTC 24
Finished Oct 15 12:50:00 PM UTC 24
Peak memory 227396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104579949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3104579949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.1614751729
Short name T915
Test name
Test status
Simulation time 256113949 ps
CPU time 2.27 seconds
Started Oct 15 12:49:45 PM UTC 24
Finished Oct 15 12:49:48 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614751729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1614751729
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1828314443
Short name T914
Test name
Test status
Simulation time 43037849 ps
CPU time 1.29 seconds
Started Oct 15 12:49:43 PM UTC 24
Finished Oct 15 12:49:45 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828314443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1828314443
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.3478514529
Short name T297
Test name
Test status
Simulation time 352441803 ps
CPU time 2.83 seconds
Started Oct 15 12:49:53 PM UTC 24
Finished Oct 15 12:49:57 PM UTC 24
Peak memory 245160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478514529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3478514529
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/45.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3798144165
Short name T948
Test name
Test status
Simulation time 14579261 ps
CPU time 1.13 seconds
Started Oct 15 12:50:52 PM UTC 24
Finished Oct 15 12:50:54 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798144165 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.3798144165
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2321804973
Short name T940
Test name
Test status
Simulation time 4621652675 ps
CPU time 6.14 seconds
Started Oct 15 12:50:31 PM UTC 24
Finished Oct 15 12:50:39 PM UTC 24
Peak memory 234776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321804973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2321804973
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.2004369264
Short name T928
Test name
Test status
Simulation time 26869899 ps
CPU time 1.2 seconds
Started Oct 15 12:50:07 PM UTC 24
Finished Oct 15 12:50:09 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004369264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2004369264
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.2450481688
Short name T1029
Test name
Test status
Simulation time 196254118415 ps
CPU time 440.44 seconds
Started Oct 15 12:50:39 PM UTC 24
Finished Oct 15 12:58:05 PM UTC 24
Peak memory 277800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450481688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2450481688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3583556818
Short name T251
Test name
Test status
Simulation time 5611130610 ps
CPU time 125.07 seconds
Started Oct 15 12:50:41 PM UTC 24
Finished Oct 15 12:52:48 PM UTC 24
Peak memory 277920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583556818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3583556818
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.1983087004
Short name T368
Test name
Test status
Simulation time 996718161269 ps
CPU time 722.68 seconds
Started Oct 15 12:50:43 PM UTC 24
Finished Oct 15 01:02:54 PM UTC 24
Peak memory 284232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983087004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.1983087004
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.1854035344
Short name T942
Test name
Test status
Simulation time 511702906 ps
CPU time 6.58 seconds
Started Oct 15 12:50:34 PM UTC 24
Finished Oct 15 12:50:41 PM UTC 24
Peak memory 234652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854035344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1854035344
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3413250470
Short name T1007
Test name
Test status
Simulation time 72905891549 ps
CPU time 150.67 seconds
Started Oct 15 12:50:34 PM UTC 24
Finished Oct 15 12:53:07 PM UTC 24
Peak memory 261416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413250470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.3413250470
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.2932142643
Short name T938
Test name
Test status
Simulation time 1879189847 ps
CPU time 6.55 seconds
Started Oct 15 12:50:26 PM UTC 24
Finished Oct 15 12:50:33 PM UTC 24
Peak memory 234936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932142643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2932142643
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.696684068
Short name T944
Test name
Test status
Simulation time 6355226397 ps
CPU time 21.98 seconds
Started Oct 15 12:50:27 PM UTC 24
Finished Oct 15 12:50:50 PM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696684068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.696684068
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.951887599
Short name T937
Test name
Test status
Simulation time 4806168368 ps
CPU time 9.78 seconds
Started Oct 15 12:50:22 PM UTC 24
Finished Oct 15 12:50:33 PM UTC 24
Peak memory 235104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951887599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.951887599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1293751315
Short name T936
Test name
Test status
Simulation time 470490359 ps
CPU time 7.32 seconds
Started Oct 15 12:50:22 PM UTC 24
Finished Oct 15 12:50:31 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293751315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1293751315
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.950206905
Short name T943
Test name
Test status
Simulation time 346672199 ps
CPU time 7.64 seconds
Started Oct 15 12:50:39 PM UTC 24
Finished Oct 15 12:50:48 PM UTC 24
Peak memory 233484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950206905 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.950206905
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.1574936361
Short name T946
Test name
Test status
Simulation time 69477125 ps
CPU time 1.38 seconds
Started Oct 15 12:50:49 PM UTC 24
Finished Oct 15 12:50:51 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574936361 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.1574936361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.2660412112
Short name T933
Test name
Test status
Simulation time 2173805135 ps
CPU time 13.01 seconds
Started Oct 15 12:50:10 PM UTC 24
Finished Oct 15 12:50:24 PM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660412112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2660412112
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1288303318
Short name T934
Test name
Test status
Simulation time 1106961657 ps
CPU time 14.61 seconds
Started Oct 15 12:50:10 PM UTC 24
Finished Oct 15 12:50:26 PM UTC 24
Peak memory 227204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288303318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1288303318
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1063737979
Short name T932
Test name
Test status
Simulation time 51856795 ps
CPU time 0.88 seconds
Started Oct 15 12:50:20 PM UTC 24
Finished Oct 15 12:50:22 PM UTC 24
Peak memory 213472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063737979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1063737979
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.4060654357
Short name T931
Test name
Test status
Simulation time 128551352 ps
CPU time 1.38 seconds
Started Oct 15 12:50:18 PM UTC 24
Finished Oct 15 12:50:21 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060654357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4060654357
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.2431539033
Short name T939
Test name
Test status
Simulation time 4544217793 ps
CPU time 6.59 seconds
Started Oct 15 12:50:30 PM UTC 24
Finished Oct 15 12:50:38 PM UTC 24
Peak memory 245032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431539033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2431539033
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/46.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.51640095
Short name T963
Test name
Test status
Simulation time 34661525 ps
CPU time 1.12 seconds
Started Oct 15 12:51:23 PM UTC 24
Finished Oct 15 12:51:25 PM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51640095 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.51640095
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2723568599
Short name T956
Test name
Test status
Simulation time 70479748 ps
CPU time 3.63 seconds
Started Oct 15 12:51:04 PM UTC 24
Finished Oct 15 12:51:09 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723568599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2723568599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.2695838421
Short name T949
Test name
Test status
Simulation time 40362965 ps
CPU time 1.15 seconds
Started Oct 15 12:50:52 PM UTC 24
Finished Oct 15 12:50:54 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695838421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2695838421
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.3535993565
Short name T1006
Test name
Test status
Simulation time 89556578356 ps
CPU time 107.82 seconds
Started Oct 15 12:51:13 PM UTC 24
Finished Oct 15 12:53:03 PM UTC 24
Peak memory 263716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535993565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3535993565
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3417909808
Short name T1015
Test name
Test status
Simulation time 109356024821 ps
CPU time 180.14 seconds
Started Oct 15 12:51:13 PM UTC 24
Finished Oct 15 12:54:16 PM UTC 24
Peak memory 261712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417909808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3417909808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2916931400
Short name T1012
Test name
Test status
Simulation time 10915297887 ps
CPU time 125.34 seconds
Started Oct 15 12:51:17 PM UTC 24
Finished Oct 15 12:53:25 PM UTC 24
Peak memory 273760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916931400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.2916931400
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.3928959737
Short name T965
Test name
Test status
Simulation time 3410463516 ps
CPU time 21 seconds
Started Oct 15 12:51:06 PM UTC 24
Finished Oct 15 12:51:28 PM UTC 24
Peak memory 245300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928959737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3928959737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2907589949
Short name T1005
Test name
Test status
Simulation time 13259703384 ps
CPU time 113.49 seconds
Started Oct 15 12:51:07 PM UTC 24
Finished Oct 15 12:53:03 PM UTC 24
Peak memory 265504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907589949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.2907589949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.3805881720
Short name T966
Test name
Test status
Simulation time 4488956793 ps
CPU time 27.94 seconds
Started Oct 15 12:50:58 PM UTC 24
Finished Oct 15 12:51:28 PM UTC 24
Peak memory 244116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805881720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3805881720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.270201013
Short name T959
Test name
Test status
Simulation time 3037981065 ps
CPU time 14.34 seconds
Started Oct 15 12:51:00 PM UTC 24
Finished Oct 15 12:51:16 PM UTC 24
Peak memory 234788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270201013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.270201013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2647932216
Short name T957
Test name
Test status
Simulation time 3280663423 ps
CPU time 11.61 seconds
Started Oct 15 12:50:58 PM UTC 24
Finished Oct 15 12:51:12 PM UTC 24
Peak memory 245008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647932216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.2647932216
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.931848154
Short name T958
Test name
Test status
Simulation time 4177943528 ps
CPU time 14.16 seconds
Started Oct 15 12:50:56 PM UTC 24
Finished Oct 15 12:51:12 PM UTC 24
Peak memory 251496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931848154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.931848154
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2235682892
Short name T969
Test name
Test status
Simulation time 1959295116 ps
CPU time 22.96 seconds
Started Oct 15 12:51:10 PM UTC 24
Finished Oct 15 12:51:35 PM UTC 24
Peak memory 231072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235682892 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.2235682892
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.1765910393
Short name T962
Test name
Test status
Simulation time 159936309 ps
CPU time 1.51 seconds
Started Oct 15 12:51:21 PM UTC 24
Finished Oct 15 12:51:24 PM UTC 24
Peak memory 226392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765910393 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.1765910393
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.1746738152
Short name T960
Test name
Test status
Simulation time 3421741513 ps
CPU time 25.98 seconds
Started Oct 15 12:50:53 PM UTC 24
Finished Oct 15 12:51:20 PM UTC 24
Peak memory 230724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746738152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1746738152
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.491443525
Short name T954
Test name
Test status
Simulation time 958408528 ps
CPU time 10.68 seconds
Started Oct 15 12:50:53 PM UTC 24
Finished Oct 15 12:51:05 PM UTC 24
Peak memory 226396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491443525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.491443525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.694482766
Short name T952
Test name
Test status
Simulation time 60083174 ps
CPU time 2.05 seconds
Started Oct 15 12:50:56 PM UTC 24
Finished Oct 15 12:50:59 PM UTC 24
Peak memory 227540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694482766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.694482766
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.199773414
Short name T951
Test name
Test status
Simulation time 66211416 ps
CPU time 1.45 seconds
Started Oct 15 12:50:56 PM UTC 24
Finished Oct 15 12:50:59 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199773414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.199773414
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.2715584921
Short name T974
Test name
Test status
Simulation time 139733617087 ps
CPU time 46.94 seconds
Started Oct 15 12:51:00 PM UTC 24
Finished Oct 15 12:51:49 PM UTC 24
Peak memory 234780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715584921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2715584921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/47.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.1314998139
Short name T980
Test name
Test status
Simulation time 55775070 ps
CPU time 1.07 seconds
Started Oct 15 12:51:59 PM UTC 24
Finished Oct 15 12:52:01 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314998139 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.1314998139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2731358863
Short name T972
Test name
Test status
Simulation time 250778178 ps
CPU time 4.89 seconds
Started Oct 15 12:51:38 PM UTC 24
Finished Oct 15 12:51:44 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731358863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2731358863
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.1227575398
Short name T964
Test name
Test status
Simulation time 46665817 ps
CPU time 1.2 seconds
Started Oct 15 12:51:25 PM UTC 24
Finished Oct 15 12:51:27 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227575398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1227575398
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.4092255963
Short name T270
Test name
Test status
Simulation time 3141591566 ps
CPU time 38.88 seconds
Started Oct 15 12:51:50 PM UTC 24
Finished Oct 15 12:52:30 PM UTC 24
Peak memory 247080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092255963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4092255963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2079133966
Short name T1026
Test name
Test status
Simulation time 129092517729 ps
CPU time 319.96 seconds
Started Oct 15 12:51:54 PM UTC 24
Finished Oct 15 12:57:18 PM UTC 24
Peak memory 267872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079133966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2079133966
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2704269654
Short name T1022
Test name
Test status
Simulation time 15556367256 ps
CPU time 178.71 seconds
Started Oct 15 12:51:55 PM UTC 24
Finished Oct 15 12:54:57 PM UTC 24
Peak memory 267868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704269654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.2704269654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.1589269614
Short name T987
Test name
Test status
Simulation time 2088484689 ps
CPU time 23.74 seconds
Started Oct 15 12:51:45 PM UTC 24
Finished Oct 15 12:52:10 PM UTC 24
Peak memory 247000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589269614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1589269614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3691406683
Short name T977
Test name
Test status
Simulation time 4943816750 ps
CPU time 10.12 seconds
Started Oct 15 12:51:46 PM UTC 24
Finished Oct 15 12:51:58 PM UTC 24
Peak memory 235040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691406683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.3691406683
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.2271776212
Short name T978
Test name
Test status
Simulation time 7586024285 ps
CPU time 20.37 seconds
Started Oct 15 12:51:36 PM UTC 24
Finished Oct 15 12:51:58 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271776212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2271776212
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.481684567
Short name T975
Test name
Test status
Simulation time 9575969351 ps
CPU time 15.46 seconds
Started Oct 15 12:51:36 PM UTC 24
Finished Oct 15 12:51:53 PM UTC 24
Peak memory 261412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481684567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.481684567
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2933582107
Short name T983
Test name
Test status
Simulation time 21869380177 ps
CPU time 25.5 seconds
Started Oct 15 12:51:36 PM UTC 24
Finished Oct 15 12:52:03 PM UTC 24
Peak memory 234748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933582107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.2933582107
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.458708073
Short name T970
Test name
Test status
Simulation time 63593784 ps
CPU time 2.96 seconds
Started Oct 15 12:51:31 PM UTC 24
Finished Oct 15 12:51:35 PM UTC 24
Peak memory 239388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458708073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.458708073
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1042016875
Short name T976
Test name
Test status
Simulation time 353083673 ps
CPU time 4.99 seconds
Started Oct 15 12:51:48 PM UTC 24
Finished Oct 15 12:51:55 PM UTC 24
Peak memory 233320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042016875 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.1042016875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.1650128291
Short name T981
Test name
Test status
Simulation time 107660215 ps
CPU time 1.51 seconds
Started Oct 15 12:51:59 PM UTC 24
Finished Oct 15 12:52:02 PM UTC 24
Peak memory 216328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650128291 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.1650128291
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.2738345216
Short name T973
Test name
Test status
Simulation time 6056125383 ps
CPU time 15.21 seconds
Started Oct 15 12:51:29 PM UTC 24
Finished Oct 15 12:51:45 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738345216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2738345216
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3106062662
Short name T968
Test name
Test status
Simulation time 1473071898 ps
CPU time 6.75 seconds
Started Oct 15 12:51:26 PM UTC 24
Finished Oct 15 12:51:34 PM UTC 24
Peak memory 227204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106062662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3106062662
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.494101106
Short name T971
Test name
Test status
Simulation time 456126643 ps
CPU time 5.72 seconds
Started Oct 15 12:51:30 PM UTC 24
Finished Oct 15 12:51:37 PM UTC 24
Peak memory 227284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494101106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.494101106
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1897472843
Short name T967
Test name
Test status
Simulation time 110467594 ps
CPU time 1.13 seconds
Started Oct 15 12:51:29 PM UTC 24
Finished Oct 15 12:51:31 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897472843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1897472843
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.776379435
Short name T986
Test name
Test status
Simulation time 16798966874 ps
CPU time 30.11 seconds
Started Oct 15 12:51:38 PM UTC 24
Finished Oct 15 12:52:09 PM UTC 24
Peak memory 244988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776379435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.776379435
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/48.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.74698736
Short name T998
Test name
Test status
Simulation time 41187998 ps
CPU time 1.1 seconds
Started Oct 15 12:52:32 PM UTC 24
Finished Oct 15 12:52:34 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74698736 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.74698736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1208755852
Short name T994
Test name
Test status
Simulation time 738515167 ps
CPU time 7.57 seconds
Started Oct 15 12:52:20 PM UTC 24
Finished Oct 15 12:52:29 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208755852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1208755852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.4219858101
Short name T982
Test name
Test status
Simulation time 21886734 ps
CPU time 1.14 seconds
Started Oct 15 12:52:00 PM UTC 24
Finished Oct 15 12:52:02 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219858101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4219858101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.483876246
Short name T1027
Test name
Test status
Simulation time 170003553672 ps
CPU time 320.63 seconds
Started Oct 15 12:52:25 PM UTC 24
Finished Oct 15 12:57:51 PM UTC 24
Peak memory 277796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483876246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.483876246
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.1254491641
Short name T1008
Test name
Test status
Simulation time 11016518673 ps
CPU time 37.3 seconds
Started Oct 15 12:52:29 PM UTC 24
Finished Oct 15 12:53:08 PM UTC 24
Peak memory 251492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254491641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1254491641
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3381962329
Short name T1017
Test name
Test status
Simulation time 33783408333 ps
CPU time 110.39 seconds
Started Oct 15 12:52:30 PM UTC 24
Finished Oct 15 12:54:23 PM UTC 24
Peak memory 277852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381962329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.3381962329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.2081464553
Short name T1002
Test name
Test status
Simulation time 5067582430 ps
CPU time 17.81 seconds
Started Oct 15 12:52:22 PM UTC 24
Finished Oct 15 12:52:42 PM UTC 24
Peak memory 234780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081464553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2081464553
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1407211543
Short name T1024
Test name
Test status
Simulation time 74978799419 ps
CPU time 249.29 seconds
Started Oct 15 12:52:22 PM UTC 24
Finished Oct 15 12:56:35 PM UTC 24
Peak memory 261376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407211543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.1407211543
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.4025578041
Short name T991
Test name
Test status
Simulation time 769679939 ps
CPU time 9.15 seconds
Started Oct 15 12:52:10 PM UTC 24
Finished Oct 15 12:52:20 PM UTC 24
Peak memory 245156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025578041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4025578041
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.1993686261
Short name T989
Test name
Test status
Simulation time 303496312 ps
CPU time 6.08 seconds
Started Oct 15 12:52:11 PM UTC 24
Finished Oct 15 12:52:19 PM UTC 24
Peak memory 244980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993686261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1993686261
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.1036162910
Short name T996
Test name
Test status
Simulation time 2869675733 ps
CPU time 18.86 seconds
Started Oct 15 12:52:10 PM UTC 24
Finished Oct 15 12:52:30 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036162910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.1036162910
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.2966729833
Short name T988
Test name
Test status
Simulation time 658118023 ps
CPU time 4.66 seconds
Started Oct 15 12:52:08 PM UTC 24
Finished Oct 15 12:52:13 PM UTC 24
Peak memory 244916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966729833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2966729833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.2760128812
Short name T999
Test name
Test status
Simulation time 1370624188 ps
CPU time 11.92 seconds
Started Oct 15 12:52:22 PM UTC 24
Finished Oct 15 12:52:36 PM UTC 24
Peak memory 233176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760128812 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.2760128812
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.3737089440
Short name T1016
Test name
Test status
Simulation time 15917047690 ps
CPU time 107.58 seconds
Started Oct 15 12:52:32 PM UTC 24
Finished Oct 15 12:54:22 PM UTC 24
Peak memory 267896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737089440 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.3737089440
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.1355028033
Short name T997
Test name
Test status
Simulation time 16584328698 ps
CPU time 29.16 seconds
Started Oct 15 12:52:03 PM UTC 24
Finished Oct 15 12:52:33 PM UTC 24
Peak memory 227416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355028033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1355028033
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3302442211
Short name T993
Test name
Test status
Simulation time 14241828316 ps
CPU time 23.58 seconds
Started Oct 15 12:52:03 PM UTC 24
Finished Oct 15 12:52:28 PM UTC 24
Peak memory 227456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302442211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3302442211
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.3760734463
Short name T985
Test name
Test status
Simulation time 643884674 ps
CPU time 3.23 seconds
Started Oct 15 12:52:04 PM UTC 24
Finished Oct 15 12:52:09 PM UTC 24
Peak memory 227668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760734463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3760734463
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2025360642
Short name T984
Test name
Test status
Simulation time 436579919 ps
CPU time 1.66 seconds
Started Oct 15 12:52:04 PM UTC 24
Finished Oct 15 12:52:07 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025360642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2025360642
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.3704072758
Short name T992
Test name
Test status
Simulation time 1066019253 ps
CPU time 7.81 seconds
Started Oct 15 12:52:15 PM UTC 24
Finished Oct 15 12:52:24 PM UTC 24
Peak memory 234940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704072758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3704072758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/49.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.2354743570
Short name T385
Test name
Test status
Simulation time 14703353 ps
CPU time 1.07 seconds
Started Oct 15 12:30:44 PM UTC 24
Finished Oct 15 12:30:46 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354743570 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2354743570
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2941491531
Short name T182
Test name
Test status
Simulation time 221693147 ps
CPU time 3.9 seconds
Started Oct 15 12:30:30 PM UTC 24
Finished Oct 15 12:30:35 PM UTC 24
Peak memory 245168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941491531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2941491531
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.116613455
Short name T381
Test name
Test status
Simulation time 17495853 ps
CPU time 1.19 seconds
Started Oct 15 12:30:07 PM UTC 24
Finished Oct 15 12:30:09 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116613455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.116613455
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.615804581
Short name T181
Test name
Test status
Simulation time 16167865340 ps
CPU time 86.58 seconds
Started Oct 15 12:30:36 PM UTC 24
Finished Oct 15 12:32:05 PM UTC 24
Peak memory 263588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615804581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.615804581
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.1528873377
Short name T172
Test name
Test status
Simulation time 1316663889 ps
CPU time 28.49 seconds
Started Oct 15 12:30:42 PM UTC 24
Finished Oct 15 12:31:12 PM UTC 24
Peak memory 234984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528873377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.1528873377
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.2947265046
Short name T107
Test name
Test status
Simulation time 337113562 ps
CPU time 7 seconds
Started Oct 15 12:30:32 PM UTC 24
Finished Oct 15 12:30:40 PM UTC 24
Peak memory 244952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947265046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2947265046
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.4118188583
Short name T252
Test name
Test status
Simulation time 96493671613 ps
CPU time 426.02 seconds
Started Oct 15 12:30:35 PM UTC 24
Finished Oct 15 12:37:47 PM UTC 24
Peak memory 261420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118188583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.4118188583
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.381391244
Short name T191
Test name
Test status
Simulation time 1064129022 ps
CPU time 25.64 seconds
Started Oct 15 12:30:26 PM UTC 24
Finished Oct 15 12:30:53 PM UTC 24
Peak memory 251040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381391244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.381391244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.1816394989
Short name T382
Test name
Test status
Simulation time 125346937 ps
CPU time 1.61 seconds
Started Oct 15 12:30:10 PM UTC 24
Finished Oct 15 12:30:13 PM UTC 24
Peak memory 228940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816394989 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mem_parity.1816394989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.2923380370
Short name T66
Test name
Test status
Simulation time 3991160994 ps
CPU time 15.88 seconds
Started Oct 15 12:30:24 PM UTC 24
Finished Oct 15 12:30:41 PM UTC 24
Peak memory 244988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923380370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.2923380370
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1011434076
Short name T246
Test name
Test status
Simulation time 685175004 ps
CPU time 7.41 seconds
Started Oct 15 12:30:21 PM UTC 24
Finished Oct 15 12:30:29 PM UTC 24
Peak memory 245092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011434076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1011434076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1252422187
Short name T158
Test name
Test status
Simulation time 5967792316 ps
CPU time 20.8 seconds
Started Oct 15 12:30:36 PM UTC 24
Finished Oct 15 12:30:59 PM UTC 24
Peak memory 233360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252422187 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.1252422187
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.1866068886
Short name T356
Test name
Test status
Simulation time 6020730494 ps
CPU time 9.66 seconds
Started Oct 15 12:30:13 PM UTC 24
Finished Oct 15 12:30:24 PM UTC 24
Peak memory 227404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866068886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1866068886
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3332413490
Short name T384
Test name
Test status
Simulation time 1266432400 ps
CPU time 6.72 seconds
Started Oct 15 12:30:12 PM UTC 24
Finished Oct 15 12:30:20 PM UTC 24
Peak memory 227224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332413490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3332413490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.4246469256
Short name T104
Test name
Test status
Simulation time 72101931 ps
CPU time 4.1 seconds
Started Oct 15 12:30:17 PM UTC 24
Finished Oct 15 12:30:23 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246469256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4246469256
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.4073135032
Short name T383
Test name
Test status
Simulation time 67818986 ps
CPU time 1.56 seconds
Started Oct 15 12:30:14 PM UTC 24
Finished Oct 15 12:30:17 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073135032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4073135032
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.805492020
Short name T212
Test name
Test status
Simulation time 211511092 ps
CPU time 4.68 seconds
Started Oct 15 12:30:30 PM UTC 24
Finished Oct 15 12:30:36 PM UTC 24
Peak memory 244904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805492020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.805492020
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/5.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.2521690127
Short name T393
Test name
Test status
Simulation time 16448229 ps
CPU time 1.22 seconds
Started Oct 15 12:31:23 PM UTC 24
Finished Oct 15 12:31:25 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521690127 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2521690127
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3871281411
Short name T391
Test name
Test status
Simulation time 65431936 ps
CPU time 2.36 seconds
Started Oct 15 12:31:10 PM UTC 24
Finished Oct 15 12:31:13 PM UTC 24
Peak memory 244832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871281411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3871281411
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3072270196
Short name T386
Test name
Test status
Simulation time 43995052 ps
CPU time 1.12 seconds
Started Oct 15 12:30:47 PM UTC 24
Finished Oct 15 12:30:49 PM UTC 24
Peak memory 213544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072270196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3072270196
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.4239946502
Short name T302
Test name
Test status
Simulation time 6173619856 ps
CPU time 52.2 seconds
Started Oct 15 12:31:14 PM UTC 24
Finished Oct 15 12:32:08 PM UTC 24
Peak memory 251444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239946502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.4239946502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.3353834385
Short name T392
Test name
Test status
Simulation time 113729339 ps
CPU time 4.8 seconds
Started Oct 15 12:31:12 PM UTC 24
Finished Oct 15 12:31:18 PM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353834385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3353834385
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.3085438926
Short name T111
Test name
Test status
Simulation time 7233242782 ps
CPU time 56.93 seconds
Started Oct 15 12:31:12 PM UTC 24
Finished Oct 15 12:32:11 PM UTC 24
Peak memory 249132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085438926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.3085438926
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.2964814821
Short name T237
Test name
Test status
Simulation time 128404145 ps
CPU time 2.92 seconds
Started Oct 15 12:31:06 PM UTC 24
Finished Oct 15 12:31:10 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964814821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2964814821
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.3692392720
Short name T209
Test name
Test status
Simulation time 13208498319 ps
CPU time 30.64 seconds
Started Oct 15 12:31:06 PM UTC 24
Finished Oct 15 12:31:38 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692392720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3692392720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.3302879217
Short name T387
Test name
Test status
Simulation time 93811888 ps
CPU time 1.39 seconds
Started Oct 15 12:30:50 PM UTC 24
Finished Oct 15 12:30:52 PM UTC 24
Peak memory 229000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302879217 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.3302879217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1060358252
Short name T58
Test name
Test status
Simulation time 195444613 ps
CPU time 6.59 seconds
Started Oct 15 12:31:04 PM UTC 24
Finished Oct 15 12:31:11 PM UTC 24
Peak memory 244968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060358252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.1060358252
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1729600328
Short name T177
Test name
Test status
Simulation time 29518663261 ps
CPU time 28.29 seconds
Started Oct 15 12:31:03 PM UTC 24
Finished Oct 15 12:31:32 PM UTC 24
Peak memory 251192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729600328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1729600328
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2756041999
Short name T159
Test name
Test status
Simulation time 307534059 ps
CPU time 5.78 seconds
Started Oct 15 12:31:13 PM UTC 24
Finished Oct 15 12:31:20 PM UTC 24
Peak memory 233180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756041999 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.2756041999
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.1348892960
Short name T37
Test name
Test status
Simulation time 27666958702 ps
CPU time 63.43 seconds
Started Oct 15 12:31:21 PM UTC 24
Finished Oct 15 12:32:26 PM UTC 24
Peak memory 261468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348892960 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.1348892960
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.270612100
Short name T363
Test name
Test status
Simulation time 337440825 ps
CPU time 5.36 seconds
Started Oct 15 12:30:54 PM UTC 24
Finished Oct 15 12:31:01 PM UTC 24
Peak memory 227276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270612100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.270612100
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2045719599
Short name T389
Test name
Test status
Simulation time 9393067777 ps
CPU time 10.28 seconds
Started Oct 15 12:30:53 PM UTC 24
Finished Oct 15 12:31:05 PM UTC 24
Peak memory 227412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045719599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2045719599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.705183278
Short name T366
Test name
Test status
Simulation time 43034670 ps
CPU time 2.09 seconds
Started Oct 15 12:31:01 PM UTC 24
Finished Oct 15 12:31:05 PM UTC 24
Peak memory 216996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705183278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.705183278
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.1658980594
Short name T388
Test name
Test status
Simulation time 239477335 ps
CPU time 1.42 seconds
Started Oct 15 12:30:59 PM UTC 24
Finished Oct 15 12:31:02 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658980594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1658980594
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.1383112668
Short name T390
Test name
Test status
Simulation time 240118396 ps
CPU time 2.79 seconds
Started Oct 15 12:31:08 PM UTC 24
Finished Oct 15 12:31:12 PM UTC 24
Peak memory 234604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383112668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1383112668
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/6.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.456071220
Short name T144
Test name
Test status
Simulation time 40762154 ps
CPU time 1.19 seconds
Started Oct 15 12:32:13 PM UTC 24
Finished Oct 15 12:32:15 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456071220 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.456071220
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2531802305
Short name T398
Test name
Test status
Simulation time 384335044 ps
CPU time 6.91 seconds
Started Oct 15 12:31:55 PM UTC 24
Finished Oct 15 12:32:03 PM UTC 24
Peak memory 234672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531802305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2531802305
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.2239131721
Short name T394
Test name
Test status
Simulation time 15496458 ps
CPU time 1.14 seconds
Started Oct 15 12:31:24 PM UTC 24
Finished Oct 15 12:31:26 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239131721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2239131721
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.2130485117
Short name T176
Test name
Test status
Simulation time 38442330229 ps
CPU time 125.77 seconds
Started Oct 15 12:32:06 PM UTC 24
Finished Oct 15 12:34:15 PM UTC 24
Peak memory 261428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130485117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2130485117
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.686517927
Short name T301
Test name
Test status
Simulation time 14963617895 ps
CPU time 59.93 seconds
Started Oct 15 12:32:09 PM UTC 24
Finished Oct 15 12:33:10 PM UTC 24
Peak memory 263800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686517927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.686517927
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.286051068
Short name T318
Test name
Test status
Simulation time 15547875568 ps
CPU time 166.9 seconds
Started Oct 15 12:32:12 PM UTC 24
Finished Oct 15 12:35:02 PM UTC 24
Peak memory 277856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286051068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.286051068
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.2756282486
Short name T344
Test name
Test status
Simulation time 1724704308 ps
CPU time 34.23 seconds
Started Oct 15 12:31:59 PM UTC 24
Finished Oct 15 12:32:35 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756282486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2756282486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.7721669
Short name T179
Test name
Test status
Simulation time 31300529479 ps
CPU time 137.66 seconds
Started Oct 15 12:32:02 PM UTC 24
Finished Oct 15 12:34:22 PM UTC 24
Peak memory 267564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7721669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM
_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.7721669
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2072758620
Short name T235
Test name
Test status
Simulation time 992630063 ps
CPU time 10.8 seconds
Started Oct 15 12:31:40 PM UTC 24
Finished Oct 15 12:31:52 PM UTC 24
Peak memory 244912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072758620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2072758620
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2323205457
Short name T244
Test name
Test status
Simulation time 13214197112 ps
CPU time 81 seconds
Started Oct 15 12:31:41 PM UTC 24
Finished Oct 15 12:33:04 PM UTC 24
Peak memory 245340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323205457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2323205457
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1602742029
Short name T395
Test name
Test status
Simulation time 95681606 ps
CPU time 1.41 seconds
Started Oct 15 12:31:26 PM UTC 24
Finished Oct 15 12:31:29 PM UTC 24
Peak memory 228880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602742029 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.1602742029
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.591324246
Short name T59
Test name
Test status
Simulation time 3173405177 ps
CPU time 18.47 seconds
Started Oct 15 12:31:39 PM UTC 24
Finished Oct 15 12:31:58 PM UTC 24
Peak memory 245236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591324246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.591324246
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2081207442
Short name T195
Test name
Test status
Simulation time 22723895800 ps
CPU time 17.01 seconds
Started Oct 15 12:31:37 PM UTC 24
Finished Oct 15 12:31:55 PM UTC 24
Peak memory 251444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081207442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2081207442
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.275521258
Short name T399
Test name
Test status
Simulation time 454091215 ps
CPU time 4.94 seconds
Started Oct 15 12:32:04 PM UTC 24
Finished Oct 15 12:32:11 PM UTC 24
Peak memory 233220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275521258 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.275521258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2218978258
Short name T350
Test name
Test status
Simulation time 423315958 ps
CPU time 8.96 seconds
Started Oct 15 12:31:29 PM UTC 24
Finished Oct 15 12:31:39 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218978258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2218978258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.2795368405
Short name T396
Test name
Test status
Simulation time 1151328783 ps
CPU time 7.04 seconds
Started Oct 15 12:31:27 PM UTC 24
Finished Oct 15 12:31:35 PM UTC 24
Peak memory 227456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795368405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2795368405
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3319339031
Short name T365
Test name
Test status
Simulation time 102954435 ps
CPU time 1.77 seconds
Started Oct 15 12:31:36 PM UTC 24
Finished Oct 15 12:31:39 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319339031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3319339031
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.4228860372
Short name T397
Test name
Test status
Simulation time 160428868 ps
CPU time 1.39 seconds
Started Oct 15 12:31:33 PM UTC 24
Finished Oct 15 12:31:36 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228860372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4228860372
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.3136763880
Short name T146
Test name
Test status
Simulation time 13023612003 ps
CPU time 24.2 seconds
Started Oct 15 12:31:53 PM UTC 24
Finished Oct 15 12:32:18 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136763880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3136763880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/7.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2186512498
Short name T402
Test name
Test status
Simulation time 16809034 ps
CPU time 1.16 seconds
Started Oct 15 12:33:05 PM UTC 24
Finished Oct 15 12:33:07 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186512498 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2186512498
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.4158598810
Short name T242
Test name
Test status
Simulation time 173653141 ps
CPU time 4.93 seconds
Started Oct 15 12:32:36 PM UTC 24
Finished Oct 15 12:32:42 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158598810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4158598810
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1043151324
Short name T145
Test name
Test status
Simulation time 46547264 ps
CPU time 1.18 seconds
Started Oct 15 12:32:16 PM UTC 24
Finished Oct 15 12:32:18 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043151324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1043151324
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.2621119636
Short name T401
Test name
Test status
Simulation time 15468429 ps
CPU time 1.13 seconds
Started Oct 15 12:32:48 PM UTC 24
Finished Oct 15 12:32:50 PM UTC 24
Peak memory 225176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621119636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2621119636
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.270429901
Short name T311
Test name
Test status
Simulation time 6472722746 ps
CPU time 41.26 seconds
Started Oct 15 12:32:51 PM UTC 24
Finished Oct 15 12:33:34 PM UTC 24
Peak memory 267672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270429901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.270429901
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.1156801226
Short name T321
Test name
Test status
Simulation time 15314809790 ps
CPU time 214.13 seconds
Started Oct 15 12:32:56 PM UTC 24
Finished Oct 15 12:36:33 PM UTC 24
Peak memory 261516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156801226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.1156801226
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2356833931
Short name T320
Test name
Test status
Simulation time 27724948666 ps
CPU time 49.64 seconds
Started Oct 15 12:32:43 PM UTC 24
Finished Oct 15 12:33:34 PM UTC 24
Peak memory 247328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356833931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2356833931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.964684506
Short name T112
Test name
Test status
Simulation time 7086837487 ps
CPU time 74.24 seconds
Started Oct 15 12:32:43 PM UTC 24
Finished Oct 15 12:33:59 PM UTC 24
Peak memory 265824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964684506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.964684506
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.177470302
Short name T204
Test name
Test status
Simulation time 4113463163 ps
CPU time 10.11 seconds
Started Oct 15 12:32:31 PM UTC 24
Finished Oct 15 12:32:42 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177470302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.177470302
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.3979911946
Short name T211
Test name
Test status
Simulation time 7596706070 ps
CPU time 107.17 seconds
Started Oct 15 12:32:33 PM UTC 24
Finished Oct 15 12:34:22 PM UTC 24
Peak memory 251168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979911946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3979911946
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.4261678707
Short name T147
Test name
Test status
Simulation time 29840209 ps
CPU time 1.51 seconds
Started Oct 15 12:32:19 PM UTC 24
Finished Oct 15 12:32:22 PM UTC 24
Peak memory 229000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261678707 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mem_parity.4261678707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2501262022
Short name T189
Test name
Test status
Simulation time 647134396 ps
CPU time 11.73 seconds
Started Oct 15 12:32:30 PM UTC 24
Finished Oct 15 12:32:43 PM UTC 24
Peak memory 244964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501262022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.2501262022
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2995751647
Short name T199
Test name
Test status
Simulation time 9483362171 ps
CPU time 20.03 seconds
Started Oct 15 12:32:26 PM UTC 24
Finished Oct 15 12:32:48 PM UTC 24
Peak memory 245288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995751647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2995751647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.441161820
Short name T403
Test name
Test status
Simulation time 10770020726 ps
CPU time 24.03 seconds
Started Oct 15 12:32:43 PM UTC 24
Finished Oct 15 12:33:09 PM UTC 24
Peak memory 233360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441161820 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.441161820
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2497879270
Short name T173
Test name
Test status
Simulation time 3631386545 ps
CPU time 18.71 seconds
Started Oct 15 12:32:59 PM UTC 24
Finished Oct 15 12:33:19 PM UTC 24
Peak memory 229468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497879270 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.2497879270
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.3015288522
Short name T357
Test name
Test status
Simulation time 1349146157 ps
CPU time 32.14 seconds
Started Oct 15 12:32:21 PM UTC 24
Finished Oct 15 12:32:55 PM UTC 24
Peak memory 227344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015288522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3015288522
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3806812865
Short name T400
Test name
Test status
Simulation time 1351098952 ps
CPU time 11.47 seconds
Started Oct 15 12:32:19 PM UTC 24
Finished Oct 15 12:32:32 PM UTC 24
Peak memory 227604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806812865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3806812865
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.3801684266
Short name T149
Test name
Test status
Simulation time 94943420 ps
CPU time 1.83 seconds
Started Oct 15 12:32:25 PM UTC 24
Finished Oct 15 12:32:29 PM UTC 24
Peak memory 226512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801684266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3801684266
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3585912884
Short name T148
Test name
Test status
Simulation time 49760516 ps
CPU time 1.35 seconds
Started Oct 15 12:32:22 PM UTC 24
Finished Oct 15 12:32:25 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585912884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3585912884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.2471050671
Short name T239
Test name
Test status
Simulation time 14810600409 ps
CPU time 21 seconds
Started Oct 15 12:32:36 PM UTC 24
Finished Oct 15 12:32:58 PM UTC 24
Peak memory 234800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471050671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2471050671
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/8.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.1158041450
Short name T411
Test name
Test status
Simulation time 41903679 ps
CPU time 1.08 seconds
Started Oct 15 12:33:43 PM UTC 24
Finished Oct 15 12:33:45 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158041450 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1158041450
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.4278795964
Short name T233
Test name
Test status
Simulation time 1105118411 ps
CPU time 15.93 seconds
Started Oct 15 12:33:32 PM UTC 24
Finished Oct 15 12:33:50 PM UTC 24
Peak memory 245148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278795964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4278795964
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.994525
Short name T404
Test name
Test status
Simulation time 150547054 ps
CPU time 1.18 seconds
Started Oct 15 12:33:08 PM UTC 24
Finished Oct 15 12:33:10 PM UTC 24
Peak memory 215852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_
TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.994525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3770196532
Short name T248
Test name
Test status
Simulation time 38658161380 ps
CPU time 303.26 seconds
Started Oct 15 12:33:37 PM UTC 24
Finished Oct 15 12:38:44 PM UTC 24
Peak memory 277812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770196532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3770196532
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2288670888
Short name T218
Test name
Test status
Simulation time 24620370687 ps
CPU time 282.07 seconds
Started Oct 15 12:33:38 PM UTC 24
Finished Oct 15 12:38:24 PM UTC 24
Peak memory 261732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288670888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2288670888
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.4129541800
Short name T345
Test name
Test status
Simulation time 606488991 ps
CPU time 7.63 seconds
Started Oct 15 12:33:34 PM UTC 24
Finished Oct 15 12:33:43 PM UTC 24
Peak memory 261340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129541800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4129541800
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.647047342
Short name T409
Test name
Test status
Simulation time 37733929 ps
CPU time 1.11 seconds
Started Oct 15 12:33:35 PM UTC 24
Finished Oct 15 12:33:38 PM UTC 24
Peak memory 225168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647047342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.647047342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.1547939919
Short name T210
Test name
Test status
Simulation time 3202636907 ps
CPU time 23.39 seconds
Started Oct 15 12:33:20 PM UTC 24
Finished Oct 15 12:33:44 PM UTC 24
Peak memory 234792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547939919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1547939919
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.4292988304
Short name T224
Test name
Test status
Simulation time 2415958568 ps
CPU time 7.26 seconds
Started Oct 15 12:33:27 PM UTC 24
Finished Oct 15 12:33:35 PM UTC 24
Peak memory 245280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292988304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4292988304
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.4264771046
Short name T405
Test name
Test status
Simulation time 83893186 ps
CPU time 1.6 seconds
Started Oct 15 12:33:09 PM UTC 24
Finished Oct 15 12:33:12 PM UTC 24
Peak memory 229000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264771046 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mem_parity.4264771046
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1688214299
Short name T68
Test name
Test status
Simulation time 12165572528 ps
CPU time 38.86 seconds
Started Oct 15 12:33:16 PM UTC 24
Finished Oct 15 12:33:56 PM UTC 24
Peak memory 251492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688214299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.1688214299
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.849518628
Short name T333
Test name
Test status
Simulation time 53178552330 ps
CPU time 20.73 seconds
Started Oct 15 12:33:14 PM UTC 24
Finished Oct 15 12:33:37 PM UTC 24
Peak memory 251120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849518628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.849518628
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.3134432022
Short name T410
Test name
Test status
Simulation time 5992914801 ps
CPU time 6.63 seconds
Started Oct 15 12:33:35 PM UTC 24
Finished Oct 15 12:33:43 PM UTC 24
Peak memory 233368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134432022 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.3134432022
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.2535748436
Short name T174
Test name
Test status
Simulation time 119383036 ps
CPU time 1.58 seconds
Started Oct 15 12:33:39 PM UTC 24
Finished Oct 15 12:33:42 PM UTC 24
Peak memory 215708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535748436 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.2535748436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.560935577
Short name T351
Test name
Test status
Simulation time 7613270682 ps
CPU time 42.66 seconds
Started Oct 15 12:33:11 PM UTC 24
Finished Oct 15 12:33:55 PM UTC 24
Peak memory 227404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560935577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.560935577
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2047704222
Short name T408
Test name
Test status
Simulation time 3477989957 ps
CPU time 23.68 seconds
Started Oct 15 12:33:11 PM UTC 24
Finished Oct 15 12:33:36 PM UTC 24
Peak memory 227696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047704222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2047704222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.3971267105
Short name T358
Test name
Test status
Simulation time 22400453 ps
CPU time 1.27 seconds
Started Oct 15 12:33:12 PM UTC 24
Finished Oct 15 12:33:15 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971267105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3971267105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1071672747
Short name T406
Test name
Test status
Simulation time 77334282 ps
CPU time 1.27 seconds
Started Oct 15 12:33:11 PM UTC 24
Finished Oct 15 12:33:14 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071672747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1071672747
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.1903576368
Short name T407
Test name
Test status
Simulation time 32289833 ps
CPU time 2.75 seconds
Started Oct 15 12:33:28 PM UTC 24
Finished Oct 15 12:33:32 PM UTC 24
Peak memory 234596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903576368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1903576368
Directory /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/9.spi_device_upload/latest
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