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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T121 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2331426054 Feb 08 06:45:59 PM UTC 25 Feb 08 06:46:07 PM UTC 25 268767721 ps
T122 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4138375889 Feb 08 06:45:52 PM UTC 25 Feb 08 06:46:07 PM UTC 25 2042720993 ps
T123 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.134784947 Feb 08 06:45:44 PM UTC 25 Feb 08 06:46:08 PM UTC 25 1697417995 ps
T135 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1643233533 Feb 08 06:46:05 PM UTC 25 Feb 08 06:46:08 PM UTC 25 56781840 ps
T1043 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.672416085 Feb 08 06:46:07 PM UTC 25 Feb 08 06:46:09 PM UTC 25 21933544 ps
T1044 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.689636132 Feb 08 06:46:07 PM UTC 25 Feb 08 06:46:09 PM UTC 25 27207464 ps
T176 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3990694245 Feb 08 06:46:05 PM UTC 25 Feb 08 06:46:10 PM UTC 25 880784454 ps
T107 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.610305544 Feb 08 06:46:08 PM UTC 25 Feb 08 06:46:11 PM UTC 25 54225155 ps
T142 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.3861118363 Feb 08 06:46:08 PM UTC 25 Feb 08 06:46:11 PM UTC 25 64903349 ps
T143 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2244159030 Feb 08 06:46:07 PM UTC 25 Feb 08 06:46:12 PM UTC 25 27901621 ps
T126 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.55953829 Feb 08 06:46:06 PM UTC 25 Feb 08 06:46:12 PM UTC 25 204478654 ps
T181 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.489028862 Feb 08 06:46:10 PM UTC 25 Feb 08 06:46:13 PM UTC 25 139345847 ps
T1045 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2381605283 Feb 08 06:46:12 PM UTC 25 Feb 08 06:46:14 PM UTC 25 12556659 ps
T1046 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.3335938399 Feb 08 06:46:12 PM UTC 25 Feb 08 06:46:14 PM UTC 25 59972472 ps
T144 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1248189804 Feb 08 06:46:12 PM UTC 25 Feb 08 06:46:15 PM UTC 25 31726683 ps
T136 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1583270120 Feb 08 06:46:11 PM UTC 25 Feb 08 06:46:15 PM UTC 25 89152847 ps
T108 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3991993567 Feb 08 06:46:13 PM UTC 25 Feb 08 06:46:17 PM UTC 25 55413771 ps
T145 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.4127268946 Feb 08 06:46:04 PM UTC 25 Feb 08 06:46:17 PM UTC 25 1480673560 ps
T1047 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.3273604311 Feb 08 06:46:14 PM UTC 25 Feb 08 06:46:17 PM UTC 25 62705868 ps
T1048 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.900420166 Feb 08 06:46:10 PM UTC 25 Feb 08 06:46:34 PM UTC 25 1223294495 ps
T129 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.1399138948 Feb 08 06:46:11 PM UTC 25 Feb 08 06:46:17 PM UTC 25 55974955 ps
T1049 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.4101578809 Feb 08 06:46:18 PM UTC 25 Feb 08 06:46:20 PM UTC 25 36379370 ps
T124 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2518849731 Feb 08 06:45:59 PM UTC 25 Feb 08 06:46:22 PM UTC 25 1835236334 ps
T146 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3125696159 Feb 08 06:46:18 PM UTC 25 Feb 08 06:46:22 PM UTC 25 239267628 ps
T132 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1285162692 Feb 08 06:46:18 PM UTC 25 Feb 08 06:46:22 PM UTC 25 221554349 ps
T1050 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2649397086 Feb 08 06:46:16 PM UTC 25 Feb 08 06:46:23 PM UTC 25 655389945 ps
T177 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.683343747 Feb 08 06:46:17 PM UTC 25 Feb 08 06:46:23 PM UTC 25 640697611 ps
T178 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2434911422 Feb 08 06:46:21 PM UTC 25 Feb 08 06:46:25 PM UTC 25 175810018 ps
T1051 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1841954765 Feb 08 06:46:23 PM UTC 25 Feb 08 06:46:26 PM UTC 25 14505686 ps
T179 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2019851307 Feb 08 06:46:21 PM UTC 25 Feb 08 06:46:26 PM UTC 25 124475099 ps
T1052 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2292976416 Feb 08 06:46:24 PM UTC 25 Feb 08 06:46:27 PM UTC 25 58254245 ps
T180 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2366202114 Feb 08 06:46:06 PM UTC 25 Feb 08 06:46:28 PM UTC 25 1036356150 ps
T1053 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3245843460 Feb 08 06:46:24 PM UTC 25 Feb 08 06:46:28 PM UTC 25 168811867 ps
T147 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1252899279 Feb 08 06:46:10 PM UTC 25 Feb 08 06:46:29 PM UTC 25 3147398881 ps
T127 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3659826096 Feb 08 06:46:22 PM UTC 25 Feb 08 06:46:29 PM UTC 25 150251198 ps
T1054 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.2511623204 Feb 08 06:46:28 PM UTC 25 Feb 08 06:46:30 PM UTC 25 26531023 ps
T1055 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3911925548 Feb 08 06:46:26 PM UTC 25 Feb 08 06:46:30 PM UTC 25 42003536 ps
T130 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.2580661436 Feb 08 06:46:27 PM UTC 25 Feb 08 06:46:32 PM UTC 25 107017541 ps
T182 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2753266561 Feb 08 06:45:57 PM UTC 25 Feb 08 06:46:32 PM UTC 25 6494043777 ps
T148 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3557508874 Feb 08 06:46:16 PM UTC 25 Feb 08 06:46:33 PM UTC 25 2761791817 ps
T149 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2242395326 Feb 08 06:46:29 PM UTC 25 Feb 08 06:46:33 PM UTC 25 272862286 ps
T1056 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2745251210 Feb 08 06:46:30 PM UTC 25 Feb 08 06:46:33 PM UTC 25 204735937 ps
T1057 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.4102692669 Feb 08 06:46:31 PM UTC 25 Feb 08 06:46:34 PM UTC 25 37705308 ps
T1058 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4264283010 Feb 08 06:46:29 PM UTC 25 Feb 08 06:46:34 PM UTC 25 106773180 ps
T1059 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.1119172012 Feb 08 06:46:18 PM UTC 25 Feb 08 06:46:34 PM UTC 25 927551992 ps
T1060 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3318170554 Feb 08 06:46:30 PM UTC 25 Feb 08 06:46:35 PM UTC 25 1039023514 ps
T217 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.336778347 Feb 08 06:46:11 PM UTC 25 Feb 08 06:46:35 PM UTC 25 315179439 ps
T150 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.4173293340 Feb 08 06:46:33 PM UTC 25 Feb 08 06:46:36 PM UTC 25 29365751 ps
T1061 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.429497697 Feb 08 06:46:34 PM UTC 25 Feb 08 06:46:36 PM UTC 25 12378159 ps
T1062 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4087386696 Feb 08 06:46:33 PM UTC 25 Feb 08 06:46:37 PM UTC 25 410245305 ps
T1063 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.277463258 Feb 08 06:46:36 PM UTC 25 Feb 08 06:46:38 PM UTC 25 15549836 ps
T1064 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.162941867 Feb 08 06:46:34 PM UTC 25 Feb 08 06:46:38 PM UTC 25 146787392 ps
T1065 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1270471653 Feb 08 06:46:34 PM UTC 25 Feb 08 06:46:39 PM UTC 25 356004490 ps
T151 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.472680511 Feb 08 06:46:36 PM UTC 25 Feb 08 06:46:39 PM UTC 25 41038305 ps
T1066 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1034806609 Feb 08 06:46:04 PM UTC 25 Feb 08 06:46:39 PM UTC 25 2443418321 ps
T1067 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4012553002 Feb 08 06:46:14 PM UTC 25 Feb 08 06:46:39 PM UTC 25 1518836049 ps
T1068 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1499553504 Feb 08 06:46:35 PM UTC 25 Feb 08 06:46:40 PM UTC 25 349213125 ps
T128 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3860960667 Feb 08 06:46:37 PM UTC 25 Feb 08 06:46:40 PM UTC 25 116939044 ps
T131 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1487113001 Feb 08 06:46:35 PM UTC 25 Feb 08 06:46:40 PM UTC 25 151442356 ps
T1069 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2621671178 Feb 08 06:46:37 PM UTC 25 Feb 08 06:46:40 PM UTC 25 128752615 ps
T1070 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2515497535 Feb 08 06:46:38 PM UTC 25 Feb 08 06:46:40 PM UTC 25 43125055 ps
T133 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.3773284899 Feb 08 06:46:34 PM UTC 25 Feb 08 06:46:40 PM UTC 25 198642374 ps
T1071 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.694105923 Feb 08 06:46:34 PM UTC 25 Feb 08 06:46:40 PM UTC 25 217916800 ps
T1072 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.61249496 Feb 08 06:46:37 PM UTC 25 Feb 08 06:46:41 PM UTC 25 138346706 ps
T1073 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3490458598 Feb 08 06:46:39 PM UTC 25 Feb 08 06:46:42 PM UTC 25 155783580 ps
T220 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3696827362 Feb 08 06:46:23 PM UTC 25 Feb 08 06:46:42 PM UTC 25 551546329 ps
T215 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.4144431315 Feb 08 06:46:34 PM UTC 25 Feb 08 06:46:43 PM UTC 25 1253033287 ps
T1074 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.999259740 Feb 08 06:46:41 PM UTC 25 Feb 08 06:46:44 PM UTC 25 208863267 ps
T1075 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3657096940 Feb 08 06:46:39 PM UTC 25 Feb 08 06:46:44 PM UTC 25 223080163 ps
T1076 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3298954219 Feb 08 06:46:39 PM UTC 25 Feb 08 06:46:44 PM UTC 25 189089744 ps
T1077 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1079740843 Feb 08 06:46:43 PM UTC 25 Feb 08 06:46:45 PM UTC 25 30261357 ps
T1078 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1225725508 Feb 08 06:46:41 PM UTC 25 Feb 08 06:46:46 PM UTC 25 430158498 ps
T1079 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.835179922 Feb 08 06:46:41 PM UTC 25 Feb 08 06:46:47 PM UTC 25 109416598 ps
T1080 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.182422910 Feb 08 06:46:45 PM UTC 25 Feb 08 06:46:47 PM UTC 25 39249532 ps
T1081 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1949899543 Feb 08 06:46:43 PM UTC 25 Feb 08 06:46:47 PM UTC 25 178406250 ps
T1082 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1805191600 Feb 08 06:46:43 PM UTC 25 Feb 08 06:46:47 PM UTC 25 793382494 ps
T1083 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3402833365 Feb 08 06:46:41 PM UTC 25 Feb 08 06:46:48 PM UTC 25 458865276 ps
T1084 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.281615323 Feb 08 06:46:41 PM UTC 25 Feb 08 06:46:48 PM UTC 25 319473603 ps
T218 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.4262180155 Feb 08 06:46:27 PM UTC 25 Feb 08 06:46:48 PM UTC 25 1804612132 ps
T1085 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2544180641 Feb 08 06:46:46 PM UTC 25 Feb 08 06:46:49 PM UTC 25 44818359 ps
T1086 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1300193583 Feb 08 06:46:43 PM UTC 25 Feb 08 06:46:49 PM UTC 25 62797451 ps
T1087 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2448119730 Feb 08 06:46:48 PM UTC 25 Feb 08 06:46:50 PM UTC 25 35037618 ps
T1088 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1531946919 Feb 08 06:46:46 PM UTC 25 Feb 08 06:46:51 PM UTC 25 75840994 ps
T1089 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3670145426 Feb 08 06:46:45 PM UTC 25 Feb 08 06:46:51 PM UTC 25 1102148690 ps
T1090 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.2665556762 Feb 08 06:46:48 PM UTC 25 Feb 08 06:46:52 PM UTC 25 35156714 ps
T1091 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1603230336 Feb 08 06:46:49 PM UTC 25 Feb 08 06:46:52 PM UTC 25 77195237 ps
T1092 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.925096102 Feb 08 06:46:41 PM UTC 25 Feb 08 06:46:52 PM UTC 25 580475330 ps
T1093 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2664727378 Feb 08 06:46:31 PM UTC 25 Feb 08 06:46:53 PM UTC 25 3051511453 ps
T1094 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2839658799 Feb 08 06:46:51 PM UTC 25 Feb 08 06:46:53 PM UTC 25 14667415 ps
T1095 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2471571661 Feb 08 06:46:46 PM UTC 25 Feb 08 06:46:53 PM UTC 25 2675405272 ps
T1096 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.4260714256 Feb 08 06:46:48 PM UTC 25 Feb 08 06:46:54 PM UTC 25 58675140 ps
T1097 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3755688073 Feb 08 06:46:48 PM UTC 25 Feb 08 06:46:54 PM UTC 25 66563916 ps
T1098 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.771456713 Feb 08 06:46:49 PM UTC 25 Feb 08 06:46:54 PM UTC 25 330778433 ps
T1099 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.4283053965 Feb 08 06:46:51 PM UTC 25 Feb 08 06:46:55 PM UTC 25 102679010 ps
T221 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3725674346 Feb 08 06:46:37 PM UTC 25 Feb 08 06:46:55 PM UTC 25 565852551 ps
T1100 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1179546168 Feb 08 06:46:51 PM UTC 25 Feb 08 06:46:56 PM UTC 25 63717501 ps
T1101 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.1417129209 Feb 08 06:46:54 PM UTC 25 Feb 08 06:46:57 PM UTC 25 23585565 ps
T1102 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.4271896298 Feb 08 06:46:52 PM UTC 25 Feb 08 06:46:57 PM UTC 25 47945851 ps
T1103 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4212738470 Feb 08 06:46:52 PM UTC 25 Feb 08 06:46:57 PM UTC 25 82070217 ps
T216 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3162533350 Feb 08 06:46:36 PM UTC 25 Feb 08 06:46:58 PM UTC 25 599644817 ps
T1104 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.1734214280 Feb 08 06:46:54 PM UTC 25 Feb 08 06:46:58 PM UTC 25 290053401 ps
T1105 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2615663340 Feb 08 06:46:55 PM UTC 25 Feb 08 06:46:59 PM UTC 25 92619970 ps
T1106 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1537594009 Feb 08 06:46:57 PM UTC 25 Feb 08 06:46:59 PM UTC 25 36170788 ps
T222 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1866280721 Feb 08 06:46:49 PM UTC 25 Feb 08 06:47:00 PM UTC 25 399578409 ps
T1107 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2447292248 Feb 08 06:46:55 PM UTC 25 Feb 08 06:47:00 PM UTC 25 199094819 ps
T1108 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3130413837 Feb 08 06:46:57 PM UTC 25 Feb 08 06:47:00 PM UTC 25 15147613 ps
T214 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.629960424 Feb 08 06:46:55 PM UTC 25 Feb 08 06:47:01 PM UTC 25 139408212 ps
T1109 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4071222910 Feb 08 06:46:57 PM UTC 25 Feb 08 06:47:01 PM UTC 25 559643885 ps
T1110 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.2443838041 Feb 08 06:46:57 PM UTC 25 Feb 08 06:47:01 PM UTC 25 57349636 ps
T1111 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.167045222 Feb 08 06:46:59 PM UTC 25 Feb 08 06:47:01 PM UTC 25 21492414 ps
T1112 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.432105826 Feb 08 06:46:57 PM UTC 25 Feb 08 06:47:02 PM UTC 25 520775273 ps
T1113 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2578629955 Feb 08 06:46:57 PM UTC 25 Feb 08 06:47:02 PM UTC 25 450409846 ps
T1114 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.3934913668 Feb 08 06:46:59 PM UTC 25 Feb 08 06:47:02 PM UTC 25 48355218 ps
T1115 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.572510828 Feb 08 06:46:59 PM UTC 25 Feb 08 06:47:03 PM UTC 25 106798273 ps
T1116 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3555802851 Feb 08 06:46:59 PM UTC 25 Feb 08 06:47:03 PM UTC 25 84093956 ps
T1117 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.989849161 Feb 08 06:47:02 PM UTC 25 Feb 08 06:47:04 PM UTC 25 38039049 ps
T1118 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1172143891 Feb 08 06:47:02 PM UTC 25 Feb 08 06:47:04 PM UTC 25 17979134 ps
T1119 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3376560054 Feb 08 06:47:02 PM UTC 25 Feb 08 06:47:04 PM UTC 25 55629356 ps
T1120 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.4108308868 Feb 08 06:46:48 PM UTC 25 Feb 08 06:47:04 PM UTC 25 1108538556 ps
T1121 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.4075991289 Feb 08 06:47:01 PM UTC 25 Feb 08 06:47:04 PM UTC 25 16488203 ps
T219 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1123301720 Feb 08 06:46:41 PM UTC 25 Feb 08 06:47:04 PM UTC 25 1381138447 ps
T1122 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1379071827 Feb 08 06:47:02 PM UTC 25 Feb 08 06:47:04 PM UTC 25 16315351 ps
T1123 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2921595992 Feb 08 06:47:02 PM UTC 25 Feb 08 06:47:04 PM UTC 25 20017610 ps
T1124 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.951877925 Feb 08 06:46:41 PM UTC 25 Feb 08 06:47:04 PM UTC 25 921406937 ps
T1125 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3168493578 Feb 08 06:46:57 PM UTC 25 Feb 08 06:47:06 PM UTC 25 209759290 ps
T1126 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.3744451398 Feb 08 06:47:04 PM UTC 25 Feb 08 06:47:06 PM UTC 25 20815733 ps
T1127 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2445889019 Feb 08 06:47:04 PM UTC 25 Feb 08 06:47:06 PM UTC 25 37262959 ps
T1128 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3118621333 Feb 08 06:47:04 PM UTC 25 Feb 08 06:47:06 PM UTC 25 40265412 ps
T1129 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2081023525 Feb 08 06:47:04 PM UTC 25 Feb 08 06:47:06 PM UTC 25 12949025 ps
T1130 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.1829092509 Feb 08 06:47:04 PM UTC 25 Feb 08 06:47:06 PM UTC 25 15008620 ps
T1131 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3149438214 Feb 08 06:47:04 PM UTC 25 Feb 08 06:47:06 PM UTC 25 40891641 ps
T1132 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.143261318 Feb 08 06:47:04 PM UTC 25 Feb 08 06:47:06 PM UTC 25 42543492 ps
T1133 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.437307470 Feb 08 06:47:04 PM UTC 25 Feb 08 06:47:06 PM UTC 25 58638256 ps
T1134 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2999770563 Feb 08 06:47:04 PM UTC 25 Feb 08 06:47:06 PM UTC 25 18650010 ps
T1135 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2391706863 Feb 08 06:47:04 PM UTC 25 Feb 08 06:47:06 PM UTC 25 48868152 ps
T1136 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3069474442 Feb 08 06:46:45 PM UTC 25 Feb 08 06:47:07 PM UTC 25 1965210102 ps
T1137 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3801787126 Feb 08 06:47:07 PM UTC 25 Feb 08 06:47:09 PM UTC 25 14455284 ps
T1138 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3175694517 Feb 08 06:47:07 PM UTC 25 Feb 08 06:47:09 PM UTC 25 19217980 ps
T1139 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.1490353019 Feb 08 06:47:07 PM UTC 25 Feb 08 06:47:10 PM UTC 25 18131733 ps
T1140 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1241940413 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 40720527 ps
T1141 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.270410015 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 17603869 ps
T1142 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3265855088 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 11020150 ps
T1143 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2496946310 Feb 08 06:47:07 PM UTC 25 Feb 08 06:47:10 PM UTC 25 20810027 ps
T1144 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2198318047 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 18577262 ps
T1145 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1555287488 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 15838109 ps
T1146 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.3210701309 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 11298974 ps
T1147 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.882355199 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 12413091 ps
T1148 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.1764653617 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 42040267 ps
T1149 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1666423356 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 138656290 ps
T1150 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.3990648659 Feb 08 06:46:54 PM UTC 25 Feb 08 06:47:18 PM UTC 25 2224100242 ps
T1151 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.1579090071 Feb 08 06:46:57 PM UTC 25 Feb 08 06:47:21 PM UTC 25 1087420276 ps

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3409472061
Short name T5
Test name
Test status
Simulation time 198583601 ps
CPU time 1.7 seconds
Started Feb 08 06:29:44 PM UTC 25
Finished Feb 08 06:29:47 PM UTC 25
Peak memory 216020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409472061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3409472061
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.1949426013
Short name T14
Test name
Test status
Simulation time 690888315 ps
CPU time 6.23 seconds
Started Feb 08 06:29:44 PM UTC 25
Finished Feb 08 06:29:52 PM UTC 25
Peak memory 234944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949426013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1949426013
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3251226362
Short name T46
Test name
Test status
Simulation time 3838015987 ps
CPU time 37.01 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:30:24 PM UTC 25
Peak memory 263724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251226362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.3251226362
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.3457277369
Short name T39
Test name
Test status
Simulation time 4958498941 ps
CPU time 34.21 seconds
Started Feb 08 06:31:28 PM UTC 25
Finished Feb 08 06:32:04 PM UTC 25
Peak memory 251700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457277369 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.3457277369
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3336694961
Short name T65
Test name
Test status
Simulation time 23099418698 ps
CPU time 104.94 seconds
Started Feb 08 06:30:35 PM UTC 25
Finished Feb 08 06:32:22 PM UTC 25
Peak memory 261724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336694961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.3336694961
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2366202114
Short name T180
Test name
Test status
Simulation time 1036356150 ps
CPU time 20.43 seconds
Started Feb 08 06:46:06 PM UTC 25
Finished Feb 08 06:46:28 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366202114 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.2366202114
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.107127611
Short name T152
Test name
Test status
Simulation time 52215750159 ps
CPU time 197.29 seconds
Started Feb 08 06:32:54 PM UTC 25
Finished Feb 08 06:36:14 PM UTC 25
Peak memory 278044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107127611 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.107127611
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3211784963
Short name T17
Test name
Test status
Simulation time 415865182 ps
CPU time 3.97 seconds
Started Feb 08 06:29:49 PM UTC 25
Finished Feb 08 06:29:54 PM UTC 25
Peak memory 235012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211784963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.3211784963
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.6296300
Short name T100
Test name
Test status
Simulation time 24880547325 ps
CPU time 105.12 seconds
Started Feb 08 06:31:03 PM UTC 25
Finished Feb 08 06:32:51 PM UTC 25
Peak memory 265784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6296300 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.6296300
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.2220699724
Short name T2
Test name
Test status
Simulation time 39726695 ps
CPU time 1.06 seconds
Started Feb 08 06:29:43 PM UTC 25
Finished Feb 08 06:29:45 PM UTC 25
Peak memory 225408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220699724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2220699724
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.4225349543
Short name T103
Test name
Test status
Simulation time 19340485506 ps
CPU time 148.16 seconds
Started Feb 08 06:31:26 PM UTC 25
Finished Feb 08 06:33:56 PM UTC 25
Peak memory 294708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225349543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4225349543
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.434838797
Short name T234
Test name
Test status
Simulation time 25537922706 ps
CPU time 139.84 seconds
Started Feb 08 06:33:46 PM UTC 25
Finished Feb 08 06:36:08 PM UTC 25
Peak memory 273968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434838797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.434838797
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.55953829
Short name T126
Test name
Test status
Simulation time 204478654 ps
CPU time 4.44 seconds
Started Feb 08 06:46:06 PM UTC 25
Finished Feb 08 06:46:12 PM UTC 25
Peak memory 226776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55953829 -assert nopostproc +UVM_TESTNAME=spi_device_bas
e_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devic
e_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.55953829
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.4114571693
Short name T9
Test name
Test status
Simulation time 62545201 ps
CPU time 1.72 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:29:49 PM UTC 25
Peak memory 257592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114571693 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4114571693
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.483273027
Short name T49
Test name
Test status
Simulation time 297820886 ps
CPU time 8.23 seconds
Started Feb 08 06:30:04 PM UTC 25
Finished Feb 08 06:30:13 PM UTC 25
Peak memory 234928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483273027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.483273027
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2792356257
Short name T95
Test name
Test status
Simulation time 12747125230 ps
CPU time 65.5 seconds
Started Feb 08 06:30:20 PM UTC 25
Finished Feb 08 06:31:28 PM UTC 25
Peak memory 251452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792356257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.2792356257
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2193442598
Short name T52
Test name
Test status
Simulation time 7324037993 ps
CPU time 76.11 seconds
Started Feb 08 06:31:53 PM UTC 25
Finished Feb 08 06:33:11 PM UTC 25
Peak memory 265780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193442598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2193442598
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2120173413
Short name T71
Test name
Test status
Simulation time 42400417971 ps
CPU time 136.03 seconds
Started Feb 08 06:30:46 PM UTC 25
Finished Feb 08 06:33:05 PM UTC 25
Peak memory 278008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120173413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.2120173413
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2269447472
Short name T90
Test name
Test status
Simulation time 2658614348 ps
CPU time 43.39 seconds
Started Feb 08 06:30:33 PM UTC 25
Finished Feb 08 06:31:18 PM UTC 25
Peak memory 247344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269447472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2269447472
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.168477779
Short name T233
Test name
Test status
Simulation time 45331821702 ps
CPU time 318.12 seconds
Started Feb 08 06:30:17 PM UTC 25
Finished Feb 08 06:35:39 PM UTC 25
Peak memory 267768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168477779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.168477779
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2998246248
Short name T8
Test name
Test status
Simulation time 41361343 ps
CPU time 1.54 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:29:49 PM UTC 25
Peak memory 229196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998246248 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.2998246248
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.1607571106
Short name T377
Test name
Test status
Simulation time 98756835818 ps
CPU time 926.83 seconds
Started Feb 08 06:30:21 PM UTC 25
Finished Feb 08 06:45:58 PM UTC 25
Peak memory 296496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607571106 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.1607571106
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1885301095
Short name T141
Test name
Test status
Simulation time 57269453 ps
CPU time 2.62 seconds
Started Feb 08 06:46:03 PM UTC 25
Finished Feb 08 06:46:07 PM UTC 25
Peak memory 216276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885301095 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1885301095
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3801260339
Short name T29
Test name
Test status
Simulation time 3752250376 ps
CPU time 7.52 seconds
Started Feb 08 06:29:56 PM UTC 25
Finished Feb 08 06:30:05 PM UTC 25
Peak memory 227612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801260339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3801260339
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.2140488287
Short name T406
Test name
Test status
Simulation time 7434669621 ps
CPU time 46.28 seconds
Started Feb 08 06:32:21 PM UTC 25
Finished Feb 08 06:33:09 PM UTC 25
Peak memory 227648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140488287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2140488287
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1081434912
Short name T184
Test name
Test status
Simulation time 58841719002 ps
CPU time 340.32 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:35:31 PM UTC 25
Peak memory 265780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081434912 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.1081434912
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.4083824895
Short name T78
Test name
Test status
Simulation time 5607479996 ps
CPU time 118.55 seconds
Started Feb 08 06:36:20 PM UTC 25
Finished Feb 08 06:38:21 PM UTC 25
Peak memory 263644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083824895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4083824895
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2087772338
Short name T42
Test name
Test status
Simulation time 18137966922 ps
CPU time 213.62 seconds
Started Feb 08 06:29:53 PM UTC 25
Finished Feb 08 06:33:30 PM UTC 25
Peak memory 261684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087772338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.2087772338
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.2439937230
Short name T331
Test name
Test status
Simulation time 10062720897 ps
CPU time 148.92 seconds
Started Feb 08 06:43:03 PM UTC 25
Finished Feb 08 06:45:34 PM UTC 25
Peak memory 263676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439937230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2439937230
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.3448662810
Short name T249
Test name
Test status
Simulation time 8734539381 ps
CPU time 147.99 seconds
Started Feb 08 06:34:18 PM UTC 25
Finished Feb 08 06:36:49 PM UTC 25
Peak memory 267796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448662810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3448662810
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.371977019
Short name T389
Test name
Test status
Simulation time 39153619260 ps
CPU time 312.23 seconds
Started Feb 08 06:38:36 PM UTC 25
Finished Feb 08 06:43:52 PM UTC 25
Peak memory 284444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371977019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.371977019
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1528494501
Short name T6
Test name
Test status
Simulation time 26498646 ps
CPU time 0.98 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:29:48 PM UTC 25
Peak memory 215552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528494501 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1528494501
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.537057591
Short name T375
Test name
Test status
Simulation time 155795873397 ps
CPU time 542.32 seconds
Started Feb 08 06:34:35 PM UTC 25
Finished Feb 08 06:43:44 PM UTC 25
Peak memory 284444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537057591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.537057591
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.4220442883
Short name T272
Test name
Test status
Simulation time 1227440604 ps
CPU time 21.63 seconds
Started Feb 08 06:30:14 PM UTC 25
Finished Feb 08 06:30:37 PM UTC 25
Peak memory 235184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220442883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4220442883
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2777975762
Short name T54
Test name
Test status
Simulation time 2296652014 ps
CPU time 42.03 seconds
Started Feb 08 06:29:53 PM UTC 25
Finished Feb 08 06:30:36 PM UTC 25
Peak memory 261328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777975762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.2777975762
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3619942041
Short name T364
Test name
Test status
Simulation time 239410371202 ps
CPU time 673.3 seconds
Started Feb 08 06:43:06 PM UTC 25
Finished Feb 08 06:54:27 PM UTC 25
Peak memory 267828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619942041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.3619942041
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2007811867
Short name T11
Test name
Test status
Simulation time 979249754 ps
CPU time 5.57 seconds
Started Feb 08 06:29:44 PM UTC 25
Finished Feb 08 06:29:51 PM UTC 25
Peak memory 245280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007811867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.2007811867
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1036630777
Short name T94
Test name
Test status
Simulation time 3605938477 ps
CPU time 122.39 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:31:51 PM UTC 25
Peak memory 264012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036630777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1036630777
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.3043681057
Short name T505
Test name
Test status
Simulation time 13934400563 ps
CPU time 79.58 seconds
Started Feb 08 06:32:53 PM UTC 25
Finished Feb 08 06:34:14 PM UTC 25
Peak memory 263764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043681057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.3043681057
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1745817511
Short name T228
Test name
Test status
Simulation time 9710091189 ps
CPU time 75.83 seconds
Started Feb 08 06:34:30 PM UTC 25
Finished Feb 08 06:35:48 PM UTC 25
Peak memory 261616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745817511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.1745817511
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.565483038
Short name T162
Test name
Test status
Simulation time 11099830728 ps
CPU time 88.31 seconds
Started Feb 08 06:36:42 PM UTC 25
Finished Feb 08 06:38:12 PM UTC 25
Peak memory 278324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565483038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.565483038
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.418998293
Short name T238
Test name
Test status
Simulation time 2928613531 ps
CPU time 89.99 seconds
Started Feb 08 06:40:15 PM UTC 25
Finished Feb 08 06:41:47 PM UTC 25
Peak memory 267824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418998293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.418998293
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1285162692
Short name T132
Test name
Test status
Simulation time 221554349 ps
CPU time 3.29 seconds
Started Feb 08 06:46:18 PM UTC 25
Finished Feb 08 06:46:22 PM UTC 25
Peak memory 226580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285162692 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1285162692
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3168493578
Short name T1125
Test name
Test status
Simulation time 209759290 ps
CPU time 7.44 seconds
Started Feb 08 06:46:57 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 226532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168493578 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.3168493578
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.1003242862
Short name T74
Test name
Test status
Simulation time 6875684056 ps
CPU time 40.58 seconds
Started Feb 08 06:29:47 PM UTC 25
Finished Feb 08 06:30:29 PM UTC 25
Peak memory 227472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003242862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1003242862
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.564339662
Short name T395
Test name
Test status
Simulation time 912765092 ps
CPU time 25.92 seconds
Started Feb 08 06:32:29 PM UTC 25
Finished Feb 08 06:32:57 PM UTC 25
Peak memory 234980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564339662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.564339662
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.588683309
Short name T370
Test name
Test status
Simulation time 326408936077 ps
CPU time 805.07 seconds
Started Feb 08 06:33:30 PM UTC 25
Finished Feb 08 06:47:05 PM UTC 25
Peak memory 278320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588683309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.588683309
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.3524454926
Short name T302
Test name
Test status
Simulation time 19556388068 ps
CPU time 251.97 seconds
Started Feb 08 06:34:35 PM UTC 25
Finished Feb 08 06:38:51 PM UTC 25
Peak memory 267816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524454926 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.3524454926
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.1978585855
Short name T170
Test name
Test status
Simulation time 327068392239 ps
CPU time 717.13 seconds
Started Feb 08 06:35:12 PM UTC 25
Finished Feb 08 06:47:18 PM UTC 25
Peak memory 267852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978585855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1978585855
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.3160188643
Short name T813
Test name
Test status
Simulation time 104907205 ps
CPU time 5.03 seconds
Started Feb 08 06:42:07 PM UTC 25
Finished Feb 08 06:42:13 PM UTC 25
Peak memory 245204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160188643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3160188643
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.730809219
Short name T232
Test name
Test status
Simulation time 244576841555 ps
CPU time 407.22 seconds
Started Feb 08 06:30:46 PM UTC 25
Finished Feb 08 06:37:39 PM UTC 25
Peak memory 267824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730809219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.730809219
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1632889908
Short name T76
Test name
Test status
Simulation time 6459902031 ps
CPU time 21.85 seconds
Started Feb 08 06:29:49 PM UTC 25
Finished Feb 08 06:30:12 PM UTC 25
Peak memory 234944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632889908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1632889908
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.1321857883
Short name T91
Test name
Test status
Simulation time 1659673624 ps
CPU time 24.07 seconds
Started Feb 08 06:29:50 PM UTC 25
Finished Feb 08 06:30:16 PM UTC 25
Peak memory 251288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321857883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1321857883
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1119620177
Short name T43
Test name
Test status
Simulation time 7075694126 ps
CPU time 118.03 seconds
Started Feb 08 06:32:34 PM UTC 25
Finished Feb 08 06:34:34 PM UTC 25
Peak memory 263732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119620177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.1119620177
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.3129329862
Short name T235
Test name
Test status
Simulation time 2625897704 ps
CPU time 72.11 seconds
Started Feb 08 06:35:40 PM UTC 25
Finished Feb 08 06:36:55 PM UTC 25
Peak memory 261648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129329862 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.3129329862
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.93607217
Short name T241
Test name
Test status
Simulation time 27167317451 ps
CPU time 98.09 seconds
Started Feb 08 06:38:08 PM UTC 25
Finished Feb 08 06:39:48 PM UTC 25
Peak memory 267796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93607217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.93607217
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.815206378
Short name T661
Test name
Test status
Simulation time 325422684 ps
CPU time 12.78 seconds
Started Feb 08 06:38:18 PM UTC 25
Finished Feb 08 06:38:32 PM UTC 25
Peak memory 245168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815206378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.815206378
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3004489126
Short name T263
Test name
Test status
Simulation time 56474596125 ps
CPU time 129.05 seconds
Started Feb 08 06:42:27 PM UTC 25
Finished Feb 08 06:44:39 PM UTC 25
Peak memory 264012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004489126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3004489126
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2341493407
Short name T383
Test name
Test status
Simulation time 7053579504 ps
CPU time 27.14 seconds
Started Feb 08 06:43:49 PM UTC 25
Finished Feb 08 06:44:17 PM UTC 25
Peak memory 249564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341493407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.2341493407
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1392915772
Short name T1
Test name
Test status
Simulation time 68891839 ps
CPU time 0.96 seconds
Started Feb 08 06:29:43 PM UTC 25
Finished Feb 08 06:29:45 PM UTC 25
Peak memory 215376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392915772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1392915772
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3249033486
Short name T106
Test name
Test status
Simulation time 130508137 ps
CPU time 1.41 seconds
Started Feb 08 06:45:56 PM UTC 25
Finished Feb 08 06:45:59 PM UTC 25
Peak memory 213756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249033486 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.3249033486
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.3773284899
Short name T133
Test name
Test status
Simulation time 198642374 ps
CPU time 5.32 seconds
Started Feb 08 06:46:34 PM UTC 25
Finished Feb 08 06:46:40 PM UTC 25
Peak memory 226560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773284899 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3773284899
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1763276807
Short name T1036
Test name
Test status
Simulation time 115332979 ps
CPU time 7.63 seconds
Started Feb 08 06:45:50 PM UTC 25
Finished Feb 08 06:45:58 PM UTC 25
Peak memory 214252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763276807 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.1763276807
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3517682553
Short name T1041
Test name
Test status
Simulation time 1142424789 ps
CPU time 15.04 seconds
Started Feb 08 06:45:48 PM UTC 25
Finished Feb 08 06:46:05 PM UTC 25
Peak memory 214136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517682553 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.3517682553
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2213850906
Short name T105
Test name
Test status
Simulation time 112922201 ps
CPU time 1.78 seconds
Started Feb 08 06:45:48 PM UTC 25
Finished Feb 08 06:45:51 PM UTC 25
Peak memory 214056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213850906 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.2213850906
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3859247607
Short name T120
Test name
Test status
Simulation time 864993739 ps
CPU time 5.52 seconds
Started Feb 08 06:45:51 PM UTC 25
Finished Feb 08 06:45:57 PM UTC 25
Peak memory 228612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3859247607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_
rw_with_rand_reset.3859247607
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2083159298
Short name T1033
Test name
Test status
Simulation time 166615139 ps
CPU time 3.74 seconds
Started Feb 08 06:45:48 PM UTC 25
Finished Feb 08 06:45:53 PM UTC 25
Peak memory 226448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083159298 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2083159298
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2753287963
Short name T1032
Test name
Test status
Simulation time 258485732 ps
CPU time 1.17 seconds
Started Feb 08 06:45:45 PM UTC 25
Finished Feb 08 06:45:47 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753287963 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2753287963
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2596094317
Short name T137
Test name
Test status
Simulation time 62803517 ps
CPU time 3.12 seconds
Started Feb 08 06:45:47 PM UTC 25
Finished Feb 08 06:45:52 PM UTC 25
Peak memory 226448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596094317 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.2596094317
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.4077267988
Short name T1031
Test name
Test status
Simulation time 12169063 ps
CPU time 1.02 seconds
Started Feb 08 06:45:45 PM UTC 25
Finished Feb 08 06:45:47 PM UTC 25
Peak memory 212224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077267988 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.4077267988
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1270034677
Short name T175
Test name
Test status
Simulation time 1677792369 ps
CPU time 4.18 seconds
Started Feb 08 06:45:50 PM UTC 25
Finished Feb 08 06:45:55 PM UTC 25
Peak memory 226476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270034677 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.1270034677
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3835873578
Short name T118
Test name
Test status
Simulation time 94286165 ps
CPU time 3.47 seconds
Started Feb 08 06:45:43 PM UTC 25
Finished Feb 08 06:45:48 PM UTC 25
Peak memory 226588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835873578 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3835873578
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.134784947
Short name T123
Test name
Test status
Simulation time 1697417995 ps
CPU time 22.47 seconds
Started Feb 08 06:45:44 PM UTC 25
Finished Feb 08 06:46:08 PM UTC 25
Peak memory 226456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134784947 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.134784947
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3228861766
Short name T140
Test name
Test status
Simulation time 1222005868 ps
CPU time 7.79 seconds
Started Feb 08 06:45:57 PM UTC 25
Finished Feb 08 06:46:06 PM UTC 25
Peak memory 226476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228861766 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.3228861766
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2753266561
Short name T182
Test name
Test status
Simulation time 6494043777 ps
CPU time 33.58 seconds
Started Feb 08 06:45:57 PM UTC 25
Finished Feb 08 06:46:32 PM UTC 25
Peak memory 214292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753266561 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.2753266561
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3982895196
Short name T134
Test name
Test status
Simulation time 371518922 ps
CPU time 3.79 seconds
Started Feb 08 06:45:59 PM UTC 25
Finished Feb 08 06:46:04 PM UTC 25
Peak memory 227980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3982895196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_
rw_with_rand_reset.3982895196
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.851195509
Short name T1037
Test name
Test status
Simulation time 69687182 ps
CPU time 3.62 seconds
Started Feb 08 06:45:56 PM UTC 25
Finished Feb 08 06:46:01 PM UTC 25
Peak memory 226388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851195509 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d
evice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.851195509
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.372326765
Short name T1034
Test name
Test status
Simulation time 45944587 ps
CPU time 1.14 seconds
Started Feb 08 06:45:53 PM UTC 25
Finished Feb 08 06:45:55 PM UTC 25
Peak memory 211900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372326765 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.372326765
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1637218708
Short name T138
Test name
Test status
Simulation time 75944851 ps
CPU time 1.97 seconds
Started Feb 08 06:45:55 PM UTC 25
Finished Feb 08 06:45:58 PM UTC 25
Peak memory 225412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637218708 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.1637218708
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2490892312
Short name T1035
Test name
Test status
Simulation time 13521636 ps
CPU time 1.04 seconds
Started Feb 08 06:45:54 PM UTC 25
Finished Feb 08 06:45:56 PM UTC 25
Peak memory 211832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490892312 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.2490892312
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3855409268
Short name T1039
Test name
Test status
Simulation time 228579330 ps
CPU time 3.69 seconds
Started Feb 08 06:45:58 PM UTC 25
Finished Feb 08 06:46:03 PM UTC 25
Peak memory 226672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855409268 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.3855409268
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2888429922
Short name T119
Test name
Test status
Simulation time 68594618 ps
CPU time 5.04 seconds
Started Feb 08 06:45:51 PM UTC 25
Finished Feb 08 06:45:57 PM UTC 25
Peak memory 226540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888429922 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2888429922
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4138375889
Short name T122
Test name
Test status
Simulation time 2042720993 ps
CPU time 14.09 seconds
Started Feb 08 06:45:52 PM UTC 25
Finished Feb 08 06:46:07 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138375889 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.4138375889
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2621671178
Short name T1069
Test name
Test status
Simulation time 128752615 ps
CPU time 2.34 seconds
Started Feb 08 06:46:37 PM UTC 25
Finished Feb 08 06:46:40 PM UTC 25
Peak memory 226824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2621671178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem
_rw_with_rand_reset.2621671178
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.472680511
Short name T151
Test name
Test status
Simulation time 41038305 ps
CPU time 1.81 seconds
Started Feb 08 06:46:36 PM UTC 25
Finished Feb 08 06:46:39 PM UTC 25
Peak memory 213208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472680511 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d
evice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.472680511
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.277463258
Short name T1063
Test name
Test status
Simulation time 15549836 ps
CPU time 1.08 seconds
Started Feb 08 06:46:36 PM UTC 25
Finished Feb 08 06:46:38 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277463258 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.277463258
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.61249496
Short name T1072
Test name
Test status
Simulation time 138346706 ps
CPU time 3.09 seconds
Started Feb 08 06:46:37 PM UTC 25
Finished Feb 08 06:46:41 PM UTC 25
Peak memory 226708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61249496 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.61249496
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1487113001
Short name T131
Test name
Test status
Simulation time 151442356 ps
CPU time 3.31 seconds
Started Feb 08 06:46:35 PM UTC 25
Finished Feb 08 06:46:40 PM UTC 25
Peak memory 226820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487113001 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.1487113001
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3162533350
Short name T216
Test name
Test status
Simulation time 599644817 ps
CPU time 20.54 seconds
Started Feb 08 06:46:36 PM UTC 25
Finished Feb 08 06:46:58 PM UTC 25
Peak memory 226456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162533350 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.3162533350
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3298954219
Short name T1076
Test name
Test status
Simulation time 189089744 ps
CPU time 3.77 seconds
Started Feb 08 06:46:39 PM UTC 25
Finished Feb 08 06:46:44 PM UTC 25
Peak memory 226760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3298954219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem
_rw_with_rand_reset.3298954219
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3490458598
Short name T1073
Test name
Test status
Simulation time 155783580 ps
CPU time 1.66 seconds
Started Feb 08 06:46:39 PM UTC 25
Finished Feb 08 06:46:42 PM UTC 25
Peak memory 225452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490458598 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.3490458598
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2515497535
Short name T1070
Test name
Test status
Simulation time 43125055 ps
CPU time 1.1 seconds
Started Feb 08 06:46:38 PM UTC 25
Finished Feb 08 06:46:40 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515497535 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.2515497535
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3657096940
Short name T1075
Test name
Test status
Simulation time 223080163 ps
CPU time 3.57 seconds
Started Feb 08 06:46:39 PM UTC 25
Finished Feb 08 06:46:44 PM UTC 25
Peak memory 226628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657096940 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstanding.3657096940
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3860960667
Short name T128
Test name
Test status
Simulation time 116939044 ps
CPU time 1.88 seconds
Started Feb 08 06:46:37 PM UTC 25
Finished Feb 08 06:46:40 PM UTC 25
Peak memory 225480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860960667 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.3860960667
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3725674346
Short name T221
Test name
Test status
Simulation time 565852551 ps
CPU time 16.85 seconds
Started Feb 08 06:46:37 PM UTC 25
Finished Feb 08 06:46:55 PM UTC 25
Peak memory 226708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725674346 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.3725674346
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3402833365
Short name T1083
Test name
Test status
Simulation time 458865276 ps
CPU time 4.95 seconds
Started Feb 08 06:46:41 PM UTC 25
Finished Feb 08 06:46:48 PM UTC 25
Peak memory 228632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3402833365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem
_rw_with_rand_reset.3402833365
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1225725508
Short name T1078
Test name
Test status
Simulation time 430158498 ps
CPU time 3.13 seconds
Started Feb 08 06:46:41 PM UTC 25
Finished Feb 08 06:46:46 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225725508 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.1225725508
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.999259740
Short name T1074
Test name
Test status
Simulation time 208863267 ps
CPU time 1 seconds
Started Feb 08 06:46:41 PM UTC 25
Finished Feb 08 06:46:44 PM UTC 25
Peak memory 211672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999259740 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.999259740
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.281615323
Short name T1084
Test name
Test status
Simulation time 319473603 ps
CPU time 5.08 seconds
Started Feb 08 06:46:41 PM UTC 25
Finished Feb 08 06:46:48 PM UTC 25
Peak memory 226480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281615323 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.281615323
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.835179922
Short name T1079
Test name
Test status
Simulation time 109416598 ps
CPU time 4.2 seconds
Started Feb 08 06:46:41 PM UTC 25
Finished Feb 08 06:46:47 PM UTC 25
Peak memory 226640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835179922 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.835179922
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1123301720
Short name T219
Test name
Test status
Simulation time 1381138447 ps
CPU time 20.91 seconds
Started Feb 08 06:46:41 PM UTC 25
Finished Feb 08 06:47:04 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123301720 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.1123301720
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1300193583
Short name T1086
Test name
Test status
Simulation time 62797451 ps
CPU time 5.16 seconds
Started Feb 08 06:46:43 PM UTC 25
Finished Feb 08 06:46:49 PM UTC 25
Peak memory 226564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1300193583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem
_rw_with_rand_reset.1300193583
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1949899543
Short name T1081
Test name
Test status
Simulation time 178406250 ps
CPU time 2.72 seconds
Started Feb 08 06:46:43 PM UTC 25
Finished Feb 08 06:46:47 PM UTC 25
Peak memory 214200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949899543 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.1949899543
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1079740843
Short name T1077
Test name
Test status
Simulation time 30261357 ps
CPU time 0.91 seconds
Started Feb 08 06:46:43 PM UTC 25
Finished Feb 08 06:46:45 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079740843 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.1079740843
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1805191600
Short name T1082
Test name
Test status
Simulation time 793382494 ps
CPU time 2.74 seconds
Started Feb 08 06:46:43 PM UTC 25
Finished Feb 08 06:46:47 PM UTC 25
Peak memory 226416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805191600 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.1805191600
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.925096102
Short name T1092
Test name
Test status
Simulation time 580475330 ps
CPU time 9.38 seconds
Started Feb 08 06:46:41 PM UTC 25
Finished Feb 08 06:46:52 PM UTC 25
Peak memory 226836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925096102 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.925096102
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.951877925
Short name T1124
Test name
Test status
Simulation time 921406937 ps
CPU time 21.05 seconds
Started Feb 08 06:46:41 PM UTC 25
Finished Feb 08 06:47:04 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951877925 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.951877925
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1531946919
Short name T1088
Test name
Test status
Simulation time 75840994 ps
CPU time 3.62 seconds
Started Feb 08 06:46:46 PM UTC 25
Finished Feb 08 06:46:51 PM UTC 25
Peak memory 228628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1531946919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem
_rw_with_rand_reset.1531946919
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2544180641
Short name T1085
Test name
Test status
Simulation time 44818359 ps
CPU time 2 seconds
Started Feb 08 06:46:46 PM UTC 25
Finished Feb 08 06:46:49 PM UTC 25
Peak memory 225472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544180641 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.2544180641
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.182422910
Short name T1080
Test name
Test status
Simulation time 39249532 ps
CPU time 1.07 seconds
Started Feb 08 06:46:45 PM UTC 25
Finished Feb 08 06:46:47 PM UTC 25
Peak memory 211924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182422910 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.182422910
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2471571661
Short name T1095
Test name
Test status
Simulation time 2675405272 ps
CPU time 6.02 seconds
Started Feb 08 06:46:46 PM UTC 25
Finished Feb 08 06:46:53 PM UTC 25
Peak memory 226708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471571661 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.2471571661
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3670145426
Short name T1089
Test name
Test status
Simulation time 1102148690 ps
CPU time 5.7 seconds
Started Feb 08 06:46:45 PM UTC 25
Finished Feb 08 06:46:51 PM UTC 25
Peak memory 226528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670145426 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.3670145426
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3069474442
Short name T1136
Test name
Test status
Simulation time 1965210102 ps
CPU time 20.79 seconds
Started Feb 08 06:46:45 PM UTC 25
Finished Feb 08 06:47:07 PM UTC 25
Peak memory 226692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069474442 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.3069474442
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.771456713
Short name T1098
Test name
Test status
Simulation time 330778433 ps
CPU time 3.8 seconds
Started Feb 08 06:46:49 PM UTC 25
Finished Feb 08 06:46:54 PM UTC 25
Peak memory 228592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
771456713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_
rw_with_rand_reset.771456713
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.2665556762
Short name T1090
Test name
Test status
Simulation time 35156714 ps
CPU time 3.14 seconds
Started Feb 08 06:46:48 PM UTC 25
Finished Feb 08 06:46:52 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665556762 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.2665556762
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2448119730
Short name T1087
Test name
Test status
Simulation time 35037618 ps
CPU time 1.05 seconds
Started Feb 08 06:46:48 PM UTC 25
Finished Feb 08 06:46:50 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448119730 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.2448119730
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3755688073
Short name T1097
Test name
Test status
Simulation time 66563916 ps
CPU time 5.14 seconds
Started Feb 08 06:46:48 PM UTC 25
Finished Feb 08 06:46:54 PM UTC 25
Peak memory 226504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755688073 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstanding.3755688073
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.4260714256
Short name T1096
Test name
Test status
Simulation time 58675140 ps
CPU time 4.76 seconds
Started Feb 08 06:46:48 PM UTC 25
Finished Feb 08 06:46:54 PM UTC 25
Peak memory 226548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260714256 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.4260714256
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.4108308868
Short name T1120
Test name
Test status
Simulation time 1108538556 ps
CPU time 14.69 seconds
Started Feb 08 06:46:48 PM UTC 25
Finished Feb 08 06:47:04 PM UTC 25
Peak memory 226564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108308868 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.4108308868
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4212738470
Short name T1103
Test name
Test status
Simulation time 82070217 ps
CPU time 3.55 seconds
Started Feb 08 06:46:52 PM UTC 25
Finished Feb 08 06:46:57 PM UTC 25
Peak memory 228780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4212738470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem
_rw_with_rand_reset.4212738470
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.4283053965
Short name T1099
Test name
Test status
Simulation time 102679010 ps
CPU time 2.86 seconds
Started Feb 08 06:46:51 PM UTC 25
Finished Feb 08 06:46:55 PM UTC 25
Peak memory 226520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283053965 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.4283053965
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2839658799
Short name T1094
Test name
Test status
Simulation time 14667415 ps
CPU time 1.15 seconds
Started Feb 08 06:46:51 PM UTC 25
Finished Feb 08 06:46:53 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839658799 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.2839658799
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1179546168
Short name T1100
Test name
Test status
Simulation time 63717501 ps
CPU time 4.18 seconds
Started Feb 08 06:46:51 PM UTC 25
Finished Feb 08 06:46:56 PM UTC 25
Peak memory 226744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179546168 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.1179546168
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1603230336
Short name T1091
Test name
Test status
Simulation time 77195237 ps
CPU time 1.8 seconds
Started Feb 08 06:46:49 PM UTC 25
Finished Feb 08 06:46:52 PM UTC 25
Peak memory 225108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603230336 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.1603230336
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1866280721
Short name T222
Test name
Test status
Simulation time 399578409 ps
CPU time 9.23 seconds
Started Feb 08 06:46:49 PM UTC 25
Finished Feb 08 06:47:00 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866280721 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.1866280721
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2615663340
Short name T1105
Test name
Test status
Simulation time 92619970 ps
CPU time 3.46 seconds
Started Feb 08 06:46:55 PM UTC 25
Finished Feb 08 06:46:59 PM UTC 25
Peak memory 228832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2615663340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem
_rw_with_rand_reset.2615663340
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.1734214280
Short name T1104
Test name
Test status
Simulation time 290053401 ps
CPU time 2.84 seconds
Started Feb 08 06:46:54 PM UTC 25
Finished Feb 08 06:46:58 PM UTC 25
Peak memory 226716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734214280 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.1734214280
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.1417129209
Short name T1101
Test name
Test status
Simulation time 23585565 ps
CPU time 1.11 seconds
Started Feb 08 06:46:54 PM UTC 25
Finished Feb 08 06:46:57 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417129209 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.1417129209
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2447292248
Short name T1107
Test name
Test status
Simulation time 199094819 ps
CPU time 4.11 seconds
Started Feb 08 06:46:55 PM UTC 25
Finished Feb 08 06:47:00 PM UTC 25
Peak memory 226492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447292248 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.2447292248
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.4271896298
Short name T1102
Test name
Test status
Simulation time 47945851 ps
CPU time 3.46 seconds
Started Feb 08 06:46:52 PM UTC 25
Finished Feb 08 06:46:57 PM UTC 25
Peak memory 226532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271896298 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.4271896298
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.3990648659
Short name T1150
Test name
Test status
Simulation time 2224100242 ps
CPU time 22.69 seconds
Started Feb 08 06:46:54 PM UTC 25
Finished Feb 08 06:47:18 PM UTC 25
Peak memory 226572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990648659 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.3990648659
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.432105826
Short name T1112
Test name
Test status
Simulation time 520775273 ps
CPU time 3.55 seconds
Started Feb 08 06:46:57 PM UTC 25
Finished Feb 08 06:47:02 PM UTC 25
Peak memory 226500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
432105826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_
rw_with_rand_reset.432105826
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2578629955
Short name T1113
Test name
Test status
Simulation time 450409846 ps
CPU time 3.82 seconds
Started Feb 08 06:46:57 PM UTC 25
Finished Feb 08 06:47:02 PM UTC 25
Peak memory 226448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578629955 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.2578629955
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1537594009
Short name T1106
Test name
Test status
Simulation time 36170788 ps
CPU time 1.1 seconds
Started Feb 08 06:46:57 PM UTC 25
Finished Feb 08 06:46:59 PM UTC 25
Peak memory 211112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537594009 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.1537594009
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4071222910
Short name T1109
Test name
Test status
Simulation time 559643885 ps
CPU time 2.78 seconds
Started Feb 08 06:46:57 PM UTC 25
Finished Feb 08 06:47:01 PM UTC 25
Peak memory 226636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071222910 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstanding.4071222910
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.629960424
Short name T214
Test name
Test status
Simulation time 139408212 ps
CPU time 5.05 seconds
Started Feb 08 06:46:55 PM UTC 25
Finished Feb 08 06:47:01 PM UTC 25
Peak memory 226588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629960424 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.629960424
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.572510828
Short name T1115
Test name
Test status
Simulation time 106798273 ps
CPU time 2.36 seconds
Started Feb 08 06:46:59 PM UTC 25
Finished Feb 08 06:47:03 PM UTC 25
Peak memory 226584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
572510828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_
rw_with_rand_reset.572510828
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.3934913668
Short name T1114
Test name
Test status
Simulation time 48355218 ps
CPU time 1.98 seconds
Started Feb 08 06:46:59 PM UTC 25
Finished Feb 08 06:47:02 PM UTC 25
Peak memory 225496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934913668 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.3934913668
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3130413837
Short name T1108
Test name
Test status
Simulation time 15147613 ps
CPU time 1.16 seconds
Started Feb 08 06:46:57 PM UTC 25
Finished Feb 08 06:47:00 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130413837 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.3130413837
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3555802851
Short name T1116
Test name
Test status
Simulation time 84093956 ps
CPU time 2.73 seconds
Started Feb 08 06:46:59 PM UTC 25
Finished Feb 08 06:47:03 PM UTC 25
Peak memory 226708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555802851 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.3555802851
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.2443838041
Short name T1110
Test name
Test status
Simulation time 57349636 ps
CPU time 2.84 seconds
Started Feb 08 06:46:57 PM UTC 25
Finished Feb 08 06:47:01 PM UTC 25
Peak memory 226588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443838041 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.2443838041
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.1579090071
Short name T1151
Test name
Test status
Simulation time 1087420276 ps
CPU time 21.99 seconds
Started Feb 08 06:46:57 PM UTC 25
Finished Feb 08 06:47:21 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579090071 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.1579090071
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.4127268946
Short name T145
Test name
Test status
Simulation time 1480673560 ps
CPU time 11.72 seconds
Started Feb 08 06:46:04 PM UTC 25
Finished Feb 08 06:46:17 PM UTC 25
Peak memory 214252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127268946 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.4127268946
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1034806609
Short name T1066
Test name
Test status
Simulation time 2443418321 ps
CPU time 33.8 seconds
Started Feb 08 06:46:04 PM UTC 25
Finished Feb 08 06:46:39 PM UTC 25
Peak memory 214448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034806609 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.1034806609
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.442823055
Short name T1042
Test name
Test status
Simulation time 74207520 ps
CPU time 1.46 seconds
Started Feb 08 06:46:03 PM UTC 25
Finished Feb 08 06:46:05 PM UTC 25
Peak memory 213496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442823055 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.442823055
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1643233533
Short name T135
Test name
Test status
Simulation time 56781840 ps
CPU time 2.04 seconds
Started Feb 08 06:46:05 PM UTC 25
Finished Feb 08 06:46:08 PM UTC 25
Peak memory 226780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1643233533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_
rw_with_rand_reset.1643233533
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1943854766
Short name T1038
Test name
Test status
Simulation time 18129784 ps
CPU time 1.11 seconds
Started Feb 08 06:46:00 PM UTC 25
Finished Feb 08 06:46:02 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943854766 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1943854766
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1339228972
Short name T139
Test name
Test status
Simulation time 190660084 ps
CPU time 2.36 seconds
Started Feb 08 06:46:03 PM UTC 25
Finished Feb 08 06:46:06 PM UTC 25
Peak memory 226680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339228972 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.1339228972
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1418369214
Short name T1040
Test name
Test status
Simulation time 12969448 ps
CPU time 1.05 seconds
Started Feb 08 06:46:02 PM UTC 25
Finished Feb 08 06:46:04 PM UTC 25
Peak memory 211832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418369214 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.1418369214
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3990694245
Short name T176
Test name
Test status
Simulation time 880784454 ps
CPU time 3.66 seconds
Started Feb 08 06:46:05 PM UTC 25
Finished Feb 08 06:46:10 PM UTC 25
Peak memory 226492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990694245 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.3990694245
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2331426054
Short name T121
Test name
Test status
Simulation time 268767721 ps
CPU time 6.34 seconds
Started Feb 08 06:45:59 PM UTC 25
Finished Feb 08 06:46:07 PM UTC 25
Peak memory 226048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331426054 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2331426054
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2518849731
Short name T124
Test name
Test status
Simulation time 1835236334 ps
CPU time 20.82 seconds
Started Feb 08 06:45:59 PM UTC 25
Finished Feb 08 06:46:22 PM UTC 25
Peak memory 226452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518849731 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.2518849731
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.167045222
Short name T1111
Test name
Test status
Simulation time 21492414 ps
CPU time 0.97 seconds
Started Feb 08 06:46:59 PM UTC 25
Finished Feb 08 06:47:01 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167045222 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.167045222
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.4075991289
Short name T1121
Test name
Test status
Simulation time 16488203 ps
CPU time 1.1 seconds
Started Feb 08 06:47:01 PM UTC 25
Finished Feb 08 06:47:04 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075991289 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.4075991289
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3376560054
Short name T1119
Test name
Test status
Simulation time 55629356 ps
CPU time 1.01 seconds
Started Feb 08 06:47:02 PM UTC 25
Finished Feb 08 06:47:04 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376560054 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.3376560054
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1379071827
Short name T1122
Test name
Test status
Simulation time 16315351 ps
CPU time 1.1 seconds
Started Feb 08 06:47:02 PM UTC 25
Finished Feb 08 06:47:04 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379071827 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.1379071827
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2921595992
Short name T1123
Test name
Test status
Simulation time 20017610 ps
CPU time 1.09 seconds
Started Feb 08 06:47:02 PM UTC 25
Finished Feb 08 06:47:04 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921595992 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.2921595992
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.989849161
Short name T1117
Test name
Test status
Simulation time 38039049 ps
CPU time 0.78 seconds
Started Feb 08 06:47:02 PM UTC 25
Finished Feb 08 06:47:04 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989849161 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.989849161
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1172143891
Short name T1118
Test name
Test status
Simulation time 17979134 ps
CPU time 0.84 seconds
Started Feb 08 06:47:02 PM UTC 25
Finished Feb 08 06:47:04 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172143891 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.1172143891
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3118621333
Short name T1128
Test name
Test status
Simulation time 40265412 ps
CPU time 0.97 seconds
Started Feb 08 06:47:04 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 211008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118621333 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.3118621333
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2081023525
Short name T1129
Test name
Test status
Simulation time 12949025 ps
CPU time 1.03 seconds
Started Feb 08 06:47:04 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 211308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081023525 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.2081023525
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.3744451398
Short name T1126
Test name
Test status
Simulation time 20815733 ps
CPU time 0.91 seconds
Started Feb 08 06:47:04 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 211748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744451398 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.3744451398
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1252899279
Short name T147
Test name
Test status
Simulation time 3147398881 ps
CPU time 18.15 seconds
Started Feb 08 06:46:10 PM UTC 25
Finished Feb 08 06:46:29 PM UTC 25
Peak memory 226600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252899279 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.1252899279
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.900420166
Short name T1048
Test name
Test status
Simulation time 1223294495 ps
CPU time 22.58 seconds
Started Feb 08 06:46:10 PM UTC 25
Finished Feb 08 06:46:34 PM UTC 25
Peak memory 214216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900420166 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.900420166
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.610305544
Short name T107
Test name
Test status
Simulation time 54225155 ps
CPU time 1.71 seconds
Started Feb 08 06:46:08 PM UTC 25
Finished Feb 08 06:46:11 PM UTC 25
Peak memory 213564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610305544 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.610305544
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1583270120
Short name T136
Test name
Test status
Simulation time 89152847 ps
CPU time 3.25 seconds
Started Feb 08 06:46:11 PM UTC 25
Finished Feb 08 06:46:15 PM UTC 25
Peak memory 226576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1583270120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_
rw_with_rand_reset.1583270120
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.3861118363
Short name T142
Test name
Test status
Simulation time 64903349 ps
CPU time 1.87 seconds
Started Feb 08 06:46:08 PM UTC 25
Finished Feb 08 06:46:11 PM UTC 25
Peak memory 225240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861118363 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3861118363
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.689636132
Short name T1044
Test name
Test status
Simulation time 27207464 ps
CPU time 1.09 seconds
Started Feb 08 06:46:07 PM UTC 25
Finished Feb 08 06:46:09 PM UTC 25
Peak memory 211900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689636132 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.689636132
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2244159030
Short name T143
Test name
Test status
Simulation time 27901621 ps
CPU time 3.2 seconds
Started Feb 08 06:46:07 PM UTC 25
Finished Feb 08 06:46:12 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244159030 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.2244159030
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.672416085
Short name T1043
Test name
Test status
Simulation time 21933544 ps
CPU time 1.03 seconds
Started Feb 08 06:46:07 PM UTC 25
Finished Feb 08 06:46:09 PM UTC 25
Peak memory 211832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672416085 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.672416085
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.489028862
Short name T181
Test name
Test status
Simulation time 139345847 ps
CPU time 2.38 seconds
Started Feb 08 06:46:10 PM UTC 25
Finished Feb 08 06:46:13 PM UTC 25
Peak memory 226432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489028862 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.489028862
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2445889019
Short name T1127
Test name
Test status
Simulation time 37262959 ps
CPU time 0.87 seconds
Started Feb 08 06:47:04 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 211820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445889019 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.2445889019
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.143261318
Short name T1132
Test name
Test status
Simulation time 42543492 ps
CPU time 0.99 seconds
Started Feb 08 06:47:04 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143261318 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.143261318
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.1829092509
Short name T1130
Test name
Test status
Simulation time 15008620 ps
CPU time 0.86 seconds
Started Feb 08 06:47:04 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829092509 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.1829092509
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3149438214
Short name T1131
Test name
Test status
Simulation time 40891641 ps
CPU time 0.92 seconds
Started Feb 08 06:47:04 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149438214 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.3149438214
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.437307470
Short name T1133
Test name
Test status
Simulation time 58638256 ps
CPU time 0.87 seconds
Started Feb 08 06:47:04 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437307470 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.437307470
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2999770563
Short name T1134
Test name
Test status
Simulation time 18650010 ps
CPU time 0.88 seconds
Started Feb 08 06:47:04 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999770563 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.2999770563
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2391706863
Short name T1135
Test name
Test status
Simulation time 48868152 ps
CPU time 1.03 seconds
Started Feb 08 06:47:04 PM UTC 25
Finished Feb 08 06:47:06 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391706863 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.2391706863
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3175694517
Short name T1138
Test name
Test status
Simulation time 19217980 ps
CPU time 0.76 seconds
Started Feb 08 06:47:07 PM UTC 25
Finished Feb 08 06:47:09 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175694517 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.3175694517
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2496946310
Short name T1143
Test name
Test status
Simulation time 20810027 ps
CPU time 1.01 seconds
Started Feb 08 06:47:07 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496946310 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.2496946310
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.1490353019
Short name T1139
Test name
Test status
Simulation time 18131733 ps
CPU time 0.88 seconds
Started Feb 08 06:47:07 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490353019 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.1490353019
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3557508874
Short name T148
Test name
Test status
Simulation time 2761791817 ps
CPU time 16.06 seconds
Started Feb 08 06:46:16 PM UTC 25
Finished Feb 08 06:46:33 PM UTC 25
Peak memory 214232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557508874 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.3557508874
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4012553002
Short name T1067
Test name
Test status
Simulation time 1518836049 ps
CPU time 23.65 seconds
Started Feb 08 06:46:14 PM UTC 25
Finished Feb 08 06:46:39 PM UTC 25
Peak memory 214252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012553002 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.4012553002
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3991993567
Short name T108
Test name
Test status
Simulation time 55413771 ps
CPU time 2.09 seconds
Started Feb 08 06:46:13 PM UTC 25
Finished Feb 08 06:46:17 PM UTC 25
Peak memory 226720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991993567 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.3991993567
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.683343747
Short name T177
Test name
Test status
Simulation time 640697611 ps
CPU time 5.18 seconds
Started Feb 08 06:46:17 PM UTC 25
Finished Feb 08 06:46:23 PM UTC 25
Peak memory 226528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
683343747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_r
w_with_rand_reset.683343747
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.3273604311
Short name T1047
Test name
Test status
Simulation time 62705868 ps
CPU time 1.76 seconds
Started Feb 08 06:46:14 PM UTC 25
Finished Feb 08 06:46:17 PM UTC 25
Peak memory 213208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273604311 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3273604311
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.3335938399
Short name T1046
Test name
Test status
Simulation time 59972472 ps
CPU time 0.98 seconds
Started Feb 08 06:46:12 PM UTC 25
Finished Feb 08 06:46:14 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335938399 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3335938399
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1248189804
Short name T144
Test name
Test status
Simulation time 31726683 ps
CPU time 1.55 seconds
Started Feb 08 06:46:12 PM UTC 25
Finished Feb 08 06:46:15 PM UTC 25
Peak memory 225412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248189804 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.1248189804
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2381605283
Short name T1045
Test name
Test status
Simulation time 12556659 ps
CPU time 0.8 seconds
Started Feb 08 06:46:12 PM UTC 25
Finished Feb 08 06:46:14 PM UTC 25
Peak memory 211832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381605283 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.2381605283
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2649397086
Short name T1050
Test name
Test status
Simulation time 655389945 ps
CPU time 5.85 seconds
Started Feb 08 06:46:16 PM UTC 25
Finished Feb 08 06:46:23 PM UTC 25
Peak memory 226708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649397086 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.2649397086
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.1399138948
Short name T129
Test name
Test status
Simulation time 55974955 ps
CPU time 5.31 seconds
Started Feb 08 06:46:11 PM UTC 25
Finished Feb 08 06:46:17 PM UTC 25
Peak memory 226816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399138948 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1399138948
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.336778347
Short name T217
Test name
Test status
Simulation time 315179439 ps
CPU time 22.49 seconds
Started Feb 08 06:46:11 PM UTC 25
Finished Feb 08 06:46:35 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336778347 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.336778347
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3801787126
Short name T1137
Test name
Test status
Simulation time 14455284 ps
CPU time 0.73 seconds
Started Feb 08 06:47:07 PM UTC 25
Finished Feb 08 06:47:09 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801787126 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.3801787126
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.270410015
Short name T1141
Test name
Test status
Simulation time 17603869 ps
CPU time 0.93 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270410015 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.270410015
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3265855088
Short name T1142
Test name
Test status
Simulation time 11020150 ps
CPU time 0.81 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265855088 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.3265855088
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.3210701309
Short name T1146
Test name
Test status
Simulation time 11298974 ps
CPU time 1.01 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210701309 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.3210701309
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1241940413
Short name T1140
Test name
Test status
Simulation time 40720527 ps
CPU time 0.76 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241940413 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.1241940413
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1555287488
Short name T1145
Test name
Test status
Simulation time 15838109 ps
CPU time 0.92 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555287488 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.1555287488
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2198318047
Short name T1144
Test name
Test status
Simulation time 18577262 ps
CPU time 0.9 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198318047 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.2198318047
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.882355199
Short name T1147
Test name
Test status
Simulation time 12413091 ps
CPU time 0.92 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882355199 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.882355199
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1666423356
Short name T1149
Test name
Test status
Simulation time 138656290 ps
CPU time 0.93 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666423356 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.1666423356
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.1764653617
Short name T1148
Test name
Test status
Simulation time 42040267 ps
CPU time 0.79 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 211836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764653617 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.1764653617
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2434911422
Short name T178
Test name
Test status
Simulation time 175810018 ps
CPU time 2.43 seconds
Started Feb 08 06:46:21 PM UTC 25
Finished Feb 08 06:46:25 PM UTC 25
Peak memory 226524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2434911422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_
rw_with_rand_reset.2434911422
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3125696159
Short name T146
Test name
Test status
Simulation time 239267628 ps
CPU time 2.88 seconds
Started Feb 08 06:46:18 PM UTC 25
Finished Feb 08 06:46:22 PM UTC 25
Peak memory 214336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125696159 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3125696159
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.4101578809
Short name T1049
Test name
Test status
Simulation time 36379370 ps
CPU time 1.06 seconds
Started Feb 08 06:46:18 PM UTC 25
Finished Feb 08 06:46:20 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101578809 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4101578809
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2019851307
Short name T179
Test name
Test status
Simulation time 124475099 ps
CPU time 3.92 seconds
Started Feb 08 06:46:21 PM UTC 25
Finished Feb 08 06:46:26 PM UTC 25
Peak memory 226320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019851307 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.2019851307
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.1119172012
Short name T1059
Test name
Test status
Simulation time 927551992 ps
CPU time 15.31 seconds
Started Feb 08 06:46:18 PM UTC 25
Finished Feb 08 06:46:34 PM UTC 25
Peak memory 225836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119172012 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.1119172012
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3911925548
Short name T1055
Test name
Test status
Simulation time 42003536 ps
CPU time 3.72 seconds
Started Feb 08 06:46:26 PM UTC 25
Finished Feb 08 06:46:30 PM UTC 25
Peak memory 226840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3911925548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_
rw_with_rand_reset.3911925548
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3245843460
Short name T1053
Test name
Test status
Simulation time 168811867 ps
CPU time 3.48 seconds
Started Feb 08 06:46:24 PM UTC 25
Finished Feb 08 06:46:28 PM UTC 25
Peak memory 226448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245843460 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3245843460
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1841954765
Short name T1051
Test name
Test status
Simulation time 14505686 ps
CPU time 1.1 seconds
Started Feb 08 06:46:23 PM UTC 25
Finished Feb 08 06:46:26 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841954765 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1841954765
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2292976416
Short name T1052
Test name
Test status
Simulation time 58254245 ps
CPU time 2.56 seconds
Started Feb 08 06:46:24 PM UTC 25
Finished Feb 08 06:46:27 PM UTC 25
Peak memory 214384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292976416 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.2292976416
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3659826096
Short name T127
Test name
Test status
Simulation time 150251198 ps
CPU time 5.79 seconds
Started Feb 08 06:46:22 PM UTC 25
Finished Feb 08 06:46:29 PM UTC 25
Peak memory 228888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659826096 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3659826096
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3696827362
Short name T220
Test name
Test status
Simulation time 551546329 ps
CPU time 17.53 seconds
Started Feb 08 06:46:23 PM UTC 25
Finished Feb 08 06:46:42 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696827362 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.3696827362
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2745251210
Short name T1056
Test name
Test status
Simulation time 204735937 ps
CPU time 2.09 seconds
Started Feb 08 06:46:30 PM UTC 25
Finished Feb 08 06:46:33 PM UTC 25
Peak memory 226548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2745251210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_
rw_with_rand_reset.2745251210
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2242395326
Short name T149
Test name
Test status
Simulation time 272862286 ps
CPU time 2.95 seconds
Started Feb 08 06:46:29 PM UTC 25
Finished Feb 08 06:46:33 PM UTC 25
Peak memory 216468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242395326 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2242395326
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.2511623204
Short name T1054
Test name
Test status
Simulation time 26531023 ps
CPU time 1.11 seconds
Started Feb 08 06:46:28 PM UTC 25
Finished Feb 08 06:46:30 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511623204 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2511623204
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4264283010
Short name T1058
Test name
Test status
Simulation time 106773180 ps
CPU time 3.9 seconds
Started Feb 08 06:46:29 PM UTC 25
Finished Feb 08 06:46:34 PM UTC 25
Peak memory 226432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264283010 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.4264283010
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.2580661436
Short name T130
Test name
Test status
Simulation time 107017541 ps
CPU time 4.39 seconds
Started Feb 08 06:46:27 PM UTC 25
Finished Feb 08 06:46:32 PM UTC 25
Peak memory 226620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580661436 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2580661436
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.4262180155
Short name T218
Test name
Test status
Simulation time 1804612132 ps
CPU time 20.38 seconds
Started Feb 08 06:46:27 PM UTC 25
Finished Feb 08 06:46:48 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262180155 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.4262180155
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1270471653
Short name T1065
Test name
Test status
Simulation time 356004490 ps
CPU time 3.77 seconds
Started Feb 08 06:46:34 PM UTC 25
Finished Feb 08 06:46:39 PM UTC 25
Peak memory 226796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1270471653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_
rw_with_rand_reset.1270471653
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.4173293340
Short name T150
Test name
Test status
Simulation time 29365751 ps
CPU time 2.64 seconds
Started Feb 08 06:46:33 PM UTC 25
Finished Feb 08 06:46:36 PM UTC 25
Peak memory 226580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173293340 -assert nopostproc +UVM_TESTNAME=spi_devic
e_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_
device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4173293340
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.4102692669
Short name T1057
Test name
Test status
Simulation time 37705308 ps
CPU time 1.09 seconds
Started Feb 08 06:46:31 PM UTC 25
Finished Feb 08 06:46:34 PM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102692669 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4102692669
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4087386696
Short name T1062
Test name
Test status
Simulation time 410245305 ps
CPU time 3.41 seconds
Started Feb 08 06:46:33 PM UTC 25
Finished Feb 08 06:46:37 PM UTC 25
Peak memory 226516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087386696 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.4087386696
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3318170554
Short name T1060
Test name
Test status
Simulation time 1039023514 ps
CPU time 3.22 seconds
Started Feb 08 06:46:30 PM UTC 25
Finished Feb 08 06:46:35 PM UTC 25
Peak memory 226600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318170554 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3318170554
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2664727378
Short name T1093
Test name
Test status
Simulation time 3051511453 ps
CPU time 20.12 seconds
Started Feb 08 06:46:31 PM UTC 25
Finished Feb 08 06:46:53 PM UTC 25
Peak memory 226576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664727378 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.2664727378
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1499553504
Short name T1068
Test name
Test status
Simulation time 349213125 ps
CPU time 3.06 seconds
Started Feb 08 06:46:35 PM UTC 25
Finished Feb 08 06:46:40 PM UTC 25
Peak memory 226524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1499553504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_
rw_with_rand_reset.1499553504
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.162941867
Short name T1064
Test name
Test status
Simulation time 146787392 ps
CPU time 2.77 seconds
Started Feb 08 06:46:34 PM UTC 25
Finished Feb 08 06:46:38 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162941867 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d
evice_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.162941867
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.429497697
Short name T1061
Test name
Test status
Simulation time 12378159 ps
CPU time 1.09 seconds
Started Feb 08 06:46:34 PM UTC 25
Finished Feb 08 06:46:36 PM UTC 25
Peak memory 211900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429497697 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.429497697
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.694105923
Short name T1071
Test name
Test status
Simulation time 217916800 ps
CPU time 5.08 seconds
Started Feb 08 06:46:34 PM UTC 25
Finished Feb 08 06:46:40 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694105923 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.694105923
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.4144431315
Short name T215
Test name
Test status
Simulation time 1253033287 ps
CPU time 7.92 seconds
Started Feb 08 06:46:34 PM UTC 25
Finished Feb 08 06:46:43 PM UTC 25
Peak memory 226680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144431315 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.4144431315
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3789490710
Short name T12
Test name
Test status
Simulation time 164759385 ps
CPU time 4.45 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:29:51 PM UTC 25
Peak memory 234928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789490710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3789490710
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1944598997
Short name T70
Test name
Test status
Simulation time 18185659753 ps
CPU time 174.08 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:32:43 PM UTC 25
Peak memory 261876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944598997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1944598997
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.1596505079
Short name T212
Test name
Test status
Simulation time 27204492169 ps
CPU time 89.81 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:31:17 PM UTC 25
Peak memory 261904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596505079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1596505079
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1599087463
Short name T117
Test name
Test status
Simulation time 84156070564 ps
CPU time 225.35 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:33:34 PM UTC 25
Peak memory 251700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599087463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.1599087463
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.1752384046
Short name T15
Test name
Test status
Simulation time 1550724569 ps
CPU time 6.37 seconds
Started Feb 08 06:29:44 PM UTC 25
Finished Feb 08 06:29:52 PM UTC 25
Peak memory 245136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752384046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1752384046
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.1623622082
Short name T3
Test name
Test status
Simulation time 117603265 ps
CPU time 1.27 seconds
Started Feb 08 06:29:43 PM UTC 25
Finished Feb 08 06:29:45 PM UTC 25
Peak memory 229136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623622082 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_parity.1623622082
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1572342594
Short name T57
Test name
Test status
Simulation time 3641875009 ps
CPU time 21.87 seconds
Started Feb 08 06:29:44 PM UTC 25
Finished Feb 08 06:30:08 PM UTC 25
Peak memory 245528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572342594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1572342594
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1301887869
Short name T21
Test name
Test status
Simulation time 397452363 ps
CPU time 11.74 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:29:59 PM UTC 25
Peak memory 233592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301887869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.1301887869
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1920553255
Short name T30
Test name
Test status
Simulation time 39131807666 ps
CPU time 19.81 seconds
Started Feb 08 06:29:44 PM UTC 25
Finished Feb 08 06:30:05 PM UTC 25
Peak memory 227412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920553255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1920553255
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.12686381
Short name T32
Test name
Test status
Simulation time 56736440513 ps
CPU time 25.36 seconds
Started Feb 08 06:29:43 PM UTC 25
Finished Feb 08 06:30:10 PM UTC 25
Peak memory 227416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12686381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.12686381
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2784708908
Short name T4
Test name
Test status
Simulation time 134027768 ps
CPU time 1.28 seconds
Started Feb 08 06:29:44 PM UTC 25
Finished Feb 08 06:29:47 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784708908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2784708908
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.3743971772
Short name T55
Test name
Test status
Simulation time 3698408555 ps
CPU time 18.03 seconds
Started Feb 08 06:29:44 PM UTC 25
Finished Feb 08 06:30:04 PM UTC 25
Peak memory 245176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743971772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3743971772
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.3392171550
Short name T41
Test name
Test status
Simulation time 40224148 ps
CPU time 1.08 seconds
Started Feb 08 06:29:55 PM UTC 25
Finished Feb 08 06:29:57 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392171550 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3392171550
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.640428933
Short name T92
Test name
Test status
Simulation time 3348001228 ps
CPU time 24.31 seconds
Started Feb 08 06:29:50 PM UTC 25
Finished Feb 08 06:30:16 PM UTC 25
Peak memory 245468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640428933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.640428933
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.1826217208
Short name T7
Test name
Test status
Simulation time 16108349 ps
CPU time 1.09 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:29:48 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826217208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1826217208
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.3715357425
Short name T40
Test name
Test status
Simulation time 81466014 ps
CPU time 1.29 seconds
Started Feb 08 06:29:53 PM UTC 25
Finished Feb 08 06:29:55 PM UTC 25
Peak memory 225412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715357425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3715357425
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.305449319
Short name T53
Test name
Test status
Simulation time 4145483424 ps
CPU time 32.46 seconds
Started Feb 08 06:29:53 PM UTC 25
Finished Feb 08 06:30:27 PM UTC 25
Peak memory 261708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305449319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.305449319
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.547774705
Short name T22
Test name
Test status
Simulation time 482819562 ps
CPU time 9.48 seconds
Started Feb 08 06:29:49 PM UTC 25
Finished Feb 08 06:30:00 PM UTC 25
Peak memory 245136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547774705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.547774705
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.4014784149
Short name T18
Test name
Test status
Simulation time 461037000 ps
CPU time 6.16 seconds
Started Feb 08 06:29:48 PM UTC 25
Finished Feb 08 06:29:56 PM UTC 25
Peak memory 245400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014784149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4014784149
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.823929738
Short name T23
Test name
Test status
Simulation time 341673444 ps
CPU time 6.67 seconds
Started Feb 08 06:29:53 PM UTC 25
Finished Feb 08 06:30:00 PM UTC 25
Peak memory 233508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823929738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.823929738
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.3238235078
Short name T19
Test name
Test status
Simulation time 158540574 ps
CPU time 1.7 seconds
Started Feb 08 06:29:55 PM UTC 25
Finished Feb 08 06:29:58 PM UTC 25
Peak memory 257532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238235078 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3238235078
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.4235887301
Short name T913
Test name
Test status
Simulation time 80528918338 ps
CPU time 839.54 seconds
Started Feb 08 06:29:54 PM UTC 25
Finished Feb 08 06:44:03 PM UTC 25
Peak memory 294544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235887301 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.4235887301
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1518666349
Short name T28
Test name
Test status
Simulation time 3665539083 ps
CPU time 15.24 seconds
Started Feb 08 06:29:46 PM UTC 25
Finished Feb 08 06:30:03 PM UTC 25
Peak memory 227384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518666349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1518666349
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.3833798336
Short name T13
Test name
Test status
Simulation time 97421084 ps
CPU time 1.98 seconds
Started Feb 08 06:29:48 PM UTC 25
Finished Feb 08 06:29:51 PM UTC 25
Peak memory 226468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833798336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3833798336
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.265334874
Short name T10
Test name
Test status
Simulation time 28344768 ps
CPU time 1.05 seconds
Started Feb 08 06:29:47 PM UTC 25
Finished Feb 08 06:29:49 PM UTC 25
Peak memory 215956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265334874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.265334874
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.2594989297
Short name T16
Test name
Test status
Simulation time 50184740 ps
CPU time 3.05 seconds
Started Feb 08 06:29:49 PM UTC 25
Finished Feb 08 06:29:53 PM UTC 25
Peak memory 234904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594989297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2594989297
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.3248395466
Short name T455
Test name
Test status
Simulation time 13565528 ps
CPU time 1.1 seconds
Started Feb 08 06:32:35 PM UTC 25
Finished Feb 08 06:32:37 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248395466 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.3248395466
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.666877544
Short name T330
Test name
Test status
Simulation time 663284614 ps
CPU time 4.99 seconds
Started Feb 08 06:32:27 PM UTC 25
Finished Feb 08 06:32:33 PM UTC 25
Peak memory 235132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666877544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.666877544
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.2704844408
Short name T194
Test name
Test status
Simulation time 232184873 ps
CPU time 1.18 seconds
Started Feb 08 06:32:20 PM UTC 25
Finished Feb 08 06:32:22 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704844408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2704844408
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.4148621879
Short name T454
Test name
Test status
Simulation time 16064495 ps
CPU time 1.17 seconds
Started Feb 08 06:32:32 PM UTC 25
Finished Feb 08 06:32:34 PM UTC 25
Peak memory 225476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148621879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4148621879
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.208657067
Short name T398
Test name
Test status
Simulation time 18308805847 ps
CPU time 68.14 seconds
Started Feb 08 06:32:33 PM UTC 25
Finished Feb 08 06:33:43 PM UTC 25
Peak memory 251700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208657067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.208657067
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2601067754
Short name T299
Test name
Test status
Simulation time 13397050758 ps
CPU time 99.6 seconds
Started Feb 08 06:32:29 PM UTC 25
Finished Feb 08 06:34:11 PM UTC 25
Peak memory 234776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601067754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.2601067754
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.2503397531
Short name T244
Test name
Test status
Simulation time 7973602549 ps
CPU time 18.99 seconds
Started Feb 08 06:32:26 PM UTC 25
Finished Feb 08 06:32:46 PM UTC 25
Peak memory 245248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503397531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2503397531
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.3710816571
Short name T452
Test name
Test status
Simulation time 158649280 ps
CPU time 3.43 seconds
Started Feb 08 06:32:26 PM UTC 25
Finished Feb 08 06:32:31 PM UTC 25
Peak memory 235000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710816571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3710816571
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.2203314438
Short name T196
Test name
Test status
Simulation time 50741124 ps
CPU time 1.51 seconds
Started Feb 08 06:32:21 PM UTC 25
Finished Feb 08 06:32:23 PM UTC 25
Peak memory 229192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203314438 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mem_parity.2203314438
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.194027775
Short name T68
Test name
Test status
Simulation time 69806589 ps
CPU time 3.83 seconds
Started Feb 08 06:32:24 PM UTC 25
Finished Feb 08 06:32:29 PM UTC 25
Peak memory 245176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194027775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.194027775
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1611466450
Short name T312
Test name
Test status
Simulation time 124620447 ps
CPU time 3.39 seconds
Started Feb 08 06:32:24 PM UTC 25
Finished Feb 08 06:32:29 PM UTC 25
Peak memory 245172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611466450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1611466450
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.158344787
Short name T457
Test name
Test status
Simulation time 317997255 ps
CPU time 5.73 seconds
Started Feb 08 06:32:32 PM UTC 25
Finished Feb 08 06:32:38 PM UTC 25
Peak memory 231284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158344787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.158344787
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.811391501
Short name T200
Test name
Test status
Simulation time 30353167943 ps
CPU time 128.66 seconds
Started Feb 08 06:32:35 PM UTC 25
Finished Feb 08 06:34:46 PM UTC 25
Peak memory 267836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811391501 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.811391501
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.475159129
Short name T466
Test name
Test status
Simulation time 5852013045 ps
CPU time 36.24 seconds
Started Feb 08 06:32:21 PM UTC 25
Finished Feb 08 06:32:58 PM UTC 25
Peak memory 227416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475159129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.475159129
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.3223206877
Short name T451
Test name
Test status
Simulation time 42528578 ps
CPU time 2.47 seconds
Started Feb 08 06:32:23 PM UTC 25
Finished Feb 08 06:32:27 PM UTC 25
Peak memory 227380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223206877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3223206877
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.294032906
Short name T198
Test name
Test status
Simulation time 53944936 ps
CPU time 1.22 seconds
Started Feb 08 06:32:23 PM UTC 25
Finished Feb 08 06:32:25 PM UTC 25
Peak memory 215812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294032906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.294032906
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.4063372830
Short name T305
Test name
Test status
Simulation time 3103923262 ps
CPU time 6.6 seconds
Started Feb 08 06:32:27 PM UTC 25
Finished Feb 08 06:32:35 PM UTC 25
Peak memory 241860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063372830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4063372830
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.1623207056
Short name T463
Test name
Test status
Simulation time 196389115 ps
CPU time 1.14 seconds
Started Feb 08 06:32:56 PM UTC 25
Finished Feb 08 06:32:58 PM UTC 25
Peak memory 215452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623207056 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.1623207056
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.4224873685
Short name T225
Test name
Test status
Simulation time 403924414 ps
CPU time 3.72 seconds
Started Feb 08 06:32:48 PM UTC 25
Finished Feb 08 06:32:52 PM UTC 25
Peak memory 234872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224873685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4224873685
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.1014027786
Short name T456
Test name
Test status
Simulation time 33847959 ps
CPU time 1.21 seconds
Started Feb 08 06:32:36 PM UTC 25
Finished Feb 08 06:32:38 PM UTC 25
Peak memory 215956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014027786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1014027786
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.2856961353
Short name T520
Test name
Test status
Simulation time 5991008218 ps
CPU time 107.32 seconds
Started Feb 08 06:32:52 PM UTC 25
Finished Feb 08 06:34:41 PM UTC 25
Peak memory 263704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856961353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2856961353
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2826873629
Short name T273
Test name
Test status
Simulation time 56772239871 ps
CPU time 167.04 seconds
Started Feb 08 06:32:53 PM UTC 25
Finished Feb 08 06:35:43 PM UTC 25
Peak memory 263736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826873629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2826873629
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.2715091607
Short name T462
Test name
Test status
Simulation time 159684777 ps
CPU time 4.36 seconds
Started Feb 08 06:32:48 PM UTC 25
Finished Feb 08 06:32:53 PM UTC 25
Peak memory 245168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715091607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2715091607
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.4123677284
Short name T461
Test name
Test status
Simulation time 34823742 ps
CPU time 1.19 seconds
Started Feb 08 06:32:50 PM UTC 25
Finished Feb 08 06:32:52 PM UTC 25
Peak memory 225412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123677284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.4123677284
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.561280377
Short name T264
Test name
Test status
Simulation time 175144592 ps
CPU time 3.67 seconds
Started Feb 08 06:32:42 PM UTC 25
Finished Feb 08 06:32:47 PM UTC 25
Peak memory 234880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561280377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.561280377
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.1212608704
Short name T279
Test name
Test status
Simulation time 781774988 ps
CPU time 18.39 seconds
Started Feb 08 06:32:43 PM UTC 25
Finished Feb 08 06:33:03 PM UTC 25
Peak memory 251348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212608704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1212608704
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.3937853700
Short name T458
Test name
Test status
Simulation time 152143937 ps
CPU time 1.62 seconds
Started Feb 08 06:32:36 PM UTC 25
Finished Feb 08 06:32:39 PM UTC 25
Peak memory 229192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937853700 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mem_parity.3937853700
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1214515823
Short name T280
Test name
Test status
Simulation time 7333604376 ps
CPU time 41.72 seconds
Started Feb 08 06:32:42 PM UTC 25
Finished Feb 08 06:33:26 PM UTC 25
Peak memory 247424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214515823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.1214515823
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.593162211
Short name T284
Test name
Test status
Simulation time 33157277340 ps
CPU time 49.74 seconds
Started Feb 08 06:32:40 PM UTC 25
Finished Feb 08 06:33:32 PM UTC 25
Peak memory 245156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593162211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.593162211
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.617888641
Short name T465
Test name
Test status
Simulation time 391131129 ps
CPU time 5.53 seconds
Started Feb 08 06:32:52 PM UTC 25
Finished Feb 08 06:32:58 PM UTC 25
Peak memory 233820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617888641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.617888641
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.1985030218
Short name T399
Test name
Test status
Simulation time 14424743830 ps
CPU time 45.44 seconds
Started Feb 08 06:32:39 PM UTC 25
Finished Feb 08 06:33:26 PM UTC 25
Peak memory 227392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985030218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1985030218
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3513398389
Short name T460
Test name
Test status
Simulation time 1003956881 ps
CPU time 11.83 seconds
Started Feb 08 06:32:38 PM UTC 25
Finished Feb 08 06:32:51 PM UTC 25
Peak memory 227332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513398389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3513398389
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.190647832
Short name T410
Test name
Test status
Simulation time 30128015 ps
CPU time 1.21 seconds
Started Feb 08 06:32:39 PM UTC 25
Finished Feb 08 06:32:41 PM UTC 25
Peak memory 215844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190647832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.190647832
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.4178518197
Short name T459
Test name
Test status
Simulation time 22665381 ps
CPU time 1.08 seconds
Started Feb 08 06:32:39 PM UTC 25
Finished Feb 08 06:32:41 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178518197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4178518197
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.3563884011
Short name T301
Test name
Test status
Simulation time 1073283617 ps
CPU time 7.87 seconds
Started Feb 08 06:32:47 PM UTC 25
Finished Feb 08 06:32:56 PM UTC 25
Peak memory 251352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563884011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3563884011
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.3072835654
Short name T473
Test name
Test status
Simulation time 15110675 ps
CPU time 1.13 seconds
Started Feb 08 06:33:11 PM UTC 25
Finished Feb 08 06:33:14 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072835654 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.3072835654
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2045886522
Short name T471
Test name
Test status
Simulation time 118833645 ps
CPU time 5.42 seconds
Started Feb 08 06:33:04 PM UTC 25
Finished Feb 08 06:33:10 PM UTC 25
Peak memory 245008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045886522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2045886522
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.1939704711
Short name T464
Test name
Test status
Simulation time 56544627 ps
CPU time 1.17 seconds
Started Feb 08 06:32:56 PM UTC 25
Finished Feb 08 06:32:58 PM UTC 25
Peak memory 215568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939704711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1939704711
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.3632050576
Short name T514
Test name
Test status
Simulation time 27903393464 ps
CPU time 86.38 seconds
Started Feb 08 06:33:08 PM UTC 25
Finished Feb 08 06:34:37 PM UTC 25
Peak memory 249328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632050576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3632050576
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.1091654354
Short name T293
Test name
Test status
Simulation time 8250950460 ps
CPU time 70.8 seconds
Started Feb 08 06:33:09 PM UTC 25
Finished Feb 08 06:34:22 PM UTC 25
Peak memory 263664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091654354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1091654354
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2432029049
Short name T640
Test name
Test status
Simulation time 17613678472 ps
CPU time 301.47 seconds
Started Feb 08 06:33:09 PM UTC 25
Finished Feb 08 06:38:15 PM UTC 25
Peak memory 278096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432029049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.2432029049
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.2520059672
Short name T470
Test name
Test status
Simulation time 78420610 ps
CPU time 5.02 seconds
Started Feb 08 06:33:04 PM UTC 25
Finished Feb 08 06:33:10 PM UTC 25
Peak memory 247072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520059672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2520059672
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.2247004278
Short name T205
Test name
Test status
Simulation time 2480126114 ps
CPU time 47.94 seconds
Started Feb 08 06:33:06 PM UTC 25
Finished Feb 08 06:33:56 PM UTC 25
Peak memory 249196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247004278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.2247004278
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2060952292
Short name T268
Test name
Test status
Simulation time 810403214 ps
CPU time 6.94 seconds
Started Feb 08 06:33:01 PM UTC 25
Finished Feb 08 06:33:09 PM UTC 25
Peak memory 245184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060952292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2060952292
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.1997620796
Short name T319
Test name
Test status
Simulation time 1297452382 ps
CPU time 29.76 seconds
Started Feb 08 06:33:03 PM UTC 25
Finished Feb 08 06:33:34 PM UTC 25
Peak memory 247416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997620796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1997620796
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.3956646146
Short name T467
Test name
Test status
Simulation time 14627093 ps
CPU time 1.55 seconds
Started Feb 08 06:32:57 PM UTC 25
Finished Feb 08 06:33:00 PM UTC 25
Peak memory 229252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956646146 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mem_parity.3956646146
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3115394019
Short name T344
Test name
Test status
Simulation time 3836902489 ps
CPU time 13.89 seconds
Started Feb 08 06:33:00 PM UTC 25
Finished Feb 08 06:33:15 PM UTC 25
Peak memory 235124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115394019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.3115394019
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1696157028
Short name T307
Test name
Test status
Simulation time 2622486023 ps
CPU time 24.42 seconds
Started Feb 08 06:33:00 PM UTC 25
Finished Feb 08 06:33:25 PM UTC 25
Peak memory 245156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696157028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1696157028
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.41842853
Short name T472
Test name
Test status
Simulation time 430583623 ps
CPU time 5.46 seconds
Started Feb 08 06:33:06 PM UTC 25
Finished Feb 08 06:33:13 PM UTC 25
Peak memory 231276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41842853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM
_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.41842853
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.3378886274
Short name T288
Test name
Test status
Simulation time 10137738660 ps
CPU time 125.28 seconds
Started Feb 08 06:33:11 PM UTC 25
Finished Feb 08 06:35:19 PM UTC 25
Peak memory 261680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378886274 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.3378886274
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.684200999
Short name T408
Test name
Test status
Simulation time 4408023115 ps
CPU time 39.24 seconds
Started Feb 08 06:32:59 PM UTC 25
Finished Feb 08 06:33:40 PM UTC 25
Peak memory 227388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684200999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.684200999
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.2173593030
Short name T469
Test name
Test status
Simulation time 2790972092 ps
CPU time 6.89 seconds
Started Feb 08 06:32:57 PM UTC 25
Finished Feb 08 06:33:05 PM UTC 25
Peak memory 227756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173593030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2173593030
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.825643463
Short name T412
Test name
Test status
Simulation time 132465127 ps
CPU time 2.28 seconds
Started Feb 08 06:32:59 PM UTC 25
Finished Feb 08 06:33:03 PM UTC 25
Peak memory 227336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825643463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.825643463
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2386443957
Short name T468
Test name
Test status
Simulation time 43925676 ps
CPU time 1.3 seconds
Started Feb 08 06:32:59 PM UTC 25
Finished Feb 08 06:33:02 PM UTC 25
Peak memory 215684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386443957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2386443957
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.118988812
Short name T274
Test name
Test status
Simulation time 16882001055 ps
CPU time 26.2 seconds
Started Feb 08 06:33:03 PM UTC 25
Finished Feb 08 06:33:30 PM UTC 25
Peak memory 245400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118988812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.118988812
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.2098527206
Short name T479
Test name
Test status
Simulation time 47085093 ps
CPU time 1.09 seconds
Started Feb 08 06:33:32 PM UTC 25
Finished Feb 08 06:33:34 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098527206 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.2098527206
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.3180399757
Short name T481
Test name
Test status
Simulation time 3323924372 ps
CPU time 8.88 seconds
Started Feb 08 06:33:26 PM UTC 25
Finished Feb 08 06:33:36 PM UTC 25
Peak memory 234912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180399757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3180399757
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.3571655837
Short name T474
Test name
Test status
Simulation time 16817888 ps
CPU time 1.18 seconds
Started Feb 08 06:33:12 PM UTC 25
Finished Feb 08 06:33:15 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571655837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3571655837
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.2709642080
Short name T539
Test name
Test status
Simulation time 23993929876 ps
CPU time 107.8 seconds
Started Feb 08 06:33:29 PM UTC 25
Finished Feb 08 06:35:19 PM UTC 25
Peak memory 245236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709642080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2709642080
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.677411715
Short name T202
Test name
Test status
Simulation time 2353932063 ps
CPU time 69.3 seconds
Started Feb 08 06:33:30 PM UTC 25
Finished Feb 08 06:34:42 PM UTC 25
Peak memory 267848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677411715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.677411715
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.4069156540
Short name T488
Test name
Test status
Simulation time 673776412 ps
CPU time 15.54 seconds
Started Feb 08 06:33:26 PM UTC 25
Finished Feb 08 06:33:43 PM UTC 25
Peak memory 247236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069156540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4069156540
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2071540058
Short name T297
Test name
Test status
Simulation time 9512169439 ps
CPU time 41.2 seconds
Started Feb 08 06:33:27 PM UTC 25
Finished Feb 08 06:34:10 PM UTC 25
Peak memory 261624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071540058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.2071540058
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.3632632940
Short name T230
Test name
Test status
Simulation time 524490709 ps
CPU time 7.26 seconds
Started Feb 08 06:33:19 PM UTC 25
Finished Feb 08 06:33:27 PM UTC 25
Peak memory 235168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632632940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3632632940
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.3903605264
Short name T276
Test name
Test status
Simulation time 1449575898 ps
CPU time 32.2 seconds
Started Feb 08 06:33:25 PM UTC 25
Finished Feb 08 06:33:59 PM UTC 25
Peak memory 245396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903605264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3903605264
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.442178228
Short name T475
Test name
Test status
Simulation time 126251520 ps
CPU time 1.49 seconds
Started Feb 08 06:33:13 PM UTC 25
Finished Feb 08 06:33:16 PM UTC 25
Peak memory 228916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442178228 -assert nopostproc
+UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mem_parity.442178228
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.982742173
Short name T478
Test name
Test status
Simulation time 387166150 ps
CPU time 4.18 seconds
Started Feb 08 06:33:19 PM UTC 25
Finished Feb 08 06:33:24 PM UTC 25
Peak memory 245140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982742173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.982742173
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.840562465
Short name T327
Test name
Test status
Simulation time 707306372 ps
CPU time 11.13 seconds
Started Feb 08 06:33:17 PM UTC 25
Finished Feb 08 06:33:29 PM UTC 25
Peak memory 234964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840562465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.840562465
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1342930644
Short name T487
Test name
Test status
Simulation time 742764543 ps
CPU time 10.38 seconds
Started Feb 08 06:33:28 PM UTC 25
Finished Feb 08 06:33:40 PM UTC 25
Peak memory 233332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342930644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.1342930644
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.4071499003
Short name T44
Test name
Test status
Simulation time 146937045571 ps
CPU time 343.82 seconds
Started Feb 08 06:33:32 PM UTC 25
Finished Feb 08 06:39:20 PM UTC 25
Peak memory 261684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071499003 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.4071499003
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.757884679
Short name T407
Test name
Test status
Simulation time 5306997939 ps
CPU time 22.01 seconds
Started Feb 08 06:33:15 PM UTC 25
Finished Feb 08 06:33:38 PM UTC 25
Peak memory 227580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757884679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.757884679
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.934711598
Short name T485
Test name
Test status
Simulation time 4885291309 ps
CPU time 23.8 seconds
Started Feb 08 06:33:14 PM UTC 25
Finished Feb 08 06:33:39 PM UTC 25
Peak memory 227200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934711598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.934711598
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.3278544674
Short name T477
Test name
Test status
Simulation time 53664748 ps
CPU time 1.26 seconds
Started Feb 08 06:33:16 PM UTC 25
Finished Feb 08 06:33:18 PM UTC 25
Peak memory 215216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278544674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3278544674
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.4051175717
Short name T476
Test name
Test status
Simulation time 80949344 ps
CPU time 1.28 seconds
Started Feb 08 06:33:16 PM UTC 25
Finished Feb 08 06:33:18 PM UTC 25
Peak memory 215136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051175717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4051175717
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.4005726975
Short name T345
Test name
Test status
Simulation time 845171237 ps
CPU time 4.82 seconds
Started Feb 08 06:33:25 PM UTC 25
Finished Feb 08 06:33:31 PM UTC 25
Peak memory 234968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005726975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4005726975
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.127806188
Short name T491
Test name
Test status
Simulation time 114946056 ps
CPU time 1.09 seconds
Started Feb 08 06:33:48 PM UTC 25
Finished Feb 08 06:33:50 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127806188 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.127806188
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3113917373
Short name T316
Test name
Test status
Simulation time 396156908 ps
CPU time 3.31 seconds
Started Feb 08 06:33:40 PM UTC 25
Finished Feb 08 06:33:45 PM UTC 25
Peak memory 234848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113917373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3113917373
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.4231959852
Short name T480
Test name
Test status
Simulation time 36812300 ps
CPU time 1.2 seconds
Started Feb 08 06:33:33 PM UTC 25
Finished Feb 08 06:33:35 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231959852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4231959852
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.3124378150
Short name T555
Test name
Test status
Simulation time 11848709393 ps
CPU time 120.81 seconds
Started Feb 08 06:33:44 PM UTC 25
Finished Feb 08 06:35:47 PM UTC 25
Peak memory 261652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124378150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3124378150
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.3101142184
Short name T581
Test name
Test status
Simulation time 27513861781 ps
CPU time 170.45 seconds
Started Feb 08 06:33:45 PM UTC 25
Finished Feb 08 06:36:38 PM UTC 25
Peak memory 265772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101142184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3101142184
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.3252089406
Short name T490
Test name
Test status
Simulation time 407670952 ps
CPU time 6.18 seconds
Started Feb 08 06:33:41 PM UTC 25
Finished Feb 08 06:33:49 PM UTC 25
Peak memory 245008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252089406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3252089406
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.1935834184
Short name T498
Test name
Test status
Simulation time 3215807561 ps
CPU time 20.1 seconds
Started Feb 08 06:33:41 PM UTC 25
Finished Feb 08 06:34:03 PM UTC 25
Peak memory 247156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935834184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.1935834184
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.3706850220
Short name T347
Test name
Test status
Simulation time 1307880813 ps
CPU time 7.4 seconds
Started Feb 08 06:33:39 PM UTC 25
Finished Feb 08 06:33:48 PM UTC 25
Peak memory 245176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706850220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3706850220
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.4182101639
Short name T322
Test name
Test status
Simulation time 1983412767 ps
CPU time 29.35 seconds
Started Feb 08 06:33:39 PM UTC 25
Finished Feb 08 06:34:10 PM UTC 25
Peak memory 234420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182101639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4182101639
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.1790411472
Short name T482
Test name
Test status
Simulation time 34309927 ps
CPU time 1.64 seconds
Started Feb 08 06:33:35 PM UTC 25
Finished Feb 08 06:33:37 PM UTC 25
Peak memory 229252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790411472 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mem_parity.1790411472
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.1137400656
Short name T236
Test name
Test status
Simulation time 829822569 ps
CPU time 4.63 seconds
Started Feb 08 06:33:39 PM UTC 25
Finished Feb 08 06:33:45 PM UTC 25
Peak memory 235132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137400656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.1137400656
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.910718244
Short name T326
Test name
Test status
Simulation time 5686866928 ps
CPU time 21.98 seconds
Started Feb 08 06:33:38 PM UTC 25
Finished Feb 08 06:34:01 PM UTC 25
Peak memory 245272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910718244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.910718244
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3875060343
Short name T492
Test name
Test status
Simulation time 129567415 ps
CPU time 5.69 seconds
Started Feb 08 06:33:44 PM UTC 25
Finished Feb 08 06:33:50 PM UTC 25
Peak memory 233796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875060343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.3875060343
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.1508296538
Short name T199
Test name
Test status
Simulation time 6810368550 ps
CPU time 88 seconds
Started Feb 08 06:33:46 PM UTC 25
Finished Feb 08 06:35:16 PM UTC 25
Peak memory 261716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508296538 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.1508296538
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.393479538
Short name T483
Test name
Test status
Simulation time 25063160 ps
CPU time 1.13 seconds
Started Feb 08 06:33:36 PM UTC 25
Finished Feb 08 06:33:38 PM UTC 25
Peak memory 215772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393479538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.393479538
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.4171153543
Short name T489
Test name
Test status
Simulation time 5333097918 ps
CPU time 10.72 seconds
Started Feb 08 06:33:35 PM UTC 25
Finished Feb 08 06:33:47 PM UTC 25
Peak memory 227700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171153543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4171153543
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3979034462
Short name T486
Test name
Test status
Simulation time 16146200 ps
CPU time 1.3 seconds
Started Feb 08 06:33:37 PM UTC 25
Finished Feb 08 06:33:39 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979034462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3979034462
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2703204975
Short name T484
Test name
Test status
Simulation time 164744154 ps
CPU time 1.18 seconds
Started Feb 08 06:33:36 PM UTC 25
Finished Feb 08 06:33:38 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703204975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2703204975
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.3853264873
Short name T356
Test name
Test status
Simulation time 449551950 ps
CPU time 3.1 seconds
Started Feb 08 06:33:39 PM UTC 25
Finished Feb 08 06:33:44 PM UTC 25
Peak memory 245128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853264873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3853264873
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.2334520469
Short name T499
Test name
Test status
Simulation time 31289278 ps
CPU time 1.14 seconds
Started Feb 08 06:34:04 PM UTC 25
Finished Feb 08 06:34:06 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334520469 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.2334520469
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2991340178
Short name T497
Test name
Test status
Simulation time 62826207 ps
CPU time 3.37 seconds
Started Feb 08 06:33:58 PM UTC 25
Finished Feb 08 06:34:02 PM UTC 25
Peak memory 244824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991340178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2991340178
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.4268390082
Short name T493
Test name
Test status
Simulation time 23004984 ps
CPU time 1.18 seconds
Started Feb 08 06:33:49 PM UTC 25
Finished Feb 08 06:33:51 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268390082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4268390082
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.435176558
Short name T287
Test name
Test status
Simulation time 3782767571 ps
CPU time 38.14 seconds
Started Feb 08 06:34:03 PM UTC 25
Finished Feb 08 06:34:43 PM UTC 25
Peak memory 247416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435176558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.435176558
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.557896103
Short name T554
Test name
Test status
Simulation time 7652487950 ps
CPU time 99 seconds
Started Feb 08 06:34:03 PM UTC 25
Finished Feb 08 06:35:44 PM UTC 25
Peak memory 261956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557896103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.557896103
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.580723728
Short name T586
Test name
Test status
Simulation time 27328339281 ps
CPU time 164.5 seconds
Started Feb 08 06:34:03 PM UTC 25
Finished Feb 08 06:36:50 PM UTC 25
Peak memory 261940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580723728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.580723728
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.1950068570
Short name T396
Test name
Test status
Simulation time 864206617 ps
CPU time 17.98 seconds
Started Feb 08 06:34:00 PM UTC 25
Finished Feb 08 06:34:19 PM UTC 25
Peak memory 234916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950068570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1950068570
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.10991187
Short name T500
Test name
Test status
Simulation time 582357257 ps
CPU time 8.11 seconds
Started Feb 08 06:34:00 PM UTC 25
Finished Feb 08 06:34:09 PM UTC 25
Peak memory 245272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10991187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.10991187
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.1912399657
Short name T325
Test name
Test status
Simulation time 308916572 ps
CPU time 5.98 seconds
Started Feb 08 06:33:54 PM UTC 25
Finished Feb 08 06:34:01 PM UTC 25
Peak memory 245276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912399657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1912399657
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.2116700490
Short name T291
Test name
Test status
Simulation time 3073259894 ps
CPU time 17.97 seconds
Started Feb 08 06:33:56 PM UTC 25
Finished Feb 08 06:34:16 PM UTC 25
Peak memory 245228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116700490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2116700490
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.646386731
Short name T494
Test name
Test status
Simulation time 105259383 ps
CPU time 1.53 seconds
Started Feb 08 06:33:50 PM UTC 25
Finished Feb 08 06:33:53 PM UTC 25
Peak memory 229188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646386731 -assert nopostproc
+UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.646386731
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2708071210
Short name T346
Test name
Test status
Simulation time 24421218015 ps
CPU time 20.5 seconds
Started Feb 08 06:33:53 PM UTC 25
Finished Feb 08 06:34:15 PM UTC 25
Peak memory 234940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708071210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.2708071210
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.17086958
Short name T83
Test name
Test status
Simulation time 25355964268 ps
CPU time 33.63 seconds
Started Feb 08 06:33:52 PM UTC 25
Finished Feb 08 06:34:27 PM UTC 25
Peak memory 261652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17086958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.17086958
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.2461718200
Short name T508
Test name
Test status
Simulation time 6956171287 ps
CPU time 14.88 seconds
Started Feb 08 06:34:02 PM UTC 25
Finished Feb 08 06:34:18 PM UTC 25
Peak memory 231256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461718200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.2461718200
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.1316958552
Short name T185
Test name
Test status
Simulation time 52154820871 ps
CPU time 173.22 seconds
Started Feb 08 06:34:03 PM UTC 25
Finished Feb 08 06:36:59 PM UTC 25
Peak memory 268108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316958552 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.1316958552
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.2295269634
Short name T409
Test name
Test status
Simulation time 7692998702 ps
CPU time 41.6 seconds
Started Feb 08 06:33:51 PM UTC 25
Finished Feb 08 06:34:34 PM UTC 25
Peak memory 227448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295269634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2295269634
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2743049024
Short name T503
Test name
Test status
Simulation time 7361097712 ps
CPU time 19.88 seconds
Started Feb 08 06:33:51 PM UTC 25
Finished Feb 08 06:34:12 PM UTC 25
Peak memory 227440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743049024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2743049024
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.3101099216
Short name T496
Test name
Test status
Simulation time 254054088 ps
CPU time 2.81 seconds
Started Feb 08 06:33:52 PM UTC 25
Finished Feb 08 06:33:56 PM UTC 25
Peak memory 227612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101099216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3101099216
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3079619259
Short name T495
Test name
Test status
Simulation time 65059835 ps
CPU time 1.46 seconds
Started Feb 08 06:33:51 PM UTC 25
Finished Feb 08 06:33:54 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079619259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3079619259
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.1474531107
Short name T250
Test name
Test status
Simulation time 5201409010 ps
CPU time 20.84 seconds
Started Feb 08 06:33:58 PM UTC 25
Finished Feb 08 06:34:20 PM UTC 25
Peak memory 261780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474531107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1474531107
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.453796424
Short name T510
Test name
Test status
Simulation time 25684959 ps
CPU time 1.12 seconds
Started Feb 08 06:34:21 PM UTC 25
Finished Feb 08 06:34:24 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453796424 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.453796424
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.175090361
Short name T88
Test name
Test status
Simulation time 1316961075 ps
CPU time 14.38 seconds
Started Feb 08 06:34:16 PM UTC 25
Finished Feb 08 06:34:32 PM UTC 25
Peak memory 235192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175090361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.175090361
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.2863261766
Short name T501
Test name
Test status
Simulation time 14339013 ps
CPU time 1.18 seconds
Started Feb 08 06:34:07 PM UTC 25
Finished Feb 08 06:34:09 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863261766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2863261766
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3327373795
Short name T289
Test name
Test status
Simulation time 3806878747 ps
CPU time 33.94 seconds
Started Feb 08 06:34:19 PM UTC 25
Finished Feb 08 06:34:55 PM UTC 25
Peak memory 261884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327373795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3327373795
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2944770981
Short name T523
Test name
Test status
Simulation time 14241443322 ps
CPU time 22.78 seconds
Started Feb 08 06:34:19 PM UTC 25
Finished Feb 08 06:34:43 PM UTC 25
Peak memory 235060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944770981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2944770981
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.326071460
Short name T81
Test name
Test status
Simulation time 485748682 ps
CPU time 8.88 seconds
Started Feb 08 06:34:16 PM UTC 25
Finished Feb 08 06:34:26 PM UTC 25
Peak memory 245456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326071460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.326071460
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.515902745
Short name T580
Test name
Test status
Simulation time 73320051632 ps
CPU time 135.95 seconds
Started Feb 08 06:34:17 PM UTC 25
Finished Feb 08 06:36:35 PM UTC 25
Peak memory 267764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515902745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.515902745
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.3320222407
Short name T114
Test name
Test status
Simulation time 690388010 ps
CPU time 8.22 seconds
Started Feb 08 06:34:13 PM UTC 25
Finished Feb 08 06:34:22 PM UTC 25
Peak memory 234964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320222407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3320222407
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.1404817755
Short name T360
Test name
Test status
Simulation time 5062616879 ps
CPU time 47.53 seconds
Started Feb 08 06:34:14 PM UTC 25
Finished Feb 08 06:35:03 PM UTC 25
Peak memory 235188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404817755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1404817755
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.1820024094
Short name T502
Test name
Test status
Simulation time 66514829 ps
CPU time 1.6 seconds
Started Feb 08 06:34:09 PM UTC 25
Finished Feb 08 06:34:12 PM UTC 25
Peak memory 229252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820024094 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.1820024094
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.2911414374
Short name T507
Test name
Test status
Simulation time 65170591 ps
CPU time 3.11 seconds
Started Feb 08 06:34:13 PM UTC 25
Finished Feb 08 06:34:17 PM UTC 25
Peak memory 244888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911414374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.2911414374
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.1209976250
Short name T357
Test name
Test status
Simulation time 3283937502 ps
CPU time 4.75 seconds
Started Feb 08 06:34:12 PM UTC 25
Finished Feb 08 06:34:17 PM UTC 25
Peak memory 245236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209976250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1209976250
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.1672722106
Short name T82
Test name
Test status
Simulation time 1064675064 ps
CPU time 6.91 seconds
Started Feb 08 06:34:18 PM UTC 25
Finished Feb 08 06:34:26 PM UTC 25
Peak memory 233332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672722106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.1672722106
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.3440241254
Short name T339
Test name
Test status
Simulation time 249888308675 ps
CPU time 539.16 seconds
Started Feb 08 06:34:20 PM UTC 25
Finished Feb 08 06:43:26 PM UTC 25
Peak memory 284200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440241254 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.3440241254
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.2734731099
Short name T529
Test name
Test status
Simulation time 11193386549 ps
CPU time 44.23 seconds
Started Feb 08 06:34:10 PM UTC 25
Finished Feb 08 06:34:56 PM UTC 25
Peak memory 227416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734731099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2734731099
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3128624665
Short name T509
Test name
Test status
Simulation time 2457408750 ps
CPU time 11.36 seconds
Started Feb 08 06:34:09 PM UTC 25
Finished Feb 08 06:34:22 PM UTC 25
Peak memory 227480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128624665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3128624665
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.603841698
Short name T506
Test name
Test status
Simulation time 127680079 ps
CPU time 2.06 seconds
Started Feb 08 06:34:11 PM UTC 25
Finished Feb 08 06:34:15 PM UTC 25
Peak memory 227680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603841698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.603841698
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3904521654
Short name T504
Test name
Test status
Simulation time 68345390 ps
CPU time 1.41 seconds
Started Feb 08 06:34:10 PM UTC 25
Finished Feb 08 06:34:13 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904521654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3904521654
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.1585249853
Short name T512
Test name
Test status
Simulation time 13973962299 ps
CPU time 16.08 seconds
Started Feb 08 06:34:15 PM UTC 25
Finished Feb 08 06:34:32 PM UTC 25
Peak memory 251576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585249853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1585249853
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.2733013197
Short name T516
Test name
Test status
Simulation time 51558857 ps
CPU time 1.11 seconds
Started Feb 08 06:34:36 PM UTC 25
Finished Feb 08 06:34:38 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733013197 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.2733013197
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.1006117015
Short name T320
Test name
Test status
Simulation time 127954233 ps
CPU time 5.31 seconds
Started Feb 08 06:34:29 PM UTC 25
Finished Feb 08 06:34:36 PM UTC 25
Peak memory 245144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006117015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1006117015
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.4215729649
Short name T511
Test name
Test status
Simulation time 53917806 ps
CPU time 1.16 seconds
Started Feb 08 06:34:22 PM UTC 25
Finished Feb 08 06:34:25 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215729649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4215729649
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.102301599
Short name T378
Test name
Test status
Simulation time 376830664509 ps
CPU time 460.92 seconds
Started Feb 08 06:34:33 PM UTC 25
Finished Feb 08 06:42:20 PM UTC 25
Peak memory 267772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102301599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.102301599
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3505570470
Short name T270
Test name
Test status
Simulation time 52521321653 ps
CPU time 160.19 seconds
Started Feb 08 06:34:35 PM UTC 25
Finished Feb 08 06:37:18 PM UTC 25
Peak memory 261588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505570470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3505570470
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.1771572811
Short name T515
Test name
Test status
Simulation time 284486403 ps
CPU time 5.64 seconds
Started Feb 08 06:34:30 PM UTC 25
Finished Feb 08 06:34:37 PM UTC 25
Peak memory 245164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771572811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1771572811
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.2665590253
Short name T231
Test name
Test status
Simulation time 150947000 ps
CPU time 5.57 seconds
Started Feb 08 06:34:27 PM UTC 25
Finished Feb 08 06:34:34 PM UTC 25
Peak memory 235004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665590253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2665590253
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.3896214334
Short name T348
Test name
Test status
Simulation time 49002365183 ps
CPU time 54.89 seconds
Started Feb 08 06:34:28 PM UTC 25
Finished Feb 08 06:35:25 PM UTC 25
Peak memory 251344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896214334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3896214334
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.4270666927
Short name T80
Test name
Test status
Simulation time 33195261 ps
CPU time 1.59 seconds
Started Feb 08 06:34:23 PM UTC 25
Finished Feb 08 06:34:25 PM UTC 25
Peak memory 229192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270666927 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.4270666927
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1482338319
Short name T333
Test name
Test status
Simulation time 4421237414 ps
CPU time 30.15 seconds
Started Feb 08 06:34:27 PM UTC 25
Finished Feb 08 06:34:58 PM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482338319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.1482338319
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.2072625638
Short name T87
Test name
Test status
Simulation time 51852065 ps
CPU time 2.52 seconds
Started Feb 08 06:34:26 PM UTC 25
Finished Feb 08 06:34:29 PM UTC 25
Peak memory 234208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072625638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2072625638
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.208389370
Short name T519
Test name
Test status
Simulation time 597527037 ps
CPU time 7.58 seconds
Started Feb 08 06:34:32 PM UTC 25
Finished Feb 08 06:34:41 PM UTC 25
Peak memory 233364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208389370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.208389370
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.3342065622
Short name T513
Test name
Test status
Simulation time 2011685513 ps
CPU time 8.99 seconds
Started Feb 08 06:34:25 PM UTC 25
Finished Feb 08 06:34:35 PM UTC 25
Peak memory 231736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342065622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3342065622
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3098184200
Short name T86
Test name
Test status
Simulation time 533067887 ps
CPU time 5.38 seconds
Started Feb 08 06:34:23 PM UTC 25
Finished Feb 08 06:34:29 PM UTC 25
Peak memory 227532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098184200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3098184200
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.3820572743
Short name T85
Test name
Test status
Simulation time 221683703 ps
CPU time 1.89 seconds
Started Feb 08 06:34:26 PM UTC 25
Finished Feb 08 06:34:29 PM UTC 25
Peak memory 226232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820572743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3820572743
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.270570992
Short name T84
Test name
Test status
Simulation time 146200162 ps
CPU time 1.09 seconds
Started Feb 08 06:34:26 PM UTC 25
Finished Feb 08 06:34:28 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270570992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.270570992
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.3960787430
Short name T318
Test name
Test status
Simulation time 267673595 ps
CPU time 7.38 seconds
Started Feb 08 06:34:29 PM UTC 25
Finished Feb 08 06:34:38 PM UTC 25
Peak memory 234896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960787430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3960787430
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.4233015056
Short name T530
Test name
Test status
Simulation time 12732789 ps
CPU time 1.1 seconds
Started Feb 08 06:34:56 PM UTC 25
Finished Feb 08 06:34:58 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233015056 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.4233015056
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.931404124
Short name T354
Test name
Test status
Simulation time 998065817 ps
CPU time 13.84 seconds
Started Feb 08 06:34:43 PM UTC 25
Finished Feb 08 06:34:59 PM UTC 25
Peak memory 234868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931404124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.931404124
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.520479950
Short name T517
Test name
Test status
Simulation time 76952855 ps
CPU time 1.22 seconds
Started Feb 08 06:34:37 PM UTC 25
Finished Feb 08 06:34:39 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520479950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.520479950
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.2655448385
Short name T684
Test name
Test status
Simulation time 139440093972 ps
CPU time 259.4 seconds
Started Feb 08 06:34:47 PM UTC 25
Finished Feb 08 06:39:10 PM UTC 25
Peak memory 261648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655448385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2655448385
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2113076634
Short name T309
Test name
Test status
Simulation time 6944718962 ps
CPU time 48.24 seconds
Started Feb 08 06:34:47 PM UTC 25
Finished Feb 08 06:35:37 PM UTC 25
Peak memory 263756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113076634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2113076634
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.3517807383
Short name T537
Test name
Test status
Simulation time 1810006797 ps
CPU time 17.06 seconds
Started Feb 08 06:34:51 PM UTC 25
Finished Feb 08 06:35:10 PM UTC 25
Peak memory 229784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517807383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.3517807383
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.1184136076
Short name T535
Test name
Test status
Simulation time 738468347 ps
CPU time 19.8 seconds
Started Feb 08 06:34:44 PM UTC 25
Finished Feb 08 06:35:05 PM UTC 25
Peak memory 251336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184136076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1184136076
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.1627128194
Short name T743
Test name
Test status
Simulation time 72735179340 ps
CPU time 342.09 seconds
Started Feb 08 06:34:45 PM UTC 25
Finished Feb 08 06:40:32 PM UTC 25
Peak memory 268052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627128194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.1627128194
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.3105474724
Short name T527
Test name
Test status
Simulation time 176185452 ps
CPU time 7.01 seconds
Started Feb 08 06:34:42 PM UTC 25
Finished Feb 08 06:34:51 PM UTC 25
Peak memory 234876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105474724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3105474724
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.662939336
Short name T161
Test name
Test status
Simulation time 8261991367 ps
CPU time 99.65 seconds
Started Feb 08 06:34:42 PM UTC 25
Finished Feb 08 06:36:24 PM UTC 25
Peak memory 261592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662939336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.662939336
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.2263868825
Short name T518
Test name
Test status
Simulation time 17495920 ps
CPU time 1.48 seconds
Started Feb 08 06:34:38 PM UTC 25
Finished Feb 08 06:34:41 PM UTC 25
Peak memory 229196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263868825 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mem_parity.2263868825
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.1275353993
Short name T285
Test name
Test status
Simulation time 9955140778 ps
CPU time 16.49 seconds
Started Feb 08 06:34:42 PM UTC 25
Finished Feb 08 06:35:00 PM UTC 25
Peak memory 235192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275353993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.1275353993
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2760594443
Short name T524
Test name
Test status
Simulation time 33860186 ps
CPU time 3.26 seconds
Started Feb 08 06:34:41 PM UTC 25
Finished Feb 08 06:34:46 PM UTC 25
Peak memory 244852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760594443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2760594443
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.2259260652
Short name T528
Test name
Test status
Simulation time 522052150 ps
CPU time 7.63 seconds
Started Feb 08 06:34:47 PM UTC 25
Finished Feb 08 06:34:55 PM UTC 25
Peak memory 233332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259260652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.2259260652
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.488917507
Short name T819
Test name
Test status
Simulation time 44484753533 ps
CPU time 440.35 seconds
Started Feb 08 06:34:52 PM UTC 25
Finished Feb 08 06:42:18 PM UTC 25
Peak memory 284216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488917507 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.488917507
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.777268621
Short name T526
Test name
Test status
Simulation time 616501554 ps
CPU time 9.44 seconds
Started Feb 08 06:34:39 PM UTC 25
Finished Feb 08 06:34:50 PM UTC 25
Peak memory 229140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777268621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.777268621
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3762531786
Short name T522
Test name
Test status
Simulation time 577696827 ps
CPU time 3.89 seconds
Started Feb 08 06:34:38 PM UTC 25
Finished Feb 08 06:34:43 PM UTC 25
Peak memory 216784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762531786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3762531786
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.2153499308
Short name T525
Test name
Test status
Simulation time 209907254 ps
CPU time 4.71 seconds
Started Feb 08 06:34:40 PM UTC 25
Finished Feb 08 06:34:46 PM UTC 25
Peak memory 227644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153499308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2153499308
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3139688208
Short name T521
Test name
Test status
Simulation time 108512145 ps
CPU time 1.28 seconds
Started Feb 08 06:34:39 PM UTC 25
Finished Feb 08 06:34:41 PM UTC 25
Peak memory 215676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139688208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3139688208
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.2332028783
Short name T246
Test name
Test status
Simulation time 9500666669 ps
CPU time 12.05 seconds
Started Feb 08 06:34:42 PM UTC 25
Finished Feb 08 06:34:56 PM UTC 25
Peak memory 245236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332028783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2332028783
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.251045558
Short name T540
Test name
Test status
Simulation time 15099182 ps
CPU time 1.13 seconds
Started Feb 08 06:35:18 PM UTC 25
Finished Feb 08 06:35:20 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251045558 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.251045558
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.2677473102
Short name T308
Test name
Test status
Simulation time 214957482 ps
CPU time 4.03 seconds
Started Feb 08 06:35:04 PM UTC 25
Finished Feb 08 06:35:09 PM UTC 25
Peak memory 234964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677473102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2677473102
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.1526789430
Short name T531
Test name
Test status
Simulation time 15987823 ps
CPU time 1.2 seconds
Started Feb 08 06:34:56 PM UTC 25
Finished Feb 08 06:34:59 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526789430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1526789430
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.1341570302
Short name T294
Test name
Test status
Simulation time 4118443479 ps
CPU time 94.61 seconds
Started Feb 08 06:35:11 PM UTC 25
Finished Feb 08 06:36:48 PM UTC 25
Peak memory 278164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341570302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1341570302
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2849436571
Short name T384
Test name
Test status
Simulation time 54375911364 ps
CPU time 349.11 seconds
Started Feb 08 06:35:17 PM UTC 25
Finished Feb 08 06:41:11 PM UTC 25
Peak memory 267828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849436571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.2849436571
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.2163272701
Short name T551
Test name
Test status
Simulation time 2472069106 ps
CPU time 36.04 seconds
Started Feb 08 06:35:06 PM UTC 25
Finished Feb 08 06:35:43 PM UTC 25
Peak memory 251192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163272701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2163272701
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1190434299
Short name T336
Test name
Test status
Simulation time 228198344990 ps
CPU time 406.54 seconds
Started Feb 08 06:35:06 PM UTC 25
Finished Feb 08 06:41:57 PM UTC 25
Peak memory 278292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190434299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.1190434299
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.3775740391
Short name T313
Test name
Test status
Simulation time 358020991 ps
CPU time 8.83 seconds
Started Feb 08 06:35:01 PM UTC 25
Finished Feb 08 06:35:12 PM UTC 25
Peak memory 235004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775740391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3775740391
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.2794003248
Short name T567
Test name
Test status
Simulation time 6448541657 ps
CPU time 62.01 seconds
Started Feb 08 06:35:03 PM UTC 25
Finished Feb 08 06:36:06 PM UTC 25
Peak memory 241792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794003248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2794003248
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.2517125671
Short name T532
Test name
Test status
Simulation time 69245918 ps
CPU time 1.37 seconds
Started Feb 08 06:34:57 PM UTC 25
Finished Feb 08 06:35:00 PM UTC 25
Peak memory 229192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517125671 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mem_parity.2517125671
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.2879731705
Short name T536
Test name
Test status
Simulation time 475853887 ps
CPU time 3.75 seconds
Started Feb 08 06:35:00 PM UTC 25
Finished Feb 08 06:35:05 PM UTC 25
Peak memory 235188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879731705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.2879731705
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1672308458
Short name T257
Test name
Test status
Simulation time 6016949307 ps
CPU time 15.07 seconds
Started Feb 08 06:35:00 PM UTC 25
Finished Feb 08 06:35:17 PM UTC 25
Peak memory 234940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672308458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1672308458
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2425284282
Short name T546
Test name
Test status
Simulation time 1665930161 ps
CPU time 17.02 seconds
Started Feb 08 06:35:10 PM UTC 25
Finished Feb 08 06:35:29 PM UTC 25
Peak memory 231192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425284282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.2425284282
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.207028577
Short name T541
Test name
Test status
Simulation time 111074561 ps
CPU time 1.46 seconds
Started Feb 08 06:35:18 PM UTC 25
Finished Feb 08 06:35:21 PM UTC 25
Peak memory 215868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207028577 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.207028577
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.1809558662
Short name T538
Test name
Test status
Simulation time 16490882465 ps
CPU time 16.91 seconds
Started Feb 08 06:34:59 PM UTC 25
Finished Feb 08 06:35:17 PM UTC 25
Peak memory 227648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809558662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1809558662
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.4240421278
Short name T544
Test name
Test status
Simulation time 19837699161 ps
CPU time 25.52 seconds
Started Feb 08 06:34:57 PM UTC 25
Finished Feb 08 06:35:24 PM UTC 25
Peak memory 227444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240421278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4240421278
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.1383176174
Short name T534
Test name
Test status
Simulation time 124355778 ps
CPU time 2.43 seconds
Started Feb 08 06:34:59 PM UTC 25
Finished Feb 08 06:35:03 PM UTC 25
Peak memory 227448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383176174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1383176174
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.941662603
Short name T533
Test name
Test status
Simulation time 145791945 ps
CPU time 1.33 seconds
Started Feb 08 06:34:59 PM UTC 25
Finished Feb 08 06:35:02 PM UTC 25
Peak memory 215840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941662603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.941662603
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.302080852
Short name T547
Test name
Test status
Simulation time 24924955383 ps
CPU time 30.47 seconds
Started Feb 08 06:35:04 PM UTC 25
Finished Feb 08 06:35:36 PM UTC 25
Peak memory 245220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302080852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.302080852
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.2495916703
Short name T98
Test name
Test status
Simulation time 22036191 ps
CPU time 1.06 seconds
Started Feb 08 06:30:10 PM UTC 25
Finished Feb 08 06:30:12 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495916703 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2495916703
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3615862338
Short name T60
Test name
Test status
Simulation time 746310646 ps
CPU time 6.12 seconds
Started Feb 08 06:30:03 PM UTC 25
Finished Feb 08 06:30:10 PM UTC 25
Peak memory 245140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615862338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3615862338
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2428647605
Short name T20
Test name
Test status
Simulation time 21937282 ps
CPU time 1.27 seconds
Started Feb 08 06:29:56 PM UTC 25
Finished Feb 08 06:29:58 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428647605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2428647605
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.2485159227
Short name T66
Test name
Test status
Simulation time 2337026578 ps
CPU time 29.53 seconds
Started Feb 08 06:30:06 PM UTC 25
Finished Feb 08 06:30:37 PM UTC 25
Peak memory 249628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485159227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2485159227
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2230037399
Short name T206
Test name
Test status
Simulation time 14196032475 ps
CPU time 159.95 seconds
Started Feb 08 06:30:06 PM UTC 25
Finished Feb 08 06:32:48 PM UTC 25
Peak memory 265752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230037399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2230037399
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1408536115
Short name T34
Test name
Test status
Simulation time 5035896750 ps
CPU time 7.82 seconds
Started Feb 08 06:30:06 PM UTC 25
Finished Feb 08 06:30:15 PM UTC 25
Peak memory 235040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408536115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.1408536115
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1278083541
Short name T50
Test name
Test status
Simulation time 32146732539 ps
CPU time 29.89 seconds
Started Feb 08 06:30:05 PM UTC 25
Finished Feb 08 06:30:36 PM UTC 25
Peak memory 247228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278083541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.1278083541
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.438883913
Short name T56
Test name
Test status
Simulation time 490309396 ps
CPU time 5.17 seconds
Started Feb 08 06:30:00 PM UTC 25
Finished Feb 08 06:30:07 PM UTC 25
Peak memory 245148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438883913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.438883913
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1516975317
Short name T93
Test name
Test status
Simulation time 487970047 ps
CPU time 14.07 seconds
Started Feb 08 06:30:01 PM UTC 25
Finished Feb 08 06:30:17 PM UTC 25
Peak memory 251536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516975317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1516975317
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.2306703792
Short name T45
Test name
Test status
Simulation time 83827009 ps
CPU time 1.59 seconds
Started Feb 08 06:29:56 PM UTC 25
Finished Feb 08 06:29:59 PM UTC 25
Peak memory 229196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306703792 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_parity.2306703792
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.647848173
Short name T63
Test name
Test status
Simulation time 82288372 ps
CPU time 4.57 seconds
Started Feb 08 06:29:59 PM UTC 25
Finished Feb 08 06:30:05 PM UTC 25
Peak memory 245176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647848173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.647848173
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1664960317
Short name T116
Test name
Test status
Simulation time 62864981 ps
CPU time 3.06 seconds
Started Feb 08 06:29:59 PM UTC 25
Finished Feb 08 06:30:03 PM UTC 25
Peak memory 245528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664960317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1664960317
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.934181942
Short name T97
Test name
Test status
Simulation time 970543959 ps
CPU time 13.17 seconds
Started Feb 08 06:30:05 PM UTC 25
Finished Feb 08 06:30:19 PM UTC 25
Peak memory 233596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934181942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.934181942
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.2253786985
Short name T25
Test name
Test status
Simulation time 305059581 ps
CPU time 1.8 seconds
Started Feb 08 06:30:08 PM UTC 25
Finished Feb 08 06:30:11 PM UTC 25
Peak memory 257532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253786985 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2253786985
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.476769805
Short name T24
Test name
Test status
Simulation time 147798426 ps
CPU time 1.46 seconds
Started Feb 08 06:30:08 PM UTC 25
Finished Feb 08 06:30:11 PM UTC 25
Peak memory 215856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476769805 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.476769805
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.3376664502
Short name T75
Test name
Test status
Simulation time 4894340517 ps
CPU time 34.11 seconds
Started Feb 08 06:29:58 PM UTC 25
Finished Feb 08 06:30:34 PM UTC 25
Peak memory 227636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376664502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3376664502
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.225408188
Short name T31
Test name
Test status
Simulation time 15613329 ps
CPU time 1.42 seconds
Started Feb 08 06:29:59 PM UTC 25
Finished Feb 08 06:30:02 PM UTC 25
Peak memory 215840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225408188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.225408188
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.800444616
Short name T27
Test name
Test status
Simulation time 51464741 ps
CPU time 1.35 seconds
Started Feb 08 06:29:58 PM UTC 25
Finished Feb 08 06:30:01 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800444616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.800444616
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.4060079287
Short name T61
Test name
Test status
Simulation time 959923273 ps
CPU time 7.16 seconds
Started Feb 08 06:30:01 PM UTC 25
Finished Feb 08 06:30:10 PM UTC 25
Peak memory 234912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060079287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4060079287
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.995871426
Short name T550
Test name
Test status
Simulation time 22695171 ps
CPU time 1.11 seconds
Started Feb 08 06:35:40 PM UTC 25
Finished Feb 08 06:35:43 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995871426 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.995871426
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.395488158
Short name T560
Test name
Test status
Simulation time 2352988552 ps
CPU time 19.35 seconds
Started Feb 08 06:35:32 PM UTC 25
Finished Feb 08 06:35:53 PM UTC 25
Peak memory 234940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395488158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.395488158
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.3250399614
Short name T542
Test name
Test status
Simulation time 21046886 ps
CPU time 1.23 seconds
Started Feb 08 06:35:20 PM UTC 25
Finished Feb 08 06:35:23 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250399614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3250399614
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.2497485457
Short name T153
Test name
Test status
Simulation time 6150620369 ps
CPU time 36.63 seconds
Started Feb 08 06:35:37 PM UTC 25
Finished Feb 08 06:36:15 PM UTC 25
Peak memory 261656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497485457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2497485457
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.104805407
Short name T243
Test name
Test status
Simulation time 22733010819 ps
CPU time 67.41 seconds
Started Feb 08 06:35:38 PM UTC 25
Finished Feb 08 06:36:47 PM UTC 25
Peak memory 261716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104805407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.104805407
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.2999654047
Short name T295
Test name
Test status
Simulation time 18124600632 ps
CPU time 91.18 seconds
Started Feb 08 06:35:39 PM UTC 25
Finished Feb 08 06:37:13 PM UTC 25
Peak memory 261716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999654047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.2999654047
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.3507883579
Short name T558
Test name
Test status
Simulation time 1197602779 ps
CPU time 10.15 seconds
Started Feb 08 06:35:36 PM UTC 25
Finished Feb 08 06:35:47 PM UTC 25
Peak memory 247252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507883579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3507883579
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1780859151
Short name T369
Test name
Test status
Simulation time 18540244588 ps
CPU time 160.06 seconds
Started Feb 08 06:35:37 PM UTC 25
Finished Feb 08 06:38:20 PM UTC 25
Peak memory 261912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780859151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.1780859151
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.3814920827
Short name T324
Test name
Test status
Simulation time 1048176263 ps
CPU time 9.77 seconds
Started Feb 08 06:35:26 PM UTC 25
Finished Feb 08 06:35:37 PM UTC 25
Peak memory 234964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814920827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3814920827
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.2197228590
Short name T549
Test name
Test status
Simulation time 386610441 ps
CPU time 10.73 seconds
Started Feb 08 06:35:28 PM UTC 25
Finished Feb 08 06:35:40 PM UTC 25
Peak memory 249496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197228590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2197228590
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.2094119581
Short name T332
Test name
Test status
Simulation time 2509496405 ps
CPU time 14.43 seconds
Started Feb 08 06:35:25 PM UTC 25
Finished Feb 08 06:35:40 PM UTC 25
Peak memory 245436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094119581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.2094119581
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.114557250
Short name T292
Test name
Test status
Simulation time 3793492532 ps
CPU time 12.93 seconds
Started Feb 08 06:35:25 PM UTC 25
Finished Feb 08 06:35:39 PM UTC 25
Peak memory 235152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114557250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.114557250
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.1568314992
Short name T552
Test name
Test status
Simulation time 904099029 ps
CPU time 5.28 seconds
Started Feb 08 06:35:37 PM UTC 25
Finished Feb 08 06:35:44 PM UTC 25
Peak memory 231604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568314992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.1568314992
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.211403094
Short name T156
Test name
Test status
Simulation time 7276961097 ps
CPU time 55.9 seconds
Started Feb 08 06:35:21 PM UTC 25
Finished Feb 08 06:36:19 PM UTC 25
Peak memory 231548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211403094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.211403094
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1373436612
Short name T548
Test name
Test status
Simulation time 13110596305 ps
CPU time 15.31 seconds
Started Feb 08 06:35:20 PM UTC 25
Finished Feb 08 06:35:37 PM UTC 25
Peak memory 227416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373436612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1373436612
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.3904163169
Short name T545
Test name
Test status
Simulation time 259986047 ps
CPU time 2.04 seconds
Started Feb 08 06:35:24 PM UTC 25
Finished Feb 08 06:35:27 PM UTC 25
Peak memory 227568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904163169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3904163169
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1193692288
Short name T543
Test name
Test status
Simulation time 63192428 ps
CPU time 1.42 seconds
Started Feb 08 06:35:21 PM UTC 25
Finished Feb 08 06:35:24 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193692288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1193692288
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.720188176
Short name T242
Test name
Test status
Simulation time 554879555 ps
CPU time 6.24 seconds
Started Feb 08 06:35:29 PM UTC 25
Finished Feb 08 06:35:36 PM UTC 25
Peak memory 234932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720188176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.720188176
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.3952187457
Short name T563
Test name
Test status
Simulation time 38187826 ps
CPU time 1.14 seconds
Started Feb 08 06:35:58 PM UTC 25
Finished Feb 08 06:36:00 PM UTC 25
Peak memory 215592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952187457 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.3952187457
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.882363861
Short name T561
Test name
Test status
Simulation time 83697833 ps
CPU time 3.73 seconds
Started Feb 08 06:35:48 PM UTC 25
Finished Feb 08 06:35:53 PM UTC 25
Peak memory 245308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882363861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.882363861
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.3563562673
Short name T553
Test name
Test status
Simulation time 342387539 ps
CPU time 1.22 seconds
Started Feb 08 06:35:42 PM UTC 25
Finished Feb 08 06:35:44 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563562673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3563562673
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.2779753360
Short name T252
Test name
Test status
Simulation time 21346670834 ps
CPU time 200.45 seconds
Started Feb 08 06:35:53 PM UTC 25
Finished Feb 08 06:39:17 PM UTC 25
Peak memory 267528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779753360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2779753360
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.57991116
Short name T729
Test name
Test status
Simulation time 53985103309 ps
CPU time 256.89 seconds
Started Feb 08 06:35:53 PM UTC 25
Finished Feb 08 06:40:14 PM UTC 25
Peak memory 261472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57991116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.57991116
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.4188591406
Short name T366
Test name
Test status
Simulation time 285948250931 ps
CPU time 428.37 seconds
Started Feb 08 06:35:55 PM UTC 25
Finished Feb 08 06:43:09 PM UTC 25
Peak memory 261672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188591406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.4188591406
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.3309577964
Short name T390
Test name
Test status
Simulation time 121712108 ps
CPU time 7.04 seconds
Started Feb 08 06:35:48 PM UTC 25
Finished Feb 08 06:35:56 PM UTC 25
Peak memory 234928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309577964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3309577964
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2573210477
Short name T590
Test name
Test status
Simulation time 1911964478 ps
CPU time 62.73 seconds
Started Feb 08 06:35:49 PM UTC 25
Finished Feb 08 06:36:54 PM UTC 25
Peak memory 261812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573210477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.2573210477
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.2154576114
Short name T310
Test name
Test status
Simulation time 2783390036 ps
CPU time 19.66 seconds
Started Feb 08 06:35:48 PM UTC 25
Finished Feb 08 06:36:09 PM UTC 25
Peak memory 245208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154576114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2154576114
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.1221366306
Short name T286
Test name
Test status
Simulation time 185796138 ps
CPU time 4.11 seconds
Started Feb 08 06:35:48 PM UTC 25
Finished Feb 08 06:35:53 PM UTC 25
Peak memory 235216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221366306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1221366306
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.1045012342
Short name T338
Test name
Test status
Simulation time 65700035 ps
CPU time 2.97 seconds
Started Feb 08 06:35:45 PM UTC 25
Finished Feb 08 06:35:49 PM UTC 25
Peak memory 245464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045012342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.1045012342
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.2738010094
Short name T159
Test name
Test status
Simulation time 12967319431 ps
CPU time 36.14 seconds
Started Feb 08 06:35:45 PM UTC 25
Finished Feb 08 06:36:22 PM UTC 25
Peak memory 245236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738010094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2738010094
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.493899243
Short name T570
Test name
Test status
Simulation time 2727686098 ps
CPU time 21 seconds
Started Feb 08 06:35:50 PM UTC 25
Finished Feb 08 06:36:13 PM UTC 25
Peak memory 233364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493899243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.493899243
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.780933354
Short name T562
Test name
Test status
Simulation time 95952313 ps
CPU time 1.56 seconds
Started Feb 08 06:35:55 PM UTC 25
Finished Feb 08 06:35:57 PM UTC 25
Peak memory 215888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780933354 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.780933354
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.2168097307
Short name T154
Test name
Test status
Simulation time 18834490968 ps
CPU time 33.57 seconds
Started Feb 08 06:35:44 PM UTC 25
Finished Feb 08 06:36:19 PM UTC 25
Peak memory 227480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168097307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2168097307
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.4090864414
Short name T557
Test name
Test status
Simulation time 1038928293 ps
CPU time 2.54 seconds
Started Feb 08 06:35:44 PM UTC 25
Finished Feb 08 06:35:47 PM UTC 25
Peak memory 216852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090864414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4090864414
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.3191389798
Short name T559
Test name
Test status
Simulation time 60369852 ps
CPU time 1.69 seconds
Started Feb 08 06:35:45 PM UTC 25
Finished Feb 08 06:35:48 PM UTC 25
Peak memory 216304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191389798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3191389798
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.1943441790
Short name T556
Test name
Test status
Simulation time 46835582 ps
CPU time 1.35 seconds
Started Feb 08 06:35:45 PM UTC 25
Finished Feb 08 06:35:47 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943441790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1943441790
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.23693381
Short name T358
Test name
Test status
Simulation time 1343839381 ps
CPU time 4.18 seconds
Started Feb 08 06:35:48 PM UTC 25
Finished Feb 08 06:35:53 PM UTC 25
Peak memory 234904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23693381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.23693381
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.934847091
Short name T571
Test name
Test status
Simulation time 30453946 ps
CPU time 1.1 seconds
Started Feb 08 06:36:23 PM UTC 25
Finished Feb 08 06:36:25 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934847091 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.934847091
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2174184827
Short name T157
Test name
Test status
Simulation time 431215223 ps
CPU time 4.6 seconds
Started Feb 08 06:36:13 PM UTC 25
Finished Feb 08 06:36:19 PM UTC 25
Peak memory 245400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174184827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2174184827
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.3392340415
Short name T564
Test name
Test status
Simulation time 53455821 ps
CPU time 1.2 seconds
Started Feb 08 06:35:58 PM UTC 25
Finished Feb 08 06:36:00 PM UTC 25
Peak memory 215736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392340415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3392340415
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.389463507
Short name T604
Test name
Test status
Simulation time 25934105548 ps
CPU time 52.96 seconds
Started Feb 08 06:36:20 PM UTC 25
Finished Feb 08 06:37:14 PM UTC 25
Peak memory 246956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389463507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.389463507
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.1903481922
Short name T598
Test name
Test status
Simulation time 5238854239 ps
CPU time 43.81 seconds
Started Feb 08 06:36:20 PM UTC 25
Finished Feb 08 06:37:05 PM UTC 25
Peak memory 261864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903481922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.1903481922
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.622801390
Short name T577
Test name
Test status
Simulation time 1516455149 ps
CPU time 13.27 seconds
Started Feb 08 06:36:15 PM UTC 25
Finished Feb 08 06:36:30 PM UTC 25
Peak memory 251376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622801390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.622801390
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.2284084566
Short name T337
Test name
Test status
Simulation time 6652847136 ps
CPU time 53.09 seconds
Started Feb 08 06:36:17 PM UTC 25
Finished Feb 08 06:37:11 PM UTC 25
Peak memory 234504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284084566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.2284084566
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.304316846
Short name T155
Test name
Test status
Simulation time 417345452 ps
CPU time 7.35 seconds
Started Feb 08 06:36:10 PM UTC 25
Finished Feb 08 06:36:19 PM UTC 25
Peak memory 234884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304316846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.304316846
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.1431626340
Short name T361
Test name
Test status
Simulation time 6063845445 ps
CPU time 60.5 seconds
Started Feb 08 06:36:11 PM UTC 25
Finished Feb 08 06:37:13 PM UTC 25
Peak memory 261592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431626340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1431626340
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.979195248
Short name T158
Test name
Test status
Simulation time 813587995 ps
CPU time 10.74 seconds
Started Feb 08 06:36:09 PM UTC 25
Finished Feb 08 06:36:21 PM UTC 25
Peak memory 234944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979195248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.979195248
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.2218638586
Short name T569
Test name
Test status
Simulation time 754463903 ps
CPU time 3.06 seconds
Started Feb 08 06:36:07 PM UTC 25
Finished Feb 08 06:36:11 PM UTC 25
Peak memory 234312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218638586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2218638586
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1815575620
Short name T574
Test name
Test status
Simulation time 128965525 ps
CPU time 6.1 seconds
Started Feb 08 06:36:20 PM UTC 25
Finished Feb 08 06:36:27 PM UTC 25
Peak memory 233268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815575620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.1815575620
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.1419031938
Short name T635
Test name
Test status
Simulation time 17452679277 ps
CPU time 106.11 seconds
Started Feb 08 06:36:22 PM UTC 25
Finished Feb 08 06:38:10 PM UTC 25
Peak memory 267780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419031938 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.1419031938
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.3433503097
Short name T565
Test name
Test status
Simulation time 27125246 ps
CPU time 1.08 seconds
Started Feb 08 06:36:01 PM UTC 25
Finished Feb 08 06:36:03 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433503097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3433503097
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.2311705001
Short name T160
Test name
Test status
Simulation time 21662211357 ps
CPU time 20.92 seconds
Started Feb 08 06:36:01 PM UTC 25
Finished Feb 08 06:36:23 PM UTC 25
Peak memory 227352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311705001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2311705001
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.1581498003
Short name T568
Test name
Test status
Simulation time 187882752 ps
CPU time 2.34 seconds
Started Feb 08 06:36:07 PM UTC 25
Finished Feb 08 06:36:10 PM UTC 25
Peak memory 216808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581498003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1581498003
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.245852557
Short name T566
Test name
Test status
Simulation time 49329240 ps
CPU time 1.25 seconds
Started Feb 08 06:36:04 PM UTC 25
Finished Feb 08 06:36:06 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245852557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.245852557
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.960059530
Short name T575
Test name
Test status
Simulation time 6610867559 ps
CPU time 14.12 seconds
Started Feb 08 06:36:12 PM UTC 25
Finished Feb 08 06:36:28 PM UTC 25
Peak memory 247268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960059530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.960059530
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.2926387426
Short name T587
Test name
Test status
Simulation time 14867483 ps
CPU time 1.14 seconds
Started Feb 08 06:36:48 PM UTC 25
Finished Feb 08 06:36:50 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926387426 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.2926387426
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.2864598775
Short name T583
Test name
Test status
Simulation time 425718781 ps
CPU time 4.1 seconds
Started Feb 08 06:36:34 PM UTC 25
Finished Feb 08 06:36:39 PM UTC 25
Peak memory 235124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864598775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2864598775
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.4195475693
Short name T572
Test name
Test status
Simulation time 23387842 ps
CPU time 1.19 seconds
Started Feb 08 06:36:24 PM UTC 25
Finished Feb 08 06:36:26 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195475693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4195475693
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.3313081338
Short name T296
Test name
Test status
Simulation time 3377114060 ps
CPU time 53.25 seconds
Started Feb 08 06:36:40 PM UTC 25
Finished Feb 08 06:37:35 PM UTC 25
Peak memory 251412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313081338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3313081338
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.866874608
Short name T165
Test name
Test status
Simulation time 196492784539 ps
CPU time 479.56 seconds
Started Feb 08 06:36:40 PM UTC 25
Finished Feb 08 06:44:45 PM UTC 25
Peak memory 284244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866874608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.866874608
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.3112066597
Short name T394
Test name
Test status
Simulation time 4151082309 ps
CPU time 81.11 seconds
Started Feb 08 06:36:36 PM UTC 25
Finished Feb 08 06:37:59 PM UTC 25
Peak memory 245232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112066597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3112066597
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.745633662
Short name T643
Test name
Test status
Simulation time 43904649439 ps
CPU time 98.41 seconds
Started Feb 08 06:36:36 PM UTC 25
Finished Feb 08 06:38:16 PM UTC 25
Peak memory 235288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745633662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.745633662
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.966668812
Short name T314
Test name
Test status
Simulation time 1725336642 ps
CPU time 11.12 seconds
Started Feb 08 06:36:30 PM UTC 25
Finished Feb 08 06:36:43 PM UTC 25
Peak memory 245184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966668812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.966668812
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.1079821830
Short name T584
Test name
Test status
Simulation time 640017242 ps
CPU time 15.83 seconds
Started Feb 08 06:36:31 PM UTC 25
Finished Feb 08 06:36:48 PM UTC 25
Peak memory 251412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079821830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1079821830
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.2947837225
Short name T582
Test name
Test status
Simulation time 324435730 ps
CPU time 9.05 seconds
Started Feb 08 06:36:28 PM UTC 25
Finished Feb 08 06:36:39 PM UTC 25
Peak memory 235132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947837225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.2947837225
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.3661818767
Short name T579
Test name
Test status
Simulation time 575927519 ps
CPU time 5.06 seconds
Started Feb 08 06:36:28 PM UTC 25
Finished Feb 08 06:36:35 PM UTC 25
Peak memory 234868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661818767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3661818767
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3779079066
Short name T585
Test name
Test status
Simulation time 2068814267 ps
CPU time 9.97 seconds
Started Feb 08 06:36:39 PM UTC 25
Finished Feb 08 06:36:50 PM UTC 25
Peak memory 233652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779079066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.3779079066
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.501168056
Short name T186
Test name
Test status
Simulation time 87521034436 ps
CPU time 295.87 seconds
Started Feb 08 06:36:44 PM UTC 25
Finished Feb 08 06:41:44 PM UTC 25
Peak memory 265788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501168056 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.501168056
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.3129410859
Short name T593
Test name
Test status
Simulation time 9964576618 ps
CPU time 31.49 seconds
Started Feb 08 06:36:26 PM UTC 25
Finished Feb 08 06:36:59 PM UTC 25
Peak memory 227412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129410859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3129410859
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.1027187696
Short name T578
Test name
Test status
Simulation time 1563224756 ps
CPU time 6.52 seconds
Started Feb 08 06:36:25 PM UTC 25
Finished Feb 08 06:36:33 PM UTC 25
Peak memory 227572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027187696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1027187696
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.1379509795
Short name T411
Test name
Test status
Simulation time 1053785351 ps
CPU time 2.89 seconds
Started Feb 08 06:36:28 PM UTC 25
Finished Feb 08 06:36:33 PM UTC 25
Peak memory 227448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379509795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1379509795
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1870168971
Short name T576
Test name
Test status
Simulation time 189536768 ps
CPU time 1.39 seconds
Started Feb 08 06:36:27 PM UTC 25
Finished Feb 08 06:36:30 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870168971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1870168971
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.3713501634
Short name T315
Test name
Test status
Simulation time 16638402449 ps
CPU time 20.97 seconds
Started Feb 08 06:36:34 PM UTC 25
Finished Feb 08 06:36:56 PM UTC 25
Peak memory 245432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713501634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3713501634
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.2525163185
Short name T599
Test name
Test status
Simulation time 12770767 ps
CPU time 1.13 seconds
Started Feb 08 06:37:03 PM UTC 25
Finished Feb 08 06:37:05 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525163185 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.2525163185
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3111234548
Short name T594
Test name
Test status
Simulation time 317966082 ps
CPU time 4.41 seconds
Started Feb 08 06:36:56 PM UTC 25
Finished Feb 08 06:37:01 PM UTC 25
Peak memory 235160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111234548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3111234548
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.1150766886
Short name T588
Test name
Test status
Simulation time 20574680 ps
CPU time 1.12 seconds
Started Feb 08 06:36:48 PM UTC 25
Finished Feb 08 06:36:50 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150766886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1150766886
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.4286614274
Short name T596
Test name
Test status
Simulation time 22417517 ps
CPU time 1.2 seconds
Started Feb 08 06:37:00 PM UTC 25
Finished Feb 08 06:37:02 PM UTC 25
Peak memory 225332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286614274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4286614274
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.359545780
Short name T709
Test name
Test status
Simulation time 8312146869 ps
CPU time 164.9 seconds
Started Feb 08 06:37:00 PM UTC 25
Finished Feb 08 06:39:48 PM UTC 25
Peak memory 264016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359545780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.359545780
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.3917896
Short name T269
Test name
Test status
Simulation time 3915219917 ps
CPU time 72.19 seconds
Started Feb 08 06:37:02 PM UTC 25
Finished Feb 08 06:38:16 PM UTC 25
Peak memory 261692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.3917896
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.2263632603
Short name T595
Test name
Test status
Simulation time 160843698 ps
CPU time 4.02 seconds
Started Feb 08 06:36:57 PM UTC 25
Finished Feb 08 06:37:02 PM UTC 25
Peak memory 234864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263632603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2263632603
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2814536583
Short name T689
Test name
Test status
Simulation time 111105395327 ps
CPU time 136.1 seconds
Started Feb 08 06:37:00 PM UTC 25
Finished Feb 08 06:39:19 PM UTC 25
Peak memory 267376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814536583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.2814536583
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.4216070408
Short name T597
Test name
Test status
Simulation time 552764435 ps
CPU time 9.54 seconds
Started Feb 08 06:36:54 PM UTC 25
Finished Feb 08 06:37:04 PM UTC 25
Peak memory 234876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216070408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4216070408
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.788421548
Short name T240
Test name
Test status
Simulation time 1916152927 ps
CPU time 35.35 seconds
Started Feb 08 06:36:55 PM UTC 25
Finished Feb 08 06:37:32 PM UTC 25
Peak memory 245116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788421548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.788421548
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.2655923214
Short name T601
Test name
Test status
Simulation time 2772102120 ps
CPU time 15.28 seconds
Started Feb 08 06:36:52 PM UTC 25
Finished Feb 08 06:37:08 PM UTC 25
Peak memory 251640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655923214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.2655923214
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3564274812
Short name T290
Test name
Test status
Simulation time 45707761605 ps
CPU time 20.46 seconds
Started Feb 08 06:36:52 PM UTC 25
Finished Feb 08 06:37:13 PM UTC 25
Peak memory 244664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564274812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3564274812
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3576204434
Short name T573
Test name
Test status
Simulation time 2205743612 ps
CPU time 11.14 seconds
Started Feb 08 06:37:00 PM UTC 25
Finished Feb 08 06:37:12 PM UTC 25
Peak memory 233268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576204434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.3576204434
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.3680276731
Short name T736
Test name
Test status
Simulation time 12599781197 ps
CPU time 195.75 seconds
Started Feb 08 06:37:03 PM UTC 25
Finished Feb 08 06:40:22 PM UTC 25
Peak memory 284208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680276731 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.3680276731
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.3183612702
Short name T606
Test name
Test status
Simulation time 4751496288 ps
CPU time 30.9 seconds
Started Feb 08 06:36:49 PM UTC 25
Finished Feb 08 06:37:22 PM UTC 25
Peak memory 227264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183612702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3183612702
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1071281927
Short name T592
Test name
Test status
Simulation time 771319138 ps
CPU time 8.19 seconds
Started Feb 08 06:36:49 PM UTC 25
Finished Feb 08 06:36:59 PM UTC 25
Peak memory 227068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071281927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1071281927
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.1543922102
Short name T591
Test name
Test status
Simulation time 19461588 ps
CPU time 1.27 seconds
Started Feb 08 06:36:52 PM UTC 25
Finished Feb 08 06:36:54 PM UTC 25
Peak memory 214620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543922102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1543922102
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.3279597485
Short name T589
Test name
Test status
Simulation time 336168909 ps
CPU time 1.51 seconds
Started Feb 08 06:36:50 PM UTC 25
Finished Feb 08 06:36:53 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279597485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3279597485
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.1911399423
Short name T352
Test name
Test status
Simulation time 654961199 ps
CPU time 3.78 seconds
Started Feb 08 06:36:55 PM UTC 25
Finished Feb 08 06:37:00 PM UTC 25
Peak memory 234852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911399423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1911399423
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.3610576
Short name T610
Test name
Test status
Simulation time 12453700 ps
CPU time 1.14 seconds
Started Feb 08 06:37:29 PM UTC 25
Finished Feb 08 06:37:31 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610576 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.3610576
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3250264658
Short name T617
Test name
Test status
Simulation time 6080940579 ps
CPU time 25.46 seconds
Started Feb 08 06:37:14 PM UTC 25
Finished Feb 08 06:37:41 PM UTC 25
Peak memory 234996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250264658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3250264658
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.1879577967
Short name T600
Test name
Test status
Simulation time 16666239 ps
CPU time 1.16 seconds
Started Feb 08 06:37:05 PM UTC 25
Finished Feb 08 06:37:08 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879577967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1879577967
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.270895824
Short name T615
Test name
Test status
Simulation time 5563902120 ps
CPU time 20.48 seconds
Started Feb 08 06:37:18 PM UTC 25
Finished Feb 08 06:37:40 PM UTC 25
Peak memory 251412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270895824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.270895824
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3478863930
Short name T622
Test name
Test status
Simulation time 27593822564 ps
CPU time 27.01 seconds
Started Feb 08 06:37:22 PM UTC 25
Finished Feb 08 06:37:51 PM UTC 25
Peak memory 229692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478863930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3478863930
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.1720617862
Short name T957
Test name
Test status
Simulation time 49392675427 ps
CPU time 449.61 seconds
Started Feb 08 06:37:24 PM UTC 25
Finished Feb 08 06:44:59 PM UTC 25
Peak memory 284208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720617862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.1720617862
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.3684546315
Short name T611
Test name
Test status
Simulation time 2235187621 ps
CPU time 16 seconds
Started Feb 08 06:37:14 PM UTC 25
Finished Feb 08 06:37:31 PM UTC 25
Peak memory 234992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684546315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3684546315
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.4292980491
Short name T637
Test name
Test status
Simulation time 12414939052 ps
CPU time 55.4 seconds
Started Feb 08 06:37:15 PM UTC 25
Finished Feb 08 06:38:12 PM UTC 25
Peak memory 261876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292980491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.4292980491
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.3056123623
Short name T618
Test name
Test status
Simulation time 13805271590 ps
CPU time 26.78 seconds
Started Feb 08 06:37:13 PM UTC 25
Finished Feb 08 06:37:41 PM UTC 25
Peak memory 245236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056123623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3056123623
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.3491431106
Short name T329
Test name
Test status
Simulation time 11918459235 ps
CPU time 52.51 seconds
Started Feb 08 06:37:13 PM UTC 25
Finished Feb 08 06:38:07 PM UTC 25
Peak memory 261808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491431106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3491431106
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3393756298
Short name T627
Test name
Test status
Simulation time 25159806223 ps
CPU time 40.23 seconds
Started Feb 08 06:37:12 PM UTC 25
Finished Feb 08 06:37:54 PM UTC 25
Peak memory 235292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393756298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.3393756298
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2535505228
Short name T607
Test name
Test status
Simulation time 2757396784 ps
CPU time 10.14 seconds
Started Feb 08 06:37:12 PM UTC 25
Finished Feb 08 06:37:23 PM UTC 25
Peak memory 245400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535505228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2535505228
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.3420308115
Short name T609
Test name
Test status
Simulation time 678844975 ps
CPU time 11.86 seconds
Started Feb 08 06:37:16 PM UTC 25
Finished Feb 08 06:37:29 PM UTC 25
Peak memory 231192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420308115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.3420308115
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.1681431915
Short name T169
Test name
Test status
Simulation time 46607342282 ps
CPU time 579.89 seconds
Started Feb 08 06:37:28 PM UTC 25
Finished Feb 08 06:47:15 PM UTC 25
Peak memory 282420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681431915 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.1681431915
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.3157199544
Short name T605
Test name
Test status
Simulation time 7870322692 ps
CPU time 7.53 seconds
Started Feb 08 06:37:07 PM UTC 25
Finished Feb 08 06:37:15 PM UTC 25
Peak memory 227672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157199544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3157199544
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.3201100788
Short name T623
Test name
Test status
Simulation time 15725320523 ps
CPU time 43.19 seconds
Started Feb 08 06:37:07 PM UTC 25
Finished Feb 08 06:37:51 PM UTC 25
Peak memory 227588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201100788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3201100788
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.1538983472
Short name T603
Test name
Test status
Simulation time 32619063 ps
CPU time 1.85 seconds
Started Feb 08 06:37:09 PM UTC 25
Finished Feb 08 06:37:12 PM UTC 25
Peak memory 216244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538983472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1538983472
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.1833091043
Short name T602
Test name
Test status
Simulation time 133712500 ps
CPU time 1.34 seconds
Started Feb 08 06:37:09 PM UTC 25
Finished Feb 08 06:37:11 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833091043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1833091043
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.597853694
Short name T608
Test name
Test status
Simulation time 8436438297 ps
CPU time 13.76 seconds
Started Feb 08 06:37:13 PM UTC 25
Finished Feb 08 06:37:28 PM UTC 25
Peak memory 245220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597853694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.597853694
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.2318670461
Short name T628
Test name
Test status
Simulation time 16258265 ps
CPU time 1.12 seconds
Started Feb 08 06:37:52 PM UTC 25
Finished Feb 08 06:37:54 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318670461 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.2318670461
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.2082131149
Short name T621
Test name
Test status
Simulation time 537800331 ps
CPU time 4.55 seconds
Started Feb 08 06:37:41 PM UTC 25
Finished Feb 08 06:37:47 PM UTC 25
Peak memory 234868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082131149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2082131149
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.800407827
Short name T612
Test name
Test status
Simulation time 28761591 ps
CPU time 1.18 seconds
Started Feb 08 06:37:30 PM UTC 25
Finished Feb 08 06:37:32 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800407827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.800407827
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.3996926476
Short name T639
Test name
Test status
Simulation time 790219664 ps
CPU time 27.82 seconds
Started Feb 08 06:37:44 PM UTC 25
Finished Feb 08 06:38:13 PM UTC 25
Peak memory 265656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996926476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3996926476
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.310275259
Short name T712
Test name
Test status
Simulation time 12540824918 ps
CPU time 123.49 seconds
Started Feb 08 06:37:47 PM UTC 25
Finished Feb 08 06:39:52 PM UTC 25
Peak memory 267824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310275259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.310275259
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.3983800432
Short name T824
Test name
Test status
Simulation time 88726340440 ps
CPU time 271.46 seconds
Started Feb 08 06:37:48 PM UTC 25
Finished Feb 08 06:42:23 PM UTC 25
Peak memory 278292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983800432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.3983800432
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.326619306
Short name T626
Test name
Test status
Simulation time 253917311 ps
CPU time 9.97 seconds
Started Feb 08 06:37:41 PM UTC 25
Finished Feb 08 06:37:53 PM UTC 25
Peak memory 245168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326619306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.326619306
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.3032880811
Short name T730
Test name
Test status
Simulation time 119275834836 ps
CPU time 149.09 seconds
Started Feb 08 06:37:43 PM UTC 25
Finished Feb 08 06:40:14 PM UTC 25
Peak memory 261624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032880811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.3032880811
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.2628023350
Short name T619
Test name
Test status
Simulation time 857524099 ps
CPU time 4.9 seconds
Started Feb 08 06:37:36 PM UTC 25
Finished Feb 08 06:37:42 PM UTC 25
Peak memory 235132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628023350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2628023350
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.3764061346
Short name T681
Test name
Test status
Simulation time 68110650398 ps
CPU time 86.6 seconds
Started Feb 08 06:37:39 PM UTC 25
Finished Feb 08 06:39:08 PM UTC 25
Peak memory 245264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764061346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3764061346
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.1180884112
Short name T341
Test name
Test status
Simulation time 145368089 ps
CPU time 3.57 seconds
Started Feb 08 06:37:36 PM UTC 25
Finished Feb 08 06:37:41 PM UTC 25
Peak memory 234924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180884112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.1180884112
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.2482672799
Short name T616
Test name
Test status
Simulation time 279328290 ps
CPU time 3.08 seconds
Started Feb 08 06:37:36 PM UTC 25
Finished Feb 08 06:37:40 PM UTC 25
Peak memory 233840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482672799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2482672799
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.329973741
Short name T625
Test name
Test status
Simulation time 2582421300 ps
CPU time 8.73 seconds
Started Feb 08 06:37:43 PM UTC 25
Finished Feb 08 06:37:52 PM UTC 25
Peak memory 233684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329973741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.329973741
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.2826748372
Short name T636
Test name
Test status
Simulation time 2187023788 ps
CPU time 18.03 seconds
Started Feb 08 06:37:52 PM UTC 25
Finished Feb 08 06:38:11 PM UTC 25
Peak memory 235056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826748372 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.2826748372
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.3816181036
Short name T620
Test name
Test status
Simulation time 1694713995 ps
CPU time 12.52 seconds
Started Feb 08 06:37:32 PM UTC 25
Finished Feb 08 06:37:46 PM UTC 25
Peak memory 227396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816181036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3816181036
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1580470662
Short name T624
Test name
Test status
Simulation time 9295616176 ps
CPU time 18.76 seconds
Started Feb 08 06:37:32 PM UTC 25
Finished Feb 08 06:37:52 PM UTC 25
Peak memory 227348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580470662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1580470662
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.1918745744
Short name T613
Test name
Test status
Simulation time 13049598 ps
CPU time 1.09 seconds
Started Feb 08 06:37:33 PM UTC 25
Finished Feb 08 06:37:35 PM UTC 25
Peak memory 215832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918745744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1918745744
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.958413107
Short name T614
Test name
Test status
Simulation time 25371370 ps
CPU time 1.15 seconds
Started Feb 08 06:37:33 PM UTC 25
Finished Feb 08 06:37:35 PM UTC 25
Peak memory 215840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958413107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.958413107
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.4167614309
Short name T304
Test name
Test status
Simulation time 10275618236 ps
CPU time 10.65 seconds
Started Feb 08 06:37:41 PM UTC 25
Finished Feb 08 06:37:53 PM UTC 25
Peak memory 245464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167614309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4167614309
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.2696731628
Short name T642
Test name
Test status
Simulation time 52270711 ps
CPU time 1.18 seconds
Started Feb 08 06:38:13 PM UTC 25
Finished Feb 08 06:38:16 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696731628 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.2696731628
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.1421141771
Short name T634
Test name
Test status
Simulation time 378524110 ps
CPU time 5.14 seconds
Started Feb 08 06:38:00 PM UTC 25
Finished Feb 08 06:38:06 PM UTC 25
Peak memory 234872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421141771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1421141771
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.2230654370
Short name T629
Test name
Test status
Simulation time 83112963 ps
CPU time 1.17 seconds
Started Feb 08 06:37:53 PM UTC 25
Finished Feb 08 06:37:56 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230654370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2230654370
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.342619609
Short name T654
Test name
Test status
Simulation time 718950963 ps
CPU time 14.32 seconds
Started Feb 08 06:38:11 PM UTC 25
Finished Feb 08 06:38:27 PM UTC 25
Peak memory 249316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342619609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.342619609
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3950345265
Short name T694
Test name
Test status
Simulation time 6333885802 ps
CPU time 72.71 seconds
Started Feb 08 06:38:11 PM UTC 25
Finished Feb 08 06:39:26 PM UTC 25
Peak memory 268084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950345265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.3950345265
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.1860312187
Short name T646
Test name
Test status
Simulation time 1944726831 ps
CPU time 12.58 seconds
Started Feb 08 06:38:03 PM UTC 25
Finished Feb 08 06:38:17 PM UTC 25
Peak memory 261780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860312187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1860312187
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3637601924
Short name T335
Test name
Test status
Simulation time 45163528488 ps
CPU time 78.52 seconds
Started Feb 08 06:38:04 PM UTC 25
Finished Feb 08 06:39:25 PM UTC 25
Peak memory 265748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637601924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.3637601924
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.4190009538
Short name T632
Test name
Test status
Simulation time 141399943 ps
CPU time 4.12 seconds
Started Feb 08 06:37:57 PM UTC 25
Finished Feb 08 06:38:02 PM UTC 25
Peak memory 234936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190009538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4190009538
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.3777681753
Short name T351
Test name
Test status
Simulation time 1009427485 ps
CPU time 10.92 seconds
Started Feb 08 06:37:58 PM UTC 25
Finished Feb 08 06:38:10 PM UTC 25
Peak memory 245396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777681753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3777681753
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3350903436
Short name T340
Test name
Test status
Simulation time 6835691020 ps
CPU time 18.94 seconds
Started Feb 08 06:37:56 PM UTC 25
Finished Feb 08 06:38:16 PM UTC 25
Peak memory 251384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350903436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.3350903436
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.2014165041
Short name T647
Test name
Test status
Simulation time 3163059264 ps
CPU time 22.44 seconds
Started Feb 08 06:37:55 PM UTC 25
Finished Feb 08 06:38:18 PM UTC 25
Peak memory 245176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014165041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2014165041
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3343392386
Short name T644
Test name
Test status
Simulation time 363941175 ps
CPU time 8.53 seconds
Started Feb 08 06:38:07 PM UTC 25
Finished Feb 08 06:38:17 PM UTC 25
Peak memory 233508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343392386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.3343392386
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.442489861
Short name T188
Test name
Test status
Simulation time 344816503223 ps
CPU time 272.98 seconds
Started Feb 08 06:38:12 PM UTC 25
Finished Feb 08 06:42:49 PM UTC 25
Peak memory 278068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442489861 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.442489861
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.991188893
Short name T649
Test name
Test status
Simulation time 2523739021 ps
CPU time 24.61 seconds
Started Feb 08 06:37:53 PM UTC 25
Finished Feb 08 06:38:19 PM UTC 25
Peak memory 227520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991188893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.991188893
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1805827525
Short name T633
Test name
Test status
Simulation time 4000004759 ps
CPU time 8.61 seconds
Started Feb 08 06:37:53 PM UTC 25
Finished Feb 08 06:38:03 PM UTC 25
Peak memory 227152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805827525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1805827525
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.2639188135
Short name T631
Test name
Test status
Simulation time 421687728 ps
CPU time 1.98 seconds
Started Feb 08 06:37:55 PM UTC 25
Finished Feb 08 06:37:58 PM UTC 25
Peak memory 216364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639188135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2639188135
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.1204241719
Short name T630
Test name
Test status
Simulation time 131444222 ps
CPU time 1.28 seconds
Started Feb 08 06:37:54 PM UTC 25
Finished Feb 08 06:37:57 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204241719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1204241719
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.1409845817
Short name T638
Test name
Test status
Simulation time 4098174605 ps
CPU time 12.95 seconds
Started Feb 08 06:37:59 PM UTC 25
Finished Feb 08 06:38:13 PM UTC 25
Peak memory 261596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409845817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1409845817
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.1936421121
Short name T653
Test name
Test status
Simulation time 16036934 ps
CPU time 1.16 seconds
Started Feb 08 06:38:23 PM UTC 25
Finished Feb 08 06:38:25 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936421121 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.1936421121
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.4237084035
Short name T652
Test name
Test status
Simulation time 456384107 ps
CPU time 4.9 seconds
Started Feb 08 06:38:18 PM UTC 25
Finished Feb 08 06:38:24 PM UTC 25
Peak memory 235220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237084035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4237084035
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.4240207052
Short name T641
Test name
Test status
Simulation time 34110111 ps
CPU time 1.17 seconds
Started Feb 08 06:38:14 PM UTC 25
Finished Feb 08 06:38:16 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240207052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4240207052
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.1797430602
Short name T700
Test name
Test status
Simulation time 9477033458 ps
CPU time 77.25 seconds
Started Feb 08 06:38:19 PM UTC 25
Finished Feb 08 06:39:38 PM UTC 25
Peak memory 261620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797430602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1797430602
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.7683918
Short name T708
Test name
Test status
Simulation time 3619677525 ps
CPU time 85 seconds
Started Feb 08 06:38:20 PM UTC 25
Finished Feb 08 06:39:48 PM UTC 25
Peak memory 267836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7683918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.7683918
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.947665080
Short name T683
Test name
Test status
Simulation time 17440818573 ps
CPU time 46.47 seconds
Started Feb 08 06:38:20 PM UTC 25
Finished Feb 08 06:39:09 PM UTC 25
Peak memory 261976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947665080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.947665080
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.2967003487
Short name T692
Test name
Test status
Simulation time 18284791603 ps
CPU time 64.97 seconds
Started Feb 08 06:38:18 PM UTC 25
Finished Feb 08 06:39:25 PM UTC 25
Peak memory 267796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967003487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.2967003487
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.1190385677
Short name T659
Test name
Test status
Simulation time 1010732015 ps
CPU time 9.82 seconds
Started Feb 08 06:38:17 PM UTC 25
Finished Feb 08 06:38:28 PM UTC 25
Peak memory 234872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190385677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1190385677
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.615732371
Short name T651
Test name
Test status
Simulation time 182276988 ps
CPU time 4.84 seconds
Started Feb 08 06:38:17 PM UTC 25
Finished Feb 08 06:38:23 PM UTC 25
Peak memory 234864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615732371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.615732371
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.531475924
Short name T380
Test name
Test status
Simulation time 10167162522 ps
CPU time 18.91 seconds
Started Feb 08 06:38:17 PM UTC 25
Finished Feb 08 06:38:37 PM UTC 25
Peak memory 245468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531475924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.531475924
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1117554034
Short name T658
Test name
Test status
Simulation time 9034234607 ps
CPU time 9.14 seconds
Started Feb 08 06:38:17 PM UTC 25
Finished Feb 08 06:38:27 PM UTC 25
Peak memory 235128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117554034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1117554034
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.1071260414
Short name T657
Test name
Test status
Simulation time 546500034 ps
CPU time 6.94 seconds
Started Feb 08 06:38:19 PM UTC 25
Finished Feb 08 06:38:27 PM UTC 25
Peak memory 233484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071260414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.1071260414
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.1246183763
Short name T664
Test name
Test status
Simulation time 1057425350 ps
CPU time 11.43 seconds
Started Feb 08 06:38:22 PM UTC 25
Finished Feb 08 06:38:34 PM UTC 25
Peak memory 235252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246183763 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.1246183763
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.3754303912
Short name T665
Test name
Test status
Simulation time 7286825643 ps
CPU time 22.12 seconds
Started Feb 08 06:38:14 PM UTC 25
Finished Feb 08 06:38:37 PM UTC 25
Peak memory 227648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754303912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3754303912
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3080046904
Short name T650
Test name
Test status
Simulation time 4863078806 ps
CPU time 6.72 seconds
Started Feb 08 06:38:14 PM UTC 25
Finished Feb 08 06:38:21 PM UTC 25
Peak memory 227540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080046904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3080046904
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.1511816669
Short name T648
Test name
Test status
Simulation time 251277318 ps
CPU time 2 seconds
Started Feb 08 06:38:16 PM UTC 25
Finished Feb 08 06:38:19 PM UTC 25
Peak memory 226492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511816669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1511816669
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.844983118
Short name T645
Test name
Test status
Simulation time 38627456 ps
CPU time 1.19 seconds
Started Feb 08 06:38:15 PM UTC 25
Finished Feb 08 06:38:17 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844983118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.844983118
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.3643918231
Short name T359
Test name
Test status
Simulation time 3158117253 ps
CPU time 16.6 seconds
Started Feb 08 06:38:17 PM UTC 25
Finished Feb 08 06:38:35 PM UTC 25
Peak memory 235032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643918231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3643918231
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.248244102
Short name T670
Test name
Test status
Simulation time 61985164 ps
CPU time 1.1 seconds
Started Feb 08 06:38:43 PM UTC 25
Finished Feb 08 06:38:45 PM UTC 25
Peak memory 215688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248244102 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.248244102
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1200325974
Short name T666
Test name
Test status
Simulation time 121518563 ps
CPU time 4.53 seconds
Started Feb 08 06:38:33 PM UTC 25
Finished Feb 08 06:38:39 PM UTC 25
Peak memory 245148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200325974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1200325974
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.3152284688
Short name T656
Test name
Test status
Simulation time 15484221 ps
CPU time 1.14 seconds
Started Feb 08 06:38:25 PM UTC 25
Finished Feb 08 06:38:27 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152284688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3152284688
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.2271338333
Short name T810
Test name
Test status
Simulation time 205688660715 ps
CPU time 209.49 seconds
Started Feb 08 06:38:38 PM UTC 25
Finished Feb 08 06:42:10 PM UTC 25
Peak memory 261680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271338333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2271338333
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.341967809
Short name T163
Test name
Test status
Simulation time 11075109401 ps
CPU time 76.03 seconds
Started Feb 08 06:38:38 PM UTC 25
Finished Feb 08 06:39:56 PM UTC 25
Peak memory 266032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341967809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.341967809
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.1141567575
Short name T391
Test name
Test status
Simulation time 742891786 ps
CPU time 8.07 seconds
Started Feb 08 06:38:33 PM UTC 25
Finished Feb 08 06:38:43 PM UTC 25
Peak memory 234876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141567575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1141567575
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3368984577
Short name T877
Test name
Test status
Simulation time 102068800966 ps
CPU time 284.46 seconds
Started Feb 08 06:38:33 PM UTC 25
Finished Feb 08 06:43:22 PM UTC 25
Peak memory 267768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368984577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.3368984577
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.1621178031
Short name T668
Test name
Test status
Simulation time 608351694 ps
CPU time 12.53 seconds
Started Feb 08 06:38:28 PM UTC 25
Finished Feb 08 06:38:42 PM UTC 25
Peak memory 235160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621178031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1621178031
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.1081515809
Short name T677
Test name
Test status
Simulation time 857174278 ps
CPU time 26.36 seconds
Started Feb 08 06:38:29 PM UTC 25
Finished Feb 08 06:38:57 PM UTC 25
Peak memory 245168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081515809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1081515809
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.3080132793
Short name T663
Test name
Test status
Simulation time 222228634 ps
CPU time 3.3 seconds
Started Feb 08 06:38:28 PM UTC 25
Finished Feb 08 06:38:33 PM UTC 25
Peak memory 245208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080132793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.3080132793
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.3963737924
Short name T673
Test name
Test status
Simulation time 5206269732 ps
CPU time 17.06 seconds
Started Feb 08 06:38:28 PM UTC 25
Finished Feb 08 06:38:47 PM UTC 25
Peak memory 235124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963737924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3963737924
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.573988432
Short name T675
Test name
Test status
Simulation time 3889737030 ps
CPU time 15.37 seconds
Started Feb 08 06:38:36 PM UTC 25
Finished Feb 08 06:38:52 PM UTC 25
Peak memory 231256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573988432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.573988432
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.997256355
Short name T1029
Test name
Test status
Simulation time 56227947418 ps
CPU time 767.47 seconds
Started Feb 08 06:38:40 PM UTC 25
Finished Feb 08 06:51:37 PM UTC 25
Peak memory 294580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997256355 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.997256355
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.3010834802
Short name T667
Test name
Test status
Simulation time 3034755065 ps
CPU time 14.67 seconds
Started Feb 08 06:38:26 PM UTC 25
Finished Feb 08 06:38:42 PM UTC 25
Peak memory 227572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010834802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3010834802
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3625603901
Short name T655
Test name
Test status
Simulation time 48894595 ps
CPU time 0.97 seconds
Started Feb 08 06:38:25 PM UTC 25
Finished Feb 08 06:38:27 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625603901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3625603901
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.2342311599
Short name T662
Test name
Test status
Simulation time 109713650 ps
CPU time 2.93 seconds
Started Feb 08 06:38:28 PM UTC 25
Finished Feb 08 06:38:32 PM UTC 25
Peak memory 227576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342311599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2342311599
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.941612617
Short name T660
Test name
Test status
Simulation time 30050728 ps
CPU time 1.08 seconds
Started Feb 08 06:38:28 PM UTC 25
Finished Feb 08 06:38:31 PM UTC 25
Peak memory 215960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941612617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.941612617
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.143333796
Short name T669
Test name
Test status
Simulation time 2280600406 ps
CPU time 12.05 seconds
Started Feb 08 06:38:31 PM UTC 25
Finished Feb 08 06:38:44 PM UTC 25
Peak memory 251740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143333796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.143333796
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.3515023788
Short name T414
Test name
Test status
Simulation time 43180760 ps
CPU time 1.12 seconds
Started Feb 08 06:30:22 PM UTC 25
Finished Feb 08 06:30:25 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515023788 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3515023788
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2034132029
Short name T62
Test name
Test status
Simulation time 3676004960 ps
CPU time 5.36 seconds
Started Feb 08 06:30:15 PM UTC 25
Finished Feb 08 06:30:21 PM UTC 25
Peak memory 235188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034132029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2034132029
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.2805283525
Short name T99
Test name
Test status
Simulation time 24780456 ps
CPU time 1.14 seconds
Started Feb 08 06:30:10 PM UTC 25
Finished Feb 08 06:30:12 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805283525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2805283525
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.2014672075
Short name T413
Test name
Test status
Simulation time 31820501 ps
CPU time 1.19 seconds
Started Feb 08 06:30:18 PM UTC 25
Finished Feb 08 06:30:20 PM UTC 25
Peak memory 225412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014672075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2014672075
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.1891666244
Short name T101
Test name
Test status
Simulation time 15404609325 ps
CPU time 171.06 seconds
Started Feb 08 06:30:19 PM UTC 25
Finished Feb 08 06:33:13 PM UTC 25
Peak memory 267788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891666244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1891666244
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.1981068360
Short name T211
Test name
Test status
Simulation time 6291389023 ps
CPU time 56.6 seconds
Started Feb 08 06:30:16 PM UTC 25
Finished Feb 08 06:31:14 PM UTC 25
Peak memory 251408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981068360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1981068360
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.3114547356
Short name T112
Test name
Test status
Simulation time 114827177 ps
CPU time 6.49 seconds
Started Feb 08 06:30:14 PM UTC 25
Finished Feb 08 06:30:21 PM UTC 25
Peak memory 245204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114547356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3114547356
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.3825052364
Short name T47
Test name
Test status
Simulation time 45118308 ps
CPU time 1.53 seconds
Started Feb 08 06:30:10 PM UTC 25
Finished Feb 08 06:30:13 PM UTC 25
Peak memory 229196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825052364 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_parity.3825052364
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.169255880
Short name T96
Test name
Test status
Simulation time 236453724 ps
CPU time 6.54 seconds
Started Feb 08 06:30:14 PM UTC 25
Finished Feb 08 06:30:21 PM UTC 25
Peak memory 245160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169255880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.169255880
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3468591223
Short name T59
Test name
Test status
Simulation time 1238767432 ps
CPU time 8.29 seconds
Started Feb 08 06:30:14 PM UTC 25
Finished Feb 08 06:30:23 PM UTC 25
Peak memory 234920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468591223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3468591223
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.1989095860
Short name T171
Test name
Test status
Simulation time 2229460991 ps
CPU time 13.96 seconds
Started Feb 08 06:30:17 PM UTC 25
Finished Feb 08 06:30:32 PM UTC 25
Peak memory 231352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989095860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.1989095860
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.2865828562
Short name T26
Test name
Test status
Simulation time 31781620 ps
CPU time 1.53 seconds
Started Feb 08 06:30:21 PM UTC 25
Finished Feb 08 06:30:24 PM UTC 25
Peak memory 257532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865828562 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2865828562
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.96768005
Short name T404
Test name
Test status
Simulation time 11660715651 ps
CPU time 61.93 seconds
Started Feb 08 06:30:11 PM UTC 25
Finished Feb 08 06:31:15 PM UTC 25
Peak memory 227428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96768005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.96768005
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2578540424
Short name T110
Test name
Test status
Simulation time 2027960158 ps
CPU time 9.8 seconds
Started Feb 08 06:30:11 PM UTC 25
Finished Feb 08 06:30:22 PM UTC 25
Peak memory 227256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578540424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2578540424
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1553670192
Short name T48
Test name
Test status
Simulation time 128456785 ps
CPU time 5.26 seconds
Started Feb 08 06:30:11 PM UTC 25
Finished Feb 08 06:30:18 PM UTC 25
Peak memory 227356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553670192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1553670192
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2801606153
Short name T33
Test name
Test status
Simulation time 27204143 ps
CPU time 1.29 seconds
Started Feb 08 06:30:11 PM UTC 25
Finished Feb 08 06:30:14 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801606153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2801606153
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.1793701786
Short name T58
Test name
Test status
Simulation time 1550065668 ps
CPU time 5.76 seconds
Started Feb 08 06:30:14 PM UTC 25
Finished Feb 08 06:30:21 PM UTC 25
Peak memory 235136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793701786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1793701786
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.3985932711
Short name T685
Test name
Test status
Simulation time 44516411 ps
CPU time 1.1 seconds
Started Feb 08 06:39:09 PM UTC 25
Finished Feb 08 06:39:11 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985932711 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.3985932711
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.1156092887
Short name T678
Test name
Test status
Simulation time 202761475 ps
CPU time 4.12 seconds
Started Feb 08 06:38:54 PM UTC 25
Finished Feb 08 06:38:59 PM UTC 25
Peak memory 245144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156092887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1156092887
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.2444113852
Short name T671
Test name
Test status
Simulation time 21998253 ps
CPU time 1.21 seconds
Started Feb 08 06:38:43 PM UTC 25
Finished Feb 08 06:38:45 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444113852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2444113852
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.3270835696
Short name T718
Test name
Test status
Simulation time 7674228050 ps
CPU time 51.97 seconds
Started Feb 08 06:39:06 PM UTC 25
Finished Feb 08 06:39:59 PM UTC 25
Peak memory 267760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270835696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3270835696
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.1920998710
Short name T781
Test name
Test status
Simulation time 137592985343 ps
CPU time 145.82 seconds
Started Feb 08 06:39:07 PM UTC 25
Finished Feb 08 06:41:35 PM UTC 25
Peak memory 261936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920998710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1920998710
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.1918649776
Short name T727
Test name
Test status
Simulation time 14371655579 ps
CPU time 58.47 seconds
Started Feb 08 06:39:09 PM UTC 25
Finished Feb 08 06:40:09 PM UTC 25
Peak memory 261656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918649776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.1918649776
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.3905146368
Short name T680
Test name
Test status
Simulation time 488088345 ps
CPU time 6.78 seconds
Started Feb 08 06:38:58 PM UTC 25
Finished Feb 08 06:39:06 PM UTC 25
Peak memory 234924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905146368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3905146368
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.544876867
Short name T388
Test name
Test status
Simulation time 50832768142 ps
CPU time 485.72 seconds
Started Feb 08 06:38:59 PM UTC 25
Finished Feb 08 06:47:11 PM UTC 25
Peak memory 267768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544876867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.544876867
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.3730589838
Short name T254
Test name
Test status
Simulation time 260862006 ps
CPU time 7.48 seconds
Started Feb 08 06:38:49 PM UTC 25
Finished Feb 08 06:38:58 PM UTC 25
Peak memory 234876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730589838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3730589838
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.2781658646
Short name T699
Test name
Test status
Simulation time 19341476444 ps
CPU time 44.96 seconds
Started Feb 08 06:38:51 PM UTC 25
Finished Feb 08 06:39:38 PM UTC 25
Peak memory 251352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781658646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2781658646
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1011964737
Short name T679
Test name
Test status
Simulation time 3343735540 ps
CPU time 16.16 seconds
Started Feb 08 06:38:47 PM UTC 25
Finished Feb 08 06:39:05 PM UTC 25
Peak memory 235000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011964737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.1011964737
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.372890969
Short name T720
Test name
Test status
Simulation time 133809446135 ps
CPU time 71.39 seconds
Started Feb 08 06:38:47 PM UTC 25
Finished Feb 08 06:40:01 PM UTC 25
Peak memory 261656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372890969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.372890969
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1510836628
Short name T686
Test name
Test status
Simulation time 544508499 ps
CPU time 11.46 seconds
Started Feb 08 06:39:00 PM UTC 25
Finished Feb 08 06:39:12 PM UTC 25
Peak memory 231192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510836628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.1510836628
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.2062708872
Short name T365
Test name
Test status
Simulation time 7138342845 ps
CPU time 63.87 seconds
Started Feb 08 06:39:09 PM UTC 25
Finished Feb 08 06:40:15 PM UTC 25
Peak memory 263728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062708872 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.2062708872
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.2921290277
Short name T682
Test name
Test status
Simulation time 5442628595 ps
CPU time 21.69 seconds
Started Feb 08 06:38:45 PM UTC 25
Finished Feb 08 06:39:08 PM UTC 25
Peak memory 227476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921290277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2921290277
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.225017032
Short name T672
Test name
Test status
Simulation time 39712669 ps
CPU time 1.1 seconds
Started Feb 08 06:38:44 PM UTC 25
Finished Feb 08 06:38:46 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225017032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.225017032
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.3893325257
Short name T676
Test name
Test status
Simulation time 203080296 ps
CPU time 5.66 seconds
Started Feb 08 06:38:46 PM UTC 25
Finished Feb 08 06:38:53 PM UTC 25
Peak memory 227356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893325257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3893325257
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.746481297
Short name T674
Test name
Test status
Simulation time 326852898 ps
CPU time 1.46 seconds
Started Feb 08 06:38:46 PM UTC 25
Finished Feb 08 06:38:49 PM UTC 25
Peak memory 215840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746481297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.746481297
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.2808680729
Short name T693
Test name
Test status
Simulation time 6894911157 ps
CPU time 31.4 seconds
Started Feb 08 06:38:52 PM UTC 25
Finished Feb 08 06:39:25 PM UTC 25
Peak memory 261588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808680729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2808680729
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.862400481
Short name T698
Test name
Test status
Simulation time 30586729 ps
CPU time 1.09 seconds
Started Feb 08 06:39:33 PM UTC 25
Finished Feb 08 06:39:36 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862400481 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.862400481
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.2891559694
Short name T355
Test name
Test status
Simulation time 62625087 ps
CPU time 4.59 seconds
Started Feb 08 06:39:26 PM UTC 25
Finished Feb 08 06:39:32 PM UTC 25
Peak memory 234992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891559694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2891559694
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.3898044216
Short name T687
Test name
Test status
Simulation time 19423119 ps
CPU time 1.21 seconds
Started Feb 08 06:39:10 PM UTC 25
Finished Feb 08 06:39:12 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898044216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3898044216
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.4080967998
Short name T834
Test name
Test status
Simulation time 22281514868 ps
CPU time 185.21 seconds
Started Feb 08 06:39:27 PM UTC 25
Finished Feb 08 06:42:35 PM UTC 25
Peak memory 263956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080967998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4080967998
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.2359724164
Short name T752
Test name
Test status
Simulation time 22374526651 ps
CPU time 74.39 seconds
Started Feb 08 06:39:29 PM UTC 25
Finished Feb 08 06:40:46 PM UTC 25
Peak memory 267888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359724164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2359724164
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2285853436
Short name T791
Test name
Test status
Simulation time 82843215539 ps
CPU time 129.38 seconds
Started Feb 08 06:39:32 PM UTC 25
Finished Feb 08 06:41:44 PM UTC 25
Peak memory 249516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285853436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.2285853436
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.3614917762
Short name T702
Test name
Test status
Simulation time 555367368 ps
CPU time 12.27 seconds
Started Feb 08 06:39:26 PM UTC 25
Finished Feb 08 06:39:39 PM UTC 25
Peak memory 245160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614917762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3614917762
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.361320148
Short name T738
Test name
Test status
Simulation time 19966113240 ps
CPU time 57.21 seconds
Started Feb 08 06:39:26 PM UTC 25
Finished Feb 08 06:40:25 PM UTC 25
Peak memory 251672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361320148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.361320148
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.3821450531
Short name T695
Test name
Test status
Simulation time 387234867 ps
CPU time 5.87 seconds
Started Feb 08 06:39:20 PM UTC 25
Finished Feb 08 06:39:27 PM UTC 25
Peak memory 234876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821450531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3821450531
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.2782370874
Short name T704
Test name
Test status
Simulation time 4367961882 ps
CPU time 19.45 seconds
Started Feb 08 06:39:21 PM UTC 25
Finished Feb 08 06:39:42 PM UTC 25
Peak memory 245488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782370874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2782370874
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1518935437
Short name T368
Test name
Test status
Simulation time 5652993540 ps
CPU time 11.49 seconds
Started Feb 08 06:39:20 PM UTC 25
Finished Feb 08 06:39:32 PM UTC 25
Peak memory 234940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518935437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.1518935437
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.3585799509
Short name T696
Test name
Test status
Simulation time 2701068554 ps
CPU time 9.26 seconds
Started Feb 08 06:39:18 PM UTC 25
Finished Feb 08 06:39:28 PM UTC 25
Peak memory 234928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585799509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3585799509
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.704625629
Short name T711
Test name
Test status
Simulation time 1351329029 ps
CPU time 22.07 seconds
Started Feb 08 06:39:27 PM UTC 25
Finished Feb 08 06:39:50 PM UTC 25
Peak memory 233560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704625629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.704625629
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.3832102787
Short name T1009
Test name
Test status
Simulation time 24963302340 ps
CPU time 383.71 seconds
Started Feb 08 06:39:32 PM UTC 25
Finished Feb 08 06:46:01 PM UTC 25
Peak memory 284236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832102787 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.3832102787
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.492657384
Short name T697
Test name
Test status
Simulation time 4192649614 ps
CPU time 16.36 seconds
Started Feb 08 06:39:13 PM UTC 25
Finished Feb 08 06:39:31 PM UTC 25
Peak memory 227628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492657384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.492657384
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.3589031059
Short name T691
Test name
Test status
Simulation time 3623004386 ps
CPU time 6.46 seconds
Started Feb 08 06:39:12 PM UTC 25
Finished Feb 08 06:39:20 PM UTC 25
Peak memory 227132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589031059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3589031059
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.2805500827
Short name T690
Test name
Test status
Simulation time 54108974 ps
CPU time 1.23 seconds
Started Feb 08 06:39:16 PM UTC 25
Finished Feb 08 06:39:19 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805500827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2805500827
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.724219869
Short name T688
Test name
Test status
Simulation time 107019877 ps
CPU time 1.24 seconds
Started Feb 08 06:39:13 PM UTC 25
Finished Feb 08 06:39:16 PM UTC 25
Peak memory 215500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724219869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.724219869
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.1115694784
Short name T705
Test name
Test status
Simulation time 2189577865 ps
CPU time 19.59 seconds
Started Feb 08 06:39:21 PM UTC 25
Finished Feb 08 06:39:42 PM UTC 25
Peak memory 261648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115694784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1115694784
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.488605430
Short name T719
Test name
Test status
Simulation time 13394913 ps
CPU time 1.08 seconds
Started Feb 08 06:39:58 PM UTC 25
Finished Feb 08 06:40:00 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488605430 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.488605430
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.4278443751
Short name T714
Test name
Test status
Simulation time 181056918 ps
CPU time 3.67 seconds
Started Feb 08 06:39:49 PM UTC 25
Finished Feb 08 06:39:54 PM UTC 25
Peak memory 245208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278443751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4278443751
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.542889821
Short name T701
Test name
Test status
Simulation time 16578972 ps
CPU time 1.17 seconds
Started Feb 08 06:39:36 PM UTC 25
Finished Feb 08 06:39:39 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542889821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.542889821
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.801668284
Short name T774
Test name
Test status
Simulation time 4742975713 ps
CPU time 89.78 seconds
Started Feb 08 06:39:53 PM UTC 25
Finished Feb 08 06:41:25 PM UTC 25
Peak memory 251420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801668284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.801668284
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1351641816
Short name T164
Test name
Test status
Simulation time 31952044650 ps
CPU time 94.03 seconds
Started Feb 08 06:39:54 PM UTC 25
Finished Feb 08 06:41:31 PM UTC 25
Peak memory 280364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351641816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1351641816
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.2144270990
Short name T728
Test name
Test status
Simulation time 1081941414 ps
CPU time 14 seconds
Started Feb 08 06:39:54 PM UTC 25
Finished Feb 08 06:40:10 PM UTC 25
Peak memory 234996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144270990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.2144270990
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.3176265735
Short name T725
Test name
Test status
Simulation time 401519796 ps
CPU time 16.65 seconds
Started Feb 08 06:39:49 PM UTC 25
Finished Feb 08 06:40:07 PM UTC 25
Peak memory 247248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176265735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3176265735
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.4094924777
Short name T814
Test name
Test status
Simulation time 13118789150 ps
CPU time 140.27 seconds
Started Feb 08 06:39:50 PM UTC 25
Finished Feb 08 06:42:13 PM UTC 25
Peak memory 261812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094924777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.4094924777
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.2903971879
Short name T707
Test name
Test status
Simulation time 118725251 ps
CPU time 3.35 seconds
Started Feb 08 06:39:43 PM UTC 25
Finished Feb 08 06:39:47 PM UTC 25
Peak memory 234876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903971879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2903971879
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.2118422532
Short name T760
Test name
Test status
Simulation time 27603620307 ps
CPU time 76.05 seconds
Started Feb 08 06:39:48 PM UTC 25
Finished Feb 08 06:41:06 PM UTC 25
Peak memory 245516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118422532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2118422532
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3276529581
Short name T715
Test name
Test status
Simulation time 3058113876 ps
CPU time 12.83 seconds
Started Feb 08 06:39:43 PM UTC 25
Finished Feb 08 06:39:57 PM UTC 25
Peak memory 245272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276529581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.3276529581
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.775459457
Short name T716
Test name
Test status
Simulation time 2672576031 ps
CPU time 13.36 seconds
Started Feb 08 06:39:43 PM UTC 25
Finished Feb 08 06:39:57 PM UTC 25
Peak memory 249556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775459457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.775459457
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.1887372338
Short name T717
Test name
Test status
Simulation time 136237501 ps
CPU time 6.18 seconds
Started Feb 08 06:39:51 PM UTC 25
Finished Feb 08 06:39:59 PM UTC 25
Peak memory 233516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887372338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.1887372338
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.637822763
Short name T786
Test name
Test status
Simulation time 43844809970 ps
CPU time 102.91 seconds
Started Feb 08 06:39:57 PM UTC 25
Finished Feb 08 06:41:42 PM UTC 25
Peak memory 251452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637822763 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.637822763
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.1917647490
Short name T742
Test name
Test status
Simulation time 8689539903 ps
CPU time 47.94 seconds
Started Feb 08 06:39:40 PM UTC 25
Finished Feb 08 06:40:29 PM UTC 25
Peak memory 227416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917647490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1917647490
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.1421103760
Short name T724
Test name
Test status
Simulation time 4943621115 ps
CPU time 24.29 seconds
Started Feb 08 06:39:39 PM UTC 25
Finished Feb 08 06:40:04 PM UTC 25
Peak memory 227436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421103760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1421103760
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.1442583285
Short name T710
Test name
Test status
Simulation time 152324190 ps
CPU time 7.41 seconds
Started Feb 08 06:39:41 PM UTC 25
Finished Feb 08 06:39:49 PM UTC 25
Peak memory 227676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442583285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1442583285
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2368401368
Short name T706
Test name
Test status
Simulation time 32437976 ps
CPU time 1.24 seconds
Started Feb 08 06:39:40 PM UTC 25
Finished Feb 08 06:39:42 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368401368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2368401368
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.1539144670
Short name T713
Test name
Test status
Simulation time 198819301 ps
CPU time 3.54 seconds
Started Feb 08 06:39:49 PM UTC 25
Finished Feb 08 06:39:54 PM UTC 25
Peak memory 235188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539144670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1539144670
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.1105866621
Short name T732
Test name
Test status
Simulation time 23521400 ps
CPU time 1.12 seconds
Started Feb 08 06:40:16 PM UTC 25
Finished Feb 08 06:40:18 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105866621 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.1105866621
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.4051169203
Short name T746
Test name
Test status
Simulation time 2569166821 ps
CPU time 27.14 seconds
Started Feb 08 06:40:08 PM UTC 25
Finished Feb 08 06:40:37 PM UTC 25
Peak memory 234936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051169203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4051169203
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.4056771759
Short name T721
Test name
Test status
Simulation time 59763295 ps
CPU time 1.17 seconds
Started Feb 08 06:39:59 PM UTC 25
Finished Feb 08 06:40:01 PM UTC 25
Peak memory 215956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056771759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4056771759
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2266311448
Short name T861
Test name
Test status
Simulation time 37437318295 ps
CPU time 168.09 seconds
Started Feb 08 06:40:14 PM UTC 25
Finished Feb 08 06:43:05 PM UTC 25
Peak memory 261620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266311448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2266311448
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.1353182547
Short name T367
Test name
Test status
Simulation time 58921982856 ps
CPU time 287.55 seconds
Started Feb 08 06:40:16 PM UTC 25
Finished Feb 08 06:45:07 PM UTC 25
Peak memory 267820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353182547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.1353182547
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.4289404516
Short name T734
Test name
Test status
Simulation time 306566472 ps
CPU time 9.14 seconds
Started Feb 08 06:40:09 PM UTC 25
Finished Feb 08 06:40:20 PM UTC 25
Peak memory 245424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289404516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4289404516
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.748384415
Short name T797
Test name
Test status
Simulation time 9087297370 ps
CPU time 99.61 seconds
Started Feb 08 06:40:11 PM UTC 25
Finished Feb 08 06:41:52 PM UTC 25
Peak memory 261656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748384415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.748384415
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.2466927157
Short name T731
Test name
Test status
Simulation time 237721937 ps
CPU time 9.78 seconds
Started Feb 08 06:40:04 PM UTC 25
Finished Feb 08 06:40:15 PM UTC 25
Peak memory 245404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466927157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2466927157
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.2694817889
Short name T349
Test name
Test status
Simulation time 1287077695 ps
CPU time 18.13 seconds
Started Feb 08 06:40:05 PM UTC 25
Finished Feb 08 06:40:25 PM UTC 25
Peak memory 245108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694817889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2694817889
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.3593040089
Short name T381
Test name
Test status
Simulation time 2756370678 ps
CPU time 7.82 seconds
Started Feb 08 06:40:04 PM UTC 25
Finished Feb 08 06:40:13 PM UTC 25
Peak memory 245272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593040089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.3593040089
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.515568899
Short name T726
Test name
Test status
Simulation time 1159451739 ps
CPU time 4.45 seconds
Started Feb 08 06:40:02 PM UTC 25
Finished Feb 08 06:40:08 PM UTC 25
Peak memory 235108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515568899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.515568899
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.4106073750
Short name T733
Test name
Test status
Simulation time 1500301335 ps
CPU time 7.01 seconds
Started Feb 08 06:40:11 PM UTC 25
Finished Feb 08 06:40:19 PM UTC 25
Peak memory 233332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106073750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.4106073750
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.1419046048
Short name T761
Test name
Test status
Simulation time 6922148359 ps
CPU time 48.73 seconds
Started Feb 08 06:40:16 PM UTC 25
Finished Feb 08 06:41:06 PM UTC 25
Peak memory 261716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419046048 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.1419046048
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.3439534996
Short name T758
Test name
Test status
Simulation time 7610790032 ps
CPU time 56.07 seconds
Started Feb 08 06:40:01 PM UTC 25
Finished Feb 08 06:40:59 PM UTC 25
Peak memory 227416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439534996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3439534996
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.3378730752
Short name T703
Test name
Test status
Simulation time 488401345 ps
CPU time 7.18 seconds
Started Feb 08 06:40:00 PM UTC 25
Finished Feb 08 06:40:08 PM UTC 25
Peak memory 227292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378730752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3378730752
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.552920504
Short name T722
Test name
Test status
Simulation time 19076317 ps
CPU time 1.08 seconds
Started Feb 08 06:40:01 PM UTC 25
Finished Feb 08 06:40:03 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552920504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.552920504
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.2583171687
Short name T723
Test name
Test status
Simulation time 49551443 ps
CPU time 1.38 seconds
Started Feb 08 06:40:01 PM UTC 25
Finished Feb 08 06:40:03 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583171687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2583171687
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.1375214368
Short name T741
Test name
Test status
Simulation time 2680729399 ps
CPU time 18.9 seconds
Started Feb 08 06:40:08 PM UTC 25
Finished Feb 08 06:40:29 PM UTC 25
Peak memory 251736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375214368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1375214368
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.3986743460
Short name T750
Test name
Test status
Simulation time 70641517 ps
CPU time 1.11 seconds
Started Feb 08 06:40:41 PM UTC 25
Finished Feb 08 06:40:43 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986743460 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.3986743460
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.2238631693
Short name T747
Test name
Test status
Simulation time 278471598 ps
CPU time 7.06 seconds
Started Feb 08 06:40:30 PM UTC 25
Finished Feb 08 06:40:38 PM UTC 25
Peak memory 234864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238631693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2238631693
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.3931684194
Short name T735
Test name
Test status
Simulation time 94427422 ps
CPU time 1.1 seconds
Started Feb 08 06:40:19 PM UTC 25
Finished Feb 08 06:40:21 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931684194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3931684194
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.4119763308
Short name T385
Test name
Test status
Simulation time 158487769 ps
CPU time 6.58 seconds
Started Feb 08 06:40:33 PM UTC 25
Finished Feb 08 06:40:41 PM UTC 25
Peak memory 245172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119763308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4119763308
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1734195726
Short name T766
Test name
Test status
Simulation time 19547120673 ps
CPU time 42.62 seconds
Started Feb 08 06:40:35 PM UTC 25
Finished Feb 08 06:41:19 PM UTC 25
Peak memory 247376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734195726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1734195726
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.1863967242
Short name T765
Test name
Test status
Simulation time 2415912627 ps
CPU time 37.73 seconds
Started Feb 08 06:40:38 PM UTC 25
Finished Feb 08 06:41:17 PM UTC 25
Peak memory 245300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863967242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.1863967242
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.2464527957
Short name T785
Test name
Test status
Simulation time 3464271379 ps
CPU time 69.72 seconds
Started Feb 08 06:40:30 PM UTC 25
Finished Feb 08 06:41:41 PM UTC 25
Peak memory 245236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464527957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2464527957
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3650175430
Short name T362
Test name
Test status
Simulation time 3069458994 ps
CPU time 13.86 seconds
Started Feb 08 06:40:33 PM UTC 25
Finished Feb 08 06:40:48 PM UTC 25
Peak memory 247312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650175430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.3650175430
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.577125159
Short name T745
Test name
Test status
Simulation time 230966749 ps
CPU time 7.44 seconds
Started Feb 08 06:40:25 PM UTC 25
Finished Feb 08 06:40:34 PM UTC 25
Peak memory 245184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577125159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.577125159
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.2603809081
Short name T749
Test name
Test status
Simulation time 1683830343 ps
CPU time 14.35 seconds
Started Feb 08 06:40:26 PM UTC 25
Finished Feb 08 06:40:42 PM UTC 25
Peak memory 245108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603809081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2603809081
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.513106009
Short name T253
Test name
Test status
Simulation time 495529120 ps
CPU time 5.8 seconds
Started Feb 08 06:40:25 PM UTC 25
Finished Feb 08 06:40:32 PM UTC 25
Peak memory 234876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513106009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.513106009
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1456129709
Short name T744
Test name
Test status
Simulation time 9683771203 ps
CPU time 5.76 seconds
Started Feb 08 06:40:25 PM UTC 25
Finished Feb 08 06:40:32 PM UTC 25
Peak memory 245436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456129709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1456129709
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.1082700239
Short name T748
Test name
Test status
Simulation time 162324140 ps
CPU time 6.1 seconds
Started Feb 08 06:40:33 PM UTC 25
Finished Feb 08 06:40:40 PM UTC 25
Peak memory 233736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082700239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.1082700239
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.3389000269
Short name T168
Test name
Test status
Simulation time 245255630234 ps
CPU time 389.04 seconds
Started Feb 08 06:40:39 PM UTC 25
Finished Feb 08 06:47:13 PM UTC 25
Peak memory 280116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389000269 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.3389000269
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.1890779247
Short name T755
Test name
Test status
Simulation time 6202850975 ps
CPU time 33.4 seconds
Started Feb 08 06:40:21 PM UTC 25
Finished Feb 08 06:40:56 PM UTC 25
Peak memory 227448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890779247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1890779247
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.1361936046
Short name T740
Test name
Test status
Simulation time 1397858652 ps
CPU time 5.65 seconds
Started Feb 08 06:40:20 PM UTC 25
Finished Feb 08 06:40:27 PM UTC 25
Peak memory 227296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361936046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1361936046
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.2039344703
Short name T739
Test name
Test status
Simulation time 117695492 ps
CPU time 1.72 seconds
Started Feb 08 06:40:23 PM UTC 25
Finished Feb 08 06:40:26 PM UTC 25
Peak memory 216244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039344703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2039344703
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.1906505609
Short name T737
Test name
Test status
Simulation time 23692956 ps
CPU time 1.24 seconds
Started Feb 08 06:40:22 PM UTC 25
Finished Feb 08 06:40:24 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906505609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1906505609
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.3451576433
Short name T771
Test name
Test status
Simulation time 56303813805 ps
CPU time 53.84 seconds
Started Feb 08 06:40:28 PM UTC 25
Finished Feb 08 06:41:23 PM UTC 25
Peak memory 261848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451576433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3451576433
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.655278188
Short name T769
Test name
Test status
Simulation time 40977345 ps
CPU time 1.09 seconds
Started Feb 08 06:41:19 PM UTC 25
Finished Feb 08 06:41:21 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655278188 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.655278188
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.269788944
Short name T759
Test name
Test status
Simulation time 40914511 ps
CPU time 3.42 seconds
Started Feb 08 06:41:00 PM UTC 25
Finished Feb 08 06:41:04 PM UTC 25
Peak memory 245372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269788944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.269788944
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.2404221093
Short name T751
Test name
Test status
Simulation time 144574779 ps
CPU time 1.14 seconds
Started Feb 08 06:40:41 PM UTC 25
Finished Feb 08 06:40:43 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404221093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2404221093
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.120125859
Short name T374
Test name
Test status
Simulation time 2544019763 ps
CPU time 27.06 seconds
Started Feb 08 06:41:08 PM UTC 25
Finished Feb 08 06:41:37 PM UTC 25
Peak memory 261656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120125859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.120125859
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2303189122
Short name T807
Test name
Test status
Simulation time 2645949388 ps
CPU time 54.21 seconds
Started Feb 08 06:41:10 PM UTC 25
Finished Feb 08 06:42:06 PM UTC 25
Peak memory 251436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303189122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2303189122
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1443572191
Short name T843
Test name
Test status
Simulation time 8888892055 ps
CPU time 89.18 seconds
Started Feb 08 06:41:11 PM UTC 25
Finished Feb 08 06:42:43 PM UTC 25
Peak memory 251476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443572191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.1443572191
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.2309642360
Short name T776
Test name
Test status
Simulation time 4600207174 ps
CPU time 19.32 seconds
Started Feb 08 06:41:05 PM UTC 25
Finished Feb 08 06:41:26 PM UTC 25
Peak memory 245236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309642360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2309642360
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.472295260
Short name T970
Test name
Test status
Simulation time 59691759871 ps
CPU time 243.26 seconds
Started Feb 08 06:41:07 PM UTC 25
Finished Feb 08 06:45:14 PM UTC 25
Peak memory 263924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472295260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.472295260
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.2704786226
Short name T756
Test name
Test status
Simulation time 314045552 ps
CPU time 5.27 seconds
Started Feb 08 06:40:50 PM UTC 25
Finished Feb 08 06:40:56 PM UTC 25
Peak memory 234968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704786226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2704786226
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.2471370823
Short name T787
Test name
Test status
Simulation time 5819877522 ps
CPU time 43.5 seconds
Started Feb 08 06:40:57 PM UTC 25
Finished Feb 08 06:41:42 PM UTC 25
Peak memory 249328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471370823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2471370823
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2884998299
Short name T768
Test name
Test status
Simulation time 36301935845 ps
CPU time 29.49 seconds
Started Feb 08 06:40:49 PM UTC 25
Finished Feb 08 06:41:19 PM UTC 25
Peak memory 245180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884998299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.2884998299
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3814963583
Short name T783
Test name
Test status
Simulation time 20223356598 ps
CPU time 50.18 seconds
Started Feb 08 06:40:48 PM UTC 25
Finished Feb 08 06:41:39 PM UTC 25
Peak memory 234936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814963583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3814963583
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.391256838
Short name T767
Test name
Test status
Simulation time 1186540515 ps
CPU time 11.11 seconds
Started Feb 08 06:41:07 PM UTC 25
Finished Feb 08 06:41:19 PM UTC 25
Peak memory 233300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391256838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.391256838
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.2973113038
Short name T342
Test name
Test status
Simulation time 7475214749 ps
CPU time 92.85 seconds
Started Feb 08 06:41:17 PM UTC 25
Finished Feb 08 06:42:52 PM UTC 25
Peak memory 261676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973113038 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.2973113038
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.3431782626
Short name T764
Test name
Test status
Simulation time 2942372194 ps
CPU time 30.88 seconds
Started Feb 08 06:40:44 PM UTC 25
Finished Feb 08 06:41:17 PM UTC 25
Peak memory 227416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431782626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3431782626
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3297680827
Short name T763
Test name
Test status
Simulation time 25825714729 ps
CPU time 24.39 seconds
Started Feb 08 06:40:43 PM UTC 25
Finished Feb 08 06:41:09 PM UTC 25
Peak memory 227608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297680827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3297680827
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.4139534446
Short name T754
Test name
Test status
Simulation time 97569035 ps
CPU time 1.11 seconds
Started Feb 08 06:40:46 PM UTC 25
Finished Feb 08 06:40:49 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139534446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4139534446
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.4201396685
Short name T753
Test name
Test status
Simulation time 21462055 ps
CPU time 1.19 seconds
Started Feb 08 06:40:44 PM UTC 25
Finished Feb 08 06:40:47 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201396685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4201396685
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.3308462428
Short name T762
Test name
Test status
Simulation time 5743767373 ps
CPU time 9.85 seconds
Started Feb 08 06:40:57 PM UTC 25
Finished Feb 08 06:41:08 PM UTC 25
Peak memory 235284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308462428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3308462428
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.1910461965
Short name T788
Test name
Test status
Simulation time 35336729 ps
CPU time 1.05 seconds
Started Feb 08 06:41:40 PM UTC 25
Finished Feb 08 06:41:42 PM UTC 25
Peak memory 215772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910461965 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.1910461965
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.775086160
Short name T777
Test name
Test status
Simulation time 58699490 ps
CPU time 3.22 seconds
Started Feb 08 06:41:26 PM UTC 25
Finished Feb 08 06:41:31 PM UTC 25
Peak memory 244796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775086160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.775086160
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.2783690275
Short name T770
Test name
Test status
Simulation time 34313401 ps
CPU time 1.11 seconds
Started Feb 08 06:41:20 PM UTC 25
Finished Feb 08 06:41:22 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783690275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2783690275
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.3126104363
Short name T826
Test name
Test status
Simulation time 15599056971 ps
CPU time 49.61 seconds
Started Feb 08 06:41:34 PM UTC 25
Finished Feb 08 06:42:26 PM UTC 25
Peak memory 247580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126104363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3126104363
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.910233080
Short name T848
Test name
Test status
Simulation time 29997049033 ps
CPU time 75.54 seconds
Started Feb 08 06:41:36 PM UTC 25
Finished Feb 08 06:42:53 PM UTC 25
Peak memory 266036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910233080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.910233080
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.4214246549
Short name T372
Test name
Test status
Simulation time 61364615243 ps
CPU time 165.76 seconds
Started Feb 08 06:41:37 PM UTC 25
Finished Feb 08 06:44:25 PM UTC 25
Peak memory 245612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214246549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.4214246549
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.321299649
Short name T800
Test name
Test status
Simulation time 1608473520 ps
CPU time 22.13 seconds
Started Feb 08 06:41:31 PM UTC 25
Finished Feb 08 06:41:55 PM UTC 25
Peak memory 251348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321299649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.321299649
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.3291757454
Short name T779
Test name
Test status
Simulation time 29639426 ps
CPU time 1.31 seconds
Started Feb 08 06:41:31 PM UTC 25
Finished Feb 08 06:41:34 PM UTC 25
Peak memory 225468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291757454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.3291757454
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.578600689
Short name T780
Test name
Test status
Simulation time 293107063 ps
CPU time 8.78 seconds
Started Feb 08 06:41:25 PM UTC 25
Finished Feb 08 06:41:35 PM UTC 25
Peak memory 234884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578600689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.578600689
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.2768298264
Short name T806
Test name
Test status
Simulation time 1908447039 ps
CPU time 33.19 seconds
Started Feb 08 06:41:26 PM UTC 25
Finished Feb 08 06:42:01 PM UTC 25
Peak memory 261524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768298264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2768298264
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.1432569387
Short name T782
Test name
Test status
Simulation time 2652294334 ps
CPU time 12.61 seconds
Started Feb 08 06:41:25 PM UTC 25
Finished Feb 08 06:41:39 PM UTC 25
Peak memory 245272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432569387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.1432569387
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.3866642107
Short name T796
Test name
Test status
Simulation time 16603133451 ps
CPU time 26.61 seconds
Started Feb 08 06:41:24 PM UTC 25
Finished Feb 08 06:41:52 PM UTC 25
Peak memory 245524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866642107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3866642107
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.3865976567
Short name T784
Test name
Test status
Simulation time 227495000 ps
CPU time 5.83 seconds
Started Feb 08 06:41:32 PM UTC 25
Finished Feb 08 06:41:39 PM UTC 25
Peak memory 231252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865976567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.3865976567
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.2015941522
Short name T187
Test name
Test status
Simulation time 2212556674 ps
CPU time 40.46 seconds
Started Feb 08 06:41:38 PM UTC 25
Finished Feb 08 06:42:20 PM UTC 25
Peak memory 261968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015941522 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.2015941522
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.1738050313
Short name T794
Test name
Test status
Simulation time 5700842582 ps
CPU time 27.81 seconds
Started Feb 08 06:41:21 PM UTC 25
Finished Feb 08 06:41:50 PM UTC 25
Peak memory 227392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738050313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1738050313
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.3036543504
Short name T772
Test name
Test status
Simulation time 467088723 ps
CPU time 2.08 seconds
Started Feb 08 06:41:21 PM UTC 25
Finished Feb 08 06:41:24 PM UTC 25
Peak memory 216824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036543504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3036543504
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.4156318001
Short name T775
Test name
Test status
Simulation time 83500468 ps
CPU time 1.51 seconds
Started Feb 08 06:41:23 PM UTC 25
Finished Feb 08 06:41:25 PM UTC 25
Peak memory 216304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156318001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4156318001
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.3459708009
Short name T773
Test name
Test status
Simulation time 15240155 ps
CPU time 1.15 seconds
Started Feb 08 06:41:22 PM UTC 25
Finished Feb 08 06:41:24 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459708009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3459708009
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.544925053
Short name T778
Test name
Test status
Simulation time 115554286 ps
CPU time 4.08 seconds
Started Feb 08 06:41:26 PM UTC 25
Finished Feb 08 06:41:31 PM UTC 25
Peak memory 245120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544925053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.544925053
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.194575864
Short name T802
Test name
Test status
Simulation time 13420141 ps
CPU time 1.11 seconds
Started Feb 08 06:41:54 PM UTC 25
Finished Feb 08 06:41:57 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194575864 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.194575864
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.65484266
Short name T798
Test name
Test status
Simulation time 241185198 ps
CPU time 5.8 seconds
Started Feb 08 06:41:45 PM UTC 25
Finished Feb 08 06:41:53 PM UTC 25
Peak memory 245116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65484266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.65484266
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.3876504937
Short name T789
Test name
Test status
Simulation time 26620243 ps
CPU time 1.14 seconds
Started Feb 08 06:41:40 PM UTC 25
Finished Feb 08 06:41:42 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876504937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3876504937
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.686689813
Short name T878
Test name
Test status
Simulation time 19347288514 ps
CPU time 89.17 seconds
Started Feb 08 06:41:51 PM UTC 25
Finished Feb 08 06:43:23 PM UTC 25
Peak memory 261692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686689813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.686689813
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.4281555576
Short name T334
Test name
Test status
Simulation time 11246357357 ps
CPU time 42.77 seconds
Started Feb 08 06:41:51 PM UTC 25
Finished Feb 08 06:42:36 PM UTC 25
Peak memory 251440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281555576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4281555576
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1061717878
Short name T845
Test name
Test status
Simulation time 17961431163 ps
CPU time 53.02 seconds
Started Feb 08 06:41:53 PM UTC 25
Finished Feb 08 06:42:48 PM UTC 25
Peak memory 261616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061717878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.1061717878
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.2249167214
Short name T816
Test name
Test status
Simulation time 3682337831 ps
CPU time 28.42 seconds
Started Feb 08 06:41:46 PM UTC 25
Finished Feb 08 06:42:17 PM UTC 25
Peak memory 245228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249167214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2249167214
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3577295788
Short name T363
Test name
Test status
Simulation time 43948104566 ps
CPU time 362.5 seconds
Started Feb 08 06:41:48 PM UTC 25
Finished Feb 08 06:47:55 PM UTC 25
Peak memory 267800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577295788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.3577295788
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.863138635
Short name T281
Test name
Test status
Simulation time 493818733 ps
CPU time 11.33 seconds
Started Feb 08 06:41:44 PM UTC 25
Finished Feb 08 06:41:57 PM UTC 25
Peak memory 245220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863138635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.863138635
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.1344365433
Short name T799
Test name
Test status
Simulation time 1599274995 ps
CPU time 7.43 seconds
Started Feb 08 06:41:45 PM UTC 25
Finished Feb 08 06:41:54 PM UTC 25
Peak memory 235124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344365433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1344365433
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.195907460
Short name T793
Test name
Test status
Simulation time 85195941 ps
CPU time 3.47 seconds
Started Feb 08 06:41:43 PM UTC 25
Finished Feb 08 06:41:48 PM UTC 25
Peak memory 245148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195907460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.195907460
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.2993203755
Short name T825
Test name
Test status
Simulation time 28845046290 ps
CPU time 38.93 seconds
Started Feb 08 06:41:43 PM UTC 25
Finished Feb 08 06:42:24 PM UTC 25
Peak memory 245344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993203755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2993203755
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1076334208
Short name T801
Test name
Test status
Simulation time 223686417 ps
CPU time 4.97 seconds
Started Feb 08 06:41:49 PM UTC 25
Finished Feb 08 06:41:55 PM UTC 25
Peak memory 231320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076334208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1076334208
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.1653012531
Short name T880
Test name
Test status
Simulation time 18974925138 ps
CPU time 89.23 seconds
Started Feb 08 06:41:53 PM UTC 25
Finished Feb 08 06:43:24 PM UTC 25
Peak memory 261836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653012531 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.1653012531
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.2063426631
Short name T811
Test name
Test status
Simulation time 15954131367 ps
CPU time 27.2 seconds
Started Feb 08 06:41:42 PM UTC 25
Finished Feb 08 06:42:11 PM UTC 25
Peak memory 227268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063426631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2063426631
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.787262851
Short name T790
Test name
Test status
Simulation time 165675590 ps
CPU time 2 seconds
Started Feb 08 06:41:40 PM UTC 25
Finished Feb 08 06:41:43 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787262851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.787262851
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.2681864320
Short name T757
Test name
Test status
Simulation time 124241109 ps
CPU time 1.42 seconds
Started Feb 08 06:41:43 PM UTC 25
Finished Feb 08 06:41:46 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681864320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2681864320
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2958449721
Short name T792
Test name
Test status
Simulation time 187026507 ps
CPU time 1.32 seconds
Started Feb 08 06:41:42 PM UTC 25
Finished Feb 08 06:41:44 PM UTC 25
Peak memory 215660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958449721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2958449721
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.3983050311
Short name T795
Test name
Test status
Simulation time 650760142 ps
CPU time 3.23 seconds
Started Feb 08 06:41:45 PM UTC 25
Finished Feb 08 06:41:50 PM UTC 25
Peak memory 235068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983050311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3983050311
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/37.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.562429568
Short name T818
Test name
Test status
Simulation time 18084491 ps
CPU time 1.09 seconds
Started Feb 08 06:42:14 PM UTC 25
Finished Feb 08 06:42:17 PM UTC 25
Peak memory 215612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562429568 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.562429568
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2713230478
Short name T812
Test name
Test status
Simulation time 149355952 ps
CPU time 3.75 seconds
Started Feb 08 06:42:07 PM UTC 25
Finished Feb 08 06:42:12 PM UTC 25
Peak memory 245192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713230478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2713230478
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.1440527293
Short name T803
Test name
Test status
Simulation time 20681225 ps
CPU time 0.91 seconds
Started Feb 08 06:41:55 PM UTC 25
Finished Feb 08 06:41:57 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440527293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1440527293
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.140016292
Short name T239
Test name
Test status
Simulation time 21561181451 ps
CPU time 119.75 seconds
Started Feb 08 06:42:11 PM UTC 25
Finished Feb 08 06:44:13 PM UTC 25
Peak memory 263932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140016292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.140016292
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3843215890
Short name T881
Test name
Test status
Simulation time 3832811698 ps
CPU time 72.89 seconds
Started Feb 08 06:42:11 PM UTC 25
Finished Feb 08 06:43:26 PM UTC 25
Peak memory 261676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843215890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3843215890
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3328086882
Short name T882
Test name
Test status
Simulation time 12461696421 ps
CPU time 74.75 seconds
Started Feb 08 06:42:12 PM UTC 25
Finished Feb 08 06:43:29 PM UTC 25
Peak memory 266092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328086882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.3328086882
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.474397222
Short name T858
Test name
Test status
Simulation time 34555356916 ps
CPU time 50.92 seconds
Started Feb 08 06:42:09 PM UTC 25
Finished Feb 08 06:43:02 PM UTC 25
Peak memory 235188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474397222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.474397222
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.1437055711
Short name T809
Test name
Test status
Simulation time 1995177782 ps
CPU time 7.76 seconds
Started Feb 08 06:42:00 PM UTC 25
Finished Feb 08 06:42:09 PM UTC 25
Peak memory 245144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437055711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1437055711
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.1419748208
Short name T827
Test name
Test status
Simulation time 1546773890 ps
CPU time 23.34 seconds
Started Feb 08 06:42:02 PM UTC 25
Finished Feb 08 06:42:26 PM UTC 25
Peak memory 235280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419748208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1419748208
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.1603510779
Short name T830
Test name
Test status
Simulation time 2225375012 ps
CPU time 29.34 seconds
Started Feb 08 06:41:58 PM UTC 25
Finished Feb 08 06:42:29 PM UTC 25
Peak memory 251580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603510779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.1603510779
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.73006084
Short name T265
Test name
Test status
Simulation time 848744380 ps
CPU time 6.54 seconds
Started Feb 08 06:41:58 PM UTC 25
Finished Feb 08 06:42:06 PM UTC 25
Peak memory 234932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73006084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.73006084
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.1297612386
Short name T822
Test name
Test status
Simulation time 1671087554 ps
CPU time 8.91 seconds
Started Feb 08 06:42:10 PM UTC 25
Finished Feb 08 06:42:20 PM UTC 25
Peak memory 233300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297612386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.1297612386
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.439932628
Short name T79
Test name
Test status
Simulation time 64960974262 ps
CPU time 613.47 seconds
Started Feb 08 06:42:13 PM UTC 25
Finished Feb 08 06:52:35 PM UTC 25
Peak memory 294500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439932628 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.439932628
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1286061339
Short name T829
Test name
Test status
Simulation time 18260131890 ps
CPU time 30.4 seconds
Started Feb 08 06:41:56 PM UTC 25
Finished Feb 08 06:42:28 PM UTC 25
Peak memory 227500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286061339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1286061339
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.3043077170
Short name T815
Test name
Test status
Simulation time 12830901024 ps
CPU time 18.4 seconds
Started Feb 08 06:41:56 PM UTC 25
Finished Feb 08 06:42:16 PM UTC 25
Peak memory 229412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043077170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3043077170
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.627537202
Short name T805
Test name
Test status
Simulation time 51553202 ps
CPU time 1.62 seconds
Started Feb 08 06:41:57 PM UTC 25
Finished Feb 08 06:42:00 PM UTC 25
Peak memory 216252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627537202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.627537202
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2658516847
Short name T804
Test name
Test status
Simulation time 209273376 ps
CPU time 1.4 seconds
Started Feb 08 06:41:57 PM UTC 25
Finished Feb 08 06:42:00 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658516847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2658516847
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.473530237
Short name T808
Test name
Test status
Simulation time 1047729033 ps
CPU time 5.32 seconds
Started Feb 08 06:42:02 PM UTC 25
Finished Feb 08 06:42:08 PM UTC 25
Peak memory 247456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473530237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.473530237
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/38.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.2176502231
Short name T832
Test name
Test status
Simulation time 36176403 ps
CPU time 1.09 seconds
Started Feb 08 06:42:30 PM UTC 25
Finished Feb 08 06:42:32 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176502231 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.2176502231
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.1991697336
Short name T840
Test name
Test status
Simulation time 5099475711 ps
CPU time 16.56 seconds
Started Feb 08 06:42:21 PM UTC 25
Finished Feb 08 06:42:39 PM UTC 25
Peak memory 245208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991697336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1991697336
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.438314572
Short name T817
Test name
Test status
Simulation time 141871608 ps
CPU time 1.17 seconds
Started Feb 08 06:42:15 PM UTC 25
Finished Feb 08 06:42:17 PM UTC 25
Peak memory 215688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438314572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.438314572
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.2731309907
Short name T373
Test name
Test status
Simulation time 250021598148 ps
CPU time 313.83 seconds
Started Feb 08 06:42:26 PM UTC 25
Finished Feb 08 06:47:44 PM UTC 25
Peak memory 275952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731309907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2731309907
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.4116403065
Short name T963
Test name
Test status
Simulation time 13381491828 ps
CPU time 158.69 seconds
Started Feb 08 06:42:28 PM UTC 25
Finished Feb 08 06:45:09 PM UTC 25
Peak memory 266036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116403065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.4116403065
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.2103192811
Short name T837
Test name
Test status
Simulation time 184130955 ps
CPU time 12.34 seconds
Started Feb 08 06:42:23 PM UTC 25
Finished Feb 08 06:42:37 PM UTC 25
Peak memory 251344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103192811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2103192811
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1551476436
Short name T889
Test name
Test status
Simulation time 19427735240 ps
CPU time 71.28 seconds
Started Feb 08 06:42:24 PM UTC 25
Finished Feb 08 06:43:37 PM UTC 25
Peak memory 251380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551476436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.1551476436
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.1953911076
Short name T831
Test name
Test status
Simulation time 442718859 ps
CPU time 8.21 seconds
Started Feb 08 06:42:21 PM UTC 25
Finished Feb 08 06:42:30 PM UTC 25
Peak memory 245304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953911076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1953911076
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.3981008708
Short name T873
Test name
Test status
Simulation time 8916852386 ps
CPU time 51.64 seconds
Started Feb 08 06:42:21 PM UTC 25
Finished Feb 08 06:43:14 PM UTC 25
Peak memory 234992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981008708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3981008708
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2354875685
Short name T386
Test name
Test status
Simulation time 24019914514 ps
CPU time 21.91 seconds
Started Feb 08 06:42:21 PM UTC 25
Finished Feb 08 06:42:44 PM UTC 25
Peak memory 245008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354875685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.2354875685
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.2359379473
Short name T857
Test name
Test status
Simulation time 8304939020 ps
CPU time 39.89 seconds
Started Feb 08 06:42:19 PM UTC 25
Finished Feb 08 06:43:00 PM UTC 25
Peak memory 261656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359379473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2359379473
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.1308221358
Short name T835
Test name
Test status
Simulation time 964621838 ps
CPU time 10.04 seconds
Started Feb 08 06:42:24 PM UTC 25
Finished Feb 08 06:42:36 PM UTC 25
Peak memory 233788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308221358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.1308221358
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2521601890
Short name T1026
Test name
Test status
Simulation time 163150819622 ps
CPU time 368.03 seconds
Started Feb 08 06:42:29 PM UTC 25
Finished Feb 08 06:48:41 PM UTC 25
Peak memory 261676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521601890 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.2521601890
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1592634628
Short name T842
Test name
Test status
Simulation time 5563513451 ps
CPU time 23.16 seconds
Started Feb 08 06:42:18 PM UTC 25
Finished Feb 08 06:42:42 PM UTC 25
Peak memory 227416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592634628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1592634628
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.96679855
Short name T823
Test name
Test status
Simulation time 755981827 ps
CPU time 4.94 seconds
Started Feb 08 06:42:17 PM UTC 25
Finished Feb 08 06:42:23 PM UTC 25
Peak memory 227276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96679855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.96679855
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.3520144087
Short name T821
Test name
Test status
Simulation time 43678974 ps
CPU time 1.38 seconds
Started Feb 08 06:42:18 PM UTC 25
Finished Feb 08 06:42:20 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520144087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3520144087
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2273494336
Short name T820
Test name
Test status
Simulation time 20360076 ps
CPU time 1.14 seconds
Started Feb 08 06:42:18 PM UTC 25
Finished Feb 08 06:42:20 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273494336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2273494336
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.496535748
Short name T828
Test name
Test status
Simulation time 211485337 ps
CPU time 4.37 seconds
Started Feb 08 06:42:21 PM UTC 25
Finished Feb 08 06:42:27 PM UTC 25
Peak memory 235200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496535748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.496535748
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.2013954659
Short name T417
Test name
Test status
Simulation time 11695315 ps
CPU time 0.99 seconds
Started Feb 08 06:30:37 PM UTC 25
Finished Feb 08 06:30:39 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013954659 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2013954659
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2882805037
Short name T226
Test name
Test status
Simulation time 376563900 ps
CPU time 6.07 seconds
Started Feb 08 06:30:28 PM UTC 25
Finished Feb 08 06:30:36 PM UTC 25
Peak memory 245136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882805037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2882805037
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.463452698
Short name T415
Test name
Test status
Simulation time 52367655 ps
CPU time 1.14 seconds
Started Feb 08 06:30:22 PM UTC 25
Finished Feb 08 06:30:25 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463452698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.463452698
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.1351587765
Short name T208
Test name
Test status
Simulation time 101709158867 ps
CPU time 143.19 seconds
Started Feb 08 06:30:32 PM UTC 25
Finished Feb 08 06:32:58 PM UTC 25
Peak memory 261656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351587765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1351587765
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.725333938
Short name T172
Test name
Test status
Simulation time 1070909400 ps
CPU time 8.99 seconds
Started Feb 08 06:30:28 PM UTC 25
Finished Feb 08 06:30:39 PM UTC 25
Peak memory 247312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725333938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.725333938
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1277650943
Short name T69
Test name
Test status
Simulation time 28317907994 ps
CPU time 121.48 seconds
Started Feb 08 06:30:30 PM UTC 25
Finished Feb 08 06:32:34 PM UTC 25
Peak memory 263932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277650943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.1277650943
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.886241662
Short name T209
Test name
Test status
Simulation time 69421817 ps
CPU time 4.88 seconds
Started Feb 08 06:30:26 PM UTC 25
Finished Feb 08 06:30:32 PM UTC 25
Peak memory 245272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886241662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.886241662
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.3664771878
Short name T282
Test name
Test status
Simulation time 26916552033 ps
CPU time 78.75 seconds
Started Feb 08 06:30:26 PM UTC 25
Finished Feb 08 06:31:47 PM UTC 25
Peak memory 245164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664771878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3664771878
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.230839928
Short name T416
Test name
Test status
Simulation time 32663440 ps
CPU time 1.66 seconds
Started Feb 08 06:30:22 PM UTC 25
Finished Feb 08 06:30:25 PM UTC 25
Peak memory 229192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230839928 -assert nopostproc
+UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_parity.230839928
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3043032957
Short name T267
Test name
Test status
Simulation time 20117457796 ps
CPU time 25.95 seconds
Started Feb 08 06:30:26 PM UTC 25
Finished Feb 08 06:30:53 PM UTC 25
Peak memory 245368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043032957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.3043032957
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.4263004215
Short name T201
Test name
Test status
Simulation time 1646976602 ps
CPU time 9.1 seconds
Started Feb 08 06:30:26 PM UTC 25
Finished Feb 08 06:30:36 PM UTC 25
Peak memory 245104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263004215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4263004215
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.4107046596
Short name T173
Test name
Test status
Simulation time 380925202 ps
CPU time 6.52 seconds
Started Feb 08 06:30:31 PM UTC 25
Finished Feb 08 06:30:39 PM UTC 25
Peak memory 231352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107046596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.4107046596
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.3868422506
Short name T36
Test name
Test status
Simulation time 80013229 ps
CPU time 1.57 seconds
Started Feb 08 06:30:37 PM UTC 25
Finished Feb 08 06:30:41 PM UTC 25
Peak memory 257532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868422506 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3868422506
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.970436257
Short name T35
Test name
Test status
Simulation time 72394002 ps
CPU time 1.38 seconds
Started Feb 08 06:30:36 PM UTC 25
Finished Feb 08 06:30:38 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970436257 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.970436257
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.2036109275
Short name T401
Test name
Test status
Simulation time 3966379719 ps
CPU time 15.12 seconds
Started Feb 08 06:30:24 PM UTC 25
Finished Feb 08 06:30:40 PM UTC 25
Peak memory 227600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036109275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2036109275
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2563729582
Short name T420
Test name
Test status
Simulation time 10390041759 ps
CPU time 16.05 seconds
Started Feb 08 06:30:24 PM UTC 25
Finished Feb 08 06:30:41 PM UTC 25
Peak memory 227448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563729582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2563729582
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.2295472724
Short name T73
Test name
Test status
Simulation time 192545475 ps
CPU time 1.55 seconds
Started Feb 08 06:30:25 PM UTC 25
Finished Feb 08 06:30:27 PM UTC 25
Peak memory 215492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295472724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2295472724
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.131894136
Short name T111
Test name
Test status
Simulation time 59216010 ps
CPU time 1.51 seconds
Started Feb 08 06:30:25 PM UTC 25
Finished Feb 08 06:30:27 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131894136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.131894136
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.4050572247
Short name T67
Test name
Test status
Simulation time 5952716542 ps
CPU time 31.39 seconds
Started Feb 08 06:30:27 PM UTC 25
Finished Feb 08 06:31:00 PM UTC 25
Peak memory 245216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050572247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4050572247
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.4159052202
Short name T849
Test name
Test status
Simulation time 24415275 ps
CPU time 1.11 seconds
Started Feb 08 06:42:51 PM UTC 25
Finished Feb 08 06:42:53 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159052202 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.4159052202
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.737334788
Short name T844
Test name
Test status
Simulation time 130518942 ps
CPU time 3.32 seconds
Started Feb 08 06:42:40 PM UTC 25
Finished Feb 08 06:42:45 PM UTC 25
Peak memory 245372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737334788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.737334788
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.3469822502
Short name T833
Test name
Test status
Simulation time 16576653 ps
CPU time 1.19 seconds
Started Feb 08 06:42:31 PM UTC 25
Finished Feb 08 06:42:33 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469822502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3469822502
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.2560219713
Short name T860
Test name
Test status
Simulation time 2497035254 ps
CPU time 18.55 seconds
Started Feb 08 06:42:45 PM UTC 25
Finished Feb 08 06:43:04 PM UTC 25
Peak memory 249368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560219713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2560219713
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1289690604
Short name T387
Test name
Test status
Simulation time 42413386079 ps
CPU time 166.51 seconds
Started Feb 08 06:42:46 PM UTC 25
Finished Feb 08 06:45:35 PM UTC 25
Peak memory 251472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289690604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1289690604
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2834372284
Short name T1023
Test name
Test status
Simulation time 92587584965 ps
CPU time 284.39 seconds
Started Feb 08 06:42:49 PM UTC 25
Finished Feb 08 06:47:37 PM UTC 25
Peak memory 265776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834372284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.2834372284
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.2099608214
Short name T850
Test name
Test status
Simulation time 636818857 ps
CPU time 9.96 seconds
Started Feb 08 06:42:42 PM UTC 25
Finished Feb 08 06:42:54 PM UTC 25
Peak memory 245168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099608214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2099608214
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1841572134
Short name T258
Test name
Test status
Simulation time 596174880 ps
CPU time 13.42 seconds
Started Feb 08 06:42:44 PM UTC 25
Finished Feb 08 06:42:58 PM UTC 25
Peak memory 245492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841572134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.1841572134
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.3023071849
Short name T852
Test name
Test status
Simulation time 5408331798 ps
CPU time 17.75 seconds
Started Feb 08 06:42:37 PM UTC 25
Finished Feb 08 06:42:56 PM UTC 25
Peak memory 245272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023071849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3023071849
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.4164141093
Short name T865
Test name
Test status
Simulation time 14413916988 ps
CPU time 27.32 seconds
Started Feb 08 06:42:39 PM UTC 25
Finished Feb 08 06:43:08 PM UTC 25
Peak memory 245460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164141093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4164141093
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.3394221266
Short name T855
Test name
Test status
Simulation time 12958273467 ps
CPU time 19.86 seconds
Started Feb 08 06:42:37 PM UTC 25
Finished Feb 08 06:42:59 PM UTC 25
Peak memory 245240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394221266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.3394221266
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2310405118
Short name T841
Test name
Test status
Simulation time 31280360 ps
CPU time 2.84 seconds
Started Feb 08 06:42:37 PM UTC 25
Finished Feb 08 06:42:41 PM UTC 25
Peak memory 234536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310405118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2310405118
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2009538176
Short name T847
Test name
Test status
Simulation time 636631930 ps
CPU time 7.74 seconds
Started Feb 08 06:42:44 PM UTC 25
Finished Feb 08 06:42:52 PM UTC 25
Peak memory 233332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009538176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.2009538176
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.3869109627
Short name T925
Test name
Test status
Simulation time 40853670278 ps
CPU time 85.54 seconds
Started Feb 08 06:42:50 PM UTC 25
Finished Feb 08 06:44:17 PM UTC 25
Peak memory 265808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869109627 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.3869109627
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.3320061148
Short name T856
Test name
Test status
Simulation time 3289785570 ps
CPU time 25.06 seconds
Started Feb 08 06:42:34 PM UTC 25
Finished Feb 08 06:43:00 PM UTC 25
Peak memory 227448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320061148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3320061148
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.284092711
Short name T836
Test name
Test status
Simulation time 223312589 ps
CPU time 2.33 seconds
Started Feb 08 06:42:33 PM UTC 25
Finished Feb 08 06:42:36 PM UTC 25
Peak memory 216792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284092711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.284092711
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.1214713632
Short name T838
Test name
Test status
Simulation time 27524208 ps
CPU time 1.06 seconds
Started Feb 08 06:42:36 PM UTC 25
Finished Feb 08 06:42:38 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214713632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1214713632
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.90262767
Short name T839
Test name
Test status
Simulation time 35513865 ps
CPU time 1.26 seconds
Started Feb 08 06:42:36 PM UTC 25
Finished Feb 08 06:42:38 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90262767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.90262767
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.658310046
Short name T846
Test name
Test status
Simulation time 1493596557 ps
CPU time 9.96 seconds
Started Feb 08 06:42:39 PM UTC 25
Finished Feb 08 06:42:51 PM UTC 25
Peak memory 245124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658310046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.658310046
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.2301055098
Short name T866
Test name
Test status
Simulation time 42039370 ps
CPU time 1.14 seconds
Started Feb 08 06:43:07 PM UTC 25
Finished Feb 08 06:43:09 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301055098 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.2301055098
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2825174019
Short name T867
Test name
Test status
Simulation time 2590251274 ps
CPU time 10.14 seconds
Started Feb 08 06:43:00 PM UTC 25
Finished Feb 08 06:43:11 PM UTC 25
Peak memory 245464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825174019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2825174019
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.3072105760
Short name T851
Test name
Test status
Simulation time 24226627 ps
CPU time 1.18 seconds
Started Feb 08 06:42:53 PM UTC 25
Finished Feb 08 06:42:55 PM UTC 25
Peak memory 215660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072105760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3072105760
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2123718302
Short name T1022
Test name
Test status
Simulation time 23248372947 ps
CPU time 258.71 seconds
Started Feb 08 06:43:05 PM UTC 25
Finished Feb 08 06:47:27 PM UTC 25
Peak memory 265808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123718302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2123718302
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.467768050
Short name T863
Test name
Test status
Simulation time 259717610 ps
CPU time 4.62 seconds
Started Feb 08 06:43:01 PM UTC 25
Finished Feb 08 06:43:06 PM UTC 25
Peak memory 234928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467768050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.467768050
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3885296433
Short name T969
Test name
Test status
Simulation time 11851573741 ps
CPU time 129.43 seconds
Started Feb 08 06:43:02 PM UTC 25
Finished Feb 08 06:45:14 PM UTC 25
Peak memory 261844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885296433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.3885296433
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.3635903974
Short name T859
Test name
Test status
Simulation time 184632916 ps
CPU time 3.26 seconds
Started Feb 08 06:42:57 PM UTC 25
Finished Feb 08 06:43:02 PM UTC 25
Peak memory 244828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635903974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3635903974
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.4289139538
Short name T875
Test name
Test status
Simulation time 4588425340 ps
CPU time 16.58 seconds
Started Feb 08 06:42:57 PM UTC 25
Finished Feb 08 06:43:15 PM UTC 25
Peak memory 247280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289139538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4289139538
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1115730737
Short name T903
Test name
Test status
Simulation time 8282864627 ps
CPU time 48.85 seconds
Started Feb 08 06:42:57 PM UTC 25
Finished Feb 08 06:43:48 PM UTC 25
Peak memory 245180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115730737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.1115730737
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.3247797484
Short name T891
Test name
Test status
Simulation time 30409887646 ps
CPU time 41.29 seconds
Started Feb 08 06:42:56 PM UTC 25
Finished Feb 08 06:43:39 PM UTC 25
Peak memory 251580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247797484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3247797484
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3767049961
Short name T871
Test name
Test status
Simulation time 2596201718 ps
CPU time 8.38 seconds
Started Feb 08 06:43:03 PM UTC 25
Finished Feb 08 06:43:12 PM UTC 25
Peak memory 231256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767049961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.3767049961
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.1188924270
Short name T371
Test name
Test status
Simulation time 97974191501 ps
CPU time 988.62 seconds
Started Feb 08 06:43:06 PM UTC 25
Finished Feb 08 06:59:46 PM UTC 25
Peak memory 278320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188924270 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.1188924270
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.2335429414
Short name T870
Test name
Test status
Simulation time 4205504235 ps
CPU time 16.28 seconds
Started Feb 08 06:42:54 PM UTC 25
Finished Feb 08 06:43:12 PM UTC 25
Peak memory 227700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335429414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2335429414
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.673534062
Short name T862
Test name
Test status
Simulation time 1356053385 ps
CPU time 10.9 seconds
Started Feb 08 06:42:53 PM UTC 25
Finished Feb 08 06:43:05 PM UTC 25
Peak memory 227264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673534062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.673534062
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.272060239
Short name T853
Test name
Test status
Simulation time 16178120 ps
CPU time 1.18 seconds
Started Feb 08 06:42:54 PM UTC 25
Finished Feb 08 06:42:57 PM UTC 25
Peak memory 215904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272060239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.272060239
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.498137551
Short name T854
Test name
Test status
Simulation time 65400882 ps
CPU time 1.43 seconds
Started Feb 08 06:42:54 PM UTC 25
Finished Feb 08 06:42:57 PM UTC 25
Peak memory 215840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498137551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.498137551
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.3361357428
Short name T868
Test name
Test status
Simulation time 622565389 ps
CPU time 11.5 seconds
Started Feb 08 06:42:59 PM UTC 25
Finished Feb 08 06:43:11 PM UTC 25
Peak memory 245404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361357428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3361357428
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.2694035608
Short name T883
Test name
Test status
Simulation time 13382356 ps
CPU time 0.99 seconds
Started Feb 08 06:43:27 PM UTC 25
Finished Feb 08 06:43:30 PM UTC 25
Peak memory 215512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694035608 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.2694035608
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1027958968
Short name T303
Test name
Test status
Simulation time 9849877175 ps
CPU time 15.83 seconds
Started Feb 08 06:43:16 PM UTC 25
Finished Feb 08 06:43:33 PM UTC 25
Peak memory 245204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027958968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1027958968
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.557947817
Short name T869
Test name
Test status
Simulation time 61543615 ps
CPU time 1.17 seconds
Started Feb 08 06:43:09 PM UTC 25
Finished Feb 08 06:43:11 PM UTC 25
Peak memory 215900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557947817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.557947817
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.345530645
Short name T930
Test name
Test status
Simulation time 4097858785 ps
CPU time 64 seconds
Started Feb 08 06:43:23 PM UTC 25
Finished Feb 08 06:44:29 PM UTC 25
Peak memory 267936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345530645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.345530645
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2057185391
Short name T1000
Test name
Test status
Simulation time 103139710029 ps
CPU time 136.08 seconds
Started Feb 08 06:43:23 PM UTC 25
Finished Feb 08 06:45:42 PM UTC 25
Peak memory 263664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057185391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2057185391
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.52400873
Short name T167
Test name
Test status
Simulation time 22535137202 ps
CPU time 224.2 seconds
Started Feb 08 06:43:24 PM UTC 25
Finished Feb 08 06:47:12 PM UTC 25
Peak memory 263768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52400873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.52400873
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3809463230
Short name T879
Test name
Test status
Simulation time 756669928 ps
CPU time 6.71 seconds
Started Feb 08 06:43:16 PM UTC 25
Finished Feb 08 06:43:24 PM UTC 25
Peak memory 234924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809463230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3809463230
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.155932117
Short name T1028
Test name
Test status
Simulation time 93035373993 ps
CPU time 411.96 seconds
Started Feb 08 06:43:17 PM UTC 25
Finished Feb 08 06:50:14 PM UTC 25
Peak memory 278324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155932117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.155932117
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.1174676015
Short name T897
Test name
Test status
Simulation time 9216828044 ps
CPU time 27.7 seconds
Started Feb 08 06:43:14 PM UTC 25
Finished Feb 08 06:43:43 PM UTC 25
Peak memory 235200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174676015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1174676015
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.271817153
Short name T887
Test name
Test status
Simulation time 6861469857 ps
CPU time 19.11 seconds
Started Feb 08 06:43:15 PM UTC 25
Finished Feb 08 06:43:35 PM UTC 25
Peak memory 245204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271817153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.271817153
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.4039632926
Short name T894
Test name
Test status
Simulation time 17465988901 ps
CPU time 26.38 seconds
Started Feb 08 06:43:13 PM UTC 25
Finished Feb 08 06:43:40 PM UTC 25
Peak memory 245336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039632926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.4039632926
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1887855299
Short name T885
Test name
Test status
Simulation time 14715579588 ps
CPU time 19.12 seconds
Started Feb 08 06:43:13 PM UTC 25
Finished Feb 08 06:43:33 PM UTC 25
Peak memory 234996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887855299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1887855299
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.4253385445
Short name T890
Test name
Test status
Simulation time 10235027189 ps
CPU time 18.79 seconds
Started Feb 08 06:43:18 PM UTC 25
Finished Feb 08 06:43:38 PM UTC 25
Peak memory 231512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253385445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.4253385445
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.387415376
Short name T166
Test name
Test status
Simulation time 67931239329 ps
CPU time 215.59 seconds
Started Feb 08 06:43:25 PM UTC 25
Finished Feb 08 06:47:04 PM UTC 25
Peak memory 261688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387415376 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.387415376
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.13426436
Short name T895
Test name
Test status
Simulation time 6800737965 ps
CPU time 29.87 seconds
Started Feb 08 06:43:10 PM UTC 25
Finished Feb 08 06:43:42 PM UTC 25
Peak memory 227480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13426436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.13426436
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3396719225
Short name T876
Test name
Test status
Simulation time 1687129014 ps
CPU time 7.19 seconds
Started Feb 08 06:43:09 PM UTC 25
Finished Feb 08 06:43:18 PM UTC 25
Peak memory 227292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396719225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3396719225
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.2504155901
Short name T874
Test name
Test status
Simulation time 16917265 ps
CPU time 1.16 seconds
Started Feb 08 06:43:12 PM UTC 25
Finished Feb 08 06:43:15 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504155901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2504155901
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1496708511
Short name T872
Test name
Test status
Simulation time 376424579 ps
CPU time 1.45 seconds
Started Feb 08 06:43:11 PM UTC 25
Finished Feb 08 06:43:14 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496708511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1496708511
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.953470887
Short name T901
Test name
Test status
Simulation time 17942894674 ps
CPU time 30.36 seconds
Started Feb 08 06:43:15 PM UTC 25
Finished Feb 08 06:43:47 PM UTC 25
Peak memory 245220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953470887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.953470887
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.3443513376
Short name T900
Test name
Test status
Simulation time 13054696 ps
CPU time 1.15 seconds
Started Feb 08 06:43:44 PM UTC 25
Finished Feb 08 06:43:46 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443513376 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.3443513376
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2409825401
Short name T898
Test name
Test status
Simulation time 34382528 ps
CPU time 3.05 seconds
Started Feb 08 06:43:39 PM UTC 25
Finished Feb 08 06:43:43 PM UTC 25
Peak memory 245140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409825401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2409825401
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.1526024268
Short name T884
Test name
Test status
Simulation time 36316492 ps
CPU time 1.22 seconds
Started Feb 08 06:43:27 PM UTC 25
Finished Feb 08 06:43:30 PM UTC 25
Peak memory 215692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526024268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1526024268
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.2787122125
Short name T379
Test name
Test status
Simulation time 25503199335 ps
CPU time 188.9 seconds
Started Feb 08 06:43:41 PM UTC 25
Finished Feb 08 06:46:53 PM UTC 25
Peak memory 265748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787122125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2787122125
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2043079563
Short name T1017
Test name
Test status
Simulation time 14520135782 ps
CPU time 197.6 seconds
Started Feb 08 06:43:41 PM UTC 25
Finished Feb 08 06:47:02 PM UTC 25
Peak memory 275984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043079563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2043079563
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.2357893065
Short name T919
Test name
Test status
Simulation time 7626381618 ps
CPU time 26.63 seconds
Started Feb 08 06:43:42 PM UTC 25
Finished Feb 08 06:44:11 PM UTC 25
Peak memory 229724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357893065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.2357893065
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.1818882899
Short name T912
Test name
Test status
Simulation time 1434037494 ps
CPU time 18.14 seconds
Started Feb 08 06:43:40 PM UTC 25
Finished Feb 08 06:44:00 PM UTC 25
Peak memory 234668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818882899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1818882899
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.4221476005
Short name T931
Test name
Test status
Simulation time 4035799917 ps
CPU time 47.88 seconds
Started Feb 08 06:43:40 PM UTC 25
Finished Feb 08 06:44:30 PM UTC 25
Peak memory 267848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221476005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.4221476005
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.4032168612
Short name T893
Test name
Test status
Simulation time 30682637 ps
CPU time 2.94 seconds
Started Feb 08 06:43:36 PM UTC 25
Finished Feb 08 06:43:40 PM UTC 25
Peak memory 235160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032168612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4032168612
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.652643417
Short name T899
Test name
Test status
Simulation time 239462860 ps
CPU time 6.9 seconds
Started Feb 08 06:43:37 PM UTC 25
Finished Feb 08 06:43:45 PM UTC 25
Peak memory 245404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652643417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.652643417
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3935497369
Short name T343
Test name
Test status
Simulation time 409578982 ps
CPU time 5.25 seconds
Started Feb 08 06:43:34 PM UTC 25
Finished Feb 08 06:43:40 PM UTC 25
Peak memory 245176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935497369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.3935497369
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3493044893
Short name T908
Test name
Test status
Simulation time 4730489316 ps
CPU time 18.8 seconds
Started Feb 08 06:43:34 PM UTC 25
Finished Feb 08 06:43:54 PM UTC 25
Peak memory 245240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493044893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3493044893
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1252256996
Short name T904
Test name
Test status
Simulation time 111888400 ps
CPU time 5.81 seconds
Started Feb 08 06:43:41 PM UTC 25
Finished Feb 08 06:43:48 PM UTC 25
Peak memory 233332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252256996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.1252256996
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.770733983
Short name T191
Test name
Test status
Simulation time 15026632395 ps
CPU time 155.07 seconds
Started Feb 08 06:43:42 PM UTC 25
Finished Feb 08 06:46:20 PM UTC 25
Peak memory 261916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770733983 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.770733983
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.1171194448
Short name T892
Test name
Test status
Simulation time 1250789234 ps
CPU time 7.98 seconds
Started Feb 08 06:43:31 PM UTC 25
Finished Feb 08 06:43:40 PM UTC 25
Peak memory 227668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171194448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1171194448
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2697647076
Short name T888
Test name
Test status
Simulation time 6622920912 ps
CPU time 4.86 seconds
Started Feb 08 06:43:31 PM UTC 25
Finished Feb 08 06:43:37 PM UTC 25
Peak memory 217216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697647076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2697647076
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3603064406
Short name T907
Test name
Test status
Simulation time 312355644 ps
CPU time 16.32 seconds
Started Feb 08 06:43:34 PM UTC 25
Finished Feb 08 06:43:51 PM UTC 25
Peak memory 227356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603064406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3603064406
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2580537146
Short name T886
Test name
Test status
Simulation time 386986949 ps
CPU time 1.46 seconds
Started Feb 08 06:43:31 PM UTC 25
Finished Feb 08 06:43:33 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580537146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2580537146
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3912195058
Short name T896
Test name
Test status
Simulation time 500643685 ps
CPU time 2.78 seconds
Started Feb 08 06:43:38 PM UTC 25
Finished Feb 08 06:43:42 PM UTC 25
Peak memory 245428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912195058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3912195058
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.3007677461
Short name T916
Test name
Test status
Simulation time 23075103 ps
CPU time 1.12 seconds
Started Feb 08 06:44:05 PM UTC 25
Finished Feb 08 06:44:07 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007677461 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.3007677461
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3402368285
Short name T909
Test name
Test status
Simulation time 148215539 ps
CPU time 3.37 seconds
Started Feb 08 06:43:52 PM UTC 25
Finished Feb 08 06:43:57 PM UTC 25
Peak memory 234692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402368285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3402368285
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.1836176980
Short name T902
Test name
Test status
Simulation time 66723787 ps
CPU time 1.19 seconds
Started Feb 08 06:43:45 PM UTC 25
Finished Feb 08 06:43:47 PM UTC 25
Peak memory 215880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836176980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1836176980
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.3126009995
Short name T939
Test name
Test status
Simulation time 16066043900 ps
CPU time 35.76 seconds
Started Feb 08 06:43:59 PM UTC 25
Finished Feb 08 06:44:36 PM UTC 25
Peak memory 234996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126009995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3126009995
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.40186510
Short name T966
Test name
Test status
Simulation time 11229644276 ps
CPU time 70.27 seconds
Started Feb 08 06:44:00 PM UTC 25
Finished Feb 08 06:45:12 PM UTC 25
Peak memory 249428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40186510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.40186510
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1268303264
Short name T1030
Test name
Test status
Simulation time 46670930113 ps
CPU time 485.75 seconds
Started Feb 08 06:44:01 PM UTC 25
Finished Feb 08 06:52:13 PM UTC 25
Peak memory 278100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268303264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.1268303264
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.892919287
Short name T915
Test name
Test status
Simulation time 3171679304 ps
CPU time 13.23 seconds
Started Feb 08 06:43:52 PM UTC 25
Finished Feb 08 06:44:07 PM UTC 25
Peak memory 251732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892919287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.892919287
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1339312092
Short name T1001
Test name
Test status
Simulation time 46240013385 ps
CPU time 106.73 seconds
Started Feb 08 06:43:54 PM UTC 25
Finished Feb 08 06:45:43 PM UTC 25
Peak memory 249364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339312092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.1339312092
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.2764408292
Short name T911
Test name
Test status
Simulation time 547195213 ps
CPU time 8.88 seconds
Started Feb 08 06:43:49 PM UTC 25
Finished Feb 08 06:43:59 PM UTC 25
Peak memory 245148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764408292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2764408292
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.327780278
Short name T984
Test name
Test status
Simulation time 8603166556 ps
CPU time 91.81 seconds
Started Feb 08 06:43:50 PM UTC 25
Finished Feb 08 06:45:24 PM UTC 25
Peak memory 235252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327780278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.327780278
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1511655198
Short name T917
Test name
Test status
Simulation time 1895703788 ps
CPU time 18.5 seconds
Started Feb 08 06:43:48 PM UTC 25
Finished Feb 08 06:44:08 PM UTC 25
Peak memory 245208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511655198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1511655198
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.1615620446
Short name T914
Test name
Test status
Simulation time 909585881 ps
CPU time 5.72 seconds
Started Feb 08 06:43:57 PM UTC 25
Finished Feb 08 06:44:04 PM UTC 25
Peak memory 233300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615620446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.1615620446
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.4164662117
Short name T920
Test name
Test status
Simulation time 183133424 ps
CPU time 6.63 seconds
Started Feb 08 06:44:04 PM UTC 25
Finished Feb 08 06:44:11 PM UTC 25
Peak memory 234868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164662117 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.4164662117
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.889339984
Short name T910
Test name
Test status
Simulation time 1028703203 ps
CPU time 11.05 seconds
Started Feb 08 06:43:46 PM UTC 25
Finished Feb 08 06:43:58 PM UTC 25
Peak memory 227548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889339984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.889339984
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1059956311
Short name T922
Test name
Test status
Simulation time 8602698424 ps
CPU time 27.49 seconds
Started Feb 08 06:43:45 PM UTC 25
Finished Feb 08 06:44:14 PM UTC 25
Peak memory 227636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059956311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1059956311
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.108647993
Short name T906
Test name
Test status
Simulation time 248077631 ps
CPU time 1.96 seconds
Started Feb 08 06:43:48 PM UTC 25
Finished Feb 08 06:43:51 PM UTC 25
Peak memory 226668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108647993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.108647993
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.393601451
Short name T905
Test name
Test status
Simulation time 96775374 ps
CPU time 1.66 seconds
Started Feb 08 06:43:47 PM UTC 25
Finished Feb 08 06:43:50 PM UTC 25
Peak memory 215840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393601451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.393601451
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.3848099455
Short name T929
Test name
Test status
Simulation time 4814097311 ps
CPU time 34.68 seconds
Started Feb 08 06:43:52 PM UTC 25
Finished Feb 08 06:44:28 PM UTC 25
Peak memory 245028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848099455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3848099455
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.765463743
Short name T934
Test name
Test status
Simulation time 11786448 ps
CPU time 1.12 seconds
Started Feb 08 06:44:29 PM UTC 25
Finished Feb 08 06:44:31 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765463743 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.765463743
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.2910920515
Short name T944
Test name
Test status
Simulation time 3906892618 ps
CPU time 24.45 seconds
Started Feb 08 06:44:16 PM UTC 25
Finished Feb 08 06:44:41 PM UTC 25
Peak memory 245208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910920515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2910920515
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.727233653
Short name T918
Test name
Test status
Simulation time 50567607 ps
CPU time 1.16 seconds
Started Feb 08 06:44:08 PM UTC 25
Finished Feb 08 06:44:10 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727233653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.727233653
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3418118924
Short name T975
Test name
Test status
Simulation time 34592456791 ps
CPU time 49.64 seconds
Started Feb 08 06:44:26 PM UTC 25
Finished Feb 08 06:45:17 PM UTC 25
Peak memory 234992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418118924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3418118924
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.170342622
Short name T959
Test name
Test status
Simulation time 1822433660 ps
CPU time 32.22 seconds
Started Feb 08 06:44:27 PM UTC 25
Finished Feb 08 06:45:01 PM UTC 25
Peak memory 229784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170342622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.170342622
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3692310839
Short name T1013
Test name
Test status
Simulation time 20567112066 ps
CPU time 121.93 seconds
Started Feb 08 06:44:27 PM UTC 25
Finished Feb 08 06:46:31 PM UTC 25
Peak memory 263760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692310839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.3692310839
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.1708431220
Short name T932
Test name
Test status
Simulation time 1637179476 ps
CPU time 10.34 seconds
Started Feb 08 06:44:19 PM UTC 25
Finished Feb 08 06:44:30 PM UTC 25
Peak memory 244928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708431220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1708431220
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3541178442
Short name T941
Test name
Test status
Simulation time 1910964493 ps
CPU time 18.73 seconds
Started Feb 08 06:44:19 PM UTC 25
Finished Feb 08 06:44:39 PM UTC 25
Peak memory 249560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541178442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.3541178442
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.451225815
Short name T928
Test name
Test status
Simulation time 3623334351 ps
CPU time 10.93 seconds
Started Feb 08 06:44:14 PM UTC 25
Finished Feb 08 06:44:26 PM UTC 25
Peak memory 234932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451225815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.451225815
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.1643058232
Short name T933
Test name
Test status
Simulation time 2039856657 ps
CPU time 15.08 seconds
Started Feb 08 06:44:14 PM UTC 25
Finished Feb 08 06:44:31 PM UTC 25
Peak memory 235056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643058232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1643058232
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3100732802
Short name T927
Test name
Test status
Simulation time 1810586301 ps
CPU time 10.88 seconds
Started Feb 08 06:44:14 PM UTC 25
Finished Feb 08 06:44:26 PM UTC 25
Peak memory 234928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100732802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.3100732802
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3691517504
Short name T938
Test name
Test status
Simulation time 16117572907 ps
CPU time 21.86 seconds
Started Feb 08 06:44:12 PM UTC 25
Finished Feb 08 06:44:35 PM UTC 25
Peak memory 251668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691517504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3691517504
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1755646474
Short name T926
Test name
Test status
Simulation time 191117593 ps
CPU time 5.76 seconds
Started Feb 08 06:44:19 PM UTC 25
Finished Feb 08 06:44:26 PM UTC 25
Peak memory 233488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755646474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.1755646474
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.1130249949
Short name T189
Test name
Test status
Simulation time 209311774 ps
CPU time 1.56 seconds
Started Feb 08 06:44:27 PM UTC 25
Finished Feb 08 06:44:30 PM UTC 25
Peak memory 216648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130249949 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.1130249949
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.2619531423
Short name T864
Test name
Test status
Simulation time 2821265700 ps
CPU time 7.81 seconds
Started Feb 08 06:44:09 PM UTC 25
Finished Feb 08 06:44:18 PM UTC 25
Peak memory 227392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619531423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2619531423
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.461771723
Short name T923
Test name
Test status
Simulation time 2811045243 ps
CPU time 5.26 seconds
Started Feb 08 06:44:08 PM UTC 25
Finished Feb 08 06:44:14 PM UTC 25
Peak memory 227684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461771723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.461771723
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.1467712000
Short name T924
Test name
Test status
Simulation time 416273812 ps
CPU time 2.36 seconds
Started Feb 08 06:44:11 PM UTC 25
Finished Feb 08 06:44:15 PM UTC 25
Peak memory 227332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467712000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1467712000
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.217089521
Short name T921
Test name
Test status
Simulation time 130983747 ps
CPU time 1.33 seconds
Started Feb 08 06:44:11 PM UTC 25
Finished Feb 08 06:44:13 PM UTC 25
Peak memory 215840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217089521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.217089521
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.3471507607
Short name T956
Test name
Test status
Simulation time 11162460882 ps
CPU time 40.14 seconds
Started Feb 08 06:44:15 PM UTC 25
Finished Feb 08 06:44:57 PM UTC 25
Peak memory 261592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471507607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3471507607
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3911049162
Short name T948
Test name
Test status
Simulation time 46848190 ps
CPU time 1.15 seconds
Started Feb 08 06:44:47 PM UTC 25
Finished Feb 08 06:44:49 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911049162 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.3911049162
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.626660688
Short name T943
Test name
Test status
Simulation time 285185871 ps
CPU time 3.37 seconds
Started Feb 08 06:44:37 PM UTC 25
Finished Feb 08 06:44:41 PM UTC 25
Peak memory 245276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626660688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.626660688
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.2253129938
Short name T935
Test name
Test status
Simulation time 53057086 ps
CPU time 1.25 seconds
Started Feb 08 06:44:30 PM UTC 25
Finished Feb 08 06:44:33 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253129938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2253129938
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.3152543910
Short name T1024
Test name
Test status
Simulation time 63659592943 ps
CPU time 176.96 seconds
Started Feb 08 06:44:40 PM UTC 25
Finished Feb 08 06:47:40 PM UTC 25
Peak memory 278036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152543910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3152543910
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.221288090
Short name T953
Test name
Test status
Simulation time 2064585523 ps
CPU time 9.31 seconds
Started Feb 08 06:44:42 PM UTC 25
Finished Feb 08 06:44:53 PM UTC 25
Peak memory 229592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221288090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.221288090
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.418710843
Short name T949
Test name
Test status
Simulation time 235168777 ps
CPU time 6.71 seconds
Started Feb 08 06:44:42 PM UTC 25
Finished Feb 08 06:44:50 PM UTC 25
Peak memory 229792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418710843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.418710843
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.1586826218
Short name T982
Test name
Test status
Simulation time 2301115027 ps
CPU time 42.24 seconds
Started Feb 08 06:44:39 PM UTC 25
Finished Feb 08 06:45:23 PM UTC 25
Peak memory 255500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586826218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1586826218
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3335857412
Short name T993
Test name
Test status
Simulation time 5969019357 ps
CPU time 52.6 seconds
Started Feb 08 06:44:40 PM UTC 25
Finished Feb 08 06:45:34 PM UTC 25
Peak memory 251412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335857412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.3335857412
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.3085355011
Short name T945
Test name
Test status
Simulation time 1576689477 ps
CPU time 10.76 seconds
Started Feb 08 06:44:35 PM UTC 25
Finished Feb 08 06:44:46 PM UTC 25
Peak memory 245176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085355011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3085355011
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.1319511263
Short name T942
Test name
Test status
Simulation time 123734223 ps
CPU time 3.23 seconds
Started Feb 08 06:44:35 PM UTC 25
Finished Feb 08 06:44:39 PM UTC 25
Peak memory 244848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319511263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1319511263
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.2037938124
Short name T961
Test name
Test status
Simulation time 5897913362 ps
CPU time 33.44 seconds
Started Feb 08 06:44:33 PM UTC 25
Finished Feb 08 06:45:08 PM UTC 25
Peak memory 234940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037938124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.2037938124
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3062022300
Short name T940
Test name
Test status
Simulation time 76055640 ps
CPU time 4.23 seconds
Started Feb 08 06:44:32 PM UTC 25
Finished Feb 08 06:44:38 PM UTC 25
Peak memory 245172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062022300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3062022300
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.1566592723
Short name T952
Test name
Test status
Simulation time 9369456145 ps
CPU time 10.91 seconds
Started Feb 08 06:44:40 PM UTC 25
Finished Feb 08 06:44:52 PM UTC 25
Peak memory 231512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566592723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.1566592723
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.2189512504
Short name T947
Test name
Test status
Simulation time 248420226 ps
CPU time 1.67 seconds
Started Feb 08 06:44:46 PM UTC 25
Finished Feb 08 06:44:49 PM UTC 25
Peak memory 215856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189512504 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.2189512504
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.2923617602
Short name T976
Test name
Test status
Simulation time 14166362190 ps
CPU time 48.48 seconds
Started Feb 08 06:44:30 PM UTC 25
Finished Feb 08 06:45:20 PM UTC 25
Peak memory 227416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923617602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2923617602
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1249334603
Short name T964
Test name
Test status
Simulation time 12685895804 ps
CPU time 38.12 seconds
Started Feb 08 06:44:30 PM UTC 25
Finished Feb 08 06:45:10 PM UTC 25
Peak memory 227608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249334603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1249334603
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.2801629904
Short name T937
Test name
Test status
Simulation time 168982633 ps
CPU time 1.66 seconds
Started Feb 08 06:44:31 PM UTC 25
Finished Feb 08 06:44:34 PM UTC 25
Peak memory 216244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801629904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2801629904
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.502732333
Short name T936
Test name
Test status
Simulation time 32776199 ps
CPU time 1.12 seconds
Started Feb 08 06:44:31 PM UTC 25
Finished Feb 08 06:44:34 PM UTC 25
Peak memory 215840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502732333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.502732333
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.1320938984
Short name T946
Test name
Test status
Simulation time 535753081 ps
CPU time 10.81 seconds
Started Feb 08 06:44:36 PM UTC 25
Finished Feb 08 06:44:48 PM UTC 25
Peak memory 234876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320938984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1320938984
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.407926524
Short name T967
Test name
Test status
Simulation time 95740450 ps
CPU time 1.09 seconds
Started Feb 08 06:45:10 PM UTC 25
Finished Feb 08 06:45:12 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407926524 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.407926524
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2412729934
Short name T971
Test name
Test status
Simulation time 9104537000 ps
CPU time 14.65 seconds
Started Feb 08 06:44:58 PM UTC 25
Finished Feb 08 06:45:14 PM UTC 25
Peak memory 235096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412729934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2412729934
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.3911092283
Short name T950
Test name
Test status
Simulation time 28133553 ps
CPU time 1.19 seconds
Started Feb 08 06:44:48 PM UTC 25
Finished Feb 08 06:44:51 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911092283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3911092283
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.3760249877
Short name T1008
Test name
Test status
Simulation time 9017126814 ps
CPU time 50.52 seconds
Started Feb 08 06:45:02 PM UTC 25
Finished Feb 08 06:45:54 PM UTC 25
Peak memory 261656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760249877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3760249877
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.837270889
Short name T1020
Test name
Test status
Simulation time 28726936949 ps
CPU time 133.64 seconds
Started Feb 08 06:45:08 PM UTC 25
Finished Feb 08 06:47:25 PM UTC 25
Peak memory 263732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837270889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.837270889
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2355123966
Short name T988
Test name
Test status
Simulation time 2632617727 ps
CPU time 19.31 seconds
Started Feb 08 06:45:09 PM UTC 25
Finished Feb 08 06:45:30 PM UTC 25
Peak memory 229628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355123966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.2355123966
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2255407253
Short name T989
Test name
Test status
Simulation time 4225429872 ps
CPU time 31.64 seconds
Started Feb 08 06:44:59 PM UTC 25
Finished Feb 08 06:45:32 PM UTC 25
Peak memory 261868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255407253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2255407253
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2540918712
Short name T1025
Test name
Test status
Simulation time 85361743947 ps
CPU time 200.93 seconds
Started Feb 08 06:45:00 PM UTC 25
Finished Feb 08 06:48:24 PM UTC 25
Peak memory 267892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540918712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.2540918712
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.530838743
Short name T965
Test name
Test status
Simulation time 3899242045 ps
CPU time 15.78 seconds
Started Feb 08 06:44:54 PM UTC 25
Finished Feb 08 06:45:11 PM UTC 25
Peak memory 234948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530838743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.530838743
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.3939029164
Short name T960
Test name
Test status
Simulation time 95475627 ps
CPU time 4.96 seconds
Started Feb 08 06:44:55 PM UTC 25
Finished Feb 08 06:45:01 PM UTC 25
Peak memory 245140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939029164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3939029164
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3013405374
Short name T979
Test name
Test status
Simulation time 58649932500 ps
CPU time 27.51 seconds
Started Feb 08 06:44:53 PM UTC 25
Finished Feb 08 06:45:22 PM UTC 25
Peak memory 245272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013405374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.3013405374
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.153256117
Short name T972
Test name
Test status
Simulation time 6607659687 ps
CPU time 20.62 seconds
Started Feb 08 06:44:53 PM UTC 25
Finished Feb 08 06:45:15 PM UTC 25
Peak memory 251640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153256117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.153256117
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2203922639
Short name T962
Test name
Test status
Simulation time 872701994 ps
CPU time 6.33 seconds
Started Feb 08 06:45:01 PM UTC 25
Finished Feb 08 06:45:09 PM UTC 25
Peak memory 233300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203922639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.2203922639
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.2507835975
Short name T1016
Test name
Test status
Simulation time 3500802240 ps
CPU time 84.39 seconds
Started Feb 08 06:45:10 PM UTC 25
Finished Feb 08 06:46:36 PM UTC 25
Peak memory 267796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507835975 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.2507835975
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.3790605944
Short name T983
Test name
Test status
Simulation time 84229229754 ps
CPU time 31.41 seconds
Started Feb 08 06:44:51 PM UTC 25
Finished Feb 08 06:45:23 PM UTC 25
Peak memory 227640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790605944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3790605944
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2447986721
Short name T951
Test name
Test status
Simulation time 30168218 ps
CPU time 1.09 seconds
Started Feb 08 06:44:49 PM UTC 25
Finished Feb 08 06:44:52 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447986721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2447986721
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.4007645350
Short name T955
Test name
Test status
Simulation time 73940762 ps
CPU time 1.29 seconds
Started Feb 08 06:44:52 PM UTC 25
Finished Feb 08 06:44:54 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007645350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4007645350
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3339466673
Short name T954
Test name
Test status
Simulation time 62281234 ps
CPU time 1.05 seconds
Started Feb 08 06:44:51 PM UTC 25
Finished Feb 08 06:44:54 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339466673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3339466673
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.1306304580
Short name T958
Test name
Test status
Simulation time 115429848 ps
CPU time 2.96 seconds
Started Feb 08 06:44:55 PM UTC 25
Finished Feb 08 06:44:59 PM UTC 25
Peak memory 234496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306304580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1306304580
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.630629389
Short name T985
Test name
Test status
Simulation time 37329014 ps
CPU time 1.03 seconds
Started Feb 08 06:45:24 PM UTC 25
Finished Feb 08 06:45:26 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630629389 -assert nopostproc +UVM_TESTNAME=spi_devi
ce_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.630629389
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3612291463
Short name T978
Test name
Test status
Simulation time 104736897 ps
CPU time 2.73 seconds
Started Feb 08 06:45:17 PM UTC 25
Finished Feb 08 06:45:21 PM UTC 25
Peak memory 244984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612291463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3612291463
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.2690367380
Short name T968
Test name
Test status
Simulation time 133598224 ps
CPU time 1.2 seconds
Started Feb 08 06:45:11 PM UTC 25
Finished Feb 08 06:45:13 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690367380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2690367380
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.443394112
Short name T1015
Test name
Test status
Simulation time 6403153995 ps
CPU time 71.05 seconds
Started Feb 08 06:45:23 PM UTC 25
Finished Feb 08 06:46:36 PM UTC 25
Peak memory 245564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443394112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.443394112
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3216295863
Short name T1018
Test name
Test status
Simulation time 57896847696 ps
CPU time 104.21 seconds
Started Feb 08 06:45:23 PM UTC 25
Finished Feb 08 06:47:09 PM UTC 25
Peak memory 267824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216295863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3216295863
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1229093341
Short name T1027
Test name
Test status
Simulation time 20230019383 ps
CPU time 244.41 seconds
Started Feb 08 06:45:24 PM UTC 25
Finished Feb 08 06:49:32 PM UTC 25
Peak memory 265780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229093341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.1229093341
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.3179748492
Short name T1007
Test name
Test status
Simulation time 1673068776 ps
CPU time 30.09 seconds
Started Feb 08 06:45:18 PM UTC 25
Finished Feb 08 06:45:50 PM UTC 25
Peak memory 245168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179748492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3179748492
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.186306222
Short name T998
Test name
Test status
Simulation time 708466556 ps
CPU time 17.73 seconds
Started Feb 08 06:45:21 PM UTC 25
Finished Feb 08 06:45:41 PM UTC 25
Peak memory 247480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186306222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.186306222
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.3863157505
Short name T977
Test name
Test status
Simulation time 800062713 ps
CPU time 4.49 seconds
Started Feb 08 06:45:15 PM UTC 25
Finished Feb 08 06:45:21 PM UTC 25
Peak memory 234884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863157505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3863157505
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.3120675656
Short name T980
Test name
Test status
Simulation time 1643036450 ps
CPU time 5.18 seconds
Started Feb 08 06:45:16 PM UTC 25
Finished Feb 08 06:45:23 PM UTC 25
Peak memory 234612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120675656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3120675656
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2480373776
Short name T994
Test name
Test status
Simulation time 5442915055 ps
CPU time 19.3 seconds
Started Feb 08 06:45:15 PM UTC 25
Finished Feb 08 06:45:36 PM UTC 25
Peak memory 245292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480373776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.2480373776
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2843641138
Short name T991
Test name
Test status
Simulation time 5111949503 ps
CPU time 17.01 seconds
Started Feb 08 06:45:15 PM UTC 25
Finished Feb 08 06:45:33 PM UTC 25
Peak memory 234888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843641138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2843641138
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2922147042
Short name T995
Test name
Test status
Simulation time 1573355961 ps
CPU time 14.49 seconds
Started Feb 08 06:45:21 PM UTC 25
Finished Feb 08 06:45:38 PM UTC 25
Peak memory 231192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922147042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.2922147042
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.2800665042
Short name T190
Test name
Test status
Simulation time 1966453950 ps
CPU time 23.35 seconds
Started Feb 08 06:45:24 PM UTC 25
Finished Feb 08 06:45:49 PM UTC 25
Peak memory 235252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800665042 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.2800665042
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.2096213094
Short name T996
Test name
Test status
Simulation time 13591545741 ps
CPU time 24.35 seconds
Started Feb 08 06:45:13 PM UTC 25
Finished Feb 08 06:45:39 PM UTC 25
Peak memory 227412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096213094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2096213094
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4031748570
Short name T981
Test name
Test status
Simulation time 2382669535 ps
CPU time 9.63 seconds
Started Feb 08 06:45:12 PM UTC 25
Finished Feb 08 06:45:23 PM UTC 25
Peak memory 227700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031748570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4031748570
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.1509814393
Short name T974
Test name
Test status
Simulation time 323129419 ps
CPU time 1.52 seconds
Started Feb 08 06:45:14 PM UTC 25
Finished Feb 08 06:45:17 PM UTC 25
Peak memory 216244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509814393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1509814393
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.357129749
Short name T973
Test name
Test status
Simulation time 127421016 ps
CPU time 1.21 seconds
Started Feb 08 06:45:13 PM UTC 25
Finished Feb 08 06:45:15 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357129749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.357129749
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.691871978
Short name T1014
Test name
Test status
Simulation time 14949896010 ps
CPU time 73.47 seconds
Started Feb 08 06:45:16 PM UTC 25
Finished Feb 08 06:46:32 PM UTC 25
Peak memory 235164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691871978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.691871978
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.3847175665
Short name T1003
Test name
Test status
Simulation time 180766722 ps
CPU time 1.08 seconds
Started Feb 08 06:45:42 PM UTC 25
Finished Feb 08 06:45:45 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847175665 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.3847175665
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1622949732
Short name T1004
Test name
Test status
Simulation time 518063060 ps
CPU time 10.05 seconds
Started Feb 08 06:45:35 PM UTC 25
Finished Feb 08 06:45:47 PM UTC 25
Peak memory 234928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622949732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1622949732
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.2998863424
Short name T986
Test name
Test status
Simulation time 87796113 ps
CPU time 1.15 seconds
Started Feb 08 06:45:24 PM UTC 25
Finished Feb 08 06:45:26 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998863424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2998863424
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.2649188641
Short name T1021
Test name
Test status
Simulation time 60555240848 ps
CPU time 103.85 seconds
Started Feb 08 06:45:39 PM UTC 25
Finished Feb 08 06:47:25 PM UTC 25
Peak memory 261624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649188641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2649188641
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.639676769
Short name T350
Test name
Test status
Simulation time 5331210996 ps
CPU time 77.91 seconds
Started Feb 08 06:45:40 PM UTC 25
Finished Feb 08 06:47:00 PM UTC 25
Peak memory 261680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639676769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.639676769
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.2570041984
Short name T1019
Test name
Test status
Simulation time 4328200342 ps
CPU time 96.16 seconds
Started Feb 08 06:45:40 PM UTC 25
Finished Feb 08 06:47:18 PM UTC 25
Peak memory 263764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570041984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.2570041984
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.1154781750
Short name T999
Test name
Test status
Simulation time 196863809 ps
CPU time 4.51 seconds
Started Feb 08 06:45:36 PM UTC 25
Finished Feb 08 06:45:41 PM UTC 25
Peak memory 245456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154781750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1154781750
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.908247447
Short name T382
Test name
Test status
Simulation time 140263370033 ps
CPU time 277.34 seconds
Started Feb 08 06:45:36 PM UTC 25
Finished Feb 08 06:50:17 PM UTC 25
Peak memory 251668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908247447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.908247447
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.842572639
Short name T1006
Test name
Test status
Simulation time 4941110412 ps
CPU time 15.12 seconds
Started Feb 08 06:45:33 PM UTC 25
Finished Feb 08 06:45:50 PM UTC 25
Peak memory 235036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842572639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.842572639
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.586911219
Short name T1002
Test name
Test status
Simulation time 1858667418 ps
CPU time 8.53 seconds
Started Feb 08 06:45:34 PM UTC 25
Finished Feb 08 06:45:44 PM UTC 25
Peak memory 245404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586911219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.586911219
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.911405964
Short name T997
Test name
Test status
Simulation time 612018507 ps
CPU time 4.41 seconds
Started Feb 08 06:45:33 PM UTC 25
Finished Feb 08 06:45:39 PM UTC 25
Peak memory 245524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911405964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.911405964
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1102037526
Short name T1011
Test name
Test status
Simulation time 74862013693 ps
CPU time 30.29 seconds
Started Feb 08 06:45:31 PM UTC 25
Finished Feb 08 06:46:03 PM UTC 25
Peak memory 261880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102037526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1102037526
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1328847478
Short name T1010
Test name
Test status
Simulation time 15523668717 ps
CPU time 23.5 seconds
Started Feb 08 06:45:37 PM UTC 25
Finished Feb 08 06:46:02 PM UTC 25
Peak memory 233396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328847478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.1328847478
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.2371992593
Short name T376
Test name
Test status
Simulation time 18132906724 ps
CPU time 127.56 seconds
Started Feb 08 06:45:42 PM UTC 25
Finished Feb 08 06:47:52 PM UTC 25
Peak memory 278068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371992593 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.2371992593
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.2333186092
Short name T1005
Test name
Test status
Simulation time 3856817488 ps
CPU time 19.09 seconds
Started Feb 08 06:45:27 PM UTC 25
Finished Feb 08 06:45:47 PM UTC 25
Peak memory 231544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333186092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2333186092
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1467470501
Short name T992
Test name
Test status
Simulation time 2674479509 ps
CPU time 7.96 seconds
Started Feb 08 06:45:25 PM UTC 25
Finished Feb 08 06:45:34 PM UTC 25
Peak memory 227476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467470501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1467470501
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.470455921
Short name T990
Test name
Test status
Simulation time 14134345 ps
CPU time 1.14 seconds
Started Feb 08 06:45:30 PM UTC 25
Finished Feb 08 06:45:32 PM UTC 25
Peak memory 215844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470455921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.470455921
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.1823775979
Short name T987
Test name
Test status
Simulation time 19043712 ps
CPU time 1.17 seconds
Started Feb 08 06:45:27 PM UTC 25
Finished Feb 08 06:45:29 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823775979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1823775979
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.3662510723
Short name T1012
Test name
Test status
Simulation time 42221421447 ps
CPU time 31.76 seconds
Started Feb 08 06:45:35 PM UTC 25
Finished Feb 08 06:46:09 PM UTC 25
Peak memory 251348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662510723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3662510723
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.2532016380
Short name T426
Test name
Test status
Simulation time 44478367 ps
CPU time 1.11 seconds
Started Feb 08 06:30:48 PM UTC 25
Finished Feb 08 06:30:50 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532016380 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2532016380
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3433397675
Short name T425
Test name
Test status
Simulation time 229927322 ps
CPU time 5.71 seconds
Started Feb 08 06:30:42 PM UTC 25
Finished Feb 08 06:30:49 PM UTC 25
Peak memory 234960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433397675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3433397675
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.991499775
Short name T418
Test name
Test status
Simulation time 63361077 ps
CPU time 1.15 seconds
Started Feb 08 06:30:37 PM UTC 25
Finished Feb 08 06:30:39 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991499775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.991499775
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.1332502628
Short name T89
Test name
Test status
Simulation time 526601386 ps
CPU time 7.52 seconds
Started Feb 08 06:30:46 PM UTC 25
Finished Feb 08 06:30:55 PM UTC 25
Peak memory 245432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332502628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1332502628
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.2163893209
Short name T213
Test name
Test status
Simulation time 54323589 ps
CPU time 4.5 seconds
Started Feb 08 06:30:42 PM UTC 25
Finished Feb 08 06:30:48 PM UTC 25
Peak memory 245400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163893209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2163893209
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.424001541
Short name T104
Test name
Test status
Simulation time 3857337056 ps
CPU time 68.42 seconds
Started Feb 08 06:30:43 PM UTC 25
Finished Feb 08 06:31:53 PM UTC 25
Peak memory 267768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424001541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.424001541
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.2951735157
Short name T247
Test name
Test status
Simulation time 867771707 ps
CPU time 3.66 seconds
Started Feb 08 06:30:41 PM UTC 25
Finished Feb 08 06:30:45 PM UTC 25
Peak memory 245360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951735157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2951735157
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.3265711614
Short name T423
Test name
Test status
Simulation time 108308124 ps
CPU time 3.82 seconds
Started Feb 08 06:30:41 PM UTC 25
Finished Feb 08 06:30:46 PM UTC 25
Peak memory 235088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265711614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3265711614
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.3133218686
Short name T419
Test name
Test status
Simulation time 29483085 ps
CPU time 1.35 seconds
Started Feb 08 06:30:37 PM UTC 25
Finished Feb 08 06:30:41 PM UTC 25
Peak memory 229192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133218686 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mem_parity.3133218686
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.921503601
Short name T422
Test name
Test status
Simulation time 168354610 ps
CPU time 3.31 seconds
Started Feb 08 06:30:40 PM UTC 25
Finished Feb 08 06:30:45 PM UTC 25
Peak memory 244828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921503601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.921503601
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1625817026
Short name T262
Test name
Test status
Simulation time 3265420405 ps
CPU time 18.85 seconds
Started Feb 08 06:30:40 PM UTC 25
Finished Feb 08 06:31:01 PM UTC 25
Peak memory 245528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625817026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1625817026
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1516519782
Short name T125
Test name
Test status
Simulation time 4045289584 ps
CPU time 13.64 seconds
Started Feb 08 06:30:43 PM UTC 25
Finished Feb 08 06:30:58 PM UTC 25
Peak memory 233400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516519782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.1516519782
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.608985710
Short name T37
Test name
Test status
Simulation time 7999995483 ps
CPU time 34.78 seconds
Started Feb 08 06:30:47 PM UTC 25
Finished Feb 08 06:31:23 PM UTC 25
Peak memory 249424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608985710 -assert nopostproc +UVM_TESTNAME=spi_d
evice_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.608985710
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.2254986790
Short name T109
Test name
Test status
Simulation time 5902649619 ps
CPU time 11.69 seconds
Started Feb 08 06:30:38 PM UTC 25
Finished Feb 08 06:30:51 PM UTC 25
Peak memory 227412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254986790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2254986790
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3480641058
Short name T424
Test name
Test status
Simulation time 1895366369 ps
CPU time 8.64 seconds
Started Feb 08 06:30:38 PM UTC 25
Finished Feb 08 06:30:48 PM UTC 25
Peak memory 227344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480641058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3480641058
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.2428547998
Short name T402
Test name
Test status
Simulation time 104682537 ps
CPU time 1.82 seconds
Started Feb 08 06:30:39 PM UTC 25
Finished Feb 08 06:30:42 PM UTC 25
Peak memory 226360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428547998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2428547998
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3763564697
Short name T421
Test name
Test status
Simulation time 141902209 ps
CPU time 1.33 seconds
Started Feb 08 06:30:39 PM UTC 25
Finished Feb 08 06:30:42 PM UTC 25
Peak memory 215628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763564697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3763564697
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2149476029
Short name T203
Test name
Test status
Simulation time 505670149 ps
CPU time 4.06 seconds
Started Feb 08 06:30:42 PM UTC 25
Finished Feb 08 06:30:47 PM UTC 25
Peak memory 235132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149476029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2149476029
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.2713270458
Short name T432
Test name
Test status
Simulation time 14826895 ps
CPU time 1.15 seconds
Started Feb 08 06:31:09 PM UTC 25
Finished Feb 08 06:31:12 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713270458 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2713270458
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3221575570
Short name T227
Test name
Test status
Simulation time 442747181 ps
CPU time 3.46 seconds
Started Feb 08 06:30:56 PM UTC 25
Finished Feb 08 06:31:00 PM UTC 25
Peak memory 234896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221575570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3221575570
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3685114730
Short name T427
Test name
Test status
Simulation time 18464202 ps
CPU time 1.23 seconds
Started Feb 08 06:30:48 PM UTC 25
Finished Feb 08 06:30:51 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685114730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3685114730
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.2621703946
Short name T237
Test name
Test status
Simulation time 77391331707 ps
CPU time 174.64 seconds
Started Feb 08 06:31:01 PM UTC 25
Finished Feb 08 06:33:59 PM UTC 25
Peak memory 261820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621703946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2621703946
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3191169114
Short name T77
Test name
Test status
Simulation time 14127669880 ps
CPU time 200.59 seconds
Started Feb 08 06:31:01 PM UTC 25
Finished Feb 08 06:34:25 PM UTC 25
Peak memory 265776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191169114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3191169114
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2478074781
Short name T207
Test name
Test status
Simulation time 7025086797 ps
CPU time 112.37 seconds
Started Feb 08 06:31:01 PM UTC 25
Finished Feb 08 06:32:56 PM UTC 25
Peak memory 278072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478074781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.2478074781
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.1986568423
Short name T392
Test name
Test status
Simulation time 5511720758 ps
CPU time 21.44 seconds
Started Feb 08 06:30:59 PM UTC 25
Finished Feb 08 06:31:22 PM UTC 25
Peak memory 234996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986568423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1986568423
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1684134749
Short name T256
Test name
Test status
Simulation time 47769013104 ps
CPU time 381.98 seconds
Started Feb 08 06:31:00 PM UTC 25
Finished Feb 08 06:37:27 PM UTC 25
Peak memory 267804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684134749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.1684134749
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.2786885866
Short name T251
Test name
Test status
Simulation time 109111334 ps
CPU time 4.48 seconds
Started Feb 08 06:30:54 PM UTC 25
Finished Feb 08 06:30:59 PM UTC 25
Peak memory 235288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786885866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2786885866
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.640061182
Short name T277
Test name
Test status
Simulation time 3916157797 ps
CPU time 47.61 seconds
Started Feb 08 06:30:55 PM UTC 25
Finished Feb 08 06:31:44 PM UTC 25
Peak memory 251384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640061182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.640061182
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.2133767640
Short name T428
Test name
Test status
Simulation time 170825890 ps
CPU time 1.58 seconds
Started Feb 08 06:30:49 PM UTC 25
Finished Feb 08 06:30:52 PM UTC 25
Peak memory 229136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133767640 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.2133767640
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.4013983664
Short name T210
Test name
Test status
Simulation time 6098197024 ps
CPU time 20.2 seconds
Started Feb 08 06:30:54 PM UTC 25
Finished Feb 08 06:31:15 PM UTC 25
Peak memory 235264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013983664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.4013983664
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.3039774821
Short name T259
Test name
Test status
Simulation time 357996043 ps
CPU time 8.81 seconds
Started Feb 08 06:30:53 PM UTC 25
Finished Feb 08 06:31:03 PM UTC 25
Peak memory 245528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039774821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3039774821
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2900087294
Short name T174
Test name
Test status
Simulation time 1340145022 ps
CPU time 8.5 seconds
Started Feb 08 06:31:01 PM UTC 25
Finished Feb 08 06:31:11 PM UTC 25
Peak memory 231516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900087294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.2900087294
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.1122567625
Short name T403
Test name
Test status
Simulation time 2080648936 ps
CPU time 20.25 seconds
Started Feb 08 06:30:51 PM UTC 25
Finished Feb 08 06:31:13 PM UTC 25
Peak memory 227408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122567625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1122567625
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3303862168
Short name T429
Test name
Test status
Simulation time 339535734 ps
CPU time 2.32 seconds
Started Feb 08 06:30:49 PM UTC 25
Finished Feb 08 06:30:53 PM UTC 25
Peak memory 216888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303862168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3303862168
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.1018868631
Short name T405
Test name
Test status
Simulation time 16048427 ps
CPU time 1.25 seconds
Started Feb 08 06:30:53 PM UTC 25
Finished Feb 08 06:30:55 PM UTC 25
Peak memory 215900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018868631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1018868631
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3017263135
Short name T430
Test name
Test status
Simulation time 380488321 ps
CPU time 1.59 seconds
Started Feb 08 06:30:51 PM UTC 25
Finished Feb 08 06:30:54 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017263135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3017263135
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.65306516
Short name T431
Test name
Test status
Simulation time 201477920 ps
CPU time 3.39 seconds
Started Feb 08 06:30:56 PM UTC 25
Finished Feb 08 06:31:00 PM UTC 25
Peak memory 244880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65306516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.65306516
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3337307906
Short name T438
Test name
Test status
Simulation time 28098379 ps
CPU time 1.11 seconds
Started Feb 08 06:31:29 PM UTC 25
Finished Feb 08 06:31:31 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337307906 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3337307906
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.725188276
Short name T306
Test name
Test status
Simulation time 168875942 ps
CPU time 6.64 seconds
Started Feb 08 06:31:19 PM UTC 25
Finished Feb 08 06:31:27 PM UTC 25
Peak memory 235132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725188276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.725188276
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.1900457136
Short name T433
Test name
Test status
Simulation time 23316513 ps
CPU time 1.07 seconds
Started Feb 08 06:31:12 PM UTC 25
Finished Feb 08 06:31:14 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900457136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1900457136
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.3533315461
Short name T51
Test name
Test status
Simulation time 47979187169 ps
CPU time 72.42 seconds
Started Feb 08 06:31:24 PM UTC 25
Finished Feb 08 06:32:39 PM UTC 25
Peak memory 265864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533315461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3533315461
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1902575502
Short name T317
Test name
Test status
Simulation time 140685575770 ps
CPU time 296.59 seconds
Started Feb 08 06:31:27 PM UTC 25
Finished Feb 08 06:36:27 PM UTC 25
Peak memory 267832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902575502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.1902575502
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.1239610649
Short name T229
Test name
Test status
Simulation time 288446818 ps
CPU time 10.88 seconds
Started Feb 08 06:31:19 PM UTC 25
Finished Feb 08 06:31:31 PM UTC 25
Peak memory 245460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239610649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1239610649
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3916876915
Short name T224
Test name
Test status
Simulation time 31104121524 ps
CPU time 155.03 seconds
Started Feb 08 06:31:23 PM UTC 25
Finished Feb 08 06:34:02 PM UTC 25
Peak memory 263696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916876915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.3916876915
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.121485511
Short name T311
Test name
Test status
Simulation time 113414761 ps
CPU time 5 seconds
Started Feb 08 06:31:18 PM UTC 25
Finished Feb 08 06:31:24 PM UTC 25
Peak memory 234808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121485511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.121485511
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.65554716
Short name T275
Test name
Test status
Simulation time 141443912 ps
CPU time 6.13 seconds
Started Feb 08 06:31:18 PM UTC 25
Finished Feb 08 06:31:25 PM UTC 25
Peak memory 234824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65554716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.65554716
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3830555904
Short name T434
Test name
Test status
Simulation time 47801324 ps
CPU time 1.51 seconds
Started Feb 08 06:31:13 PM UTC 25
Finished Feb 08 06:31:15 PM UTC 25
Peak memory 229192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830555904 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.3830555904
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.117527830
Short name T245
Test name
Test status
Simulation time 20834263493 ps
CPU time 39.44 seconds
Started Feb 08 06:31:16 PM UTC 25
Finished Feb 08 06:31:57 PM UTC 25
Peak memory 245240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117527830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.117527830
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1693280619
Short name T204
Test name
Test status
Simulation time 23531538892 ps
CPU time 48.1 seconds
Started Feb 08 06:31:16 PM UTC 25
Finished Feb 08 06:32:06 PM UTC 25
Peak memory 251384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693280619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1693280619
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3371883919
Short name T441
Test name
Test status
Simulation time 1460680516 ps
CPU time 14.29 seconds
Started Feb 08 06:31:24 PM UTC 25
Finished Feb 08 06:31:40 PM UTC 25
Peak memory 233520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371883919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.3371883919
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.3431249438
Short name T397
Test name
Test status
Simulation time 10234359869 ps
CPU time 36.06 seconds
Started Feb 08 06:31:15 PM UTC 25
Finished Feb 08 06:31:52 PM UTC 25
Peak memory 229776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431249438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3431249438
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.4241655135
Short name T437
Test name
Test status
Simulation time 2706327571 ps
CPU time 8.2 seconds
Started Feb 08 06:31:14 PM UTC 25
Finished Feb 08 06:31:23 PM UTC 25
Peak memory 227460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241655135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4241655135
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3392332547
Short name T436
Test name
Test status
Simulation time 38082079 ps
CPU time 1.15 seconds
Started Feb 08 06:31:16 PM UTC 25
Finished Feb 08 06:31:19 PM UTC 25
Peak memory 215900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392332547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3392332547
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1191989483
Short name T435
Test name
Test status
Simulation time 60673034 ps
CPU time 1.1 seconds
Started Feb 08 06:31:15 PM UTC 25
Finished Feb 08 06:31:17 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191989483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1191989483
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.3081411434
Short name T255
Test name
Test status
Simulation time 119257896283 ps
CPU time 45.45 seconds
Started Feb 08 06:31:18 PM UTC 25
Finished Feb 08 06:32:05 PM UTC 25
Peak memory 245268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081411434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3081411434
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.1707323251
Short name T445
Test name
Test status
Simulation time 11558053 ps
CPU time 1.09 seconds
Started Feb 08 06:31:58 PM UTC 25
Finished Feb 08 06:32:01 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707323251 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1707323251
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1812791917
Short name T113
Test name
Test status
Simulation time 4495842079 ps
CPU time 13.59 seconds
Started Feb 08 06:31:46 PM UTC 25
Finished Feb 08 06:32:01 PM UTC 25
Peak memory 234932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812791917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1812791917
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1933424368
Short name T439
Test name
Test status
Simulation time 16726122 ps
CPU time 1.16 seconds
Started Feb 08 06:31:32 PM UTC 25
Finished Feb 08 06:31:34 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933424368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1933424368
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.3289941472
Short name T72
Test name
Test status
Simulation time 42855371738 ps
CPU time 89.85 seconds
Started Feb 08 06:31:52 PM UTC 25
Finished Feb 08 06:33:24 PM UTC 25
Peak memory 278008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289941472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3289941472
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.4017245314
Short name T102
Test name
Test status
Simulation time 4658134691 ps
CPU time 92.24 seconds
Started Feb 08 06:31:54 PM UTC 25
Finished Feb 08 06:33:28 PM UTC 25
Peak memory 263768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017245314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.4017245314
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.4034084024
Short name T393
Test name
Test status
Simulation time 14117518271 ps
CPU time 41.75 seconds
Started Feb 08 06:31:48 PM UTC 25
Finished Feb 08 06:32:31 PM UTC 25
Peak memory 251352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034084024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4034084024
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3439819048
Short name T271
Test name
Test status
Simulation time 235283890205 ps
CPU time 378.38 seconds
Started Feb 08 06:31:51 PM UTC 25
Finished Feb 08 06:38:14 PM UTC 25
Peak memory 263956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439819048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.3439819048
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2150255018
Short name T266
Test name
Test status
Simulation time 6983996292 ps
CPU time 20.31 seconds
Started Feb 08 06:31:43 PM UTC 25
Finished Feb 08 06:32:06 PM UTC 25
Peak memory 242148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150255018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2150255018
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.3109546766
Short name T260
Test name
Test status
Simulation time 764255082 ps
CPU time 17.32 seconds
Started Feb 08 06:31:45 PM UTC 25
Finished Feb 08 06:32:04 PM UTC 25
Peak memory 245392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109546766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3109546766
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1944052547
Short name T440
Test name
Test status
Simulation time 56369657 ps
CPU time 1.54 seconds
Started Feb 08 06:31:32 PM UTC 25
Finished Feb 08 06:31:34 PM UTC 25
Peak memory 229196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944052547 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mem_parity.1944052547
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.629317037
Short name T64
Test name
Test status
Simulation time 189428241 ps
CPU time 5.94 seconds
Started Feb 08 06:31:42 PM UTC 25
Finished Feb 08 06:31:50 PM UTC 25
Peak memory 245404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629317037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.629317037
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1518523019
Short name T278
Test name
Test status
Simulation time 5641986314 ps
CPU time 14.48 seconds
Started Feb 08 06:31:41 PM UTC 25
Finished Feb 08 06:31:57 PM UTC 25
Peak memory 245272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518523019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1518523019
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3644797623
Short name T192
Test name
Test status
Simulation time 2202880438 ps
CPU time 27.33 seconds
Started Feb 08 06:31:51 PM UTC 25
Finished Feb 08 06:32:20 PM UTC 25
Peak memory 233368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644797623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.3644797623
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.3009255713
Short name T38
Test name
Test status
Simulation time 165088431 ps
CPU time 1.47 seconds
Started Feb 08 06:31:57 PM UTC 25
Finished Feb 08 06:32:00 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009255713 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.3009255713
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.1338219137
Short name T400
Test name
Test status
Simulation time 29690597661 ps
CPU time 13.77 seconds
Started Feb 08 06:31:35 PM UTC 25
Finished Feb 08 06:31:50 PM UTC 25
Peak memory 227760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338219137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1338219137
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1521012843
Short name T444
Test name
Test status
Simulation time 1776057178 ps
CPU time 8.01 seconds
Started Feb 08 06:31:35 PM UTC 25
Finished Feb 08 06:31:44 PM UTC 25
Peak memory 227496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521012843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1521012843
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.1407402923
Short name T443
Test name
Test status
Simulation time 48653811 ps
CPU time 1.86 seconds
Started Feb 08 06:31:39 PM UTC 25
Finished Feb 08 06:31:42 PM UTC 25
Peak memory 226116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407402923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1407402923
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.1288105765
Short name T442
Test name
Test status
Simulation time 411228326 ps
CPU time 1.61 seconds
Started Feb 08 06:31:39 PM UTC 25
Finished Feb 08 06:31:42 PM UTC 25
Peak memory 215844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288105765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1288105765
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.298090063
Short name T353
Test name
Test status
Simulation time 4212428128 ps
CPU time 29.49 seconds
Started Feb 08 06:31:46 PM UTC 25
Finished Feb 08 06:32:17 PM UTC 25
Peak memory 251356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298090063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.298090063
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2540754705
Short name T193
Test name
Test status
Simulation time 51373642 ps
CPU time 1.15 seconds
Started Feb 08 06:32:18 PM UTC 25
Finished Feb 08 06:32:20 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540754705 -assert nopostproc +UVM_TESTNAME=spi_dev
ice_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2540754705
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1518682692
Short name T323
Test name
Test status
Simulation time 111970467 ps
CPU time 3.45 seconds
Started Feb 08 06:32:06 PM UTC 25
Finished Feb 08 06:32:11 PM UTC 25
Peak memory 245392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518682692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1518682692
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.299464733
Short name T446
Test name
Test status
Simulation time 13911298 ps
CPU time 1.22 seconds
Started Feb 08 06:31:58 PM UTC 25
Finished Feb 08 06:32:01 PM UTC 25
Peak memory 215716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299464733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.299464733
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.2444692704
Short name T261
Test name
Test status
Simulation time 8303098187 ps
CPU time 98.13 seconds
Started Feb 08 06:32:10 PM UTC 25
Finished Feb 08 06:33:51 PM UTC 25
Peak memory 263956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444692704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2444692704
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3160739559
Short name T248
Test name
Test status
Simulation time 6783469265 ps
CPU time 114.5 seconds
Started Feb 08 06:32:11 PM UTC 25
Finished Feb 08 06:34:08 PM UTC 25
Peak memory 268144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160739559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3160739559
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2571818880
Short name T298
Test name
Test status
Simulation time 1449150608 ps
CPU time 44.92 seconds
Started Feb 08 06:32:15 PM UTC 25
Finished Feb 08 06:33:02 PM UTC 25
Peak memory 251644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571818880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.2571818880
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3105431733
Short name T283
Test name
Test status
Simulation time 234776139 ps
CPU time 7.33 seconds
Started Feb 08 06:32:06 PM UTC 25
Finished Feb 08 06:32:15 PM UTC 25
Peak memory 235188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105431733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3105431733
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2260249880
Short name T223
Test name
Test status
Simulation time 22695016489 ps
CPU time 101.99 seconds
Started Feb 08 06:32:07 PM UTC 25
Finished Feb 08 06:33:51 PM UTC 25
Peak memory 261884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260249880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.2260249880
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2722299829
Short name T115
Test name
Test status
Simulation time 1084005775 ps
CPU time 14.14 seconds
Started Feb 08 06:32:05 PM UTC 25
Finished Feb 08 06:32:20 PM UTC 25
Peak memory 234940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722299829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2722299829
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1939446588
Short name T328
Test name
Test status
Simulation time 6861975126 ps
CPU time 20.35 seconds
Started Feb 08 06:32:05 PM UTC 25
Finished Feb 08 06:32:27 PM UTC 25
Peak memory 235020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939446588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1939446588
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.1146171123
Short name T447
Test name
Test status
Simulation time 27361532 ps
CPU time 1.57 seconds
Started Feb 08 06:32:00 PM UTC 25
Finished Feb 08 06:32:03 PM UTC 25
Peak memory 229192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146171123 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mem_parity.1146171123
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3732274636
Short name T195
Test name
Test status
Simulation time 7459932755 ps
CPU time 17.07 seconds
Started Feb 08 06:32:05 PM UTC 25
Finished Feb 08 06:32:23 PM UTC 25
Peak memory 235108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732274636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2
p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.3732274636
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2897988428
Short name T300
Test name
Test status
Simulation time 1234460817 ps
CPU time 4.2 seconds
Started Feb 08 06:32:04 PM UTC 25
Finished Feb 08 06:32:09 PM UTC 25
Peak memory 235164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897988428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2897988428
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2427616114
Short name T453
Test name
Test status
Simulation time 1515279252 ps
CPU time 21.57 seconds
Started Feb 08 06:32:08 PM UTC 25
Finished Feb 08 06:32:31 PM UTC 25
Peak memory 231352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427616114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.2427616114
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.1603089128
Short name T183
Test name
Test status
Simulation time 198074629 ps
CPU time 1.55 seconds
Started Feb 08 06:32:17 PM UTC 25
Finished Feb 08 06:32:19 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603089128 -assert nopostproc +UVM_TESTNAME=spi_
device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.1603089128
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2014947093
Short name T197
Test name
Test status
Simulation time 1353341215 ps
CPU time 21.94 seconds
Started Feb 08 06:32:02 PM UTC 25
Finished Feb 08 06:32:25 PM UTC 25
Peak memory 227324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014947093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2014947093
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3454067038
Short name T449
Test name
Test status
Simulation time 17686798 ps
CPU time 1.08 seconds
Started Feb 08 06:32:02 PM UTC 25
Finished Feb 08 06:32:04 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454067038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3454067038
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.1292588907
Short name T450
Test name
Test status
Simulation time 115339503 ps
CPU time 2.21 seconds
Started Feb 08 06:32:04 PM UTC 25
Finished Feb 08 06:32:07 PM UTC 25
Peak memory 227668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292588907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1292588907
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.4010193816
Short name T448
Test name
Test status
Simulation time 25005710 ps
CPU time 1.01 seconds
Started Feb 08 06:32:02 PM UTC 25
Finished Feb 08 06:32:04 PM UTC 25
Peak memory 215956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010193816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4010193816
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.3774768134
Short name T321
Test name
Test status
Simulation time 2514241040 ps
CPU time 9.95 seconds
Started Feb 08 06:32:05 PM UTC 25
Finished Feb 08 06:32:16 PM UTC 25
Peak memory 251736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774768134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SE
Q=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3774768134
Directory /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_upload/latest
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