| T631 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.2639188135 |
|
|
Feb 08 06:37:55 PM UTC 25 |
Feb 08 06:37:58 PM UTC 25 |
421687728 ps |
| T394 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.3112066597 |
|
|
Feb 08 06:36:36 PM UTC 25 |
Feb 08 06:37:59 PM UTC 25 |
4151082309 ps |
| T632 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.4190009538 |
|
|
Feb 08 06:37:57 PM UTC 25 |
Feb 08 06:38:02 PM UTC 25 |
141399943 ps |
| T633 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1805827525 |
|
|
Feb 08 06:37:53 PM UTC 25 |
Feb 08 06:38:03 PM UTC 25 |
4000004759 ps |
| T634 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.1421141771 |
|
|
Feb 08 06:38:00 PM UTC 25 |
Feb 08 06:38:06 PM UTC 25 |
378524110 ps |
| T329 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.3491431106 |
|
|
Feb 08 06:37:13 PM UTC 25 |
Feb 08 06:38:07 PM UTC 25 |
11918459235 ps |
| T351 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.3777681753 |
|
|
Feb 08 06:37:58 PM UTC 25 |
Feb 08 06:38:10 PM UTC 25 |
1009427485 ps |
| T635 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.1419031938 |
|
|
Feb 08 06:36:22 PM UTC 25 |
Feb 08 06:38:10 PM UTC 25 |
17452679277 ps |
| T636 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.2826748372 |
|
|
Feb 08 06:37:52 PM UTC 25 |
Feb 08 06:38:11 PM UTC 25 |
2187023788 ps |
| T637 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.4292980491 |
|
|
Feb 08 06:37:15 PM UTC 25 |
Feb 08 06:38:12 PM UTC 25 |
12414939052 ps |
| T162 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.565483038 |
|
|
Feb 08 06:36:42 PM UTC 25 |
Feb 08 06:38:12 PM UTC 25 |
11099830728 ps |
| T638 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.1409845817 |
|
|
Feb 08 06:37:59 PM UTC 25 |
Feb 08 06:38:13 PM UTC 25 |
4098174605 ps |
| T639 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.3996926476 |
|
|
Feb 08 06:37:44 PM UTC 25 |
Feb 08 06:38:13 PM UTC 25 |
790219664 ps |
| T271 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3439819048 |
|
|
Feb 08 06:31:51 PM UTC 25 |
Feb 08 06:38:14 PM UTC 25 |
235283890205 ps |
| T640 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2432029049 |
|
|
Feb 08 06:33:09 PM UTC 25 |
Feb 08 06:38:15 PM UTC 25 |
17613678472 ps |
| T641 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.4240207052 |
|
|
Feb 08 06:38:14 PM UTC 25 |
Feb 08 06:38:16 PM UTC 25 |
34110111 ps |
| T642 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.2696731628 |
|
|
Feb 08 06:38:13 PM UTC 25 |
Feb 08 06:38:16 PM UTC 25 |
52270711 ps |
| T340 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3350903436 |
|
|
Feb 08 06:37:56 PM UTC 25 |
Feb 08 06:38:16 PM UTC 25 |
6835691020 ps |
| T269 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.3917896 |
|
|
Feb 08 06:37:02 PM UTC 25 |
Feb 08 06:38:16 PM UTC 25 |
3915219917 ps |
| T643 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.745633662 |
|
|
Feb 08 06:36:36 PM UTC 25 |
Feb 08 06:38:16 PM UTC 25 |
43904649439 ps |
| T644 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3343392386 |
|
|
Feb 08 06:38:07 PM UTC 25 |
Feb 08 06:38:17 PM UTC 25 |
363941175 ps |
| T645 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.844983118 |
|
|
Feb 08 06:38:15 PM UTC 25 |
Feb 08 06:38:17 PM UTC 25 |
38627456 ps |
| T646 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.1860312187 |
|
|
Feb 08 06:38:03 PM UTC 25 |
Feb 08 06:38:17 PM UTC 25 |
1944726831 ps |
| T647 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.2014165041 |
|
|
Feb 08 06:37:55 PM UTC 25 |
Feb 08 06:38:18 PM UTC 25 |
3163059264 ps |
| T648 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.1511816669 |
|
|
Feb 08 06:38:16 PM UTC 25 |
Feb 08 06:38:19 PM UTC 25 |
251277318 ps |
| T649 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.991188893 |
|
|
Feb 08 06:37:53 PM UTC 25 |
Feb 08 06:38:19 PM UTC 25 |
2523739021 ps |
| T369 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1780859151 |
|
|
Feb 08 06:35:37 PM UTC 25 |
Feb 08 06:38:20 PM UTC 25 |
18540244588 ps |
| T78 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.4083824895 |
|
|
Feb 08 06:36:20 PM UTC 25 |
Feb 08 06:38:21 PM UTC 25 |
5607479996 ps |
| T650 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3080046904 |
|
|
Feb 08 06:38:14 PM UTC 25 |
Feb 08 06:38:21 PM UTC 25 |
4863078806 ps |
| T651 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.615732371 |
|
|
Feb 08 06:38:17 PM UTC 25 |
Feb 08 06:38:23 PM UTC 25 |
182276988 ps |
| T652 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.4237084035 |
|
|
Feb 08 06:38:18 PM UTC 25 |
Feb 08 06:38:24 PM UTC 25 |
456384107 ps |
| T653 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.1936421121 |
|
|
Feb 08 06:38:23 PM UTC 25 |
Feb 08 06:38:25 PM UTC 25 |
16036934 ps |
| T654 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.342619609 |
|
|
Feb 08 06:38:11 PM UTC 25 |
Feb 08 06:38:27 PM UTC 25 |
718950963 ps |
| T655 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3625603901 |
|
|
Feb 08 06:38:25 PM UTC 25 |
Feb 08 06:38:27 PM UTC 25 |
48894595 ps |
| T656 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.3152284688 |
|
|
Feb 08 06:38:25 PM UTC 25 |
Feb 08 06:38:27 PM UTC 25 |
15484221 ps |
| T657 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.1071260414 |
|
|
Feb 08 06:38:19 PM UTC 25 |
Feb 08 06:38:27 PM UTC 25 |
546500034 ps |
| T658 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1117554034 |
|
|
Feb 08 06:38:17 PM UTC 25 |
Feb 08 06:38:27 PM UTC 25 |
9034234607 ps |
| T659 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.1190385677 |
|
|
Feb 08 06:38:17 PM UTC 25 |
Feb 08 06:38:28 PM UTC 25 |
1010732015 ps |
| T660 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.941612617 |
|
|
Feb 08 06:38:28 PM UTC 25 |
Feb 08 06:38:31 PM UTC 25 |
30050728 ps |
| T661 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.815206378 |
|
|
Feb 08 06:38:18 PM UTC 25 |
Feb 08 06:38:32 PM UTC 25 |
325422684 ps |
| T662 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.2342311599 |
|
|
Feb 08 06:38:28 PM UTC 25 |
Feb 08 06:38:32 PM UTC 25 |
109713650 ps |
| T663 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.3080132793 |
|
|
Feb 08 06:38:28 PM UTC 25 |
Feb 08 06:38:33 PM UTC 25 |
222228634 ps |
| T664 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.1246183763 |
|
|
Feb 08 06:38:22 PM UTC 25 |
Feb 08 06:38:34 PM UTC 25 |
1057425350 ps |
| T359 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.3643918231 |
|
|
Feb 08 06:38:17 PM UTC 25 |
Feb 08 06:38:35 PM UTC 25 |
3158117253 ps |
| T665 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.3754303912 |
|
|
Feb 08 06:38:14 PM UTC 25 |
Feb 08 06:38:37 PM UTC 25 |
7286825643 ps |
| T380 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.531475924 |
|
|
Feb 08 06:38:17 PM UTC 25 |
Feb 08 06:38:37 PM UTC 25 |
10167162522 ps |
| T666 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1200325974 |
|
|
Feb 08 06:38:33 PM UTC 25 |
Feb 08 06:38:39 PM UTC 25 |
121518563 ps |
| T667 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.3010834802 |
|
|
Feb 08 06:38:26 PM UTC 25 |
Feb 08 06:38:42 PM UTC 25 |
3034755065 ps |
| T668 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.1621178031 |
|
|
Feb 08 06:38:28 PM UTC 25 |
Feb 08 06:38:42 PM UTC 25 |
608351694 ps |
| T391 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.1141567575 |
|
|
Feb 08 06:38:33 PM UTC 25 |
Feb 08 06:38:43 PM UTC 25 |
742891786 ps |
| T669 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.143333796 |
|
|
Feb 08 06:38:31 PM UTC 25 |
Feb 08 06:38:44 PM UTC 25 |
2280600406 ps |
| T670 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.248244102 |
|
|
Feb 08 06:38:43 PM UTC 25 |
Feb 08 06:38:45 PM UTC 25 |
61985164 ps |
| T671 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.2444113852 |
|
|
Feb 08 06:38:43 PM UTC 25 |
Feb 08 06:38:45 PM UTC 25 |
21998253 ps |
| T672 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.225017032 |
|
|
Feb 08 06:38:44 PM UTC 25 |
Feb 08 06:38:46 PM UTC 25 |
39712669 ps |
| T673 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.3963737924 |
|
|
Feb 08 06:38:28 PM UTC 25 |
Feb 08 06:38:47 PM UTC 25 |
5206269732 ps |
| T674 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.746481297 |
|
|
Feb 08 06:38:46 PM UTC 25 |
Feb 08 06:38:49 PM UTC 25 |
326852898 ps |
| T302 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.3524454926 |
|
|
Feb 08 06:34:35 PM UTC 25 |
Feb 08 06:38:51 PM UTC 25 |
19556388068 ps |
| T675 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.573988432 |
|
|
Feb 08 06:38:36 PM UTC 25 |
Feb 08 06:38:52 PM UTC 25 |
3889737030 ps |
| T676 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.3893325257 |
|
|
Feb 08 06:38:46 PM UTC 25 |
Feb 08 06:38:53 PM UTC 25 |
203080296 ps |
| T677 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.1081515809 |
|
|
Feb 08 06:38:29 PM UTC 25 |
Feb 08 06:38:57 PM UTC 25 |
857174278 ps |
| T254 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.3730589838 |
|
|
Feb 08 06:38:49 PM UTC 25 |
Feb 08 06:38:58 PM UTC 25 |
260862006 ps |
| T678 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.1156092887 |
|
|
Feb 08 06:38:54 PM UTC 25 |
Feb 08 06:38:59 PM UTC 25 |
202761475 ps |
| T679 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1011964737 |
|
|
Feb 08 06:38:47 PM UTC 25 |
Feb 08 06:39:05 PM UTC 25 |
3343735540 ps |
| T680 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.3905146368 |
|
|
Feb 08 06:38:58 PM UTC 25 |
Feb 08 06:39:06 PM UTC 25 |
488088345 ps |
| T681 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.3764061346 |
|
|
Feb 08 06:37:39 PM UTC 25 |
Feb 08 06:39:08 PM UTC 25 |
68110650398 ps |
| T682 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.2921290277 |
|
|
Feb 08 06:38:45 PM UTC 25 |
Feb 08 06:39:08 PM UTC 25 |
5442628595 ps |
| T683 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.947665080 |
|
|
Feb 08 06:38:20 PM UTC 25 |
Feb 08 06:39:09 PM UTC 25 |
17440818573 ps |
| T684 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.2655448385 |
|
|
Feb 08 06:34:47 PM UTC 25 |
Feb 08 06:39:10 PM UTC 25 |
139440093972 ps |
| T685 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.3985932711 |
|
|
Feb 08 06:39:09 PM UTC 25 |
Feb 08 06:39:11 PM UTC 25 |
44516411 ps |
| T686 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1510836628 |
|
|
Feb 08 06:39:00 PM UTC 25 |
Feb 08 06:39:12 PM UTC 25 |
544508499 ps |
| T687 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.3898044216 |
|
|
Feb 08 06:39:10 PM UTC 25 |
Feb 08 06:39:12 PM UTC 25 |
19423119 ps |
| T688 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.724219869 |
|
|
Feb 08 06:39:13 PM UTC 25 |
Feb 08 06:39:16 PM UTC 25 |
107019877 ps |
| T252 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.2779753360 |
|
|
Feb 08 06:35:53 PM UTC 25 |
Feb 08 06:39:17 PM UTC 25 |
21346670834 ps |
| T689 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2814536583 |
|
|
Feb 08 06:37:00 PM UTC 25 |
Feb 08 06:39:19 PM UTC 25 |
111105395327 ps |
| T690 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.2805500827 |
|
|
Feb 08 06:39:16 PM UTC 25 |
Feb 08 06:39:19 PM UTC 25 |
54108974 ps |
| T691 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.3589031059 |
|
|
Feb 08 06:39:12 PM UTC 25 |
Feb 08 06:39:20 PM UTC 25 |
3623004386 ps |
| T44 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.4071499003 |
|
|
Feb 08 06:33:32 PM UTC 25 |
Feb 08 06:39:20 PM UTC 25 |
146937045571 ps |
| T335 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3637601924 |
|
|
Feb 08 06:38:04 PM UTC 25 |
Feb 08 06:39:25 PM UTC 25 |
45163528488 ps |
| T692 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.2967003487 |
|
|
Feb 08 06:38:18 PM UTC 25 |
Feb 08 06:39:25 PM UTC 25 |
18284791603 ps |
| T693 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.2808680729 |
|
|
Feb 08 06:38:52 PM UTC 25 |
Feb 08 06:39:25 PM UTC 25 |
6894911157 ps |
| T694 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3950345265 |
|
|
Feb 08 06:38:11 PM UTC 25 |
Feb 08 06:39:26 PM UTC 25 |
6333885802 ps |
| T695 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.3821450531 |
|
|
Feb 08 06:39:20 PM UTC 25 |
Feb 08 06:39:27 PM UTC 25 |
387234867 ps |
| T696 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.3585799509 |
|
|
Feb 08 06:39:18 PM UTC 25 |
Feb 08 06:39:28 PM UTC 25 |
2701068554 ps |
| T697 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.492657384 |
|
|
Feb 08 06:39:13 PM UTC 25 |
Feb 08 06:39:31 PM UTC 25 |
4192649614 ps |
| T355 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.2891559694 |
|
|
Feb 08 06:39:26 PM UTC 25 |
Feb 08 06:39:32 PM UTC 25 |
62625087 ps |
| T368 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1518935437 |
|
|
Feb 08 06:39:20 PM UTC 25 |
Feb 08 06:39:32 PM UTC 25 |
5652993540 ps |
| T698 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.862400481 |
|
|
Feb 08 06:39:33 PM UTC 25 |
Feb 08 06:39:36 PM UTC 25 |
30586729 ps |
| T699 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.2781658646 |
|
|
Feb 08 06:38:51 PM UTC 25 |
Feb 08 06:39:38 PM UTC 25 |
19341476444 ps |
| T700 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.1797430602 |
|
|
Feb 08 06:38:19 PM UTC 25 |
Feb 08 06:39:38 PM UTC 25 |
9477033458 ps |
| T701 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.542889821 |
|
|
Feb 08 06:39:36 PM UTC 25 |
Feb 08 06:39:39 PM UTC 25 |
16578972 ps |
| T702 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.3614917762 |
|
|
Feb 08 06:39:26 PM UTC 25 |
Feb 08 06:39:39 PM UTC 25 |
555367368 ps |
| T703 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.3378730752 |
|
|
Feb 08 06:40:00 PM UTC 25 |
Feb 08 06:40:08 PM UTC 25 |
488401345 ps |
| T704 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.2782370874 |
|
|
Feb 08 06:39:21 PM UTC 25 |
Feb 08 06:39:42 PM UTC 25 |
4367961882 ps |
| T705 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.1115694784 |
|
|
Feb 08 06:39:21 PM UTC 25 |
Feb 08 06:39:42 PM UTC 25 |
2189577865 ps |
| T706 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2368401368 |
|
|
Feb 08 06:39:40 PM UTC 25 |
Feb 08 06:39:42 PM UTC 25 |
32437976 ps |
| T707 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.2903971879 |
|
|
Feb 08 06:39:43 PM UTC 25 |
Feb 08 06:39:47 PM UTC 25 |
118725251 ps |
| T708 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.7683918 |
|
|
Feb 08 06:38:20 PM UTC 25 |
Feb 08 06:39:48 PM UTC 25 |
3619677525 ps |
| T709 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.359545780 |
|
|
Feb 08 06:37:00 PM UTC 25 |
Feb 08 06:39:48 PM UTC 25 |
8312146869 ps |
| T241 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.93607217 |
|
|
Feb 08 06:38:08 PM UTC 25 |
Feb 08 06:39:48 PM UTC 25 |
27167317451 ps |
| T710 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.1442583285 |
|
|
Feb 08 06:39:41 PM UTC 25 |
Feb 08 06:39:49 PM UTC 25 |
152324190 ps |
| T711 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.704625629 |
|
|
Feb 08 06:39:27 PM UTC 25 |
Feb 08 06:39:50 PM UTC 25 |
1351329029 ps |
| T712 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.310275259 |
|
|
Feb 08 06:37:47 PM UTC 25 |
Feb 08 06:39:52 PM UTC 25 |
12540824918 ps |
| T713 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.1539144670 |
|
|
Feb 08 06:39:49 PM UTC 25 |
Feb 08 06:39:54 PM UTC 25 |
198819301 ps |
| T714 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.4278443751 |
|
|
Feb 08 06:39:49 PM UTC 25 |
Feb 08 06:39:54 PM UTC 25 |
181056918 ps |
| T163 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.341967809 |
|
|
Feb 08 06:38:38 PM UTC 25 |
Feb 08 06:39:56 PM UTC 25 |
11075109401 ps |
| T715 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3276529581 |
|
|
Feb 08 06:39:43 PM UTC 25 |
Feb 08 06:39:57 PM UTC 25 |
3058113876 ps |
| T716 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.775459457 |
|
|
Feb 08 06:39:43 PM UTC 25 |
Feb 08 06:39:57 PM UTC 25 |
2672576031 ps |
| T717 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.1887372338 |
|
|
Feb 08 06:39:51 PM UTC 25 |
Feb 08 06:39:59 PM UTC 25 |
136237501 ps |
| T718 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.3270835696 |
|
|
Feb 08 06:39:06 PM UTC 25 |
Feb 08 06:39:59 PM UTC 25 |
7674228050 ps |
| T719 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.488605430 |
|
|
Feb 08 06:39:58 PM UTC 25 |
Feb 08 06:40:00 PM UTC 25 |
13394913 ps |
| T720 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.372890969 |
|
|
Feb 08 06:38:47 PM UTC 25 |
Feb 08 06:40:01 PM UTC 25 |
133809446135 ps |
| T721 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.4056771759 |
|
|
Feb 08 06:39:59 PM UTC 25 |
Feb 08 06:40:01 PM UTC 25 |
59763295 ps |
| T722 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.552920504 |
|
|
Feb 08 06:40:01 PM UTC 25 |
Feb 08 06:40:03 PM UTC 25 |
19076317 ps |
| T723 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.2583171687 |
|
|
Feb 08 06:40:01 PM UTC 25 |
Feb 08 06:40:03 PM UTC 25 |
49551443 ps |
| T724 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.1421103760 |
|
|
Feb 08 06:39:39 PM UTC 25 |
Feb 08 06:40:04 PM UTC 25 |
4943621115 ps |
| T725 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.3176265735 |
|
|
Feb 08 06:39:49 PM UTC 25 |
Feb 08 06:40:07 PM UTC 25 |
401519796 ps |
| T726 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.515568899 |
|
|
Feb 08 06:40:02 PM UTC 25 |
Feb 08 06:40:08 PM UTC 25 |
1159451739 ps |
| T727 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.1918649776 |
|
|
Feb 08 06:39:09 PM UTC 25 |
Feb 08 06:40:09 PM UTC 25 |
14371655579 ps |
| T728 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.2144270990 |
|
|
Feb 08 06:39:54 PM UTC 25 |
Feb 08 06:40:10 PM UTC 25 |
1081941414 ps |
| T381 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.3593040089 |
|
|
Feb 08 06:40:04 PM UTC 25 |
Feb 08 06:40:13 PM UTC 25 |
2756370678 ps |
| T729 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.57991116 |
|
|
Feb 08 06:35:53 PM UTC 25 |
Feb 08 06:40:14 PM UTC 25 |
53985103309 ps |
| T730 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.3032880811 |
|
|
Feb 08 06:37:43 PM UTC 25 |
Feb 08 06:40:14 PM UTC 25 |
119275834836 ps |
| T365 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.2062708872 |
|
|
Feb 08 06:39:09 PM UTC 25 |
Feb 08 06:40:15 PM UTC 25 |
7138342845 ps |
| T731 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.2466927157 |
|
|
Feb 08 06:40:04 PM UTC 25 |
Feb 08 06:40:15 PM UTC 25 |
237721937 ps |
| T732 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.1105866621 |
|
|
Feb 08 06:40:16 PM UTC 25 |
Feb 08 06:40:18 PM UTC 25 |
23521400 ps |
| T733 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.4106073750 |
|
|
Feb 08 06:40:11 PM UTC 25 |
Feb 08 06:40:19 PM UTC 25 |
1500301335 ps |
| T734 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.4289404516 |
|
|
Feb 08 06:40:09 PM UTC 25 |
Feb 08 06:40:20 PM UTC 25 |
306566472 ps |
| T735 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.3931684194 |
|
|
Feb 08 06:40:19 PM UTC 25 |
Feb 08 06:40:21 PM UTC 25 |
94427422 ps |
| T736 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.3680276731 |
|
|
Feb 08 06:37:03 PM UTC 25 |
Feb 08 06:40:22 PM UTC 25 |
12599781197 ps |
| T737 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.1906505609 |
|
|
Feb 08 06:40:22 PM UTC 25 |
Feb 08 06:40:24 PM UTC 25 |
23692956 ps |
| T349 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.2694817889 |
|
|
Feb 08 06:40:05 PM UTC 25 |
Feb 08 06:40:25 PM UTC 25 |
1287077695 ps |
| T738 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.361320148 |
|
|
Feb 08 06:39:26 PM UTC 25 |
Feb 08 06:40:25 PM UTC 25 |
19966113240 ps |
| T739 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.2039344703 |
|
|
Feb 08 06:40:23 PM UTC 25 |
Feb 08 06:40:26 PM UTC 25 |
117695492 ps |
| T740 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.1361936046 |
|
|
Feb 08 06:40:20 PM UTC 25 |
Feb 08 06:40:27 PM UTC 25 |
1397858652 ps |
| T741 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.1375214368 |
|
|
Feb 08 06:40:08 PM UTC 25 |
Feb 08 06:40:29 PM UTC 25 |
2680729399 ps |
| T742 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.1917647490 |
|
|
Feb 08 06:39:40 PM UTC 25 |
Feb 08 06:40:29 PM UTC 25 |
8689539903 ps |
| T743 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.1627128194 |
|
|
Feb 08 06:34:45 PM UTC 25 |
Feb 08 06:40:32 PM UTC 25 |
72735179340 ps |
| T744 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1456129709 |
|
|
Feb 08 06:40:25 PM UTC 25 |
Feb 08 06:40:32 PM UTC 25 |
9683771203 ps |
| T253 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.513106009 |
|
|
Feb 08 06:40:25 PM UTC 25 |
Feb 08 06:40:32 PM UTC 25 |
495529120 ps |
| T745 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.577125159 |
|
|
Feb 08 06:40:25 PM UTC 25 |
Feb 08 06:40:34 PM UTC 25 |
230966749 ps |
| T746 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.4051169203 |
|
|
Feb 08 06:40:08 PM UTC 25 |
Feb 08 06:40:37 PM UTC 25 |
2569166821 ps |
| T747 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.2238631693 |
|
|
Feb 08 06:40:30 PM UTC 25 |
Feb 08 06:40:38 PM UTC 25 |
278471598 ps |
| T748 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.1082700239 |
|
|
Feb 08 06:40:33 PM UTC 25 |
Feb 08 06:40:40 PM UTC 25 |
162324140 ps |
| T385 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.4119763308 |
|
|
Feb 08 06:40:33 PM UTC 25 |
Feb 08 06:40:41 PM UTC 25 |
158487769 ps |
| T749 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.2603809081 |
|
|
Feb 08 06:40:26 PM UTC 25 |
Feb 08 06:40:42 PM UTC 25 |
1683830343 ps |
| T750 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.3986743460 |
|
|
Feb 08 06:40:41 PM UTC 25 |
Feb 08 06:40:43 PM UTC 25 |
70641517 ps |
| T751 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.2404221093 |
|
|
Feb 08 06:40:41 PM UTC 25 |
Feb 08 06:40:43 PM UTC 25 |
144574779 ps |
| T752 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.2359724164 |
|
|
Feb 08 06:39:29 PM UTC 25 |
Feb 08 06:40:46 PM UTC 25 |
22374526651 ps |
| T753 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.4201396685 |
|
|
Feb 08 06:40:44 PM UTC 25 |
Feb 08 06:40:47 PM UTC 25 |
21462055 ps |
| T362 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3650175430 |
|
|
Feb 08 06:40:33 PM UTC 25 |
Feb 08 06:40:48 PM UTC 25 |
3069458994 ps |
| T754 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.4139534446 |
|
|
Feb 08 06:40:46 PM UTC 25 |
Feb 08 06:40:49 PM UTC 25 |
97569035 ps |
| T755 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.1890779247 |
|
|
Feb 08 06:40:21 PM UTC 25 |
Feb 08 06:40:56 PM UTC 25 |
6202850975 ps |
| T756 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.2704786226 |
|
|
Feb 08 06:40:50 PM UTC 25 |
Feb 08 06:40:56 PM UTC 25 |
314045552 ps |
| T757 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.2681864320 |
|
|
Feb 08 06:41:43 PM UTC 25 |
Feb 08 06:41:46 PM UTC 25 |
124241109 ps |
| T758 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.3439534996 |
|
|
Feb 08 06:40:01 PM UTC 25 |
Feb 08 06:40:59 PM UTC 25 |
7610790032 ps |
| T759 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.269788944 |
|
|
Feb 08 06:41:00 PM UTC 25 |
Feb 08 06:41:04 PM UTC 25 |
40914511 ps |
| T760 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.2118422532 |
|
|
Feb 08 06:39:48 PM UTC 25 |
Feb 08 06:41:06 PM UTC 25 |
27603620307 ps |
| T761 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.1419046048 |
|
|
Feb 08 06:40:16 PM UTC 25 |
Feb 08 06:41:06 PM UTC 25 |
6922148359 ps |
| T762 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.3308462428 |
|
|
Feb 08 06:40:57 PM UTC 25 |
Feb 08 06:41:08 PM UTC 25 |
5743767373 ps |
| T763 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3297680827 |
|
|
Feb 08 06:40:43 PM UTC 25 |
Feb 08 06:41:09 PM UTC 25 |
25825714729 ps |
| T384 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2849436571 |
|
|
Feb 08 06:35:17 PM UTC 25 |
Feb 08 06:41:11 PM UTC 25 |
54375911364 ps |
| T764 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.3431782626 |
|
|
Feb 08 06:40:44 PM UTC 25 |
Feb 08 06:41:17 PM UTC 25 |
2942372194 ps |
| T765 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.1863967242 |
|
|
Feb 08 06:40:38 PM UTC 25 |
Feb 08 06:41:17 PM UTC 25 |
2415912627 ps |
| T766 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1734195726 |
|
|
Feb 08 06:40:35 PM UTC 25 |
Feb 08 06:41:19 PM UTC 25 |
19547120673 ps |
| T767 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.391256838 |
|
|
Feb 08 06:41:07 PM UTC 25 |
Feb 08 06:41:19 PM UTC 25 |
1186540515 ps |
| T768 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2884998299 |
|
|
Feb 08 06:40:49 PM UTC 25 |
Feb 08 06:41:19 PM UTC 25 |
36301935845 ps |
| T769 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.655278188 |
|
|
Feb 08 06:41:19 PM UTC 25 |
Feb 08 06:41:21 PM UTC 25 |
40977345 ps |
| T770 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.2783690275 |
|
|
Feb 08 06:41:20 PM UTC 25 |
Feb 08 06:41:22 PM UTC 25 |
34313401 ps |
| T771 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.3451576433 |
|
|
Feb 08 06:40:28 PM UTC 25 |
Feb 08 06:41:23 PM UTC 25 |
56303813805 ps |
| T772 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.3036543504 |
|
|
Feb 08 06:41:21 PM UTC 25 |
Feb 08 06:41:24 PM UTC 25 |
467088723 ps |
| T773 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.3459708009 |
|
|
Feb 08 06:41:22 PM UTC 25 |
Feb 08 06:41:24 PM UTC 25 |
15240155 ps |
| T774 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.801668284 |
|
|
Feb 08 06:39:53 PM UTC 25 |
Feb 08 06:41:25 PM UTC 25 |
4742975713 ps |
| T775 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.4156318001 |
|
|
Feb 08 06:41:23 PM UTC 25 |
Feb 08 06:41:25 PM UTC 25 |
83500468 ps |
| T776 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.2309642360 |
|
|
Feb 08 06:41:05 PM UTC 25 |
Feb 08 06:41:26 PM UTC 25 |
4600207174 ps |
| T164 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1351641816 |
|
|
Feb 08 06:39:54 PM UTC 25 |
Feb 08 06:41:31 PM UTC 25 |
31952044650 ps |
| T777 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.775086160 |
|
|
Feb 08 06:41:26 PM UTC 25 |
Feb 08 06:41:31 PM UTC 25 |
58699490 ps |
| T778 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.544925053 |
|
|
Feb 08 06:41:26 PM UTC 25 |
Feb 08 06:41:31 PM UTC 25 |
115554286 ps |
| T779 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.3291757454 |
|
|
Feb 08 06:41:31 PM UTC 25 |
Feb 08 06:41:34 PM UTC 25 |
29639426 ps |
| T780 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.578600689 |
|
|
Feb 08 06:41:25 PM UTC 25 |
Feb 08 06:41:35 PM UTC 25 |
293107063 ps |
| T781 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.1920998710 |
|
|
Feb 08 06:39:07 PM UTC 25 |
Feb 08 06:41:35 PM UTC 25 |
137592985343 ps |
| T374 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.120125859 |
|
|
Feb 08 06:41:08 PM UTC 25 |
Feb 08 06:41:37 PM UTC 25 |
2544019763 ps |
| T782 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.1432569387 |
|
|
Feb 08 06:41:25 PM UTC 25 |
Feb 08 06:41:39 PM UTC 25 |
2652294334 ps |
| T783 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3814963583 |
|
|
Feb 08 06:40:48 PM UTC 25 |
Feb 08 06:41:39 PM UTC 25 |
20223356598 ps |
| T784 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.3865976567 |
|
|
Feb 08 06:41:32 PM UTC 25 |
Feb 08 06:41:39 PM UTC 25 |
227495000 ps |
| T785 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.2464527957 |
|
|
Feb 08 06:40:30 PM UTC 25 |
Feb 08 06:41:41 PM UTC 25 |
3464271379 ps |
| T786 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.637822763 |
|
|
Feb 08 06:39:57 PM UTC 25 |
Feb 08 06:41:42 PM UTC 25 |
43844809970 ps |
| T787 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.2471370823 |
|
|
Feb 08 06:40:57 PM UTC 25 |
Feb 08 06:41:42 PM UTC 25 |
5819877522 ps |
| T788 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.1910461965 |
|
|
Feb 08 06:41:40 PM UTC 25 |
Feb 08 06:41:42 PM UTC 25 |
35336729 ps |
| T789 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.3876504937 |
|
|
Feb 08 06:41:40 PM UTC 25 |
Feb 08 06:41:42 PM UTC 25 |
26620243 ps |
| T790 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.787262851 |
|
|
Feb 08 06:41:40 PM UTC 25 |
Feb 08 06:41:43 PM UTC 25 |
165675590 ps |
| T791 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2285853436 |
|
|
Feb 08 06:39:32 PM UTC 25 |
Feb 08 06:41:44 PM UTC 25 |
82843215539 ps |
| T186 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.501168056 |
|
|
Feb 08 06:36:44 PM UTC 25 |
Feb 08 06:41:44 PM UTC 25 |
87521034436 ps |
| T792 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2958449721 |
|
|
Feb 08 06:41:42 PM UTC 25 |
Feb 08 06:41:44 PM UTC 25 |
187026507 ps |
| T238 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.418998293 |
|
|
Feb 08 06:40:15 PM UTC 25 |
Feb 08 06:41:47 PM UTC 25 |
2928613531 ps |
| T793 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.195907460 |
|
|
Feb 08 06:41:43 PM UTC 25 |
Feb 08 06:41:48 PM UTC 25 |
85195941 ps |
| T794 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.1738050313 |
|
|
Feb 08 06:41:21 PM UTC 25 |
Feb 08 06:41:50 PM UTC 25 |
5700842582 ps |
| T795 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.3983050311 |
|
|
Feb 08 06:41:45 PM UTC 25 |
Feb 08 06:41:50 PM UTC 25 |
650760142 ps |
| T796 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.3866642107 |
|
|
Feb 08 06:41:24 PM UTC 25 |
Feb 08 06:41:52 PM UTC 25 |
16603133451 ps |
| T797 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.748384415 |
|
|
Feb 08 06:40:11 PM UTC 25 |
Feb 08 06:41:52 PM UTC 25 |
9087297370 ps |
| T798 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.65484266 |
|
|
Feb 08 06:41:45 PM UTC 25 |
Feb 08 06:41:53 PM UTC 25 |
241185198 ps |
| T799 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.1344365433 |
|
|
Feb 08 06:41:45 PM UTC 25 |
Feb 08 06:41:54 PM UTC 25 |
1599274995 ps |
| T800 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.321299649 |
|
|
Feb 08 06:41:31 PM UTC 25 |
Feb 08 06:41:55 PM UTC 25 |
1608473520 ps |
| T801 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1076334208 |
|
|
Feb 08 06:41:49 PM UTC 25 |
Feb 08 06:41:55 PM UTC 25 |
223686417 ps |
| T802 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.194575864 |
|
|
Feb 08 06:41:54 PM UTC 25 |
Feb 08 06:41:57 PM UTC 25 |
13420141 ps |
| T281 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.863138635 |
|
|
Feb 08 06:41:44 PM UTC 25 |
Feb 08 06:41:57 PM UTC 25 |
493818733 ps |
| T803 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.1440527293 |
|
|
Feb 08 06:41:55 PM UTC 25 |
Feb 08 06:41:57 PM UTC 25 |
20681225 ps |
| T336 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1190434299 |
|
|
Feb 08 06:35:06 PM UTC 25 |
Feb 08 06:41:57 PM UTC 25 |
228198344990 ps |
| T804 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2658516847 |
|
|
Feb 08 06:41:57 PM UTC 25 |
Feb 08 06:42:00 PM UTC 25 |
209273376 ps |
| T805 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.627537202 |
|
|
Feb 08 06:41:57 PM UTC 25 |
Feb 08 06:42:00 PM UTC 25 |
51553202 ps |
| T806 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.2768298264 |
|
|
Feb 08 06:41:26 PM UTC 25 |
Feb 08 06:42:01 PM UTC 25 |
1908447039 ps |
| T265 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.73006084 |
|
|
Feb 08 06:41:58 PM UTC 25 |
Feb 08 06:42:06 PM UTC 25 |
848744380 ps |
| T807 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2303189122 |
|
|
Feb 08 06:41:10 PM UTC 25 |
Feb 08 06:42:06 PM UTC 25 |
2645949388 ps |
| T808 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.473530237 |
|
|
Feb 08 06:42:02 PM UTC 25 |
Feb 08 06:42:08 PM UTC 25 |
1047729033 ps |
| T809 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.1437055711 |
|
|
Feb 08 06:42:00 PM UTC 25 |
Feb 08 06:42:09 PM UTC 25 |
1995177782 ps |
| T810 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.2271338333 |
|
|
Feb 08 06:38:38 PM UTC 25 |
Feb 08 06:42:10 PM UTC 25 |
205688660715 ps |
| T811 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.2063426631 |
|
|
Feb 08 06:41:42 PM UTC 25 |
Feb 08 06:42:11 PM UTC 25 |
15954131367 ps |
| T812 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2713230478 |
|
|
Feb 08 06:42:07 PM UTC 25 |
Feb 08 06:42:12 PM UTC 25 |
149355952 ps |
| T813 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.3160188643 |
|
|
Feb 08 06:42:07 PM UTC 25 |
Feb 08 06:42:13 PM UTC 25 |
104907205 ps |
| T814 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.4094924777 |
|
|
Feb 08 06:39:50 PM UTC 25 |
Feb 08 06:42:13 PM UTC 25 |
13118789150 ps |
| T815 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.3043077170 |
|
|
Feb 08 06:41:56 PM UTC 25 |
Feb 08 06:42:16 PM UTC 25 |
12830901024 ps |
| T816 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.2249167214 |
|
|
Feb 08 06:41:46 PM UTC 25 |
Feb 08 06:42:17 PM UTC 25 |
3682337831 ps |
| T817 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.438314572 |
|
|
Feb 08 06:42:15 PM UTC 25 |
Feb 08 06:42:17 PM UTC 25 |
141871608 ps |
| T818 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.562429568 |
|
|
Feb 08 06:42:14 PM UTC 25 |
Feb 08 06:42:17 PM UTC 25 |
18084491 ps |
| T819 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.488917507 |
|
|
Feb 08 06:34:52 PM UTC 25 |
Feb 08 06:42:18 PM UTC 25 |
44484753533 ps |
| T187 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.2015941522 |
|
|
Feb 08 06:41:38 PM UTC 25 |
Feb 08 06:42:20 PM UTC 25 |
2212556674 ps |
| T820 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2273494336 |
|
|
Feb 08 06:42:18 PM UTC 25 |
Feb 08 06:42:20 PM UTC 25 |
20360076 ps |
| T378 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.102301599 |
|
|
Feb 08 06:34:33 PM UTC 25 |
Feb 08 06:42:20 PM UTC 25 |
376830664509 ps |
| T821 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.3520144087 |
|
|
Feb 08 06:42:18 PM UTC 25 |
Feb 08 06:42:20 PM UTC 25 |
43678974 ps |
| T822 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.1297612386 |
|
|
Feb 08 06:42:10 PM UTC 25 |
Feb 08 06:42:20 PM UTC 25 |
1671087554 ps |
| T823 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.96679855 |
|
|
Feb 08 06:42:17 PM UTC 25 |
Feb 08 06:42:23 PM UTC 25 |
755981827 ps |
| T824 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.3983800432 |
|
|
Feb 08 06:37:48 PM UTC 25 |
Feb 08 06:42:23 PM UTC 25 |
88726340440 ps |
| T825 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.2993203755 |
|
|
Feb 08 06:41:43 PM UTC 25 |
Feb 08 06:42:24 PM UTC 25 |
28845046290 ps |
| T826 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.3126104363 |
|
|
Feb 08 06:41:34 PM UTC 25 |
Feb 08 06:42:26 PM UTC 25 |
15599056971 ps |
| T827 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.1419748208 |
|
|
Feb 08 06:42:02 PM UTC 25 |
Feb 08 06:42:26 PM UTC 25 |
1546773890 ps |
| T828 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.496535748 |
|
|
Feb 08 06:42:21 PM UTC 25 |
Feb 08 06:42:27 PM UTC 25 |
211485337 ps |
| T829 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1286061339 |
|
|
Feb 08 06:41:56 PM UTC 25 |
Feb 08 06:42:28 PM UTC 25 |
18260131890 ps |
| T830 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.1603510779 |
|
|
Feb 08 06:41:58 PM UTC 25 |
Feb 08 06:42:29 PM UTC 25 |
2225375012 ps |
| T831 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.1953911076 |
|
|
Feb 08 06:42:21 PM UTC 25 |
Feb 08 06:42:30 PM UTC 25 |
442718859 ps |
| T832 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.2176502231 |
|
|
Feb 08 06:42:30 PM UTC 25 |
Feb 08 06:42:32 PM UTC 25 |
36176403 ps |
| T833 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.3469822502 |
|
|
Feb 08 06:42:31 PM UTC 25 |
Feb 08 06:42:33 PM UTC 25 |
16576653 ps |
| T834 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.4080967998 |
|
|
Feb 08 06:39:27 PM UTC 25 |
Feb 08 06:42:35 PM UTC 25 |
22281514868 ps |
| T835 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.1308221358 |
|
|
Feb 08 06:42:24 PM UTC 25 |
Feb 08 06:42:36 PM UTC 25 |
964621838 ps |
| T334 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.4281555576 |
|
|
Feb 08 06:41:51 PM UTC 25 |
Feb 08 06:42:36 PM UTC 25 |
11246357357 ps |
| T836 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.284092711 |
|
|
Feb 08 06:42:33 PM UTC 25 |
Feb 08 06:42:36 PM UTC 25 |
223312589 ps |
| T837 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.2103192811 |
|
|
Feb 08 06:42:23 PM UTC 25 |
Feb 08 06:42:37 PM UTC 25 |
184130955 ps |
| T838 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.1214713632 |
|
|
Feb 08 06:42:36 PM UTC 25 |
Feb 08 06:42:38 PM UTC 25 |
27524208 ps |
| T839 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.90262767 |
|
|
Feb 08 06:42:36 PM UTC 25 |
Feb 08 06:42:38 PM UTC 25 |
35513865 ps |
| T840 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.1991697336 |
|
|
Feb 08 06:42:21 PM UTC 25 |
Feb 08 06:42:39 PM UTC 25 |
5099475711 ps |
| T841 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2310405118 |
|
|
Feb 08 06:42:37 PM UTC 25 |
Feb 08 06:42:41 PM UTC 25 |
31280360 ps |
| T842 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1592634628 |
|
|
Feb 08 06:42:18 PM UTC 25 |
Feb 08 06:42:42 PM UTC 25 |
5563513451 ps |