| T620 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.189318805 |
|
|
Oct 15 12:41:48 PM UTC 24 |
Oct 15 12:41:59 PM UTC 24 |
833236083 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.1866309329 |
|
|
Oct 15 12:39:56 PM UTC 24 |
Oct 15 12:42:00 PM UTC 24 |
38464677761 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.2974363090 |
|
|
Oct 15 12:42:00 PM UTC 24 |
Oct 15 12:42:03 PM UTC 24 |
11202773 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.3868506294 |
|
|
Oct 15 12:42:01 PM UTC 24 |
Oct 15 12:42:04 PM UTC 24 |
85342723 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1619171165 |
|
|
Oct 15 12:41:43 PM UTC 24 |
Oct 15 12:42:06 PM UTC 24 |
1553128767 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.1624028750 |
|
|
Oct 15 12:40:38 PM UTC 24 |
Oct 15 12:42:06 PM UTC 24 |
18673699476 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.1220068365 |
|
|
Oct 15 12:35:06 PM UTC 24 |
Oct 15 12:42:06 PM UTC 24 |
175353622685 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2912029051 |
|
|
Oct 15 12:41:55 PM UTC 24 |
Oct 15 12:42:10 PM UTC 24 |
5787780837 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3463142359 |
|
|
Oct 15 12:38:48 PM UTC 24 |
Oct 15 12:42:10 PM UTC 24 |
18699743926 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.835699649 |
|
|
Oct 15 12:42:07 PM UTC 24 |
Oct 15 12:42:10 PM UTC 24 |
94095377 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3676957434 |
|
|
Oct 15 12:42:07 PM UTC 24 |
Oct 15 12:42:10 PM UTC 24 |
169963759 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.3665003379 |
|
|
Oct 15 12:42:05 PM UTC 24 |
Oct 15 12:42:12 PM UTC 24 |
3224933666 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.3709731365 |
|
|
Oct 15 12:42:11 PM UTC 24 |
Oct 15 12:42:17 PM UTC 24 |
1581040136 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.710236139 |
|
|
Oct 15 12:42:13 PM UTC 24 |
Oct 15 12:42:17 PM UTC 24 |
163598030 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.4177195490 |
|
|
Oct 15 12:41:36 PM UTC 24 |
Oct 15 12:42:18 PM UTC 24 |
22445836318 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.1308028038 |
|
|
Oct 15 12:42:11 PM UTC 24 |
Oct 15 12:42:21 PM UTC 24 |
8319275343 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.3779734783 |
|
|
Oct 15 12:37:58 PM UTC 24 |
Oct 15 12:42:21 PM UTC 24 |
19515310726 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.2104426400 |
|
|
Oct 15 12:38:51 PM UTC 24 |
Oct 15 12:42:22 PM UTC 24 |
19900112275 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.3978779523 |
|
|
Oct 15 12:42:11 PM UTC 24 |
Oct 15 12:42:22 PM UTC 24 |
7651602099 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1496940746 |
|
|
Oct 15 12:42:23 PM UTC 24 |
Oct 15 12:42:26 PM UTC 24 |
49500266 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3697271118 |
|
|
Oct 15 12:42:07 PM UTC 24 |
Oct 15 12:42:26 PM UTC 24 |
9423169013 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.2501823044 |
|
|
Oct 15 12:42:18 PM UTC 24 |
Oct 15 12:42:27 PM UTC 24 |
152142892 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.1339322317 |
|
|
Oct 15 12:42:26 PM UTC 24 |
Oct 15 12:42:29 PM UTC 24 |
13929841 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.1251591050 |
|
|
Oct 15 12:40:43 PM UTC 24 |
Oct 15 12:42:29 PM UTC 24 |
7509569527 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.2285015487 |
|
|
Oct 15 12:42:27 PM UTC 24 |
Oct 15 12:42:30 PM UTC 24 |
127575021 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.486943369 |
|
|
Oct 15 12:42:30 PM UTC 24 |
Oct 15 12:42:32 PM UTC 24 |
15061491 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.4203747310 |
|
|
Oct 15 12:42:03 PM UTC 24 |
Oct 15 12:42:33 PM UTC 24 |
33644936303 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.1692769425 |
|
|
Oct 15 12:42:19 PM UTC 24 |
Oct 15 12:42:34 PM UTC 24 |
3416808236 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.4063106602 |
|
|
Oct 15 12:42:31 PM UTC 24 |
Oct 15 12:42:34 PM UTC 24 |
103173716 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.432534274 |
|
|
Oct 15 12:42:33 PM UTC 24 |
Oct 15 12:42:38 PM UTC 24 |
432086294 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.1279335448 |
|
|
Oct 15 12:41:18 PM UTC 24 |
Oct 15 12:42:38 PM UTC 24 |
9768963089 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.2840688870 |
|
|
Oct 15 12:35:44 PM UTC 24 |
Oct 15 12:42:39 PM UTC 24 |
49036360224 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.2337272225 |
|
|
Oct 15 12:41:21 PM UTC 24 |
Oct 15 12:42:40 PM UTC 24 |
47443097491 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2174077155 |
|
|
Oct 15 12:41:13 PM UTC 24 |
Oct 15 12:42:43 PM UTC 24 |
24985044770 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.3614457361 |
|
|
Oct 15 12:42:39 PM UTC 24 |
Oct 15 12:42:45 PM UTC 24 |
257853869 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.2570328553 |
|
|
Oct 15 12:42:29 PM UTC 24 |
Oct 15 12:42:50 PM UTC 24 |
2567654519 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.2792937581 |
|
|
Oct 15 12:42:35 PM UTC 24 |
Oct 15 12:42:56 PM UTC 24 |
8049729082 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.605392599 |
|
|
Oct 15 12:42:45 PM UTC 24 |
Oct 15 12:42:59 PM UTC 24 |
1341316396 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.816653518 |
|
|
Oct 15 12:42:30 PM UTC 24 |
Oct 15 12:43:00 PM UTC 24 |
2089077557 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.1243766863 |
|
|
Oct 15 12:42:39 PM UTC 24 |
Oct 15 12:43:01 PM UTC 24 |
5417816146 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3914949250 |
|
|
Oct 15 12:40:43 PM UTC 24 |
Oct 15 12:43:01 PM UTC 24 |
6716348810 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.2592087845 |
|
|
Oct 15 12:42:35 PM UTC 24 |
Oct 15 12:43:01 PM UTC 24 |
2194362898 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.915218762 |
|
|
Oct 15 12:37:55 PM UTC 24 |
Oct 15 12:43:03 PM UTC 24 |
26451957722 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.2237525329 |
|
|
Oct 15 12:43:01 PM UTC 24 |
Oct 15 12:43:03 PM UTC 24 |
32811725 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.4159308892 |
|
|
Oct 15 12:43:02 PM UTC 24 |
Oct 15 12:43:04 PM UTC 24 |
11346294 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.228751044 |
|
|
Oct 15 12:42:40 PM UTC 24 |
Oct 15 12:43:05 PM UTC 24 |
7585171232 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.3993804415 |
|
|
Oct 15 12:43:02 PM UTC 24 |
Oct 15 12:43:05 PM UTC 24 |
33016595 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3627816953 |
|
|
Oct 15 12:41:52 PM UTC 24 |
Oct 15 12:43:05 PM UTC 24 |
17573548979 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2081983645 |
|
|
Oct 15 12:43:04 PM UTC 24 |
Oct 15 12:43:06 PM UTC 24 |
39885578 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.3301856946 |
|
|
Oct 15 12:43:04 PM UTC 24 |
Oct 15 12:43:06 PM UTC 24 |
38215382 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.1776457248 |
|
|
Oct 15 12:43:07 PM UTC 24 |
Oct 15 12:43:11 PM UTC 24 |
58777996 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.3257098359 |
|
|
Oct 15 12:43:07 PM UTC 24 |
Oct 15 12:43:11 PM UTC 24 |
250117051 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3912306901 |
|
|
Oct 15 12:42:35 PM UTC 24 |
Oct 15 12:43:12 PM UTC 24 |
9725631016 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.4138825646 |
|
|
Oct 15 12:43:06 PM UTC 24 |
Oct 15 12:43:16 PM UTC 24 |
581888347 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2597302303 |
|
|
Oct 15 12:43:05 PM UTC 24 |
Oct 15 12:43:18 PM UTC 24 |
974361698 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.3168256136 |
|
|
Oct 15 12:43:13 PM UTC 24 |
Oct 15 12:43:20 PM UTC 24 |
1306808921 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.2180028929 |
|
|
Oct 15 12:43:12 PM UTC 24 |
Oct 15 12:43:22 PM UTC 24 |
1366019166 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3180340816 |
|
|
Oct 15 12:41:19 PM UTC 24 |
Oct 15 12:43:24 PM UTC 24 |
7127803827 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.954245940 |
|
|
Oct 15 12:43:06 PM UTC 24 |
Oct 15 12:43:25 PM UTC 24 |
9276465845 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.1761907383 |
|
|
Oct 15 12:43:25 PM UTC 24 |
Oct 15 12:43:28 PM UTC 24 |
41271337 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.2885748498 |
|
|
Oct 15 12:43:26 PM UTC 24 |
Oct 15 12:43:29 PM UTC 24 |
29237737 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.4024235423 |
|
|
Oct 15 12:36:29 PM UTC 24 |
Oct 15 12:43:29 PM UTC 24 |
389214178464 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.895170575 |
|
|
Oct 15 12:42:46 PM UTC 24 |
Oct 15 12:43:30 PM UTC 24 |
17515762317 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.2594829792 |
|
|
Oct 15 12:43:02 PM UTC 24 |
Oct 15 12:43:30 PM UTC 24 |
7484444268 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.2437301024 |
|
|
Oct 15 12:42:11 PM UTC 24 |
Oct 15 12:43:31 PM UTC 24 |
18709371176 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3320571426 |
|
|
Oct 15 12:42:18 PM UTC 24 |
Oct 15 12:43:32 PM UTC 24 |
14965481808 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1514881885 |
|
|
Oct 15 12:43:31 PM UTC 24 |
Oct 15 12:43:34 PM UTC 24 |
189399346 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.1650800842 |
|
|
Oct 15 12:43:31 PM UTC 24 |
Oct 15 12:43:34 PM UTC 24 |
30219145 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.3095790401 |
|
|
Oct 15 12:42:22 PM UTC 24 |
Oct 15 12:43:34 PM UTC 24 |
4524651473 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.333115194 |
|
|
Oct 15 12:44:38 PM UTC 24 |
Oct 15 12:44:40 PM UTC 24 |
44299330 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1517950335 |
|
|
Oct 15 12:43:08 PM UTC 24 |
Oct 15 12:43:34 PM UTC 24 |
18033848306 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.982284736 |
|
|
Oct 15 12:43:30 PM UTC 24 |
Oct 15 12:43:38 PM UTC 24 |
2322549751 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.3439297182 |
|
|
Oct 15 12:43:36 PM UTC 24 |
Oct 15 12:43:41 PM UTC 24 |
170331021 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.502162759 |
|
|
Oct 15 12:43:34 PM UTC 24 |
Oct 15 12:43:43 PM UTC 24 |
2742026116 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.772578030 |
|
|
Oct 15 12:43:36 PM UTC 24 |
Oct 15 12:43:44 PM UTC 24 |
177248583 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.1549132929 |
|
|
Oct 15 12:41:59 PM UTC 24 |
Oct 15 12:43:45 PM UTC 24 |
16487071641 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1730799411 |
|
|
Oct 15 12:43:32 PM UTC 24 |
Oct 15 12:43:46 PM UTC 24 |
7666814317 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.217978197 |
|
|
Oct 15 12:43:35 PM UTC 24 |
Oct 15 12:43:46 PM UTC 24 |
1086556138 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.3706046220 |
|
|
Oct 15 12:43:23 PM UTC 24 |
Oct 15 12:43:48 PM UTC 24 |
1486693405 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.2973914568 |
|
|
Oct 15 12:43:48 PM UTC 24 |
Oct 15 12:43:50 PM UTC 24 |
12117913 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.3682407412 |
|
|
Oct 15 12:43:18 PM UTC 24 |
Oct 15 12:43:50 PM UTC 24 |
2227585517 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1256907969 |
|
|
Oct 15 12:42:22 PM UTC 24 |
Oct 15 12:43:50 PM UTC 24 |
4501893664 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.3990756383 |
|
|
Oct 15 12:43:50 PM UTC 24 |
Oct 15 12:43:52 PM UTC 24 |
19336410 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3724487329 |
|
|
Oct 15 12:43:29 PM UTC 24 |
Oct 15 12:43:53 PM UTC 24 |
2959205418 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.1303877625 |
|
|
Oct 15 12:43:51 PM UTC 24 |
Oct 15 12:43:54 PM UTC 24 |
59515800 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.2687129483 |
|
|
Oct 15 12:43:42 PM UTC 24 |
Oct 15 12:43:54 PM UTC 24 |
2054584515 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.2161591662 |
|
|
Oct 15 12:43:51 PM UTC 24 |
Oct 15 12:43:55 PM UTC 24 |
122171859 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.1712412387 |
|
|
Oct 15 12:43:54 PM UTC 24 |
Oct 15 12:43:56 PM UTC 24 |
79146445 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.3326116361 |
|
|
Oct 15 12:32:12 PM UTC 24 |
Oct 15 12:43:57 PM UTC 24 |
286875631692 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.1596060673 |
|
|
Oct 15 12:43:55 PM UTC 24 |
Oct 15 12:43:59 PM UTC 24 |
566289383 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.1721982335 |
|
|
Oct 15 12:43:58 PM UTC 24 |
Oct 15 12:44:02 PM UTC 24 |
183605813 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2168692054 |
|
|
Oct 15 12:43:54 PM UTC 24 |
Oct 15 12:44:02 PM UTC 24 |
362256373 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.3591750765 |
|
|
Oct 15 12:43:35 PM UTC 24 |
Oct 15 12:44:03 PM UTC 24 |
5380059949 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.1521395414 |
|
|
Oct 15 12:44:00 PM UTC 24 |
Oct 15 12:44:05 PM UTC 24 |
76692296 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.84135371 |
|
|
Oct 15 12:43:51 PM UTC 24 |
Oct 15 12:44:12 PM UTC 24 |
10755364596 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2732959403 |
|
|
Oct 15 12:39:56 PM UTC 24 |
Oct 15 12:44:12 PM UTC 24 |
20275587313 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.652374016 |
|
|
Oct 15 12:43:56 PM UTC 24 |
Oct 15 12:44:13 PM UTC 24 |
6931876793 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.881588668 |
|
|
Oct 15 12:44:14 PM UTC 24 |
Oct 15 12:44:17 PM UTC 24 |
77229767 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.2373830777 |
|
|
Oct 15 12:43:55 PM UTC 24 |
Oct 15 12:44:19 PM UTC 24 |
3333111718 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.396268568 |
|
|
Oct 15 12:44:03 PM UTC 24 |
Oct 15 12:44:19 PM UTC 24 |
1025817338 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.3195028931 |
|
|
Oct 15 12:44:18 PM UTC 24 |
Oct 15 12:44:20 PM UTC 24 |
17209663 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.1623601579 |
|
|
Oct 15 12:44:20 PM UTC 24 |
Oct 15 12:44:22 PM UTC 24 |
62858582 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.4162715115 |
|
|
Oct 15 12:43:31 PM UTC 24 |
Oct 15 12:44:23 PM UTC 24 |
30027998287 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2186599880 |
|
|
Oct 15 12:44:21 PM UTC 24 |
Oct 15 12:44:24 PM UTC 24 |
144849660 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2842719974 |
|
|
Oct 15 12:43:40 PM UTC 24 |
Oct 15 12:44:24 PM UTC 24 |
48620098777 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.2110822189 |
|
|
Oct 15 12:43:56 PM UTC 24 |
Oct 15 12:44:29 PM UTC 24 |
2940672782 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.2784714761 |
|
|
Oct 15 12:44:24 PM UTC 24 |
Oct 15 12:44:29 PM UTC 24 |
897394629 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2133681630 |
|
|
Oct 15 12:37:57 PM UTC 24 |
Oct 15 12:44:30 PM UTC 24 |
27455314035 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.3644735864 |
|
|
Oct 15 12:44:25 PM UTC 24 |
Oct 15 12:44:31 PM UTC 24 |
1635402413 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.298931753 |
|
|
Oct 15 12:44:06 PM UTC 24 |
Oct 15 12:44:32 PM UTC 24 |
14641691499 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.1969201805 |
|
|
Oct 15 12:44:13 PM UTC 24 |
Oct 15 12:44:33 PM UTC 24 |
2987303833 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.866419425 |
|
|
Oct 15 12:42:41 PM UTC 24 |
Oct 15 12:44:34 PM UTC 24 |
4995121225 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.1772546708 |
|
|
Oct 15 12:44:20 PM UTC 24 |
Oct 15 12:44:36 PM UTC 24 |
1912041263 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.1295410804 |
|
|
Oct 15 12:39:21 PM UTC 24 |
Oct 15 12:44:36 PM UTC 24 |
41497092512 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.845053320 |
|
|
Oct 15 12:44:31 PM UTC 24 |
Oct 15 12:44:36 PM UTC 24 |
566255420 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.3491676502 |
|
|
Oct 15 12:40:42 PM UTC 24 |
Oct 15 12:44:37 PM UTC 24 |
28029053983 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.1315770327 |
|
|
Oct 15 12:44:25 PM UTC 24 |
Oct 15 12:44:40 PM UTC 24 |
868115575 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.3227816644 |
|
|
Oct 15 12:44:24 PM UTC 24 |
Oct 15 12:44:40 PM UTC 24 |
2142568328 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.2975160460 |
|
|
Oct 15 12:44:34 PM UTC 24 |
Oct 15 12:44:41 PM UTC 24 |
148614473 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.3635215521 |
|
|
Oct 15 12:44:41 PM UTC 24 |
Oct 15 12:44:44 PM UTC 24 |
27530230 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.1537005975 |
|
|
Oct 15 12:41:22 PM UTC 24 |
Oct 15 12:44:44 PM UTC 24 |
13086588866 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.3772081417 |
|
|
Oct 15 12:44:43 PM UTC 24 |
Oct 15 12:44:45 PM UTC 24 |
30325804 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2082184513 |
|
|
Oct 15 12:43:45 PM UTC 24 |
Oct 15 12:44:46 PM UTC 24 |
4103573050 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.4120769874 |
|
|
Oct 15 12:44:47 PM UTC 24 |
Oct 15 12:44:51 PM UTC 24 |
97176708 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3601591005 |
|
|
Oct 15 12:44:45 PM UTC 24 |
Oct 15 12:44:52 PM UTC 24 |
469662901 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.909609097 |
|
|
Oct 15 12:44:42 PM UTC 24 |
Oct 15 12:44:55 PM UTC 24 |
5292441180 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.2502302143 |
|
|
Oct 15 12:44:44 PM UTC 24 |
Oct 15 12:44:55 PM UTC 24 |
552426893 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.3287047184 |
|
|
Oct 15 12:44:47 PM UTC 24 |
Oct 15 12:44:58 PM UTC 24 |
2311624343 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.1086151527 |
|
|
Oct 15 12:44:41 PM UTC 24 |
Oct 15 12:45:00 PM UTC 24 |
1981329723 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.125099124 |
|
|
Oct 15 12:44:04 PM UTC 24 |
Oct 15 12:45:01 PM UTC 24 |
2887704980 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.3368642482 |
|
|
Oct 15 12:44:56 PM UTC 24 |
Oct 15 12:45:02 PM UTC 24 |
121175285 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1208976001 |
|
|
Oct 15 12:44:56 PM UTC 24 |
Oct 15 12:45:04 PM UTC 24 |
2465364796 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.2166949181 |
|
|
Oct 15 12:37:34 PM UTC 24 |
Oct 15 12:45:06 PM UTC 24 |
189093943298 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.2870370481 |
|
|
Oct 15 12:44:52 PM UTC 24 |
Oct 15 12:45:08 PM UTC 24 |
2341405587 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.128285703 |
|
|
Oct 15 12:43:44 PM UTC 24 |
Oct 15 12:45:10 PM UTC 24 |
27082992785 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.225199267 |
|
|
Oct 15 12:44:31 PM UTC 24 |
Oct 15 12:45:10 PM UTC 24 |
27543388212 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.4122382632 |
|
|
Oct 15 12:45:09 PM UTC 24 |
Oct 15 12:45:11 PM UTC 24 |
43493180 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.3722661156 |
|
|
Oct 15 12:45:00 PM UTC 24 |
Oct 15 12:45:13 PM UTC 24 |
4556865707 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.2720275081 |
|
|
Oct 15 12:45:11 PM UTC 24 |
Oct 15 12:45:13 PM UTC 24 |
84102201 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.548350381 |
|
|
Oct 15 12:45:14 PM UTC 24 |
Oct 15 12:45:16 PM UTC 24 |
172346003 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.2302650739 |
|
|
Oct 15 12:44:33 PM UTC 24 |
Oct 15 12:45:19 PM UTC 24 |
9021866355 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3516405615 |
|
|
Oct 15 12:45:11 PM UTC 24 |
Oct 15 12:45:20 PM UTC 24 |
913444585 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1388647856 |
|
|
Oct 15 12:43:20 PM UTC 24 |
Oct 15 12:45:22 PM UTC 24 |
13956488299 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1164831307 |
|
|
Oct 15 12:47:57 PM UTC 24 |
Oct 15 12:48:05 PM UTC 24 |
3037321012 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.836003437 |
|
|
Oct 15 12:45:15 PM UTC 24 |
Oct 15 12:45:23 PM UTC 24 |
479866613 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.2883328969 |
|
|
Oct 15 12:36:27 PM UTC 24 |
Oct 15 12:45:27 PM UTC 24 |
105724499573 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.2401827227 |
|
|
Oct 15 12:45:21 PM UTC 24 |
Oct 15 12:45:27 PM UTC 24 |
136831009 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.1148737751 |
|
|
Oct 15 12:45:24 PM UTC 24 |
Oct 15 12:45:29 PM UTC 24 |
208004333 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.3553882127 |
|
|
Oct 15 12:45:21 PM UTC 24 |
Oct 15 12:45:29 PM UTC 24 |
759607395 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.3861453339 |
|
|
Oct 15 12:44:38 PM UTC 24 |
Oct 15 12:45:30 PM UTC 24 |
2319565829 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3924884460 |
|
|
Oct 15 12:45:27 PM UTC 24 |
Oct 15 12:45:31 PM UTC 24 |
147495024 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.1716572497 |
|
|
Oct 15 12:44:38 PM UTC 24 |
Oct 15 12:45:32 PM UTC 24 |
11605482872 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1851937196 |
|
|
Oct 15 12:38:47 PM UTC 24 |
Oct 15 12:45:33 PM UTC 24 |
64280350975 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.1950656643 |
|
|
Oct 15 12:45:23 PM UTC 24 |
Oct 15 12:45:34 PM UTC 24 |
2567486248 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.3741950996 |
|
|
Oct 15 12:43:21 PM UTC 24 |
Oct 15 12:45:35 PM UTC 24 |
28495006967 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.907464628 |
|
|
Oct 15 12:45:30 PM UTC 24 |
Oct 15 12:45:35 PM UTC 24 |
73531440 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.2702803245 |
|
|
Oct 15 12:45:34 PM UTC 24 |
Oct 15 12:45:37 PM UTC 24 |
10846562 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.752624192 |
|
|
Oct 15 12:44:03 PM UTC 24 |
Oct 15 12:45:37 PM UTC 24 |
8946500782 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.3734402203 |
|
|
Oct 15 12:45:36 PM UTC 24 |
Oct 15 12:45:38 PM UTC 24 |
13701067 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.977032228 |
|
|
Oct 15 12:45:37 PM UTC 24 |
Oct 15 12:45:39 PM UTC 24 |
34683079 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.4294136561 |
|
|
Oct 15 12:45:36 PM UTC 24 |
Oct 15 12:45:39 PM UTC 24 |
514479639 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2467430232 |
|
|
Oct 15 12:45:38 PM UTC 24 |
Oct 15 12:45:41 PM UTC 24 |
35570420 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.273924222 |
|
|
Oct 15 12:45:17 PM UTC 24 |
Oct 15 12:45:41 PM UTC 24 |
4308596478 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.479270436 |
|
|
Oct 15 12:45:11 PM UTC 24 |
Oct 15 12:45:43 PM UTC 24 |
15878699829 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.2738524632 |
|
|
Oct 15 12:44:31 PM UTC 24 |
Oct 15 12:45:43 PM UTC 24 |
27929284559 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.262488060 |
|
|
Oct 15 12:45:38 PM UTC 24 |
Oct 15 12:45:44 PM UTC 24 |
68696834 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2043951521 |
|
|
Oct 15 12:45:40 PM UTC 24 |
Oct 15 12:45:46 PM UTC 24 |
548885035 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.1428713441 |
|
|
Oct 15 12:45:43 PM UTC 24 |
Oct 15 12:45:48 PM UTC 24 |
233270081 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1921346874 |
|
|
Oct 15 12:44:36 PM UTC 24 |
Oct 15 12:45:51 PM UTC 24 |
17746788677 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.3763497961 |
|
|
Oct 15 12:45:44 PM UTC 24 |
Oct 15 12:45:51 PM UTC 24 |
692663028 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.3972265633 |
|
|
Oct 15 12:38:29 PM UTC 24 |
Oct 15 12:45:52 PM UTC 24 |
361475242123 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.3575197555 |
|
|
Oct 15 12:45:43 PM UTC 24 |
Oct 15 12:45:54 PM UTC 24 |
1342639693 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.1191616517 |
|
|
Oct 15 12:44:52 PM UTC 24 |
Oct 15 12:45:55 PM UTC 24 |
5945745728 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.4272653235 |
|
|
Oct 15 12:43:00 PM UTC 24 |
Oct 15 12:45:55 PM UTC 24 |
12308664996 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.660099625 |
|
|
Oct 15 12:45:33 PM UTC 24 |
Oct 15 12:45:56 PM UTC 24 |
1092789142 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1028776998 |
|
|
Oct 15 12:44:33 PM UTC 24 |
Oct 15 12:45:57 PM UTC 24 |
12255777703 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.1213697928 |
|
|
Oct 15 12:45:44 PM UTC 24 |
Oct 15 12:45:57 PM UTC 24 |
1430057039 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.2348448737 |
|
|
Oct 15 12:45:55 PM UTC 24 |
Oct 15 12:45:57 PM UTC 24 |
21000432 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.3286459766 |
|
|
Oct 15 12:44:13 PM UTC 24 |
Oct 15 12:45:58 PM UTC 24 |
39183675770 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.1914945990 |
|
|
Oct 15 12:45:56 PM UTC 24 |
Oct 15 12:45:58 PM UTC 24 |
39584643 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.3796996488 |
|
|
Oct 15 12:45:47 PM UTC 24 |
Oct 15 12:45:59 PM UTC 24 |
17083323586 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.3565184642 |
|
|
Oct 15 12:45:58 PM UTC 24 |
Oct 15 12:46:00 PM UTC 24 |
99879379 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.2443647423 |
|
|
Oct 15 12:45:58 PM UTC 24 |
Oct 15 12:46:00 PM UTC 24 |
107056305 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.1907705056 |
|
|
Oct 15 12:45:41 PM UTC 24 |
Oct 15 12:46:00 PM UTC 24 |
11076009374 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3888493593 |
|
|
Oct 15 12:43:46 PM UTC 24 |
Oct 15 12:46:05 PM UTC 24 |
216169863855 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.912875802 |
|
|
Oct 15 12:38:49 PM UTC 24 |
Oct 15 12:46:06 PM UTC 24 |
39967122992 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.1942809828 |
|
|
Oct 15 12:45:41 PM UTC 24 |
Oct 15 12:46:06 PM UTC 24 |
31112242200 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.2151465186 |
|
|
Oct 15 12:46:02 PM UTC 24 |
Oct 15 12:46:06 PM UTC 24 |
217926864 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.1411657519 |
|
|
Oct 15 12:46:00 PM UTC 24 |
Oct 15 12:46:07 PM UTC 24 |
1170329815 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.1143606840 |
|
|
Oct 15 12:44:58 PM UTC 24 |
Oct 15 12:46:07 PM UTC 24 |
3588654164 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.1935768113 |
|
|
Oct 15 12:45:56 PM UTC 24 |
Oct 15 12:46:08 PM UTC 24 |
2516751526 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.1607012618 |
|
|
Oct 15 12:48:03 PM UTC 24 |
Oct 15 12:48:05 PM UTC 24 |
57827757 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2441773963 |
|
|
Oct 15 12:45:44 PM UTC 24 |
Oct 15 12:46:12 PM UTC 24 |
2998468439 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.434570777 |
|
|
Oct 15 12:46:10 PM UTC 24 |
Oct 15 12:46:12 PM UTC 24 |
44588266 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2344488287 |
|
|
Oct 15 12:45:58 PM UTC 24 |
Oct 15 12:46:13 PM UTC 24 |
18031298976 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.8358094 |
|
|
Oct 15 12:46:08 PM UTC 24 |
Oct 15 12:46:13 PM UTC 24 |
878888142 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.1592011330 |
|
|
Oct 15 12:46:12 PM UTC 24 |
Oct 15 12:46:14 PM UTC 24 |
41791199 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.1549323051 |
|
|
Oct 15 12:46:02 PM UTC 24 |
Oct 15 12:46:15 PM UTC 24 |
9271743854 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.3279170244 |
|
|
Oct 15 12:46:08 PM UTC 24 |
Oct 15 12:46:16 PM UTC 24 |
241731931 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.3927878227 |
|
|
Oct 15 12:46:02 PM UTC 24 |
Oct 15 12:46:17 PM UTC 24 |
2446444549 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.1997474791 |
|
|
Oct 15 12:45:58 PM UTC 24 |
Oct 15 12:46:17 PM UTC 24 |
1153817945 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.4172175406 |
|
|
Oct 15 12:46:15 PM UTC 24 |
Oct 15 12:46:18 PM UTC 24 |
325169151 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2083394550 |
|
|
Oct 15 12:46:13 PM UTC 24 |
Oct 15 12:46:18 PM UTC 24 |
944149154 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.426074138 |
|
|
Oct 15 12:46:15 PM UTC 24 |
Oct 15 12:46:18 PM UTC 24 |
78643828 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.3427096217 |
|
|
Oct 15 12:46:00 PM UTC 24 |
Oct 15 12:46:19 PM UTC 24 |
12664180508 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1846341300 |
|
|
Oct 15 12:42:57 PM UTC 24 |
Oct 15 12:46:21 PM UTC 24 |
36665175961 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.1710541855 |
|
|
Oct 15 12:46:20 PM UTC 24 |
Oct 15 12:46:24 PM UTC 24 |
986677886 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.768764688 |
|
|
Oct 15 12:46:17 PM UTC 24 |
Oct 15 12:46:27 PM UTC 24 |
1329112445 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1563666234 |
|
|
Oct 15 12:46:22 PM UTC 24 |
Oct 15 12:46:30 PM UTC 24 |
106463792 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.944633536 |
|
|
Oct 15 12:46:20 PM UTC 24 |
Oct 15 12:46:35 PM UTC 24 |
4426033782 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.452687009 |
|
|
Oct 15 12:46:20 PM UTC 24 |
Oct 15 12:46:37 PM UTC 24 |
6167934191 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2917361506 |
|
|
Oct 15 12:46:17 PM UTC 24 |
Oct 15 12:46:37 PM UTC 24 |
11572638140 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.256171302 |
|
|
Oct 15 12:46:35 PM UTC 24 |
Oct 15 12:46:38 PM UTC 24 |
71338903 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.1611096052 |
|
|
Oct 15 12:45:29 PM UTC 24 |
Oct 15 12:46:40 PM UTC 24 |
13755932025 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.875390586 |
|
|
Oct 15 12:46:38 PM UTC 24 |
Oct 15 12:46:40 PM UTC 24 |
47869430 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.1947849634 |
|
|
Oct 15 12:46:38 PM UTC 24 |
Oct 15 12:46:40 PM UTC 24 |
33263299 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2475465328 |
|
|
Oct 15 12:46:42 PM UTC 24 |
Oct 15 12:46:44 PM UTC 24 |
85852007 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.211750728 |
|
|
Oct 15 12:46:42 PM UTC 24 |
Oct 15 12:46:45 PM UTC 24 |
148320331 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.2741417804 |
|
|
Oct 15 12:46:18 PM UTC 24 |
Oct 15 12:46:48 PM UTC 24 |
4808064728 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.252919410 |
|
|
Oct 15 12:46:20 PM UTC 24 |
Oct 15 12:46:48 PM UTC 24 |
3814402389 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.2202055289 |
|
|
Oct 15 12:46:39 PM UTC 24 |
Oct 15 12:46:51 PM UTC 24 |
1970971442 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.1097610247 |
|
|
Oct 15 12:46:45 PM UTC 24 |
Oct 15 12:46:56 PM UTC 24 |
220509981 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.650680477 |
|
|
Oct 15 12:46:45 PM UTC 24 |
Oct 15 12:46:57 PM UTC 24 |
23718006579 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.3886135702 |
|
|
Oct 15 12:46:52 PM UTC 24 |
Oct 15 12:46:58 PM UTC 24 |
1405049416 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.2675703163 |
|
|
Oct 15 12:46:50 PM UTC 24 |
Oct 15 12:46:59 PM UTC 24 |
1166980106 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.4066086197 |
|
|
Oct 15 12:46:15 PM UTC 24 |
Oct 15 12:46:59 PM UTC 24 |
6248446534 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.473546725 |
|
|
Oct 15 12:47:00 PM UTC 24 |
Oct 15 12:47:02 PM UTC 24 |
22842349 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.3897986719 |
|
|
Oct 15 12:45:53 PM UTC 24 |
Oct 15 12:47:03 PM UTC 24 |
17570144007 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1628619973 |
|
|
Oct 15 12:46:57 PM UTC 24 |
Oct 15 12:47:05 PM UTC 24 |
308464335 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.582108296 |
|
|
Oct 15 12:47:00 PM UTC 24 |
Oct 15 12:47:10 PM UTC 24 |
1024339950 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.959200616 |
|
|
Oct 15 12:47:11 PM UTC 24 |
Oct 15 12:47:13 PM UTC 24 |
30359891 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.1405632123 |
|
|
Oct 15 12:35:53 PM UTC 24 |
Oct 15 12:47:14 PM UTC 24 |
149929959896 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.3895725957 |
|
|
Oct 15 12:46:42 PM UTC 24 |
Oct 15 12:47:14 PM UTC 24 |
16148153830 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.3370254984 |
|
|
Oct 15 12:46:25 PM UTC 24 |
Oct 15 12:47:16 PM UTC 24 |
2240096566 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.1177206887 |
|
|
Oct 15 12:47:15 PM UTC 24 |
Oct 15 12:47:17 PM UTC 24 |
34659248 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.4244493076 |
|
|
Oct 15 12:47:15 PM UTC 24 |
Oct 15 12:47:17 PM UTC 24 |
29420767 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2566829536 |
|
|
Oct 15 12:47:17 PM UTC 24 |
Oct 15 12:47:19 PM UTC 24 |
13290467 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.3301979354 |
|
|
Oct 15 12:47:19 PM UTC 24 |
Oct 15 12:47:23 PM UTC 24 |
917002171 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1537469866 |
|
|
Oct 15 12:47:19 PM UTC 24 |
Oct 15 12:47:28 PM UTC 24 |
234713763 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.1612923863 |
|
|
Oct 15 12:46:50 PM UTC 24 |
Oct 15 12:47:28 PM UTC 24 |
4339996370 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.1086250897 |
|
|
Oct 15 12:47:24 PM UTC 24 |
Oct 15 12:47:31 PM UTC 24 |
311974302 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.618912606 |
|
|
Oct 15 12:41:52 PM UTC 24 |
Oct 15 12:47:33 PM UTC 24 |
123657117536 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.218964862 |
|
|
Oct 15 12:45:05 PM UTC 24 |
Oct 15 12:47:33 PM UTC 24 |
5015166547 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.1352129818 |
|
|
Oct 15 12:47:32 PM UTC 24 |
Oct 15 12:47:36 PM UTC 24 |
28950954 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.3962721758 |
|
|
Oct 15 12:47:33 PM UTC 24 |
Oct 15 12:47:37 PM UTC 24 |
58918660 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.1215797418 |
|
|
Oct 15 12:47:20 PM UTC 24 |
Oct 15 12:47:40 PM UTC 24 |
38746927325 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.2842793258 |
|
|
Oct 15 12:47:30 PM UTC 24 |
Oct 15 12:47:41 PM UTC 24 |
857735161 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.120665582 |
|
|
Oct 15 12:47:42 PM UTC 24 |
Oct 15 12:47:44 PM UTC 24 |
86347791 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.3129259600 |
|
|
Oct 15 12:45:31 PM UTC 24 |
Oct 15 12:47:46 PM UTC 24 |
25323406866 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.1935455124 |
|
|
Oct 15 12:47:30 PM UTC 24 |
Oct 15 12:47:48 PM UTC 24 |
3243434512 ps |