| T820 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.967415898 |
|
|
Oct 15 12:47:04 PM UTC 24 |
Oct 15 12:47:48 PM UTC 24 |
1069942129 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.2273499743 |
|
|
Oct 15 12:47:47 PM UTC 24 |
Oct 15 12:47:49 PM UTC 24 |
14298759 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.3088783789 |
|
|
Oct 15 12:45:51 PM UTC 24 |
Oct 15 12:47:50 PM UTC 24 |
19105390682 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.3636192210 |
|
|
Oct 15 12:47:48 PM UTC 24 |
Oct 15 12:47:51 PM UTC 24 |
16972406 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2467236356 |
|
|
Oct 15 12:47:37 PM UTC 24 |
Oct 15 12:47:51 PM UTC 24 |
7850682373 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.3426519379 |
|
|
Oct 15 12:47:51 PM UTC 24 |
Oct 15 12:47:54 PM UTC 24 |
108517867 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.154386726 |
|
|
Oct 15 12:45:33 PM UTC 24 |
Oct 15 12:47:54 PM UTC 24 |
8447692066 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.1829301540 |
|
|
Oct 15 12:47:51 PM UTC 24 |
Oct 15 12:47:54 PM UTC 24 |
277260193 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.2918397217 |
|
|
Oct 15 12:47:15 PM UTC 24 |
Oct 15 12:47:56 PM UTC 24 |
2071583372 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2131050737 |
|
|
Oct 15 12:47:53 PM UTC 24 |
Oct 15 12:47:57 PM UTC 24 |
143700186 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1052440903 |
|
|
Oct 15 12:46:21 PM UTC 24 |
Oct 15 12:47:57 PM UTC 24 |
15242961495 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2747279956 |
|
|
Oct 15 12:47:03 PM UTC 24 |
Oct 15 12:47:59 PM UTC 24 |
2403467776 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.1477105264 |
|
|
Oct 15 12:47:56 PM UTC 24 |
Oct 15 12:48:00 PM UTC 24 |
34149766 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.350907355 |
|
|
Oct 15 12:45:30 PM UTC 24 |
Oct 15 12:48:01 PM UTC 24 |
34290874593 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.3800015961 |
|
|
Oct 15 12:47:57 PM UTC 24 |
Oct 15 12:48:01 PM UTC 24 |
34514150 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.764267179 |
|
|
Oct 15 12:45:03 PM UTC 24 |
Oct 15 12:48:01 PM UTC 24 |
8288879841 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.3542178834 |
|
|
Oct 15 12:47:56 PM UTC 24 |
Oct 15 12:48:02 PM UTC 24 |
189919805 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.873556470 |
|
|
Oct 15 12:47:54 PM UTC 24 |
Oct 15 12:48:03 PM UTC 24 |
895124662 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.98272605 |
|
|
Oct 15 12:48:04 PM UTC 24 |
Oct 15 12:48:06 PM UTC 24 |
20255982 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.752475225 |
|
|
Oct 15 12:46:02 PM UTC 24 |
Oct 15 12:48:08 PM UTC 24 |
171160615388 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.1088058984 |
|
|
Oct 15 12:48:01 PM UTC 24 |
Oct 15 12:48:08 PM UTC 24 |
326759475 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.2562634225 |
|
|
Oct 15 12:47:35 PM UTC 24 |
Oct 15 12:48:09 PM UTC 24 |
2913540067 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.2986578766 |
|
|
Oct 15 12:48:07 PM UTC 24 |
Oct 15 12:48:09 PM UTC 24 |
14156327 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3914922788 |
|
|
Oct 15 12:46:31 PM UTC 24 |
Oct 15 12:48:10 PM UTC 24 |
110639803758 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.4206635955 |
|
|
Oct 15 12:47:50 PM UTC 24 |
Oct 15 12:48:11 PM UTC 24 |
8084724803 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.838171880 |
|
|
Oct 15 12:48:10 PM UTC 24 |
Oct 15 12:48:13 PM UTC 24 |
132376882 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.3787569344 |
|
|
Oct 15 12:48:10 PM UTC 24 |
Oct 15 12:48:13 PM UTC 24 |
126636671 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.1128717132 |
|
|
Oct 15 12:46:58 PM UTC 24 |
Oct 15 12:48:13 PM UTC 24 |
3738885956 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.2939930691 |
|
|
Oct 15 12:40:43 PM UTC 24 |
Oct 15 12:48:18 PM UTC 24 |
63829273183 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.1106177977 |
|
|
Oct 15 12:47:58 PM UTC 24 |
Oct 15 12:48:18 PM UTC 24 |
14583430780 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.732826388 |
|
|
Oct 15 12:48:11 PM UTC 24 |
Oct 15 12:48:19 PM UTC 24 |
643284555 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.3426894106 |
|
|
Oct 15 12:48:08 PM UTC 24 |
Oct 15 12:48:20 PM UTC 24 |
5254713319 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.2544716437 |
|
|
Oct 15 12:48:14 PM UTC 24 |
Oct 15 12:48:22 PM UTC 24 |
1082557736 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.240675826 |
|
|
Oct 15 12:48:10 PM UTC 24 |
Oct 15 12:48:23 PM UTC 24 |
5743436848 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.3271709395 |
|
|
Oct 15 12:47:38 PM UTC 24 |
Oct 15 12:48:24 PM UTC 24 |
1250267730 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2715298047 |
|
|
Oct 15 12:48:07 PM UTC 24 |
Oct 15 12:48:24 PM UTC 24 |
12774922887 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.839737446 |
|
|
Oct 15 12:47:50 PM UTC 24 |
Oct 15 12:48:26 PM UTC 24 |
6278621834 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2353216809 |
|
|
Oct 15 12:46:08 PM UTC 24 |
Oct 15 12:48:27 PM UTC 24 |
132066375942 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.229116187 |
|
|
Oct 15 12:48:25 PM UTC 24 |
Oct 15 12:48:28 PM UTC 24 |
30187087 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.3527256596 |
|
|
Oct 15 12:48:25 PM UTC 24 |
Oct 15 12:48:28 PM UTC 24 |
18407345 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2903411363 |
|
|
Oct 15 12:48:14 PM UTC 24 |
Oct 15 12:48:30 PM UTC 24 |
3568920859 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3517091979 |
|
|
Oct 15 12:48:29 PM UTC 24 |
Oct 15 12:48:32 PM UTC 24 |
89162199 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2347498135 |
|
|
Oct 15 12:48:19 PM UTC 24 |
Oct 15 12:48:33 PM UTC 24 |
2069811612 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.1387540336 |
|
|
Oct 15 12:48:30 PM UTC 24 |
Oct 15 12:48:35 PM UTC 24 |
176834638 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.2780770304 |
|
|
Oct 15 12:48:19 PM UTC 24 |
Oct 15 12:48:36 PM UTC 24 |
4187836745 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.276727443 |
|
|
Oct 15 12:48:10 PM UTC 24 |
Oct 15 12:48:37 PM UTC 24 |
28465532321 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2112599590 |
|
|
Oct 15 12:48:19 PM UTC 24 |
Oct 15 12:48:38 PM UTC 24 |
1312151006 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.4187031635 |
|
|
Oct 15 12:43:48 PM UTC 24 |
Oct 15 12:48:38 PM UTC 24 |
400415275747 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.221616040 |
|
|
Oct 15 12:48:31 PM UTC 24 |
Oct 15 12:48:42 PM UTC 24 |
2568647730 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.256319019 |
|
|
Oct 15 12:48:13 PM UTC 24 |
Oct 15 12:48:43 PM UTC 24 |
4930927290 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.2782252932 |
|
|
Oct 15 12:47:00 PM UTC 24 |
Oct 15 12:48:43 PM UTC 24 |
51282668641 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.2855661485 |
|
|
Oct 15 12:48:38 PM UTC 24 |
Oct 15 12:48:45 PM UTC 24 |
222906396 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1688951325 |
|
|
Oct 15 12:48:27 PM UTC 24 |
Oct 15 12:48:48 PM UTC 24 |
104574997901 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2785572195 |
|
|
Oct 15 12:48:43 PM UTC 24 |
Oct 15 12:48:49 PM UTC 24 |
630243257 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.2499037975 |
|
|
Oct 15 12:48:49 PM UTC 24 |
Oct 15 12:48:52 PM UTC 24 |
106867399 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.1236164735 |
|
|
Oct 15 12:48:50 PM UTC 24 |
Oct 15 12:48:52 PM UTC 24 |
40438313 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1811617855 |
|
|
Oct 15 12:48:03 PM UTC 24 |
Oct 15 12:48:53 PM UTC 24 |
10566411904 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.2906588922 |
|
|
Oct 15 12:48:53 PM UTC 24 |
Oct 15 12:48:55 PM UTC 24 |
51109584 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.1721463433 |
|
|
Oct 15 12:48:37 PM UTC 24 |
Oct 15 12:48:57 PM UTC 24 |
4504250618 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3051702566 |
|
|
Oct 15 12:47:42 PM UTC 24 |
Oct 15 12:48:57 PM UTC 24 |
3811100816 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.1598645857 |
|
|
Oct 15 12:48:34 PM UTC 24 |
Oct 15 12:48:57 PM UTC 24 |
2918188463 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3762376222 |
|
|
Oct 15 12:48:55 PM UTC 24 |
Oct 15 12:48:58 PM UTC 24 |
229974984 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1070177601 |
|
|
Oct 15 12:48:33 PM UTC 24 |
Oct 15 12:48:59 PM UTC 24 |
32464431097 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3428310487 |
|
|
Oct 15 12:48:40 PM UTC 24 |
Oct 15 12:49:00 PM UTC 24 |
1242941906 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.752849712 |
|
|
Oct 15 12:48:58 PM UTC 24 |
Oct 15 12:49:03 PM UTC 24 |
72221760 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.745436382 |
|
|
Oct 15 12:48:55 PM UTC 24 |
Oct 15 12:49:03 PM UTC 24 |
1338130801 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.2709236612 |
|
|
Oct 15 12:48:36 PM UTC 24 |
Oct 15 12:49:04 PM UTC 24 |
2199955422 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.3441419904 |
|
|
Oct 15 12:48:58 PM UTC 24 |
Oct 15 12:49:05 PM UTC 24 |
1244960249 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1087520176 |
|
|
Oct 15 12:48:54 PM UTC 24 |
Oct 15 12:49:06 PM UTC 24 |
1117092431 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3099915730 |
|
|
Oct 15 12:48:58 PM UTC 24 |
Oct 15 12:49:08 PM UTC 24 |
951776558 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1427243890 |
|
|
Oct 15 12:49:04 PM UTC 24 |
Oct 15 12:49:11 PM UTC 24 |
488907248 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3582770746 |
|
|
Oct 15 12:48:58 PM UTC 24 |
Oct 15 12:49:12 PM UTC 24 |
2752506069 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.2986426641 |
|
|
Oct 15 12:48:15 PM UTC 24 |
Oct 15 12:49:12 PM UTC 24 |
21749178746 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.2478490099 |
|
|
Oct 15 12:49:01 PM UTC 24 |
Oct 15 12:49:14 PM UTC 24 |
1226774055 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2098185945 |
|
|
Oct 15 12:49:06 PM UTC 24 |
Oct 15 12:49:15 PM UTC 24 |
1361284896 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.4224889972 |
|
|
Oct 15 12:49:13 PM UTC 24 |
Oct 15 12:49:15 PM UTC 24 |
14308897 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.4105576806 |
|
|
Oct 15 12:49:13 PM UTC 24 |
Oct 15 12:49:16 PM UTC 24 |
40930575 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.1842362494 |
|
|
Oct 15 12:49:14 PM UTC 24 |
Oct 15 12:49:17 PM UTC 24 |
57996474 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.2318650759 |
|
|
Oct 15 12:44:35 PM UTC 24 |
Oct 15 12:49:17 PM UTC 24 |
278658761129 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.3245166822 |
|
|
Oct 15 12:49:17 PM UTC 24 |
Oct 15 12:49:19 PM UTC 24 |
123477944 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.3007365866 |
|
|
Oct 15 12:49:17 PM UTC 24 |
Oct 15 12:49:20 PM UTC 24 |
197924891 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.99240163 |
|
|
Oct 15 12:48:28 PM UTC 24 |
Oct 15 12:49:22 PM UTC 24 |
9107408822 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.1876923669 |
|
|
Oct 15 12:49:01 PM UTC 24 |
Oct 15 12:49:22 PM UTC 24 |
3278617954 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.3757559731 |
|
|
Oct 15 12:49:24 PM UTC 24 |
Oct 15 12:49:28 PM UTC 24 |
171502857 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.1162648416 |
|
|
Oct 15 12:49:21 PM UTC 24 |
Oct 15 12:49:29 PM UTC 24 |
575694339 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1599119137 |
|
|
Oct 15 12:48:21 PM UTC 24 |
Oct 15 12:49:30 PM UTC 24 |
6470390304 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1316229358 |
|
|
Oct 15 12:49:16 PM UTC 24 |
Oct 15 12:49:30 PM UTC 24 |
6012634590 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.265698530 |
|
|
Oct 15 12:42:23 PM UTC 24 |
Oct 15 12:49:30 PM UTC 24 |
77097181832 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.3326523456 |
|
|
Oct 15 12:49:19 PM UTC 24 |
Oct 15 12:49:31 PM UTC 24 |
2491207102 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.1930677173 |
|
|
Oct 15 12:49:04 PM UTC 24 |
Oct 15 12:49:33 PM UTC 24 |
3152656752 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.1845646430 |
|
|
Oct 15 12:49:16 PM UTC 24 |
Oct 15 12:49:35 PM UTC 24 |
13540884683 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3788030490 |
|
|
Oct 15 12:49:29 PM UTC 24 |
Oct 15 12:49:38 PM UTC 24 |
364856816 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.38233778 |
|
|
Oct 15 12:49:21 PM UTC 24 |
Oct 15 12:49:38 PM UTC 24 |
10377239995 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.3449362573 |
|
|
Oct 15 12:49:39 PM UTC 24 |
Oct 15 12:49:42 PM UTC 24 |
12840694 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.1339737752 |
|
|
Oct 15 12:49:39 PM UTC 24 |
Oct 15 12:49:42 PM UTC 24 |
39228777 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.1240773478 |
|
|
Oct 15 12:49:24 PM UTC 24 |
Oct 15 12:49:42 PM UTC 24 |
2707719296 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.417202992 |
|
|
Oct 15 12:49:32 PM UTC 24 |
Oct 15 12:49:43 PM UTC 24 |
273934449 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3769477094 |
|
|
Oct 15 12:49:32 PM UTC 24 |
Oct 15 12:49:43 PM UTC 24 |
1300220142 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1828314443 |
|
|
Oct 15 12:49:43 PM UTC 24 |
Oct 15 12:49:45 PM UTC 24 |
43037849 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.1614751729 |
|
|
Oct 15 12:49:45 PM UTC 24 |
Oct 15 12:49:48 PM UTC 24 |
256113949 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.987528489 |
|
|
Oct 15 12:49:30 PM UTC 24 |
Oct 15 12:49:49 PM UTC 24 |
2653362539 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3041382155 |
|
|
Oct 15 12:49:45 PM UTC 24 |
Oct 15 12:49:52 PM UTC 24 |
1156840411 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.1973751940 |
|
|
Oct 15 12:49:07 PM UTC 24 |
Oct 15 12:49:54 PM UTC 24 |
3549301606 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.3565493578 |
|
|
Oct 15 12:49:49 PM UTC 24 |
Oct 15 12:49:56 PM UTC 24 |
208886930 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.3478514529 |
|
|
Oct 15 12:49:53 PM UTC 24 |
Oct 15 12:49:57 PM UTC 24 |
352441803 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.1618686781 |
|
|
Oct 15 12:49:43 PM UTC 24 |
Oct 15 12:49:58 PM UTC 24 |
1702628084 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1780647749 |
|
|
Oct 15 12:49:55 PM UTC 24 |
Oct 15 12:50:00 PM UTC 24 |
356598997 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3104579949 |
|
|
Oct 15 12:49:43 PM UTC 24 |
Oct 15 12:50:00 PM UTC 24 |
5192778796 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.3666787679 |
|
|
Oct 15 12:49:51 PM UTC 24 |
Oct 15 12:50:02 PM UTC 24 |
3096292556 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.614859688 |
|
|
Oct 15 12:49:58 PM UTC 24 |
Oct 15 12:50:04 PM UTC 24 |
234086112 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.428866518 |
|
|
Oct 15 12:49:47 PM UTC 24 |
Oct 15 12:50:05 PM UTC 24 |
2310189796 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2230450284 |
|
|
Oct 15 12:49:59 PM UTC 24 |
Oct 15 12:50:06 PM UTC 24 |
2709280718 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.1339408755 |
|
|
Oct 15 12:50:07 PM UTC 24 |
Oct 15 12:50:09 PM UTC 24 |
114053817 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.2004369264 |
|
|
Oct 15 12:50:07 PM UTC 24 |
Oct 15 12:50:09 PM UTC 24 |
26869899 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.1965015175 |
|
|
Oct 15 12:45:53 PM UTC 24 |
Oct 15 12:50:17 PM UTC 24 |
65564473576 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.2689731942 |
|
|
Oct 15 12:48:40 PM UTC 24 |
Oct 15 12:50:19 PM UTC 24 |
9434356589 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.4060654357 |
|
|
Oct 15 12:50:18 PM UTC 24 |
Oct 15 12:50:21 PM UTC 24 |
128551352 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1063737979 |
|
|
Oct 15 12:50:20 PM UTC 24 |
Oct 15 12:50:22 PM UTC 24 |
51856795 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.2660412112 |
|
|
Oct 15 12:50:10 PM UTC 24 |
Oct 15 12:50:24 PM UTC 24 |
2173805135 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1288303318 |
|
|
Oct 15 12:50:10 PM UTC 24 |
Oct 15 12:50:26 PM UTC 24 |
1106961657 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.3796501196 |
|
|
Oct 15 12:45:49 PM UTC 24 |
Oct 15 12:50:29 PM UTC 24 |
198727556049 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1293751315 |
|
|
Oct 15 12:50:22 PM UTC 24 |
Oct 15 12:50:31 PM UTC 24 |
470490359 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.951887599 |
|
|
Oct 15 12:50:22 PM UTC 24 |
Oct 15 12:50:33 PM UTC 24 |
4806168368 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.2932142643 |
|
|
Oct 15 12:50:26 PM UTC 24 |
Oct 15 12:50:33 PM UTC 24 |
1879189847 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.2431539033 |
|
|
Oct 15 12:50:30 PM UTC 24 |
Oct 15 12:50:38 PM UTC 24 |
4544217793 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2321804973 |
|
|
Oct 15 12:50:31 PM UTC 24 |
Oct 15 12:50:39 PM UTC 24 |
4621652675 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.115578551 |
|
|
Oct 15 12:46:06 PM UTC 24 |
Oct 15 12:50:39 PM UTC 24 |
30634749688 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.1854035344 |
|
|
Oct 15 12:50:34 PM UTC 24 |
Oct 15 12:50:41 PM UTC 24 |
511702906 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.950206905 |
|
|
Oct 15 12:50:39 PM UTC 24 |
Oct 15 12:50:48 PM UTC 24 |
346672199 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.696684068 |
|
|
Oct 15 12:50:27 PM UTC 24 |
Oct 15 12:50:50 PM UTC 24 |
6355226397 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.3056053258 |
|
|
Oct 15 12:48:03 PM UTC 24 |
Oct 15 12:50:50 PM UTC 24 |
10820176060 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.1574936361 |
|
|
Oct 15 12:50:49 PM UTC 24 |
Oct 15 12:50:51 PM UTC 24 |
69477125 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2899331484 |
|
|
Oct 15 12:49:06 PM UTC 24 |
Oct 15 12:50:52 PM UTC 24 |
4913349074 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3798144165 |
|
|
Oct 15 12:50:52 PM UTC 24 |
Oct 15 12:50:54 PM UTC 24 |
14579261 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.2695838421 |
|
|
Oct 15 12:50:52 PM UTC 24 |
Oct 15 12:50:54 PM UTC 24 |
40362965 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.102364317 |
|
|
Oct 15 12:40:22 PM UTC 24 |
Oct 15 12:50:55 PM UTC 24 |
154706904221 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.85468074 |
|
|
Oct 15 12:48:46 PM UTC 24 |
Oct 15 12:50:56 PM UTC 24 |
13201392843 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3701652681 |
|
|
Oct 15 12:49:12 PM UTC 24 |
Oct 15 12:50:57 PM UTC 24 |
3484461303 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.199773414 |
|
|
Oct 15 12:50:56 PM UTC 24 |
Oct 15 12:50:59 PM UTC 24 |
66211416 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.694482766 |
|
|
Oct 15 12:50:56 PM UTC 24 |
Oct 15 12:50:59 PM UTC 24 |
60083174 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3765125725 |
|
|
Oct 15 12:43:12 PM UTC 24 |
Oct 15 12:51:03 PM UTC 24 |
55708572054 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.491443525 |
|
|
Oct 15 12:50:53 PM UTC 24 |
Oct 15 12:51:05 PM UTC 24 |
958408528 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.889057816 |
|
|
Oct 15 12:50:03 PM UTC 24 |
Oct 15 12:51:05 PM UTC 24 |
9126998307 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2723568599 |
|
|
Oct 15 12:51:04 PM UTC 24 |
Oct 15 12:51:09 PM UTC 24 |
70479748 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2647932216 |
|
|
Oct 15 12:50:58 PM UTC 24 |
Oct 15 12:51:12 PM UTC 24 |
3280663423 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.931848154 |
|
|
Oct 15 12:50:56 PM UTC 24 |
Oct 15 12:51:12 PM UTC 24 |
4177943528 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.270201013 |
|
|
Oct 15 12:51:00 PM UTC 24 |
Oct 15 12:51:16 PM UTC 24 |
3037981065 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.1746738152 |
|
|
Oct 15 12:50:53 PM UTC 24 |
Oct 15 12:51:20 PM UTC 24 |
3421741513 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.4156359299 |
|
|
Oct 15 12:49:58 PM UTC 24 |
Oct 15 12:51:21 PM UTC 24 |
11909304811 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.1765910393 |
|
|
Oct 15 12:51:21 PM UTC 24 |
Oct 15 12:51:24 PM UTC 24 |
159936309 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.51640095 |
|
|
Oct 15 12:51:23 PM UTC 24 |
Oct 15 12:51:25 PM UTC 24 |
34661525 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.1227575398 |
|
|
Oct 15 12:51:25 PM UTC 24 |
Oct 15 12:51:27 PM UTC 24 |
46665817 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.3928959737 |
|
|
Oct 15 12:51:06 PM UTC 24 |
Oct 15 12:51:28 PM UTC 24 |
3410463516 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.3805881720 |
|
|
Oct 15 12:50:58 PM UTC 24 |
Oct 15 12:51:28 PM UTC 24 |
4488956793 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1897472843 |
|
|
Oct 15 12:51:29 PM UTC 24 |
Oct 15 12:51:31 PM UTC 24 |
110467594 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3106062662 |
|
|
Oct 15 12:51:26 PM UTC 24 |
Oct 15 12:51:34 PM UTC 24 |
1473071898 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2235682892 |
|
|
Oct 15 12:51:10 PM UTC 24 |
Oct 15 12:51:35 PM UTC 24 |
1959295116 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.458708073 |
|
|
Oct 15 12:51:31 PM UTC 24 |
Oct 15 12:51:35 PM UTC 24 |
63593784 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.1096791433 |
|
|
Oct 15 12:45:34 PM UTC 24 |
Oct 15 12:51:36 PM UTC 24 |
69171514811 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.494101106 |
|
|
Oct 15 12:51:30 PM UTC 24 |
Oct 15 12:51:37 PM UTC 24 |
456126643 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2731358863 |
|
|
Oct 15 12:51:38 PM UTC 24 |
Oct 15 12:51:44 PM UTC 24 |
250778178 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.2738345216 |
|
|
Oct 15 12:51:29 PM UTC 24 |
Oct 15 12:51:45 PM UTC 24 |
6056125383 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.2333449718 |
|
|
Oct 15 12:39:58 PM UTC 24 |
Oct 15 12:51:48 PM UTC 24 |
88250969631 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.2715584921 |
|
|
Oct 15 12:51:00 PM UTC 24 |
Oct 15 12:51:49 PM UTC 24 |
139733617087 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.481684567 |
|
|
Oct 15 12:51:36 PM UTC 24 |
Oct 15 12:51:53 PM UTC 24 |
9575969351 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1042016875 |
|
|
Oct 15 12:51:48 PM UTC 24 |
Oct 15 12:51:55 PM UTC 24 |
353083673 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3691406683 |
|
|
Oct 15 12:51:46 PM UTC 24 |
Oct 15 12:51:58 PM UTC 24 |
4943816750 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.2271776212 |
|
|
Oct 15 12:51:36 PM UTC 24 |
Oct 15 12:51:58 PM UTC 24 |
7586024285 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.592043902 |
|
|
Oct 15 12:49:34 PM UTC 24 |
Oct 15 12:51:59 PM UTC 24 |
48031192787 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.1314998139 |
|
|
Oct 15 12:51:59 PM UTC 24 |
Oct 15 12:52:01 PM UTC 24 |
55775070 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.1650128291 |
|
|
Oct 15 12:51:59 PM UTC 24 |
Oct 15 12:52:02 PM UTC 24 |
107660215 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.4219858101 |
|
|
Oct 15 12:52:00 PM UTC 24 |
Oct 15 12:52:02 PM UTC 24 |
21886734 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2933582107 |
|
|
Oct 15 12:51:36 PM UTC 24 |
Oct 15 12:52:03 PM UTC 24 |
21869380177 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2025360642 |
|
|
Oct 15 12:52:04 PM UTC 24 |
Oct 15 12:52:07 PM UTC 24 |
436579919 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.3760734463 |
|
|
Oct 15 12:52:04 PM UTC 24 |
Oct 15 12:52:09 PM UTC 24 |
643884674 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.776379435 |
|
|
Oct 15 12:51:38 PM UTC 24 |
Oct 15 12:52:09 PM UTC 24 |
16798966874 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.1589269614 |
|
|
Oct 15 12:51:45 PM UTC 24 |
Oct 15 12:52:10 PM UTC 24 |
2088484689 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.2966729833 |
|
|
Oct 15 12:52:08 PM UTC 24 |
Oct 15 12:52:13 PM UTC 24 |
658118023 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.1993686261 |
|
|
Oct 15 12:52:11 PM UTC 24 |
Oct 15 12:52:19 PM UTC 24 |
303496312 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3532064627 |
|
|
Oct 15 12:48:03 PM UTC 24 |
Oct 15 12:52:20 PM UTC 24 |
35591249606 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.4025578041 |
|
|
Oct 15 12:52:10 PM UTC 24 |
Oct 15 12:52:20 PM UTC 24 |
769679939 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.3704072758 |
|
|
Oct 15 12:52:15 PM UTC 24 |
Oct 15 12:52:24 PM UTC 24 |
1066019253 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3302442211 |
|
|
Oct 15 12:52:03 PM UTC 24 |
Oct 15 12:52:28 PM UTC 24 |
14241828316 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1208755852 |
|
|
Oct 15 12:52:20 PM UTC 24 |
Oct 15 12:52:29 PM UTC 24 |
738515167 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.867209953 |
|
|
Oct 15 12:49:09 PM UTC 24 |
Oct 15 12:52:30 PM UTC 24 |
22485009045 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.4092255963 |
|
|
Oct 15 12:51:50 PM UTC 24 |
Oct 15 12:52:30 PM UTC 24 |
3141591566 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.1036162910 |
|
|
Oct 15 12:52:10 PM UTC 24 |
Oct 15 12:52:30 PM UTC 24 |
2869675733 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.1355028033 |
|
|
Oct 15 12:52:03 PM UTC 24 |
Oct 15 12:52:33 PM UTC 24 |
16584328698 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.74698736 |
|
|
Oct 15 12:52:32 PM UTC 24 |
Oct 15 12:52:34 PM UTC 24 |
41187998 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.2760128812 |
|
|
Oct 15 12:52:22 PM UTC 24 |
Oct 15 12:52:36 PM UTC 24 |
1370624188 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.420006908 |
|
|
Oct 15 12:49:36 PM UTC 24 |
Oct 15 12:52:40 PM UTC 24 |
34173934684 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2688480778 |
|
|
Oct 15 12:37:13 PM UTC 24 |
Oct 15 12:52:41 PM UTC 24 |
188194523768 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.2081464553 |
|
|
Oct 15 12:52:22 PM UTC 24 |
Oct 15 12:52:42 PM UTC 24 |
5067582430 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2137605003 |
|
|
Oct 15 12:47:45 PM UTC 24 |
Oct 15 12:52:44 PM UTC 24 |
23998450865 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3583556818 |
|
|
Oct 15 12:50:41 PM UTC 24 |
Oct 15 12:52:48 PM UTC 24 |
5611130610 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.1185522678 |
|
|
Oct 15 12:48:44 PM UTC 24 |
Oct 15 12:53:03 PM UTC 24 |
143566353528 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2907589949 |
|
|
Oct 15 12:51:07 PM UTC 24 |
Oct 15 12:53:03 PM UTC 24 |
13259703384 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.3535993565 |
|
|
Oct 15 12:51:13 PM UTC 24 |
Oct 15 12:53:03 PM UTC 24 |
89556578356 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3413250470 |
|
|
Oct 15 12:50:34 PM UTC 24 |
Oct 15 12:53:07 PM UTC 24 |
72905891549 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.1254491641 |
|
|
Oct 15 12:52:29 PM UTC 24 |
Oct 15 12:53:08 PM UTC 24 |
11016518673 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3022052361 |
|
|
Oct 15 12:50:00 PM UTC 24 |
Oct 15 12:53:15 PM UTC 24 |
42826896618 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.666674608 |
|
|
Oct 15 12:42:51 PM UTC 24 |
Oct 15 12:53:16 PM UTC 24 |
65867399024 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.770293003 |
|
|
Oct 15 12:48:23 PM UTC 24 |
Oct 15 12:53:21 PM UTC 24 |
22534495464 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2916931400 |
|
|
Oct 15 12:51:17 PM UTC 24 |
Oct 15 12:53:25 PM UTC 24 |
10915297887 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2388062434 |
|
|
Oct 15 12:49:32 PM UTC 24 |
Oct 15 12:53:39 PM UTC 24 |
108851306541 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2410395540 |
|
|
Oct 15 12:45:02 PM UTC 24 |
Oct 15 12:53:56 PM UTC 24 |
279909392374 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3349804265 |
|
|
Oct 15 12:48:00 PM UTC 24 |
Oct 15 12:54:12 PM UTC 24 |
49201682912 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3417909808 |
|
|
Oct 15 12:51:13 PM UTC 24 |
Oct 15 12:54:16 PM UTC 24 |
109356024821 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.3737089440 |
|
|
Oct 15 12:52:32 PM UTC 24 |
Oct 15 12:54:22 PM UTC 24 |
15917047690 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3381962329 |
|
|
Oct 15 12:52:30 PM UTC 24 |
Oct 15 12:54:23 PM UTC 24 |
33783408333 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1543292737 |
|
|
Oct 15 12:50:02 PM UTC 24 |
Oct 15 12:54:25 PM UTC 24 |
19201552420 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3413923183 |
|
|
Oct 15 12:46:08 PM UTC 24 |
Oct 15 12:54:25 PM UTC 24 |
208453156340 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.4117616412 |
|
|
Oct 15 12:48:24 PM UTC 24 |
Oct 15 12:54:47 PM UTC 24 |
36370695248 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1153021089 |
|
|
Oct 15 12:49:32 PM UTC 24 |
Oct 15 12:54:47 PM UTC 24 |
132521207492 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2704269654 |
|
|
Oct 15 12:51:55 PM UTC 24 |
Oct 15 12:54:57 PM UTC 24 |
15556367256 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2781209497 |
|
|
Oct 15 12:47:07 PM UTC 24 |
Oct 15 12:55:12 PM UTC 24 |
52591168841 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1407211543 |
|
|
Oct 15 12:52:22 PM UTC 24 |
Oct 15 12:56:35 PM UTC 24 |
74978799419 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.3820535681 |
|
|
Oct 15 12:50:05 PM UTC 24 |
Oct 15 12:57:13 PM UTC 24 |
56972444751 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2079133966 |
|
|
Oct 15 12:51:54 PM UTC 24 |
Oct 15 12:57:18 PM UTC 24 |
129092517729 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.483876246 |
|
|
Oct 15 12:52:25 PM UTC 24 |
Oct 15 12:57:51 PM UTC 24 |
170003553672 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.1947740469 |
|
|
Oct 15 12:46:10 PM UTC 24 |
Oct 15 12:57:53 PM UTC 24 |
229647684310 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.1721723470 |
|
|
Oct 15 12:48:44 PM UTC 24 |
Oct 15 12:58:03 PM UTC 24 |
64518826740 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.2450481688 |
|
|
Oct 15 12:50:39 PM UTC 24 |
Oct 15 12:58:05 PM UTC 24 |
196254118415 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.162674151 |
|
|
Oct 15 12:46:29 PM UTC 24 |
Oct 15 12:58:49 PM UTC 24 |
82559580525 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.3110779008 |
|
|
Oct 15 12:45:07 PM UTC 24 |
Oct 15 01:01:19 PM UTC 24 |
1972085799483 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.1983087004 |
|
|
Oct 15 12:50:43 PM UTC 24 |
Oct 15 01:02:54 PM UTC 24 |
996718161269 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3777957311 |
|
|
Oct 15 11:39:46 AM UTC 24 |
Oct 15 11:39:48 AM UTC 24 |
49261999 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.712477283 |
|
|
Oct 15 11:39:46 AM UTC 24 |
Oct 15 11:39:49 AM UTC 24 |
65523004 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3290793977 |
|
|
Oct 15 11:40:02 AM UTC 24 |
Oct 15 11:40:07 AM UTC 24 |
592210075 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1985087332 |
|
|
Oct 15 11:39:48 AM UTC 24 |
Oct 15 11:39:49 AM UTC 24 |
38755164 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3793660244 |
|
|
Oct 15 11:39:48 AM UTC 24 |
Oct 15 11:39:50 AM UTC 24 |
41778481 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3758480169 |
|
|
Oct 15 11:39:48 AM UTC 24 |
Oct 15 11:39:50 AM UTC 24 |
15648805 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.347705132 |
|
|
Oct 15 11:39:48 AM UTC 24 |
Oct 15 11:39:50 AM UTC 24 |
36110193 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3058219855 |
|
|
Oct 15 11:39:48 AM UTC 24 |
Oct 15 11:39:50 AM UTC 24 |
80461986 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3284579333 |
|
|
Oct 15 11:39:48 AM UTC 24 |
Oct 15 11:39:50 AM UTC 24 |
38812377 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4072377958 |
|
|
Oct 15 11:39:48 AM UTC 24 |
Oct 15 11:39:51 AM UTC 24 |
61204503 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2294189486 |
|
|
Oct 15 11:39:50 AM UTC 24 |
Oct 15 11:39:52 AM UTC 24 |
28964863 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.803643285 |
|
|
Oct 15 11:39:50 AM UTC 24 |
Oct 15 11:39:52 AM UTC 24 |
35049555 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4271503436 |
|
|
Oct 15 11:39:49 AM UTC 24 |
Oct 15 11:39:52 AM UTC 24 |
37174511 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2852215689 |
|
|
Oct 15 11:39:48 AM UTC 24 |
Oct 15 11:39:53 AM UTC 24 |
207042648 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1569705872 |
|
|
Oct 15 11:39:50 AM UTC 24 |
Oct 15 11:39:53 AM UTC 24 |
29444421 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1996249132 |
|
|
Oct 15 11:39:48 AM UTC 24 |
Oct 15 11:39:53 AM UTC 24 |
254454719 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3972113723 |
|
|
Oct 15 11:39:49 AM UTC 24 |
Oct 15 11:39:53 AM UTC 24 |
700562279 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2549832494 |
|
|
Oct 15 11:39:51 AM UTC 24 |
Oct 15 11:39:53 AM UTC 24 |
33050133 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3520234634 |
|
|
Oct 15 11:39:48 AM UTC 24 |
Oct 15 11:39:53 AM UTC 24 |
321711554 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2432391788 |
|
|
Oct 15 11:39:50 AM UTC 24 |
Oct 15 11:39:53 AM UTC 24 |
49531048 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1404690062 |
|
|
Oct 15 11:39:51 AM UTC 24 |
Oct 15 11:39:54 AM UTC 24 |
161741100 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.3541484208 |
|
|
Oct 15 11:39:52 AM UTC 24 |
Oct 15 11:39:54 AM UTC 24 |
23946626 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4057337090 |
|
|
Oct 15 11:39:50 AM UTC 24 |
Oct 15 11:39:54 AM UTC 24 |
154657440 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.3835948422 |
|
|
Oct 15 11:39:52 AM UTC 24 |
Oct 15 11:39:54 AM UTC 24 |
37515716 ps |