| T843 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1443572191 |
|
|
Feb 08 06:41:11 PM UTC 25 |
Feb 08 06:42:43 PM UTC 25 |
8888892055 ps |
| T386 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2354875685 |
|
|
Feb 08 06:42:21 PM UTC 25 |
Feb 08 06:42:44 PM UTC 25 |
24019914514 ps |
| T844 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.737334788 |
|
|
Feb 08 06:42:40 PM UTC 25 |
Feb 08 06:42:45 PM UTC 25 |
130518942 ps |
| T845 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1061717878 |
|
|
Feb 08 06:41:53 PM UTC 25 |
Feb 08 06:42:48 PM UTC 25 |
17961431163 ps |
| T188 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.442489861 |
|
|
Feb 08 06:38:12 PM UTC 25 |
Feb 08 06:42:49 PM UTC 25 |
344816503223 ps |
| T846 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.658310046 |
|
|
Feb 08 06:42:39 PM UTC 25 |
Feb 08 06:42:51 PM UTC 25 |
1493596557 ps |
| T342 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.2973113038 |
|
|
Feb 08 06:41:17 PM UTC 25 |
Feb 08 06:42:52 PM UTC 25 |
7475214749 ps |
| T847 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2009538176 |
|
|
Feb 08 06:42:44 PM UTC 25 |
Feb 08 06:42:52 PM UTC 25 |
636631930 ps |
| T848 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.910233080 |
|
|
Feb 08 06:41:36 PM UTC 25 |
Feb 08 06:42:53 PM UTC 25 |
29997049033 ps |
| T849 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.4159052202 |
|
|
Feb 08 06:42:51 PM UTC 25 |
Feb 08 06:42:53 PM UTC 25 |
24415275 ps |
| T850 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.2099608214 |
|
|
Feb 08 06:42:42 PM UTC 25 |
Feb 08 06:42:54 PM UTC 25 |
636818857 ps |
| T851 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.3072105760 |
|
|
Feb 08 06:42:53 PM UTC 25 |
Feb 08 06:42:55 PM UTC 25 |
24226627 ps |
| T852 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.3023071849 |
|
|
Feb 08 06:42:37 PM UTC 25 |
Feb 08 06:42:56 PM UTC 25 |
5408331798 ps |
| T853 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.272060239 |
|
|
Feb 08 06:42:54 PM UTC 25 |
Feb 08 06:42:57 PM UTC 25 |
16178120 ps |
| T854 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.498137551 |
|
|
Feb 08 06:42:54 PM UTC 25 |
Feb 08 06:42:57 PM UTC 25 |
65400882 ps |
| T258 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1841572134 |
|
|
Feb 08 06:42:44 PM UTC 25 |
Feb 08 06:42:58 PM UTC 25 |
596174880 ps |
| T855 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.3394221266 |
|
|
Feb 08 06:42:37 PM UTC 25 |
Feb 08 06:42:59 PM UTC 25 |
12958273467 ps |
| T856 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.3320061148 |
|
|
Feb 08 06:42:34 PM UTC 25 |
Feb 08 06:43:00 PM UTC 25 |
3289785570 ps |
| T857 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.2359379473 |
|
|
Feb 08 06:42:19 PM UTC 25 |
Feb 08 06:43:00 PM UTC 25 |
8304939020 ps |
| T858 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.474397222 |
|
|
Feb 08 06:42:09 PM UTC 25 |
Feb 08 06:43:02 PM UTC 25 |
34555356916 ps |
| T859 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.3635903974 |
|
|
Feb 08 06:42:57 PM UTC 25 |
Feb 08 06:43:02 PM UTC 25 |
184632916 ps |
| T860 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.2560219713 |
|
|
Feb 08 06:42:45 PM UTC 25 |
Feb 08 06:43:04 PM UTC 25 |
2497035254 ps |
| T861 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2266311448 |
|
|
Feb 08 06:40:14 PM UTC 25 |
Feb 08 06:43:05 PM UTC 25 |
37437318295 ps |
| T862 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.673534062 |
|
|
Feb 08 06:42:53 PM UTC 25 |
Feb 08 06:43:05 PM UTC 25 |
1356053385 ps |
| T863 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.467768050 |
|
|
Feb 08 06:43:01 PM UTC 25 |
Feb 08 06:43:06 PM UTC 25 |
259717610 ps |
| T864 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.2619531423 |
|
|
Feb 08 06:44:09 PM UTC 25 |
Feb 08 06:44:18 PM UTC 25 |
2821265700 ps |
| T865 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.4164141093 |
|
|
Feb 08 06:42:39 PM UTC 25 |
Feb 08 06:43:08 PM UTC 25 |
14413916988 ps |
| T366 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.4188591406 |
|
|
Feb 08 06:35:55 PM UTC 25 |
Feb 08 06:43:09 PM UTC 25 |
285948250931 ps |
| T866 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.2301055098 |
|
|
Feb 08 06:43:07 PM UTC 25 |
Feb 08 06:43:09 PM UTC 25 |
42039370 ps |
| T867 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2825174019 |
|
|
Feb 08 06:43:00 PM UTC 25 |
Feb 08 06:43:11 PM UTC 25 |
2590251274 ps |
| T868 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.3361357428 |
|
|
Feb 08 06:42:59 PM UTC 25 |
Feb 08 06:43:11 PM UTC 25 |
622565389 ps |
| T869 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.557947817 |
|
|
Feb 08 06:43:09 PM UTC 25 |
Feb 08 06:43:11 PM UTC 25 |
61543615 ps |
| T870 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.2335429414 |
|
|
Feb 08 06:42:54 PM UTC 25 |
Feb 08 06:43:12 PM UTC 25 |
4205504235 ps |
| T871 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3767049961 |
|
|
Feb 08 06:43:03 PM UTC 25 |
Feb 08 06:43:12 PM UTC 25 |
2596201718 ps |
| T872 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1496708511 |
|
|
Feb 08 06:43:11 PM UTC 25 |
Feb 08 06:43:14 PM UTC 25 |
376424579 ps |
| T873 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.3981008708 |
|
|
Feb 08 06:42:21 PM UTC 25 |
Feb 08 06:43:14 PM UTC 25 |
8916852386 ps |
| T874 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.2504155901 |
|
|
Feb 08 06:43:12 PM UTC 25 |
Feb 08 06:43:15 PM UTC 25 |
16917265 ps |
| T875 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.4289139538 |
|
|
Feb 08 06:42:57 PM UTC 25 |
Feb 08 06:43:15 PM UTC 25 |
4588425340 ps |
| T876 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3396719225 |
|
|
Feb 08 06:43:09 PM UTC 25 |
Feb 08 06:43:18 PM UTC 25 |
1687129014 ps |
| T877 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3368984577 |
|
|
Feb 08 06:38:33 PM UTC 25 |
Feb 08 06:43:22 PM UTC 25 |
102068800966 ps |
| T878 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.686689813 |
|
|
Feb 08 06:41:51 PM UTC 25 |
Feb 08 06:43:23 PM UTC 25 |
19347288514 ps |
| T879 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3809463230 |
|
|
Feb 08 06:43:16 PM UTC 25 |
Feb 08 06:43:24 PM UTC 25 |
756669928 ps |
| T880 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.1653012531 |
|
|
Feb 08 06:41:53 PM UTC 25 |
Feb 08 06:43:24 PM UTC 25 |
18974925138 ps |
| T881 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3843215890 |
|
|
Feb 08 06:42:11 PM UTC 25 |
Feb 08 06:43:26 PM UTC 25 |
3832811698 ps |
| T339 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.3440241254 |
|
|
Feb 08 06:34:20 PM UTC 25 |
Feb 08 06:43:26 PM UTC 25 |
249888308675 ps |
| T882 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3328086882 |
|
|
Feb 08 06:42:12 PM UTC 25 |
Feb 08 06:43:29 PM UTC 25 |
12461696421 ps |
| T883 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.2694035608 |
|
|
Feb 08 06:43:27 PM UTC 25 |
Feb 08 06:43:30 PM UTC 25 |
13382356 ps |
| T884 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.1526024268 |
|
|
Feb 08 06:43:27 PM UTC 25 |
Feb 08 06:43:30 PM UTC 25 |
36316492 ps |
| T303 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1027958968 |
|
|
Feb 08 06:43:16 PM UTC 25 |
Feb 08 06:43:33 PM UTC 25 |
9849877175 ps |
| T885 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1887855299 |
|
|
Feb 08 06:43:13 PM UTC 25 |
Feb 08 06:43:33 PM UTC 25 |
14715579588 ps |
| T886 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2580537146 |
|
|
Feb 08 06:43:31 PM UTC 25 |
Feb 08 06:43:33 PM UTC 25 |
386986949 ps |
| T887 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.271817153 |
|
|
Feb 08 06:43:15 PM UTC 25 |
Feb 08 06:43:35 PM UTC 25 |
6861469857 ps |
| T888 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2697647076 |
|
|
Feb 08 06:43:31 PM UTC 25 |
Feb 08 06:43:37 PM UTC 25 |
6622920912 ps |
| T889 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1551476436 |
|
|
Feb 08 06:42:24 PM UTC 25 |
Feb 08 06:43:37 PM UTC 25 |
19427735240 ps |
| T890 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.4253385445 |
|
|
Feb 08 06:43:18 PM UTC 25 |
Feb 08 06:43:38 PM UTC 25 |
10235027189 ps |
| T891 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.3247797484 |
|
|
Feb 08 06:42:56 PM UTC 25 |
Feb 08 06:43:39 PM UTC 25 |
30409887646 ps |
| T892 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.1171194448 |
|
|
Feb 08 06:43:31 PM UTC 25 |
Feb 08 06:43:40 PM UTC 25 |
1250789234 ps |
| T893 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.4032168612 |
|
|
Feb 08 06:43:36 PM UTC 25 |
Feb 08 06:43:40 PM UTC 25 |
30682637 ps |
| T343 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3935497369 |
|
|
Feb 08 06:43:34 PM UTC 25 |
Feb 08 06:43:40 PM UTC 25 |
409578982 ps |
| T894 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.4039632926 |
|
|
Feb 08 06:43:13 PM UTC 25 |
Feb 08 06:43:40 PM UTC 25 |
17465988901 ps |
| T895 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.13426436 |
|
|
Feb 08 06:43:10 PM UTC 25 |
Feb 08 06:43:42 PM UTC 25 |
6800737965 ps |
| T896 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3912195058 |
|
|
Feb 08 06:43:38 PM UTC 25 |
Feb 08 06:43:42 PM UTC 25 |
500643685 ps |
| T897 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.1174676015 |
|
|
Feb 08 06:43:14 PM UTC 25 |
Feb 08 06:43:43 PM UTC 25 |
9216828044 ps |
| T898 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2409825401 |
|
|
Feb 08 06:43:39 PM UTC 25 |
Feb 08 06:43:43 PM UTC 25 |
34382528 ps |
| T375 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.537057591 |
|
|
Feb 08 06:34:35 PM UTC 25 |
Feb 08 06:43:44 PM UTC 25 |
155795873397 ps |
| T899 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.652643417 |
|
|
Feb 08 06:43:37 PM UTC 25 |
Feb 08 06:43:45 PM UTC 25 |
239462860 ps |
| T900 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.3443513376 |
|
|
Feb 08 06:43:44 PM UTC 25 |
Feb 08 06:43:46 PM UTC 25 |
13054696 ps |
| T901 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.953470887 |
|
|
Feb 08 06:43:15 PM UTC 25 |
Feb 08 06:43:47 PM UTC 25 |
17942894674 ps |
| T902 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.1836176980 |
|
|
Feb 08 06:43:45 PM UTC 25 |
Feb 08 06:43:47 PM UTC 25 |
66723787 ps |
| T903 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1115730737 |
|
|
Feb 08 06:42:57 PM UTC 25 |
Feb 08 06:43:48 PM UTC 25 |
8282864627 ps |
| T904 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1252256996 |
|
|
Feb 08 06:43:41 PM UTC 25 |
Feb 08 06:43:48 PM UTC 25 |
111888400 ps |
| T905 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.393601451 |
|
|
Feb 08 06:43:47 PM UTC 25 |
Feb 08 06:43:50 PM UTC 25 |
96775374 ps |
| T906 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.108647993 |
|
|
Feb 08 06:43:48 PM UTC 25 |
Feb 08 06:43:51 PM UTC 25 |
248077631 ps |
| T907 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3603064406 |
|
|
Feb 08 06:43:34 PM UTC 25 |
Feb 08 06:43:51 PM UTC 25 |
312355644 ps |
| T389 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.371977019 |
|
|
Feb 08 06:38:36 PM UTC 25 |
Feb 08 06:43:52 PM UTC 25 |
39153619260 ps |
| T908 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3493044893 |
|
|
Feb 08 06:43:34 PM UTC 25 |
Feb 08 06:43:54 PM UTC 25 |
4730489316 ps |
| T909 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3402368285 |
|
|
Feb 08 06:43:52 PM UTC 25 |
Feb 08 06:43:57 PM UTC 25 |
148215539 ps |
| T910 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.889339984 |
|
|
Feb 08 06:43:46 PM UTC 25 |
Feb 08 06:43:58 PM UTC 25 |
1028703203 ps |
| T911 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.2764408292 |
|
|
Feb 08 06:43:49 PM UTC 25 |
Feb 08 06:43:59 PM UTC 25 |
547195213 ps |
| T912 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.1818882899 |
|
|
Feb 08 06:43:40 PM UTC 25 |
Feb 08 06:44:00 PM UTC 25 |
1434037494 ps |
| T913 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.4235887301 |
|
|
Feb 08 06:29:54 PM UTC 25 |
Feb 08 06:44:03 PM UTC 25 |
80528918338 ps |
| T914 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.1615620446 |
|
|
Feb 08 06:43:57 PM UTC 25 |
Feb 08 06:44:04 PM UTC 25 |
909585881 ps |
| T915 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.892919287 |
|
|
Feb 08 06:43:52 PM UTC 25 |
Feb 08 06:44:07 PM UTC 25 |
3171679304 ps |
| T916 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.3007677461 |
|
|
Feb 08 06:44:05 PM UTC 25 |
Feb 08 06:44:07 PM UTC 25 |
23075103 ps |
| T917 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1511655198 |
|
|
Feb 08 06:43:48 PM UTC 25 |
Feb 08 06:44:08 PM UTC 25 |
1895703788 ps |
| T918 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.727233653 |
|
|
Feb 08 06:44:08 PM UTC 25 |
Feb 08 06:44:10 PM UTC 25 |
50567607 ps |
| T919 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.2357893065 |
|
|
Feb 08 06:43:42 PM UTC 25 |
Feb 08 06:44:11 PM UTC 25 |
7626381618 ps |
| T920 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.4164662117 |
|
|
Feb 08 06:44:04 PM UTC 25 |
Feb 08 06:44:11 PM UTC 25 |
183133424 ps |
| T921 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.217089521 |
|
|
Feb 08 06:44:11 PM UTC 25 |
Feb 08 06:44:13 PM UTC 25 |
130983747 ps |
| T239 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.140016292 |
|
|
Feb 08 06:42:11 PM UTC 25 |
Feb 08 06:44:13 PM UTC 25 |
21561181451 ps |
| T922 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1059956311 |
|
|
Feb 08 06:43:45 PM UTC 25 |
Feb 08 06:44:14 PM UTC 25 |
8602698424 ps |
| T923 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.461771723 |
|
|
Feb 08 06:44:08 PM UTC 25 |
Feb 08 06:44:14 PM UTC 25 |
2811045243 ps |
| T924 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.1467712000 |
|
|
Feb 08 06:44:11 PM UTC 25 |
Feb 08 06:44:15 PM UTC 25 |
416273812 ps |
| T925 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.3869109627 |
|
|
Feb 08 06:42:50 PM UTC 25 |
Feb 08 06:44:17 PM UTC 25 |
40853670278 ps |
| T383 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2341493407 |
|
|
Feb 08 06:43:49 PM UTC 25 |
Feb 08 06:44:17 PM UTC 25 |
7053579504 ps |
| T372 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.4214246549 |
|
|
Feb 08 06:41:37 PM UTC 25 |
Feb 08 06:44:25 PM UTC 25 |
61364615243 ps |
| T926 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1755646474 |
|
|
Feb 08 06:44:19 PM UTC 25 |
Feb 08 06:44:26 PM UTC 25 |
191117593 ps |
| T927 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3100732802 |
|
|
Feb 08 06:44:14 PM UTC 25 |
Feb 08 06:44:26 PM UTC 25 |
1810586301 ps |
| T928 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.451225815 |
|
|
Feb 08 06:44:14 PM UTC 25 |
Feb 08 06:44:26 PM UTC 25 |
3623334351 ps |
| T929 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.3848099455 |
|
|
Feb 08 06:43:52 PM UTC 25 |
Feb 08 06:44:28 PM UTC 25 |
4814097311 ps |
| T930 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.345530645 |
|
|
Feb 08 06:43:23 PM UTC 25 |
Feb 08 06:44:29 PM UTC 25 |
4097858785 ps |
| T189 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.1130249949 |
|
|
Feb 08 06:44:27 PM UTC 25 |
Feb 08 06:44:30 PM UTC 25 |
209311774 ps |
| T931 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.4221476005 |
|
|
Feb 08 06:43:40 PM UTC 25 |
Feb 08 06:44:30 PM UTC 25 |
4035799917 ps |
| T932 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.1708431220 |
|
|
Feb 08 06:44:19 PM UTC 25 |
Feb 08 06:44:30 PM UTC 25 |
1637179476 ps |
| T933 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.1643058232 |
|
|
Feb 08 06:44:14 PM UTC 25 |
Feb 08 06:44:31 PM UTC 25 |
2039856657 ps |
| T934 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.765463743 |
|
|
Feb 08 06:44:29 PM UTC 25 |
Feb 08 06:44:31 PM UTC 25 |
11786448 ps |
| T935 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.2253129938 |
|
|
Feb 08 06:44:30 PM UTC 25 |
Feb 08 06:44:33 PM UTC 25 |
53057086 ps |
| T936 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.502732333 |
|
|
Feb 08 06:44:31 PM UTC 25 |
Feb 08 06:44:34 PM UTC 25 |
32776199 ps |
| T937 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.2801629904 |
|
|
Feb 08 06:44:31 PM UTC 25 |
Feb 08 06:44:34 PM UTC 25 |
168982633 ps |
| T938 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3691517504 |
|
|
Feb 08 06:44:12 PM UTC 25 |
Feb 08 06:44:35 PM UTC 25 |
16117572907 ps |
| T939 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.3126009995 |
|
|
Feb 08 06:43:59 PM UTC 25 |
Feb 08 06:44:36 PM UTC 25 |
16066043900 ps |
| T940 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3062022300 |
|
|
Feb 08 06:44:32 PM UTC 25 |
Feb 08 06:44:38 PM UTC 25 |
76055640 ps |
| T941 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3541178442 |
|
|
Feb 08 06:44:19 PM UTC 25 |
Feb 08 06:44:39 PM UTC 25 |
1910964493 ps |
| T263 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3004489126 |
|
|
Feb 08 06:42:27 PM UTC 25 |
Feb 08 06:44:39 PM UTC 25 |
56474596125 ps |
| T942 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.1319511263 |
|
|
Feb 08 06:44:35 PM UTC 25 |
Feb 08 06:44:39 PM UTC 25 |
123734223 ps |
| T943 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.626660688 |
|
|
Feb 08 06:44:37 PM UTC 25 |
Feb 08 06:44:41 PM UTC 25 |
285185871 ps |
| T944 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.2910920515 |
|
|
Feb 08 06:44:16 PM UTC 25 |
Feb 08 06:44:41 PM UTC 25 |
3906892618 ps |
| T165 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.866874608 |
|
|
Feb 08 06:36:40 PM UTC 25 |
Feb 08 06:44:45 PM UTC 25 |
196492784539 ps |
| T945 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.3085355011 |
|
|
Feb 08 06:44:35 PM UTC 25 |
Feb 08 06:44:46 PM UTC 25 |
1576689477 ps |
| T946 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.1320938984 |
|
|
Feb 08 06:44:36 PM UTC 25 |
Feb 08 06:44:48 PM UTC 25 |
535753081 ps |
| T947 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.2189512504 |
|
|
Feb 08 06:44:46 PM UTC 25 |
Feb 08 06:44:49 PM UTC 25 |
248420226 ps |
| T948 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3911049162 |
|
|
Feb 08 06:44:47 PM UTC 25 |
Feb 08 06:44:49 PM UTC 25 |
46848190 ps |
| T949 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.418710843 |
|
|
Feb 08 06:44:42 PM UTC 25 |
Feb 08 06:44:50 PM UTC 25 |
235168777 ps |
| T950 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.3911092283 |
|
|
Feb 08 06:44:48 PM UTC 25 |
Feb 08 06:44:51 PM UTC 25 |
28133553 ps |
| T951 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2447986721 |
|
|
Feb 08 06:44:49 PM UTC 25 |
Feb 08 06:44:52 PM UTC 25 |
30168218 ps |
| T952 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.1566592723 |
|
|
Feb 08 06:44:40 PM UTC 25 |
Feb 08 06:44:52 PM UTC 25 |
9369456145 ps |
| T953 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.221288090 |
|
|
Feb 08 06:44:42 PM UTC 25 |
Feb 08 06:44:53 PM UTC 25 |
2064585523 ps |
| T954 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3339466673 |
|
|
Feb 08 06:44:51 PM UTC 25 |
Feb 08 06:44:54 PM UTC 25 |
62281234 ps |
| T955 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.4007645350 |
|
|
Feb 08 06:44:52 PM UTC 25 |
Feb 08 06:44:54 PM UTC 25 |
73940762 ps |
| T956 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.3471507607 |
|
|
Feb 08 06:44:15 PM UTC 25 |
Feb 08 06:44:57 PM UTC 25 |
11162460882 ps |
| T957 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.1720617862 |
|
|
Feb 08 06:37:24 PM UTC 25 |
Feb 08 06:44:59 PM UTC 25 |
49392675427 ps |
| T958 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.1306304580 |
|
|
Feb 08 06:44:55 PM UTC 25 |
Feb 08 06:44:59 PM UTC 25 |
115429848 ps |
| T959 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.170342622 |
|
|
Feb 08 06:44:27 PM UTC 25 |
Feb 08 06:45:01 PM UTC 25 |
1822433660 ps |
| T960 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.3939029164 |
|
|
Feb 08 06:44:55 PM UTC 25 |
Feb 08 06:45:01 PM UTC 25 |
95475627 ps |
| T367 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.1353182547 |
|
|
Feb 08 06:40:16 PM UTC 25 |
Feb 08 06:45:07 PM UTC 25 |
58921982856 ps |
| T961 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.2037938124 |
|
|
Feb 08 06:44:33 PM UTC 25 |
Feb 08 06:45:08 PM UTC 25 |
5897913362 ps |
| T962 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2203922639 |
|
|
Feb 08 06:45:01 PM UTC 25 |
Feb 08 06:45:09 PM UTC 25 |
872701994 ps |
| T963 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.4116403065 |
|
|
Feb 08 06:42:28 PM UTC 25 |
Feb 08 06:45:09 PM UTC 25 |
13381491828 ps |
| T964 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1249334603 |
|
|
Feb 08 06:44:30 PM UTC 25 |
Feb 08 06:45:10 PM UTC 25 |
12685895804 ps |
| T965 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.530838743 |
|
|
Feb 08 06:44:54 PM UTC 25 |
Feb 08 06:45:11 PM UTC 25 |
3899242045 ps |
| T966 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.40186510 |
|
|
Feb 08 06:44:00 PM UTC 25 |
Feb 08 06:45:12 PM UTC 25 |
11229644276 ps |
| T967 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.407926524 |
|
|
Feb 08 06:45:10 PM UTC 25 |
Feb 08 06:45:12 PM UTC 25 |
95740450 ps |
| T968 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.2690367380 |
|
|
Feb 08 06:45:11 PM UTC 25 |
Feb 08 06:45:13 PM UTC 25 |
133598224 ps |
| T969 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3885296433 |
|
|
Feb 08 06:43:02 PM UTC 25 |
Feb 08 06:45:14 PM UTC 25 |
11851573741 ps |
| T970 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.472295260 |
|
|
Feb 08 06:41:07 PM UTC 25 |
Feb 08 06:45:14 PM UTC 25 |
59691759871 ps |
| T971 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2412729934 |
|
|
Feb 08 06:44:58 PM UTC 25 |
Feb 08 06:45:14 PM UTC 25 |
9104537000 ps |
| T972 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.153256117 |
|
|
Feb 08 06:44:53 PM UTC 25 |
Feb 08 06:45:15 PM UTC 25 |
6607659687 ps |
| T973 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.357129749 |
|
|
Feb 08 06:45:13 PM UTC 25 |
Feb 08 06:45:15 PM UTC 25 |
127421016 ps |
| T974 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.1509814393 |
|
|
Feb 08 06:45:14 PM UTC 25 |
Feb 08 06:45:17 PM UTC 25 |
323129419 ps |
| T975 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3418118924 |
|
|
Feb 08 06:44:26 PM UTC 25 |
Feb 08 06:45:17 PM UTC 25 |
34592456791 ps |
| T976 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.2923617602 |
|
|
Feb 08 06:44:30 PM UTC 25 |
Feb 08 06:45:20 PM UTC 25 |
14166362190 ps |
| T977 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.3863157505 |
|
|
Feb 08 06:45:15 PM UTC 25 |
Feb 08 06:45:21 PM UTC 25 |
800062713 ps |
| T978 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3612291463 |
|
|
Feb 08 06:45:17 PM UTC 25 |
Feb 08 06:45:21 PM UTC 25 |
104736897 ps |
| T979 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3013405374 |
|
|
Feb 08 06:44:53 PM UTC 25 |
Feb 08 06:45:22 PM UTC 25 |
58649932500 ps |
| T980 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.3120675656 |
|
|
Feb 08 06:45:16 PM UTC 25 |
Feb 08 06:45:23 PM UTC 25 |
1643036450 ps |
| T981 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4031748570 |
|
|
Feb 08 06:45:12 PM UTC 25 |
Feb 08 06:45:23 PM UTC 25 |
2382669535 ps |
| T982 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.1586826218 |
|
|
Feb 08 06:44:39 PM UTC 25 |
Feb 08 06:45:23 PM UTC 25 |
2301115027 ps |
| T983 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.3790605944 |
|
|
Feb 08 06:44:51 PM UTC 25 |
Feb 08 06:45:23 PM UTC 25 |
84229229754 ps |
| T984 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.327780278 |
|
|
Feb 08 06:43:50 PM UTC 25 |
Feb 08 06:45:24 PM UTC 25 |
8603166556 ps |
| T985 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.630629389 |
|
|
Feb 08 06:45:24 PM UTC 25 |
Feb 08 06:45:26 PM UTC 25 |
37329014 ps |
| T986 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.2998863424 |
|
|
Feb 08 06:45:24 PM UTC 25 |
Feb 08 06:45:26 PM UTC 25 |
87796113 ps |
| T987 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.1823775979 |
|
|
Feb 08 06:45:27 PM UTC 25 |
Feb 08 06:45:29 PM UTC 25 |
19043712 ps |
| T988 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2355123966 |
|
|
Feb 08 06:45:09 PM UTC 25 |
Feb 08 06:45:30 PM UTC 25 |
2632617727 ps |
| T989 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2255407253 |
|
|
Feb 08 06:44:59 PM UTC 25 |
Feb 08 06:45:32 PM UTC 25 |
4225429872 ps |
| T990 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.470455921 |
|
|
Feb 08 06:45:30 PM UTC 25 |
Feb 08 06:45:32 PM UTC 25 |
14134345 ps |
| T991 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2843641138 |
|
|
Feb 08 06:45:15 PM UTC 25 |
Feb 08 06:45:33 PM UTC 25 |
5111949503 ps |
| T992 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1467470501 |
|
|
Feb 08 06:45:25 PM UTC 25 |
Feb 08 06:45:34 PM UTC 25 |
2674479509 ps |
| T993 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3335857412 |
|
|
Feb 08 06:44:40 PM UTC 25 |
Feb 08 06:45:34 PM UTC 25 |
5969019357 ps |
| T331 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.2439937230 |
|
|
Feb 08 06:43:03 PM UTC 25 |
Feb 08 06:45:34 PM UTC 25 |
10062720897 ps |
| T387 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1289690604 |
|
|
Feb 08 06:42:46 PM UTC 25 |
Feb 08 06:45:35 PM UTC 25 |
42413386079 ps |
| T994 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2480373776 |
|
|
Feb 08 06:45:15 PM UTC 25 |
Feb 08 06:45:36 PM UTC 25 |
5442915055 ps |
| T995 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2922147042 |
|
|
Feb 08 06:45:21 PM UTC 25 |
Feb 08 06:45:38 PM UTC 25 |
1573355961 ps |
| T996 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.2096213094 |
|
|
Feb 08 06:45:13 PM UTC 25 |
Feb 08 06:45:39 PM UTC 25 |
13591545741 ps |
| T997 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.911405964 |
|
|
Feb 08 06:45:33 PM UTC 25 |
Feb 08 06:45:39 PM UTC 25 |
612018507 ps |
| T998 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.186306222 |
|
|
Feb 08 06:45:21 PM UTC 25 |
Feb 08 06:45:41 PM UTC 25 |
708466556 ps |
| T999 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.1154781750 |
|
|
Feb 08 06:45:36 PM UTC 25 |
Feb 08 06:45:41 PM UTC 25 |
196863809 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2057185391 |
|
|
Feb 08 06:43:23 PM UTC 25 |
Feb 08 06:45:42 PM UTC 25 |
103139710029 ps |
| T1001 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1339312092 |
|
|
Feb 08 06:43:54 PM UTC 25 |
Feb 08 06:45:43 PM UTC 25 |
46240013385 ps |
| T1002 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.586911219 |
|
|
Feb 08 06:45:34 PM UTC 25 |
Feb 08 06:45:44 PM UTC 25 |
1858667418 ps |
| T1003 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.3847175665 |
|
|
Feb 08 06:45:42 PM UTC 25 |
Feb 08 06:45:45 PM UTC 25 |
180766722 ps |
| T1004 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1622949732 |
|
|
Feb 08 06:45:35 PM UTC 25 |
Feb 08 06:45:47 PM UTC 25 |
518063060 ps |
| T1005 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.2333186092 |
|
|
Feb 08 06:45:27 PM UTC 25 |
Feb 08 06:45:47 PM UTC 25 |
3856817488 ps |
| T190 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.2800665042 |
|
|
Feb 08 06:45:24 PM UTC 25 |
Feb 08 06:45:49 PM UTC 25 |
1966453950 ps |
| T1006 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.842572639 |
|
|
Feb 08 06:45:33 PM UTC 25 |
Feb 08 06:45:50 PM UTC 25 |
4941110412 ps |
| T1007 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.3179748492 |
|
|
Feb 08 06:45:18 PM UTC 25 |
Feb 08 06:45:50 PM UTC 25 |
1673068776 ps |
| T1008 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.3760249877 |
|
|
Feb 08 06:45:02 PM UTC 25 |
Feb 08 06:45:54 PM UTC 25 |
9017126814 ps |
| T377 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.1607571106 |
|
|
Feb 08 06:30:21 PM UTC 25 |
Feb 08 06:45:58 PM UTC 25 |
98756835818 ps |
| T1009 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.3832102787 |
|
|
Feb 08 06:39:32 PM UTC 25 |
Feb 08 06:46:01 PM UTC 25 |
24963302340 ps |
| T1010 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1328847478 |
|
|
Feb 08 06:45:37 PM UTC 25 |
Feb 08 06:46:02 PM UTC 25 |
15523668717 ps |
| T1011 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1102037526 |
|
|
Feb 08 06:45:31 PM UTC 25 |
Feb 08 06:46:03 PM UTC 25 |
74862013693 ps |
| T1012 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.3662510723 |
|
|
Feb 08 06:45:35 PM UTC 25 |
Feb 08 06:46:09 PM UTC 25 |
42221421447 ps |
| T191 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.770733983 |
|
|
Feb 08 06:43:42 PM UTC 25 |
Feb 08 06:46:20 PM UTC 25 |
15026632395 ps |
| T1013 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3692310839 |
|
|
Feb 08 06:44:27 PM UTC 25 |
Feb 08 06:46:31 PM UTC 25 |
20567112066 ps |
| T1014 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.691871978 |
|
|
Feb 08 06:45:16 PM UTC 25 |
Feb 08 06:46:32 PM UTC 25 |
14949896010 ps |
| T1015 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.443394112 |
|
|
Feb 08 06:45:23 PM UTC 25 |
Feb 08 06:46:36 PM UTC 25 |
6403153995 ps |
| T1016 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.2507835975 |
|
|
Feb 08 06:45:10 PM UTC 25 |
Feb 08 06:46:36 PM UTC 25 |
3500802240 ps |
| T379 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.2787122125 |
|
|
Feb 08 06:43:41 PM UTC 25 |
Feb 08 06:46:53 PM UTC 25 |
25503199335 ps |
| T350 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.639676769 |
|
|
Feb 08 06:45:40 PM UTC 25 |
Feb 08 06:47:00 PM UTC 25 |
5331210996 ps |
| T1017 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2043079563 |
|
|
Feb 08 06:43:41 PM UTC 25 |
Feb 08 06:47:02 PM UTC 25 |
14520135782 ps |
| T166 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.387415376 |
|
|
Feb 08 06:43:25 PM UTC 25 |
Feb 08 06:47:04 PM UTC 25 |
67931239329 ps |
| T370 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.588683309 |
|
|
Feb 08 06:33:30 PM UTC 25 |
Feb 08 06:47:05 PM UTC 25 |
326408936077 ps |
| T1018 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3216295863 |
|
|
Feb 08 06:45:23 PM UTC 25 |
Feb 08 06:47:09 PM UTC 25 |
57896847696 ps |
| T388 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.544876867 |
|
|
Feb 08 06:38:59 PM UTC 25 |
Feb 08 06:47:11 PM UTC 25 |
50832768142 ps |
| T167 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.52400873 |
|
|
Feb 08 06:43:24 PM UTC 25 |
Feb 08 06:47:12 PM UTC 25 |
22535137202 ps |
| T168 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.3389000269 |
|
|
Feb 08 06:40:39 PM UTC 25 |
Feb 08 06:47:13 PM UTC 25 |
245255630234 ps |
| T169 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.1681431915 |
|
|
Feb 08 06:37:28 PM UTC 25 |
Feb 08 06:47:15 PM UTC 25 |
46607342282 ps |
| T170 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.1978585855 |
|
|
Feb 08 06:35:12 PM UTC 25 |
Feb 08 06:47:18 PM UTC 25 |
327068392239 ps |
| T1019 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.2570041984 |
|
|
Feb 08 06:45:40 PM UTC 25 |
Feb 08 06:47:18 PM UTC 25 |
4328200342 ps |
| T1020 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.837270889 |
|
|
Feb 08 06:45:08 PM UTC 25 |
Feb 08 06:47:25 PM UTC 25 |
28726936949 ps |
| T1021 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.2649188641 |
|
|
Feb 08 06:45:39 PM UTC 25 |
Feb 08 06:47:25 PM UTC 25 |
60555240848 ps |
| T1022 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2123718302 |
|
|
Feb 08 06:43:05 PM UTC 25 |
Feb 08 06:47:27 PM UTC 25 |
23248372947 ps |
| T1023 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2834372284 |
|
|
Feb 08 06:42:49 PM UTC 25 |
Feb 08 06:47:37 PM UTC 25 |
92587584965 ps |
| T1024 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.3152543910 |
|
|
Feb 08 06:44:40 PM UTC 25 |
Feb 08 06:47:40 PM UTC 25 |
63659592943 ps |
| T373 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.2731309907 |
|
|
Feb 08 06:42:26 PM UTC 25 |
Feb 08 06:47:44 PM UTC 25 |
250021598148 ps |
| T376 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.2371992593 |
|
|
Feb 08 06:45:42 PM UTC 25 |
Feb 08 06:47:52 PM UTC 25 |
18132906724 ps |
| T363 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3577295788 |
|
|
Feb 08 06:41:48 PM UTC 25 |
Feb 08 06:47:55 PM UTC 25 |
43948104566 ps |
| T1025 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2540918712 |
|
|
Feb 08 06:45:00 PM UTC 25 |
Feb 08 06:48:24 PM UTC 25 |
85361743947 ps |
| T1026 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2521601890 |
|
|
Feb 08 06:42:29 PM UTC 25 |
Feb 08 06:48:41 PM UTC 25 |
163150819622 ps |
| T1027 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1229093341 |
|
|
Feb 08 06:45:24 PM UTC 25 |
Feb 08 06:49:32 PM UTC 25 |
20230019383 ps |
| T1028 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.155932117 |
|
|
Feb 08 06:43:17 PM UTC 25 |
Feb 08 06:50:14 PM UTC 25 |
93035373993 ps |
| T382 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.908247447 |
|
|
Feb 08 06:45:36 PM UTC 25 |
Feb 08 06:50:17 PM UTC 25 |
140263370033 ps |
| T1029 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.997256355 |
|
|
Feb 08 06:38:40 PM UTC 25 |
Feb 08 06:51:37 PM UTC 25 |
56227947418 ps |
| T1030 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1268303264 |
|
|
Feb 08 06:44:01 PM UTC 25 |
Feb 08 06:52:13 PM UTC 25 |
46670930113 ps |
| T79 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.439932628 |
|
|
Feb 08 06:42:13 PM UTC 25 |
Feb 08 06:52:35 PM UTC 25 |
64960974262 ps |
| T364 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3619942041 |
|
|
Feb 08 06:43:06 PM UTC 25 |
Feb 08 06:54:27 PM UTC 25 |
239410371202 ps |
| T371 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.1188924270 |
|
|
Feb 08 06:43:06 PM UTC 25 |
Feb 08 06:59:46 PM UTC 25 |
97974191501 ps |
| T1031 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.4077267988 |
|
|
Feb 08 06:45:45 PM UTC 25 |
Feb 08 06:45:47 PM UTC 25 |
12169063 ps |
| T1032 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2753287963 |
|
|
Feb 08 06:45:45 PM UTC 25 |
Feb 08 06:45:47 PM UTC 25 |
258485732 ps |
| T118 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3835873578 |
|
|
Feb 08 06:45:43 PM UTC 25 |
Feb 08 06:45:48 PM UTC 25 |
94286165 ps |
| T105 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2213850906 |
|
|
Feb 08 06:45:48 PM UTC 25 |
Feb 08 06:45:51 PM UTC 25 |
112922201 ps |
| T137 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2596094317 |
|
|
Feb 08 06:45:47 PM UTC 25 |
Feb 08 06:45:52 PM UTC 25 |
62803517 ps |
| T1033 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2083159298 |
|
|
Feb 08 06:45:48 PM UTC 25 |
Feb 08 06:45:53 PM UTC 25 |
166615139 ps |
| T175 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1270034677 |
|
|
Feb 08 06:45:50 PM UTC 25 |
Feb 08 06:45:55 PM UTC 25 |
1677792369 ps |
| T1034 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.372326765 |
|
|
Feb 08 06:45:53 PM UTC 25 |
Feb 08 06:45:55 PM UTC 25 |
45944587 ps |
| T1035 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2490892312 |
|
|
Feb 08 06:45:54 PM UTC 25 |
Feb 08 06:45:56 PM UTC 25 |
13521636 ps |
| T119 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2888429922 |
|
|
Feb 08 06:45:51 PM UTC 25 |
Feb 08 06:45:57 PM UTC 25 |
68594618 ps |
| T120 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3859247607 |
|
|
Feb 08 06:45:51 PM UTC 25 |
Feb 08 06:45:57 PM UTC 25 |
864993739 ps |
| T138 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1637218708 |
|
|
Feb 08 06:45:55 PM UTC 25 |
Feb 08 06:45:58 PM UTC 25 |
75944851 ps |
| T1036 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1763276807 |
|
|
Feb 08 06:45:50 PM UTC 25 |
Feb 08 06:45:58 PM UTC 25 |
115332979 ps |
| T106 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3249033486 |
|
|
Feb 08 06:45:56 PM UTC 25 |
Feb 08 06:45:59 PM UTC 25 |
130508137 ps |
| T1037 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.851195509 |
|
|
Feb 08 06:45:56 PM UTC 25 |
Feb 08 06:46:01 PM UTC 25 |
69687182 ps |
| T1038 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1943854766 |
|
|
Feb 08 06:46:00 PM UTC 25 |
Feb 08 06:46:02 PM UTC 25 |
18129784 ps |
| T1039 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3855409268 |
|
|
Feb 08 06:45:58 PM UTC 25 |
Feb 08 06:46:03 PM UTC 25 |
228579330 ps |
| T1040 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1418369214 |
|
|
Feb 08 06:46:02 PM UTC 25 |
Feb 08 06:46:04 PM UTC 25 |
12969448 ps |
| T134 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3982895196 |
|
|
Feb 08 06:45:59 PM UTC 25 |
Feb 08 06:46:04 PM UTC 25 |
371518922 ps |
| T1041 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3517682553 |
|
|
Feb 08 06:45:48 PM UTC 25 |
Feb 08 06:46:05 PM UTC 25 |
1142424789 ps |
| T1042 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.442823055 |
|
|
Feb 08 06:46:03 PM UTC 25 |
Feb 08 06:46:05 PM UTC 25 |
74207520 ps |
| T139 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1339228972 |
|
|
Feb 08 06:46:03 PM UTC 25 |
Feb 08 06:46:06 PM UTC 25 |
190660084 ps |
| T140 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3228861766 |
|
|
Feb 08 06:45:57 PM UTC 25 |
Feb 08 06:46:06 PM UTC 25 |
1222005868 ps |
| T141 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1885301095 |
|
|
Feb 08 06:46:03 PM UTC 25 |
Feb 08 06:46:07 PM UTC 25 |
57269453 ps |