SPI_HOST Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.517m	13.178ms	46	50	92.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	58.112us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	39.482us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	166.234us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	41.739us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	32.533us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	39.482us	20	20	100.00
		spi_host_csr_aliasing	3.000s	41.739us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	45.076us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	118.288us	5	5	100.00
V1		TOTAL			111	115	96.52
V2	performance	spi_host_performance	4.000s	29.805us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.567m	9.652ms	50	50	100.00
		spi_host_error_cmd	3.000s	23.969us	50	50	100.00
		spi_host_event	23.817m	533.953ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.200m	52.397ms	50	50	100.00
V2	speed	spi_host_speed	6.200m	52.397ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.200m	52.397ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	3.000m	14.508ms	46	50	92.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	413.029us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.200m	52.397ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.200m	52.397ms	50	50	100.00
V2	duplex	spi_host_smoke	10.517m	13.178ms	46	50	92.00
V2	tx_rx_only	spi_host_smoke	10.517m	13.178ms	46	50	92.00
V2	stress_all	spi_host_stress_all	4.617m	11.803ms	48	50	96.00
V2	spien	spi_host_spien	6.683m	9.313ms	50	50	100.00
V2	stall	spi_host_status_stall	11.283m	100.000ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.167m	5.957ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	18.742us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	50.150us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	169.215us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	169.215us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	58.112us	5	5	100.00
		spi_host_csr_rw	3.000s	39.482us	20	20	100.00
		spi_host_csr_aliasing	3.000s	41.739us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	104.342us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	58.112us	5	5	100.00
		spi_host_csr_rw	3.000s	39.482us	20	20	100.00
		spi_host_csr_aliasing	3.000s	41.739us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	104.342us	20	20	100.00
V2		TOTAL			682	690	98.84
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	72.970us	20	20	100.00
		spi_host_sec_cm	2.000s	633.727us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	72.970us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			818	830	98.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.08	98.19	95.98	99.74	96.25	95.70	100.00	98.60	91.29

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 7 failures:

Test spi_host_smoke has 3 failures.

12.spi_host_smoke.3074863466
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_smoke/latest/run.log

  UVM_FATAL @ 93793781475 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9fe3e914) == 0x0
  UVM_INFO @ 93793781475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.spi_host_smoke.78078132
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_smoke/latest/run.log

  UVM_FATAL @ 104816090782 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7fc21514) == 0x0
  UVM_INFO @ 104816090782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test spi_host_sw_reset has 3 failures.

24.spi_host_sw_reset.3670712959
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 15740817540 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x12136554) == 0x0
  UVM_INFO @ 15740817540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.spi_host_sw_reset.1037127282
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10086237214 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2a7cad4) == 0x0
  UVM_INFO @ 10086237214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test spi_host_stress_all has 1 failures.

49.spi_host_stress_all.2838914951
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 10111206348 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x78ab1d14) == 0x0
  UVM_INFO @ 10111206348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_sw_reset has 1 failures.
  - 4.spi_host_sw_reset.2668149507
    Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 11298337808 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xda9f7754) == 0x0
  UVM_INFO @ 11298337808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 6.spi_host_smoke.3648202774
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 97173605848 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x947a1c94) == 0x0
  UVM_INFO @ 97173605848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 31.spi_host_status_stall.4144012912
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 38.spi_host_status_stall.4206291778
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 43.spi_host_stress_all.740179890
    Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10073808276 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa78b0e54) == 0x0
  UVM_INFO @ 10073808276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```