5c87d18988| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 11.283m | 14.047ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 20.753us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 19.060us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 164.032us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 20.888us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 23.056us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 19.060us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 20.888us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 49.773us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 22.211us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | performance | spi_host_performance | 4.000s | 31.757us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.200m | 14.838ms | 49 | 50 | 98.00 |
| spi_host_error_cmd | 4.000s | 27.957us | 50 | 50 | 100.00 | ||
| spi_host_event | 18.883m | 25.074ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.400m | 10.251ms | 48 | 50 | 96.00 |
| V2 | speed | spi_host_speed | 5.400m | 10.251ms | 48 | 50 | 96.00 |
| V2 | chip_select_timing | spi_host_speed | 5.400m | 10.251ms | 48 | 50 | 96.00 |
| V2 | sw_reset | spi_host_sw_reset | 6.250m | 11.736ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 346.056us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.400m | 10.251ms | 48 | 50 | 96.00 |
| V2 | full_cycle | spi_host_speed | 5.400m | 10.251ms | 48 | 50 | 96.00 |
| V2 | duplex | spi_host_smoke | 11.283m | 14.047ms | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 11.283m | 14.047ms | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 4.683m | 21.617ms | 49 | 50 | 98.00 |
| V2 | spien | spi_host_spien | 6.700m | 35.682ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 11.300m | 14.657ms | 48 | 50 | 96.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 47.000s | 3.482ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 17.442us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 4.000s | 18.500us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 88.286us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 88.286us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 20.753us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 19.060us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 20.888us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 28.720us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 20.753us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 19.060us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 20.888us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 28.720us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 684 | 690 | 99.13 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 328.884us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 600.999us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 328.884us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 824 | 830 | 99.28 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 15 | 15 | 11 | 73.33 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.05 | 98.13 | 95.98 | 99.73 | 96.43 | 95.70 | 100.00 | 98.60 | 91.29 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:
Test spi_host_stress_all has 1 failures.
21.spi_host_stress_all.26647224618046687218337918424879837037388939485216837487240008352209034891221
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_stress_all/latest/run.log
UVM_FATAL @ 11201365655 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbd451594) == 0x0
UVM_INFO @ 11201365655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 2 failures.
29.spi_host_speed.102104538643219615545354720328740713133336169176102600243607568025210913813309
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_speed/latest/run.log
UVM_FATAL @ 65082045801 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3205d314) == 0x0
UVM_INFO @ 65082045801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_speed.65180701124079273394943491078121107079498090113091186196110193679171505321764
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_speed/latest/run.log
UVM_FATAL @ 124029082169 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x92fff494) == 0x0
UVM_INFO @ 124029082169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_overflow_underflow has 1 failures.
47.spi_host_overflow_underflow.71182176460995499481596083662800022481343614409425241223288603471848686946675
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 36456042134 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6705694) == 0x0
UVM_INFO @ 36456042134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
49.spi_host_status_stall.67174091935221500893610322914334140300476133408853659679381258242977264658124
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_status_stall/latest/run.log
UVM_FATAL @ 121424345792 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd2ab5994) == 0x0
UVM_INFO @ 121424345792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
30.spi_host_status_stall.108835697871834463342429510169198576286747874061875595693940479299607199786364
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_status_stall/latest/run.log
UVM_FATAL @ 16582405706 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x80001f14) == 0x1
UVM_INFO @ 16582405706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---