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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.76 100.00 97.98 99.15 100.00 99.71 99.70 94.75


Total test records in report: 990
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T265 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.77013796694343981999319957735185713861208210660528262281324120117884276113829 Nov 22 02:07:21 PM PST 23 Nov 22 02:41:45 PM PST 23 624328106 ps
T266 /workspace/coverage/default/10.sram_ctrl_max_throughput.43771713896864027706121533382090869642732018485116716499663955467260416473300 Nov 22 02:07:40 PM PST 23 Nov 22 02:10:01 PM PST 23 1342947357 ps
T267 /workspace/coverage/default/33.sram_ctrl_smoke.109536957068181689899183144703601237937000662077835817219962497591982738574229 Nov 22 02:15:31 PM PST 23 Nov 22 02:15:50 PM PST 23 988289480 ps
T268 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.105570111984086637843990773490401833360978445471503880093187382582627125622217 Nov 22 02:15:28 PM PST 23 Nov 22 02:17:36 PM PST 23 1371125703 ps
T269 /workspace/coverage/default/16.sram_ctrl_partial_access.43028369447828460030828416863699600933066298605274981566112960510608964184467 Nov 22 02:12:13 PM PST 23 Nov 22 02:12:35 PM PST 23 1006378621 ps
T270 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.79727569459398508121987715344607116486629117696046918641472234718164675511243 Nov 22 02:07:38 PM PST 23 Nov 22 02:09:23 PM PST 23 1371125703 ps
T271 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.104193429715012263762290357885815748723612938461484837431989328674297183572371 Nov 22 02:17:02 PM PST 23 Nov 22 02:18:22 PM PST 23 4750777237 ps
T272 /workspace/coverage/default/43.sram_ctrl_lc_escalation.111043014605477921377464576042413020723297909952933548906405478589872230626863 Nov 22 02:16:13 PM PST 23 Nov 22 02:17:56 PM PST 23 19084394710 ps
T273 /workspace/coverage/default/20.sram_ctrl_lc_escalation.85609703325282521030450817882248964397810277221177813794518098137665040336228 Nov 22 02:12:51 PM PST 23 Nov 22 02:14:36 PM PST 23 19084394710 ps
T274 /workspace/coverage/default/48.sram_ctrl_executable.41149178694468628462684995744734376752219213707358845142709826837042087597477 Nov 22 02:18:08 PM PST 23 Nov 22 02:31:55 PM PST 23 31712811539 ps
T275 /workspace/coverage/default/30.sram_ctrl_bijection.38714949493521046113827897193556493062679604343661264945776478960888512695442 Nov 22 02:14:52 PM PST 23 Nov 22 03:00:42 PM PST 23 295482808505 ps
T276 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.30322514275796336139321951335578151797100446032233660466199313204728111929667 Nov 22 02:07:40 PM PST 23 Nov 22 02:17:04 PM PST 23 45083829570 ps
T277 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.53733283498830787486025502382808433428899308982172073489090483063763278401557 Nov 22 02:11:15 PM PST 23 Nov 22 02:29:46 PM PST 23 13467153934 ps
T278 /workspace/coverage/default/22.sram_ctrl_partial_access.38722444175317569349361949199798417655504605441764003214724436737637192292908 Nov 22 02:13:16 PM PST 23 Nov 22 02:13:36 PM PST 23 1006378621 ps
T279 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.77245224098620096529204608192522844056165793863675417431385092306223543280150 Nov 22 02:13:54 PM PST 23 Nov 22 02:42:04 PM PST 23 624328106 ps
T280 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.34211557462938058434430518627321214791614921312145638757692416892602272558919 Nov 22 02:11:27 PM PST 23 Nov 22 02:12:45 PM PST 23 4750777237 ps
T281 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.35931381824593632987218291788601368603651147543303112936294855406474494104839 Nov 22 02:11:39 PM PST 23 Nov 22 02:28:41 PM PST 23 13467153934 ps
T282 /workspace/coverage/default/33.sram_ctrl_multiple_keys.41335447567461592146112702211846556313294951385470112374700508181886292431124 Nov 22 02:15:29 PM PST 23 Nov 22 02:30:58 PM PST 23 28731174678 ps
T283 /workspace/coverage/default/3.sram_ctrl_ram_cfg.86511347897409308009243449063779776809633524957804356592158579577285252144064 Nov 22 02:07:21 PM PST 23 Nov 22 02:07:28 PM PST 23 607542526 ps
T284 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.97220560141677314473211484740640901714418148156349795239775307860330700307554 Nov 22 02:13:43 PM PST 23 Nov 22 02:43:04 PM PST 23 624328106 ps
T285 /workspace/coverage/default/34.sram_ctrl_partial_access.79690226011454862946281613515575567198073956246936408383848447269616792176235 Nov 22 02:15:32 PM PST 23 Nov 22 02:15:50 PM PST 23 1006378621 ps
T286 /workspace/coverage/default/46.sram_ctrl_ram_cfg.93069926518663622756814547426112659359943664379758443989513316529975424704826 Nov 22 02:17:02 PM PST 23 Nov 22 02:17:11 PM PST 23 607542526 ps
T287 /workspace/coverage/default/7.sram_ctrl_lc_escalation.91254950241665991464675668583585965950767583698744623927800901769963777778683 Nov 22 02:07:24 PM PST 23 Nov 22 02:09:10 PM PST 23 19084394710 ps
T288 /workspace/coverage/default/44.sram_ctrl_mem_walk.58092729646422406524979646571195565119543125356136836407184926249843554552797 Nov 22 02:16:33 PM PST 23 Nov 22 02:19:08 PM PST 23 18445453393 ps
T289 /workspace/coverage/default/38.sram_ctrl_lc_escalation.51791548675083148346517323207151823302144100660802798912886071735858946704661 Nov 22 02:16:33 PM PST 23 Nov 22 02:18:16 PM PST 23 19084394710 ps
T290 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.53495168289895495218886579714740186949293969901327736879624417580143644319971 Nov 22 02:07:36 PM PST 23 Nov 22 02:25:09 PM PST 23 13467153934 ps
T291 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3986536056053191272460467963061897930032325192255645457141799998927660795273 Nov 22 02:16:44 PM PST 23 Nov 22 02:18:04 PM PST 23 4750777237 ps
T292 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.32214027692825344062780486159594544483279899960056117107994468499431194138472 Nov 22 02:07:18 PM PST 23 Nov 22 02:25:22 PM PST 23 13467153934 ps
T293 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.107201670992146482473667604447335184950176483344613467371784522811649488138025 Nov 22 02:16:14 PM PST 23 Nov 22 02:31:53 PM PST 23 13467153934 ps
T294 /workspace/coverage/default/22.sram_ctrl_regwen.88447987956252265996281810433023539989116634681470028382372802795046727248933 Nov 22 02:13:14 PM PST 23 Nov 22 02:22:07 PM PST 23 19913691647 ps
T295 /workspace/coverage/default/18.sram_ctrl_multiple_keys.111416591950219340514049620696577863664017873908889853774922684938944714754230 Nov 22 02:12:18 PM PST 23 Nov 22 02:28:25 PM PST 23 28731174678 ps
T296 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.76998529219532656419025408170431130945961905598149045809808715766775050171766 Nov 22 02:07:45 PM PST 23 Nov 22 02:17:31 PM PST 23 45083829570 ps
T297 /workspace/coverage/default/10.sram_ctrl_mem_walk.81339386144484500615042459106474808209861276915293285803736733511154366447426 Nov 22 02:07:41 PM PST 23 Nov 22 02:10:12 PM PST 23 18445453393 ps
T298 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.50331177651817338490068289073433692023931774842934929404410292265404676764621 Nov 22 02:13:16 PM PST 23 Nov 22 02:43:11 PM PST 23 624328106 ps
T299 /workspace/coverage/default/5.sram_ctrl_regwen.22478793642770209803943369672576002111575714404824752711847557614835206466952 Nov 22 02:07:35 PM PST 23 Nov 22 02:20:00 PM PST 23 19913691647 ps
T300 /workspace/coverage/default/22.sram_ctrl_ram_cfg.112595673139969423302761350653929880488086862174129521582901150347982825981044 Nov 22 02:13:15 PM PST 23 Nov 22 02:13:21 PM PST 23 607542526 ps
T301 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.15872728761108321294140322603314761871442902031063939080993452645648657163751 Nov 22 02:07:41 PM PST 23 Nov 22 02:17:22 PM PST 23 45083829570 ps
T302 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.100283415645294570649960989799759482527753497564584561331194317385134333319344 Nov 22 02:07:19 PM PST 23 Nov 22 02:09:40 PM PST 23 1371125703 ps
T303 /workspace/coverage/default/13.sram_ctrl_ram_cfg.112083371973444327469369795819130300718428078055563065779913247696120457433235 Nov 22 02:11:19 PM PST 23 Nov 22 02:11:26 PM PST 23 607542526 ps
T304 /workspace/coverage/default/39.sram_ctrl_ram_cfg.103895272733032074793231045357004878586427414792840984783180957394603103988239 Nov 22 02:16:38 PM PST 23 Nov 22 02:16:45 PM PST 23 607542526 ps
T305 /workspace/coverage/default/42.sram_ctrl_bijection.26554778980327317510376231654076838504831068937244878634244259824810579825344 Nov 22 02:16:40 PM PST 23 Nov 22 03:01:48 PM PST 23 295482808505 ps
T306 /workspace/coverage/default/14.sram_ctrl_smoke.113068490126761410536147742537300776189101558477613973987858697311715102417109 Nov 22 02:11:27 PM PST 23 Nov 22 02:11:45 PM PST 23 988289480 ps
T307 /workspace/coverage/default/31.sram_ctrl_regwen.27416228395012778529840119097603835198130931075398828093969139696117930139526 Nov 22 02:14:55 PM PST 23 Nov 22 02:23:43 PM PST 23 19913691647 ps
T308 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.54238847366030347195305921511681504467898201371467168269914218009362952263897 Nov 22 02:17:40 PM PST 23 Nov 22 02:24:41 PM PST 23 9325508496 ps
T309 /workspace/coverage/default/20.sram_ctrl_smoke.36887264514257275799314783952763603469380595870190357822941446764161648491178 Nov 22 02:12:35 PM PST 23 Nov 22 02:12:52 PM PST 23 988289480 ps
T310 /workspace/coverage/default/19.sram_ctrl_executable.24124963162554785800132319562780636613622437920098521394690136529519024813691 Nov 22 02:12:51 PM PST 23 Nov 22 02:27:49 PM PST 23 31712811539 ps
T311 /workspace/coverage/default/13.sram_ctrl_multiple_keys.88022087401299231351383463833886266496995032986173285310131440233697631540376 Nov 22 02:11:20 PM PST 23 Nov 22 02:26:01 PM PST 23 28731174678 ps
T312 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.23942114466852152539118429011544036496898449487297745103727195104343435442920 Nov 22 02:07:35 PM PST 23 Nov 22 02:38:38 PM PST 23 624328106 ps
T313 /workspace/coverage/default/17.sram_ctrl_regwen.95664672409971462500662574790994152351677395958178250082920843508138943879364 Nov 22 02:12:32 PM PST 23 Nov 22 02:23:13 PM PST 23 19913691647 ps
T314 /workspace/coverage/default/43.sram_ctrl_partial_access.3118250718077209793733441169074779027424959943285676217246303403947254510202 Nov 22 02:16:18 PM PST 23 Nov 22 02:16:37 PM PST 23 1006378621 ps
T315 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.44265874371442963590998448772182683807760902034973303618497922682391871407247 Nov 22 02:16:30 PM PST 23 Nov 22 02:17:48 PM PST 23 4750777237 ps
T316 /workspace/coverage/default/48.sram_ctrl_partial_access.24567878638505232062756135635310790579735409788006607561501719171318509233247 Nov 22 02:17:31 PM PST 23 Nov 22 02:17:50 PM PST 23 1006378621 ps
T317 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.46828441300570107030647390740444002382627970259948997733062752968126425843499 Nov 22 02:12:13 PM PST 23 Nov 22 02:14:43 PM PST 23 1371125703 ps
T318 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.43711491722633257954107230264484795133901709726591275619355688742405780974775 Nov 22 02:14:12 PM PST 23 Nov 22 02:44:28 PM PST 23 624328106 ps
T319 /workspace/coverage/default/4.sram_ctrl_bijection.81493687150881062315197486123772082202435413509324700149127004368114148721826 Nov 22 02:07:19 PM PST 23 Nov 22 02:53:26 PM PST 23 295482808505 ps
T320 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.48412645814854914783746376973973472992258429319833668595426475817379994666286 Nov 22 02:17:01 PM PST 23 Nov 22 02:50:22 PM PST 23 624328106 ps
T321 /workspace/coverage/default/24.sram_ctrl_mem_walk.42712161618016160535776313570838128066713168120733352703604264421258816910461 Nov 22 02:13:57 PM PST 23 Nov 22 02:16:38 PM PST 23 18445453393 ps
T322 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.54373157071095779754698978417369768721731336134407037661300806494351865752523 Nov 22 02:15:47 PM PST 23 Nov 22 02:23:07 PM PST 23 9325508496 ps
T323 /workspace/coverage/default/12.sram_ctrl_lc_escalation.74338491368089705711872487970685067245104056722746905801017157361546868493884 Nov 22 02:11:16 PM PST 23 Nov 22 02:13:02 PM PST 23 19084394710 ps
T324 /workspace/coverage/default/33.sram_ctrl_bijection.61592764640079468339838025915002426246511827206570247204701561365830840806082 Nov 22 02:15:35 PM PST 23 Nov 22 02:59:45 PM PST 23 295482808505 ps
T325 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.60322399172968119777093966662978641990499401866523112121258917292617252926637 Nov 22 02:07:19 PM PST 23 Nov 22 02:17:13 PM PST 23 45083829570 ps
T326 /workspace/coverage/default/4.sram_ctrl_alert_test.17567089085791457701283252175618353479915605661995422175673613501514155737795 Nov 22 02:07:36 PM PST 23 Nov 22 02:07:38 PM PST 23 16600825 ps
T327 /workspace/coverage/default/44.sram_ctrl_max_throughput.12315340759943355512664984839500356621025098150738939932871525650973484545539 Nov 22 02:16:39 PM PST 23 Nov 22 02:18:15 PM PST 23 1342947357 ps
T328 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.80554517119117779950336760462864058390311212480092005929725901909156755005205 Nov 22 02:07:37 PM PST 23 Nov 22 02:25:38 PM PST 23 13467153934 ps
T329 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.10457976343755819223109798488690879424301101977286354706507388273700074294779 Nov 22 02:12:18 PM PST 23 Nov 22 02:13:41 PM PST 23 4750777237 ps
T330 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.93505251794622152016126605513988972438779658139999489105786245575448690076461 Nov 22 02:13:55 PM PST 23 Nov 22 02:15:14 PM PST 23 4750777237 ps
T331 /workspace/coverage/default/15.sram_ctrl_regwen.109190861869912521671946782774780139427679318218475552293482472775547944355174 Nov 22 02:11:40 PM PST 23 Nov 22 02:21:07 PM PST 23 19913691647 ps
T332 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.22654687715587345850730870738958311374303617989186370526970421370032874057416 Nov 22 02:13:56 PM PST 23 Nov 22 02:42:56 PM PST 23 624328106 ps
T333 /workspace/coverage/default/30.sram_ctrl_smoke.24265793801018093744796673636541407989197492754895357752807698843943564263513 Nov 22 02:14:55 PM PST 23 Nov 22 02:15:15 PM PST 23 988289480 ps
T334 /workspace/coverage/default/3.sram_ctrl_max_throughput.58960635882585830013513944938818915805206768296930814233539528890551880208926 Nov 22 02:07:25 PM PST 23 Nov 22 02:09:31 PM PST 23 1342947357 ps
T335 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4992841181409713679703256779701040642924192936897093423434251113341104583033 Nov 22 02:17:41 PM PST 23 Nov 22 02:19:00 PM PST 23 4750777237 ps
T336 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.7442252227346184195671398787544675368356971417780599551839123890543518082513 Nov 22 02:17:15 PM PST 23 Nov 22 02:52:50 PM PST 23 624328106 ps
T337 /workspace/coverage/default/2.sram_ctrl_multiple_keys.52720461667914266800863096230877028011119192412669138847079386881521365157339 Nov 22 02:07:07 PM PST 23 Nov 22 02:21:33 PM PST 23 28731174678 ps
T338 /workspace/coverage/default/45.sram_ctrl_ram_cfg.112672165140608483232100512925327916459788915715284291154197857370497004450048 Nov 22 02:16:43 PM PST 23 Nov 22 02:16:50 PM PST 23 607542526 ps
T339 /workspace/coverage/default/23.sram_ctrl_smoke.6287094297135588737948991784245067098462845026704555244479870518368220343572 Nov 22 02:13:13 PM PST 23 Nov 22 02:13:29 PM PST 23 988289480 ps
T340 /workspace/coverage/default/4.sram_ctrl_ram_cfg.23544183102529801035311026988898207791938329870035770129049304437683965416387 Nov 22 02:07:21 PM PST 23 Nov 22 02:07:29 PM PST 23 607542526 ps
T341 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3691624191321070142278266637718006606902331353866526680452535118482157851675 Nov 22 02:17:48 PM PST 23 Nov 22 02:27:00 PM PST 23 45083829570 ps
T342 /workspace/coverage/default/40.sram_ctrl_smoke.43698978876317467424344775476383738792538643679796437664203448387100835683179 Nov 22 02:16:12 PM PST 23 Nov 22 02:16:31 PM PST 23 988289480 ps
T343 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.22794181751631717761436734434572184271773747005259774961947085411447826701401 Nov 22 02:14:41 PM PST 23 Nov 22 02:30:27 PM PST 23 13467153934 ps
T344 /workspace/coverage/default/28.sram_ctrl_regwen.37041799974621041045825550250519013707424750443396161953149256720587711145310 Nov 22 02:14:11 PM PST 23 Nov 22 02:24:00 PM PST 23 19913691647 ps
T345 /workspace/coverage/default/9.sram_ctrl_ram_cfg.35178251220130458365693986129317196602541927516718996865908960882249439334565 Nov 22 02:07:34 PM PST 23 Nov 22 02:07:43 PM PST 23 607542526 ps
T346 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.17205778229473446099319106103099986125965617817991942581425988029559745433805 Nov 22 02:16:36 PM PST 23 Nov 22 02:17:57 PM PST 23 4750777237 ps
T347 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.100711183190809799664911073565198779292460675659868794974912425814391001072761 Nov 22 02:13:57 PM PST 23 Nov 22 02:15:50 PM PST 23 1371125703 ps
T348 /workspace/coverage/default/47.sram_ctrl_multiple_keys.81298309424623664525568047960716248997246619035782835211575162398444273551038 Nov 22 02:17:02 PM PST 23 Nov 22 02:32:27 PM PST 23 28731174678 ps
T349 /workspace/coverage/default/49.sram_ctrl_ram_cfg.43008476459499284227224041666811383809525118990032511111811914453776698560024 Nov 22 02:17:51 PM PST 23 Nov 22 02:17:57 PM PST 23 607542526 ps
T350 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.31597266741867244481067568364386300570474786341427271872959996694335704888816 Nov 22 02:12:17 PM PST 23 Nov 22 02:13:40 PM PST 23 4750777237 ps
T351 /workspace/coverage/default/29.sram_ctrl_executable.115436456683706574833132744691855544120718543891166852030870524170244286322669 Nov 22 02:14:36 PM PST 23 Nov 22 02:29:41 PM PST 23 31712811539 ps
T352 /workspace/coverage/default/7.sram_ctrl_max_throughput.61217523742951322401416630921632399718726622538522529410188349868183935006112 Nov 22 02:07:39 PM PST 23 Nov 22 02:09:59 PM PST 23 1342947357 ps
T353 /workspace/coverage/default/2.sram_ctrl_max_throughput.73058362475170429976431835800188485497131028164472328890721263436476799338127 Nov 22 02:07:07 PM PST 23 Nov 22 02:09:16 PM PST 23 1342947357 ps
T354 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.100696312781752067234687477586756662918688158371347128643475868849179233036584 Nov 22 02:12:54 PM PST 23 Nov 22 02:14:11 PM PST 23 4750777237 ps
T355 /workspace/coverage/default/11.sram_ctrl_ram_cfg.91756484503571847540499783965559176708292495216170506896176136247052672672748 Nov 22 02:11:16 PM PST 23 Nov 22 02:11:23 PM PST 23 607542526 ps
T356 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.48825259845798022767200028753861049400760937746506998988676448170247884889594 Nov 22 02:12:58 PM PST 23 Nov 22 02:14:52 PM PST 23 1371125703 ps
T357 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1419254284051700224128733722599549630159848685259732068869802020218899312667 Nov 22 02:17:41 PM PST 23 Nov 22 02:45:45 PM PST 23 624328106 ps
T358 /workspace/coverage/default/27.sram_ctrl_regwen.20544292802065967355302111219794036027174447096697887547177875173258391927392 Nov 22 02:14:05 PM PST 23 Nov 22 02:25:47 PM PST 23 19913691647 ps
T359 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.12057857139972953262060379967775720408636630457868853003160238685229774065276 Nov 22 02:12:32 PM PST 23 Nov 22 02:28:08 PM PST 23 13467153934 ps
T360 /workspace/coverage/default/27.sram_ctrl_alert_test.29113145535570614229278822599195154624423538817568696063561914574577253584832 Nov 22 02:14:15 PM PST 23 Nov 22 02:14:17 PM PST 23 16600825 ps
T361 /workspace/coverage/default/25.sram_ctrl_bijection.106238657245000166460704836953804349648957106403812299804654974575796600421221 Nov 22 02:13:44 PM PST 23 Nov 22 03:00:29 PM PST 23 295482808505 ps
T362 /workspace/coverage/default/46.sram_ctrl_bijection.46380155454824362851517129777515245574048075828564421388916744018871601213754 Nov 22 02:16:38 PM PST 23 Nov 22 03:02:42 PM PST 23 295482808505 ps
T363 /workspace/coverage/default/6.sram_ctrl_executable.67115242294128130532754715715254747254249536910416760414468155273498923832474 Nov 22 02:07:38 PM PST 23 Nov 22 02:22:16 PM PST 23 31712811539 ps
T364 /workspace/coverage/default/36.sram_ctrl_executable.12855434829414845135527653813949338107238080635092199653913476110435834100090 Nov 22 02:15:39 PM PST 23 Nov 22 02:30:22 PM PST 23 31712811539 ps
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T366 /workspace/coverage/default/26.sram_ctrl_bijection.82406194974144047800143352229854403540799263565529924460388912512757720737037 Nov 22 02:13:55 PM PST 23 Nov 22 02:59:49 PM PST 23 295482808505 ps
T367 /workspace/coverage/default/12.sram_ctrl_partial_access.105701769554508972811302893890140640360659578095479158445788335264184982906558 Nov 22 02:11:17 PM PST 23 Nov 22 02:11:35 PM PST 23 1006378621 ps
T368 /workspace/coverage/default/32.sram_ctrl_partial_access.60285546051398254619194266005402864635804291555595216735152543545564404598630 Nov 22 02:15:30 PM PST 23 Nov 22 02:15:49 PM PST 23 1006378621 ps
T369 /workspace/coverage/default/32.sram_ctrl_ram_cfg.113012573273461409443896176246560653867384055926289424849046789529037227897399 Nov 22 02:14:55 PM PST 23 Nov 22 02:15:04 PM PST 23 607542526 ps
T370 /workspace/coverage/default/36.sram_ctrl_lc_escalation.76223199221685896448251480885957819859135364812353216447271908908701538427759 Nov 22 02:15:40 PM PST 23 Nov 22 02:17:26 PM PST 23 19084394710 ps
T371 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.43320943159546433670105093199957010620578722692140357934667982145912590333332 Nov 22 02:07:21 PM PST 23 Nov 22 02:38:45 PM PST 23 624328106 ps
T372 /workspace/coverage/default/9.sram_ctrl_executable.84656631706031949332650161683363264379777477520476938178189582940856530936391 Nov 22 02:07:41 PM PST 23 Nov 22 02:19:53 PM PST 23 31712811539 ps
T373 /workspace/coverage/default/42.sram_ctrl_lc_escalation.42938404189725941993755645437285453429847474520951528199593496133174577262496 Nov 22 02:16:27 PM PST 23 Nov 22 02:18:13 PM PST 23 19084394710 ps
T374 /workspace/coverage/default/2.sram_ctrl_alert_test.95395660652582139058018372167972137592600631049812847435043105369658074271292 Nov 22 02:07:06 PM PST 23 Nov 22 02:07:12 PM PST 23 16600825 ps
T375 /workspace/coverage/default/15.sram_ctrl_mem_walk.89834793035270434199439988891336707288553484626333531249577939183077802449146 Nov 22 02:11:40 PM PST 23 Nov 22 02:14:18 PM PST 23 18445453393 ps
T376 /workspace/coverage/default/45.sram_ctrl_lc_escalation.4559139940114826572017761608795074876499918477233135673954866060913813560906 Nov 22 02:16:37 PM PST 23 Nov 22 02:18:25 PM PST 23 19084394710 ps
T377 /workspace/coverage/default/47.sram_ctrl_lc_escalation.77090052606012925286491248360510387322968705906100091716303691985995068917427 Nov 22 02:17:02 PM PST 23 Nov 22 02:18:48 PM PST 23 19084394710 ps
T378 /workspace/coverage/default/48.sram_ctrl_lc_escalation.2098239010684946790612084963890981095143942798605545730283818383041837486085 Nov 22 02:17:32 PM PST 23 Nov 22 02:19:18 PM PST 23 19084394710 ps
T379 /workspace/coverage/default/45.sram_ctrl_executable.106317762880479615883226399605694337070550342522907051405774205667351597689940 Nov 22 02:16:37 PM PST 23 Nov 22 02:30:03 PM PST 23 31712811539 ps
T380 /workspace/coverage/default/49.sram_ctrl_smoke.53743558366974966682160792969840176812339087246351580258314061135144850193665 Nov 22 02:17:12 PM PST 23 Nov 22 02:17:30 PM PST 23 988289480 ps
T381 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.9275550850712727527756341910759490770196977533299614592448012321193314728839 Nov 22 02:14:35 PM PST 23 Nov 22 02:48:54 PM PST 23 624328106 ps
T382 /workspace/coverage/default/17.sram_ctrl_lc_escalation.51949284885184848952700305238183920767464724140739659529166616908221167592636 Nov 22 02:12:18 PM PST 23 Nov 22 02:14:02 PM PST 23 19084394710 ps
T383 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.108767298176388597187350584688388943845700835102983536038829219917848332996376 Nov 22 02:17:31 PM PST 23 Nov 22 02:34:23 PM PST 23 13467153934 ps
T384 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.48437189816544566373340210398352915614997231282704164173442983400460606422663 Nov 22 02:16:35 PM PST 23 Nov 22 02:17:56 PM PST 23 4750777237 ps
T385 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.20787457245158070061187041479544195945603802595047817619859837811704823658869 Nov 22 02:16:28 PM PST 23 Nov 22 02:45:35 PM PST 23 624328106 ps
T386 /workspace/coverage/default/6.sram_ctrl_bijection.102748158618039133091634252200586740617455684010858829559040778094405829115102 Nov 22 02:07:42 PM PST 23 Nov 22 02:53:33 PM PST 23 295482808505 ps
T387 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.10917571167172060674681843982468791425248426540234734159005483067763069260161 Nov 22 02:16:37 PM PST 23 Nov 22 02:18:45 PM PST 23 1371125703 ps
T388 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.52550108142396070677858716695431826313322645886976701424453715590924320135560 Nov 22 02:16:29 PM PST 23 Nov 22 02:48:53 PM PST 23 624328106 ps
T389 /workspace/coverage/default/40.sram_ctrl_bijection.81108153299753179696564026456400937391596269862294071083266482765719565572197 Nov 22 02:16:31 PM PST 23 Nov 22 03:01:48 PM PST 23 295482808505 ps
T390 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.48869948700450274565363325836072421677170893126698253756135140083752742354041 Nov 22 02:15:55 PM PST 23 Nov 22 02:17:13 PM PST 23 4750777237 ps
T391 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3109839682380101941845871417334310444698122262889432160282066338647757870286 Nov 22 02:17:02 PM PST 23 Nov 22 02:49:08 PM PST 23 624328106 ps
T392 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.105025907989423617573331296326744652475459722092215863184617168360131346464653 Nov 22 02:07:21 PM PST 23 Nov 22 02:08:43 PM PST 23 4750777237 ps
T393 /workspace/coverage/default/37.sram_ctrl_partial_access.43754925797754263790345646227920119121546918138416808676181810018664281742209 Nov 22 02:15:57 PM PST 23 Nov 22 02:16:16 PM PST 23 1006378621 ps
T394 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.63153675436842114804874307210651498193549230656077143570357180378131978125982 Nov 22 02:16:43 PM PST 23 Nov 22 02:26:10 PM PST 23 45083829570 ps
T395 /workspace/coverage/default/29.sram_ctrl_bijection.1398360790013502445662206392112566367488386020396673913168382833010400308538 Nov 22 02:14:14 PM PST 23 Nov 22 03:00:29 PM PST 23 295482808505 ps
T396 /workspace/coverage/default/40.sram_ctrl_mem_walk.13724513492180425006469210074286003374175706832904607416022493430280825678651 Nov 22 02:16:19 PM PST 23 Nov 22 02:19:00 PM PST 23 18445453393 ps
T397 /workspace/coverage/default/1.sram_ctrl_alert_test.3784617781505200413903724876986551372773407261379642724891136635944632944759 Nov 22 02:07:18 PM PST 23 Nov 22 02:07:19 PM PST 23 16600825 ps
T398 /workspace/coverage/default/12.sram_ctrl_regwen.19552600604423705769363906076205344330139576503023217734457442480624266275066 Nov 22 02:11:18 PM PST 23 Nov 22 02:20:57 PM PST 23 19913691647 ps
T399 /workspace/coverage/default/21.sram_ctrl_alert_test.42151710758020254534406361365622310981144422707564633759089823259910968859536 Nov 22 02:13:00 PM PST 23 Nov 22 02:13:02 PM PST 23 16600825 ps
T400 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.17588889393210929877699582787642651193187453482711209697365279856079983294462 Nov 22 02:14:52 PM PST 23 Nov 22 02:31:18 PM PST 23 13467153934 ps
T401 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.112653607518444256768650824095321067464890033491846586314556317132098107094382 Nov 22 02:17:19 PM PST 23 Nov 22 02:19:24 PM PST 23 1371125703 ps
T402 /workspace/coverage/default/9.sram_ctrl_mem_walk.74387499023917631561761947029301335891050939120758801768215378658433542102011 Nov 22 02:07:42 PM PST 23 Nov 22 02:10:20 PM PST 23 18445453393 ps
T403 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.20084946614398365236644662669625655420390325393454562351033970762117812588099 Nov 22 02:14:54 PM PST 23 Nov 22 02:43:26 PM PST 23 624328106 ps
T404 /workspace/coverage/default/14.sram_ctrl_ram_cfg.45378232298444185736789048206659088647356037758691092321248127701740825462261 Nov 22 02:11:28 PM PST 23 Nov 22 02:11:35 PM PST 23 607542526 ps
T405 /workspace/coverage/default/23.sram_ctrl_multiple_keys.40051652075309415904579464463883329634569313755080422721263487566286835362365 Nov 22 02:13:16 PM PST 23 Nov 22 02:25:43 PM PST 23 28731174678 ps
T406 /workspace/coverage/default/4.sram_ctrl_lc_escalation.85879920270239234296237992465392637311792927516480550187132522145257591206581 Nov 22 02:07:19 PM PST 23 Nov 22 02:09:02 PM PST 23 19084394710 ps
T407 /workspace/coverage/default/39.sram_ctrl_executable.60816276539070885268144314143501002571136613908952331842111003440400775812383 Nov 22 02:16:17 PM PST 23 Nov 22 02:29:17 PM PST 23 31712811539 ps
T408 /workspace/coverage/default/34.sram_ctrl_smoke.100402601544450098298222369865462294965396361917568535451806958331110526384915 Nov 22 02:15:40 PM PST 23 Nov 22 02:15:58 PM PST 23 988289480 ps
T409 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.105003182911112234733474697567948453563560601485319497610783430763452558962874 Nov 22 02:12:21 PM PST 23 Nov 22 02:50:47 PM PST 23 624328106 ps
T410 /workspace/coverage/default/4.sram_ctrl_max_throughput.33417121669638035989610098003270704078733397101518369626099125120892188946970 Nov 22 02:07:21 PM PST 23 Nov 22 02:09:15 PM PST 23 1342947357 ps
T411 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.26496178508254375919362205388428167330100119551467552649598426807186071806281 Nov 22 02:11:28 PM PST 23 Nov 22 02:20:50 PM PST 23 45083829570 ps
T412 /workspace/coverage/default/30.sram_ctrl_alert_test.73594625043195208420977379577087241472491171879037176023731966388954645024023 Nov 22 02:14:54 PM PST 23 Nov 22 02:14:59 PM PST 23 16600825 ps
T413 /workspace/coverage/default/19.sram_ctrl_mem_walk.38721964564818971263548621525049042914843623676156000227680447502145874353552 Nov 22 02:12:50 PM PST 23 Nov 22 02:15:31 PM PST 23 18445453393 ps
T414 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.22034230303643971210186712465717928281006311417036508654684250112181019392913 Nov 22 02:13:15 PM PST 23 Nov 22 02:14:32 PM PST 23 4750777237 ps
T415 /workspace/coverage/default/45.sram_ctrl_smoke.95125434252259660796512650567017678885114179199485607708501082707537648516663 Nov 22 02:16:41 PM PST 23 Nov 22 02:16:59 PM PST 23 988289480 ps
T416 /workspace/coverage/default/35.sram_ctrl_multiple_keys.56963274442479364656076181303183696223383675603680843534292155305494275105928 Nov 22 02:15:44 PM PST 23 Nov 22 02:28:17 PM PST 23 28731174678 ps
T417 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.85370606620458465883172396608660312553064483507858223226030590639402740600363 Nov 22 02:07:35 PM PST 23 Nov 22 02:09:22 PM PST 23 1371125703 ps
T418 /workspace/coverage/default/47.sram_ctrl_executable.52696245884594912039411789052627636990867442142783394043989686848315465855320 Nov 22 02:17:06 PM PST 23 Nov 22 02:28:59 PM PST 23 31712811539 ps
T419 /workspace/coverage/default/43.sram_ctrl_alert_test.11677680995045534522873307454067886256657889721969617609217304296809166323783 Nov 22 02:16:33 PM PST 23 Nov 22 02:16:34 PM PST 23 16600825 ps
T420 /workspace/coverage/default/1.sram_ctrl_ram_cfg.71303009588920609749847813355830880482365359057078640167562394503485861667377 Nov 22 02:07:20 PM PST 23 Nov 22 02:07:27 PM PST 23 607542526 ps
T421 /workspace/coverage/default/39.sram_ctrl_lc_escalation.46455225594263558323970738618487204582986815920175819038778529027261073003640 Nov 22 02:16:33 PM PST 23 Nov 22 02:18:17 PM PST 23 19084394710 ps
T422 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.109604443241149142447747349082883098446234135615133525806930269931869296924781 Nov 22 02:13:19 PM PST 23 Nov 22 02:15:28 PM PST 23 1371125703 ps
T423 /workspace/coverage/default/7.sram_ctrl_smoke.49274818990814182145567366411305697340028874606429047186414772665315503489400 Nov 22 02:07:36 PM PST 23 Nov 22 02:07:56 PM PST 23 988289480 ps
T424 /workspace/coverage/default/49.sram_ctrl_alert_test.90886941699910329589604253058268331435167948038507840110367476489532052137786 Nov 22 02:18:07 PM PST 23 Nov 22 02:18:09 PM PST 23 16600825 ps
T425 /workspace/coverage/default/9.sram_ctrl_alert_test.107021559134521326914093253985917695878937632483501998550102514952374875516480 Nov 22 02:07:38 PM PST 23 Nov 22 02:07:41 PM PST 23 16600825 ps
T426 /workspace/coverage/default/0.sram_ctrl_max_throughput.85652975483871234728381981842917060815707291328649225938429152912811534675205 Nov 22 02:07:07 PM PST 23 Nov 22 02:08:54 PM PST 23 1342947357 ps
T427 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.12009702370980687489173292276593207000183184115557048912629876173600869836784 Nov 22 02:16:28 PM PST 23 Nov 22 02:26:05 PM PST 23 45083829570 ps
T428 /workspace/coverage/default/8.sram_ctrl_smoke.24057397384362640996312320591079873172944216252875204398778786823304368887383 Nov 22 02:07:36 PM PST 23 Nov 22 02:07:56 PM PST 23 988289480 ps
T429 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.78771247127464952379127593013889199909048709415022672961673004368133133125020 Nov 22 02:07:02 PM PST 23 Nov 22 02:09:09 PM PST 23 1371125703 ps
T430 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.24750137753452791108876723449910718521509640937749735735933932507808718421555 Nov 22 02:11:26 PM PST 23 Nov 22 02:28:01 PM PST 23 13467153934 ps
T431 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.22034292843912522763281539341761366903346535258173443158484639204601466201200 Nov 22 02:07:05 PM PST 23 Nov 22 02:14:20 PM PST 23 9325508496 ps
T432 /workspace/coverage/default/39.sram_ctrl_mem_walk.22239616931141311000666627986256954588423158076955429168544292685138784901522 Nov 22 02:16:35 PM PST 23 Nov 22 02:19:18 PM PST 23 18445453393 ps
T433 /workspace/coverage/default/14.sram_ctrl_alert_test.1915489783793400716692169033799684492363125029078432516116676430539684594837 Nov 22 02:11:35 PM PST 23 Nov 22 02:11:36 PM PST 23 16600825 ps
T434 /workspace/coverage/default/19.sram_ctrl_max_throughput.51234561885161516733370699505124031324514766509228860953364016919094178954193 Nov 22 02:12:32 PM PST 23 Nov 22 02:14:42 PM PST 23 1342947357 ps
T435 /workspace/coverage/default/45.sram_ctrl_bijection.1921377752269692838661618528114667518818760175566460363144359772185299323188 Nov 22 02:16:40 PM PST 23 Nov 22 03:02:08 PM PST 23 295482808505 ps
T436 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.81813567286114882489926477698917233205423423409735740926145129581817848310767 Nov 22 02:16:30 PM PST 23 Nov 22 02:31:24 PM PST 23 13467153934 ps
T437 /workspace/coverage/default/35.sram_ctrl_lc_escalation.36315286697769896124129428172773932622111942054747895283622100691607115541728 Nov 22 02:16:09 PM PST 23 Nov 22 02:17:53 PM PST 23 19084394710 ps
T438 /workspace/coverage/default/17.sram_ctrl_multiple_keys.16686215553983864261829765444293065453383513275020482731639721573576270564442 Nov 22 02:12:00 PM PST 23 Nov 22 02:27:25 PM PST 23 28731174678 ps
T439 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.73338947530284451646132270999938009753354384537854434305400727515757753196099 Nov 22 02:07:21 PM PST 23 Nov 22 02:16:45 PM PST 23 45083829570 ps
T440 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.10657166697164871967077600534942605322214486456591667255297721196023224974802 Nov 22 02:16:41 PM PST 23 Nov 22 02:23:44 PM PST 23 9325508496 ps
T441 /workspace/coverage/default/28.sram_ctrl_max_throughput.62014475693522555095737417963038931917201104754555959548572855415888252960077 Nov 22 02:14:15 PM PST 23 Nov 22 02:16:25 PM PST 23 1342947357 ps
T442 /workspace/coverage/default/5.sram_ctrl_multiple_keys.107907240717704071074667170415711036680416472249873398212699980841010925907443 Nov 22 02:07:38 PM PST 23 Nov 22 02:24:33 PM PST 23 28731174678 ps
T443 /workspace/coverage/default/6.sram_ctrl_max_throughput.88620919540147095445186739418184537606555046568364243035781742984869161638621 Nov 22 02:07:24 PM PST 23 Nov 22 02:09:33 PM PST 23 1342947357 ps
T444 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.63296679439965636533613506908147783398482615268328693658994415675931057442810 Nov 22 02:07:42 PM PST 23 Nov 22 02:17:09 PM PST 23 45083829570 ps
T445 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.76412885372498138021850435258278869437648852566943916200603248471582690971383 Nov 22 02:17:03 PM PST 23 Nov 22 02:34:31 PM PST 23 13467153934 ps
T446 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.62521797604419582756554224442469152689709004307806924390303946255032872554998 Nov 22 02:17:06 PM PST 23 Nov 22 02:26:42 PM PST 23 45083829570 ps
T447 /workspace/coverage/default/31.sram_ctrl_alert_test.4308242794931653420655323061114387781305318544751227600785423317831583718176 Nov 22 02:14:56 PM PST 23 Nov 22 02:14:59 PM PST 23 16600825 ps
T448 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.37566966840750595155796128065359667250276728982624196007890719813038455684885 Nov 22 02:17:08 PM PST 23 Nov 22 02:18:34 PM PST 23 4750777237 ps
T24 /workspace/coverage/default/4.sram_ctrl_sec_cm.94862616190992729263057295706826492395745614968360716304602738992705684462267 Nov 22 02:07:35 PM PST 23 Nov 22 02:07:40 PM PST 23 216402798 ps
T38 /workspace/coverage/default/6.sram_ctrl_mem_walk.95889045330545241430044198529172259115391201664297222909761381102490650178975 Nov 22 02:07:34 PM PST 23 Nov 22 02:10:16 PM PST 23 18445453393 ps
T39 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.46839457415934113709443131573439204873889836457048269574615436742410584857317 Nov 22 02:13:56 PM PST 23 Nov 22 02:23:22 PM PST 23 45083829570 ps
T40 /workspace/coverage/default/46.sram_ctrl_executable.107628686823709468994739473634154098952601528798725235326838085164508659231068 Nov 22 02:17:08 PM PST 23 Nov 22 02:30:01 PM PST 23 31712811539 ps
T41 /workspace/coverage/default/23.sram_ctrl_regwen.4233760943593005474905764455524659628575727815591181160064700526410616497037 Nov 22 02:13:16 PM PST 23 Nov 22 02:22:47 PM PST 23 19913691647 ps
T42 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.10166387311563545568446565678934943598689530522108952290518255170624536479509 Nov 22 02:16:42 PM PST 23 Nov 22 02:32:01 PM PST 23 13467153934 ps
T43 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.25873578498341103532309778636349489537888402650520699001742666069652420492002 Nov 22 02:16:28 PM PST 23 Nov 22 02:26:08 PM PST 23 45083829570 ps
T44 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.74075858969977856908552538678977049872174033098500144197094000165352522764031 Nov 22 02:07:21 PM PST 23 Nov 22 02:17:13 PM PST 23 45083829570 ps
T45 /workspace/coverage/default/30.sram_ctrl_max_throughput.7818571356374555986703376786362293905823911022163094566460336339287246132801 Nov 22 02:14:43 PM PST 23 Nov 22 02:16:49 PM PST 23 1342947357 ps
T46 /workspace/coverage/default/25.sram_ctrl_lc_escalation.105735745859239714550126216054104341743823974451986059801971799018579941350782 Nov 22 02:13:51 PM PST 23 Nov 22 02:15:37 PM PST 23 19084394710 ps
T449 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.22845984289649760749501583469985013976370074580370087382748655387970001193841 Nov 22 02:13:47 PM PST 23 Nov 22 02:15:22 PM PST 23 1371125703 ps
T450 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.44474049413164534375309748170518876753380902437104481328726623802635602346310 Nov 22 02:11:17 PM PST 23 Nov 22 02:13:06 PM PST 23 1371125703 ps
T451 /workspace/coverage/default/49.sram_ctrl_multiple_keys.70586391532034761857273383149262828399695045484056633265495423769725171337959 Nov 22 02:17:15 PM PST 23 Nov 22 02:31:25 PM PST 23 28731174678 ps
T452 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.59418765429074480685876878977182214398724874284757977447566215218609687959448 Nov 22 02:07:21 PM PST 23 Nov 22 02:39:42 PM PST 23 624328106 ps
T453 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.15064598150323865400946681521429663685404510225230199012391889645535077252481 Nov 22 02:11:16 PM PST 23 Nov 22 02:25:55 PM PST 23 13467153934 ps
T454 /workspace/coverage/default/37.sram_ctrl_multiple_keys.900926893051005991284449800105610208099522215279061189173414384931748957592 Nov 22 02:15:42 PM PST 23 Nov 22 02:29:10 PM PST 23 28731174678 ps
T455 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.114477218268314570846733036185158609380496033008494203138794822546902358087391 Nov 22 02:07:19 PM PST 23 Nov 22 02:14:26 PM PST 23 9325508496 ps
T456 /workspace/coverage/default/2.sram_ctrl_partial_access.107342562868949019702770640961260822683855483719016497049826902477377907019725 Nov 22 02:07:20 PM PST 23 Nov 22 02:07:41 PM PST 23 1006378621 ps
T457 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.15357777738368425574205823354918225420530640919349964141062309412898199612414 Nov 22 02:07:43 PM PST 23 Nov 22 02:09:12 PM PST 23 1371125703 ps
T458 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.59775394302855025265042629330642083733435463193133392630018850624277079723866 Nov 22 02:12:16 PM PST 23 Nov 22 02:19:20 PM PST 23 9325508496 ps
T459 /workspace/coverage/default/33.sram_ctrl_regwen.73651424523608268968747639348874304942392827565087392444708287660349718909096 Nov 22 02:14:58 PM PST 23 Nov 22 02:24:16 PM PST 23 19913691647 ps
T460 /workspace/coverage/default/9.sram_ctrl_regwen.63613966651725075347927428427625827333870372824522713616653838992611344626684 Nov 22 02:07:38 PM PST 23 Nov 22 02:18:22 PM PST 23 19913691647 ps
T461 /workspace/coverage/default/10.sram_ctrl_multiple_keys.91335809470540223544602720429995434915865818290569560338340445349470177611934 Nov 22 02:07:38 PM PST 23 Nov 22 02:22:14 PM PST 23 28731174678 ps
T462 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.87005508989434857250588017944937022246687607173719053345334914326967039694655 Nov 22 02:12:57 PM PST 23 Nov 22 02:28:32 PM PST 23 13467153934 ps
T463 /workspace/coverage/default/35.sram_ctrl_regwen.249095944332486127729293394130891832904205094404766405831946290489203881940 Nov 22 02:15:41 PM PST 23 Nov 22 02:24:03 PM PST 23 19913691647 ps
T464 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.25732866058195862692473390119177763595835934093235118213634009885663687052248 Nov 22 02:16:31 PM PST 23 Nov 22 02:17:47 PM PST 23 4750777237 ps
T465 /workspace/coverage/default/7.sram_ctrl_alert_test.103117777682120731127160767191492593568299340030099959761419697659610657987301 Nov 22 02:07:37 PM PST 23 Nov 22 02:07:40 PM PST 23 16600825 ps
T466 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.114751904522240563823415875018483432625682716427760108686365024668403508533821 Nov 22 02:15:40 PM PST 23 Nov 22 02:17:54 PM PST 23 1371125703 ps
T467 /workspace/coverage/default/30.sram_ctrl_executable.21530775677461038870514654964625250795536244932335746653829680982562712321568 Nov 22 02:14:41 PM PST 23 Nov 22 02:27:18 PM PST 23 31712811539 ps
T468 /workspace/coverage/default/37.sram_ctrl_regwen.86395880569733162336951939425182209671510236742075413851979181162844710060220 Nov 22 02:16:33 PM PST 23 Nov 22 02:24:41 PM PST 23 19913691647 ps
T469 /workspace/coverage/default/1.sram_ctrl_mem_walk.54345307656035657241134135983740707102611792545987693951561583715973283628855 Nov 22 02:07:19 PM PST 23 Nov 22 02:09:57 PM PST 23 18445453393 ps
T470 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.35756850921890578285149376383755458514939378583386466604697764667285653619687 Nov 22 02:13:16 PM PST 23 Nov 22 02:20:46 PM PST 23 9325508496 ps
T471 /workspace/coverage/default/1.sram_ctrl_lc_escalation.74617542037004636652741300235135838693542823657918374609564727249464413365933 Nov 22 02:07:20 PM PST 23 Nov 22 02:09:06 PM PST 23 19084394710 ps
T472 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.101849600205718104502918889709366997979571189422636223350125682782910747219638 Nov 22 02:11:40 PM PST 23 Nov 22 02:13:02 PM PST 23 4750777237 ps
T473 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.86214541454427303232245346088711491481490857056308436524626036899990263371124 Nov 22 02:11:17 PM PST 23 Nov 22 02:18:05 PM PST 23 9325508496 ps
T474 /workspace/coverage/default/16.sram_ctrl_regwen.107889197396681137610076462431774698064105581869244337383820114740934644173686 Nov 22 02:12:15 PM PST 23 Nov 22 02:21:03 PM PST 23 19913691647 ps
T475 /workspace/coverage/default/16.sram_ctrl_bijection.65326532910713526934138083472741591386976442931705688626963234824384099467735 Nov 22 02:11:41 PM PST 23 Nov 22 02:56:52 PM PST 23 295482808505 ps
T476 /workspace/coverage/default/27.sram_ctrl_bijection.96423693120682871844179731739397830129225443534172134511732452501015727380271 Nov 22 02:14:00 PM PST 23 Nov 22 02:59:46 PM PST 23 295482808505 ps
T477 /workspace/coverage/default/14.sram_ctrl_executable.98174202291538497887943670299603644215706276643363576592987634837458190485433 Nov 22 02:11:27 PM PST 23 Nov 22 02:25:37 PM PST 23 31712811539 ps
T478 /workspace/coverage/default/47.sram_ctrl_alert_test.22342060555500297485253501114614226475212180356454190038950338826913203272214 Nov 22 02:17:02 PM PST 23 Nov 22 02:17:06 PM PST 23 16600825 ps
T479 /workspace/coverage/default/42.sram_ctrl_ram_cfg.19387482073610279008477401016235139746083860753517595769098411107588309063527 Nov 22 02:16:39 PM PST 23 Nov 22 02:16:45 PM PST 23 607542526 ps
T480 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.81164926440714900944250202222477735949535612010529507896385923011495516967713 Nov 22 02:07:35 PM PST 23 Nov 22 02:09:34 PM PST 23 1371125703 ps
T481 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.111589572823822414375847944635928814080721615319557463735099939497582709168919 Nov 22 02:16:18 PM PST 23 Nov 22 02:51:25 PM PST 23 624328106 ps
T482 /workspace/coverage/default/25.sram_ctrl_regwen.67753774373124696901902254268741198761427253250953962291220871580657437186656 Nov 22 02:13:54 PM PST 23 Nov 22 02:23:26 PM PST 23 19913691647 ps
T483 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.47030040766206898390652754985531755095215694810065439383717092985803395115791 Nov 22 02:16:16 PM PST 23 Nov 22 02:25:57 PM PST 23 45083829570 ps
T484 /workspace/coverage/default/38.sram_ctrl_ram_cfg.49920883607760877312706712563492771093697173221931315061922057109293219155150 Nov 22 02:16:12 PM PST 23 Nov 22 02:16:19 PM PST 23 607542526 ps
T485 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.69354047678141778331902502834216526978046309372010089758735065426373319907733 Nov 22 02:16:18 PM PST 23 Nov 22 02:33:30 PM PST 23 13467153934 ps
T486 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.29918625018118436882535956124933733737891396940139441782534773977732346271344 Nov 22 02:07:20 PM PST 23 Nov 22 02:08:41 PM PST 23 4750777237 ps
T487 /workspace/coverage/default/25.sram_ctrl_multiple_keys.48419650153612422391004466968134835744611991398717678184239095631678436848615 Nov 22 02:13:35 PM PST 23 Nov 22 02:25:28 PM PST 23 28731174678 ps
T488 /workspace/coverage/default/2.sram_ctrl_regwen.31292248498677221770169231580775040708300180716279129803775455515683849718545 Nov 22 02:07:10 PM PST 23 Nov 22 02:16:59 PM PST 23 19913691647 ps
T489 /workspace/coverage/default/37.sram_ctrl_mem_walk.103851882710681783369752967406881566141139198216326482875551473249844078618426 Nov 22 02:16:39 PM PST 23 Nov 22 02:19:17 PM PST 23 18445453393 ps
T490 /workspace/coverage/default/23.sram_ctrl_ram_cfg.74325632490492450018417728132142480039230782308761865320097341515564610106516 Nov 22 02:13:43 PM PST 23 Nov 22 02:13:50 PM PST 23 607542526 ps
T491 /workspace/coverage/default/15.sram_ctrl_alert_test.79409834359400708856301331718826916284550458155548313841277356195378814287124 Nov 22 02:11:41 PM PST 23 Nov 22 02:11:42 PM PST 23 16600825 ps
T492 /workspace/coverage/default/25.sram_ctrl_smoke.72764243242055576377797031815972742092803987276508424912917560799603360530765 Nov 22 02:13:54 PM PST 23 Nov 22 02:14:13 PM PST 23 988289480 ps
T493 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.41715627464580945268088517399409070983093463365156512661940723560636067979259 Nov 22 02:07:40 PM PST 23 Nov 22 02:14:30 PM PST 23 9325508496 ps
T494 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.77060691526591415744016096133051562746257959009826663340760492877953539715221 Nov 22 02:07:22 PM PST 23 Nov 22 02:09:16 PM PST 23 1371125703 ps
T495 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.23589700146980345047941371167549403051587223642539718879805256891926629174092 Nov 22 02:12:52 PM PST 23 Nov 22 02:40:36 PM PST 23 624328106 ps
T496 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.15402216294457349776817097149524923460137619741348558020340018306127216994562 Nov 22 02:14:51 PM PST 23 Nov 22 02:24:23 PM PST 23 45083829570 ps
T497 /workspace/coverage/default/21.sram_ctrl_multiple_keys.113916024150543722347091873669021126661478505806789977481315512876119331944131 Nov 22 02:12:43 PM PST 23 Nov 22 02:25:33 PM PST 23 28731174678 ps
T498 /workspace/coverage/default/32.sram_ctrl_alert_test.85898214444470970515811055853133366439158120897065140301883410261050163687708 Nov 22 02:15:31 PM PST 23 Nov 22 02:15:32 PM PST 23 16600825 ps
T499 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.30760328185372152549276691211379360483698900858485034006656096565675124734666 Nov 22 02:11:27 PM PST 23 Nov 22 02:12:48 PM PST 23 4750777237 ps
T500 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.110273451304064873710996005335786531066357471261188320984051256845104031901127 Nov 22 02:07:35 PM PST 23 Nov 22 02:17:14 PM PST 23 45083829570 ps
T501 /workspace/coverage/default/48.sram_ctrl_max_throughput.64647420309797065029237542367658563373508035537234565777947909139069953511332 Nov 22 02:17:34 PM PST 23 Nov 22 02:19:37 PM PST 23 1342947357 ps
T502 /workspace/coverage/default/49.sram_ctrl_regwen.65136745524426823013695220452767464518589255437491267131155694836854492848069 Nov 22 02:17:16 PM PST 23 Nov 22 02:27:46 PM PST 23 19913691647 ps
T503 /workspace/coverage/default/23.sram_ctrl_lc_escalation.47055454269059721263546711477190845552841418087099070088495043684607772948851 Nov 22 02:13:18 PM PST 23 Nov 22 02:15:00 PM PST 23 19084394710 ps
T504 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.104316390072420374319870056094060578487212257400203556131051070749802719512333 Nov 22 02:07:42 PM PST 23 Nov 22 02:38:00 PM PST 23 624328106 ps
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