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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.76 100.00 97.98 99.15 100.00 99.71 99.70 94.75


Total test records in report: 990
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T752 /workspace/coverage/default/41.sram_ctrl_alert_test.74661918891317525212334162876016954846047189935705520235960487574766296359582 Nov 22 02:16:39 PM PST 23 Nov 22 02:16:40 PM PST 23 16600825 ps
T753 /workspace/coverage/default/35.sram_ctrl_max_throughput.98695052462029185844791697845923642856949208639742803639451263909791699547415 Nov 22 02:15:55 PM PST 23 Nov 22 02:17:51 PM PST 23 1342947357 ps
T754 /workspace/coverage/default/16.sram_ctrl_multiple_keys.4072209334563683596464622309052107926450764424893912894437681524368892913688 Nov 22 02:11:41 PM PST 23 Nov 22 02:22:48 PM PST 23 28731174678 ps
T755 /workspace/coverage/default/20.sram_ctrl_partial_access.24733939036341673376904423564052340010247309885288924425919733467043290622495 Nov 22 02:12:33 PM PST 23 Nov 22 02:12:51 PM PST 23 1006378621 ps
T756 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.77784107997666428795848615936079279784413685456999301646550486950038483213968 Nov 22 02:14:51 PM PST 23 Nov 22 02:44:20 PM PST 23 624328106 ps
T757 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.17576526508777412180660126583946173617506772596571048410707033963447109799904 Nov 22 02:16:30 PM PST 23 Nov 22 02:30:30 PM PST 23 13467153934 ps
T758 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.107196578770366991636238925440818077513741074208142730388540771229226644205062 Nov 22 02:16:36 PM PST 23 Nov 22 02:33:31 PM PST 23 13467153934 ps
T759 /workspace/coverage/default/44.sram_ctrl_partial_access.112854553273973187734226024846935513008006300514554102474908929244994645274971 Nov 22 02:16:36 PM PST 23 Nov 22 02:16:56 PM PST 23 1006378621 ps
T760 /workspace/coverage/default/47.sram_ctrl_max_throughput.97464425940267751668362965850674356875411904402131985080545038535454184802607 Nov 22 02:16:56 PM PST 23 Nov 22 02:18:48 PM PST 23 1342947357 ps
T761 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3591757767892938191842997359468518659942778069412005941295332692362298373310 Nov 22 02:12:53 PM PST 23 Nov 22 02:19:59 PM PST 23 9325508496 ps
T762 /workspace/coverage/default/24.sram_ctrl_lc_escalation.38996845127948848087303887649161762893801936993627798631522621580561082990404 Nov 22 02:13:54 PM PST 23 Nov 22 02:15:38 PM PST 23 19084394710 ps
T763 /workspace/coverage/default/0.sram_ctrl_bijection.14236853175365790837420994345329792466505124407444047651439458105105871243319 Nov 22 02:07:05 PM PST 23 Nov 22 02:54:32 PM PST 23 295482808505 ps
T764 /workspace/coverage/default/17.sram_ctrl_alert_test.13990121283724769217268585237326255389368044155316652322125412270061526892823 Nov 22 02:12:16 PM PST 23 Nov 22 02:12:18 PM PST 23 16600825 ps
T765 /workspace/coverage/default/36.sram_ctrl_ram_cfg.110110458426339301985127392722856139925481377290108059811435473177848799851259 Nov 22 02:16:07 PM PST 23 Nov 22 02:16:14 PM PST 23 607542526 ps
T766 /workspace/coverage/default/11.sram_ctrl_multiple_keys.43896697481078286182682952405436287265275354564270390027421694540038451932702 Nov 22 02:07:43 PM PST 23 Nov 22 02:23:18 PM PST 23 28731174678 ps
T767 /workspace/coverage/default/38.sram_ctrl_multiple_keys.45884557439662093237824619866388004235413777549810610529736598853441084750864 Nov 22 02:16:17 PM PST 23 Nov 22 02:28:32 PM PST 23 28731174678 ps
T768 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.71330817175347587547972050601041357848957877098733645360693081818122837250985 Nov 22 02:12:19 PM PST 23 Nov 22 02:19:24 PM PST 23 9325508496 ps
T769 /workspace/coverage/default/1.sram_ctrl_partial_access.15880121183995594582963746141282029343938481337945523626505652259950753403119 Nov 22 02:07:21 PM PST 23 Nov 22 02:07:41 PM PST 23 1006378621 ps
T770 /workspace/coverage/default/15.sram_ctrl_partial_access.16048700891261296252435459057837590215068110745754615072415250479891434602158 Nov 22 02:11:35 PM PST 23 Nov 22 02:11:52 PM PST 23 1006378621 ps
T771 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.43594091765730442106609531782725301297777014612431665819336152544024286154603 Nov 22 02:14:53 PM PST 23 Nov 22 02:16:45 PM PST 23 1371125703 ps
T772 /workspace/coverage/default/31.sram_ctrl_mem_walk.93744793908871203507954898493978743258074630134493650105479826282293283388425 Nov 22 02:14:52 PM PST 23 Nov 22 02:17:36 PM PST 23 18445453393 ps
T773 /workspace/coverage/default/34.sram_ctrl_mem_walk.82956360044676677478772562548159297224761738223293200854960098584361576615231 Nov 22 02:15:33 PM PST 23 Nov 22 02:18:01 PM PST 23 18445453393 ps
T774 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.93278992181250049782501954643462756384936951172277503721829603117386964381698 Nov 22 02:12:59 PM PST 23 Nov 22 02:20:03 PM PST 23 9325508496 ps
T775 /workspace/coverage/default/29.sram_ctrl_ram_cfg.11296484102765231048813376447482452514425092096527598924723746033742671747210 Nov 22 02:14:35 PM PST 23 Nov 22 02:14:42 PM PST 23 607542526 ps
T776 /workspace/coverage/default/15.sram_ctrl_executable.20650826174749108037045927234475721218462542612567838400679320898728145701125 Nov 22 02:11:40 PM PST 23 Nov 22 02:27:03 PM PST 23 31712811539 ps
T777 /workspace/coverage/default/12.sram_ctrl_bijection.38271302603396034366809515719586621176667138255285263420609053421516432641676 Nov 22 02:11:17 PM PST 23 Nov 22 02:57:38 PM PST 23 295482808505 ps
T778 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.67431320223298341844455542114738841637730732613408629402609729609139060651872 Nov 22 02:14:51 PM PST 23 Nov 22 02:24:20 PM PST 23 45083829570 ps
T779 /workspace/coverage/default/2.sram_ctrl_lc_escalation.69051013191969961906681473188025150455950962620643109063331507621151836501673 Nov 22 02:07:06 PM PST 23 Nov 22 02:08:55 PM PST 23 19084394710 ps
T780 /workspace/coverage/default/49.sram_ctrl_max_throughput.18003198491722677836428836853728474060225642734898218081892344038699016926332 Nov 22 02:17:49 PM PST 23 Nov 22 02:19:43 PM PST 23 1342947357 ps
T781 /workspace/coverage/default/26.sram_ctrl_max_throughput.25108693211950500984868047189456142667064276053533111616361686209926538048151 Nov 22 02:13:51 PM PST 23 Nov 22 02:15:56 PM PST 23 1342947357 ps
T782 /workspace/coverage/default/16.sram_ctrl_mem_walk.31826243918918317444858699567817948084849142241227214026586057583307891326899 Nov 22 02:12:18 PM PST 23 Nov 22 02:14:59 PM PST 23 18445453393 ps
T783 /workspace/coverage/default/41.sram_ctrl_ram_cfg.50033937734227916439050514969389958742160617180796022890233361715859292124566 Nov 22 02:16:35 PM PST 23 Nov 22 02:16:41 PM PST 23 607542526 ps
T784 /workspace/coverage/default/41.sram_ctrl_regwen.5489070818668393457906265752680159512661812127531365002948269425257982288955 Nov 22 02:16:31 PM PST 23 Nov 22 02:24:57 PM PST 23 19913691647 ps
T785 /workspace/coverage/default/40.sram_ctrl_multiple_keys.52554916513604576865022613543792651613663550473655947591745842569294463299933 Nov 22 02:16:29 PM PST 23 Nov 22 02:29:36 PM PST 23 28731174678 ps
T786 /workspace/coverage/default/10.sram_ctrl_bijection.112540147403982170934804616840696440180986479954051139037849140966550252515330 Nov 22 02:07:39 PM PST 23 Nov 22 02:53:43 PM PST 23 295482808505 ps
T787 /workspace/coverage/default/33.sram_ctrl_max_throughput.51662373707233623303289145674123344167474375507606678709771123168836075396896 Nov 22 02:15:39 PM PST 23 Nov 22 02:17:43 PM PST 23 1342947357 ps
T788 /workspace/coverage/default/17.sram_ctrl_max_throughput.37280575077858540754785626237040137076901344162405532937559629904797056759071 Nov 22 02:12:18 PM PST 23 Nov 22 02:14:25 PM PST 23 1342947357 ps
T789 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.82196554509378104856162792360530432840324419977751300044328031162210558545865 Nov 22 02:12:35 PM PST 23 Nov 22 02:28:45 PM PST 23 13467153934 ps
T790 /workspace/coverage/default/9.sram_ctrl_partial_access.92883366273055736551786963827548085496065485475613441385851584863629509636727 Nov 22 02:07:43 PM PST 23 Nov 22 02:08:03 PM PST 23 1006378621 ps
T791 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3381712537472595842095161957008492340346944109855315742166551121666800378702 Nov 22 02:16:11 PM PST 23 Nov 22 02:25:28 PM PST 23 45083829570 ps
T792 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.44600697952367689978462185657674990985130999417142434274431303891750948476864 Nov 22 02:15:34 PM PST 23 Nov 22 02:24:52 PM PST 23 45083829570 ps
T793 /workspace/coverage/default/44.sram_ctrl_lc_escalation.72392220264116461258506030909398013869573392271264975777628661044586530164451 Nov 22 02:16:38 PM PST 23 Nov 22 02:18:21 PM PST 23 19084394710 ps
T794 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.85897369651807382915839856006983293793657440980109803057375067056055461825160 Nov 22 02:15:23 PM PST 23 Nov 22 02:24:55 PM PST 23 45083829570 ps
T795 /workspace/coverage/default/3.sram_ctrl_multiple_keys.99669523554986995117448522075482120764967762871405571944774127915081926985734 Nov 22 02:07:06 PM PST 23 Nov 22 02:21:35 PM PST 23 28731174678 ps
T796 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.27426022085729766674751374854834151155836438771779133591600830096275855047108 Nov 22 02:13:43 PM PST 23 Nov 22 02:20:48 PM PST 23 9325508496 ps
T797 /workspace/coverage/default/40.sram_ctrl_lc_escalation.11148056542127265053661292916756651358526812686661409996596598200949057092081 Nov 22 02:16:16 PM PST 23 Nov 22 02:18:01 PM PST 23 19084394710 ps
T798 /workspace/coverage/default/17.sram_ctrl_ram_cfg.46602710155964998096919208353445166801773245713700857631193161957935563975876 Nov 22 02:12:18 PM PST 23 Nov 22 02:12:26 PM PST 23 607542526 ps
T799 /workspace/coverage/default/27.sram_ctrl_partial_access.1658576409713877934228031121432536503320478115628595325358155453050594001116 Nov 22 02:13:58 PM PST 23 Nov 22 02:14:18 PM PST 23 1006378621 ps
T800 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.41496296697418645612784144497048992759255604460784192875409062463024428142946 Nov 22 02:12:35 PM PST 23 Nov 22 02:14:35 PM PST 23 1371125703 ps
T801 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.114346420042087711565982589589701360225720307282038237338541685755385717936792 Nov 22 02:16:10 PM PST 23 Nov 22 02:33:29 PM PST 23 13467153934 ps
T802 /workspace/coverage/default/32.sram_ctrl_max_throughput.107986098538850129210215130414889583541783908598984924564055420364166540153304 Nov 22 02:15:28 PM PST 23 Nov 22 02:17:28 PM PST 23 1342947357 ps
T803 /workspace/coverage/default/29.sram_ctrl_max_throughput.95077339745519363042735836995226232741678684188974952554686985688323573843629 Nov 22 02:14:41 PM PST 23 Nov 22 02:16:41 PM PST 23 1342947357 ps
T804 /workspace/coverage/default/8.sram_ctrl_mem_walk.73905393019677193319027534263085933463403242322548875865214509110332891680581 Nov 22 02:07:41 PM PST 23 Nov 22 02:10:17 PM PST 23 18445453393 ps
T805 /workspace/coverage/default/5.sram_ctrl_bijection.20557991652474699150635211045452630704752669606939458118117546001053797623174 Nov 22 02:07:38 PM PST 23 Nov 22 02:53:38 PM PST 23 295482808505 ps
T806 /workspace/coverage/default/39.sram_ctrl_bijection.32968259489382438196346535577488404782488573182385831785699700767027199877499 Nov 22 02:16:30 PM PST 23 Nov 22 03:03:18 PM PST 23 295482808505 ps
T807 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.66854663679532477894743093357594428564817598992256046596781194500252828030532 Nov 22 02:16:35 PM PST 23 Nov 22 02:50:58 PM PST 23 624328106 ps
T808 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.110040884733603922689838384802443488492934970032287782646750352484944106176295 Nov 22 02:14:16 PM PST 23 Nov 22 02:21:23 PM PST 23 9325508496 ps
T809 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.89728300076405509086103304650787430289103988395382791923738748133961561031259 Nov 22 02:16:08 PM PST 23 Nov 22 02:18:19 PM PST 23 1371125703 ps
T810 /workspace/coverage/default/35.sram_ctrl_alert_test.17068106108228267560780613832307307576179674580007919372235563676624204714960 Nov 22 02:15:54 PM PST 23 Nov 22 02:15:55 PM PST 23 16600825 ps
T811 /workspace/coverage/default/16.sram_ctrl_ram_cfg.30890972788301477744110947229308241774180662613203488874551056783734336486799 Nov 22 02:12:12 PM PST 23 Nov 22 02:12:22 PM PST 23 607542526 ps
T812 /workspace/coverage/default/45.sram_ctrl_mem_walk.60712173949020285879648534426662503152958863028646769795404168457320327012117 Nov 22 02:16:44 PM PST 23 Nov 22 02:19:23 PM PST 23 18445453393 ps
T813 /workspace/coverage/default/26.sram_ctrl_partial_access.10921809800050932710144433032066066416644024550310773592664632854836618626898 Nov 22 02:13:55 PM PST 23 Nov 22 02:14:14 PM PST 23 1006378621 ps
T814 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.24376610032743614085397632241187073902554870023675338350333929442903361125539 Nov 22 02:11:35 PM PST 23 Nov 22 02:18:49 PM PST 23 9325508496 ps
T815 /workspace/coverage/default/48.sram_ctrl_mem_walk.28044681112341300684347415165322074731020726563321117763875162249260318271248 Nov 22 02:17:16 PM PST 23 Nov 22 02:19:56 PM PST 23 18445453393 ps
T816 /workspace/coverage/default/36.sram_ctrl_mem_walk.74970769801280865540686380466535004765713244638392025304268644361009238207558 Nov 22 02:15:34 PM PST 23 Nov 22 02:18:10 PM PST 23 18445453393 ps
T817 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.31342624169660234699404031988278376526797938287381949410500125641462656151324 Nov 22 02:11:28 PM PST 23 Nov 22 02:48:36 PM PST 23 624328106 ps
T818 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.40392266418090842235842311942105770636337364928449250026328923066919100074002 Nov 22 02:07:38 PM PST 23 Nov 22 02:09:24 PM PST 23 1371125703 ps
T819 /workspace/coverage/default/21.sram_ctrl_mem_walk.6151432524917473670957831809249674551659515830610337373335634251756157139605 Nov 22 02:12:58 PM PST 23 Nov 22 02:15:42 PM PST 23 18445453393 ps
T820 /workspace/coverage/default/20.sram_ctrl_mem_walk.42346466323676235252446395125191902899281353333970629061511913990276394426708 Nov 22 02:12:50 PM PST 23 Nov 22 02:15:29 PM PST 23 18445453393 ps
T821 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.46367048847650477155887575591136320492647244408526273689233148848320445695698 Nov 22 02:16:31 PM PST 23 Nov 22 02:26:17 PM PST 23 45083829570 ps
T822 /workspace/coverage/default/13.sram_ctrl_bijection.105850257911630294257978996856118816467388809929004131464673923308190818501448 Nov 22 02:11:20 PM PST 23 Nov 22 02:57:52 PM PST 23 295482808505 ps
T823 /workspace/coverage/default/16.sram_ctrl_smoke.7034390366851252515846920555921541684089257975633460438752017633189000699414 Nov 22 02:11:40 PM PST 23 Nov 22 02:11:59 PM PST 23 988289480 ps
T824 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.4160904248690155320319594872148471905637860784053621870117286229513688189543 Nov 22 02:07:39 PM PST 23 Nov 22 02:09:00 PM PST 23 4750777237 ps
T825 /workspace/coverage/default/25.sram_ctrl_partial_access.131998598740320006165766882993740871803682390575337490236361048014685742755 Nov 22 02:13:50 PM PST 23 Nov 22 02:14:10 PM PST 23 1006378621 ps
T826 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.44506422316821263836915088221686559677792474173270636767155308586198527632067 Nov 22 02:14:57 PM PST 23 Nov 22 02:17:05 PM PST 23 1371125703 ps
T827 /workspace/coverage/default/12.sram_ctrl_mem_walk.28995607836990060929882415920185932759342231074593301268868015625814081997186 Nov 22 02:11:18 PM PST 23 Nov 22 02:14:01 PM PST 23 18445453393 ps
T828 /workspace/coverage/default/31.sram_ctrl_partial_access.81289480902161927610039447347778641600756178511290723803638816377387305561678 Nov 22 02:14:52 PM PST 23 Nov 22 02:15:14 PM PST 23 1006378621 ps
T829 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.106681548153619422267918595478159181602815068447625709651404535389973404531158 Nov 22 02:07:33 PM PST 23 Nov 22 02:09:45 PM PST 23 1371125703 ps
T830 /workspace/coverage/default/28.sram_ctrl_lc_escalation.58745901258272105434505511935918947060969362343087706512222051339355486497249 Nov 22 02:14:14 PM PST 23 Nov 22 02:16:00 PM PST 23 19084394710 ps
T831 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.16921806083075200949920920101092736987679304229285350430219786279608109341899 Nov 22 02:15:32 PM PST 23 Nov 22 02:22:35 PM PST 23 9325508496 ps
T832 /workspace/coverage/default/14.sram_ctrl_mem_walk.85594607609585756532817463135867865698206937735636466325099038280413098099189 Nov 22 02:11:26 PM PST 23 Nov 22 02:14:12 PM PST 23 18445453393 ps
T833 /workspace/coverage/default/15.sram_ctrl_max_throughput.91815639230652012147950171340733554280345364917193907975442893243623729249744 Nov 22 02:11:36 PM PST 23 Nov 22 02:13:40 PM PST 23 1342947357 ps
T834 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.58070683195160400829391589217265215483910686162472156596691381508730226854262 Nov 22 02:16:38 PM PST 23 Nov 22 02:25:56 PM PST 23 45083829570 ps
T835 /workspace/coverage/default/7.sram_ctrl_partial_access.107726063779450903645603128660894891532453477091858776619378002812487360624737 Nov 22 02:07:38 PM PST 23 Nov 22 02:07:58 PM PST 23 1006378621 ps
T836 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.27940177714923765773462253616283750550672891140669482405107896666917773910000 Nov 22 02:12:22 PM PST 23 Nov 22 02:43:41 PM PST 23 624328106 ps
T837 /workspace/coverage/default/16.sram_ctrl_max_throughput.55992064750154653665120466959305300640433697205298613339654475924268378929630 Nov 22 02:12:02 PM PST 23 Nov 22 02:14:10 PM PST 23 1342947357 ps
T838 /workspace/coverage/default/44.sram_ctrl_smoke.43275286209630884567179477552151673080133975674667090992499407887445394585952 Nov 22 02:16:33 PM PST 23 Nov 22 02:16:52 PM PST 23 988289480 ps
T839 /workspace/coverage/default/11.sram_ctrl_alert_test.32640424409486980645006551611462358898402607264205560081660824745544184028014 Nov 22 02:11:17 PM PST 23 Nov 22 02:11:18 PM PST 23 16600825 ps
T840 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.40830703600054094219408329203665638302601342865174264531737469682359788575008 Nov 22 02:14:53 PM PST 23 Nov 22 02:22:09 PM PST 23 9325508496 ps
T841 /workspace/coverage/default/13.sram_ctrl_lc_escalation.959393740518167349986682417246064638396913996905356991609730491421872786966 Nov 22 02:11:19 PM PST 23 Nov 22 02:13:05 PM PST 23 19084394710 ps
T842 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.90981264123470559164011072456608307314117931913063698010278467525939192418980 Nov 22 02:16:16 PM PST 23 Nov 22 02:23:28 PM PST 23 9325508496 ps
T843 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.14916066366019188013817332907561445929843487301293462894922154340215793481789 Nov 22 02:13:00 PM PST 23 Nov 22 02:22:49 PM PST 23 45083829570 ps
T844 /workspace/coverage/default/15.sram_ctrl_smoke.5970118569503750734989565291200028956737500039084475091797460788887291736156 Nov 22 02:11:39 PM PST 23 Nov 22 02:11:58 PM PST 23 988289480 ps
T845 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.11661294588224036361485674111255930206305700129767227834240081854120279801144 Nov 22 02:15:35 PM PST 23 Nov 22 02:32:07 PM PST 23 13467153934 ps
T846 /workspace/coverage/default/36.sram_ctrl_regwen.62307982455950884751365872066666041332797691274169856575080274753699546199842 Nov 22 02:15:57 PM PST 23 Nov 22 02:26:10 PM PST 23 19913691647 ps
T847 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.14743301300654775287851155011431637967381987683963806015961233918616580609137 Nov 22 02:07:22 PM PST 23 Nov 22 02:14:24 PM PST 23 9325508496 ps
T848 /workspace/coverage/default/30.sram_ctrl_mem_walk.36360675248386450314163217619154966275625980660602274364181812928835135194183 Nov 22 02:14:55 PM PST 23 Nov 22 02:17:33 PM PST 23 18445453393 ps
T849 /workspace/coverage/default/0.sram_ctrl_partial_access.99575018609465906086995141259168136387291956090829967925219877066169849432490 Nov 22 02:07:05 PM PST 23 Nov 22 02:07:30 PM PST 23 1006378621 ps
T850 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.87761745542554751633026825000407639025471115134034321801125934345089610718233 Nov 22 02:12:01 PM PST 23 Nov 22 02:19:11 PM PST 23 9325508496 ps
T851 /workspace/coverage/default/22.sram_ctrl_smoke.62860671088627549536922132272296249565458883443062697827328165403107262861026 Nov 22 02:12:59 PM PST 23 Nov 22 02:13:16 PM PST 23 988289480 ps
T852 /workspace/coverage/default/47.sram_ctrl_ram_cfg.97762740373290348467905550490106329625789706590870675206561151010909785917051 Nov 22 02:17:09 PM PST 23 Nov 22 02:17:19 PM PST 23 607542526 ps
T853 /workspace/coverage/default/18.sram_ctrl_regwen.95898024780089884580471214435519298684337878572840213677441478996510904841059 Nov 22 02:12:35 PM PST 23 Nov 22 02:22:07 PM PST 23 19913691647 ps
T854 /workspace/coverage/default/12.sram_ctrl_ram_cfg.20677156860764593241515162828403708772549167171071784448811513240977509705819 Nov 22 02:11:19 PM PST 23 Nov 22 02:11:26 PM PST 23 607542526 ps
T855 /workspace/coverage/default/26.sram_ctrl_mem_walk.32612139772642488741598567946352540368182443053041850634039526652087108386671 Nov 22 02:13:53 PM PST 23 Nov 22 02:16:34 PM PST 23 18445453393 ps
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T857 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.16703936748779888319512421074963763645227585013470315227134503395099491157703 Nov 22 02:13:36 PM PST 23 Nov 22 02:20:40 PM PST 23 9325508496 ps
T858 /workspace/coverage/default/21.sram_ctrl_bijection.46352732074536492390406864795074519939749554109025799605002587390601713520292 Nov 22 02:12:58 PM PST 23 Nov 22 02:58:20 PM PST 23 295482808505 ps
T859 /workspace/coverage/default/35.sram_ctrl_mem_walk.37076414356729749279693114167688840226111712453936597819977196094096802185535 Nov 22 02:15:35 PM PST 23 Nov 22 02:18:11 PM PST 23 18445453393 ps
T860 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2857311998563646903301929970316430515443928033074045545387733516550099513960 Nov 22 02:07:36 PM PST 23 Nov 22 02:14:37 PM PST 23 9325508496 ps
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T862 /workspace/coverage/default/46.sram_ctrl_mem_walk.105394243876632214032652293376253321025963192931630367845188387757800613633907 Nov 22 02:16:52 PM PST 23 Nov 22 02:19:30 PM PST 23 18445453393 ps
T863 /workspace/coverage/default/39.sram_ctrl_partial_access.5412085516736960284211680810206859439661726142591168226545514999150128919261 Nov 22 02:16:29 PM PST 23 Nov 22 02:16:50 PM PST 23 1006378621 ps
T864 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.13872810442066626594212591781701397331070361701468308617688617259816032208364 Nov 22 02:07:21 PM PST 23 Nov 22 02:09:17 PM PST 23 1371125703 ps
T865 /workspace/coverage/default/28.sram_ctrl_executable.24850411772512343546780149649407070098601955816738127979618165647025442118519 Nov 22 02:14:12 PM PST 23 Nov 22 02:28:47 PM PST 23 31712811539 ps
T866 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.76394143259891863188544599407180068362641105178892201617539781165286417766697 Nov 22 02:16:37 PM PST 23 Nov 22 02:44:25 PM PST 23 624328106 ps
T867 /workspace/coverage/default/8.sram_ctrl_multiple_keys.49437811064726166490889540056226098020410136422037098325286746641435106737580 Nov 22 02:07:41 PM PST 23 Nov 22 02:21:58 PM PST 23 28731174678 ps
T868 /workspace/coverage/default/42.sram_ctrl_regwen.137730516076642370989709231641699550276875186435603475818428795252839687746 Nov 22 02:16:18 PM PST 23 Nov 22 02:26:13 PM PST 23 19913691647 ps
T869 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.9860163381422896432748056959347849865992449636858510788991077708701263614674 Nov 22 02:13:16 PM PST 23 Nov 22 02:30:50 PM PST 23 13467153934 ps
T870 /workspace/coverage/default/30.sram_ctrl_regwen.11393104290923828500565518653076225524679638738105050520528101998018421481604 Nov 22 02:14:42 PM PST 23 Nov 22 02:24:34 PM PST 23 19913691647 ps
T871 /workspace/coverage/default/3.sram_ctrl_smoke.114674890991487967912451468788510589419951411567045988502046987372033308184523 Nov 22 02:07:20 PM PST 23 Nov 22 02:07:37 PM PST 23 988289480 ps
T872 /workspace/coverage/default/36.sram_ctrl_bijection.105193094535483714844872544281207657801972482491276796861712101581580915129980 Nov 22 02:15:41 PM PST 23 Nov 22 03:00:51 PM PST 23 295482808505 ps
T873 /workspace/coverage/default/12.sram_ctrl_executable.83015794451167867588709093090640235422253462632805005603733453815401402350110 Nov 22 02:11:16 PM PST 23 Nov 22 02:27:04 PM PST 23 31712811539 ps
T874 /workspace/coverage/default/37.sram_ctrl_alert_test.75657295621288676170368420425066570151633563959994716994329173050897508578492 Nov 22 02:16:27 PM PST 23 Nov 22 02:16:28 PM PST 23 16600825 ps
T875 /workspace/coverage/default/0.sram_ctrl_executable.50053472331875680528654747997343673619588764459331200674534996910204644310432 Nov 22 02:07:20 PM PST 23 Nov 22 02:23:58 PM PST 23 31712811539 ps
T876 /workspace/coverage/default/17.sram_ctrl_mem_walk.76326916799107143752950485615326585779023859998417687166576948291386248157522 Nov 22 02:12:22 PM PST 23 Nov 22 02:15:02 PM PST 23 18445453393 ps
T877 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.38711735526398738190532800360396338930063547184392042502234130036187585646520 Nov 22 02:07:00 PM PST 23 Nov 22 02:09:14 PM PST 23 1371125703 ps
T878 /workspace/coverage/default/0.sram_ctrl_mem_walk.12866653507669721460422948692204691748231331895054698292526095045144583380998 Nov 22 02:07:06 PM PST 23 Nov 22 02:09:55 PM PST 23 18445453393 ps
T879 /workspace/coverage/default/42.sram_ctrl_smoke.93935149631149575777560804004870117365124250252141642798027529481334177391558 Nov 22 02:16:36 PM PST 23 Nov 22 02:16:56 PM PST 23 988289480 ps
T880 /workspace/coverage/default/49.sram_ctrl_mem_walk.115603393235978463129376258675199154966027194181021762610970725077124888050216 Nov 22 02:17:16 PM PST 23 Nov 22 02:19:53 PM PST 23 18445453393 ps
T881 /workspace/coverage/default/43.sram_ctrl_smoke.13302040049934794721027685970819328572359480040380452372558963580493798528481 Nov 22 02:16:35 PM PST 23 Nov 22 02:16:53 PM PST 23 988289480 ps
T882 /workspace/coverage/default/4.sram_ctrl_smoke.70167178323678993264300057179126396012806735295723911889731673079760023308258 Nov 22 02:07:19 PM PST 23 Nov 22 02:07:38 PM PST 23 988289480 ps
T883 /workspace/coverage/default/32.sram_ctrl_bijection.44134302814279234166247017610546299953564527264094679088336185547175794702009 Nov 22 02:14:55 PM PST 23 Nov 22 03:01:00 PM PST 23 295482808505 ps
T884 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.87430746624652618413618686872392113758268047647713434473722313089823856060468 Nov 22 02:12:18 PM PST 23 Nov 22 02:21:49 PM PST 23 45083829570 ps
T885 /workspace/coverage/default/19.sram_ctrl_partial_access.21363015002366665488548835327163984877523572827228080012255774466644912086327 Nov 22 02:12:34 PM PST 23 Nov 22 02:12:53 PM PST 23 1006378621 ps
T886 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3000614722796924193446635959145080751015434392657237206061148384460777560886 Nov 22 02:15:28 PM PST 23 Nov 22 02:16:51 PM PST 23 4750777237 ps
T887 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.90229773131214919519151734546960748577914425113672080577070120142450876624513 Nov 22 02:15:41 PM PST 23 Nov 22 02:25:15 PM PST 23 45083829570 ps
T888 /workspace/coverage/default/31.sram_ctrl_multiple_keys.27503611860069054293328027736221983896079219017867057479404630527983799225889 Nov 22 02:14:42 PM PST 23 Nov 22 02:29:17 PM PST 23 28731174678 ps
T889 /workspace/coverage/default/16.sram_ctrl_alert_test.78350143842123360629745927342865214679894090770309127471568400128495881052819 Nov 22 02:12:17 PM PST 23 Nov 22 02:12:18 PM PST 23 16600825 ps
T890 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.37128604054060234527272023560162887930239199248298782394744319878435396028268 Nov 22 02:12:18 PM PST 23 Nov 22 02:14:27 PM PST 23 1371125703 ps
T891 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.45536119367762557210849307372321160607238676808056940760740762619865276749404 Nov 22 02:07:23 PM PST 23 Nov 22 02:08:40 PM PST 23 4750777237 ps
T892 /workspace/coverage/default/11.sram_ctrl_executable.91762344062453192387735312909807169704666147256268900994048456910235711475092 Nov 22 02:11:15 PM PST 23 Nov 22 02:25:09 PM PST 23 31712811539 ps
T893 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.17982143772372522531366313357905710595984910717468664544798084772172851328638 Nov 22 02:14:25 PM PST 23 Nov 22 02:16:11 PM PST 23 1371125703 ps
T894 /workspace/coverage/default/33.sram_ctrl_partial_access.103593411459995085873075130715414254372656234698681892386816909506372437598109 Nov 22 02:15:30 PM PST 23 Nov 22 02:15:48 PM PST 23 1006378621 ps
T895 /workspace/coverage/default/41.sram_ctrl_max_throughput.115236525092740361979088392488218156599720202435683570905982193951658598250016 Nov 22 02:16:50 PM PST 23 Nov 22 02:18:48 PM PST 23 1342947357 ps
T896 /workspace/coverage/default/27.sram_ctrl_max_throughput.111646539978171940174325245772602202607362092792568388919896422221463369468715 Nov 22 02:13:58 PM PST 23 Nov 22 02:16:03 PM PST 23 1342947357 ps
T897 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.101839037033852991836323107550827636477578546387657123968238975694769135242297 Nov 22 02:12:18 PM PST 23 Nov 22 02:22:02 PM PST 23 45083829570 ps
T898 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.10357539733983662590471830319031583037332584577758030130387331362622119072025 Nov 22 02:16:30 PM PST 23 Nov 22 02:31:19 PM PST 23 13467153934 ps
T899 /workspace/coverage/default/11.sram_ctrl_max_throughput.47278336623854218803103932032245833077827419352509502963244915226424927636641 Nov 22 02:07:41 PM PST 23 Nov 22 02:09:46 PM PST 23 1342947357 ps
T900 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.40024797387935235223021140138397670723697742919450088490983982907599114694681 Nov 22 02:07:38 PM PST 23 Nov 22 02:39:50 PM PST 23 624328106 ps
T901 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.32795828260602876389556450352809108622514676417419864044535192387655567620038 Nov 22 02:15:32 PM PST 23 Nov 22 02:25:07 PM PST 23 45083829570 ps
T902 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.46448542111123012523554749767215596187416991673085447059586058117769436811531 Nov 22 02:14:11 PM PST 23 Nov 22 02:15:32 PM PST 23 4750777237 ps
T903 /workspace/coverage/default/36.sram_ctrl_max_throughput.19110897249859128951060721289567038327922173806498756309187778578650545687047 Nov 22 02:15:57 PM PST 23 Nov 22 02:18:07 PM PST 23 1342947357 ps
T904 /workspace/coverage/default/28.sram_ctrl_alert_test.97614114071954600221686701157841540554439682623616371082011414814663327927963 Nov 22 02:14:14 PM PST 23 Nov 22 02:14:16 PM PST 23 16600825 ps
T905 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2844877470588187446826195650948634644537087236657359783773763851723142929450 Nov 22 02:11:19 PM PST 23 Nov 22 02:29:19 PM PST 23 13467153934 ps
T906 /workspace/coverage/default/0.sram_ctrl_lc_escalation.14316558283802171417493146248402980722688950856079795747261678811767122688992 Nov 22 02:07:11 PM PST 23 Nov 22 02:08:58 PM PST 23 19084394710 ps
T907 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.52122101929598311338855182533226757461958519624688932938978663903749951015361 Nov 22 02:15:39 PM PST 23 Nov 22 02:48:41 PM PST 23 624328106 ps
T908 /workspace/coverage/default/9.sram_ctrl_bijection.106162974465322553943267040471880687709510015802976279838745609335064059623706 Nov 22 02:07:41 PM PST 23 Nov 22 02:52:05 PM PST 23 295482808505 ps
T909 /workspace/coverage/default/39.sram_ctrl_alert_test.20553349979514760296853788944258794058438211014435538841053446829063562528476 Nov 22 02:16:36 PM PST 23 Nov 22 02:16:37 PM PST 23 16600825 ps
T910 /workspace/coverage/default/3.sram_ctrl_alert_test.73477378402306336466987833033244630051700527794113511260666068466194689288228 Nov 22 02:07:22 PM PST 23 Nov 22 02:07:23 PM PST 23 16600825 ps
T911 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.109823630389452689175761857477618364572170425174809755981973149286528447492145 Nov 22 02:12:33 PM PST 23 Nov 22 02:21:56 PM PST 23 45083829570 ps
T912 /workspace/coverage/default/44.sram_ctrl_ram_cfg.100830790360376088529903978790832541392689458078075258287335173612117600622262 Nov 22 02:16:35 PM PST 23 Nov 22 02:16:41 PM PST 23 607542526 ps
T913 /workspace/coverage/default/41.sram_ctrl_partial_access.59716614613485936166952464457906400211785858228314758102861286149652012715452 Nov 22 02:16:39 PM PST 23 Nov 22 02:16:58 PM PST 23 1006378621 ps
T914 /workspace/coverage/default/47.sram_ctrl_smoke.78973204064977986635302584271311953285112101963451396102922803140560962281627 Nov 22 02:16:50 PM PST 23 Nov 22 02:17:10 PM PST 23 988289480 ps
T915 /workspace/coverage/default/46.sram_ctrl_max_throughput.92276119218079078362731226048003704234020400553813572841563246669535427783833 Nov 22 02:17:01 PM PST 23 Nov 22 02:19:21 PM PST 23 1342947357 ps
T916 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.24785348461995533982232216723814428534869183869405182300200134469778579203735 Nov 22 02:14:53 PM PST 23 Nov 22 02:24:46 PM PST 23 45083829570 ps
T917 /workspace/coverage/default/41.sram_ctrl_mem_walk.33557788446502920470996585444194899035678574748786547592716882803061781666281 Nov 22 02:16:40 PM PST 23 Nov 22 02:19:15 PM PST 23 18445453393 ps
T918 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.78722191229875160389667114212923345369392557976448968842026365822040484678724 Nov 22 02:14:52 PM PST 23 Nov 22 02:43:21 PM PST 23 624328106 ps
T919 /workspace/coverage/default/8.sram_ctrl_lc_escalation.49718127222531008794938160482443964698618156651165122610686419527224577096688 Nov 22 02:07:40 PM PST 23 Nov 22 02:09:27 PM PST 23 19084394710 ps
T920 /workspace/coverage/default/24.sram_ctrl_partial_access.76435445624249256566200485885414182411273931763989745273586104681313418928545 Nov 22 02:13:51 PM PST 23 Nov 22 02:14:12 PM PST 23 1006378621 ps
T921 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.62967935467795987627563882198739943309563920612721214100067941087531163592301 Nov 22 02:14:30 PM PST 23 Nov 22 02:15:52 PM PST 23 4750777237 ps
T922 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.53872919051169979555544128322588059914047669539856133800387765102889773219500 Nov 22 02:15:27 PM PST 23 Nov 22 02:22:36 PM PST 23 9325508496 ps
T923 /workspace/coverage/default/41.sram_ctrl_executable.9207852291945114986506082862439692220643467444837742436176791899823091349533 Nov 22 02:16:29 PM PST 23 Nov 22 02:30:13 PM PST 23 31712811539 ps
T924 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.76064151858763415194269462099956007007217681226291767583508507880981933655198 Nov 22 02:14:54 PM PST 23 Nov 22 02:24:36 PM PST 23 45083829570 ps
T925 /workspace/coverage/default/24.sram_ctrl_executable.3099644964393052079182846923050628032584283630858998756114176262210296772476 Nov 22 02:13:44 PM PST 23 Nov 22 02:26:38 PM PST 23 31712811539 ps
T926 /workspace/coverage/default/25.sram_ctrl_executable.59360450927184922350318137319970383978422944506573837226970694775579872379886 Nov 22 02:13:54 PM PST 23 Nov 22 02:27:35 PM PST 23 31712811539 ps
T927 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.98407341398966671863374533412619110409604878517931381949257732086084829268211 Nov 22 02:13:21 PM PST 23 Nov 22 02:46:07 PM PST 23 624328106 ps
T928 /workspace/coverage/default/28.sram_ctrl_bijection.92689978700679257941619839138590611267192047765859015416645152136972671156154 Nov 22 02:14:14 PM PST 23 Nov 22 02:59:32 PM PST 23 295482808505 ps
T929 /workspace/coverage/default/0.sram_ctrl_ram_cfg.69449508693335185162731949899036543490901198779082267224880417653392503992909 Nov 22 02:07:19 PM PST 23 Nov 22 02:07:26 PM PST 23 607542526 ps
T930 /workspace/coverage/default/15.sram_ctrl_bijection.112741635325622324396781206335183698697059929475066152909083205781327638719505 Nov 22 02:11:36 PM PST 23 Nov 22 02:57:17 PM PST 23 295482808505 ps
T931 /workspace/coverage/default/21.sram_ctrl_executable.52060595081352575001880108066294764577471840817677277488188545252546621906701 Nov 22 02:12:53 PM PST 23 Nov 22 02:31:06 PM PST 23 31712811539 ps
T932 /workspace/coverage/default/6.sram_ctrl_alert_test.5616802863889510673594583480712683351768576954011780755040991659145609068462 Nov 22 02:07:24 PM PST 23 Nov 22 02:07:26 PM PST 23 16600825 ps
T933 /workspace/coverage/default/5.sram_ctrl_lc_escalation.84571802172034863713122680112928596206633416699385322828348310498328367903310 Nov 22 02:07:36 PM PST 23 Nov 22 02:09:25 PM PST 23 19084394710 ps
T934 /workspace/coverage/default/43.sram_ctrl_executable.90172692597022359026582731206386559224002438225512207214059509126037627385936 Nov 22 02:16:35 PM PST 23 Nov 22 02:29:53 PM PST 23 31712811539 ps
T935 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.19741918599664555346456677627625719332733560211347364106625299561610682779506 Nov 22 02:07:07 PM PST 23 Nov 22 02:38:20 PM PST 23 624328106 ps
T936 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.36633260171279416796328785820136983818319372945882724550152639396999420141038 Nov 22 02:07:22 PM PST 23 Nov 22 02:23:53 PM PST 23 13467153934 ps
T937 /workspace/coverage/default/49.sram_ctrl_partial_access.75843620366666554589457024463829575509106801391863781296313324614097004348257 Nov 22 02:17:33 PM PST 23 Nov 22 02:17:53 PM PST 23 1006378621 ps
T938 /workspace/coverage/default/2.sram_ctrl_bijection.57860237628164388481965034091881555330737147120078002151234615207755058516277 Nov 22 02:07:18 PM PST 23 Nov 22 02:52:50 PM PST 23 295482808505 ps
T939 /workspace/coverage/default/34.sram_ctrl_alert_test.52201084803120919030452148415274154848040250622734140865097414797572686676889 Nov 22 02:15:30 PM PST 23 Nov 22 02:15:31 PM PST 23 16600825 ps
T940 /workspace/coverage/default/44.sram_ctrl_bijection.96007243982652836601371269325025900220413773965827005160526220948828816719636 Nov 22 02:16:35 PM PST 23 Nov 22 03:01:33 PM PST 23 295482808505 ps
T941 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.40294297540232927778334388078720640898489170566465282225649163523485045188870 Nov 22 02:07:38 PM PST 23 Nov 22 02:14:52 PM PST 23 9325508496 ps
T942 /workspace/coverage/default/6.sram_ctrl_smoke.85897682959419541130346706608501654673341479460401171833431376666351335264765 Nov 22 02:07:37 PM PST 23 Nov 22 02:07:56 PM PST 23 988289480 ps
T943 /workspace/coverage/default/32.sram_ctrl_lc_escalation.93608229287002883160653796762218367396719347125459635292596903712907594856189 Nov 22 02:15:12 PM PST 23 Nov 22 02:16:56 PM PST 23 19084394710 ps
T37 /workspace/coverage/default/3.sram_ctrl_sec_cm.11649788384939314101327735162523106162731914603074395343856964757601650411147 Nov 22 02:07:20 PM PST 23 Nov 22 02:07:24 PM PST 23 216402798 ps
T944 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.18983872577140397262285234310276238180882536759025680447600814477702019495658 Nov 22 02:13:51 PM PST 23 Nov 22 02:15:07 PM PST 23 4750777237 ps
T945 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.57626811586187221322169999392960958158109599636693584295757640925692214697935 Nov 22 02:07:20 PM PST 23 Nov 22 02:35:59 PM PST 23 624328106 ps
T946 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.7286873354261973957700977128628170788988790113325547176992209083850305566571 Nov 22 02:14:59 PM PST 23 Nov 22 02:50:29 PM PST 23 624328106 ps
T947 /workspace/coverage/default/35.sram_ctrl_smoke.50813585665712812478427933478573113592211039927563619584700856510374705780840 Nov 22 02:15:33 PM PST 23 Nov 22 02:15:50 PM PST 23 988289480 ps
T948 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.89375234650950147384113434632117571164702383324817190552060838041804308765081 Nov 22 02:16:17 PM PST 23 Nov 22 02:17:56 PM PST 23 1371125703 ps
T949 /workspace/coverage/default/12.sram_ctrl_max_throughput.43597377986235563365978746760352656878702233502104176505929010581465922619105 Nov 22 02:11:16 PM PST 23 Nov 22 02:13:20 PM PST 23 1342947357 ps
T950 /workspace/coverage/default/46.sram_ctrl_smoke.104804472716365616289650838809990992570863649214669135223777508578479119023977 Nov 22 02:16:44 PM PST 23 Nov 22 02:17:01 PM PST 23 988289480 ps
T951 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.47678856833653359498732535770501306142473020443053053212480940665037394205781 Nov 22 02:12:35 PM PST 23 Nov 22 02:22:05 PM PST 23 45083829570 ps
T952 /workspace/coverage/default/7.sram_ctrl_mem_walk.67843821570140716484230787818925369540354935821849187812431876746542162853995 Nov 22 02:07:36 PM PST 23 Nov 22 02:10:16 PM PST 23 18445453393 ps
T953 /workspace/coverage/default/42.sram_ctrl_multiple_keys.23309389073774053300987657847071660297473896051058607948442378967399969863687 Nov 22 02:16:32 PM PST 23 Nov 22 02:27:25 PM PST 23 28731174678 ps
T954 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.35833620963117231667787188645963267319686189090017733101146468112930405175755 Nov 22 02:07:24 PM PST 23 Nov 22 02:08:45 PM PST 23 4750777237 ps
T955 /workspace/coverage/default/6.sram_ctrl_partial_access.10255021083601663162926901658845296391188374288493341690300566477421138298713 Nov 22 02:07:35 PM PST 23 Nov 22 02:07:55 PM PST 23 1006378621 ps
T956 /workspace/coverage/default/42.sram_ctrl_executable.98527383043194447457253207251360695343688393240048080022996785513721515537416 Nov 22 02:16:39 PM PST 23 Nov 22 02:30:00 PM PST 23 31712811539 ps
T957 /workspace/coverage/default/48.sram_ctrl_ram_cfg.4615850392545358122187005024774353204588776035953841574632898575425804318594 Nov 22 02:17:41 PM PST 23 Nov 22 02:17:47 PM PST 23 607542526 ps
T958 /workspace/coverage/default/12.sram_ctrl_multiple_keys.105696714819742047455206491526535702242324760008479903843416420134348809806531 Nov 22 02:11:18 PM PST 23 Nov 22 02:25:21 PM PST 23 28731174678 ps
T959 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.33736115873766677796347744859418466660986994699192669943269458770709260932104 Nov 22 02:16:38 PM PST 23 Nov 22 02:45:45 PM PST 23 624328106 ps
T960 /workspace/coverage/default/10.sram_ctrl_alert_test.1820972545689654327373802500370241730806403197402453894980984415998278993266 Nov 22 02:07:41 PM PST 23 Nov 22 02:07:43 PM PST 23 16600825 ps
T961 /workspace/coverage/default/10.sram_ctrl_lc_escalation.71271543813604498035142155892459876421841699829735101919662650411071619323900 Nov 22 02:07:40 PM PST 23 Nov 22 02:09:26 PM PST 23 19084394710 ps
T962 /workspace/coverage/default/10.sram_ctrl_ram_cfg.15272213846248682612675919931050794842408466057859747531741551438774463187812 Nov 22 02:07:40 PM PST 23 Nov 22 02:07:48 PM PST 23 607542526 ps
T963 /workspace/coverage/default/19.sram_ctrl_ram_cfg.55381236624696457272702460601748373205081080752181917721057604850784862059831 Nov 22 02:12:33 PM PST 23 Nov 22 02:12:40 PM PST 23 607542526 ps
T964 /workspace/coverage/default/14.sram_ctrl_multiple_keys.8258077801808688950884783394947505629723756203087515965163361309687563413301 Nov 22 02:11:27 PM PST 23 Nov 22 02:23:52 PM PST 23 28731174678 ps
T965 /workspace/coverage/default/46.sram_ctrl_lc_escalation.106834389152398109472086770783951321355412188890936175993758817011393377784632 Nov 22 02:16:53 PM PST 23 Nov 22 02:18:39 PM PST 23 19084394710 ps
T966 /workspace/coverage/default/37.sram_ctrl_lc_escalation.44134011058515930491646826222262648674868965502023744992416183894440472925593 Nov 22 02:15:56 PM PST 23 Nov 22 02:17:44 PM PST 23 19084394710 ps
T967 /workspace/coverage/default/36.sram_ctrl_alert_test.84705385896864626927481458058248432955750801364588174053087446182331765645635 Nov 22 02:15:33 PM PST 23 Nov 22 02:15:34 PM PST 23 16600825 ps
T968 /workspace/coverage/default/27.sram_ctrl_multiple_keys.97916272559070598216534974644199870563403238829379214474535707665343245197188 Nov 22 02:13:58 PM PST 23 Nov 22 02:26:37 PM PST 23 28731174678 ps
T969 /workspace/coverage/default/42.sram_ctrl_max_throughput.66150211890001667082202689680778824692154911244116097916977993845686128598803 Nov 22 02:16:27 PM PST 23 Nov 22 02:18:46 PM PST 23 1342947357 ps
T970 /workspace/coverage/default/0.sram_ctrl_alert_test.112809873363349528972392864898077135181306272668744478382512681107687817217554 Nov 22 02:07:10 PM PST 23 Nov 22 02:07:14 PM PST 23 16600825 ps
T971 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2089528353824115406358661095669777566762333457080584780429040194877062703734 Nov 22 02:13:45 PM PST 23 Nov 22 02:16:11 PM PST 23 1371125703 ps
T972 /workspace/coverage/default/49.sram_ctrl_lc_escalation.52226390314423620070253765244112940505359500385325868108106596468291532671461 Nov 22 02:18:07 PM PST 23 Nov 22 02:19:54 PM PST 23 19084394710 ps
T973 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.43709487604813468034780113281576947316344043413179523001524247471378435113247 Nov 22 02:07:39 PM PST 23 Nov 22 02:09:00 PM PST 23 4750777237 ps
T974 /workspace/coverage/default/30.sram_ctrl_ram_cfg.115293677084918470913324104152563095341597221739206003266245099199641135595512 Nov 22 02:14:52 PM PST 23 Nov 22 02:15:03 PM PST 23 607542526 ps
T975 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.43664551500023086314312109946927838294049480572673008516510763831938645113811 Nov 22 02:13:56 PM PST 23 Nov 22 02:16:06 PM PST 23 1371125703 ps
T976 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.81150740998011153623897760732886764706888931605480030406853587644597828199682 Nov 22 02:15:29 PM PST 23 Nov 22 02:17:44 PM PST 23 1371125703 ps
T977 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.18925083120601703775492371549462810071916905587280283461098992410929064244262 Nov 22 02:13:15 PM PST 23 Nov 22 02:14:34 PM PST 23 4750777237 ps
T978 /workspace/coverage/default/47.sram_ctrl_bijection.84420512045173481293129304159186337980092371204087528985850583797793822741140 Nov 22 02:17:02 PM PST 23 Nov 22 03:02:12 PM PST 23 295482808505 ps
T979 /workspace/coverage/default/10.sram_ctrl_partial_access.99634353628997104058971577551266126392101418875864294040443601077326313091842 Nov 22 02:07:40 PM PST 23 Nov 22 02:07:59 PM PST 23 1006378621 ps
T980 /workspace/coverage/default/15.sram_ctrl_multiple_keys.91644436968765977810162317123932864212795042318296104118281105537988194613956 Nov 22 02:11:35 PM PST 23 Nov 22 02:25:02 PM PST 23 28731174678 ps
T981 /workspace/coverage/default/44.sram_ctrl_alert_test.98711589901653226013508476118207529846384481314377257086278905787051956601731 Nov 22 02:16:41 PM PST 23 Nov 22 02:16:42 PM PST 23 16600825 ps
T982 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.47245868682126866576476338184303603461565579450210072324370923225436553227872 Nov 22 02:15:41 PM PST 23 Nov 22 02:17:02 PM PST 23 4750777237 ps
T983 /workspace/coverage/default/29.sram_ctrl_regwen.103848063293595661815152408095072264703918241081152731495406737000412585420369 Nov 22 02:14:35 PM PST 23 Nov 22 02:22:24 PM PST 23 19913691647 ps
T984 /workspace/coverage/default/35.sram_ctrl_executable.75053617968069208460862835801008530319015713191011369967840955623448308417732 Nov 22 02:15:29 PM PST 23 Nov 22 02:32:28 PM PST 23 31712811539 ps
T985 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.7595557551495408345890688385717838124103723376122669723041087092211042780840 Nov 22 02:13:54 PM PST 23 Nov 22 02:28:30 PM PST 23 13467153934 ps
T986 /workspace/coverage/default/7.sram_ctrl_bijection.80653019179698410878847121789814288910781857385770212367376496972816188216839 Nov 22 02:07:39 PM PST 23 Nov 22 02:54:34 PM PST 23 295482808505 ps
T987 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3553927664429362214543277242600463551041236528238157113159220887372098272101 Nov 22 02:16:59 PM PST 23 Nov 22 02:26:24 PM PST 23 45083829570 ps
T988 /workspace/coverage/default/18.sram_ctrl_bijection.82648891117661201283086133853492569417101216924295133637094750306154958669218 Nov 22 02:12:17 PM PST 23 Nov 22 02:58:11 PM PST 23 295482808505 ps
T989 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.111923358358096233328857323004579321898655044287622959861171728884148908406997 Nov 22 02:07:38 PM PST 23 Nov 22 02:14:50 PM PST 23 9325508496 ps
T990 /workspace/coverage/default/28.sram_ctrl_multiple_keys.97811685290178731894810901566673963354123597239128445328467806743929147403281 Nov 22 02:14:12 PM PST 23 Nov 22 02:26:58 PM PST 23 28731174678 ps

Test location /workspace/coverage/default/8.sram_ctrl_executable.91500219965896360570686756661426088787789142678287606847853833443340902905381
Short name T11
Test name
Test status
Simulation time 31712811539 ps
CPU time 851.52 seconds
Started Nov 22 02:07:42 PM PST 23
Finished Nov 22 02:21:55 PM PST 23
Peak memory 368076 kb
Host smart-142bd8d5-4e62-44d3-aa9f-83be10a1a3ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91500219965896360570686756661426088787789142678287606847853833443340902905381 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.91500219965896360570686756661426088787789142678287606847853833443340902905381
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.56582608650029326352104044042833961323250158000098357863351900788378825124247
Short name T6
Test name
Test status
Simulation time 19084394710 ps
CPU time 102.2 seconds
Started Nov 22 02:12:00 PM PST 23
Finished Nov 22 02:13:45 PM PST 23
Peak memory 211020 kb
Host smart-b8321590-0c54-4cac-894b-7b55b68c736a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56582608650029326352104044042833961323250158000098357863351900788378825124247 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.56582608650029326352104044042833961323250158000098357863351900788378825124247
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.43886095997820648722421815691572195678478931410035572105101579451565158238044
Short name T7
Test name
Test status
Simulation time 624328106 ps
CPU time 2096.24 seconds
Started Nov 22 02:16:28 PM PST 23
Finished Nov 22 02:51:25 PM PST 23
Peak memory 498184 kb
Host smart-42fe9857-4a17-4ee8-8547-558b231e2f4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=43886095997820648722421815691572195678478931410035572105101579451565158238044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sr
am_ctrl_stress_all_with_rand_reset.43886095997820648722421815691572195678478931410035572105101579451565158238044
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.67675029381190049517062106407797730676416685891344084791301784604830895758033
Short name T48
Test name
Test status
Simulation time 163313937 ps
CPU time 1.53 seconds
Started Nov 22 01:55:02 PM PST 23
Finished Nov 22 01:55:07 PM PST 23
Peak memory 202152 kb
Host smart-30ad1f58-ecca-473f-8bdc-624e6e811ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67675029381190049517062106407797730676416685891344084791301
784604830895758033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_intg_err.6767502938119004951706210640779773067641
6685891344084791301784604830895758033
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.13120504934857314420837775327770236715412398188633612849905670881483356558498
Short name T88
Test name
Test status
Simulation time 45083829570 ps
CPU time 580.49 seconds
Started Nov 22 02:07:22 PM PST 23
Finished Nov 22 02:17:04 PM PST 23
Peak memory 202884 kb
Host smart-3c303e69-7ab6-4769-8e6c-caebc1f4adb1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131205049348573144208377753277702367154123981886336128499056708814833
56558498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access_b2b.13120504934857314420837775327770236715412
398188633612849905670881483356558498
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.84423835779181357535424951568718653075447971542744866599249987674449978198657
Short name T25
Test name
Test status
Simulation time 216402798 ps
CPU time 2.02 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:07:23 PM PST 23
Peak memory 221268 kb
Host smart-f8fb7ed6-28ab-4fa8-8651-63b6719d0026
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8442383577918135753542495156871865307544797154274486659924998767444
9978198657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.844238357791813575354249515687186530754479715427448665992499
87674449978198657
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.34953618832356279411506402639801648347315217292131758681669161668026600639640
Short name T3
Test name
Test status
Simulation time 19913691647 ps
CPU time 673.27 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:22:30 PM PST 23
Peak memory 372528 kb
Host smart-f2b8bd06-60cc-446e-8eca-8619508da10c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34953618832356279411506402639801648347315217292131758681669161668026600639640 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.34953618832356279411506402639801648347315217292131758681669161668026600639640
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.91447411859016362181924983567242500317354490065865365638679636353396416937708
Short name T31
Test name
Test status
Simulation time 6599780302 ps
CPU time 56.55 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:59 PM PST 23
Peak memory 202344 kb
Host smart-6ab8e0f4-4046-458d-ac93-ab0ddecac8ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91447411859016362181924983567242500317354490065865365638
679636353396416937708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.914474118590163621819249
83567242500317354490065865365638679636353396416937708
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.28057463972678240848635104862312828242549956787914562036637392835413030617586
Short name T19
Test name
Test status
Simulation time 13467153934 ps
CPU time 1038.77 seconds
Started Nov 22 02:07:04 PM PST 23
Finished Nov 22 02:24:24 PM PST 23
Peak memory 378812 kb
Host smart-9f77de45-f539-423e-b305-a5983f34420f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28057463972678240848635104862312828242549956787914562036637392835413030617586
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_key_req.2805746397267824084863510486231282824254
9956787914562036637392835413030617586
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.57493233779843990970741700383966532235785139962202853654898243934796512288501
Short name T252
Test name
Test status
Simulation time 607542526 ps
CPU time 6.2 seconds
Started Nov 22 02:07:06 PM PST 23
Finished Nov 22 02:07:17 PM PST 23
Peak memory 203080 kb
Host smart-bbde0310-1d25-4c9c-8fdd-9eac50d9f0f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57493233779843990970741700383966532235785139962202853654898243934796512288501 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.57493233779843990970741700383966532235785139962202853654898243934796512288501
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.97721573573045472314525426454159139203474304338488778184535240872076070300809
Short name T255
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:11:20 PM PST 23
Finished Nov 22 02:11:21 PM PST 23
Peak memory 202580 kb
Host smart-c2e03b83-77d0-47d2-8091-7e28d133b94e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977215735730454723145254264541591392034743043384887781845352408720
76070300809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.977215735730454723145254264541591392034743043384887781
84535240872076070300809
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.77671534573352185148574000369631618969715444943027097838840173340484268644098
Short name T64
Test name
Test status
Simulation time 22582920 ps
CPU time 0.63 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:54:58 PM PST 23
Peak memory 201824 kb
Host smart-8baae45a-abeb-4eb6-b98a-c6f0e663a3e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77671534573352185148574000369631618969715444943027097838840173
340484268644098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_aliasing.7767153457335218514857400036963161896971544
4943027097838840173340484268644098
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.55463029822207436965198577677370798155867372064810384530660350053608247921646
Short name T145
Test name
Test status
Simulation time 122117838 ps
CPU time 1.32 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 01:54:53 PM PST 23
Peak memory 202180 kb
Host smart-0fd723a2-b0fd-4327-8540-02157de1f5a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55463029822207436965198577677370798155867372064810384530660350
053608247921646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_bash.5546302982220743696519857767737079815586737
2064810384530660350053608247921646
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.73506251104599959907197125012983945993190343559821940488057152114874441488107
Short name T159
Test name
Test status
Simulation time 23779339 ps
CPU time 0.65 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 01:54:53 PM PST 23
Peak memory 201996 kb
Host smart-6145fbce-b3b3-4c7a-8b30-11784a600f50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73506251104599959907197125012983945993190343559821940488057152
114874441488107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_reset.7350625110459995990719712501298394599319034
3559821940488057152114874441488107
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.31151297542882181734008777778513858307734846636601993562460852147034137156789
Short name T50
Test name
Test status
Simulation time 609578224 ps
CPU time 5.22 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:10 PM PST 23
Peak memory 202112 kb
Host smart-974fa00c-520e-445f-a0fb-f0f71c1f746d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311512975428821
81734008777778513858307734846636601993562460852147034137156789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_r
w_with_rand_reset.31151297542882181734008777778513858307734846636601993562460852147034137156789
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.61165113511442705793176420017562603902104835420693767331688977341754970228273
Short name T69
Test name
Test status
Simulation time 19547230 ps
CPU time 0.64 seconds
Started Nov 22 01:54:50 PM PST 23
Finished Nov 22 01:54:52 PM PST 23
Peak memory 201980 kb
Host smart-c60c8018-4dbe-48c4-9337-a787c2e9cf0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61165113511442705793176420017562603902104835420693767331688977341754
970228273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.6116511351144270579317642001756260390210483542069376733
1688977341754970228273
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.71461085596839642352803879595430879560378065862907186126103312436007685792137
Short name T167
Test name
Test status
Simulation time 6599780302 ps
CPU time 59.74 seconds
Started Nov 22 01:54:46 PM PST 23
Finished Nov 22 01:55:46 PM PST 23
Peak memory 202388 kb
Host smart-4e912d3b-69d9-4e5a-93f2-8a1c5a23d078
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71461085596839642352803879595430879560378065862907186126
103312436007685792137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.7146108559683964235280387
9595430879560378065862907186126103312436007685792137
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.5498193194699947925986336642794049335573016442929163104494856031632776245022
Short name T138
Test name
Test status
Simulation time 23886481 ps
CPU time 0.68 seconds
Started Nov 22 01:54:51 PM PST 23
Finished Nov 22 01:54:53 PM PST 23
Peak memory 202048 kb
Host smart-7047bc1a-2993-4a8b-b484-a873dabe6970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54981931946999479259863366427940493355730164429291
63104494856031632776245022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.549819319469994792598633
6642794049335573016442929163104494856031632776245022
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.21303005843898178506414549872606275834121661495410015147939063825696292395803
Short name T187
Test name
Test status
Simulation time 117100021 ps
CPU time 2.53 seconds
Started Nov 22 01:54:49 PM PST 23
Finished Nov 22 01:54:53 PM PST 23
Peak memory 202188 kb
Host smart-32691d86-f734-44ee-b8fa-497719a5a9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21303005843898178506414549872606275834121661495410015147939063825696292
395803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.2130300584389817850641454987260627583412166149541001514
7939063825696292395803
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.40731725216397540708136331474712153000829677266943249815020029463131138626306
Short name T178
Test name
Test status
Simulation time 163313937 ps
CPU time 1.49 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:54:49 PM PST 23
Peak memory 202092 kb
Host smart-a6aa9a20-1fe1-4cbc-a0a3-a67b1c7e549d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40731725216397540708136331474712153000829677266943249815020
029463131138626306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_intg_err.40731725216397540708136331474712153000829
677266943249815020029463131138626306
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.6461806534861362036476013141340844237734983074995272098094728913622277812237
Short name T210
Test name
Test status
Simulation time 22582920 ps
CPU time 0.66 seconds
Started Nov 22 01:54:52 PM PST 23
Finished Nov 22 01:54:54 PM PST 23
Peak memory 202072 kb
Host smart-bd6ae621-4c53-489c-93c4-a6c23471d917
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64618065348613620364760131413408442377349830749952720980947289
13622277812237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_aliasing.64618065348613620364760131413408442377349830
74995272098094728913622277812237
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.99010753011305628975578792118893773372497492980128916830987536097104182810107
Short name T122
Test name
Test status
Simulation time 122117838 ps
CPU time 1.32 seconds
Started Nov 22 01:54:53 PM PST 23
Finished Nov 22 01:54:56 PM PST 23
Peak memory 202184 kb
Host smart-a5ea52c0-90ba-4811-b62a-2ef92a64b988
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99010753011305628975578792118893773372497492980128916830987536
097104182810107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.9901075301130562897557879211889377337249749
2980128916830987536097104182810107
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.81368886264710465322790727508751245229257594866695137754487804066591484420838
Short name T192
Test name
Test status
Simulation time 23779339 ps
CPU time 0.63 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:55:00 PM PST 23
Peak memory 201972 kb
Host smart-5c107246-7b22-438e-ab77-bdc819e9335c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81368886264710465322790727508751245229257594866695137754487804
066591484420838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_reset.8136888626471046532279072750875124522925759
4866695137754487804066591484420838
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.96726415734964811810006189543143620458148880611764893493721536817109366085210
Short name T63
Test name
Test status
Simulation time 609578224 ps
CPU time 5.2 seconds
Started Nov 22 01:54:54 PM PST 23
Finished Nov 22 01:55:01 PM PST 23
Peak memory 202092 kb
Host smart-ec8ed0f8-fa7d-40b7-9bf9-9955165fb344
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967264157349648
11810006189543143620458148880611764893493721536817109366085210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_r
w_with_rand_reset.96726415734964811810006189543143620458148880611764893493721536817109366085210
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.114133135089823081968350807840182562493155794938048668986148029318386510347082
Short name T176
Test name
Test status
Simulation time 19547230 ps
CPU time 0.68 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:54:59 PM PST 23
Peak memory 201988 kb
Host smart-fe24d05e-089f-43d3-9513-a502569ef8ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11413313508982308196835080784018256249315579493804866898614802931838
6510347082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.114133135089823081968350807840182562493155794938048668
986148029318386510347082
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.86085289985713739840595274710705586414745367072192828158575234386002106340481
Short name T84
Test name
Test status
Simulation time 6599780302 ps
CPU time 55.9 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:55:53 PM PST 23
Peak memory 202380 kb
Host smart-15ca9347-f960-44e1-bfc1-c8ddea5c6286
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86085289985713739840595274710705586414745367072192828158
575234386002106340481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.8608528998571373984059527
4710705586414745367072192828158575234386002106340481
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.25294721308175567514993254976722528917299882410905878572740491685430232856766
Short name T71
Test name
Test status
Simulation time 23886481 ps
CPU time 0.65 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:02 PM PST 23
Peak memory 201992 kb
Host smart-21c0a803-b1b2-48be-85c2-d37a553cf2b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25294721308175567514993254976722528917299882410905
878572740491685430232856766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.25294721308175567514993
254976722528917299882410905878572740491685430232856766
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.10885563205416197970303094457582796116174452380453849967305400827122979936436
Short name T215
Test name
Test status
Simulation time 117100021 ps
CPU time 2.38 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:55:01 PM PST 23
Peak memory 202184 kb
Host smart-71332625-b348-4d94-8f4f-97ef5c025320
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10885563205416197970303094457582796116174452380453849967305400827122979
936436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.1088556320541619797030309445758279611617445238045384996
7305400827122979936436
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.55221053937313941714682830054523459849425731071978088749963934026457451836324
Short name T204
Test name
Test status
Simulation time 163313937 ps
CPU time 1.43 seconds
Started Nov 22 01:54:47 PM PST 23
Finished Nov 22 01:54:49 PM PST 23
Peak memory 201992 kb
Host smart-ee5e9e3f-8f7a-42fa-8c4d-b2455efdb904
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55221053937313941714682830054523459849425731071978088749963
934026457451836324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_intg_err.55221053937313941714682830054523459849425
731071978088749963934026457451836324
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.114283093249972753519544059163280145238877828691890222249201778493596217284581
Short name T186
Test name
Test status
Simulation time 609578224 ps
CPU time 5.31 seconds
Started Nov 22 01:55:03 PM PST 23
Finished Nov 22 01:55:12 PM PST 23
Peak memory 202192 kb
Host smart-e32e3a69-bb43-4091-881c-15cf706c9e4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114283093249972
753519544059163280145238877828691890222249201778493596217284581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem
_rw_with_rand_reset.114283093249972753519544059163280145238877828691890222249201778493596217284581
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.77850814228922720028417556196782502103366539157994972371591181652984735536001
Short name T152
Test name
Test status
Simulation time 19547230 ps
CPU time 0.62 seconds
Started Nov 22 01:55:02 PM PST 23
Finished Nov 22 01:55:07 PM PST 23
Peak memory 201988 kb
Host smart-7209071e-763a-4377-a301-634a795d7464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77850814228922720028417556196782502103366539157994972371591181652984
735536001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.778508142289227200284175561967825021033665391579949723
71591181652984735536001
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.33693274085043288077818723938727364666718150358285048397796726177616089780344
Short name T213
Test name
Test status
Simulation time 6599780302 ps
CPU time 56.75 seconds
Started Nov 22 01:55:02 PM PST 23
Finished Nov 22 01:56:03 PM PST 23
Peak memory 202348 kb
Host smart-b7cafa61-f817-41af-a5ef-eb46df58b841
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33693274085043288077818723938727364666718150358285048397
796726177616089780344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.336932740850432880778187
23938727364666718150358285048397796726177616089780344
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.102090798558225618714210810727550317983958953969827899520034138960125332011419
Short name T189
Test name
Test status
Simulation time 23886481 ps
CPU time 0.71 seconds
Started Nov 22 01:55:05 PM PST 23
Finished Nov 22 01:55:09 PM PST 23
Peak memory 202060 kb
Host smart-6a165c62-4ac5-4e27-b6a5-15863f614351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10209079855822561871421081072755031798395895396982
7899520034138960125332011419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.102090798558225618714
210810727550317983958953969827899520034138960125332011419
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.68109867432021687773944888846384548275465514344895265475989834070233950254274
Short name T57
Test name
Test status
Simulation time 117100021 ps
CPU time 2.46 seconds
Started Nov 22 01:55:16 PM PST 23
Finished Nov 22 01:55:20 PM PST 23
Peak memory 202208 kb
Host smart-5e176807-9330-418c-ad38-159f0aff53ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68109867432021687773944888846384548275465514344895265475989834070233950
254274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.681098674320216877739448888463845482754655143448952654
75989834070233950254274
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.85496929916767435639680743766685541201224599722134428551832343324307592513926
Short name T124
Test name
Test status
Simulation time 609578224 ps
CPU time 5.35 seconds
Started Nov 22 01:55:03 PM PST 23
Finished Nov 22 01:55:13 PM PST 23
Peak memory 202180 kb
Host smart-c04f95f9-4678-444b-a9b7-931e1b23599a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854969299167674
35639680743766685541201224599722134428551832343324307592513926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_
rw_with_rand_reset.85496929916767435639680743766685541201224599722134428551832343324307592513926
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.26524079794436608048423006079806256528702133554301221361608200135576180001883
Short name T157
Test name
Test status
Simulation time 19547230 ps
CPU time 0.65 seconds
Started Nov 22 01:55:14 PM PST 23
Finished Nov 22 01:55:16 PM PST 23
Peak memory 201992 kb
Host smart-e0419887-c78e-455d-8e87-f67bfedbf679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26524079794436608048423006079806256528702133554301221361608200135576
180001883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.265240797944366080484230060798062565287021335543012213
61608200135576180001883
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.12007403740571077682143060438531484021851132880453236427796077681288908619192
Short name T32
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:55:17 PM PST 23
Finished Nov 22 01:55:19 PM PST 23
Peak memory 201944 kb
Host smart-81f30bc8-cc4c-4891-a54a-66dcd387cbab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12007403740571077682143060438531484021851132880453
236427796077681288908619192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1200740374057107768214
3060438531484021851132880453236427796077681288908619192
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.35070764332577133522023776168424856803168778388003523459817123391255297576574
Short name T209
Test name
Test status
Simulation time 117100021 ps
CPU time 2.34 seconds
Started Nov 22 01:55:14 PM PST 23
Finished Nov 22 01:55:17 PM PST 23
Peak memory 202200 kb
Host smart-2d145de7-5257-4a30-b7dc-1f7351590583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35070764332577133522023776168424856803168778388003523459817123391255297
576574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.350707643325771335220237761684248568031687783880035234
59817123391255297576574
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.92671118812612931593232787075399846656642063783120464243574390679823797845647
Short name T185
Test name
Test status
Simulation time 163313937 ps
CPU time 1.54 seconds
Started Nov 22 01:55:03 PM PST 23
Finished Nov 22 01:55:08 PM PST 23
Peak memory 202164 kb
Host smart-9e234369-fb04-4067-a486-df8c092bf38d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92671118812612931593232787075399846656642063783120464243574
390679823797845647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_intg_err.9267111881261293159323278707539984665664
2063783120464243574390679823797845647
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.28396412284469339667035682003936544637390369771046962410348706978768367213249
Short name T123
Test name
Test status
Simulation time 609578224 ps
CPU time 5.14 seconds
Started Nov 22 01:55:16 PM PST 23
Finished Nov 22 01:55:22 PM PST 23
Peak memory 202144 kb
Host smart-58b3f6b1-85ca-4317-b2fd-ccdf6cb73df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283964122844693
39667035682003936544637390369771046962410348706978768367213249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_
rw_with_rand_reset.28396412284469339667035682003936544637390369771046962410348706978768367213249
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.44220108766693112709492361897463513828073568436381713752027570358251885829304
Short name T196
Test name
Test status
Simulation time 19547230 ps
CPU time 0.65 seconds
Started Nov 22 01:55:20 PM PST 23
Finished Nov 22 01:55:21 PM PST 23
Peak memory 202000 kb
Host smart-868439b4-8132-41fb-83bc-3ca66b7d6f9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44220108766693112709492361897463513828073568436381713752027570358251
885829304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.442201087666931127094923618974635138280735684363817137
52027570358251885829304
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.92574553490816719080025078389496148714434730316639409294916197198109586833345
Short name T81
Test name
Test status
Simulation time 6599780302 ps
CPU time 59.68 seconds
Started Nov 22 01:55:29 PM PST 23
Finished Nov 22 01:56:29 PM PST 23
Peak memory 202356 kb
Host smart-05bc8934-c3e4-4c99-a6f7-f043d9e6ffe9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92574553490816719080025078389496148714434730316639409294
916197198109586833345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.925745534908167190800250
78389496148714434730316639409294916197198109586833345
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.59391605579866802736515735894551934200191260117311480031394669696021290131010
Short name T136
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:55:23 PM PST 23
Finished Nov 22 01:55:25 PM PST 23
Peak memory 202048 kb
Host smart-098a42eb-8fe1-4cc4-afb3-0e047f5c1ab3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59391605579866802736515735894551934200191260117311
480031394669696021290131010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.5939160557986680273651
5735894551934200191260117311480031394669696021290131010
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.65285733560913185608747064657468406533206180832871939261534633031473635919958
Short name T203
Test name
Test status
Simulation time 117100021 ps
CPU time 2.44 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:55:01 PM PST 23
Peak memory 202208 kb
Host smart-2215ad91-0b2f-4a5b-accf-9ede1bc25bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65285733560913185608747064657468406533206180832871939261534633031473635
919958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.652857335609131856087470646574684065332061808328719392
61534633031473635919958
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.84952136589659008873558452297705090695454886572909421823031433341265979803810
Short name T53
Test name
Test status
Simulation time 163313937 ps
CPU time 1.55 seconds
Started Nov 22 01:55:16 PM PST 23
Finished Nov 22 01:55:19 PM PST 23
Peak memory 202116 kb
Host smart-f4237290-38cf-4d28-9515-c2491376f976
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84952136589659008873558452297705090695454886572909421823031
433341265979803810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_intg_err.8495213658965900887355845229770509069545
4886572909421823031433341265979803810
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.13525278061176384095880825966787844948115315772018649129197307819184383394919
Short name T156
Test name
Test status
Simulation time 609578224 ps
CPU time 5.15 seconds
Started Nov 22 01:55:15 PM PST 23
Finished Nov 22 01:55:21 PM PST 23
Peak memory 202176 kb
Host smart-cc0b846e-b6f9-4a29-8b9d-80bd871fda40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135252780611763
84095880825966787844948115315772018649129197307819184383394919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_
rw_with_rand_reset.13525278061176384095880825966787844948115315772018649129197307819184383394919
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.53816298029072511586735132513698933336994263970034695183116912633790502469652
Short name T165
Test name
Test status
Simulation time 19547230 ps
CPU time 0.63 seconds
Started Nov 22 01:55:17 PM PST 23
Finished Nov 22 01:55:19 PM PST 23
Peak memory 201732 kb
Host smart-ce60801c-7446-477d-a00b-7a0c845cd559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53816298029072511586735132513698933336994263970034695183116912633790
502469652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.538162980290725115867351325136989333369942639700346951
83116912633790502469652
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.96396940503270038670510401781606454616779767948761192222955774361836651067004
Short name T173
Test name
Test status
Simulation time 6599780302 ps
CPU time 58.17 seconds
Started Nov 22 01:55:17 PM PST 23
Finished Nov 22 01:56:16 PM PST 23
Peak memory 202292 kb
Host smart-77e5ef46-186b-4481-8d9b-f174e4371adb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96396940503270038670510401781606454616779767948761192222
955774361836651067004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.963969405032700386705104
01781606454616779767948761192222955774361836651067004
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.28073842112919194892892491907513496988301990300477062212391666735974195218595
Short name T155
Test name
Test status
Simulation time 23886481 ps
CPU time 0.67 seconds
Started Nov 22 01:55:12 PM PST 23
Finished Nov 22 01:55:13 PM PST 23
Peak memory 202004 kb
Host smart-33f01b97-e577-4659-85a0-7a25f7972dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28073842112919194892892491907513496988301990300477
062212391666735974195218595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2807384211291919489289
2491907513496988301990300477062212391666735974195218595
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.103680850422852171897616120267898621110313585011291848358813567312066038662763
Short name T150
Test name
Test status
Simulation time 117100021 ps
CPU time 2.59 seconds
Started Nov 22 01:55:30 PM PST 23
Finished Nov 22 01:55:34 PM PST 23
Peak memory 202208 kb
Host smart-c2d53ed5-4da8-488f-bf6f-92c8542d6e60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10368085042285217189761612026789862111031358501129184835881356731206603
8662763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.10368085042285217189761612026789862111031358501129184
8358813567312066038662763
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.72161406910027710784534158897122708640283592612319816121028284997280108894667
Short name T168
Test name
Test status
Simulation time 163313937 ps
CPU time 1.47 seconds
Started Nov 22 01:55:12 PM PST 23
Finished Nov 22 01:55:15 PM PST 23
Peak memory 202060 kb
Host smart-3cef1a57-aa6a-41ce-810b-97de526765b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72161406910027710784534158897122708640283592612319816121028
284997280108894667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_intg_err.7216140691002771078453415889712270864028
3592612319816121028284997280108894667
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2753388801222790784762166359440804078639770071694006766118366200426597588409
Short name T202
Test name
Test status
Simulation time 609578224 ps
CPU time 5.25 seconds
Started Nov 22 01:55:13 PM PST 23
Finished Nov 22 01:55:20 PM PST 23
Peak memory 202064 kb
Host smart-049680fd-ed62-4479-8c90-907d1b794b9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275338880122279
0784762166359440804078639770071694006766118366200426597588409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_r
w_with_rand_reset.2753388801222790784762166359440804078639770071694006766118366200426597588409
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.109220307288222441580776216968852381357820340614090908571963114148021718277220
Short name T147
Test name
Test status
Simulation time 19547230 ps
CPU time 0.63 seconds
Started Nov 22 01:55:17 PM PST 23
Finished Nov 22 01:55:19 PM PST 23
Peak memory 201896 kb
Host smart-2689877c-4389-4568-9efd-62886159a18c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10922030728822244158077621696885238135782034061409090857196311414802
1718277220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.10922030728822244158077621696885238135782034061409090
8571963114148021718277220
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.24316379693410198168974636929809471582256986702887037812267831414456456057521
Short name T190
Test name
Test status
Simulation time 6599780302 ps
CPU time 58.99 seconds
Started Nov 22 01:55:13 PM PST 23
Finished Nov 22 01:56:13 PM PST 23
Peak memory 202348 kb
Host smart-967331d1-5fa7-45b5-a55c-4d2637a2d847
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24316379693410198168974636929809471582256986702887037812
267831414456456057521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.243163796934101981689746
36929809471582256986702887037812267831414456456057521
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.54686919289222119138480301159059662212359808631906554940257505090982479677821
Short name T193
Test name
Test status
Simulation time 23886481 ps
CPU time 0.65 seconds
Started Nov 22 01:55:16 PM PST 23
Finished Nov 22 01:55:18 PM PST 23
Peak memory 201896 kb
Host smart-50d174af-2178-49d4-a767-f06bd33035ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54686919289222119138480301159059662212359808631906
554940257505090982479677821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.5468691928922211913848
0301159059662212359808631906554940257505090982479677821
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.74935775348446543620301075272505320928479133810301673103428548837526370744580
Short name T206
Test name
Test status
Simulation time 117100021 ps
CPU time 2.39 seconds
Started Nov 22 01:55:15 PM PST 23
Finished Nov 22 01:55:18 PM PST 23
Peak memory 202200 kb
Host smart-8023cb72-9a7c-4cb2-be2e-40dedf2efc38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74935775348446543620301075272505320928479133810301673103428548837526370
744580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.749357753484465436203010752725053209284791338103016731
03428548837526370744580
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.42050395587334384894656781291956537119223233963363281496803716727506309072098
Short name T211
Test name
Test status
Simulation time 163313937 ps
CPU time 1.47 seconds
Started Nov 22 01:55:16 PM PST 23
Finished Nov 22 01:55:19 PM PST 23
Peak memory 202160 kb
Host smart-45d5bf71-6db0-4468-a2a1-a3031b960724
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42050395587334384894656781291956537119223233963363281496803
716727506309072098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_intg_err.4205039558733438489465678129195653711922
3233963363281496803716727506309072098
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.6129430770868737286973581567024016833421007710427826296709374708963229912445
Short name T130
Test name
Test status
Simulation time 609578224 ps
CPU time 5.41 seconds
Started Nov 22 01:55:19 PM PST 23
Finished Nov 22 01:55:25 PM PST 23
Peak memory 202172 kb
Host smart-8bda9f58-db61-4510-8428-9386d138c785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612943077086873
7286973581567024016833421007710427826296709374708963229912445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_r
w_with_rand_reset.6129430770868737286973581567024016833421007710427826296709374708963229912445
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.16429328088108863185898691246250559479438832487975219700557897932524774752405
Short name T132
Test name
Test status
Simulation time 19547230 ps
CPU time 0.63 seconds
Started Nov 22 01:55:14 PM PST 23
Finished Nov 22 01:55:16 PM PST 23
Peak memory 201924 kb
Host smart-cc43ba34-01ce-4bf3-abbf-ef5a27cea057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16429328088108863185898691246250559479438832487975219700557897932524
774752405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.164293280881088631858986912462505594794388324879752197
00557897932524774752405
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.64596020427356262482596168260181124629404187252242605454597679794562494336051
Short name T85
Test name
Test status
Simulation time 6599780302 ps
CPU time 58.02 seconds
Started Nov 22 01:55:15 PM PST 23
Finished Nov 22 01:56:13 PM PST 23
Peak memory 202296 kb
Host smart-9ecc2e7a-4fc5-47e3-923c-de78204ea52e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64596020427356262482596168260181124629404187252242605454
597679794562494336051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.645960204273562624825961
68260181124629404187252242605454597679794562494336051
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.114092636433972087775584276278459075461230008302917764472870171503756737264008
Short name T135
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:55:16 PM PST 23
Finished Nov 22 01:55:18 PM PST 23
Peak memory 202056 kb
Host smart-6ce371aa-afe1-4f06-b625-8e5c3ba03232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11409263643397208777558427627845907546123000830291
7764472870171503756737264008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.114092636433972087775
584276278459075461230008302917764472870171503756737264008
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.16683384380872382608109423910533040996479431321485118877128881171439546085399
Short name T169
Test name
Test status
Simulation time 117100021 ps
CPU time 2.32 seconds
Started Nov 22 01:55:13 PM PST 23
Finished Nov 22 01:55:16 PM PST 23
Peak memory 202128 kb
Host smart-f0f27774-7314-4c0b-b0e6-994e96261e2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16683384380872382608109423910533040996479431321485118877128881171439546
085399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.166833843808723826081094239105330409964794313214851188
77128881171439546085399
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.90825624285135790952516004537182304776109446870412989668834352134893236194858
Short name T137
Test name
Test status
Simulation time 163313937 ps
CPU time 1.47 seconds
Started Nov 22 01:55:11 PM PST 23
Finished Nov 22 01:55:13 PM PST 23
Peak memory 202168 kb
Host smart-19b417af-961e-43ae-96b1-f6a4aa62c521
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90825624285135790952516004537182304776109446870412989668834
352134893236194858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_intg_err.9082562428513579095251600453718230477610
9446870412989668834352134893236194858
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.53810410784606333883194070254548636685283471011541262397516351879783948885699
Short name T163
Test name
Test status
Simulation time 609578224 ps
CPU time 5.17 seconds
Started Nov 22 01:55:15 PM PST 23
Finished Nov 22 01:55:21 PM PST 23
Peak memory 202160 kb
Host smart-b4240c05-63df-45e0-b1f8-b30d9eb7a0b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538104107846063
33883194070254548636685283471011541262397516351879783948885699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_
rw_with_rand_reset.53810410784606333883194070254548636685283471011541262397516351879783948885699
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.61331131106322234623729956527645991018858235272319968808253478362482250641217
Short name T127
Test name
Test status
Simulation time 19547230 ps
CPU time 0.64 seconds
Started Nov 22 01:55:20 PM PST 23
Finished Nov 22 01:55:21 PM PST 23
Peak memory 202000 kb
Host smart-67b85ad8-0344-4b11-a9ed-cedfe6d9abc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61331131106322234623729956527645991018858235272319968808253478362482
250641217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.613311311063222346237299565276459910188582352723199688
08253478362482250641217
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.8879784263405482895945722070460820040732480522934155339997508095189025040025
Short name T86
Test name
Test status
Simulation time 6599780302 ps
CPU time 58.36 seconds
Started Nov 22 01:55:16 PM PST 23
Finished Nov 22 01:56:16 PM PST 23
Peak memory 202316 kb
Host smart-d0cb91ff-a9bf-4e89-be6d-98edefce9cf5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88797842634054828959457220704608200407324805229341553399
97508095189025040025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.8879784263405482895945722
070460820040732480522934155339997508095189025040025
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.77822413249595707897252258113948291680051378124373947410563850541335562034463
Short name T96
Test name
Test status
Simulation time 23886481 ps
CPU time 0.71 seconds
Started Nov 22 01:55:14 PM PST 23
Finished Nov 22 01:55:15 PM PST 23
Peak memory 201920 kb
Host smart-9652c549-766b-4665-bbd3-90ad44449bed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77822413249595707897252258113948291680051378124373
947410563850541335562034463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.7782241324959570789725
2258113948291680051378124373947410563850541335562034463
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.49419978625018015794611224626327874289390174943024976804298062610448369315291
Short name T191
Test name
Test status
Simulation time 117100021 ps
CPU time 2.45 seconds
Started Nov 22 01:55:33 PM PST 23
Finished Nov 22 01:55:36 PM PST 23
Peak memory 202208 kb
Host smart-d0b8d421-362c-4753-9f47-4a445965e24d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49419978625018015794611224626327874289390174943024976804298062610448369
315291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.494199786250180157946112246263278742893901749430249768
04298062610448369315291
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.111310604526398987070910091953818569414716403451129193805330663881140262935069
Short name T154
Test name
Test status
Simulation time 163313937 ps
CPU time 1.53 seconds
Started Nov 22 01:55:11 PM PST 23
Finished Nov 22 01:55:13 PM PST 23
Peak memory 202176 kb
Host smart-bdd8d580-5f57-4d68-bf35-e1bedaa6ebf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11131060452639898707091009195381856941471640345112919380533
0663881140262935069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_intg_err.111310604526398987070910091953818569414
716403451129193805330663881140262935069
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.103893343158297421828240478497285892365340947681963054671970279335716151949800
Short name T201
Test name
Test status
Simulation time 609578224 ps
CPU time 5.08 seconds
Started Nov 22 01:55:14 PM PST 23
Finished Nov 22 01:55:20 PM PST 23
Peak memory 202132 kb
Host smart-c83d7580-a37b-4889-9d11-b6d0033961e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103893343158297
421828240478497285892365340947681963054671970279335716151949800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem
_rw_with_rand_reset.103893343158297421828240478497285892365340947681963054671970279335716151949800
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.8504768809475117202033563294205174532521568729423800640749744222698954520162
Short name T171
Test name
Test status
Simulation time 19547230 ps
CPU time 0.61 seconds
Started Nov 22 01:55:13 PM PST 23
Finished Nov 22 01:55:14 PM PST 23
Peak memory 202008 kb
Host smart-94f8cb76-cde9-4868-835d-c35d7783e223
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85047688094751172020335632942051745325215687294238006407497442226989
54520162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.8504768809475117202033563294205174532521568729423800640
749744222698954520162
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.30289478462768985131349709593073352066062995234609903602155646809383155898260
Short name T139
Test name
Test status
Simulation time 6599780302 ps
CPU time 57.09 seconds
Started Nov 22 01:55:14 PM PST 23
Finished Nov 22 01:56:12 PM PST 23
Peak memory 202112 kb
Host smart-74632dc9-cb22-45c6-ae13-bcda08d0561c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30289478462768985131349709593073352066062995234609903602
155646809383155898260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.302894784627689851313497
09593073352066062995234609903602155646809383155898260
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.106808613613331305943048798644930206514255581797305763679951723873959143396349
Short name T170
Test name
Test status
Simulation time 23886481 ps
CPU time 0.67 seconds
Started Nov 22 01:55:13 PM PST 23
Finished Nov 22 01:55:15 PM PST 23
Peak memory 202000 kb
Host smart-e9de0674-9f5b-4a8b-9d06-df3836fd29b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10680861361333130594304879864493020651425558179730
5763679951723873959143396349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.106808613613331305943
048798644930206514255581797305763679951723873959143396349
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.10442951025476605586555108735105628130177658322680207608493995930848957996942
Short name T172
Test name
Test status
Simulation time 117100021 ps
CPU time 2.44 seconds
Started Nov 22 01:55:13 PM PST 23
Finished Nov 22 01:55:16 PM PST 23
Peak memory 202208 kb
Host smart-883c7e02-c18b-439e-bb71-2268567fd7ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10442951025476605586555108735105628130177658322680207608493995930848957
996942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.104429510254766055865551087351056281301776583226802076
08493995930848957996942
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2346890792682761939360708380453632925945306326042678579217651325001808196692
Short name T142
Test name
Test status
Simulation time 163313937 ps
CPU time 1.55 seconds
Started Nov 22 01:55:15 PM PST 23
Finished Nov 22 01:55:18 PM PST 23
Peak memory 202104 kb
Host smart-4040f8e9-504d-424a-8cc9-cc6748f13b72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23468907926827619393607083804536329259453063260426785792176
51325001808196692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_intg_err.23468907926827619393607083804536329259453
06326042678579217651325001808196692
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.61378348831018304818619751485286270084179009106281752041078773751199544397140
Short name T166
Test name
Test status
Simulation time 609578224 ps
CPU time 5.2 seconds
Started Nov 22 01:55:33 PM PST 23
Finished Nov 22 01:55:40 PM PST 23
Peak memory 201992 kb
Host smart-9dccc28c-6dd0-4435-8d92-a60ae05ee37e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613783488310183
04818619751485286270084179009106281752041078773751199544397140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_
rw_with_rand_reset.61378348831018304818619751485286270084179009106281752041078773751199544397140
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.5727840388464264007023930061384418554495343448625228506613591880054243251736
Short name T195
Test name
Test status
Simulation time 19547230 ps
CPU time 0.61 seconds
Started Nov 22 01:55:34 PM PST 23
Finished Nov 22 01:55:37 PM PST 23
Peak memory 201976 kb
Host smart-e7ce8200-377f-4697-b85d-a90ca5fbf480
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57278403884642640070239300613844185544953434486252285066135918800542
43251736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.5727840388464264007023930061384418554495343448625228506
613591880054243251736
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.10802973449096983307588226112716846497332216127285774938199724404191272368627
Short name T77
Test name
Test status
Simulation time 6599780302 ps
CPU time 58.47 seconds
Started Nov 22 01:55:14 PM PST 23
Finished Nov 22 01:56:13 PM PST 23
Peak memory 202364 kb
Host smart-a7bd7a0c-2052-420c-a501-9ec6ac6e786f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10802973449096983307588226112716846497332216127285774938
199724404191272368627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.108029734490969833075882
26112716846497332216127285774938199724404191272368627
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.113661322765775341675056646452898103562040629050166301453843348576760878391144
Short name T179
Test name
Test status
Simulation time 23886481 ps
CPU time 0.65 seconds
Started Nov 22 01:55:34 PM PST 23
Finished Nov 22 01:55:36 PM PST 23
Peak memory 201984 kb
Host smart-a67d30af-fead-4112-97a4-9e1eb5ddcf8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11366132276577534167505664645289810356204062905016
6301453843348576760878391144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.113661322765775341675
056646452898103562040629050166301453843348576760878391144
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.670164647643522888858581715613672606021799275848467541082507969987344764391
Short name T60
Test name
Test status
Simulation time 117100021 ps
CPU time 2.46 seconds
Started Nov 22 01:55:15 PM PST 23
Finished Nov 22 01:55:18 PM PST 23
Peak memory 202192 kb
Host smart-de19cbee-5f1b-4913-8a26-44058f845bcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67016464764352288885858171561367260602179927584846754108250796998734476
4391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.67016464764352288885858171561367260602179927584846754108
2507969987344764391
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.87761969234963493236196594210753723056734620983425640195630620833280474463000
Short name T128
Test name
Test status
Simulation time 163313937 ps
CPU time 1.5 seconds
Started Nov 22 01:55:20 PM PST 23
Finished Nov 22 01:55:22 PM PST 23
Peak memory 202168 kb
Host smart-0c76579c-0f71-4a79-ab64-37111134353e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87761969234963493236196594210753723056734620983425640195630
620833280474463000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_intg_err.8776196923496349323619659421075372305673
4620983425640195630620833280474463000
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.30046181533722445649216928368539379611345409597366649536827707570970045291802
Short name T143
Test name
Test status
Simulation time 609578224 ps
CPU time 5.24 seconds
Started Nov 22 01:55:34 PM PST 23
Finished Nov 22 01:55:41 PM PST 23
Peak memory 202184 kb
Host smart-022720cf-4b5d-43a3-b7e5-fbf3cb7bd752
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300461815337224
45649216928368539379611345409597366649536827707570970045291802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_
rw_with_rand_reset.30046181533722445649216928368539379611345409597366649536827707570970045291802
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.90266491336684871862364616748606484752062607572496498991776158605503272681099
Short name T141
Test name
Test status
Simulation time 19547230 ps
CPU time 0.62 seconds
Started Nov 22 01:55:35 PM PST 23
Finished Nov 22 01:55:38 PM PST 23
Peak memory 201976 kb
Host smart-472b7eeb-e165-40f9-9763-1666022cdd1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90266491336684871862364616748606484752062607572496498991776158605503
272681099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.902664913366848718623646167486064847520626075724964989
91776158605503272681099
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.103211154912372674403456714302975642778037012914020900030594641927353276934887
Short name T153
Test name
Test status
Simulation time 6599780302 ps
CPU time 55 seconds
Started Nov 22 01:55:34 PM PST 23
Finished Nov 22 01:56:31 PM PST 23
Peak memory 202320 kb
Host smart-c3c01b64-7e40-4dfc-94a4-98c8f02b63c1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10321115491237267440345671430297564277803701291402090003
0594641927353276934887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.10321115491237267440345
6714302975642778037012914020900030594641927353276934887
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.75587944230571732010444725210334378489945169878858737366499074575992622797087
Short name T144
Test name
Test status
Simulation time 23886481 ps
CPU time 0.67 seconds
Started Nov 22 01:55:35 PM PST 23
Finished Nov 22 01:55:38 PM PST 23
Peak memory 202012 kb
Host smart-3ab0bf26-6fd4-4f85-8471-2e1e66706ffc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75587944230571732010444725210334378489945169878858
737366499074575992622797087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.7558794423057173201044
4725210334378489945169878858737366499074575992622797087
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.38241638472650502841811160385397340316368123576822575179486301835705613421667
Short name T59
Test name
Test status
Simulation time 117100021 ps
CPU time 2.37 seconds
Started Nov 22 01:55:35 PM PST 23
Finished Nov 22 01:55:39 PM PST 23
Peak memory 202212 kb
Host smart-b1203253-05a1-4838-80f1-adff8d5794a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38241638472650502841811160385397340316368123576822575179486301835705613
421667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.382416384726505028418111603853973403163681235768225751
79486301835705613421667
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.103069340598747431990071044771124132974926048755095464332150456962950656345182
Short name T47
Test name
Test status
Simulation time 163313937 ps
CPU time 1.44 seconds
Started Nov 22 01:55:33 PM PST 23
Finished Nov 22 01:55:35 PM PST 23
Peak memory 202112 kb
Host smart-312f1546-a6a0-4867-91ea-b972c783612d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10306934059874743199007104477112413297492604875509546433215
0456962950656345182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_intg_err.103069340598747431990071044771124132974
926048755095464332150456962950656345182
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.73983361105693687217764672700484913355352697285945388662574935674259925671288
Short name T126
Test name
Test status
Simulation time 22582920 ps
CPU time 0.66 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:54:58 PM PST 23
Peak memory 202068 kb
Host smart-3e1a4d10-21d4-4d49-a0db-43cb5687a902
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73983361105693687217764672700484913355352697285945388662574935
674259925671288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_aliasing.7398336110569368721776467270048491335535269
7285945388662574935674259925671288
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.15474479891670548892218945944925612429787134237901825443147620343188064944576
Short name T160
Test name
Test status
Simulation time 122117838 ps
CPU time 1.33 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:03 PM PST 23
Peak memory 202132 kb
Host smart-0489d790-86d4-4a34-bd4e-0143efc5ab13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15474479891670548892218945944925612429787134237901825443147620
343188064944576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.1547447989167054889221894594492561242978713
4237901825443147620343188064944576
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.78708103697583881776286149189657531401819402409069497086150817836179386540092
Short name T66
Test name
Test status
Simulation time 23779339 ps
CPU time 0.69 seconds
Started Nov 22 01:54:54 PM PST 23
Finished Nov 22 01:54:57 PM PST 23
Peak memory 201952 kb
Host smart-5ec150f2-b9b5-4a6a-9a70-cf755916cffd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78708103697583881776286149189657531401819402409069497086150817
836179386540092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_reset.7870810369758388177628614918965753140181940
2409069497086150817836179386540092
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.39757538203191427449273522235785879739277651992642770010268199798723259966846
Short name T51
Test name
Test status
Simulation time 609578224 ps
CPU time 5.24 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:10 PM PST 23
Peak memory 202212 kb
Host smart-5d9d542d-607b-4be4-a7ce-6f2812192778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397575382031914
27449273522235785879739277651992642770010268199798723259966846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_r
w_with_rand_reset.39757538203191427449273522235785879739277651992642770010268199798723259966846
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.87952917610482111939900079438745538750371900184082431092991745369464661417712
Short name T80
Test name
Test status
Simulation time 19547230 ps
CPU time 0.63 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:54:58 PM PST 23
Peak memory 201940 kb
Host smart-59b98ee9-a4ce-4327-9e08-e13551e1f71a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87952917610482111939900079438745538750371900184082431092991745369464
661417712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.8795291761048211193990007943874553875037190018408243109
2991745369464661417712
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.97516860504755559732182431463975439449917216778530988356167022781947515403288
Short name T164
Test name
Test status
Simulation time 6599780302 ps
CPU time 58.1 seconds
Started Nov 22 01:54:51 PM PST 23
Finished Nov 22 01:55:51 PM PST 23
Peak memory 202252 kb
Host smart-19a5b07e-bc6c-4f8e-801f-9b9709bd2e64
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97516860504755559732182431463975439449917216778530988356
167022781947515403288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.9751686050475555973218243
1463975439449917216778530988356167022781947515403288
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.21669999302620157421332876632725765636041480744236003361825489026203340085192
Short name T212
Test name
Test status
Simulation time 23886481 ps
CPU time 0.67 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:54:59 PM PST 23
Peak memory 202056 kb
Host smart-fcb02e5d-41b5-406e-9b2a-dec99fe284ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21669999302620157421332876632725765636041480744236
003361825489026203340085192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.21669999302620157421332
876632725765636041480744236003361825489026203340085192
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.42601008519622297573023060351469273407969513590554830449226457863712482144882
Short name T174
Test name
Test status
Simulation time 117100021 ps
CPU time 2.44 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:55:02 PM PST 23
Peak memory 202204 kb
Host smart-e9ca1b10-6d60-495c-a1f9-fc44e6d018a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42601008519622297573023060351469273407969513590554830449226457863712482
144882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.4260100851962229757302306035146927340796951359055483044
9226457863712482144882
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.55281314534479351765588494765018590137523459564421829253345281065317904877562
Short name T175
Test name
Test status
Simulation time 163313937 ps
CPU time 1.54 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 202172 kb
Host smart-49c7e1a0-ad7a-4ad3-b83a-cc4f2501bbea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55281314534479351765588494765018590137523459564421829253345
281065317904877562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_intg_err.55281314534479351765588494765018590137523
459564421829253345281065317904877562
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.62746283545692386397693538652031091269369409791532639912643354838406043443197
Short name T30
Test name
Test status
Simulation time 22582920 ps
CPU time 0.71 seconds
Started Nov 22 01:54:55 PM PST 23
Finished Nov 22 01:54:58 PM PST 23
Peak memory 201996 kb
Host smart-db96b7d4-3fc9-49b7-b628-d08ce90a580c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62746283545692386397693538652031091269369409791532639912643354
838406043443197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.6274628354569238639769353865203109126936940
9791532639912643354838406043443197
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.82899458900857819930128144140838487631744732028535471085671289552582166294886
Short name T140
Test name
Test status
Simulation time 122117838 ps
CPU time 1.29 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:55:02 PM PST 23
Peak memory 202156 kb
Host smart-4aaeac4b-434b-454b-a169-2923875779d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82899458900857819930128144140838487631744732028535471085671289
552582166294886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_bash.8289945890085781993012814414083848763174473
2028535471085671289552582166294886
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.69125063116818918079171883624956482020463431849939686088877450514117108743938
Short name T125
Test name
Test status
Simulation time 23779339 ps
CPU time 0.63 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:02 PM PST 23
Peak memory 201972 kb
Host smart-e1da007c-eaae-43fe-8321-f03b4fbd1b71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69125063116818918079171883624956482020463431849939686088877450
514117108743938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_reset.6912506311681891807917188362495648202046343
1849939686088877450514117108743938
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.10265965801160319342922288048165964291537045583674172312225960399636336660992
Short name T198
Test name
Test status
Simulation time 609578224 ps
CPU time 5.18 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:55:09 PM PST 23
Peak memory 202204 kb
Host smart-7ea0eadf-e7bc-46ec-adba-ea9ec544aa31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102659658011603
19342922288048165964291537045583674172312225960399636336660992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_r
w_with_rand_reset.10265965801160319342922288048165964291537045583674172312225960399636336660992
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.31964992380519496049604698737831435414377928201654282352330966619603322384514
Short name T129
Test name
Test status
Simulation time 19547230 ps
CPU time 0.62 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:55:01 PM PST 23
Peak memory 201936 kb
Host smart-ad1c374c-420c-4bbc-bd96-57c783e357d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31964992380519496049604698737831435414377928201654282352330966619603
322384514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.3196499238051949604960469873783143541437792820165428235
2330966619603322384514
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.104198086280643600581056486010368836519799598592726634244625540625924061023894
Short name T162
Test name
Test status
Simulation time 6599780302 ps
CPU time 58.57 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:56:03 PM PST 23
Peak memory 202380 kb
Host smart-13d22619-48cd-4c46-aac8-7136de533c98
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10419808628064360058105648601036883651979959859272663424
4625540625924061023894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.104198086280643600581056
486010368836519799598592726634244625540625924061023894
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.51171154468460862196607619170892472631347097569251722943895126288100848924039
Short name T99
Test name
Test status
Simulation time 23886481 ps
CPU time 0.65 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 202068 kb
Host smart-a22429e7-5c2e-4ecf-8c9c-4d2667ad38d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51171154468460862196607619170892472631347097569251
722943895126288100848924039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.51171154468460862196607
619170892472631347097569251722943895126288100848924039
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.54091580787935463831960597657937433038328151556659657103207428682468429234458
Short name T58
Test name
Test status
Simulation time 117100021 ps
CPU time 2.43 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:55:03 PM PST 23
Peak memory 202168 kb
Host smart-f262b6cb-b7ce-4f01-99f0-b955ec6102de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54091580787935463831960597657937433038328151556659657103207428682468429
234458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.5409158078793546383196059765793743303832815155665965710
3207428682468429234458
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.85371674674149293606425275792358827613741264280915777957752733551617481132194
Short name T183
Test name
Test status
Simulation time 163313937 ps
CPU time 1.51 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:03 PM PST 23
Peak memory 202060 kb
Host smart-ae7bdeaf-8599-4f8e-a3f0-b43d3b98d60b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85371674674149293606425275792358827613741264280915777957752
733551617481132194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_intg_err.85371674674149293606425275792358827613741
264280915777957752733551617481132194
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.114760855771495887991376764846292605452052750410043571839176427366505061161949
Short name T194
Test name
Test status
Simulation time 22582920 ps
CPU time 0.66 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:02 PM PST 23
Peak memory 202040 kb
Host smart-3eaf91ce-ea3b-49b6-bf47-70b53da69e9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11476085577149588799137676484629260545205275041004357183917642
7366505061161949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_aliasing.114760855771495887991376764846292605452052
750410043571839176427366505061161949
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.36012596917899307105210684084039466729713262532777076937320645785368242115444
Short name T67
Test name
Test status
Simulation time 122117838 ps
CPU time 1.3 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:55:00 PM PST 23
Peak memory 202144 kb
Host smart-3557d0eb-6951-4757-bec5-0f1ae4898579
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36012596917899307105210684084039466729713262532777076937320645
785368242115444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_bash.3601259691789930710521068408403946672971326
2532777076937320645785368242115444
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.38247381663261697107512461027348987333602112273802272993611563404847626532502
Short name T177
Test name
Test status
Simulation time 23779339 ps
CPU time 0.65 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 202020 kb
Host smart-20673afe-9823-44cf-b694-c0329e8d8e73
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247381663261697107512461027348987333602112273802272993611563
404847626532502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_reset.3824738166326169710751246102734898733360211
2273802272993611563404847626532502
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.49472841528790214190133861162965304815358432458210030085774297281173150063161
Short name T200
Test name
Test status
Simulation time 609578224 ps
CPU time 5.24 seconds
Started Nov 22 01:55:02 PM PST 23
Finished Nov 22 01:55:11 PM PST 23
Peak memory 202192 kb
Host smart-bdc83414-4da1-4c74-bbab-76f40fde005c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494728415287902
14190133861162965304815358432458210030085774297281173150063161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_r
w_with_rand_reset.49472841528790214190133861162965304815358432458210030085774297281173150063161
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.72131591288988861383020352033415336699431853766037642850533996771049478034949
Short name T205
Test name
Test status
Simulation time 19547230 ps
CPU time 0.6 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 202000 kb
Host smart-3dc6bb81-6b04-4ad6-9482-488fbc1ecfac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72131591288988861383020352033415336699431853766037642850533996771049
478034949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.7213159128898886138302035203341533669943185376603764285
0533996771049478034949
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.93177519516785476753792694427293544757138130934456272902746426281181831409984
Short name T87
Test name
Test status
Simulation time 6599780302 ps
CPU time 56.82 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:56:02 PM PST 23
Peak memory 202360 kb
Host smart-62c6530a-2575-4ccc-8b8b-e39b336947f1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93177519516785476753792694427293544757138130934456272902
746426281181831409984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.9317751951678547675379269
4427293544757138130934456272902746426281181831409984
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.52402300398668724933108397378185348010901923032624895689961037248468315250539
Short name T149
Test name
Test status
Simulation time 23886481 ps
CPU time 0.72 seconds
Started Nov 22 01:54:55 PM PST 23
Finished Nov 22 01:54:58 PM PST 23
Peak memory 202008 kb
Host smart-c5f7783c-c7f5-43ef-8795-8693d5c30884
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52402300398668724933108397378185348010901923032624
895689961037248468315250539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.52402300398668724933108
397378185348010901923032624895689961037248468315250539
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.93558634982218313494583045095251791402617731873897691126627425580921147750503
Short name T56
Test name
Test status
Simulation time 117100021 ps
CPU time 2.44 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:55:03 PM PST 23
Peak memory 202192 kb
Host smart-3e271a14-b67e-4518-ac16-fb9a7088a41b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93558634982218313494583045095251791402617731873897691126627425580921147
750503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.9355863498221831349458304509525179140261773187389769112
6627425580921147750503
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.40615128841264764863536184555350119168682709041229061669522262383641545366356
Short name T134
Test name
Test status
Simulation time 163313937 ps
CPU time 1.42 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:55:01 PM PST 23
Peak memory 202108 kb
Host smart-711e67d5-3e7d-473e-af4b-973f007d62be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40615128841264764863536184555350119168682709041229061669522
262383641545366356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_intg_err.40615128841264764863536184555350119168682
709041229061669522262383641545366356
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.32512268922028897778247421190217845357111061731622474120974990474610047567793
Short name T146
Test name
Test status
Simulation time 609578224 ps
CPU time 5.32 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:07 PM PST 23
Peak memory 202092 kb
Host smart-0f81c218-4900-4917-91ad-3a9b7bf61bac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325122689220288
97778247421190217845357111061731622474120974990474610047567793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_r
w_with_rand_reset.32512268922028897778247421190217845357111061731622474120974990474610047567793
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.106100637150894289721600707371789813228252766636754291294535629738724247824334
Short name T161
Test name
Test status
Simulation time 19547230 ps
CPU time 0.61 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:55:04 PM PST 23
Peak memory 201988 kb
Host smart-c9de6338-d6c5-40af-878f-9fffaad86bfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10610063715089428972160070737178981322825276663675429129453562973872
4247824334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.106100637150894289721600707371789813228252766636754291
294535629738724247824334
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.52154708174082915490241353810147950748445221552037214695548416931211604076811
Short name T68
Test name
Test status
Simulation time 6599780302 ps
CPU time 57.59 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:55:55 PM PST 23
Peak memory 202068 kb
Host smart-219e9125-bbe6-4b02-a6a0-d23fdce35765
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52154708174082915490241353810147950748445221552037214695
548416931211604076811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.5215470817408291549024135
3810147950748445221552037214695548416931211604076811
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.95537291622258273661265236646308842766500278177520440952985819582440148088893
Short name T180
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:55:02 PM PST 23
Peak memory 201988 kb
Host smart-b7cd0ce6-6ae2-48dc-8389-2a457416447f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95537291622258273661265236646308842766500278177520
440952985819582440148088893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.95537291622258273661265
236646308842766500278177520440952985819582440148088893
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.76218344811629093157643678602429730359749804024530230882560518490799230779788
Short name T54
Test name
Test status
Simulation time 117100021 ps
CPU time 2.42 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:08 PM PST 23
Peak memory 202208 kb
Host smart-6f399fa0-f316-4df5-9a5b-d51419cf2ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76218344811629093157643678602429730359749804024530230882560518490799230
779788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.7621834481162909315764367860242973035974980402453023088
2560518490799230779788
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.106953177646651158281561049400073966757182732385531125813202582949523697747936
Short name T49
Test name
Test status
Simulation time 163313937 ps
CPU time 1.52 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:55:01 PM PST 23
Peak memory 202148 kb
Host smart-cc5236cb-a88b-42b0-8a70-2be89a4248e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10695317764665115828156104940007396675718273238553112581320
2582949523697747936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_intg_err.1069531776466511582815610494000739667571
82732385531125813202582949523697747936
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.10776305821613019645643104123423593926092886353154496470179951236060021424861
Short name T52
Test name
Test status
Simulation time 609578224 ps
CPU time 5.42 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:55:09 PM PST 23
Peak memory 202196 kb
Host smart-c901ebb1-6c43-4fba-99e9-911deb194bd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107763058216130
19645643104123423593926092886353154496470179951236060021424861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_r
w_with_rand_reset.10776305821613019645643104123423593926092886353154496470179951236060021424861
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.72498509719034281865012652999048648258712613855664347778004318442270176984504
Short name T65
Test name
Test status
Simulation time 19547230 ps
CPU time 0.62 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 202000 kb
Host smart-58329631-c133-49d5-a7c8-dc38f864ae1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72498509719034281865012652999048648258712613855664347778004318442270
176984504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.7249850971903428186501265299904864825871261385566434777
8004318442270176984504
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.6147690435437613040930997881488506146754508728024833274372063123670348107368
Short name T181
Test name
Test status
Simulation time 6599780302 ps
CPU time 55.73 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:55:57 PM PST 23
Peak memory 202272 kb
Host smart-314532d0-6604-4598-a4ad-863c1d91a4d0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61476904354376130409309978814885061467545087280248332743
72063123670348107368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.61476904354376130409309978
81488506146754508728024833274372063123670348107368
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.26465664620752747247334714167694387205265917088641784305717029628519905471485
Short name T98
Test name
Test status
Simulation time 23886481 ps
CPU time 0.76 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 202040 kb
Host smart-3eb9a3ae-14d2-49fe-adfb-a259184b411e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26465664620752747247334714167694387205265917088641
784305717029628519905471485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.26465664620752747247334
714167694387205265917088641784305717029628519905471485
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.38365065300502150476387525339988660965742068399935273786135530148099501637769
Short name T182
Test name
Test status
Simulation time 117100021 ps
CPU time 2.41 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:07 PM PST 23
Peak memory 202208 kb
Host smart-e0fac04b-2756-411c-9185-1e15a83ce103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38365065300502150476387525339988660965742068399935273786135530148099501
637769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.3836506530050215047638752533998866096574206839993527378
6135530148099501637769
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.93054744943016274227569424506859463866541600163312695192472309128606683173865
Short name T197
Test name
Test status
Simulation time 163313937 ps
CPU time 1.5 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:06 PM PST 23
Peak memory 202172 kb
Host smart-db40263c-f112-4ec6-b232-3b4e29d04b28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93054744943016274227569424506859463866541600163312695192472
309128606683173865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_intg_err.93054744943016274227569424506859463866541
600163312695192472309128606683173865
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.17055585524241717329211729386568134570967571914794990420049006738434426384269
Short name T214
Test name
Test status
Simulation time 609578224 ps
CPU time 5.28 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:10 PM PST 23
Peak memory 202196 kb
Host smart-7996eaee-882f-4d66-a26a-a4fe9a62e2fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170555855242417
17329211729386568134570967571914794990420049006738434426384269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_r
w_with_rand_reset.17055585524241717329211729386568134570967571914794990420049006738434426384269
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.62865182040719649560217832902292039833816057136984017361081556473910268152324
Short name T70
Test name
Test status
Simulation time 19547230 ps
CPU time 0.61 seconds
Started Nov 22 01:54:59 PM PST 23
Finished Nov 22 01:55:03 PM PST 23
Peak memory 201988 kb
Host smart-51f30f27-fd9b-4a35-8632-78cd027d1ed2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62865182040719649560217832902292039833816057136984017361081556473910
268152324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.6286518204071964956021783290229203983381605713698401736
1081556473910268152324
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1788505344261904705647516108466418990679600893545237429181790121243170224085
Short name T83
Test name
Test status
Simulation time 6599780302 ps
CPU time 56.63 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:56:01 PM PST 23
Peak memory 202324 kb
Host smart-a124c9a2-c0c5-4b92-8b50-b9c90671adac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17885053442619047056475161084664189906796008935452374291
81790121243170224085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.17885053442619047056475161
08466418990679600893545237429181790121243170224085
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.54470711131283528066830022597444772227365863781056551929231569781259233604481
Short name T151
Test name
Test status
Simulation time 23886481 ps
CPU time 0.64 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:55:04 PM PST 23
Peak memory 201992 kb
Host smart-1d57ae8b-c82e-4358-9ee0-5e4498eb915b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54470711131283528066830022597444772227365863781056
551929231569781259233604481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.54470711131283528066830
022597444772227365863781056551929231569781259233604481
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.51864385224181930031316165096451777802934021714034290839245171000842046081810
Short name T55
Test name
Test status
Simulation time 117100021 ps
CPU time 2.45 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:07 PM PST 23
Peak memory 202164 kb
Host smart-e8a99ac0-e230-4c8b-bcbb-c1ec5e87e201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51864385224181930031316165096451777802934021714034290839245171000842046
081810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.5186438522418193003131616509645177780293402171403429083
9245171000842046081810
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.6717016130418538571827433867789769714057226571462556995737811320253518184733
Short name T133
Test name
Test status
Simulation time 163313937 ps
CPU time 1.48 seconds
Started Nov 22 01:55:04 PM PST 23
Finished Nov 22 01:55:09 PM PST 23
Peak memory 202196 kb
Host smart-bc1e18a1-5d28-4060-bb9d-6fd752d9278c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67170161304185385718274338677897697140572265714625569957378
11320253518184733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_intg_err.671701613041853857182743386778976971405722
6571462556995737811320253518184733
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.48441691054872613505342829509943036320569742589463830561039792090198530359861
Short name T208
Test name
Test status
Simulation time 609578224 ps
CPU time 5.09 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:55:09 PM PST 23
Peak memory 202168 kb
Host smart-c0f45578-2f0e-4a10-a9b5-c715211a8e5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484416910548726
13505342829509943036320569742589463830561039792090198530359861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_r
w_with_rand_reset.48441691054872613505342829509943036320569742589463830561039792090198530359861
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.57551692702204569504893566368013001463646312994454454612563704876046250376580
Short name T78
Test name
Test status
Simulation time 19547230 ps
CPU time 0.63 seconds
Started Nov 22 01:54:56 PM PST 23
Finished Nov 22 01:54:59 PM PST 23
Peak memory 201852 kb
Host smart-8401806d-e01a-4b65-a57c-4c9964ecd2df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57551692702204569504893566368013001463646312994454454612563704876046
250376580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.5755169270220456950489356636801300146364631299445445461
2563704876046250376580
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.100378487120127451095545822979861728130367066941935269374968904261612857818345
Short name T188
Test name
Test status
Simulation time 6599780302 ps
CPU time 56.73 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:56:01 PM PST 23
Peak memory 202292 kb
Host smart-680e0b2e-2f76-46de-ab5f-8a050679fa30
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10037848712012745109554582297986172813036706694193526937
4968904261612857818345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.100378487120127451095545
822979861728130367066941935269374968904261612857818345
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.50260613777827375233379027488079298649020262073251618283318702229172874656880
Short name T131
Test name
Test status
Simulation time 23886481 ps
CPU time 0.67 seconds
Started Nov 22 01:55:03 PM PST 23
Finished Nov 22 01:55:08 PM PST 23
Peak memory 202036 kb
Host smart-6fcf06bb-0cb7-4131-8dae-2b3f384e14dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50260613777827375233379027488079298649020262073251
618283318702229172874656880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.50260613777827375233379
027488079298649020262073251618283318702229172874656880
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.89810490053213331165134152149133561089994378667025560410798718438104862799469
Short name T148
Test name
Test status
Simulation time 117100021 ps
CPU time 2.45 seconds
Started Nov 22 01:54:57 PM PST 23
Finished Nov 22 01:55:01 PM PST 23
Peak memory 202192 kb
Host smart-aade04f0-50ab-434c-a242-5d13d4563b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89810490053213331165134152149133561089994378667025560410798718438104862
799469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.8981049005321333116513415214913356108999437866702556041
0798718438104862799469
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.107561028670912098466949084365539322444596124217628596728834945832299718783748
Short name T184
Test name
Test status
Simulation time 163313937 ps
CPU time 1.56 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:07 PM PST 23
Peak memory 202108 kb
Host smart-c45925ef-094e-421e-843a-336179745220
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10756102867091209846694908436553932244459612421762859672883
4945832299718783748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_intg_err.1075610286709120984669490843655393224445
96124217628596728834945832299718783748
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.63924063712984168663822962045398062650331678972911578669295397800587258099799
Short name T62
Test name
Test status
Simulation time 609578224 ps
CPU time 5.05 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 202044 kb
Host smart-e2ca55b6-63b6-403c-ac9f-559b65e7d518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639240637129841
68663822962045398062650331678972911578669295397800587258099799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_r
w_with_rand_reset.63924063712984168663822962045398062650331678972911578669295397800587258099799
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.98422744247689494619722581158429349373909871206550051599214947549081620751950
Short name T207
Test name
Test status
Simulation time 19547230 ps
CPU time 0.62 seconds
Started Nov 22 01:55:02 PM PST 23
Finished Nov 22 01:55:06 PM PST 23
Peak memory 201976 kb
Host smart-0245e4a3-d042-4a9e-8f4c-8c3d6561eaf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98422744247689494619722581158429349373909871206550051599214947549081
620751950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.9842274424768949461972258115842934937390987120655005159
9214947549081620751950
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.10526243101749363336146484349002130946591912372913208928135092944157395404304
Short name T79
Test name
Test status
Simulation time 6599780302 ps
CPU time 57.91 seconds
Started Nov 22 01:54:58 PM PST 23
Finished Nov 22 01:55:59 PM PST 23
Peak memory 202228 kb
Host smart-f49937bb-5ddd-4928-8385-204dcee9b3d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526243101749363336146484349002130946591912372913208928
135092944157395404304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1052624310174936333614648
4349002130946591912372913208928135092944157395404304
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.26209100846828647687021217690865422260712389168770831560647202968697977603411
Short name T97
Test name
Test status
Simulation time 23886481 ps
CPU time 0.68 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:55:04 PM PST 23
Peak memory 202016 kb
Host smart-3e54a180-b1c2-4d74-a9a9-60041fb5ad7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26209100846828647687021217690865422260712389168770
831560647202968697977603411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.26209100846828647687021
217690865422260712389168770831560647202968697977603411
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.104253788264897596578876015016003926725164304813835885977560003265426639186042
Short name T199
Test name
Test status
Simulation time 117100021 ps
CPU time 2.58 seconds
Started Nov 22 01:55:01 PM PST 23
Finished Nov 22 01:55:07 PM PST 23
Peak memory 202160 kb
Host smart-d10e31df-dffd-4b39-ba56-d167b78c5776
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10425378826489759657887601501600392672516430481383588597756000326542663
9186042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.104253788264897596578876015016003926725164304813835885
977560003265426639186042
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.85674737186548614548316117704908961218873631332261808521826276765077681400303
Short name T158
Test name
Test status
Simulation time 163313937 ps
CPU time 1.53 seconds
Started Nov 22 01:55:00 PM PST 23
Finished Nov 22 01:55:05 PM PST 23
Peak memory 202172 kb
Host smart-d1adb546-8e61-45fa-b261-64bcf5038873
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85674737186548614548316117704908961218873631332261808521826
276765077681400303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_intg_err.85674737186548614548316117704908961218873
631332261808521826276765077681400303
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.112809873363349528972392864898077135181306272668744478382512681107687817217554
Short name T970
Test name
Test status
Simulation time 16600825 ps
CPU time 0.65 seconds
Started Nov 22 02:07:10 PM PST 23
Finished Nov 22 02:07:14 PM PST 23
Peak memory 202600 kb
Host smart-704634b8-eaf4-46c8-be41-ea5f73de0ed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112809873363349528972392864898077135181306272668744478382512681107
687817217554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.112809873363349528972392864898077135181306272668744478
382512681107687817217554
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.14236853175365790837420994345329792466505124407444047651439458105105871243319
Short name T763
Test name
Test status
Simulation time 295482808505 ps
CPU time 2845.16 seconds
Started Nov 22 02:07:05 PM PST 23
Finished Nov 22 02:54:32 PM PST 23
Peak memory 202892 kb
Host smart-18d69f20-5cef-4bac-856c-e04828212311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14236853175365790837420994345329792466505124407444047651439458105105871243319 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.14236853175365790837420994345329792466505124407444047651439458105105871243319
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.50053472331875680528654747997343673619588764459331200674534996910204644310432
Short name T875
Test name
Test status
Simulation time 31712811539 ps
CPU time 996.43 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:23:58 PM PST 23
Peak memory 368112 kb
Host smart-068b803d-5a63-4928-b8fd-82ff97724f2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50053472331875680528654747997343673619588764459331200674534996910204644310432 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.50053472331875680528654747997343673619588764459331200674534996910204644310432
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.14316558283802171417493146248402980722688950856079795747261678811767122688992
Short name T906
Test name
Test status
Simulation time 19084394710 ps
CPU time 103.47 seconds
Started Nov 22 02:07:11 PM PST 23
Finished Nov 22 02:08:58 PM PST 23
Peak memory 211072 kb
Host smart-0520f8f2-b1b3-4b69-af46-202c7a63ac87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14316558283802171417493146248402980722688950856079795747261678811767122688992 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.14316558283802171417493146248402980722688950856079795747261678811767122688992
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.85652975483871234728381981842917060815707291328649225938429152912811534675205
Short name T426
Test name
Test status
Simulation time 1342947357 ps
CPU time 100.76 seconds
Started Nov 22 02:07:07 PM PST 23
Finished Nov 22 02:08:54 PM PST 23
Peak memory 351216 kb
Host smart-a437d198-1640-4a05-9265-2dce2024fd1d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8565297548387123472838198184291706081570729132864922593
8429152912811534675205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max_throughput.856529754838712347283819818429170608
15707291328649225938429152912811534675205
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.79153322629509074238243547559406800928198004633996058580909034171827797765521
Short name T76
Test name
Test status
Simulation time 4750777237 ps
CPU time 82.05 seconds
Started Nov 22 02:07:22 PM PST 23
Finished Nov 22 02:08:45 PM PST 23
Peak memory 212348 kb
Host smart-e239ceef-5626-4746-8fbe-da6eff14a2d8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79153322629509074238243547559406800928198004633996058580909034171827
797765521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.7915332262950907423824354755940680092819800463399
6058580909034171827797765521
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.12866653507669721460422948692204691748231331895054698292526095045144583380998
Short name T878
Test name
Test status
Simulation time 18445453393 ps
CPU time 163.86 seconds
Started Nov 22 02:07:06 PM PST 23
Finished Nov 22 02:09:55 PM PST 23
Peak memory 202796 kb
Host smart-4f509dae-a1a2-4146-a99a-bb8c1c6fb044
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12866653507669721460422948692204691748231331895054698292526095045144583380998
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.12866653507669721460422948692204691748231331895054698292526095045144583380998
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.103813192958839404615839212678928050024085286358311912008590536902985794078392
Short name T588
Test name
Test status
Simulation time 28731174678 ps
CPU time 780.06 seconds
Started Nov 22 02:07:04 PM PST 23
Finished Nov 22 02:20:06 PM PST 23
Peak memory 378576 kb
Host smart-af1bdc2d-4e20-46a5-8b66-cec7ebe7c932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103813192958839404615839212678928050024085286358311912008590536902985794078392 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.103813192958839404615839212678928050024085286358311912008590536902985794078392
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.99575018609465906086995141259168136387291956090829967925219877066169849432490
Short name T849
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.98 seconds
Started Nov 22 02:07:05 PM PST 23
Finished Nov 22 02:07:30 PM PST 23
Peak memory 245640 kb
Host smart-7475f319-4942-48fe-b8d6-f52d04cbec75
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995750186094659060869951412591681363872919560908299679252198770661698
49432490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.9957501860946590608699514125916813638729195609082996792
5219877066169849432490
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.60322399172968119777093966662978641990499401866523112121258917292617252926637
Short name T325
Test name
Test status
Simulation time 45083829570 ps
CPU time 592.35 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:17:13 PM PST 23
Peak memory 202852 kb
Host smart-c95b5ecd-979c-40bd-a3d1-5a16ea404d5d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603223991729681197770939666629786419904994018665231121212589172926172
52926637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access_b2b.60322399172968119777093966662978641990499
401866523112121258917292617252926637
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.69449508693335185162731949899036543490901198779082267224880417653392503992909
Short name T929
Test name
Test status
Simulation time 607542526 ps
CPU time 6.35 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:07:26 PM PST 23
Peak memory 203120 kb
Host smart-98ea4a7c-3e79-428c-ad4a-a9553e7f04db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69449508693335185162731949899036543490901198779082267224880417653392503992909 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.69449508693335185162731949899036543490901198779082267224880417653392503992909
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.107297785454567685038307186258119697339366234560768921711455021964528067944913
Short name T521
Test name
Test status
Simulation time 19913691647 ps
CPU time 544.79 seconds
Started Nov 22 02:07:23 PM PST 23
Finished Nov 22 02:16:29 PM PST 23
Peak memory 372520 kb
Host smart-6593fc2a-85c0-470f-a480-54f0d051b6fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107297785454567685038307186258119697339366234560768921711455021964528067944913 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.107297785454567685038307186258119697339366234560768921711455021964528067944913
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.97672599528330236192942045119989877698878615016547966009305707559228181242001
Short name T555
Test name
Test status
Simulation time 988289480 ps
CPU time 18.81 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:07:40 PM PST 23
Peak memory 245648 kb
Host smart-7488eb3a-0822-40d0-9a3d-9411d6b7e26e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97672599528330236192942045119989877698878615016547966009305707559228181242001 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.97672599528330236192942045119989877698878615016547966009305707559228181242001
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.57626811586187221322169999392960958158109599636693584295757640925692214697935
Short name T945
Test name
Test status
Simulation time 624328106 ps
CPU time 1717.78 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:35:59 PM PST 23
Peak memory 498156 kb
Host smart-09fe3a13-0ae5-42b1-8f73-c9b179d8318e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=57626811586187221322169999392960958158109599636693584295757640925692214697935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sra
m_ctrl_stress_all_with_rand_reset.57626811586187221322169999392960958158109599636693584295757640925692214697935
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.114477218268314570846733036185158609380496033008494203138794822546902358087391
Short name T455
Test name
Test status
Simulation time 9325508496 ps
CPU time 424.95 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:14:26 PM PST 23
Peak memory 202956 kb
Host smart-04f7919d-1d5e-49db-927e-28945cf3ff6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11447721826831457084673303618515860938049603300849420313879482254690235808739
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.114477218268314570846733036185158609380496033008494
203138794822546902358087391
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.38711735526398738190532800360396338930063547184392042502234130036187585646520
Short name T877
Test name
Test status
Simulation time 1371125703 ps
CPU time 133.05 seconds
Started Nov 22 02:07:00 PM PST 23
Finished Nov 22 02:09:14 PM PST 23
Peak memory 351156 kb
Host smart-2f12923d-17b3-4dac-813e-9b021b774140
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387117355263987381905328003603963389300635471843920425
02234130036187585646520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.38711735526398738190532
800360396338930063547184392042502234130036187585646520
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.86848055439220614350805965016649565636996623524747237169182259414244574683084
Short name T238
Test name
Test status
Simulation time 13467153934 ps
CPU time 955.92 seconds
Started Nov 22 02:07:05 PM PST 23
Finished Nov 22 02:23:03 PM PST 23
Peak memory 378828 kb
Host smart-69fdc171-966a-4fd6-bed9-133aee144273
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86848055439220614350805965016649565636996623524747237169182259414244574683084
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_key_req.8684805543922061435080596501664956563699
6623524747237169182259414244574683084
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.3784617781505200413903724876986551372773407261379642724891136635944632944759
Short name T397
Test name
Test status
Simulation time 16600825 ps
CPU time 0.64 seconds
Started Nov 22 02:07:18 PM PST 23
Finished Nov 22 02:07:19 PM PST 23
Peak memory 202556 kb
Host smart-be00dbbf-b6a6-4188-898e-66d35b5c7ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378461778150520041390372487698655137277340726137964272489113663594
4632944759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.37846177815052004139037248769865513727734072613796427248
91136635944632944759
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.23819635589509637366062558660310180490308599132930925093865020353634112922575
Short name T27
Test name
Test status
Simulation time 295482808505 ps
CPU time 2800.04 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:54:01 PM PST 23
Peak memory 202796 kb
Host smart-c0506cc0-5182-4723-8c3c-53632137eddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23819635589509637366062558660310180490308599132930925093865020353634112922575 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.23819635589509637366062558660310180490308599132930925093865020353634112922575
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.34742728431912817542883885338988671308477904232337415100174357295879045868621
Short name T218
Test name
Test status
Simulation time 31712811539 ps
CPU time 1081.46 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:25:23 PM PST 23
Peak memory 368044 kb
Host smart-3481e41c-d3fc-4cb4-b389-6e5da3c2105b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34742728431912817542883885338988671308477904232337415100174357295879045868621 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.34742728431912817542883885338988671308477904232337415100174357295879045868621
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.74617542037004636652741300235135838693542823657918374609564727249464413365933
Short name T471
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.35 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:09:06 PM PST 23
Peak memory 211088 kb
Host smart-a1c931cb-3a72-4076-a564-78fe9b7640aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74617542037004636652741300235135838693542823657918374609564727249464413365933 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.74617542037004636652741300235135838693542823657918374609564727249464413365933
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.61163402776535538230857521363775249160778641809063539061045292897798968275286
Short name T695
Test name
Test status
Simulation time 1342947357 ps
CPU time 122.91 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:09:23 PM PST 23
Peak memory 351224 kb
Host smart-6c57e702-9b43-4edc-ab71-5aa9245ec32b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6116340277653553823085752136377524916077864180906353906
1045292897798968275286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max_throughput.611634027765355382308575213637752491
60778641809063539061045292897798968275286
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.17651771502651172777502700922211279672003241460407553354565263008748135679360
Short name T227
Test name
Test status
Simulation time 4750777237 ps
CPU time 81.35 seconds
Started Nov 22 02:07:22 PM PST 23
Finished Nov 22 02:08:45 PM PST 23
Peak memory 212316 kb
Host smart-d4672884-2cbc-4aa5-a52b-11bf1093e855
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17651771502651172777502700922211279672003241460407553354565263008748
135679360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.1765177150265117277750270092221127967200324146040
7553354565263008748135679360
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.54345307656035657241134135983740707102611792545987693951561583715973283628855
Short name T469
Test name
Test status
Simulation time 18445453393 ps
CPU time 156.42 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:09:57 PM PST 23
Peak memory 202716 kb
Host smart-a55fb5ba-694e-4e1e-a33c-09c57e933d82
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54345307656035657241134135983740707102611792545987693951561583715973283628855
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.54345307656035657241134135983740707102611792545987693951561583715973283628855
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.8181650315877850080548491325064569744762337523649434429218517889801716275628
Short name T678
Test name
Test status
Simulation time 28731174678 ps
CPU time 1037.23 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:24:40 PM PST 23
Peak memory 378668 kb
Host smart-0b37f0e8-a917-4b6f-b772-7df6ba893309
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8181650315877850080548491325064569744762337523649434429218517889801716275628 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.8181650315877850080548491325064569744762337523649434429218517889801716275628
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.15880121183995594582963746141282029343938481337945523626505652259950753403119
Short name T769
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.87 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:07:41 PM PST 23
Peak memory 245688 kb
Host smart-4e27c003-c83e-4bc1-bcd2-b88054a07212
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158801211839955945829637461412820293439384813379455236265056522599507
53403119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.1588012118399559458296374614128202934393848133794552362
6505652259950753403119
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.104374162890066184764856889487323050134984476502831978645826577925100163868538
Short name T642
Test name
Test status
Simulation time 45083829570 ps
CPU time 597.78 seconds
Started Nov 22 02:07:07 PM PST 23
Finished Nov 22 02:17:10 PM PST 23
Peak memory 202848 kb
Host smart-b0b40c67-9e19-4946-8c81-c156516832ef
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104374162890066184764856889487323050134984476502831978645826577925100
163868538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access_b2b.1043741628900661847648568894873230501349
84476502831978645826577925100163868538
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.71303009588920609749847813355830880482365359057078640167562394503485861667377
Short name T420
Test name
Test status
Simulation time 607542526 ps
CPU time 6.11 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:07:27 PM PST 23
Peak memory 202932 kb
Host smart-7b7cf9ea-761f-45c4-857e-0da46ea6111d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71303009588920609749847813355830880482365359057078640167562394503485861667377 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.71303009588920609749847813355830880482365359057078640167562394503485861667377
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.97581121378408147199760825372724387577701015050083311031617585739317200246662
Short name T709
Test name
Test status
Simulation time 19913691647 ps
CPU time 505.42 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:15:46 PM PST 23
Peak memory 372536 kb
Host smart-52476d60-d622-44e7-969b-f1c9290425f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97581121378408147199760825372724387577701015050083311031617585739317200246662 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.97581121378408147199760825372724387577701015050083311031617585739317200246662
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.78697229452657256874857329639802786284763244256602691738185079493550208149396
Short name T26
Test name
Test status
Simulation time 216402798 ps
CPU time 2.09 seconds
Started Nov 22 02:07:05 PM PST 23
Finished Nov 22 02:07:13 PM PST 23
Peak memory 221192 kb
Host smart-260d58d3-1fb4-41ee-85ad-585c7332c610
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7869722945265725687485732963980278628476324425660269173818507949355
0208149396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.786972294526572568748573296398027862847632442566026917381850
79493550208149396
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.35212588445775237340485611638125259500683250865409133677951932658538244423109
Short name T618
Test name
Test status
Simulation time 988289480 ps
CPU time 18.5 seconds
Started Nov 22 02:07:09 PM PST 23
Finished Nov 22 02:07:32 PM PST 23
Peak memory 245572 kb
Host smart-4a50ad9d-3799-49d5-88e7-a907a7979696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35212588445775237340485611638125259500683250865409133677951932658538244423109 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.35212588445775237340485611638125259500683250865409133677951932658538244423109
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.77013796694343981999319957735185713861208210660528262281324120117884276113829
Short name T265
Test name
Test status
Simulation time 624328106 ps
CPU time 2062.29 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:41:45 PM PST 23
Peak memory 498200 kb
Host smart-0b8fc772-26c6-4e11-9d70-4ec2bec2e48d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=77013796694343981999319957735185713861208210660528262281324120117884276113829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sra
m_ctrl_stress_all_with_rand_reset.77013796694343981999319957735185713861208210660528262281324120117884276113829
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.22034292843912522763281539341761366903346535258173443158484639204601466201200
Short name T431
Test name
Test status
Simulation time 9325508496 ps
CPU time 429.7 seconds
Started Nov 22 02:07:05 PM PST 23
Finished Nov 22 02:14:20 PM PST 23
Peak memory 202888 kb
Host smart-679ac201-25d4-4d00-af89-5f500af5ff2a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22034292843912522763281539341761366903346535258173443158484639204601466201200
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.2203429284391252276328153934176136690334653525817344
3158484639204601466201200
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.100283415645294570649960989799759482527753497564584561331194317385134333319344
Short name T302
Test name
Test status
Simulation time 1371125703 ps
CPU time 140.6 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:09:40 PM PST 23
Peak memory 351164 kb
Host smart-ff690b11-6c2a-4e7c-a585-20476cb407f0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100283415645294570649960989799759482527753497564584561
331194317385134333319344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.1002834156452945706499
60989799759482527753497564584561331194317385134333319344
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.78295387342906768555146807273939534448140297905591086790721603898014902142558
Short name T547
Test name
Test status
Simulation time 13467153934 ps
CPU time 992.29 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:24:14 PM PST 23
Peak memory 378684 kb
Host smart-8ef75a25-4b0f-4f2f-af5b-c9fb3e0b26b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78295387342906768555146807273939534448140297905591086790721603898014902142558
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during_key_req.782953873429067685551468072739395344481
40297905591086790721603898014902142558
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.1820972545689654327373802500370241730806403197402453894980984415998278993266
Short name T960
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 02:07:41 PM PST 23
Finished Nov 22 02:07:43 PM PST 23
Peak memory 202508 kb
Host smart-e70dd4cc-8027-4331-a189-f6e31ee79deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182097254568965432737380250037024173080640319740245389498098441599
8278993266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1820972545689654327373802500370241730806403197402453894
980984415998278993266
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.112540147403982170934804616840696440180986479954051139037849140966550252515330
Short name T786
Test name
Test status
Simulation time 295482808505 ps
CPU time 2761.62 seconds
Started Nov 22 02:07:39 PM PST 23
Finished Nov 22 02:53:43 PM PST 23
Peak memory 202892 kb
Host smart-2c21c9a4-cbf7-41c6-a057-6a913666dbe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112540147403982170934804616840696440180986479954051139037849140966550252515330 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.112540147403982170934804616840696440180986479954051139037849140966550252515330
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.34832647289644940590347170646353240339852442365227873862916705844602441463462
Short name T264
Test name
Test status
Simulation time 31712811539 ps
CPU time 1078.03 seconds
Started Nov 22 02:07:41 PM PST 23
Finished Nov 22 02:25:41 PM PST 23
Peak memory 368040 kb
Host smart-a5bdceda-fb00-4926-a492-f05fe471709b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34832647289644940590347170646353240339852442365227873862916705844602441463462 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.34832647289644940590347170646353240339852442365227873862916705844602441463462
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.71271543813604498035142155892459876421841699829735101919662650411071619323900
Short name T961
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.15 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:09:26 PM PST 23
Peak memory 210972 kb
Host smart-4154ece1-2245-491d-9cc5-a6c0fe1336d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71271543813604498035142155892459876421841699829735101919662650411071619323900 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.71271543813604498035142155892459876421841699829735101919662650411071619323900
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.43771713896864027706121533382090869642732018485116716499663955467260416473300
Short name T266
Test name
Test status
Simulation time 1342947357 ps
CPU time 138.89 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:10:01 PM PST 23
Peak memory 351192 kb
Host smart-7f7737b5-e83f-4b36-9185-813b460101a9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4377171389686402770612153338209086964273201848511671649
9663955467260416473300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_max_throughput.43771713896864027706121533382090869
642732018485116716499663955467260416473300
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.4160904248690155320319594872148471905637860784053621870117286229513688189543
Short name T824
Test name
Test status
Simulation time 4750777237 ps
CPU time 79 seconds
Started Nov 22 02:07:39 PM PST 23
Finished Nov 22 02:09:00 PM PST 23
Peak memory 212384 kb
Host smart-5449051b-3bf3-49e9-aa89-8ddf8a59ceed
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41609042486901553203195948721484719056378607840536218701172862295136
88189543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.4160904248690155320319594872148471905637860784053
621870117286229513688189543
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.81339386144484500615042459106474808209861276915293285803736733511154366447426
Short name T297
Test name
Test status
Simulation time 18445453393 ps
CPU time 149.15 seconds
Started Nov 22 02:07:41 PM PST 23
Finished Nov 22 02:10:12 PM PST 23
Peak memory 202692 kb
Host smart-4d4c1a3f-7cf6-4883-a2a8-9bac91331eef
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81339386144484500615042459106474808209861276915293285803736733511154366447426
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.81339386144484500615042459106474808209861276915293285803736733511154366447426
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.91335809470540223544602720429995434915865818290569560338340445349470177611934
Short name T461
Test name
Test status
Simulation time 28731174678 ps
CPU time 873.12 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 378644 kb
Host smart-24839a1c-c55f-482a-a171-e6a3e1249e20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91335809470540223544602720429995434915865818290569560338340445349470177611934 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.91335809470540223544602720429995434915865818290569560338340445349470177611934
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.99634353628997104058971577551266126392101418875864294040443601077326313091842
Short name T979
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.62 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:07:59 PM PST 23
Peak memory 245580 kb
Host smart-8d46fae2-7ab2-4069-b689-9da5c5aaabd4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996343536289971040589715775512661263921014188758642940404436010773263
13091842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.996343536289971040589715775512661263921014188758642940
40443601077326313091842
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.63296679439965636533613506908147783398482615268328693658994415675931057442810
Short name T444
Test name
Test status
Simulation time 45083829570 ps
CPU time 565.56 seconds
Started Nov 22 02:07:42 PM PST 23
Finished Nov 22 02:17:09 PM PST 23
Peak memory 202804 kb
Host smart-b72026cd-a3af-496d-a071-1140c864dd63
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632966794399656365336135069081477833984826152683286936589944156759310
57442810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access_b2b.6329667943996563653361350690814778339848
2615268328693658994415675931057442810
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.15272213846248682612675919931050794842408466057859747531741551438774463187812
Short name T962
Test name
Test status
Simulation time 607542526 ps
CPU time 6.2 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:07:48 PM PST 23
Peak memory 203108 kb
Host smart-e330d967-4fcb-45c6-944a-2e2cf316bbb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15272213846248682612675919931050794842408466057859747531741551438774463187812 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.15272213846248682612675919931050794842408466057859747531741551438774463187812
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.16698653681883382364484455777460293154610756022955893569678272473688855478200
Short name T567
Test name
Test status
Simulation time 19913691647 ps
CPU time 580.04 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:17:22 PM PST 23
Peak memory 372572 kb
Host smart-313c9b3d-0d3d-41d0-aa7e-4ed1971b81c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16698653681883382364484455777460293154610756022955893569678272473688855478200 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.16698653681883382364484455777460293154610756022955893569678272473688855478200
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.71569320930495032181545335246410134007879804239601298913866140691067188519629
Short name T740
Test name
Test status
Simulation time 988289480 ps
CPU time 17.74 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:07:56 PM PST 23
Peak memory 245712 kb
Host smart-a2f18040-256e-4403-bfdb-e8e6fef7ce81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71569320930495032181545335246410134007879804239601298913866140691067188519629 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.71569320930495032181545335246410134007879804239601298913866140691067188519629
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.104316390072420374319870056094060578487212257400203556131051070749802719512333
Short name T504
Test name
Test status
Simulation time 624328106 ps
CPU time 1816 seconds
Started Nov 22 02:07:42 PM PST 23
Finished Nov 22 02:38:00 PM PST 23
Peak memory 498168 kb
Host smart-47222ef3-834a-4772-9842-81d109b8d88a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=104316390072420374319870056094060578487212257400203556131051070749802719512333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.s
ram_ctrl_stress_all_with_rand_reset.104316390072420374319870056094060578487212257400203556131051070749802719512333
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.40294297540232927778334388078720640898489170566465282225649163523485045188870
Short name T941
Test name
Test status
Simulation time 9325508496 ps
CPU time 432.46 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:14:52 PM PST 23
Peak memory 202884 kb
Host smart-513e8cbe-31d1-4fa2-8a3e-f0727cf19c2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40294297540232927778334388078720640898489170566465282225649163523485045188870
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.402942975402329277783343880787206408984891705664652
82225649163523485045188870
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.40392266418090842235842311942105770636337364928449250026328923066919100074002
Short name T818
Test name
Test status
Simulation time 1371125703 ps
CPU time 102.99 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:09:24 PM PST 23
Peak memory 351180 kb
Host smart-d7efee2b-0f12-4be2-8670-e9f97960461f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403922664180908422358423119421057706363373649284492500
26328923066919100074002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.4039226641809084223584
2311942105770636337364928449250026328923066919100074002
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.15064598150323865400946681521429663685404510225230199012391889645535077252481
Short name T453
Test name
Test status
Simulation time 13467153934 ps
CPU time 877.8 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:25:55 PM PST 23
Peak memory 378764 kb
Host smart-396b0388-cb3a-48d3-8c9c-9dcb56499b8f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15064598150323865400946681521429663685404510225230199012391889645535077252481
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during_key_req.150645981503238654009466815214296636854
04510225230199012391889645535077252481
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.32640424409486980645006551611462358898402607264205560081660824745544184028014
Short name T839
Test name
Test status
Simulation time 16600825 ps
CPU time 0.66 seconds
Started Nov 22 02:11:17 PM PST 23
Finished Nov 22 02:11:18 PM PST 23
Peak memory 202548 kb
Host smart-43bc8ef3-a225-423e-82d9-1c9806e0bd2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326404244094869806450065516114623588984026072642055600816608247455
44184028014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.326404244094869806450065516114623588984026072642055600
81660824745544184028014
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.94567558145300147761921332221055391419187896041212940157421527266307624918430
Short name T575
Test name
Test status
Simulation time 295482808505 ps
CPU time 2641.11 seconds
Started Nov 22 02:07:39 PM PST 23
Finished Nov 22 02:51:43 PM PST 23
Peak memory 202752 kb
Host smart-15162206-f5b8-45e1-b485-294cff4f852c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94567558145300147761921332221055391419187896041212940157421527266307624918430 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.94567558145300147761921332221055391419187896041212940157421527266307624918430
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.91762344062453192387735312909807169704666147256268900994048456910235711475092
Short name T892
Test name
Test status
Simulation time 31712811539 ps
CPU time 833.06 seconds
Started Nov 22 02:11:15 PM PST 23
Finished Nov 22 02:25:09 PM PST 23
Peak memory 368012 kb
Host smart-51bea129-992e-48e4-a25f-53b062529bff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91762344062453192387735312909807169704666147256268900994048456910235711475092 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.91762344062453192387735312909807169704666147256268900994048456910235711475092
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.36730963147197501108298017079648655583959453028983281362662620015478363287176
Short name T736
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.47 seconds
Started Nov 22 02:11:15 PM PST 23
Finished Nov 22 02:13:02 PM PST 23
Peak memory 211092 kb
Host smart-cb419517-e171-4724-80ce-9e6bf1160092
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36730963147197501108298017079648655583959453028983281362662620015478363287176 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.36730963147197501108298017079648655583959453028983281362662620015478363287176
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.47278336623854218803103932032245833077827419352509502963244915226424927636641
Short name T899
Test name
Test status
Simulation time 1342947357 ps
CPU time 122.93 seconds
Started Nov 22 02:07:41 PM PST 23
Finished Nov 22 02:09:46 PM PST 23
Peak memory 351116 kb
Host smart-05bfe144-9237-466d-9c0c-7c40277e348f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4727833662385421880310393203224583307782741935250950296
3244915226424927636641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_max_throughput.47278336623854218803103932032245833
077827419352509502963244915226424927636641
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.48739311568081635918883939726971405210993705835650790358163928921537980401455
Short name T693
Test name
Test status
Simulation time 4750777237 ps
CPU time 76.8 seconds
Started Nov 22 02:11:15 PM PST 23
Finished Nov 22 02:12:33 PM PST 23
Peak memory 212224 kb
Host smart-6ad489c9-0e28-43fb-8bbc-f8ff51dcc97e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48739311568081635918883939726971405210993705835650790358163928921537
980401455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.487393115680816359188839397269714052109937058356
50790358163928921537980401455
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.113358069922254369363955964460283425350072815025673393060721049060599403786989
Short name T524
Test name
Test status
Simulation time 18445453393 ps
CPU time 166.09 seconds
Started Nov 22 02:11:17 PM PST 23
Finished Nov 22 02:14:04 PM PST 23
Peak memory 202736 kb
Host smart-c98e6cdb-411e-4399-a68e-689f43f689b9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113358069922254369363955964460283425350072815025673393060721049060599403786989
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.113358069922254369363955964460283425350072815025673393060721049060599403786989
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.43896697481078286182682952405436287265275354564270390027421694540038451932702
Short name T766
Test name
Test status
Simulation time 28731174678 ps
CPU time 933.69 seconds
Started Nov 22 02:07:43 PM PST 23
Finished Nov 22 02:23:18 PM PST 23
Peak memory 378780 kb
Host smart-e4c72e65-ed48-4d7a-bf42-e5d96c260b5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43896697481078286182682952405436287265275354564270390027421694540038451932702 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.43896697481078286182682952405436287265275354564270390027421694540038451932702
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.76563944905194740929275334525420659083036828293580270629282502547220811481142
Short name T579
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.03 seconds
Started Nov 22 02:07:43 PM PST 23
Finished Nov 22 02:08:03 PM PST 23
Peak memory 245728 kb
Host smart-d4f58943-977f-4ed4-b04b-86fee3de7b80
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765639449051947409292753345254206590830368282935802706292825025472208
11481142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.765639449051947409292753345254206590830368282935802706
29282502547220811481142
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.75699531533517815694557142712618720028796750296971168060537553846463846190945
Short name T239
Test name
Test status
Simulation time 45083829570 ps
CPU time 559.53 seconds
Started Nov 22 02:07:41 PM PST 23
Finished Nov 22 02:17:03 PM PST 23
Peak memory 202776 kb
Host smart-c939a93c-7c4f-424e-9da3-e95c731b04d7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756995315335178156945571427126187200287967502969711680605375538464638
46190945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access_b2b.7569953153351781569455714271261872002879
6750296971168060537553846463846190945
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.91756484503571847540499783965559176708292495216170506896176136247052672672748
Short name T355
Test name
Test status
Simulation time 607542526 ps
CPU time 6.18 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:11:23 PM PST 23
Peak memory 203124 kb
Host smart-2421839b-860b-49f3-b371-515ad9b97935
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91756484503571847540499783965559176708292495216170506896176136247052672672748 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.91756484503571847540499783965559176708292495216170506896176136247052672672748
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.89670178055763676321883738736013322575073595869931205174563048315926115777305
Short name T540
Test name
Test status
Simulation time 988289480 ps
CPU time 18.5 seconds
Started Nov 22 02:07:43 PM PST 23
Finished Nov 22 02:08:03 PM PST 23
Peak memory 245800 kb
Host smart-b1787039-fa2a-4fb2-b039-17207db2a706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89670178055763676321883738736013322575073595869931205174563048315926115777305 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.89670178055763676321883738736013322575073595869931205174563048315926115777305
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.92297796798872436447988990897439193602217678520393545007065640586490984709178
Short name T526
Test name
Test status
Simulation time 624328106 ps
CPU time 1660.3 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:38:57 PM PST 23
Peak memory 498228 kb
Host smart-9bbf62fa-bc0b-4bea-992a-18b53cba07cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=92297796798872436447988990897439193602217678520393545007065640586490984709178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sr
am_ctrl_stress_all_with_rand_reset.92297796798872436447988990897439193602217678520393545007065640586490984709178
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.94566916753977620486751088543293061761623474882021004564755636678424417796482
Short name T100
Test name
Test status
Simulation time 9325508496 ps
CPU time 404.82 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:14:25 PM PST 23
Peak memory 202792 kb
Host smart-52b16d73-648c-4a28-81f6-5b5f7754d28d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94566916753977620486751088543293061761623474882021004564755636678424417796482
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.945669167539776204867510885432930617616234748820210
04564755636678424417796482
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.15357777738368425574205823354918225420530640919349964141062309412898199612414
Short name T457
Test name
Test status
Simulation time 1371125703 ps
CPU time 88.27 seconds
Started Nov 22 02:07:43 PM PST 23
Finished Nov 22 02:09:12 PM PST 23
Peak memory 351152 kb
Host smart-50e72089-3a99-41d9-b58a-828cc736b8f7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153577777383684255742058233549182254205306409193499641
41062309412898199612414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.1535777773836842557420
5823354918225420530640919349964141062309412898199612414
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.53733283498830787486025502382808433428899308982172073489090483063763278401557
Short name T277
Test name
Test status
Simulation time 13467153934 ps
CPU time 1110.89 seconds
Started Nov 22 02:11:15 PM PST 23
Finished Nov 22 02:29:46 PM PST 23
Peak memory 378620 kb
Host smart-b3553516-707b-4ab9-9cd7-29bc91bcde79
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53733283498830787486025502382808433428899308982172073489090483063763278401557
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during_key_req.537332834988307874860255023828084334288
99308982172073489090483063763278401557
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.38271302603396034366809515719586621176667138255285263420609053421516432641676
Short name T777
Test name
Test status
Simulation time 295482808505 ps
CPU time 2780.56 seconds
Started Nov 22 02:11:17 PM PST 23
Finished Nov 22 02:57:38 PM PST 23
Peak memory 202848 kb
Host smart-f41d492d-bdd7-4113-b2eb-8724dfb2cf54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38271302603396034366809515719586621176667138255285263420609053421516432641676 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.38271302603396034366809515719586621176667138255285263420609053421516432641676
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.83015794451167867588709093090640235422253462632805005603733453815401402350110
Short name T873
Test name
Test status
Simulation time 31712811539 ps
CPU time 946.91 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:27:04 PM PST 23
Peak memory 368024 kb
Host smart-848c9145-fa37-495c-a0a6-fc9e92db5a98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83015794451167867588709093090640235422253462632805005603733453815401402350110 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.83015794451167867588709093090640235422253462632805005603733453815401402350110
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.74338491368089705711872487970685067245104056722746905801017157361546868493884
Short name T323
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.36 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:13:02 PM PST 23
Peak memory 211000 kb
Host smart-399ed7a6-5051-48c7-8682-1eeae9cf41e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74338491368089705711872487970685067245104056722746905801017157361546868493884 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.74338491368089705711872487970685067245104056722746905801017157361546868493884
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.43597377986235563365978746760352656878702233502104176505929010581465922619105
Short name T949
Test name
Test status
Simulation time 1342947357 ps
CPU time 122.95 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:13:20 PM PST 23
Peak memory 351116 kb
Host smart-39b7ed43-29a2-4d5e-aaf6-8f4ab0ca1356
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4359737798623556336597874676035265687870223350210417650
5929010581465922619105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_max_throughput.43597377986235563365978746760352656
878702233502104176505929010581465922619105
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.12226508748301500209453661144212639577679328058200360924964044299823446630897
Short name T82
Test name
Test status
Simulation time 4750777237 ps
CPU time 82.12 seconds
Started Nov 22 02:11:19 PM PST 23
Finished Nov 22 02:12:42 PM PST 23
Peak memory 212324 kb
Host smart-b444f89f-eac5-43de-9d00-861bcfdb1569
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12226508748301500209453661144212639577679328058200360924964044299823
446630897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.122265087483015002094536611442126395776793280582
00360924964044299823446630897
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.28995607836990060929882415920185932759342231074593301268868015625814081997186
Short name T827
Test name
Test status
Simulation time 18445453393 ps
CPU time 161.41 seconds
Started Nov 22 02:11:18 PM PST 23
Finished Nov 22 02:14:01 PM PST 23
Peak memory 202752 kb
Host smart-936aa808-66ee-44cb-a0bb-3538bb4549b1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28995607836990060929882415920185932759342231074593301268868015625814081997186
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.28995607836990060929882415920185932759342231074593301268868015625814081997186
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.105696714819742047455206491526535702242324760008479903843416420134348809806531
Short name T958
Test name
Test status
Simulation time 28731174678 ps
CPU time 841.28 seconds
Started Nov 22 02:11:18 PM PST 23
Finished Nov 22 02:25:21 PM PST 23
Peak memory 378636 kb
Host smart-a199905e-aa70-4cda-8584-2c8e5c663d9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105696714819742047455206491526535702242324760008479903843416420134348809806531 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.105696714819742047455206491526535702242324760008479903843416420134348809806531
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.105701769554508972811302893890140640360659578095479158445788335264184982906558
Short name T367
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.5 seconds
Started Nov 22 02:11:17 PM PST 23
Finished Nov 22 02:11:35 PM PST 23
Peak memory 245696 kb
Host smart-cc1f504c-8c55-480b-809d-aa3fbeda4e1a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105701769554508972811302893890140640360659578095479158445788335264184
982906558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.10570176955450897281130289389014064036065957809547915
8445788335264184982906558
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.69554273526720662201186459108129187826069792599572390099958323126213747235898
Short name T261
Test name
Test status
Simulation time 45083829570 ps
CPU time 562.51 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:20:39 PM PST 23
Peak memory 202868 kb
Host smart-43fadf6d-6d25-4e22-9b6f-8485112eefa6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695542735267206622011864591081291878260697925995723900999583231262137
47235898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access_b2b.6955427352672066220118645910812918782606
9792599572390099958323126213747235898
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.20677156860764593241515162828403708772549167171071784448811513240977509705819
Short name T854
Test name
Test status
Simulation time 607542526 ps
CPU time 6.19 seconds
Started Nov 22 02:11:19 PM PST 23
Finished Nov 22 02:11:26 PM PST 23
Peak memory 203120 kb
Host smart-5e2a9d07-6372-498a-b2b8-dc770e98fe91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20677156860764593241515162828403708772549167171071784448811513240977509705819 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.20677156860764593241515162828403708772549167171071784448811513240977509705819
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.19552600604423705769363906076205344330139576503023217734457442480624266275066
Short name T398
Test name
Test status
Simulation time 19913691647 ps
CPU time 578.43 seconds
Started Nov 22 02:11:18 PM PST 23
Finished Nov 22 02:20:57 PM PST 23
Peak memory 372508 kb
Host smart-f331b2d2-8911-4e17-bbd7-3bff89fa0ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19552600604423705769363906076205344330139576503023217734457442480624266275066 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.19552600604423705769363906076205344330139576503023217734457442480624266275066
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.100730811282970285803723010683339137397127523689577803644912050872074606985742
Short name T669
Test name
Test status
Simulation time 988289480 ps
CPU time 18.2 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:11:35 PM PST 23
Peak memory 245668 kb
Host smart-66e0d620-b538-40ba-ae7f-fac1d12652b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100730811282970285803723010683339137397127523689577803644912050872074606985742 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.100730811282970285803723010683339137397127523689577803644912050872074606985742
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.92108622493368827305875768906779651274836009463198247923116920920583327395969
Short name T701
Test name
Test status
Simulation time 624328106 ps
CPU time 1711.34 seconds
Started Nov 22 02:11:19 PM PST 23
Finished Nov 22 02:39:51 PM PST 23
Peak memory 498180 kb
Host smart-13c6190a-aea8-4296-938a-517b416f6ea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=92108622493368827305875768906779651274836009463198247923116920920583327395969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sr
am_ctrl_stress_all_with_rand_reset.92108622493368827305875768906779651274836009463198247923116920920583327395969
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.63876671114010302730337387881594155563683167269132519333392668586837317898956
Short name T507
Test name
Test status
Simulation time 9325508496 ps
CPU time 423.36 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:18:21 PM PST 23
Peak memory 202892 kb
Host smart-dce242dc-033b-41fc-869f-47b7b76cf3d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63876671114010302730337387881594155563683167269132519333392668586837317898956
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.638766711140103027303373878815941555636831672691325
19333392668586837317898956
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.84312528736275254052644743390534747583914399559551967657171303983581492166889
Short name T253
Test name
Test status
Simulation time 1371125703 ps
CPU time 139.74 seconds
Started Nov 22 02:11:16 PM PST 23
Finished Nov 22 02:13:36 PM PST 23
Peak memory 351192 kb
Host smart-571c4df7-5de6-4103-8613-8a9f8db07c6b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843125287362752540526447433905347475839143995595519676
57171303983581492166889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.8431252873627525405264
4743390534747583914399559551967657171303983581492166889
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2844877470588187446826195650948634644537087236657359783773763851723142929450
Short name T905
Test name
Test status
Simulation time 13467153934 ps
CPU time 1078.63 seconds
Started Nov 22 02:11:19 PM PST 23
Finished Nov 22 02:29:19 PM PST 23
Peak memory 380816 kb
Host smart-bcb14f0b-638d-49a4-b1f9-796df7290090
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844877470588187446826195650948634644537087236657359783773763851723142929450
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during_key_req.2844877470588187446826195650948634644537
087236657359783773763851723142929450
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.62061697479568573998675581668803202481556467315997405760843130387615448053772
Short name T715
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:11:28 PM PST 23
Peak memory 202492 kb
Host smart-c87bb198-c04c-4806-9378-480cab86833b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620616974795685739986755816688032024815564673159974057608431303876
15448053772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.620616974795685739986755816688032024815564673159974057
60843130387615448053772
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.105850257911630294257978996856118816467388809929004131464673923308190818501448
Short name T822
Test name
Test status
Simulation time 295482808505 ps
CPU time 2791.21 seconds
Started Nov 22 02:11:20 PM PST 23
Finished Nov 22 02:57:52 PM PST 23
Peak memory 202872 kb
Host smart-a31affec-4dab-479b-8635-253a89379026
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105850257911630294257978996856118816467388809929004131464673923308190818501448 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.105850257911630294257978996856118816467388809929004131464673923308190818501448
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.114588513386423180282663990401324484932130176186593739206631566854726767328374
Short name T585
Test name
Test status
Simulation time 31712811539 ps
CPU time 859.74 seconds
Started Nov 22 02:11:20 PM PST 23
Finished Nov 22 02:25:40 PM PST 23
Peak memory 368024 kb
Host smart-096bdd52-0b4d-4c8b-a216-441446c8282c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114588513386423180282663990401324484932130176186593739206631566854726767328374 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.114588513386423180282663990401324484932130176186593739206631566854726767328374
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.959393740518167349986682417246064638396913996905356991609730491421872786966
Short name T841
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.82 seconds
Started Nov 22 02:11:19 PM PST 23
Finished Nov 22 02:13:05 PM PST 23
Peak memory 211072 kb
Host smart-afac9b60-40ae-436f-8d30-b03a06475265
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959393740518167349986682417246064638396913996905356991609730491421872786966 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.959393740518167349986682417246064638396913996905356991609730491421872786966
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.8561102205623849734430862651063193566483682170986383036830440878285300564020
Short name T520
Test name
Test status
Simulation time 1342947357 ps
CPU time 103.07 seconds
Started Nov 22 02:11:17 PM PST 23
Finished Nov 22 02:13:01 PM PST 23
Peak memory 351180 kb
Host smart-40221c35-80a7-4734-aceb-0f1b5eccc813
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8561102205623849734430862651063193566483682170986383036
830440878285300564020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_max_throughput.856110220562384973443086265106319356
6483682170986383036830440878285300564020
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.30760328185372152549276691211379360483698900858485034006656096565675124734666
Short name T499
Test name
Test status
Simulation time 4750777237 ps
CPU time 79.82 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:12:48 PM PST 23
Peak memory 212280 kb
Host smart-93040b4f-9796-4923-b6ef-edad349cdc16
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30760328185372152549276691211379360483698900858485034006656096565675
124734666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.307603281853721525492766912113793604836989008584
85034006656096565675124734666
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.30844947952459994631288897081406390401224017586433604765099190825509177764532
Short name T108
Test name
Test status
Simulation time 18445453393 ps
CPU time 156.06 seconds
Started Nov 22 02:11:19 PM PST 23
Finished Nov 22 02:13:55 PM PST 23
Peak memory 202800 kb
Host smart-943541b2-a0a8-4eef-8efa-f4f12432fc6c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30844947952459994631288897081406390401224017586433604765099190825509177764532
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.30844947952459994631288897081406390401224017586433604765099190825509177764532
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.88022087401299231351383463833886266496995032986173285310131440233697631540376
Short name T311
Test name
Test status
Simulation time 28731174678 ps
CPU time 880 seconds
Started Nov 22 02:11:20 PM PST 23
Finished Nov 22 02:26:01 PM PST 23
Peak memory 378664 kb
Host smart-032364ae-95be-4418-baef-2893828da68e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88022087401299231351383463833886266496995032986173285310131440233697631540376 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.88022087401299231351383463833886266496995032986173285310131440233697631540376
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.28461579224738705352674596998513206741238143194549823397491555328506906757846
Short name T113
Test name
Test status
Simulation time 1006378621 ps
CPU time 16.72 seconds
Started Nov 22 02:11:20 PM PST 23
Finished Nov 22 02:11:38 PM PST 23
Peak memory 245680 kb
Host smart-76ec388c-0b1c-46f8-ad6a-de7e4ac65b22
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284615792247387053526745969985132067412381431945498233974915553285069
06757846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.284615792247387053526745969985132067412381431945498233
97491555328506906757846
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.22665604742996489002441929973296033405497085532902709442354661475882292943423
Short name T698
Test name
Test status
Simulation time 45083829570 ps
CPU time 562.92 seconds
Started Nov 22 02:11:20 PM PST 23
Finished Nov 22 02:20:44 PM PST 23
Peak memory 202880 kb
Host smart-529a1a24-c4e0-443e-9916-c06c9050d8b9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226656047429964890024419299732960334054970855329027094423546614758822
92943423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access_b2b.2266560474299648900244192997329603340549
7085532902709442354661475882292943423
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.112083371973444327469369795819130300718428078055563065779913247696120457433235
Short name T303
Test name
Test status
Simulation time 607542526 ps
CPU time 6.14 seconds
Started Nov 22 02:11:19 PM PST 23
Finished Nov 22 02:11:26 PM PST 23
Peak memory 203080 kb
Host smart-e4e4c0d1-f424-4e15-a15c-4a9212746207
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112083371973444327469369795819130300718428078055563065779913247696120457433235 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.112083371973444327469369795819130300718428078055563065779913247696120457433235
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.32420283149322171653664428401156253841442633912899655379807728212429412885575
Short name T542
Test name
Test status
Simulation time 19913691647 ps
CPU time 535.97 seconds
Started Nov 22 02:11:19 PM PST 23
Finished Nov 22 02:20:16 PM PST 23
Peak memory 372508 kb
Host smart-9182bc79-a499-4c93-b365-b86d9b970277
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32420283149322171653664428401156253841442633912899655379807728212429412885575 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.32420283149322171653664428401156253841442633912899655379807728212429412885575
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.27254529455110058827891803311150852312365404008806724003663392767044543673677
Short name T710
Test name
Test status
Simulation time 988289480 ps
CPU time 17.46 seconds
Started Nov 22 02:11:20 PM PST 23
Finished Nov 22 02:11:39 PM PST 23
Peak memory 245664 kb
Host smart-0137334c-b5aa-4554-89b7-0258791d337e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27254529455110058827891803311150852312365404008806724003663392767044543673677 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.27254529455110058827891803311150852312365404008806724003663392767044543673677
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.31342624169660234699404031988278376526797938287381949410500125641462656151324
Short name T817
Test name
Test status
Simulation time 624328106 ps
CPU time 2226.39 seconds
Started Nov 22 02:11:28 PM PST 23
Finished Nov 22 02:48:36 PM PST 23
Peak memory 498160 kb
Host smart-bac4eb28-3788-4a7c-b9b7-b2665a51babf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=31342624169660234699404031988278376526797938287381949410500125641462656151324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sr
am_ctrl_stress_all_with_rand_reset.31342624169660234699404031988278376526797938287381949410500125641462656151324
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.86214541454427303232245346088711491481490857056308436524626036899990263371124
Short name T473
Test name
Test status
Simulation time 9325508496 ps
CPU time 407.23 seconds
Started Nov 22 02:11:17 PM PST 23
Finished Nov 22 02:18:05 PM PST 23
Peak memory 202928 kb
Host smart-7b32563d-1d91-4e8a-9dbc-1e9b3d15fa2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86214541454427303232245346088711491481490857056308436524626036899990263371124
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.862145414544273032322453460887114914814908570563084
36524626036899990263371124
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.44474049413164534375309748170518876753380902437104481328726623802635602346310
Short name T450
Test name
Test status
Simulation time 1371125703 ps
CPU time 107.78 seconds
Started Nov 22 02:11:17 PM PST 23
Finished Nov 22 02:13:06 PM PST 23
Peak memory 351224 kb
Host smart-54daed7f-2054-4589-9d2e-3bc9047b1fb4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444740494131645343753097481705188767533809024371044813
28726623802635602346310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.4447404941316453437530
9748170518876753380902437104481328726623802635602346310
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.24750137753452791108876723449910718521509640937749735735933932507808718421555
Short name T430
Test name
Test status
Simulation time 13467153934 ps
CPU time 993.75 seconds
Started Nov 22 02:11:26 PM PST 23
Finished Nov 22 02:28:01 PM PST 23
Peak memory 378784 kb
Host smart-fe7c2148-f5fc-4be0-86cc-904c073db25c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24750137753452791108876723449910718521509640937749735735933932507808718421555
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during_key_req.247501377534527911088767234499107185215
09640937749735735933932507808718421555
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.1915489783793400716692169033799684492363125029078432516116676430539684594837
Short name T433
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:11:35 PM PST 23
Finished Nov 22 02:11:36 PM PST 23
Peak memory 202552 kb
Host smart-128fc9b8-a14f-4abf-8dc7-4342fbfaeed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191548978379340071669216903379968449236312502907843251611667643053
9684594837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.1915489783793400716692169033799684492363125029078432516
116676430539684594837
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.27190003799475646944026550181515978595733625867127159765446004143860381435956
Short name T247
Test name
Test status
Simulation time 295482808505 ps
CPU time 2689.02 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:56:17 PM PST 23
Peak memory 202888 kb
Host smart-24db0e7b-f2e4-4d0b-82a0-55e489f1e334
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27190003799475646944026550181515978595733625867127159765446004143860381435956 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.27190003799475646944026550181515978595733625867127159765446004143860381435956
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.98174202291538497887943670299603644215706276643363576592987634837458190485433
Short name T477
Test name
Test status
Simulation time 31712811539 ps
CPU time 849.3 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:25:37 PM PST 23
Peak memory 368016 kb
Host smart-94f06902-8ad6-4293-a9ca-9ece683ffe9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98174202291538497887943670299603644215706276643363576592987634837458190485433 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.98174202291538497887943670299603644215706276643363576592987634837458190485433
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.4590356316745180477694680870202857654060134108769071485927132325883624928166
Short name T600
Test name
Test status
Simulation time 19084394710 ps
CPU time 103.98 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:13:12 PM PST 23
Peak memory 211064 kb
Host smart-3b77746c-c03e-460a-a829-ce69a54f5d83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4590356316745180477694680870202857654060134108769071485927132325883624928166 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.4590356316745180477694680870202857654060134108769071485927132325883624928166
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.2004531777933684782330822211369183975811376453689667297314477522701219094616
Short name T551
Test name
Test status
Simulation time 1342947357 ps
CPU time 122.23 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:13:30 PM PST 23
Peak memory 351184 kb
Host smart-eaec4298-2ba2-482c-8021-2abbd8035118
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004531777933684782330822211369183975811376453689667297
314477522701219094616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_max_throughput.200453177793368478233082221136918397
5811376453689667297314477522701219094616
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.34211557462938058434430518627321214791614921312145638757692416892602272558919
Short name T280
Test name
Test status
Simulation time 4750777237 ps
CPU time 77.18 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:12:45 PM PST 23
Peak memory 212380 kb
Host smart-b3eeeda9-59fd-4e82-8d43-54ac9bb21a7f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34211557462938058434430518627321214791614921312145638757692416892602
272558919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.342115574629380584344305186273212147916149213121
45638757692416892602272558919
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.85594607609585756532817463135867865698206937735636466325099038280413098099189
Short name T832
Test name
Test status
Simulation time 18445453393 ps
CPU time 165.01 seconds
Started Nov 22 02:11:26 PM PST 23
Finished Nov 22 02:14:12 PM PST 23
Peak memory 202676 kb
Host smart-5ddd6f2a-98f9-420d-a8d6-d05fbcfdd043
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85594607609585756532817463135867865698206937735636466325099038280413098099189
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.85594607609585756532817463135867865698206937735636466325099038280413098099189
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.8258077801808688950884783394947505629723756203087515965163361309687563413301
Short name T964
Test name
Test status
Simulation time 28731174678 ps
CPU time 744.51 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:23:52 PM PST 23
Peak memory 378592 kb
Host smart-913d1abf-6190-45f7-878b-ef23e1a248c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8258077801808688950884783394947505629723756203087515965163361309687563413301 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.8258077801808688950884783394947505629723756203087515965163361309687563413301
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.53199036150544922024386070323716599472574357562983982570180713656799238482650
Short name T670
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.61 seconds
Started Nov 22 02:11:28 PM PST 23
Finished Nov 22 02:11:47 PM PST 23
Peak memory 245652 kb
Host smart-3200ed8f-6e2d-40e8-9a29-d7b83804cb71
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531990361505449220243860703237165994725743575629839825701807136567992
38482650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.531990361505449220243860703237165994725743575629839825
70180713656799238482650
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.26496178508254375919362205388428167330100119551467552649598426807186071806281
Short name T411
Test name
Test status
Simulation time 45083829570 ps
CPU time 561.74 seconds
Started Nov 22 02:11:28 PM PST 23
Finished Nov 22 02:20:50 PM PST 23
Peak memory 202756 kb
Host smart-20ca3367-b846-42d1-8d52-4ba68201579f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264961785082543759193622053884281673301001195514675526495984268071860
71806281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access_b2b.2649617850825437591936220538842816733010
0119551467552649598426807186071806281
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.45378232298444185736789048206659088647356037758691092321248127701740825462261
Short name T404
Test name
Test status
Simulation time 607542526 ps
CPU time 6.03 seconds
Started Nov 22 02:11:28 PM PST 23
Finished Nov 22 02:11:35 PM PST 23
Peak memory 202988 kb
Host smart-18296356-b4ee-40a1-9aa3-4eec91e2a2fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45378232298444185736789048206659088647356037758691092321248127701740825462261 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.45378232298444185736789048206659088647356037758691092321248127701740825462261
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.35510907709521384062067732414387727522505459133560525432189440763208088507929
Short name T557
Test name
Test status
Simulation time 19913691647 ps
CPU time 571.92 seconds
Started Nov 22 02:11:28 PM PST 23
Finished Nov 22 02:21:01 PM PST 23
Peak memory 372456 kb
Host smart-617c52b2-7965-4d9f-a812-4bcf9c78f12a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35510907709521384062067732414387727522505459133560525432189440763208088507929 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.35510907709521384062067732414387727522505459133560525432189440763208088507929
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.113068490126761410536147742537300776189101558477613973987858697311715102417109
Short name T306
Test name
Test status
Simulation time 988289480 ps
CPU time 17.18 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:11:45 PM PST 23
Peak memory 245620 kb
Host smart-6ef01bee-3c6f-4e2a-b9ad-e15ebbd3651e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113068490126761410536147742537300776189101558477613973987858697311715102417109 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.113068490126761410536147742537300776189101558477613973987858697311715102417109
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.7513280565685746618685806259552349153634068672198503890950758988337329467749
Short name T744
Test name
Test status
Simulation time 624328106 ps
CPU time 1851.83 seconds
Started Nov 22 02:11:35 PM PST 23
Finished Nov 22 02:42:27 PM PST 23
Peak memory 498028 kb
Host smart-df1ced22-6738-4e44-ace2-fd2148c1d01e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=7513280565685746618685806259552349153634068672198503890950758988337329467749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sra
m_ctrl_stress_all_with_rand_reset.7513280565685746618685806259552349153634068672198503890950758988337329467749
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.84780865084192019883012583638088589753961438307488715880844004994238214197599
Short name T593
Test name
Test status
Simulation time 9325508496 ps
CPU time 417.72 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:18:25 PM PST 23
Peak memory 202952 kb
Host smart-771d2be6-d428-4e63-a42a-6abc15cedc8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84780865084192019883012583638088589753961438307488715880844004994238214197599
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.847808650841920198830125836380885897539614383074887
15880844004994238214197599
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.75545058730503344163066596134556164355251182179712674697812385207382092657156
Short name T634
Test name
Test status
Simulation time 1371125703 ps
CPU time 121 seconds
Started Nov 22 02:11:27 PM PST 23
Finished Nov 22 02:13:29 PM PST 23
Peak memory 351208 kb
Host smart-eb87d38e-e316-450d-9b5e-861fb6e94afc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755450587305033441630665961345561643552511821797126746
97812385207382092657156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.7554505873050334416306
6596134556164355251182179712674697812385207382092657156
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.35931381824593632987218291788601368603651147543303112936294855406474494104839
Short name T281
Test name
Test status
Simulation time 13467153934 ps
CPU time 1020.88 seconds
Started Nov 22 02:11:39 PM PST 23
Finished Nov 22 02:28:41 PM PST 23
Peak memory 378816 kb
Host smart-ef9264cb-ccf7-44a6-a980-6dc7cb85a6ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35931381824593632987218291788601368603651147543303112936294855406474494104839
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during_key_req.359313818245936329872182917886013686036
51147543303112936294855406474494104839
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.79409834359400708856301331718826916284550458155548313841277356195378814287124
Short name T491
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:11:41 PM PST 23
Finished Nov 22 02:11:42 PM PST 23
Peak memory 202592 kb
Host smart-34eeef84-6979-4ac8-a4a1-3e76c4757456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794098343594007088563013317188269162845504581555483138412773561953
78814287124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.794098343594007088563013317188269162845504581555483138
41277356195378814287124
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.112741635325622324396781206335183698697059929475066152909083205781327638719505
Short name T930
Test name
Test status
Simulation time 295482808505 ps
CPU time 2740.6 seconds
Started Nov 22 02:11:36 PM PST 23
Finished Nov 22 02:57:17 PM PST 23
Peak memory 202828 kb
Host smart-aebe091c-cef5-4a9c-adb6-d3752afbc49b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112741635325622324396781206335183698697059929475066152909083205781327638719505 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.112741635325622324396781206335183698697059929475066152909083205781327638719505
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.20650826174749108037045927234475721218462542612567838400679320898728145701125
Short name T776
Test name
Test status
Simulation time 31712811539 ps
CPU time 922.12 seconds
Started Nov 22 02:11:40 PM PST 23
Finished Nov 22 02:27:03 PM PST 23
Peak memory 368048 kb
Host smart-cb004033-9a64-4bcf-a97e-5fe0a5a15aae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20650826174749108037045927234475721218462542612567838400679320898728145701125 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.20650826174749108037045927234475721218462542612567838400679320898728145701125
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.29873461971224156052629564868349722822614900877385018048097453918016809391452
Short name T683
Test name
Test status
Simulation time 19084394710 ps
CPU time 106.11 seconds
Started Nov 22 02:11:35 PM PST 23
Finished Nov 22 02:13:22 PM PST 23
Peak memory 211028 kb
Host smart-0067055f-bd6f-4aef-aca6-54e9e7b7963d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29873461971224156052629564868349722822614900877385018048097453918016809391452 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.29873461971224156052629564868349722822614900877385018048097453918016809391452
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.91815639230652012147950171340733554280345364917193907975442893243623729249744
Short name T833
Test name
Test status
Simulation time 1342947357 ps
CPU time 123.52 seconds
Started Nov 22 02:11:36 PM PST 23
Finished Nov 22 02:13:40 PM PST 23
Peak memory 351120 kb
Host smart-e894b8a4-7260-4a86-8e29-19241e175f38
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9181563923065201214795017134073355428034536491719390797
5442893243623729249744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_max_throughput.91815639230652012147950171340733554
280345364917193907975442893243623729249744
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.101849600205718104502918889709366997979571189422636223350125682782910747219638
Short name T472
Test name
Test status
Simulation time 4750777237 ps
CPU time 81.8 seconds
Started Nov 22 02:11:40 PM PST 23
Finished Nov 22 02:13:02 PM PST 23
Peak memory 212260 kb
Host smart-a5a95853-750d-4c5d-b4b1-cabe60019697
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10184960020571810450291888970936699797957118942263622335012568278291
0747219638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.10184960020571810450291888970936699797957118942
2636223350125682782910747219638
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.89834793035270434199439988891336707288553484626333531249577939183077802449146
Short name T375
Test name
Test status
Simulation time 18445453393 ps
CPU time 157.66 seconds
Started Nov 22 02:11:40 PM PST 23
Finished Nov 22 02:14:18 PM PST 23
Peak memory 202768 kb
Host smart-63fff4d6-19d2-4512-a271-74100e5fb2ff
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89834793035270434199439988891336707288553484626333531249577939183077802449146
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.89834793035270434199439988891336707288553484626333531249577939183077802449146
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.91644436968765977810162317123932864212795042318296104118281105537988194613956
Short name T980
Test name
Test status
Simulation time 28731174678 ps
CPU time 806.68 seconds
Started Nov 22 02:11:35 PM PST 23
Finished Nov 22 02:25:02 PM PST 23
Peak memory 378708 kb
Host smart-96dd1fb8-9016-4bfa-9857-3a0c99e0afcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91644436968765977810162317123932864212795042318296104118281105537988194613956 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.91644436968765977810162317123932864212795042318296104118281105537988194613956
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.16048700891261296252435459057837590215068110745754615072415250479891434602158
Short name T770
Test name
Test status
Simulation time 1006378621 ps
CPU time 16.58 seconds
Started Nov 22 02:11:35 PM PST 23
Finished Nov 22 02:11:52 PM PST 23
Peak memory 245728 kb
Host smart-14b34586-d375-4837-8b6c-5edc3f37bf13
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160487008912612962524354590578375902150681107457546150724152504798914
34602158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.160487008912612962524354590578375902150681107457546150
72415250479891434602158
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.5706782459546526096897190274077471077833478831086848447494360801591444830491
Short name T573
Test name
Test status
Simulation time 45083829570 ps
CPU time 582.19 seconds
Started Nov 22 02:11:34 PM PST 23
Finished Nov 22 02:21:17 PM PST 23
Peak memory 202708 kb
Host smart-e07df4cc-45d7-48c9-a1ff-f63d48d0ae72
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570678245954652609689719027407747107783347883108684844749436080159144
4830491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access_b2b.57067824595465260968971902740774710778334
78831086848447494360801591444830491
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.110465380861960047015989230244116002702120677891286488985293252698021411367025
Short name T626
Test name
Test status
Simulation time 607542526 ps
CPU time 6.01 seconds
Started Nov 22 02:11:39 PM PST 23
Finished Nov 22 02:11:46 PM PST 23
Peak memory 203116 kb
Host smart-f6445503-c149-43a3-8314-02499f8f65e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110465380861960047015989230244116002702120677891286488985293252698021411367025 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.110465380861960047015989230244116002702120677891286488985293252698021411367025
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.109190861869912521671946782774780139427679318218475552293482472775547944355174
Short name T331
Test name
Test status
Simulation time 19913691647 ps
CPU time 566.32 seconds
Started Nov 22 02:11:40 PM PST 23
Finished Nov 22 02:21:07 PM PST 23
Peak memory 372520 kb
Host smart-3739aef1-5a86-4f3a-a7c7-3236b392bb01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109190861869912521671946782774780139427679318218475552293482472775547944355174 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.109190861869912521671946782774780139427679318218475552293482472775547944355174
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.5970118569503750734989565291200028956737500039084475091797460788887291736156
Short name T844
Test name
Test status
Simulation time 988289480 ps
CPU time 18.34 seconds
Started Nov 22 02:11:39 PM PST 23
Finished Nov 22 02:11:58 PM PST 23
Peak memory 245648 kb
Host smart-7de40134-d67e-4acb-b5cc-0e10427624d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5970118569503750734989565291200028956737500039084475091797460788887291736156 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.5970118569503750734989565291200028956737500039084475091797460788887291736156
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.94231334619638750995141052919221984316091131512873616191567031615977783644816
Short name T750
Test name
Test status
Simulation time 624328106 ps
CPU time 1776.28 seconds
Started Nov 22 02:11:41 PM PST 23
Finished Nov 22 02:41:18 PM PST 23
Peak memory 498160 kb
Host smart-9d00515e-a775-42f9-af3d-aec03e977cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=94231334619638750995141052919221984316091131512873616191567031615977783644816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sr
am_ctrl_stress_all_with_rand_reset.94231334619638750995141052919221984316091131512873616191567031615977783644816
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.24376610032743614085397632241187073902554870023675338350333929442903361125539
Short name T814
Test name
Test status
Simulation time 9325508496 ps
CPU time 433.23 seconds
Started Nov 22 02:11:35 PM PST 23
Finished Nov 22 02:18:49 PM PST 23
Peak memory 202836 kb
Host smart-45e16351-83de-4c84-a982-589bda0a2c4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24376610032743614085397632241187073902554870023675338350333929442903361125539
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.243766100327436140853976322411870739025548700236753
38350333929442903361125539
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.106811414164843765756792522226006415292669157043624455373820930992033432957173
Short name T217
Test name
Test status
Simulation time 1371125703 ps
CPU time 116.26 seconds
Started Nov 22 02:11:34 PM PST 23
Finished Nov 22 02:13:31 PM PST 23
Peak memory 351156 kb
Host smart-864483e0-d492-46c5-8ca5-a80fd5877163
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106811414164843765756792522226006415292669157043624455
373820930992033432957173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.106811414164843765756
792522226006415292669157043624455373820930992033432957173
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.102703595264357632224481482077335011584028716240925251558581324616384711343246
Short name T607
Test name
Test status
Simulation time 13467153934 ps
CPU time 987.08 seconds
Started Nov 22 02:11:59 PM PST 23
Finished Nov 22 02:28:30 PM PST 23
Peak memory 378756 kb
Host smart-d7d0cd18-c9ef-4d5b-b914-2c063f13d7ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10270359526435763222448148207733501158402871624092525155858132461638471134324
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during_key_req.10270359526435763222448148207733501158
4028716240925251558581324616384711343246
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.78350143842123360629745927342865214679894090770309127471568400128495881052819
Short name T889
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:12:17 PM PST 23
Finished Nov 22 02:12:18 PM PST 23
Peak memory 202492 kb
Host smart-a7020541-da21-4447-8ec0-e536e60fde58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783501438421233606297459273428652146798940907703091274715684001284
95881052819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.783501438421233606297459273428652146798940907703091274
71568400128495881052819
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.65326532910713526934138083472741591386976442931705688626963234824384099467735
Short name T475
Test name
Test status
Simulation time 295482808505 ps
CPU time 2710.68 seconds
Started Nov 22 02:11:41 PM PST 23
Finished Nov 22 02:56:52 PM PST 23
Peak memory 202804 kb
Host smart-fe532dc4-8ad4-4fdc-8f8b-ac0c76943b62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65326532910713526934138083472741591386976442931705688626963234824384099467735 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.65326532910713526934138083472741591386976442931705688626963234824384099467735
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.106940786598521730967802865927891989751217277662889262958195040901306084574772
Short name T17
Test name
Test status
Simulation time 31712811539 ps
CPU time 884.62 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:27:04 PM PST 23
Peak memory 368032 kb
Host smart-4e644bf8-f310-432e-b275-5aa33b242759
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106940786598521730967802865927891989751217277662889262958195040901306084574772 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.106940786598521730967802865927891989751217277662889262958195040901306084574772
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.55992064750154653665120466959305300640433697205298613339654475924268378929630
Short name T837
Test name
Test status
Simulation time 1342947357 ps
CPU time 126.95 seconds
Started Nov 22 02:12:02 PM PST 23
Finished Nov 22 02:14:10 PM PST 23
Peak memory 351044 kb
Host smart-f6d79686-7989-4e67-b765-bebf37069ef5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5599206475015465366512046695930530064043369720529861333
9654475924268378929630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_max_throughput.55992064750154653665120466959305300
640433697205298613339654475924268378929630
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.38171894869294863013760767260140880923100857452118142990833556995340857458981
Short name T74
Test name
Test status
Simulation time 4750777237 ps
CPU time 77.95 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:13:38 PM PST 23
Peak memory 212336 kb
Host smart-fe2406f9-8aaf-41db-8f6d-7d7b8d96816c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38171894869294863013760767260140880923100857452118142990833556995340
857458981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.381718948692948630137607672601408809231008574521
18142990833556995340857458981
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.31826243918918317444858699567817948084849142241227214026586057583307891326899
Short name T782
Test name
Test status
Simulation time 18445453393 ps
CPU time 159.3 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:14:59 PM PST 23
Peak memory 202760 kb
Host smart-36471531-90e4-4fb9-8c84-38ea51d84b5c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31826243918918317444858699567817948084849142241227214026586057583307891326899
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.31826243918918317444858699567817948084849142241227214026586057583307891326899
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.4072209334563683596464622309052107926450764424893912894437681524368892913688
Short name T754
Test name
Test status
Simulation time 28731174678 ps
CPU time 665.4 seconds
Started Nov 22 02:11:41 PM PST 23
Finished Nov 22 02:22:48 PM PST 23
Peak memory 378536 kb
Host smart-77401ef2-9b9c-49cc-aebd-ec6520c4cbf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072209334563683596464622309052107926450764424893912894437681524368892913688 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.4072209334563683596464622309052107926450764424893912894437681524368892913688
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.43028369447828460030828416863699600933066298605274981566112960510608964184467
Short name T269
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.91 seconds
Started Nov 22 02:12:13 PM PST 23
Finished Nov 22 02:12:35 PM PST 23
Peak memory 245672 kb
Host smart-967725c3-de09-44bd-8439-cf8af921f816
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430283694478284600308284168636996009330662986052749815661129605106089
64184467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.430283694478284600308284168636996009330662986052749815
66112960510608964184467
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.87430746624652618413618686872392113758268047647713434473722313089823856060468
Short name T884
Test name
Test status
Simulation time 45083829570 ps
CPU time 569.12 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:21:49 PM PST 23
Peak memory 202888 kb
Host smart-cf489df7-9122-475d-8aa6-2e119891cd43
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874307466246526184136186868723921137582680476477134344737223130898238
56060468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access_b2b.8743074662465261841361868687239211375826
8047647713434473722313089823856060468
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.30890972788301477744110947229308241774180662613203488874551056783734336486799
Short name T811
Test name
Test status
Simulation time 607542526 ps
CPU time 6.08 seconds
Started Nov 22 02:12:12 PM PST 23
Finished Nov 22 02:12:22 PM PST 23
Peak memory 203116 kb
Host smart-0698e1f2-12df-4049-88e2-e91eb98d98c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30890972788301477744110947229308241774180662613203488874551056783734336486799 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.30890972788301477744110947229308241774180662613203488874551056783734336486799
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.107889197396681137610076462431774698064105581869244337383820114740934644173686
Short name T474
Test name
Test status
Simulation time 19913691647 ps
CPU time 526.58 seconds
Started Nov 22 02:12:15 PM PST 23
Finished Nov 22 02:21:03 PM PST 23
Peak memory 372544 kb
Host smart-477bbf73-0ff1-4677-8978-94a3822bcb79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107889197396681137610076462431774698064105581869244337383820114740934644173686 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.107889197396681137610076462431774698064105581869244337383820114740934644173686
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.7034390366851252515846920555921541684089257975633460438752017633189000699414
Short name T823
Test name
Test status
Simulation time 988289480 ps
CPU time 18.48 seconds
Started Nov 22 02:11:40 PM PST 23
Finished Nov 22 02:11:59 PM PST 23
Peak memory 245652 kb
Host smart-8d3fc36d-b543-407c-a5e5-ff5fc3fcb142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7034390366851252515846920555921541684089257975633460438752017633189000699414 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.7034390366851252515846920555921541684089257975633460438752017633189000699414
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.4978206322932935475132483877512764175713461242087225247722178851174867586336
Short name T691
Test name
Test status
Simulation time 624328106 ps
CPU time 1961.53 seconds
Started Nov 22 02:12:15 PM PST 23
Finished Nov 22 02:44:58 PM PST 23
Peak memory 498060 kb
Host smart-d9357995-0760-49d0-8dff-c512edb891a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4978206322932935475132483877512764175713461242087225247722178851174867586336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sra
m_ctrl_stress_all_with_rand_reset.4978206322932935475132483877512764175713461242087225247722178851174867586336
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.87761745542554751633026825000407639025471115134034321801125934345089610718233
Short name T850
Test name
Test status
Simulation time 9325508496 ps
CPU time 427.94 seconds
Started Nov 22 02:12:01 PM PST 23
Finished Nov 22 02:19:11 PM PST 23
Peak memory 203008 kb
Host smart-84c103d5-9703-4a9a-a307-8e609b994f66
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87761745542554751633026825000407639025471115134034321801125934345089610718233
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.877617455425547516330268250004076390254711151340343
21801125934345089610718233
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.46828441300570107030647390740444002382627970259948997733062752968126425843499
Short name T317
Test name
Test status
Simulation time 1371125703 ps
CPU time 147.2 seconds
Started Nov 22 02:12:13 PM PST 23
Finished Nov 22 02:14:43 PM PST 23
Peak memory 351148 kb
Host smart-0f86d56e-a0a2-4c91-babf-d84ee9ffb308
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468284413005701070306473907404440023826279702599489977
33062752968126425843499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.4682844130057010703064
7390740444002382627970259948997733062752968126425843499
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.102617421266852684588327479085519555067172789294010339148929925582261502892612
Short name T365
Test name
Test status
Simulation time 13467153934 ps
CPU time 994.23 seconds
Started Nov 22 02:12:17 PM PST 23
Finished Nov 22 02:28:53 PM PST 23
Peak memory 378672 kb
Host smart-c2a507ad-f8f9-46ad-ab35-6361f58985f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10261742126685268458832747908551955506717278929401033914892992558226150289261
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during_key_req.10261742126685268458832747908551955506
7172789294010339148929925582261502892612
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.13990121283724769217268585237326255389368044155316652322125412270061526892823
Short name T764
Test name
Test status
Simulation time 16600825 ps
CPU time 0.64 seconds
Started Nov 22 02:12:16 PM PST 23
Finished Nov 22 02:12:18 PM PST 23
Peak memory 202528 kb
Host smart-710cb4d1-ccdc-4bc6-86ed-6b188e19c886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139901212837247692172685852373262553893680441553166523221254122700
61526892823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.139901212837247692172685852373262553893680441553166523
22125412270061526892823
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.114535423405506613323558216844113594371317987526751552470072597427945562488926
Short name T659
Test name
Test status
Simulation time 295482808505 ps
CPU time 2787.49 seconds
Started Nov 22 02:12:17 PM PST 23
Finished Nov 22 02:58:47 PM PST 23
Peak memory 202892 kb
Host smart-66b25dee-e442-48d8-8df3-4812b33ef526
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114535423405506613323558216844113594371317987526751552470072597427945562488926 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.114535423405506613323558216844113594371317987526751552470072597427945562488926
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.107049778849075706080363240220934224086138464596641515169404588908462648002406
Short name T668
Test name
Test status
Simulation time 31712811539 ps
CPU time 830.82 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:26:11 PM PST 23
Peak memory 367988 kb
Host smart-2e84ca35-519b-413c-9bab-f9e763cabaf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107049778849075706080363240220934224086138464596641515169404588908462648002406 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.107049778849075706080363240220934224086138464596641515169404588908462648002406
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.51949284885184848952700305238183920767464724140739659529166616908221167592636
Short name T382
Test name
Test status
Simulation time 19084394710 ps
CPU time 101.61 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:14:02 PM PST 23
Peak memory 210984 kb
Host smart-9098deae-6792-49e2-9d6e-2edde2878366
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51949284885184848952700305238183920767464724140739659529166616908221167592636 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.51949284885184848952700305238183920767464724140739659529166616908221167592636
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.37280575077858540754785626237040137076901344162405532937559629904797056759071
Short name T788
Test name
Test status
Simulation time 1342947357 ps
CPU time 125.53 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:14:25 PM PST 23
Peak memory 351164 kb
Host smart-d9231643-4d45-4ecb-99cb-f0fb3d4672ba
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728057507785854075478562623704013707690134416240553293
7559629904797056759071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_max_throughput.37280575077858540754785626237040137
076901344162405532937559629904797056759071
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.31597266741867244481067568364386300570474786341427271872959996694335704888816
Short name T350
Test name
Test status
Simulation time 4750777237 ps
CPU time 80.93 seconds
Started Nov 22 02:12:17 PM PST 23
Finished Nov 22 02:13:40 PM PST 23
Peak memory 212360 kb
Host smart-e11bdefe-5359-4211-9f5e-04ebb9e2acea
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31597266741867244481067568364386300570474786341427271872959996694335
704888816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.315972667418672444810675683643863005704747863414
27271872959996694335704888816
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.76326916799107143752950485615326585779023859998417687166576948291386248157522
Short name T876
Test name
Test status
Simulation time 18445453393 ps
CPU time 159.33 seconds
Started Nov 22 02:12:22 PM PST 23
Finished Nov 22 02:15:02 PM PST 23
Peak memory 202780 kb
Host smart-21e306d1-9cf2-4ef5-9a9f-ce8de5a406b3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76326916799107143752950485615326585779023859998417687166576948291386248157522
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.76326916799107143752950485615326585779023859998417687166576948291386248157522
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.16686215553983864261829765444293065453383513275020482731639721573576270564442
Short name T438
Test name
Test status
Simulation time 28731174678 ps
CPU time 921.84 seconds
Started Nov 22 02:12:00 PM PST 23
Finished Nov 22 02:27:25 PM PST 23
Peak memory 378552 kb
Host smart-0f6dcab8-ddea-455a-9aca-c0041c710adf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16686215553983864261829765444293065453383513275020482731639721573576270564442 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.16686215553983864261829765444293065453383513275020482731639721573576270564442
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.24892313832722449785825377964237069533578869167489468057940172077356142357121
Short name T673
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.12 seconds
Started Nov 22 02:12:17 PM PST 23
Finished Nov 22 02:12:39 PM PST 23
Peak memory 245688 kb
Host smart-0eb28c6f-ca72-46f7-b042-12479dc20f5b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248923138327224497858253779642370695335788691674894680579401720773561
42357121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.248923138327224497858253779642370695335788691674894680
57940172077356142357121
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.49928978493105519676685769231456321046800597078989649589400634428131004832590
Short name T623
Test name
Test status
Simulation time 45083829570 ps
CPU time 577.63 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:21:58 PM PST 23
Peak memory 202768 kb
Host smart-73d38003-64bc-494c-93ea-4470a0eab1be
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499289784931055196766857692314563210468005970789896495894006344281310
04832590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access_b2b.4992897849310551967668576923145632104680
0597078989649589400634428131004832590
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.46602710155964998096919208353445166801773245713700857631193161957935563975876
Short name T798
Test name
Test status
Simulation time 607542526 ps
CPU time 6.02 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:12:26 PM PST 23
Peak memory 203028 kb
Host smart-141a5fff-75d4-419a-86e7-4229962b6cc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46602710155964998096919208353445166801773245713700857631193161957935563975876 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.46602710155964998096919208353445166801773245713700857631193161957935563975876
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.95664672409971462500662574790994152351677395958178250082920843508138943879364
Short name T313
Test name
Test status
Simulation time 19913691647 ps
CPU time 640.33 seconds
Started Nov 22 02:12:32 PM PST 23
Finished Nov 22 02:23:13 PM PST 23
Peak memory 372536 kb
Host smart-d65b1839-05a0-4118-93f5-da7a21972ced
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95664672409971462500662574790994152351677395958178250082920843508138943879364 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.95664672409971462500662574790994152351677395958178250082920843508138943879364
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.31377705510593371987571525973129561643318701721527740271834935700920167889489
Short name T544
Test name
Test status
Simulation time 988289480 ps
CPU time 17.2 seconds
Started Nov 22 02:12:02 PM PST 23
Finished Nov 22 02:12:20 PM PST 23
Peak memory 245544 kb
Host smart-f8228ab5-8479-46b7-bbf8-d3073eb714fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31377705510593371987571525973129561643318701721527740271834935700920167889489 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.31377705510593371987571525973129561643318701721527740271834935700920167889489
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.27940177714923765773462253616283750550672891140669482405107896666917773910000
Short name T836
Test name
Test status
Simulation time 624328106 ps
CPU time 1877.89 seconds
Started Nov 22 02:12:22 PM PST 23
Finished Nov 22 02:43:41 PM PST 23
Peak memory 498180 kb
Host smart-3b83ec12-4c01-40a2-b1f7-b8fa93eb58d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=27940177714923765773462253616283750550672891140669482405107896666917773910000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sr
am_ctrl_stress_all_with_rand_reset.27940177714923765773462253616283750550672891140669482405107896666917773910000
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.77821556652183158434885703203431830311048665593510389441885105509597914690848
Short name T603
Test name
Test status
Simulation time 9325508496 ps
CPU time 426.26 seconds
Started Nov 22 02:12:14 PM PST 23
Finished Nov 22 02:19:22 PM PST 23
Peak memory 202888 kb
Host smart-46b0a1cf-a9b0-4729-91bf-fd048a4891be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77821556652183158434885703203431830311048665593510389441885105509597914690848
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.778215566521831584348857032034318303110486655935103
89441885105509597914690848
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.37128604054060234527272023560162887930239199248298782394744319878435396028268
Short name T890
Test name
Test status
Simulation time 1371125703 ps
CPU time 127.11 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:14:27 PM PST 23
Peak memory 350960 kb
Host smart-ad67b0f6-126d-4948-a4a7-70d904dc9ed2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371286040540602345272720235601628879302391992482987823
94744319878435396028268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.3712860405406023452727
2023560162887930239199248298782394744319878435396028268
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.12057857139972953262060379967775720408636630457868853003160238685229774065276
Short name T359
Test name
Test status
Simulation time 13467153934 ps
CPU time 934.85 seconds
Started Nov 22 02:12:32 PM PST 23
Finished Nov 22 02:28:08 PM PST 23
Peak memory 378768 kb
Host smart-6b4caf0d-7e9c-4e7e-94e8-a0e55a6d2397
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12057857139972953262060379967775720408636630457868853003160238685229774065276
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during_key_req.120578571399729532620603799677757204086
36630457868853003160238685229774065276
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.93242344686330138514057025902253108960106973975725723369482434888761183001868
Short name T240
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:12:35 PM PST 23
Finished Nov 22 02:12:36 PM PST 23
Peak memory 202572 kb
Host smart-852be0e8-d086-4158-aaf8-4e7f322d94f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932423446863301385140570259022531089601069739757257233694824348887
61183001868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.932423446863301385140570259022531089601069739757257233
69482434888761183001868
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.82648891117661201283086133853492569417101216924295133637094750306154958669218
Short name T988
Test name
Test status
Simulation time 295482808505 ps
CPU time 2750.98 seconds
Started Nov 22 02:12:17 PM PST 23
Finished Nov 22 02:58:11 PM PST 23
Peak memory 202960 kb
Host smart-190cdb1c-4791-4dfd-a0de-a6f4bb848ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82648891117661201283086133853492569417101216924295133637094750306154958669218 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.82648891117661201283086133853492569417101216924295133637094750306154958669218
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.6108544153117086010118348244899762563141001846304611105988222024043734546849
Short name T562
Test name
Test status
Simulation time 31712811539 ps
CPU time 892.83 seconds
Started Nov 22 02:12:33 PM PST 23
Finished Nov 22 02:27:27 PM PST 23
Peak memory 368112 kb
Host smart-765accef-8587-48ee-a8fb-0d47c6c9da1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6108544153117086010118348244899762563141001846304611105988222024043734546849 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.6108544153117086010118348244899762563141001846304611105988222024043734546849
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.85955272828484431602817142999735276025496440474100728213663987543318306648878
Short name T702
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.35 seconds
Started Nov 22 02:12:17 PM PST 23
Finished Nov 22 02:14:04 PM PST 23
Peak memory 211076 kb
Host smart-d7a138c7-6e62-4f9b-9bcf-1e4bdfef22a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85955272828484431602817142999735276025496440474100728213663987543318306648878 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.85955272828484431602817142999735276025496440474100728213663987543318306648878
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.66752410564357833543903843467688781678702079569266988927211629705917381883336
Short name T533
Test name
Test status
Simulation time 1342947357 ps
CPU time 126.71 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:14:27 PM PST 23
Peak memory 351032 kb
Host smart-7a244916-b5b6-4713-b2d3-c99dd5c05260
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6675241056435783354390384346768878167870207956926698892
7211629705917381883336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_max_throughput.66752410564357833543903843467688781
678702079569266988927211629705917381883336
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.10457976343755819223109798488690879424301101977286354706507388273700074294779
Short name T329
Test name
Test status
Simulation time 4750777237 ps
CPU time 81.27 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:13:41 PM PST 23
Peak memory 212332 kb
Host smart-72c37a6b-2dd6-4236-9037-2cf90ac436b9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457976343755819223109798488690879424301101977286354706507388273700
074294779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.104579763437558192231097984886908794243011019772
86354706507388273700074294779
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.41449909161355230882121405665017221315236279220240264034032780773373610327769
Short name T554
Test name
Test status
Simulation time 18445453393 ps
CPU time 160.24 seconds
Started Nov 22 02:12:53 PM PST 23
Finished Nov 22 02:15:34 PM PST 23
Peak memory 202788 kb
Host smart-0ea4841f-9486-4dcf-a4c6-d8a912a61f40
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41449909161355230882121405665017221315236279220240264034032780773373610327769
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.41449909161355230882121405665017221315236279220240264034032780773373610327769
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.111416591950219340514049620696577863664017873908889853774922684938944714754230
Short name T295
Test name
Test status
Simulation time 28731174678 ps
CPU time 965.39 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:28:25 PM PST 23
Peak memory 378576 kb
Host smart-ed6ad341-8ec2-46ba-bb3b-2c8b09d000ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111416591950219340514049620696577863664017873908889853774922684938944714754230 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.111416591950219340514049620696577863664017873908889853774922684938944714754230
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.72560551457667753265074218313107160161548287672715700758228194149733597785763
Short name T114
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.85 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:12:40 PM PST 23
Peak memory 245656 kb
Host smart-eda14f2b-4949-4841-a35b-d05454fb33da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725605514576677532650742183131071601615482876727157007582281941497335
97785763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.725605514576677532650742183131071601615482876727157007
58228194149733597785763
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.101839037033852991836323107550827636477578546387657123968238975694769135242297
Short name T897
Test name
Test status
Simulation time 45083829570 ps
CPU time 581.84 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:22:02 PM PST 23
Peak memory 202908 kb
Host smart-f859fa10-ab27-45fc-b4fe-acf63694f33f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101839037033852991836323107550827636477578546387657123968238975694769
135242297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access_b2b.101839037033852991836323107550827636477
578546387657123968238975694769135242297
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.94381856655303101560505734898047770691233103500797858422532853340380472035463
Short name T512
Test name
Test status
Simulation time 607542526 ps
CPU time 6.17 seconds
Started Nov 22 02:12:21 PM PST 23
Finished Nov 22 02:12:28 PM PST 23
Peak memory 203128 kb
Host smart-cf6f215a-da09-4d8d-b662-623292a69043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94381856655303101560505734898047770691233103500797858422532853340380472035463 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.94381856655303101560505734898047770691233103500797858422532853340380472035463
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.95898024780089884580471214435519298684337878572840213677441478996510904841059
Short name T853
Test name
Test status
Simulation time 19913691647 ps
CPU time 571.21 seconds
Started Nov 22 02:12:35 PM PST 23
Finished Nov 22 02:22:07 PM PST 23
Peak memory 372536 kb
Host smart-eff42c88-9171-439d-909b-c9f40772d851
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95898024780089884580471214435519298684337878572840213677441478996510904841059 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.95898024780089884580471214435519298684337878572840213677441478996510904841059
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.46144317135586959411519535913193286956987105147681974697741738777348722024355
Short name T637
Test name
Test status
Simulation time 988289480 ps
CPU time 18.65 seconds
Started Nov 22 02:12:18 PM PST 23
Finished Nov 22 02:12:39 PM PST 23
Peak memory 245556 kb
Host smart-d3016484-164b-47fa-9ab5-4b2fa90a0249
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46144317135586959411519535913193286956987105147681974697741738777348722024355 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.46144317135586959411519535913193286956987105147681974697741738777348722024355
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.105003182911112234733474697567948453563560601485319497610783430763452558962874
Short name T409
Test name
Test status
Simulation time 624328106 ps
CPU time 2306.01 seconds
Started Nov 22 02:12:21 PM PST 23
Finished Nov 22 02:50:47 PM PST 23
Peak memory 498208 kb
Host smart-dfb6a629-00a2-40d0-b640-61c3818e0750
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=105003182911112234733474697567948453563560601485319497610783430763452558962874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.s
ram_ctrl_stress_all_with_rand_reset.105003182911112234733474697567948453563560601485319497610783430763452558962874
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.59775394302855025265042629330642083733435463193133392630018850624277079723866
Short name T458
Test name
Test status
Simulation time 9325508496 ps
CPU time 422.42 seconds
Started Nov 22 02:12:16 PM PST 23
Finished Nov 22 02:19:20 PM PST 23
Peak memory 202896 kb
Host smart-d86be750-e553-4c6a-beda-a1b211e4453e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59775394302855025265042629330642083733435463193133392630018850624277079723866
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.597753943028550252650426293306420837334354631931333
92630018850624277079723866
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.18217850030673032648306319224791878908073586008499901995704630230685952967789
Short name T118
Test name
Test status
Simulation time 1371125703 ps
CPU time 113.04 seconds
Started Nov 22 02:12:21 PM PST 23
Finished Nov 22 02:14:15 PM PST 23
Peak memory 351200 kb
Host smart-f614076c-20b3-4090-9ff5-8a82a6c389cc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182178500306730326483063192247918789080735860084999019
95704630230685952967789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1821785003067303264830
6319224791878908073586008499901995704630230685952967789
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.41953776197155724946430497963750665750240538822234664464651326112983930614787
Short name T565
Test name
Test status
Simulation time 13467153934 ps
CPU time 1020.8 seconds
Started Nov 22 02:12:49 PM PST 23
Finished Nov 22 02:29:51 PM PST 23
Peak memory 378780 kb
Host smart-856a2611-ac17-4052-9416-89e15621b715
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41953776197155724946430497963750665750240538822234664464651326112983930614787
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during_key_req.419537761971557249464304979637506657502
40538822234664464651326112983930614787
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.39481370189828629188896668598739101327862579460391290613931920115007515374009
Short name T550
Test name
Test status
Simulation time 16600825 ps
CPU time 0.63 seconds
Started Nov 22 02:12:48 PM PST 23
Finished Nov 22 02:12:49 PM PST 23
Peak memory 202568 kb
Host smart-85208614-7e7a-490e-ae06-77b6410157e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394813701898286291888966685987391013278625794603912906139319201150
07515374009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.394813701898286291888966685987391013278625794603912906
13931920115007515374009
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.7488803540532577937460679299969233099995371334751721410288304089866089043687
Short name T553
Test name
Test status
Simulation time 295482808505 ps
CPU time 2817.6 seconds
Started Nov 22 02:12:34 PM PST 23
Finished Nov 22 02:59:32 PM PST 23
Peak memory 202912 kb
Host smart-0b495748-c70d-4489-b5eb-c15fc163a4bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7488803540532577937460679299969233099995371334751721410288304089866089043687 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.7488803540532577937460679299969233099995371334751721410288304089866089043687
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.24124963162554785800132319562780636613622437920098521394690136529519024813691
Short name T310
Test name
Test status
Simulation time 31712811539 ps
CPU time 897 seconds
Started Nov 22 02:12:51 PM PST 23
Finished Nov 22 02:27:49 PM PST 23
Peak memory 368028 kb
Host smart-60317af4-f4b4-432f-b004-afd5827275ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24124963162554785800132319562780636613622437920098521394690136529519024813691 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.24124963162554785800132319562780636613622437920098521394690136529519024813691
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.3491796460357932741891796931911150614155746142390840978327808332218514913813
Short name T237
Test name
Test status
Simulation time 19084394710 ps
CPU time 100.22 seconds
Started Nov 22 02:12:33 PM PST 23
Finished Nov 22 02:14:14 PM PST 23
Peak memory 211116 kb
Host smart-3006ef26-9dea-4242-bd23-f37b92da891a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491796460357932741891796931911150614155746142390840978327808332218514913813 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.3491796460357932741891796931911150614155746142390840978327808332218514913813
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.51234561885161516733370699505124031324514766509228860953364016919094178954193
Short name T434
Test name
Test status
Simulation time 1342947357 ps
CPU time 129.33 seconds
Started Nov 22 02:12:32 PM PST 23
Finished Nov 22 02:14:42 PM PST 23
Peak memory 351176 kb
Host smart-489141ea-ba46-4f2a-99ad-bd11a09c58af
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5123456188516151673337069950512403132451476650922886095
3364016919094178954193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_max_throughput.51234561885161516733370699505124031
324514766509228860953364016919094178954193
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.100696312781752067234687477586756662918688158371347128643475868849179233036584
Short name T354
Test name
Test status
Simulation time 4750777237 ps
CPU time 75.28 seconds
Started Nov 22 02:12:54 PM PST 23
Finished Nov 22 02:14:11 PM PST 23
Peak memory 212324 kb
Host smart-8a4d328c-fc15-4c12-98e7-638e35167e5a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10069631278175206723468747758675666291868815837134712864347586884917
9233036584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.10069631278175206723468747758675666291868815837
1347128643475868849179233036584
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.38721964564818971263548621525049042914843623676156000227680447502145874353552
Short name T413
Test name
Test status
Simulation time 18445453393 ps
CPU time 160.03 seconds
Started Nov 22 02:12:50 PM PST 23
Finished Nov 22 02:15:31 PM PST 23
Peak memory 202800 kb
Host smart-d2664cd7-1533-4d8c-ba06-c9b2ff903365
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38721964564818971263548621525049042914843623676156000227680447502145874353552
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.38721964564818971263548621525049042914843623676156000227680447502145874353552
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.113785817895634857736813058919558253354553865166435367511141612116699158819547
Short name T511
Test name
Test status
Simulation time 28731174678 ps
CPU time 951.9 seconds
Started Nov 22 02:12:19 PM PST 23
Finished Nov 22 02:28:12 PM PST 23
Peak memory 378664 kb
Host smart-d63406c1-8cf1-4d56-aa46-d1393cbea106
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113785817895634857736813058919558253354553865166435367511141612116699158819547 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.113785817895634857736813058919558253354553865166435367511141612116699158819547
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.21363015002366665488548835327163984877523572827228080012255774466644912086327
Short name T885
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.31 seconds
Started Nov 22 02:12:34 PM PST 23
Finished Nov 22 02:12:53 PM PST 23
Peak memory 245652 kb
Host smart-d0be352f-60a5-490c-8551-345ae910403d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213630150023666654885488353271639848775235728272280800122557744666449
12086327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.213630150023666654885488353271639848775235728272280800
12255774466644912086327
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.47678856833653359498732535770501306142473020443053053212480940665037394205781
Short name T951
Test name
Test status
Simulation time 45083829570 ps
CPU time 569.07 seconds
Started Nov 22 02:12:35 PM PST 23
Finished Nov 22 02:22:05 PM PST 23
Peak memory 202884 kb
Host smart-2e68f1ff-86e2-4d3b-9521-2d7600bd9035
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476788568336533594987325357705013061424730204430530532124809406650373
94205781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access_b2b.4767885683365335949873253577050130614247
3020443053053212480940665037394205781
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.55381236624696457272702460601748373205081080752181917721057604850784862059831
Short name T963
Test name
Test status
Simulation time 607542526 ps
CPU time 5.98 seconds
Started Nov 22 02:12:33 PM PST 23
Finished Nov 22 02:12:40 PM PST 23
Peak memory 203024 kb
Host smart-4aae91ee-b80a-483f-8d87-94e385b2ce43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55381236624696457272702460601748373205081080752181917721057604850784862059831 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.55381236624696457272702460601748373205081080752181917721057604850784862059831
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.110683447596910266133685514971535421813563860031818983920630544968903923575475
Short name T581
Test name
Test status
Simulation time 19913691647 ps
CPU time 572.07 seconds
Started Nov 22 02:12:51 PM PST 23
Finished Nov 22 02:22:23 PM PST 23
Peak memory 372644 kb
Host smart-0c956b7e-e612-4cb7-9cbb-5bf098c9504d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110683447596910266133685514971535421813563860031818983920630544968903923575475 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.110683447596910266133685514971535421813563860031818983920630544968903923575475
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.24652599586261991848906881999306354103917182373254167424342372172608046061887
Short name T639
Test name
Test status
Simulation time 988289480 ps
CPU time 16.94 seconds
Started Nov 22 02:12:21 PM PST 23
Finished Nov 22 02:12:38 PM PST 23
Peak memory 245676 kb
Host smart-125a2826-7e53-4995-8973-52812a1d6363
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24652599586261991848906881999306354103917182373254167424342372172608046061887 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.24652599586261991848906881999306354103917182373254167424342372172608046061887
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.109107868646612364844910763729269436320529295076598876184620902407870757465634
Short name T506
Test name
Test status
Simulation time 624328106 ps
CPU time 1726.09 seconds
Started Nov 22 02:12:53 PM PST 23
Finished Nov 22 02:41:40 PM PST 23
Peak memory 498148 kb
Host smart-d6b066a5-13f7-4c65-ab8c-cf5ff851c5ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=109107868646612364844910763729269436320529295076598876184620902407870757465634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s
ram_ctrl_stress_all_with_rand_reset.109107868646612364844910763729269436320529295076598876184620902407870757465634
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.71330817175347587547972050601041357848957877098733645360693081818122837250985
Short name T768
Test name
Test status
Simulation time 9325508496 ps
CPU time 423.84 seconds
Started Nov 22 02:12:19 PM PST 23
Finished Nov 22 02:19:24 PM PST 23
Peak memory 202820 kb
Host smart-efc2c928-4f18-42b2-afdc-aa088fd2b5e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71330817175347587547972050601041357848957877098733645360693081818122837250985
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.713308171753475875479720506010413578489578770987336
45360693081818122837250985
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.41496296697418645612784144497048992759255604460784192875409062463024428142946
Short name T800
Test name
Test status
Simulation time 1371125703 ps
CPU time 119.77 seconds
Started Nov 22 02:12:35 PM PST 23
Finished Nov 22 02:14:35 PM PST 23
Peak memory 351180 kb
Host smart-337be545-cf70-4a87-a733-3f5b85ba16c5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414962966974186456127841444970489927592556044607841928
75409062463024428142946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.4149629669741864561278
4144497048992759255604460784192875409062463024428142946
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.36633260171279416796328785820136983818319372945882724550152639396999420141038
Short name T936
Test name
Test status
Simulation time 13467153934 ps
CPU time 989.31 seconds
Started Nov 22 02:07:22 PM PST 23
Finished Nov 22 02:23:53 PM PST 23
Peak memory 378812 kb
Host smart-2148da20-915c-4272-b612-ae09aa3e0b26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36633260171279416796328785820136983818319372945882724550152639396999420141038
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_key_req.3663326017127941679632878582013698381831
9372945882724550152639396999420141038
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.95395660652582139058018372167972137592600631049812847435043105369658074271292
Short name T374
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:07:06 PM PST 23
Finished Nov 22 02:07:12 PM PST 23
Peak memory 202688 kb
Host smart-d4ac339c-3d61-49e9-bcd3-b0bb2ca0df29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953956606525821390580183721679721375926006310498128474350431053696
58074271292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.9539566065258213905801837216797213759260063104981284743
5043105369658074271292
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.57860237628164388481965034091881555330737147120078002151234615207755058516277
Short name T938
Test name
Test status
Simulation time 295482808505 ps
CPU time 2730.96 seconds
Started Nov 22 02:07:18 PM PST 23
Finished Nov 22 02:52:50 PM PST 23
Peak memory 202824 kb
Host smart-168b3c8f-4885-4155-85b2-4e2926c83098
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57860237628164388481965034091881555330737147120078002151234615207755058516277 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.57860237628164388481965034091881555330737147120078002151234615207755058516277
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.7745016435907713719135435141402815047450556275897511134573539486613281079916
Short name T250
Test name
Test status
Simulation time 31712811539 ps
CPU time 765.9 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:20:07 PM PST 23
Peak memory 368028 kb
Host smart-4e8e9a29-88c9-4998-b97b-ef63ca3f4003
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7745016435907713719135435141402815047450556275897511134573539486613281079916 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.7745016435907713719135435141402815047450556275897511134573539486613281079916
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.69051013191969961906681473188025150455950962620643109063331507621151836501673
Short name T779
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.12 seconds
Started Nov 22 02:07:06 PM PST 23
Finished Nov 22 02:08:55 PM PST 23
Peak memory 211084 kb
Host smart-5e6a9d60-d6c1-4bf2-a59d-3e9476f1e05b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69051013191969961906681473188025150455950962620643109063331507621151836501673 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.69051013191969961906681473188025150455950962620643109063331507621151836501673
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.73058362475170429976431835800188485497131028164472328890721263436476799338127
Short name T353
Test name
Test status
Simulation time 1342947357 ps
CPU time 122.95 seconds
Started Nov 22 02:07:07 PM PST 23
Finished Nov 22 02:09:16 PM PST 23
Peak memory 351172 kb
Host smart-dd952323-6be0-4ed0-a7f5-918f4e9f2479
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7305836247517042997643183580018848549713102816447232889
0721263436476799338127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max_throughput.730583624751704299764318358001884854
97131028164472328890721263436476799338127
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.24358108455417966612533444978210927948878431257059008392214128061939991770931
Short name T10
Test name
Test status
Simulation time 4750777237 ps
CPU time 79.43 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:08:41 PM PST 23
Peak memory 212340 kb
Host smart-0c1154d2-da1f-4905-9719-fd78dbeba44a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24358108455417966612533444978210927948878431257059008392214128061939
991770931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.2435810845541796661253344497821092794887843125705
9008392214128061939991770931
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.15012098295363177823845164163961866402139229468513485193180744588144304497224
Short name T718
Test name
Test status
Simulation time 18445453393 ps
CPU time 155.51 seconds
Started Nov 22 02:07:07 PM PST 23
Finished Nov 22 02:09:49 PM PST 23
Peak memory 202772 kb
Host smart-69646564-b66f-4d3f-b1f6-bd7a6daf2d8a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15012098295363177823845164163961866402139229468513485193180744588144304497224
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.15012098295363177823845164163961866402139229468513485193180744588144304497224
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.52720461667914266800863096230877028011119192412669138847079386881521365157339
Short name T337
Test name
Test status
Simulation time 28731174678 ps
CPU time 859.59 seconds
Started Nov 22 02:07:07 PM PST 23
Finished Nov 22 02:21:33 PM PST 23
Peak memory 378648 kb
Host smart-ebfece8d-81eb-41f4-8385-5c31efad2fc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52720461667914266800863096230877028011119192412669138847079386881521365157339 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.52720461667914266800863096230877028011119192412669138847079386881521365157339
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.107342562868949019702770640961260822683855483719016497049826902477377907019725
Short name T456
Test name
Test status
Simulation time 1006378621 ps
CPU time 20.11 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:07:41 PM PST 23
Peak memory 245656 kb
Host smart-67a91d92-ba35-4b24-914f-ef84bc06ff81
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107342562868949019702770640961260822683855483719016497049826902477377
907019725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.107342562868949019702770640961260822683855483719016497
049826902477377907019725
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.74075858969977856908552538678977049872174033098500144197094000165352522764031
Short name T44
Test name
Test status
Simulation time 45083829570 ps
CPU time 591.24 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:17:13 PM PST 23
Peak memory 202816 kb
Host smart-d88598a5-7148-4450-9a0f-682df3212015
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740758589699778569085525386789770498721740330985001441970940001653525
22764031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access_b2b.74075858969977856908552538678977049872174
033098500144197094000165352522764031
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.31292248498677221770169231580775040708300180716279129803775455515683849718545
Short name T488
Test name
Test status
Simulation time 19913691647 ps
CPU time 586.02 seconds
Started Nov 22 02:07:10 PM PST 23
Finished Nov 22 02:16:59 PM PST 23
Peak memory 372528 kb
Host smart-81183dbe-23bc-4d7b-9138-7bca2037b42c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31292248498677221770169231580775040708300180716279129803775455515683849718545 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.31292248498677221770169231580775040708300180716279129803775455515683849718545
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.75668097987430080264928916519636709144575755584681963209520445000737793668255
Short name T36
Test name
Test status
Simulation time 216402798 ps
CPU time 1.97 seconds
Started Nov 22 02:07:06 PM PST 23
Finished Nov 22 02:07:13 PM PST 23
Peak memory 221204 kb
Host smart-bae7991e-2254-4521-8bdd-05653930cf39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7566809798743008026492891651963670914457575558468196320952044500073
7793668255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.756680979874300802649289165196367091445757555846819632095204
45000737793668255
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.18871252523357014941858006583808342990722432352533907974611981194066078942144
Short name T115
Test name
Test status
Simulation time 988289480 ps
CPU time 18 seconds
Started Nov 22 02:07:06 PM PST 23
Finished Nov 22 02:07:29 PM PST 23
Peak memory 245620 kb
Host smart-29ed7bfd-341c-44b8-8a2f-25f7cbfd5568
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18871252523357014941858006583808342990722432352533907974611981194066078942144 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.18871252523357014941858006583808342990722432352533907974611981194066078942144
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.19741918599664555346456677627625719332733560211347364106625299561610682779506
Short name T935
Test name
Test status
Simulation time 624328106 ps
CPU time 1867 seconds
Started Nov 22 02:07:07 PM PST 23
Finished Nov 22 02:38:20 PM PST 23
Peak memory 498172 kb
Host smart-f1cd3a62-3e40-4434-8177-1ea5deadf375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=19741918599664555346456677627625719332733560211347364106625299561610682779506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sra
m_ctrl_stress_all_with_rand_reset.19741918599664555346456677627625719332733560211347364106625299561610682779506
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.14743301300654775287851155011431637967381987683963806015961233918616580609137
Short name T847
Test name
Test status
Simulation time 9325508496 ps
CPU time 421.06 seconds
Started Nov 22 02:07:22 PM PST 23
Finished Nov 22 02:14:24 PM PST 23
Peak memory 202888 kb
Host smart-b239321d-52d1-4cf0-956e-788c31a2f19a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14743301300654775287851155011431637967381987683963806015961233918616580609137
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.1474330130065477528785115501143163796738198768396380
6015961233918616580609137
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.78771247127464952379127593013889199909048709415022672961673004368133133125020
Short name T429
Test name
Test status
Simulation time 1371125703 ps
CPU time 125.65 seconds
Started Nov 22 02:07:02 PM PST 23
Finished Nov 22 02:09:09 PM PST 23
Peak memory 351192 kb
Host smart-9ea5dc39-2e13-4237-9b0a-56d88a942a74
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787712471274649523791275930138891999090487094150226729
61673004368133133125020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.78771247127464952379127
593013889199909048709415022672961673004368133133125020
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.82196554509378104856162792360530432840324419977751300044328031162210558545865
Short name T789
Test name
Test status
Simulation time 13467153934 ps
CPU time 968.47 seconds
Started Nov 22 02:12:35 PM PST 23
Finished Nov 22 02:28:45 PM PST 23
Peak memory 378756 kb
Host smart-29cc4670-6c2e-4866-b06d-59efe4a6a2f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82196554509378104856162792360530432840324419977751300044328031162210558545865
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during_key_req.821965545093781048561627923605304328403
24419977751300044328031162210558545865
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.81038312005076686062904662127424311099887466279261974599003092754770193948802
Short name T558
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:13:00 PM PST 23
Finished Nov 22 02:13:01 PM PST 23
Peak memory 202488 kb
Host smart-23317c07-872a-4bcd-8193-9faa2e4669d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810383120050766860629046621274243110998874662792619745990030927547
70193948802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.810383120050766860629046621274243110998874662792619745
99003092754770193948802
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.13107051609915471190359102953453716355993457973583740788751231226912045363400
Short name T28
Test name
Test status
Simulation time 295482808505 ps
CPU time 2735.84 seconds
Started Nov 22 02:12:33 PM PST 23
Finished Nov 22 02:58:10 PM PST 23
Peak memory 202776 kb
Host smart-f5cb40a1-8ee1-47b2-bd65-2d27512cc398
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13107051609915471190359102953453716355993457973583740788751231226912045363400 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.13107051609915471190359102953453716355993457973583740788751231226912045363400
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.85363066048326301784789382061960063199987850837889198856006753302135514450941
Short name T516
Test name
Test status
Simulation time 31712811539 ps
CPU time 862.04 seconds
Started Nov 22 02:12:32 PM PST 23
Finished Nov 22 02:26:55 PM PST 23
Peak memory 368068 kb
Host smart-3cac9bd4-de10-418d-9c35-4ff08bfcbec1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85363066048326301784789382061960063199987850837889198856006753302135514450941 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.85363066048326301784789382061960063199987850837889198856006753302135514450941
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.85609703325282521030450817882248964397810277221177813794518098137665040336228
Short name T273
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.61 seconds
Started Nov 22 02:12:51 PM PST 23
Finished Nov 22 02:14:36 PM PST 23
Peak memory 211052 kb
Host smart-db6c9a94-c263-4600-8024-fd0cb20306b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85609703325282521030450817882248964397810277221177813794518098137665040336228 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.85609703325282521030450817882248964397810277221177813794518098137665040336228
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.75285702035325743248002636375230304621570401374031542536826317271618965560595
Short name T109
Test name
Test status
Simulation time 1342947357 ps
CPU time 126.64 seconds
Started Nov 22 02:12:34 PM PST 23
Finished Nov 22 02:14:41 PM PST 23
Peak memory 351224 kb
Host smart-69c2cb99-815f-47c2-9fd4-12c053c5ae8e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7528570203532574324800263637523030462157040137403154253
6826317271618965560595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_max_throughput.75285702035325743248002636375230304
621570401374031542536826317271618965560595
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.65767587816148386748878622607329826489370748418893207071675035948014465317603
Short name T729
Test name
Test status
Simulation time 4750777237 ps
CPU time 80.34 seconds
Started Nov 22 02:12:50 PM PST 23
Finished Nov 22 02:14:11 PM PST 23
Peak memory 212220 kb
Host smart-09e614e8-0b40-4c30-a596-b2cefb872267
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65767587816148386748878622607329826489370748418893207071675035948014
465317603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.657675878161483867488786226073298264893707484188
93207071675035948014465317603
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.42346466323676235252446395125191902899281353333970629061511913990276394426708
Short name T820
Test name
Test status
Simulation time 18445453393 ps
CPU time 158.41 seconds
Started Nov 22 02:12:50 PM PST 23
Finished Nov 22 02:15:29 PM PST 23
Peak memory 202792 kb
Host smart-a54b2f30-48bd-4c99-8c5c-8b177cb1cb11
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42346466323676235252446395125191902899281353333970629061511913990276394426708
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.42346466323676235252446395125191902899281353333970629061511913990276394426708
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.20402959751433360530044875468736197282173733133224801406507280190660384319092
Short name T576
Test name
Test status
Simulation time 28731174678 ps
CPU time 881.43 seconds
Started Nov 22 02:12:33 PM PST 23
Finished Nov 22 02:27:16 PM PST 23
Peak memory 378664 kb
Host smart-28b6b21f-eaa4-4c1e-8e5d-b44250fd12ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402959751433360530044875468736197282173733133224801406507280190660384319092 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.20402959751433360530044875468736197282173733133224801406507280190660384319092
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.24733939036341673376904423564052340010247309885288924425919733467043290622495
Short name T755
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.08 seconds
Started Nov 22 02:12:33 PM PST 23
Finished Nov 22 02:12:51 PM PST 23
Peak memory 245628 kb
Host smart-398eaf07-a1fe-4f6f-9c0d-d1be87efb959
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247339390363416733769044235640523400102473098852889244259197334670432
90622495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.247339390363416733769044235640523400102473098852889244
25919733467043290622495
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.109823630389452689175761857477618364572170425174809755981973149286528447492145
Short name T911
Test name
Test status
Simulation time 45083829570 ps
CPU time 562.65 seconds
Started Nov 22 02:12:33 PM PST 23
Finished Nov 22 02:21:56 PM PST 23
Peak memory 202776 kb
Host smart-f508364f-b47f-4d9d-9cf2-2db24ae2d917
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109823630389452689175761857477618364572170425174809755981973149286528
447492145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access_b2b.109823630389452689175761857477618364572
170425174809755981973149286528447492145
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.77205332449846106363383983845960975436321745440888347756694133632699537437556
Short name T721
Test name
Test status
Simulation time 607542526 ps
CPU time 6.02 seconds
Started Nov 22 02:12:50 PM PST 23
Finished Nov 22 02:12:57 PM PST 23
Peak memory 203108 kb
Host smart-aa0a80b2-dae2-4ae3-9ce0-8af920ad86ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77205332449846106363383983845960975436321745440888347756694133632699537437556 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.77205332449846106363383983845960975436321745440888347756694133632699537437556
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.61669075240175882145540177414045291532733876611704292110849414594322095994638
Short name T714
Test name
Test status
Simulation time 19913691647 ps
CPU time 641.78 seconds
Started Nov 22 02:12:53 PM PST 23
Finished Nov 22 02:23:35 PM PST 23
Peak memory 372536 kb
Host smart-ff48fa69-6db6-4a20-a5bf-8858f96cad9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61669075240175882145540177414045291532733876611704292110849414594322095994638 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.61669075240175882145540177414045291532733876611704292110849414594322095994638
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.36887264514257275799314783952763603469380595870190357822941446764161648491178
Short name T309
Test name
Test status
Simulation time 988289480 ps
CPU time 16.32 seconds
Started Nov 22 02:12:35 PM PST 23
Finished Nov 22 02:12:52 PM PST 23
Peak memory 245664 kb
Host smart-a9af58e9-8217-4b8f-9494-c9c830ae5010
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36887264514257275799314783952763603469380595870190357822941446764161648491178 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.36887264514257275799314783952763603469380595870190357822941446764161648491178
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.23589700146980345047941371167549403051587223642539718879805256891926629174092
Short name T495
Test name
Test status
Simulation time 624328106 ps
CPU time 1663.19 seconds
Started Nov 22 02:12:52 PM PST 23
Finished Nov 22 02:40:36 PM PST 23
Peak memory 498160 kb
Host smart-3067e6a0-087b-45c8-9d0d-5da99e84f714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=23589700146980345047941371167549403051587223642539718879805256891926629174092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sr
am_ctrl_stress_all_with_rand_reset.23589700146980345047941371167549403051587223642539718879805256891926629174092
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3591757767892938191842997359468518659942778069412005941295332692362298373310
Short name T761
Test name
Test status
Simulation time 9325508496 ps
CPU time 425.96 seconds
Started Nov 22 02:12:53 PM PST 23
Finished Nov 22 02:19:59 PM PST 23
Peak memory 202900 kb
Host smart-ab32cc41-c302-4ce2-9ce9-2d9bd702616f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591757767892938191842997359468518659942778069412005941295332692362298373310
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.3591757767892938191842997359468518659942778069412005
941295332692362298373310
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.111361904846248141806797983085832339261721084748630704594850873801500897833952
Short name T106
Test name
Test status
Simulation time 1371125703 ps
CPU time 125.97 seconds
Started Nov 22 02:12:51 PM PST 23
Finished Nov 22 02:14:58 PM PST 23
Peak memory 351304 kb
Host smart-d9055514-86da-4fc3-ae01-0a894e0ea45f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111361904846248141806797983085832339261721084748630704
594850873801500897833952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.111361904846248141806
797983085832339261721084748630704594850873801500897833952
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.87005508989434857250588017944937022246687607173719053345334914326967039694655
Short name T462
Test name
Test status
Simulation time 13467153934 ps
CPU time 934.5 seconds
Started Nov 22 02:12:57 PM PST 23
Finished Nov 22 02:28:32 PM PST 23
Peak memory 378776 kb
Host smart-0b9cf04e-eee3-4865-aa14-0b17d29ca5cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87005508989434857250588017944937022246687607173719053345334914326967039694655
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during_key_req.870055089894348572505880179449370222466
87607173719053345334914326967039694655
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.42151710758020254534406361365622310981144422707564633759089823259910968859536
Short name T399
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:13:00 PM PST 23
Finished Nov 22 02:13:02 PM PST 23
Peak memory 202608 kb
Host smart-1c6c31cc-2514-41a8-a99b-1de1d9b92acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421517107580202545344063613656223109811444227075646337590898232599
10968859536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.421517107580202545344063613656223109811444227075646337
59089823259910968859536
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.46352732074536492390406864795074519939749554109025799605002587390601713520292
Short name T858
Test name
Test status
Simulation time 295482808505 ps
CPU time 2720.5 seconds
Started Nov 22 02:12:58 PM PST 23
Finished Nov 22 02:58:20 PM PST 23
Peak memory 202852 kb
Host smart-c540c545-3e2b-4d7d-9686-49b45eaa8a01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46352732074536492390406864795074519939749554109025799605002587390601713520292 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.46352732074536492390406864795074519939749554109025799605002587390601713520292
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.52060595081352575001880108066294764577471840817677277488188545252546621906701
Short name T931
Test name
Test status
Simulation time 31712811539 ps
CPU time 1092.94 seconds
Started Nov 22 02:12:53 PM PST 23
Finished Nov 22 02:31:06 PM PST 23
Peak memory 368024 kb
Host smart-9f6af127-a5bf-4c3f-96bb-f27e7246d2fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52060595081352575001880108066294764577471840817677277488188545252546621906701 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.52060595081352575001880108066294764577471840817677277488188545252546621906701
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.43994856128588555525273055961296683220065455778841762636991650823090089085651
Short name T604
Test name
Test status
Simulation time 19084394710 ps
CPU time 103.84 seconds
Started Nov 22 02:12:36 PM PST 23
Finished Nov 22 02:14:21 PM PST 23
Peak memory 211020 kb
Host smart-cdf67c91-21a7-444a-9d6e-e349e4507936
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43994856128588555525273055961296683220065455778841762636991650823090089085651 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.43994856128588555525273055961296683220065455778841762636991650823090089085651
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.114428881117759822274332829858417188683914053283653169309775787642761818623445
Short name T747
Test name
Test status
Simulation time 1342947357 ps
CPU time 148.12 seconds
Started Nov 22 02:13:00 PM PST 23
Finished Nov 22 02:15:29 PM PST 23
Peak memory 351112 kb
Host smart-88cf9f11-69a2-4aee-843b-d13811260c1e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144288811177598222743328298584171886839140532836531693
09775787642761818623445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_max_throughput.1144288811177598222743328298584171
88683914053283653169309775787642761818623445
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.13268264982215206276778147542145249668781680441815245666726115094576849400234
Short name T627
Test name
Test status
Simulation time 4750777237 ps
CPU time 77.48 seconds
Started Nov 22 02:13:00 PM PST 23
Finished Nov 22 02:14:18 PM PST 23
Peak memory 212172 kb
Host smart-00d2edc5-c088-4ebd-94e7-9b3005f93c75
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13268264982215206276778147542145249668781680441815245666726115094576
849400234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.132682649822152062767781475421452496687816804418
15245666726115094576849400234
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.6151432524917473670957831809249674551659515830610337373335634251756157139605
Short name T819
Test name
Test status
Simulation time 18445453393 ps
CPU time 162.79 seconds
Started Nov 22 02:12:58 PM PST 23
Finished Nov 22 02:15:42 PM PST 23
Peak memory 202780 kb
Host smart-e53976a0-5b92-47b1-8f86-8f0e8a5e6db0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6151432524917473670957831809249674551659515830610337373335634251756157139605 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.6151432524917473670957831809249674551659515830610337373335634251756157139605
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.113916024150543722347091873669021126661478505806789977481315512876119331944131
Short name T497
Test name
Test status
Simulation time 28731174678 ps
CPU time 769.2 seconds
Started Nov 22 02:12:43 PM PST 23
Finished Nov 22 02:25:33 PM PST 23
Peak memory 378656 kb
Host smart-d87a8c9c-91df-4871-9c90-e13028e28c25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113916024150543722347091873669021126661478505806789977481315512876119331944131 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.113916024150543722347091873669021126661478505806789977481315512876119331944131
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.18152810040112457980884965760832168778159691643678979616247765076335008824332
Short name T739
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.78 seconds
Started Nov 22 02:12:54 PM PST 23
Finished Nov 22 02:13:15 PM PST 23
Peak memory 245652 kb
Host smart-a3ea0afd-026b-4a9b-9efd-2e9d4118c067
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181528100401124579808849657608321687781596916436789796162477650763350
08824332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.181528100401124579808849657608321687781596916436789796
16247765076335008824332
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.14916066366019188013817332907561445929843487301293462894922154340215793481789
Short name T843
Test name
Test status
Simulation time 45083829570 ps
CPU time 588.27 seconds
Started Nov 22 02:13:00 PM PST 23
Finished Nov 22 02:22:49 PM PST 23
Peak memory 202768 kb
Host smart-c835efb0-2873-45c6-8182-aa6fe57a5dd5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149160663660191880138173329075614459298434873012934628949221543402157
93481789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access_b2b.1491606636601918801381733290756144592984
3487301293462894922154340215793481789
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.14041097237628763952611545808716246664724584401093342282041253484302015198069
Short name T676
Test name
Test status
Simulation time 607542526 ps
CPU time 6.18 seconds
Started Nov 22 02:12:58 PM PST 23
Finished Nov 22 02:13:05 PM PST 23
Peak memory 203088 kb
Host smart-efce2c2f-b6ec-4c61-96a4-a16cb042e6ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14041097237628763952611545808716246664724584401093342282041253484302015198069 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.14041097237628763952611545808716246664724584401093342282041253484302015198069
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.30218398886526219127427501308770666935269123411816508797937106938723464036315
Short name T574
Test name
Test status
Simulation time 19913691647 ps
CPU time 589.13 seconds
Started Nov 22 02:13:00 PM PST 23
Finished Nov 22 02:22:49 PM PST 23
Peak memory 372448 kb
Host smart-0f5107fc-0368-4b29-8abf-400f7abba9db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30218398886526219127427501308770666935269123411816508797937106938723464036315 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.30218398886526219127427501308770666935269123411816508797937106938723464036315
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.33300377311285779323759311637419609822511684732842485311079495780310124427366
Short name T258
Test name
Test status
Simulation time 988289480 ps
CPU time 19.25 seconds
Started Nov 22 02:12:53 PM PST 23
Finished Nov 22 02:13:13 PM PST 23
Peak memory 245652 kb
Host smart-b0729a48-1b2e-4f31-8663-a06c24d186a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33300377311285779323759311637419609822511684732842485311079495780310124427366 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.33300377311285779323759311637419609822511684732842485311079495780310124427366
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.66779462821097208800694726783957806909832144979360577696364894981957680547016
Short name T523
Test name
Test status
Simulation time 624328106 ps
CPU time 1884.59 seconds
Started Nov 22 02:13:01 PM PST 23
Finished Nov 22 02:44:26 PM PST 23
Peak memory 498088 kb
Host smart-c71f26b0-95a7-40dc-b28b-c0ec58160df9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=66779462821097208800694726783957806909832144979360577696364894981957680547016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sr
am_ctrl_stress_all_with_rand_reset.66779462821097208800694726783957806909832144979360577696364894981957680547016
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.93278992181250049782501954643462756384936951172277503721829603117386964381698
Short name T774
Test name
Test status
Simulation time 9325508496 ps
CPU time 423.46 seconds
Started Nov 22 02:12:59 PM PST 23
Finished Nov 22 02:20:03 PM PST 23
Peak memory 202888 kb
Host smart-fa1e5e3b-d59e-489c-9985-e4cea38c7f8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93278992181250049782501954643462756384936951172277503721829603117386964381698
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.932789921812500497825019546434627563849369511722775
03721829603117386964381698
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.48825259845798022767200028753861049400760937746506998988676448170247884889594
Short name T356
Test name
Test status
Simulation time 1371125703 ps
CPU time 114.09 seconds
Started Nov 22 02:12:58 PM PST 23
Finished Nov 22 02:14:52 PM PST 23
Peak memory 351096 kb
Host smart-fdffaa5b-bc43-442a-a5e6-13f60b4d6eca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488252598457980227672000287538610494007609377465069989
88676448170247884889594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.4882525984579802276720
0028753861049400760937746506998988676448170247884889594
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.9860163381422896432748056959347849865992449636858510788991077708701263614674
Short name T869
Test name
Test status
Simulation time 13467153934 ps
CPU time 1053.54 seconds
Started Nov 22 02:13:16 PM PST 23
Finished Nov 22 02:30:50 PM PST 23
Peak memory 380872 kb
Host smart-66156813-f213-4a76-8934-90865a0ed0b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9860163381422896432748056959347849865992449636858510788991077708701263614674
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during_key_req.9860163381422896432748056959347849865992
449636858510788991077708701263614674
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.48568844147245060302533813889880592125809687553411803930634236574000490022464
Short name T249
Test name
Test status
Simulation time 16600825 ps
CPU time 0.65 seconds
Started Nov 22 02:13:15 PM PST 23
Finished Nov 22 02:13:16 PM PST 23
Peak memory 202612 kb
Host smart-e48cb9ea-bd9c-4849-a018-c6d4212093f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485688441472450603025338138898805921258096875534118039306342365740
00490022464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.485688441472450603025338138898805921258096875534118039
30634236574000490022464
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.59782266868987338606195520368936906557864729103549503881119867098082984943543
Short name T700
Test name
Test status
Simulation time 295482808505 ps
CPU time 2722.85 seconds
Started Nov 22 02:12:59 PM PST 23
Finished Nov 22 02:58:23 PM PST 23
Peak memory 202708 kb
Host smart-15b16255-9134-4417-aaae-033470a09bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59782266868987338606195520368936906557864729103549503881119867098082984943543 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.59782266868987338606195520368936906557864729103549503881119867098082984943543
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.71563913326519892822028640137520369132629392939645287227117133477806660235257
Short name T651
Test name
Test status
Simulation time 31712811539 ps
CPU time 918.87 seconds
Started Nov 22 02:13:13 PM PST 23
Finished Nov 22 02:28:33 PM PST 23
Peak memory 368036 kb
Host smart-322b7b7a-af2c-4b9d-9e0b-60f51d4b5dfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71563913326519892822028640137520369132629392939645287227117133477806660235257 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.71563913326519892822028640137520369132629392939645287227117133477806660235257
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.50280806647767012242414628701299182613613945969423241292411933440182576109679
Short name T638
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.27 seconds
Started Nov 22 02:13:13 PM PST 23
Finished Nov 22 02:14:58 PM PST 23
Peak memory 210984 kb
Host smart-b16935e7-6166-49e7-be10-bb2da1488a39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50280806647767012242414628701299182613613945969423241292411933440182576109679 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.50280806647767012242414628701299182613613945969423241292411933440182576109679
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.34048450681017480580066035426612861224344785977502090976074876426973209628910
Short name T591
Test name
Test status
Simulation time 1342947357 ps
CPU time 130.75 seconds
Started Nov 22 02:13:13 PM PST 23
Finished Nov 22 02:15:25 PM PST 23
Peak memory 351140 kb
Host smart-edde75b9-4ccd-4e6c-bec0-6eb044d7374f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404845068101748058006603542661286122434478597750209097
6074876426973209628910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_max_throughput.34048450681017480580066035426612861
224344785977502090976074876426973209628910
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.22034230303643971210186712465717928281006311417036508654684250112181019392913
Short name T414
Test name
Test status
Simulation time 4750777237 ps
CPU time 76.68 seconds
Started Nov 22 02:13:15 PM PST 23
Finished Nov 22 02:14:32 PM PST 23
Peak memory 212336 kb
Host smart-4b8117db-eccc-42e4-a530-104d39025199
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22034230303643971210186712465717928281006311417036508654684250112181
019392913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.220342303036439712101867124657179282810063114170
36508654684250112181019392913
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.60332625588961380605464988759955797232267163517443960741982021080486071559153
Short name T621
Test name
Test status
Simulation time 18445453393 ps
CPU time 153.09 seconds
Started Nov 22 02:13:20 PM PST 23
Finished Nov 22 02:15:54 PM PST 23
Peak memory 202796 kb
Host smart-bce6e227-f05b-4ded-bb91-f312c2bbd7dc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60332625588961380605464988759955797232267163517443960741982021080486071559153
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.60332625588961380605464988759955797232267163517443960741982021080486071559153
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.50780868758909995715816472527083983392890962046176981924413088604943299530356
Short name T640
Test name
Test status
Simulation time 28731174678 ps
CPU time 785.8 seconds
Started Nov 22 02:13:00 PM PST 23
Finished Nov 22 02:26:07 PM PST 23
Peak memory 378560 kb
Host smart-0e6f43ac-6c83-4758-9e31-f391e18e7a93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50780868758909995715816472527083983392890962046176981924413088604943299530356 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.50780868758909995715816472527083983392890962046176981924413088604943299530356
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.38722444175317569349361949199798417655504605441764003214724436737637192292908
Short name T278
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.11 seconds
Started Nov 22 02:13:16 PM PST 23
Finished Nov 22 02:13:36 PM PST 23
Peak memory 245728 kb
Host smart-fdd9d776-d529-4c6c-afad-9eff0245accb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387224441753175693493619491997984176555046054417640032147244367376371
92292908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.387224441753175693493619491997984176555046054417640032
14724436737637192292908
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2194083945625318622486001997661311636624764113469753261085004815199613404945
Short name T93
Test name
Test status
Simulation time 45083829570 ps
CPU time 576.81 seconds
Started Nov 22 02:13:16 PM PST 23
Finished Nov 22 02:22:54 PM PST 23
Peak memory 202972 kb
Host smart-2ad39214-8cd7-46be-a3a3-651d7349d182
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219408394562531862248600199766131163662476411346975326108500481519961
3404945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access_b2b.21940839456253186224860019976613116366247
64113469753261085004815199613404945
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.112595673139969423302761350653929880488086862174129521582901150347982825981044
Short name T300
Test name
Test status
Simulation time 607542526 ps
CPU time 6.1 seconds
Started Nov 22 02:13:15 PM PST 23
Finished Nov 22 02:13:21 PM PST 23
Peak memory 203044 kb
Host smart-c7e9fe9f-ab78-4426-a0b8-ab81d8a71f44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112595673139969423302761350653929880488086862174129521582901150347982825981044 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.112595673139969423302761350653929880488086862174129521582901150347982825981044
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.88447987956252265996281810433023539989116634681470028382372802795046727248933
Short name T294
Test name
Test status
Simulation time 19913691647 ps
CPU time 531.97 seconds
Started Nov 22 02:13:14 PM PST 23
Finished Nov 22 02:22:07 PM PST 23
Peak memory 372600 kb
Host smart-8d89264f-3f0a-4b55-ad96-0a3a4e657508
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88447987956252265996281810433023539989116634681470028382372802795046727248933 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.88447987956252265996281810433023539989116634681470028382372802795046727248933
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.62860671088627549536922132272296249565458883443062697827328165403107262861026
Short name T851
Test name
Test status
Simulation time 988289480 ps
CPU time 16.09 seconds
Started Nov 22 02:12:59 PM PST 23
Finished Nov 22 02:13:16 PM PST 23
Peak memory 245500 kb
Host smart-780ab739-9435-4198-ae3a-253d5fbacc84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62860671088627549536922132272296249565458883443062697827328165403107262861026 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.62860671088627549536922132272296249565458883443062697827328165403107262861026
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.98407341398966671863374533412619110409604878517931381949257732086084829268211
Short name T927
Test name
Test status
Simulation time 624328106 ps
CPU time 1964.76 seconds
Started Nov 22 02:13:21 PM PST 23
Finished Nov 22 02:46:07 PM PST 23
Peak memory 498196 kb
Host smart-d0f3eb5f-6563-4184-aeb0-f2f8028b9478
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=98407341398966671863374533412619110409604878517931381949257732086084829268211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sr
am_ctrl_stress_all_with_rand_reset.98407341398966671863374533412619110409604878517931381949257732086084829268211
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.58710148265580561083822536944393564019026291173096509275899463882919306624363
Short name T95
Test name
Test status
Simulation time 9325508496 ps
CPU time 422.18 seconds
Started Nov 22 02:12:58 PM PST 23
Finished Nov 22 02:20:00 PM PST 23
Peak memory 202960 kb
Host smart-c8c99101-c604-4824-b2bd-7e05cb700fa7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58710148265580561083822536944393564019026291173096509275899463882919306624363
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.587101482655805610838225369443935640190262911730965
09275899463882919306624363
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.50422925436755349559165612712339394426129096377039814733896493596340499791567
Short name T119
Test name
Test status
Simulation time 1371125703 ps
CPU time 128.35 seconds
Started Nov 22 02:13:14 PM PST 23
Finished Nov 22 02:15:23 PM PST 23
Peak memory 351180 kb
Host smart-4389630f-aea1-476c-a439-323c47700d3d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504229254367553495591656127123393944261290963770398147
33896493596340499791567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.5042292543675534955916
5612712339394426129096377039814733896493596340499791567
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.45300542004848483107714264862310996003520060989240096293365018819707382032655
Short name T508
Test name
Test status
Simulation time 13467153934 ps
CPU time 1108.39 seconds
Started Nov 22 02:13:16 PM PST 23
Finished Nov 22 02:31:45 PM PST 23
Peak memory 378756 kb
Host smart-1206f32c-36f2-4aac-8885-0926d8b69911
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45300542004848483107714264862310996003520060989240096293365018819707382032655
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during_key_req.453005420048484831077142648623109960035
20060989240096293365018819707382032655
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.40112574239276150679232205024462922440169366073088670972693242233351416207775
Short name T624
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:13:49 PM PST 23
Finished Nov 22 02:13:50 PM PST 23
Peak memory 202504 kb
Host smart-ac98e571-087e-47e3-b7ae-e6828a3d8fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401125742392761506792322050244629224401693660730886709726932422333
51416207775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.401125742392761506792322050244629224401693660730886709
72693242233351416207775
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.12413211755757316004029160477983487431493895491157424830080914763121753971105
Short name T245
Test name
Test status
Simulation time 295482808505 ps
CPU time 2718.88 seconds
Started Nov 22 02:13:20 PM PST 23
Finished Nov 22 02:58:40 PM PST 23
Peak memory 202880 kb
Host smart-c4a6ebb1-7786-485f-a0f3-2ff017b3e3e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12413211755757316004029160477983487431493895491157424830080914763121753971105 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.12413211755757316004029160477983487431493895491157424830080914763121753971105
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.23672169165983942869688336583350555320526685259825489231026442356703682246139
Short name T704
Test name
Test status
Simulation time 31712811539 ps
CPU time 909.27 seconds
Started Nov 22 02:13:15 PM PST 23
Finished Nov 22 02:28:25 PM PST 23
Peak memory 367980 kb
Host smart-fd4dbc90-3b51-419d-8392-e3572fc08e07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23672169165983942869688336583350555320526685259825489231026442356703682246139 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.23672169165983942869688336583350555320526685259825489231026442356703682246139
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.47055454269059721263546711477190845552841418087099070088495043684607772948851
Short name T503
Test name
Test status
Simulation time 19084394710 ps
CPU time 101.52 seconds
Started Nov 22 02:13:18 PM PST 23
Finished Nov 22 02:15:00 PM PST 23
Peak memory 211036 kb
Host smart-6362e541-3c37-4840-bb74-ca28e5bce334
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47055454269059721263546711477190845552841418087099070088495043684607772948851 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.47055454269059721263546711477190845552841418087099070088495043684607772948851
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.6455075806798252180675612855339997341219162403905519454016978026673448571441
Short name T8
Test name
Test status
Simulation time 1342947357 ps
CPU time 117.82 seconds
Started Nov 22 02:13:19 PM PST 23
Finished Nov 22 02:15:17 PM PST 23
Peak memory 351148 kb
Host smart-1692b3c3-d1d1-426f-8161-62049b35d42f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6455075806798252180675612855339997341219162403905519454
016978026673448571441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_max_throughput.645507580679825218067561285533999734
1219162403905519454016978026673448571441
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.18925083120601703775492371549462810071916905587280283461098992410929064244262
Short name T977
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.29 seconds
Started Nov 22 02:13:15 PM PST 23
Finished Nov 22 02:14:34 PM PST 23
Peak memory 212344 kb
Host smart-46bec243-5f41-4f7d-88e7-f6a4b1d73b7f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18925083120601703775492371549462810071916905587280283461098992410929
064244262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.189250831206017037754923715494628100719169055872
80283461098992410929064244262
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.45207178340446478158572213375079247072247992646523552230514385242789496090838
Short name T861
Test name
Test status
Simulation time 18445453393 ps
CPU time 157.71 seconds
Started Nov 22 02:13:19 PM PST 23
Finished Nov 22 02:15:57 PM PST 23
Peak memory 202752 kb
Host smart-d40dd919-d986-4da4-844b-d52f628e9bde
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45207178340446478158572213375079247072247992646523552230514385242789496090838
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.45207178340446478158572213375079247072247992646523552230514385242789496090838
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.40051652075309415904579464463883329634569313755080422721263487566286835362365
Short name T405
Test name
Test status
Simulation time 28731174678 ps
CPU time 746.42 seconds
Started Nov 22 02:13:16 PM PST 23
Finished Nov 22 02:25:43 PM PST 23
Peak memory 378748 kb
Host smart-a78455e8-f4d9-4995-ade7-aedd774ce696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40051652075309415904579464463883329634569313755080422721263487566286835362365 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.40051652075309415904579464463883329634569313755080422721263487566286835362365
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.83600253138806848663026411176868948544752890812342804393257793126116297235181
Short name T530
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.71 seconds
Started Nov 22 02:13:14 PM PST 23
Finished Nov 22 02:13:34 PM PST 23
Peak memory 245624 kb
Host smart-819d6553-a7df-42b6-9694-4c39fae228f1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836002531388068486630264111768689485447528908123428043932577931261162
97235181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.836002531388068486630264111768689485447528908123428043
93257793126116297235181
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.52976986384827756141646158154957112644369480703274485987565608689977404484814
Short name T725
Test name
Test status
Simulation time 45083829570 ps
CPU time 573.11 seconds
Started Nov 22 02:13:12 PM PST 23
Finished Nov 22 02:22:46 PM PST 23
Peak memory 202848 kb
Host smart-78479cd7-831c-497a-9e02-330b2a523dbb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529769863848277561416461581549571126443694807032744859875656086899774
04484814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access_b2b.5297698638482775614164615815495711264436
9480703274485987565608689977404484814
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.74325632490492450018417728132142480039230782308761865320097341515564610106516
Short name T490
Test name
Test status
Simulation time 607542526 ps
CPU time 6.1 seconds
Started Nov 22 02:13:43 PM PST 23
Finished Nov 22 02:13:50 PM PST 23
Peak memory 203044 kb
Host smart-943f0fde-fa03-47b1-a957-2c2b34c9bc82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74325632490492450018417728132142480039230782308761865320097341515564610106516 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.74325632490492450018417728132142480039230782308761865320097341515564610106516
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.4233760943593005474905764455524659628575727815591181160064700526410616497037
Short name T41
Test name
Test status
Simulation time 19913691647 ps
CPU time 570.22 seconds
Started Nov 22 02:13:16 PM PST 23
Finished Nov 22 02:22:47 PM PST 23
Peak memory 372572 kb
Host smart-31d35f78-1e7e-4aaf-8a8b-378ca22a1faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233760943593005474905764455524659628575727815591181160064700526410616497037 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.4233760943593005474905764455524659628575727815591181160064700526410616497037
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.6287094297135588737948991784245067098462845026704555244479870518368220343572
Short name T339
Test name
Test status
Simulation time 988289480 ps
CPU time 15.64 seconds
Started Nov 22 02:13:13 PM PST 23
Finished Nov 22 02:13:29 PM PST 23
Peak memory 245532 kb
Host smart-a992a009-d75a-45b2-bb7a-8ee18d40b078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6287094297135588737948991784245067098462845026704555244479870518368220343572 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.6287094297135588737948991784245067098462845026704555244479870518368220343572
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.50331177651817338490068289073433692023931774842934929404410292265404676764621
Short name T298
Test name
Test status
Simulation time 624328106 ps
CPU time 1794.54 seconds
Started Nov 22 02:13:16 PM PST 23
Finished Nov 22 02:43:11 PM PST 23
Peak memory 498228 kb
Host smart-ef15cc9e-c09b-4d25-b11e-b7cf6257f912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=50331177651817338490068289073433692023931774842934929404410292265404676764621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sr
am_ctrl_stress_all_with_rand_reset.50331177651817338490068289073433692023931774842934929404410292265404676764621
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.35756850921890578285149376383755458514939378583386466604697764667285653619687
Short name T470
Test name
Test status
Simulation time 9325508496 ps
CPU time 449.84 seconds
Started Nov 22 02:13:16 PM PST 23
Finished Nov 22 02:20:46 PM PST 23
Peak memory 202952 kb
Host smart-9f497f9a-4392-456d-ab6a-8bd21ad01b76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35756850921890578285149376383755458514939378583386466604697764667285653619687
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.357568509218905782851493763837554585149393785833864
66604697764667285653619687
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.109604443241149142447747349082883098446234135615133525806930269931869296924781
Short name T422
Test name
Test status
Simulation time 1371125703 ps
CPU time 127.88 seconds
Started Nov 22 02:13:19 PM PST 23
Finished Nov 22 02:15:28 PM PST 23
Peak memory 351172 kb
Host smart-8f7fe704-39fe-4d90-a501-f412096eaa4d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109604443241149142447747349082883098446234135615133525
806930269931869296924781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.109604443241149142447
747349082883098446234135615133525806930269931869296924781
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.57841287435760943475030617422491507418047484714906900206727074407154369053488
Short name T688
Test name
Test status
Simulation time 13467153934 ps
CPU time 856.19 seconds
Started Nov 22 02:13:44 PM PST 23
Finished Nov 22 02:28:01 PM PST 23
Peak memory 378684 kb
Host smart-a7d0dafd-2149-477b-8ed6-440704e642d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57841287435760943475030617422491507418047484714906900206727074407154369053488
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during_key_req.578412874357609434750306174224915074180
47484714906900206727074407154369053488
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.47009931853501751822633900891696687225640163613539209896437379113610433244517
Short name T256
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:13:53 PM PST 23
Finished Nov 22 02:13:55 PM PST 23
Peak memory 202540 kb
Host smart-1e5e86a7-12b9-4fb1-a7a4-972e8d6f4066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470099318535017518226339008916966872256401636135392098964373791136
10433244517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.470099318535017518226339008916966872256401636135392098
96437379113610433244517
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.90025672945876178608009589305346524391740509088008383048339726684972658725476
Short name T622
Test name
Test status
Simulation time 295482808505 ps
CPU time 2873.69 seconds
Started Nov 22 02:13:44 PM PST 23
Finished Nov 22 03:01:39 PM PST 23
Peak memory 202904 kb
Host smart-ea529861-9a9e-4bea-82da-543c91939b69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90025672945876178608009589305346524391740509088008383048339726684972658725476 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.90025672945876178608009589305346524391740509088008383048339726684972658725476
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.3099644964393052079182846923050628032584283630858998756114176262210296772476
Short name T925
Test name
Test status
Simulation time 31712811539 ps
CPU time 773.34 seconds
Started Nov 22 02:13:44 PM PST 23
Finished Nov 22 02:26:38 PM PST 23
Peak memory 368024 kb
Host smart-7981ea83-8f59-426b-ab29-32ebdeb75fe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099644964393052079182846923050628032584283630858998756114176262210296772476 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.3099644964393052079182846923050628032584283630858998756114176262210296772476
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.38996845127948848087303887649161762893801936993627798631522621580561082990404
Short name T762
Test name
Test status
Simulation time 19084394710 ps
CPU time 103.6 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:15:38 PM PST 23
Peak memory 211116 kb
Host smart-4960f638-3cc5-4a90-8068-7145c09323cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38996845127948848087303887649161762893801936993627798631522621580561082990404 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.38996845127948848087303887649161762893801936993627798631522621580561082990404
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.43422598264552219197252824198045238425661466275795939094855708537789576397420
Short name T509
Test name
Test status
Simulation time 1342947357 ps
CPU time 126.02 seconds
Started Nov 22 02:13:51 PM PST 23
Finished Nov 22 02:15:57 PM PST 23
Peak memory 351092 kb
Host smart-18048b87-d937-4469-a01c-bb88ad8b685e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4342259826455221919725282419804523842566146627579593909
4855708537789576397420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_max_throughput.43422598264552219197252824198045238
425661466275795939094855708537789576397420
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.37856441497490735232772385923192005821807448481636337015073599833146732624949
Short name T727
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.81 seconds
Started Nov 22 02:13:44 PM PST 23
Finished Nov 22 02:15:03 PM PST 23
Peak memory 212328 kb
Host smart-2f02f766-d6c5-4532-b985-9f305ee162a4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37856441497490735232772385923192005821807448481636337015073599833146
732624949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.378564414974907352327723859231920058218074484816
36337015073599833146732624949
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.42712161618016160535776313570838128066713168120733352703604264421258816910461
Short name T321
Test name
Test status
Simulation time 18445453393 ps
CPU time 160.71 seconds
Started Nov 22 02:13:57 PM PST 23
Finished Nov 22 02:16:38 PM PST 23
Peak memory 202868 kb
Host smart-535c4b0b-e5ad-41ea-a1e8-5af48ccd01ad
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42712161618016160535776313570838128066713168120733352703604264421258816910461
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.42712161618016160535776313570838128066713168120733352703604264421258816910461
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.105383713462397021567072893922416741329690904156088892323633774376861263016050
Short name T228
Test name
Test status
Simulation time 28731174678 ps
CPU time 828.76 seconds
Started Nov 22 02:13:45 PM PST 23
Finished Nov 22 02:27:34 PM PST 23
Peak memory 378676 kb
Host smart-a6edba81-0ca5-4872-aa07-07d023cfdbdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105383713462397021567072893922416741329690904156088892323633774376861263016050 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.105383713462397021567072893922416741329690904156088892323633774376861263016050
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.76435445624249256566200485885414182411273931763989745273586104681313418928545
Short name T920
Test name
Test status
Simulation time 1006378621 ps
CPU time 20.5 seconds
Started Nov 22 02:13:51 PM PST 23
Finished Nov 22 02:14:12 PM PST 23
Peak memory 245672 kb
Host smart-121b5884-9248-4e0f-b1e5-6c8f45f758e2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764354456242492565662004858854141824112739317639897452735861046813134
18928545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.764354456242492565662004858854141824112739317639897452
73586104681313418928545
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.29300716446572105425899103246774172552581449230974231690264115150399148413246
Short name T662
Test name
Test status
Simulation time 45083829570 ps
CPU time 585.08 seconds
Started Nov 22 02:13:50 PM PST 23
Finished Nov 22 02:23:36 PM PST 23
Peak memory 202828 kb
Host smart-9b884e42-8a77-46b3-820f-ab6c7c026957
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293007164465721054258991032467741725525814492309742316902641151503991
48413246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access_b2b.2930071644657210542589910324677417255258
1449230974231690264115150399148413246
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.18654861670807026311102307689073720556760269949793297072790370784858065587922
Short name T35
Test name
Test status
Simulation time 607542526 ps
CPU time 6.1 seconds
Started Nov 22 02:13:53 PM PST 23
Finished Nov 22 02:14:00 PM PST 23
Peak memory 203116 kb
Host smart-2222f332-454b-4868-bf3b-4c8f888c6f0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18654861670807026311102307689073720556760269949793297072790370784858065587922 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.18654861670807026311102307689073720556760269949793297072790370784858065587922
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.70499092221266894607616050484857890638629600176435354811222638997285105301227
Short name T697
Test name
Test status
Simulation time 19913691647 ps
CPU time 664.36 seconds
Started Nov 22 02:13:44 PM PST 23
Finished Nov 22 02:24:49 PM PST 23
Peak memory 372528 kb
Host smart-9efbfd6d-514d-4783-89ea-aa229bed5026
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70499092221266894607616050484857890638629600176435354811222638997285105301227 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.70499092221266894607616050484857890638629600176435354811222638997285105301227
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.58654544257864788318216591203616402170986608831095972987178799702674952796718
Short name T89
Test name
Test status
Simulation time 988289480 ps
CPU time 17.71 seconds
Started Nov 22 02:13:35 PM PST 23
Finished Nov 22 02:13:53 PM PST 23
Peak memory 245728 kb
Host smart-11b04618-98c3-4b57-92d2-cdc1c0e00522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58654544257864788318216591203616402170986608831095972987178799702674952796718 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.58654544257864788318216591203616402170986608831095972987178799702674952796718
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.97220560141677314473211484740640901714418148156349795239775307860330700307554
Short name T284
Test name
Test status
Simulation time 624328106 ps
CPU time 1760.52 seconds
Started Nov 22 02:13:43 PM PST 23
Finished Nov 22 02:43:04 PM PST 23
Peak memory 498188 kb
Host smart-4674416e-c092-4f95-a815-607906723849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=97220560141677314473211484740640901714418148156349795239775307860330700307554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sr
am_ctrl_stress_all_with_rand_reset.97220560141677314473211484740640901714418148156349795239775307860330700307554
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.27426022085729766674751374854834151155836438771779133591600830096275855047108
Short name T796
Test name
Test status
Simulation time 9325508496 ps
CPU time 423.65 seconds
Started Nov 22 02:13:43 PM PST 23
Finished Nov 22 02:20:48 PM PST 23
Peak memory 202816 kb
Host smart-8d2e76fd-a562-4ddb-b6fb-9eaead3488a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27426022085729766674751374854834151155836438771779133591600830096275855047108
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.274260220857297666747513748548341511558364387717791
33591600830096275855047108
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.22845984289649760749501583469985013976370074580370087382748655387970001193841
Short name T449
Test name
Test status
Simulation time 1371125703 ps
CPU time 93.93 seconds
Started Nov 22 02:13:47 PM PST 23
Finished Nov 22 02:15:22 PM PST 23
Peak memory 351216 kb
Host smart-7d432c4c-9745-4754-a4d7-86d9acf1197f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228459842896497607495015834699850139763700745803700873
82748655387970001193841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.2284598428964976074950
1583469985013976370074580370087382748655387970001193841
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.7595557551495408345890688385717838124103723376122669723041087092211042780840
Short name T985
Test name
Test status
Simulation time 13467153934 ps
CPU time 875.34 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:28:30 PM PST 23
Peak memory 380756 kb
Host smart-6d3f9049-01b6-4718-9e6a-81fcf769d3c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7595557551495408345890688385717838124103723376122669723041087092211042780840
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during_key_req.7595557551495408345890688385717838124103
723376122669723041087092211042780840
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.41593127561462716651218751305360598510639211929372587150205020070000829677148
Short name T259
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 02:13:55 PM PST 23
Finished Nov 22 02:13:56 PM PST 23
Peak memory 202636 kb
Host smart-87a15bf8-358e-41b7-93a1-0da3468e458a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415931275614627166512187513053605985106392119293725871502050200700
00829677148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.415931275614627166512187513053605985106392119293725871
50205020070000829677148
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.106238657245000166460704836953804349648957106403812299804654974575796600421221
Short name T361
Test name
Test status
Simulation time 295482808505 ps
CPU time 2803.48 seconds
Started Nov 22 02:13:44 PM PST 23
Finished Nov 22 03:00:29 PM PST 23
Peak memory 202884 kb
Host smart-595f7280-bd7a-48f5-9793-06869c2c1bba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106238657245000166460704836953804349648957106403812299804654974575796600421221 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.106238657245000166460704836953804349648957106403812299804654974575796600421221
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.59360450927184922350318137319970383978422944506573837226970694775579872379886
Short name T926
Test name
Test status
Simulation time 31712811539 ps
CPU time 820.78 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:27:35 PM PST 23
Peak memory 367968 kb
Host smart-24d78155-a454-493f-8054-571e82b6fe3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59360450927184922350318137319970383978422944506573837226970694775579872379886 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.59360450927184922350318137319970383978422944506573837226970694775579872379886
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.105735745859239714550126216054104341743823974451986059801971799018579941350782
Short name T46
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.41 seconds
Started Nov 22 02:13:51 PM PST 23
Finished Nov 22 02:15:37 PM PST 23
Peak memory 211072 kb
Host smart-74cd0038-6a5b-416a-9b0b-4870a649e7bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105735745859239714550126216054104341743823974451986059801971799018579941350782 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.105735745859239714550126216054104341743823974451986059801971799018579941350782
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.82542735823679971968124154923093732584354056901400777369656096718520420624167
Short name T535
Test name
Test status
Simulation time 1342947357 ps
CPU time 114.56 seconds
Started Nov 22 02:13:56 PM PST 23
Finished Nov 22 02:15:51 PM PST 23
Peak memory 351252 kb
Host smart-865b53cc-fc76-4d31-a701-99e79c679ac7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8254273582367997196812415492309373258435405690140077736
9656096718520420624167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_max_throughput.82542735823679971968124154923093732
584354056901400777369656096718520420624167
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.18983872577140397262285234310276238180882536759025680447600814477702019495658
Short name T944
Test name
Test status
Simulation time 4750777237 ps
CPU time 75.83 seconds
Started Nov 22 02:13:51 PM PST 23
Finished Nov 22 02:15:07 PM PST 23
Peak memory 212244 kb
Host smart-50e850e8-dec7-45b3-9d3e-e03df7fabfa4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18983872577140397262285234310276238180882536759025680447600814477702
019495658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.189838725771403972622852343102762381808825367590
25680447600814477702019495658
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.3787605747663566589653501336423557669704648376062180293613486594139466630314
Short name T525
Test name
Test status
Simulation time 18445453393 ps
CPU time 155.38 seconds
Started Nov 22 02:13:53 PM PST 23
Finished Nov 22 02:16:29 PM PST 23
Peak memory 202820 kb
Host smart-fc7a8957-cfde-4b76-b63f-a069cd147176
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787605747663566589653501336423557669704648376062180293613486594139466630314 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.3787605747663566589653501336423557669704648376062180293613486594139466630314
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.48419650153612422391004466968134835744611991398717678184239095631678436848615
Short name T487
Test name
Test status
Simulation time 28731174678 ps
CPU time 712.43 seconds
Started Nov 22 02:13:35 PM PST 23
Finished Nov 22 02:25:28 PM PST 23
Peak memory 378700 kb
Host smart-d8f19983-bb7f-4622-ad1b-59a14ae3b3c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48419650153612422391004466968134835744611991398717678184239095631678436848615 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.48419650153612422391004466968134835744611991398717678184239095631678436848615
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.131998598740320006165766882993740871803682390575337490236361048014685742755
Short name T825
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.35 seconds
Started Nov 22 02:13:50 PM PST 23
Finished Nov 22 02:14:10 PM PST 23
Peak memory 245608 kb
Host smart-36d3c1cb-5ef1-49e9-8e27-c75e1f76824a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131998598740320006165766882993740871803682390575337490236361048014685
742755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.13199859874032000616576688299374087180368239057533749023
6361048014685742755
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.82594608290622981656886664116019337970390838767514373096132369432183153320509
Short name T707
Test name
Test status
Simulation time 45083829570 ps
CPU time 558.41 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:23:13 PM PST 23
Peak memory 202864 kb
Host smart-81d6626d-b412-4507-8581-dfbbaa6c67e3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825946082906229816568866641160193379703908387675143730961323694321831
53320509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access_b2b.8259460829062298165688666411601933797039
0838767514373096132369432183153320509
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.16422829074147680226309656381506859755731452506845646241199584519875679319436
Short name T748
Test name
Test status
Simulation time 607542526 ps
CPU time 6.2 seconds
Started Nov 22 02:13:50 PM PST 23
Finished Nov 22 02:13:57 PM PST 23
Peak memory 203128 kb
Host smart-0bb86d79-87a1-41e0-af03-fe89d2bd9407
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16422829074147680226309656381506859755731452506845646241199584519875679319436 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.16422829074147680226309656381506859755731452506845646241199584519875679319436
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.67753774373124696901902254268741198761427253250953962291220871580657437186656
Short name T482
Test name
Test status
Simulation time 19913691647 ps
CPU time 571.85 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:23:26 PM PST 23
Peak memory 372540 kb
Host smart-d1ace51e-144a-451e-b86d-8e07aedc3f6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67753774373124696901902254268741198761427253250953962291220871580657437186656 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.67753774373124696901902254268741198761427253250953962291220871580657437186656
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.72764243242055576377797031815972742092803987276508424912917560799603360530765
Short name T492
Test name
Test status
Simulation time 988289480 ps
CPU time 18.38 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:14:13 PM PST 23
Peak memory 245584 kb
Host smart-2acdd874-af86-4d0f-862c-b825d6c42702
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72764243242055576377797031815972742092803987276508424912917560799603360530765 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.72764243242055576377797031815972742092803987276508424912917560799603360530765
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.77245224098620096529204608192522844056165793863675417431385092306223543280150
Short name T279
Test name
Test status
Simulation time 624328106 ps
CPU time 1689.74 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:42:04 PM PST 23
Peak memory 498200 kb
Host smart-0e58cac4-6862-4fdb-9f11-aa586d2b29d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=77245224098620096529204608192522844056165793863675417431385092306223543280150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sr
am_ctrl_stress_all_with_rand_reset.77245224098620096529204608192522844056165793863675417431385092306223543280150
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.16703936748779888319512421074963763645227585013470315227134503395099491157703
Short name T857
Test name
Test status
Simulation time 9325508496 ps
CPU time 423.31 seconds
Started Nov 22 02:13:36 PM PST 23
Finished Nov 22 02:20:40 PM PST 23
Peak memory 202888 kb
Host smart-51aa5173-b312-49c9-8905-79f0c5795841
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16703936748779888319512421074963763645227585013470315227134503395099491157703
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.167039367487798883195124210749637636452275850134703
15227134503395099491157703
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2089528353824115406358661095669777566762333457080584780429040194877062703734
Short name T971
Test name
Test status
Simulation time 1371125703 ps
CPU time 146.15 seconds
Started Nov 22 02:13:45 PM PST 23
Finished Nov 22 02:16:11 PM PST 23
Peak memory 351188 kb
Host smart-ca2e7614-37d4-48ce-afdc-bd886bfcb4f1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208952835382411540635866109566977756676233345708058478
0429040194877062703734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.20895283538241154063586
61095669777566762333457080584780429040194877062703734
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.24313659124725377436310875378817160362214016990333398726375481454907415410461
Short name T655
Test name
Test status
Simulation time 13467153934 ps
CPU time 1032.67 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:31:08 PM PST 23
Peak memory 378740 kb
Host smart-b213d696-12bc-42f6-8880-36b48bf8ed36
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24313659124725377436310875378817160362214016990333398726375481454907415410461
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during_key_req.243136591247253774363108753788171603622
14016990333398726375481454907415410461
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.56441651653424492419244037852764964143242147274954343708119820238220878987194
Short name T23
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:14:00 PM PST 23
Finished Nov 22 02:14:01 PM PST 23
Peak memory 202616 kb
Host smart-db7f63c9-4371-4c64-a81e-07434609e4f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564416516534244924192440378527649641432421472749543437081198202382
20878987194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.564416516534244924192440378527649641432421472749543437
08119820238220878987194
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.82406194974144047800143352229854403540799263565529924460388912512757720737037
Short name T366
Test name
Test status
Simulation time 295482808505 ps
CPU time 2753.23 seconds
Started Nov 22 02:13:55 PM PST 23
Finished Nov 22 02:59:49 PM PST 23
Peak memory 202844 kb
Host smart-80a15675-fd0c-4406-af8d-17c9b4887da9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82406194974144047800143352229854403540799263565529924460388912512757720737037 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.82406194974144047800143352229854403540799263565529924460388912512757720737037
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.19162857130371756830822059441080555334183144800423173168107226046942689626600
Short name T734
Test name
Test status
Simulation time 31712811539 ps
CPU time 966.26 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:30:01 PM PST 23
Peak memory 367996 kb
Host smart-62c1729c-f6f5-4133-b689-08da31b8c4fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19162857130371756830822059441080555334183144800423173168107226046942689626600 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.19162857130371756830822059441080555334183144800423173168107226046942689626600
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.67329332952058922945642249174726527429766224749108391727788495556164746876486
Short name T601
Test name
Test status
Simulation time 19084394710 ps
CPU time 108.04 seconds
Started Nov 22 02:13:56 PM PST 23
Finished Nov 22 02:15:45 PM PST 23
Peak memory 211160 kb
Host smart-8df059e2-c091-400f-8ab2-d48e7e1c950e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67329332952058922945642249174726527429766224749108391727788495556164746876486 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.67329332952058922945642249174726527429766224749108391727788495556164746876486
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.25108693211950500984868047189456142667064276053533111616361686209926538048151
Short name T781
Test name
Test status
Simulation time 1342947357 ps
CPU time 124.35 seconds
Started Nov 22 02:13:51 PM PST 23
Finished Nov 22 02:15:56 PM PST 23
Peak memory 351176 kb
Host smart-d7c8c23a-c8de-451c-a3f1-618827e10425
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510869321195050098486804718945614266706427605353311161
6361686209926538048151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_max_throughput.25108693211950500984868047189456142
667064276053533111616361686209926538048151
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.93505251794622152016126605513988972438779658139999489105786245575448690076461
Short name T330
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.53 seconds
Started Nov 22 02:13:55 PM PST 23
Finished Nov 22 02:15:14 PM PST 23
Peak memory 212320 kb
Host smart-2b19b60c-5ca4-4b92-8861-d9659211dee6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93505251794622152016126605513988972438779658139999489105786245575448
690076461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.935052517946221520161266055139889724387796581399
99489105786245575448690076461
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.32612139772642488741598567946352540368182443053041850634039526652087108386671
Short name T855
Test name
Test status
Simulation time 18445453393 ps
CPU time 160.79 seconds
Started Nov 22 02:13:53 PM PST 23
Finished Nov 22 02:16:34 PM PST 23
Peak memory 202736 kb
Host smart-3afce447-5355-419b-9999-e2b25c4d9701
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32612139772642488741598567946352540368182443053041850634039526652087108386671
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.32612139772642488741598567946352540368182443053041850634039526652087108386671
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.68130848788928886928546010829478924491658255496206760688048741083185055707381
Short name T528
Test name
Test status
Simulation time 28731174678 ps
CPU time 762.69 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:26:37 PM PST 23
Peak memory 378684 kb
Host smart-f54d3569-3e2b-4f6e-ba6a-8129e68979cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68130848788928886928546010829478924491658255496206760688048741083185055707381 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.68130848788928886928546010829478924491658255496206760688048741083185055707381
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.10921809800050932710144433032066066416644024550310773592664632854836618626898
Short name T813
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.86 seconds
Started Nov 22 02:13:55 PM PST 23
Finished Nov 22 02:14:14 PM PST 23
Peak memory 245616 kb
Host smart-ad16ad78-3595-422e-b3de-f84ad78f3bef
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109218098000509327101444330320660664166440245503107735926646328548366
18626898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.109218098000509327101444330320660664166440245503107735
92664632854836618626898
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.46839457415934113709443131573439204873889836457048269574615436742410584857317
Short name T39
Test name
Test status
Simulation time 45083829570 ps
CPU time 565.73 seconds
Started Nov 22 02:13:56 PM PST 23
Finished Nov 22 02:23:22 PM PST 23
Peak memory 202808 kb
Host smart-8259e5ca-b4bd-4bab-9544-6ec58920ba13
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468394574159341137094431315734392048738898364570482695746154367424105
84857317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access_b2b.4683945741593411370944313157343920487388
9836457048269574615436742410584857317
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.90064635712808067412079882097767192872270137362768380461657575604886466813141
Short name T590
Test name
Test status
Simulation time 607542526 ps
CPU time 6.02 seconds
Started Nov 22 02:13:56 PM PST 23
Finished Nov 22 02:14:03 PM PST 23
Peak memory 203068 kb
Host smart-638169e5-d56a-45a5-b1df-cf09c073db97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90064635712808067412079882097767192872270137362768380461657575604886466813141 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.90064635712808067412079882097767192872270137362768380461657575604886466813141
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.27390867141873846985196151950074682826199651653645963784366783079832572832297
Short name T103
Test name
Test status
Simulation time 19913691647 ps
CPU time 643.74 seconds
Started Nov 22 02:13:57 PM PST 23
Finished Nov 22 02:24:41 PM PST 23
Peak memory 372608 kb
Host smart-c595130c-ade8-44f7-852b-f3b1338808ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27390867141873846985196151950074682826199651653645963784366783079832572832297 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.27390867141873846985196151950074682826199651653645963784366783079832572832297
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.27704790670124467001105854140054500124803481838083736108649035019460982657045
Short name T643
Test name
Test status
Simulation time 988289480 ps
CPU time 19.09 seconds
Started Nov 22 02:13:52 PM PST 23
Finished Nov 22 02:14:11 PM PST 23
Peak memory 245660 kb
Host smart-a7a89226-f3c5-4fba-a0e7-90193fce3d07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27704790670124467001105854140054500124803481838083736108649035019460982657045 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.27704790670124467001105854140054500124803481838083736108649035019460982657045
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.22654687715587345850730870738958311374303617989186370526970421370032874057416
Short name T332
Test name
Test status
Simulation time 624328106 ps
CPU time 1738.75 seconds
Started Nov 22 02:13:56 PM PST 23
Finished Nov 22 02:42:56 PM PST 23
Peak memory 498136 kb
Host smart-00a1ffce-e9ff-4f5c-93a9-f2b8edc79f68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=22654687715587345850730870738958311374303617989186370526970421370032874057416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sr
am_ctrl_stress_all_with_rand_reset.22654687715587345850730870738958311374303617989186370526970421370032874057416
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.86449957788710387246433180365943389279850804715818089217761387546567262228108
Short name T705
Test name
Test status
Simulation time 9325508496 ps
CPU time 431.23 seconds
Started Nov 22 02:13:54 PM PST 23
Finished Nov 22 02:21:06 PM PST 23
Peak memory 202868 kb
Host smart-5b9d7f93-0b8b-4974-8bb1-955ce836183d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86449957788710387246433180365943389279850804715818089217761387546567262228108
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.864499577887103872464331803659433892798508047158180
89217761387546567262228108
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.43664551500023086314312109946927838294049480572673008516510763831938645113811
Short name T975
Test name
Test status
Simulation time 1371125703 ps
CPU time 128.91 seconds
Started Nov 22 02:13:56 PM PST 23
Finished Nov 22 02:16:06 PM PST 23
Peak memory 351224 kb
Host smart-366d648d-3992-463a-ab14-d95c36e0bdfd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436645515000230863143121099469278382940494805726730085
16510763831938645113811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.4366455150002308631431
2109946927838294049480572673008516510763831938645113811
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.32251814890815425101713039508760785658414571067421583345450416916288317157924
Short name T696
Test name
Test status
Simulation time 13467153934 ps
CPU time 935.2 seconds
Started Nov 22 02:13:57 PM PST 23
Finished Nov 22 02:29:33 PM PST 23
Peak memory 378784 kb
Host smart-85a12b44-392c-4b6f-a59e-40b5acee4689
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32251814890815425101713039508760785658414571067421583345450416916288317157924
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during_key_req.322518148908154251017130395087607856584
14571067421583345450416916288317157924
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.29113145535570614229278822599195154624423538817568696063561914574577253584832
Short name T360
Test name
Test status
Simulation time 16600825 ps
CPU time 0.67 seconds
Started Nov 22 02:14:15 PM PST 23
Finished Nov 22 02:14:17 PM PST 23
Peak memory 202580 kb
Host smart-ff7eb9bc-1f62-4961-aa1b-a1f8845c0638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291131455355706142292788225991951546244235388175686960635619145745
77253584832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.291131455355706142292788225991951546244235388175686960
63561914574577253584832
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.96423693120682871844179731739397830129225443534172134511732452501015727380271
Short name T476
Test name
Test status
Simulation time 295482808505 ps
CPU time 2744.57 seconds
Started Nov 22 02:14:00 PM PST 23
Finished Nov 22 02:59:46 PM PST 23
Peak memory 202912 kb
Host smart-fcc7a9bb-eee9-41fd-b3f0-eae7ba1d26cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96423693120682871844179731739397830129225443534172134511732452501015727380271 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.96423693120682871844179731739397830129225443534172134511732452501015727380271
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.77321349434825344506951295511706132948161952149860269189180163368108642427573
Short name T110
Test name
Test status
Simulation time 31712811539 ps
CPU time 891.71 seconds
Started Nov 22 02:14:03 PM PST 23
Finished Nov 22 02:28:56 PM PST 23
Peak memory 368044 kb
Host smart-718813ed-9108-41a6-9f4d-8f06bff35120
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77321349434825344506951295511706132948161952149860269189180163368108642427573 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.77321349434825344506951295511706132948161952149860269189180163368108642427573
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.13922202754422007563679635669044858673985856476183440229687729762609455301476
Short name T644
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.28 seconds
Started Nov 22 02:14:00 PM PST 23
Finished Nov 22 02:15:46 PM PST 23
Peak memory 211108 kb
Host smart-d24e6ac1-b6a2-4732-8504-2ed17be8f883
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13922202754422007563679635669044858673985856476183440229687729762609455301476 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.13922202754422007563679635669044858673985856476183440229687729762609455301476
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.111646539978171940174325245772602202607362092792568388919896422221463369468715
Short name T896
Test name
Test status
Simulation time 1342947357 ps
CPU time 124.31 seconds
Started Nov 22 02:13:58 PM PST 23
Finished Nov 22 02:16:03 PM PST 23
Peak memory 351188 kb
Host smart-40af6109-7d83-410a-ae91-a64672f4d1b4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116465399781719401743252457726022026073620927925683889
19896422221463369468715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_max_throughput.1116465399781719401743252457726022
02607362092792568388919896422221463369468715
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.23521227892992050481506459782818898248365787857963315782061513243004755332531
Short name T73
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.89 seconds
Started Nov 22 02:14:06 PM PST 23
Finished Nov 22 02:15:25 PM PST 23
Peak memory 212280 kb
Host smart-8649e175-5949-471c-a6fd-21d41dc3f249
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23521227892992050481506459782818898248365787857963315782061513243004
755332531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.235212278929920504815064597828188982483657878579
63315782061513243004755332531
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.81697929558535171023819641888257190651015120544831737204769541553884406981156
Short name T117
Test name
Test status
Simulation time 18445453393 ps
CPU time 158.9 seconds
Started Nov 22 02:14:05 PM PST 23
Finished Nov 22 02:16:44 PM PST 23
Peak memory 202832 kb
Host smart-31672c62-f8a7-425f-b9a6-2bf97512698e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81697929558535171023819641888257190651015120544831737204769541553884406981156
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.81697929558535171023819641888257190651015120544831737204769541553884406981156
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.97916272559070598216534974644199870563403238829379214474535707665343245197188
Short name T968
Test name
Test status
Simulation time 28731174678 ps
CPU time 758.46 seconds
Started Nov 22 02:13:58 PM PST 23
Finished Nov 22 02:26:37 PM PST 23
Peak memory 378664 kb
Host smart-c71c63ac-2efb-4486-b501-9e9701dcaab2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97916272559070598216534974644199870563403238829379214474535707665343245197188 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.97916272559070598216534974644199870563403238829379214474535707665343245197188
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.1658576409713877934228031121432536503320478115628595325358155453050594001116
Short name T799
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.31 seconds
Started Nov 22 02:13:58 PM PST 23
Finished Nov 22 02:14:18 PM PST 23
Peak memory 245616 kb
Host smart-6d5c180e-a354-4826-adf1-4d0b9b889005
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165857640971387793422803112143253650332047811562859532535815545305059
4001116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.1658576409713877934228031121432536503320478115628595325
358155453050594001116
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3912857692180187091634343275057729694712985576983234506400826128209271071454
Short name T658
Test name
Test status
Simulation time 45083829570 ps
CPU time 571.85 seconds
Started Nov 22 02:13:56 PM PST 23
Finished Nov 22 02:23:28 PM PST 23
Peak memory 202708 kb
Host smart-6b91061a-0392-425c-8763-15b20cf17984
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391285769218018709163434327505772969471298557698323450640082612820927
1071454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access_b2b.39128576921801870916343432750577296947129
85576983234506400826128209271071454
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.29892131953870217019591829075175051950974601523394236013484661345104477007967
Short name T233
Test name
Test status
Simulation time 607542526 ps
CPU time 6.19 seconds
Started Nov 22 02:14:06 PM PST 23
Finished Nov 22 02:14:12 PM PST 23
Peak memory 203104 kb
Host smart-d9a47cf2-8f3b-483f-84da-80f114cce7c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29892131953870217019591829075175051950974601523394236013484661345104477007967 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.29892131953870217019591829075175051950974601523394236013484661345104477007967
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.20544292802065967355302111219794036027174447096697887547177875173258391927392
Short name T358
Test name
Test status
Simulation time 19913691647 ps
CPU time 701.5 seconds
Started Nov 22 02:14:05 PM PST 23
Finished Nov 22 02:25:47 PM PST 23
Peak memory 372492 kb
Host smart-a607e234-87ee-4785-af7d-107d3cb70ce9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20544292802065967355302111219794036027174447096697887547177875173258391927392 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.20544292802065967355302111219794036027174447096697887547177875173258391927392
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.59130077269332144754624207384779390510731667630577599282406785677226398531904
Short name T609
Test name
Test status
Simulation time 988289480 ps
CPU time 16.77 seconds
Started Nov 22 02:13:57 PM PST 23
Finished Nov 22 02:14:14 PM PST 23
Peak memory 245696 kb
Host smart-2328b5eb-dae6-4ae5-b038-f161190d99fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59130077269332144754624207384779390510731667630577599282406785677226398531904 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.59130077269332144754624207384779390510731667630577599282406785677226398531904
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.92676551723609765351919628593224785630783488136129682761241577651247746940723
Short name T720
Test name
Test status
Simulation time 624328106 ps
CPU time 1966.73 seconds
Started Nov 22 02:14:06 PM PST 23
Finished Nov 22 02:46:53 PM PST 23
Peak memory 498124 kb
Host smart-79580603-b18e-428e-a986-4ff39dc87657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=92676551723609765351919628593224785630783488136129682761241577651247746940723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sr
am_ctrl_stress_all_with_rand_reset.92676551723609765351919628593224785630783488136129682761241577651247746940723
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.50820689106156364250526105498521638840896272198827071661969277832583220051116
Short name T667
Test name
Test status
Simulation time 9325508496 ps
CPU time 425.79 seconds
Started Nov 22 02:14:09 PM PST 23
Finished Nov 22 02:21:16 PM PST 23
Peak memory 202896 kb
Host smart-a2568b47-14f5-4de2-bd60-fe77ce993636
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50820689106156364250526105498521638840896272198827071661969277832583220051116
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.508206891061563642505261054985216388408962721988270
71661969277832583220051116
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.100711183190809799664911073565198779292460675659868794974912425814391001072761
Short name T347
Test name
Test status
Simulation time 1371125703 ps
CPU time 111.78 seconds
Started Nov 22 02:13:57 PM PST 23
Finished Nov 22 02:15:50 PM PST 23
Peak memory 351208 kb
Host smart-73f4ac30-3ef8-4dab-8a10-dfeefb9c54f4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100711183190809799664911073565198779292460675659868794
974912425814391001072761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.100711183190809799664
911073565198779292460675659868794974912425814391001072761
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.39976662087478753278685201731720148200670744756107484754664912030121228433107
Short name T690
Test name
Test status
Simulation time 13467153934 ps
CPU time 998.27 seconds
Started Nov 22 02:14:14 PM PST 23
Finished Nov 22 02:30:53 PM PST 23
Peak memory 378756 kb
Host smart-a4e878b5-0134-41ec-ac63-9b958abcc919
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39976662087478753278685201731720148200670744756107484754664912030121228433107
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during_key_req.399766620874787532786852017317201482006
70744756107484754664912030121228433107
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.97614114071954600221686701157841540554439682623616371082011414814663327927963
Short name T904
Test name
Test status
Simulation time 16600825 ps
CPU time 0.66 seconds
Started Nov 22 02:14:14 PM PST 23
Finished Nov 22 02:14:16 PM PST 23
Peak memory 202580 kb
Host smart-9c5f6365-fffc-4699-beca-a12744d1de58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976141140719546002216867011578415405544396826236163710820114148146
63327927963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.976141140719546002216867011578415405544396826236163710
82011414814663327927963
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.92689978700679257941619839138590611267192047765859015416645152136972671156154
Short name T928
Test name
Test status
Simulation time 295482808505 ps
CPU time 2717.24 seconds
Started Nov 22 02:14:14 PM PST 23
Finished Nov 22 02:59:32 PM PST 23
Peak memory 202844 kb
Host smart-c3dfa4ad-e8ef-4065-a511-b8cad616ab7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92689978700679257941619839138590611267192047765859015416645152136972671156154 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.92689978700679257941619839138590611267192047765859015416645152136972671156154
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.24850411772512343546780149649407070098601955816738127979618165647025442118519
Short name T865
Test name
Test status
Simulation time 31712811539 ps
CPU time 873.81 seconds
Started Nov 22 02:14:12 PM PST 23
Finished Nov 22 02:28:47 PM PST 23
Peak memory 368044 kb
Host smart-ae166959-7e1e-4457-8db9-75c99aa67445
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24850411772512343546780149649407070098601955816738127979618165647025442118519 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.24850411772512343546780149649407070098601955816738127979618165647025442118519
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.58745901258272105434505511935918947060969362343087706512222051339355486497249
Short name T830
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.59 seconds
Started Nov 22 02:14:14 PM PST 23
Finished Nov 22 02:16:00 PM PST 23
Peak memory 211044 kb
Host smart-6d39ec90-4855-4341-b6f0-6afaa561a149
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58745901258272105434505511935918947060969362343087706512222051339355486497249 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.58745901258272105434505511935918947060969362343087706512222051339355486497249
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.62014475693522555095737417963038931917201104754555959548572855415888252960077
Short name T441
Test name
Test status
Simulation time 1342947357 ps
CPU time 129.39 seconds
Started Nov 22 02:14:15 PM PST 23
Finished Nov 22 02:16:25 PM PST 23
Peak memory 351172 kb
Host smart-a4181248-309e-4f28-8e2b-9cc2ec5f740e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6201447569352255509573741796303893191720110475455595954
8572855415888252960077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_max_throughput.62014475693522555095737417963038931
917201104754555959548572855415888252960077
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.46448542111123012523554749767215596187416991673085447059586058117769436811531
Short name T902
Test name
Test status
Simulation time 4750777237 ps
CPU time 80.45 seconds
Started Nov 22 02:14:11 PM PST 23
Finished Nov 22 02:15:32 PM PST 23
Peak memory 212328 kb
Host smart-815ff904-5d94-4aca-8289-13bc6e7fa14e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46448542111123012523554749767215596187416991673085447059586058117769
436811531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.464485421111230125235547497672155961874169916730
85447059586058117769436811531
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.43445554546756780472162189314871689616694950558740811654575175739403566550351
Short name T541
Test name
Test status
Simulation time 18445453393 ps
CPU time 157.44 seconds
Started Nov 22 02:14:15 PM PST 23
Finished Nov 22 02:16:53 PM PST 23
Peak memory 202776 kb
Host smart-30c702db-14e5-464f-95d9-1850e26d77bf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43445554546756780472162189314871689616694950558740811654575175739403566550351
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.43445554546756780472162189314871689616694950558740811654575175739403566550351
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.97811685290178731894810901566673963354123597239128445328467806743929147403281
Short name T990
Test name
Test status
Simulation time 28731174678 ps
CPU time 765.2 seconds
Started Nov 22 02:14:12 PM PST 23
Finished Nov 22 02:26:58 PM PST 23
Peak memory 378684 kb
Host smart-e89760e0-0a88-4724-8250-af0e23f1fc97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97811685290178731894810901566673963354123597239128445328467806743929147403281 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.97811685290178731894810901566673963354123597239128445328467806743929147403281
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.31208411551668938474994102731603016385629722745421333908127112692566992356798
Short name T226
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.87 seconds
Started Nov 22 02:14:10 PM PST 23
Finished Nov 22 02:14:29 PM PST 23
Peak memory 245572 kb
Host smart-e87b93ca-ec07-4981-9b8d-6311a928e74e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312084115516689384749941027316030163856297227454213339081271126925669
92356798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.312084115516689384749941027316030163856297227454213339
08127112692566992356798
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3966901297996731689350867286084208421775509841119222539361240825291728535947
Short name T568
Test name
Test status
Simulation time 45083829570 ps
CPU time 585.12 seconds
Started Nov 22 02:14:10 PM PST 23
Finished Nov 22 02:23:56 PM PST 23
Peak memory 202884 kb
Host smart-0eabebe4-5810-4888-beb5-150d9a67d6bd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396690129799673168935086728608420842177550984111922253936124082529172
8535947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access_b2b.39669012979967316893508672860842084217755
09841119222539361240825291728535947
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.38992787188562896944100470688980070434798143572461016918544391810603204104673
Short name T597
Test name
Test status
Simulation time 607542526 ps
CPU time 6.18 seconds
Started Nov 22 02:14:12 PM PST 23
Finished Nov 22 02:14:19 PM PST 23
Peak memory 203116 kb
Host smart-48c03149-dd6f-4ac0-bc8e-fa64c3c4abf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38992787188562896944100470688980070434798143572461016918544391810603204104673 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.38992787188562896944100470688980070434798143572461016918544391810603204104673
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.37041799974621041045825550250519013707424750443396161953149256720587711145310
Short name T344
Test name
Test status
Simulation time 19913691647 ps
CPU time 588.56 seconds
Started Nov 22 02:14:11 PM PST 23
Finished Nov 22 02:24:00 PM PST 23
Peak memory 372536 kb
Host smart-68aec929-8a65-44dd-935a-d48031ef3c91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37041799974621041045825550250519013707424750443396161953149256720587711145310 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.37041799974621041045825550250519013707424750443396161953149256720587711145310
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.34379266823024498249891533738120674017793041968688210019472624054456822136806
Short name T116
Test name
Test status
Simulation time 988289480 ps
CPU time 18.5 seconds
Started Nov 22 02:14:15 PM PST 23
Finished Nov 22 02:14:34 PM PST 23
Peak memory 245652 kb
Host smart-f9a5c2f6-c252-4d54-9077-9d263482ed89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34379266823024498249891533738120674017793041968688210019472624054456822136806 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.34379266823024498249891533738120674017793041968688210019472624054456822136806
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.43711491722633257954107230264484795133901709726591275619355688742405780974775
Short name T318
Test name
Test status
Simulation time 624328106 ps
CPU time 1815.35 seconds
Started Nov 22 02:14:12 PM PST 23
Finished Nov 22 02:44:28 PM PST 23
Peak memory 498184 kb
Host smart-c805e573-a617-422e-bfcf-588cada19d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=43711491722633257954107230264484795133901709726591275619355688742405780974775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sr
am_ctrl_stress_all_with_rand_reset.43711491722633257954107230264484795133901709726591275619355688742405780974775
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.110040884733603922689838384802443488492934970032287782646750352484944106176295
Short name T808
Test name
Test status
Simulation time 9325508496 ps
CPU time 427.02 seconds
Started Nov 22 02:14:16 PM PST 23
Finished Nov 22 02:21:23 PM PST 23
Peak memory 202920 kb
Host smart-3a975057-4537-4d7d-ae2c-86710211d722
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11004088473360392268983838480244348849293497003228778264675035248494410617629
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.11004088473360392268983838480244348849293497003228
7782646750352484944106176295
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.114933525505018457542553349484964217492102511163555677704625760087811960908481
Short name T595
Test name
Test status
Simulation time 1371125703 ps
CPU time 104.77 seconds
Started Nov 22 02:14:15 PM PST 23
Finished Nov 22 02:16:00 PM PST 23
Peak memory 351208 kb
Host smart-2fc21ca3-8b8c-43dc-b6ed-baf9585b2f8a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114933525505018457542553349484964217492102511163555677
704625760087811960908481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.114933525505018457542
553349484964217492102511163555677704625760087811960908481
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.30663530816260711234860790461112851246668083223002720215699564777756787117923
Short name T527
Test name
Test status
Simulation time 13467153934 ps
CPU time 898.75 seconds
Started Nov 22 02:14:41 PM PST 23
Finished Nov 22 02:29:40 PM PST 23
Peak memory 378780 kb
Host smart-fa18f88e-6f00-4787-8272-8e9eebca6747
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30663530816260711234860790461112851246668083223002720215699564777756787117923
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during_key_req.306635308162607112348607904611128512466
68083223002720215699564777756787117923
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.109112963080123280944291559790648167104430610632301215069223180750063281205477
Short name T22
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:14:50 PM PST 23
Finished Nov 22 02:14:52 PM PST 23
Peak memory 202516 kb
Host smart-cc2effe8-3b38-4206-b1d3-73b4322fa526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109112963080123280944291559790648167104430610632301215069223180750
063281205477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.10911296308012328094429155979064816710443061063230121
5069223180750063281205477
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.1398360790013502445662206392112566367488386020396673913168382833010400308538
Short name T395
Test name
Test status
Simulation time 295482808505 ps
CPU time 2773.22 seconds
Started Nov 22 02:14:14 PM PST 23
Finished Nov 22 03:00:29 PM PST 23
Peak memory 202840 kb
Host smart-32294fd9-b2e9-48b5-b89b-f7f49da20870
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398360790013502445662206392112566367488386020396673913168382833010400308538 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.1398360790013502445662206392112566367488386020396673913168382833010400308538
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.115436456683706574833132744691855544120718543891166852030870524170244286322669
Short name T351
Test name
Test status
Simulation time 31712811539 ps
CPU time 903.98 seconds
Started Nov 22 02:14:36 PM PST 23
Finished Nov 22 02:29:41 PM PST 23
Peak memory 368060 kb
Host smart-5514de9f-9b21-46de-8f3d-9c9646e9c6a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115436456683706574833132744691855544120718543891166852030870524170244286322669 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.115436456683706574833132744691855544120718543891166852030870524170244286322669
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.28484581239370797324375690251957330449168672778999545682949627047408333501558
Short name T723
Test name
Test status
Simulation time 19084394710 ps
CPU time 102.92 seconds
Started Nov 22 02:14:40 PM PST 23
Finished Nov 22 02:16:23 PM PST 23
Peak memory 211088 kb
Host smart-a526974e-6e89-4792-a626-4e07952604aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28484581239370797324375690251957330449168672778999545682949627047408333501558 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.28484581239370797324375690251957330449168672778999545682949627047408333501558
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.95077339745519363042735836995226232741678684188974952554686985688323573843629
Short name T803
Test name
Test status
Simulation time 1342947357 ps
CPU time 118.68 seconds
Started Nov 22 02:14:41 PM PST 23
Finished Nov 22 02:16:41 PM PST 23
Peak memory 351176 kb
Host smart-2640f166-e000-4528-a99e-1f42549e55c2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9507733974551936304273583699522623274167868418897495255
4686985688323573843629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_max_throughput.95077339745519363042735836995226232
741678684188974952554686985688323573843629
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.62967935467795987627563882198739943309563920612721214100067941087531163592301
Short name T921
Test name
Test status
Simulation time 4750777237 ps
CPU time 80.65 seconds
Started Nov 22 02:14:30 PM PST 23
Finished Nov 22 02:15:52 PM PST 23
Peak memory 212304 kb
Host smart-ab907aad-9f8e-4c7e-b3d4-39d2910eaaf3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62967935467795987627563882198739943309563920612721214100067941087531
163592301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.629679354677959876275638821987399433095639206127
21214100067941087531163592301
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.58604607531008610537466429324248617520169881739274279867621925861423333934188
Short name T856
Test name
Test status
Simulation time 18445453393 ps
CPU time 159.32 seconds
Started Nov 22 02:14:26 PM PST 23
Finished Nov 22 02:17:06 PM PST 23
Peak memory 202772 kb
Host smart-a02d2885-5ed7-4e7d-8b03-76a3a81db466
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58604607531008610537466429324248617520169881739274279867621925861423333934188
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.58604607531008610537466429324248617520169881739274279867621925861423333934188
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.2342544793525473240990331617739839227778934531659200880022252094697387980274
Short name T513
Test name
Test status
Simulation time 28731174678 ps
CPU time 832.61 seconds
Started Nov 22 02:14:35 PM PST 23
Finished Nov 22 02:28:28 PM PST 23
Peak memory 378680 kb
Host smart-1884c193-7a58-43c6-aa22-390a63c888a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342544793525473240990331617739839227778934531659200880022252094697387980274 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.2342544793525473240990331617739839227778934531659200880022252094697387980274
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.69693962084969749972568058539812502999145100469585158180218044708133708948858
Short name T246
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.61 seconds
Started Nov 22 02:14:34 PM PST 23
Finished Nov 22 02:14:52 PM PST 23
Peak memory 245612 kb
Host smart-74eb4edd-9dbf-4caf-96aa-9e615ed332ac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696939620849697499725680585398125029991451004695851581802180447081337
08948858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.696939620849697499725680585398125029991451004695851581
80218044708133708948858
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.15402216294457349776817097149524923460137619741348558020340018306127216994562
Short name T496
Test name
Test status
Simulation time 45083829570 ps
CPU time 570.47 seconds
Started Nov 22 02:14:51 PM PST 23
Finished Nov 22 02:24:23 PM PST 23
Peak memory 202832 kb
Host smart-f82c0715-e3c0-4f3f-9151-51f000c87f43
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154022162944573497768170971495249234601376197413485580203400183061272
16994562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access_b2b.1540221629445734977681709714952492346013
7619741348558020340018306127216994562
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.11296484102765231048813376447482452514425092096527598924723746033742671747210
Short name T775
Test name
Test status
Simulation time 607542526 ps
CPU time 6.18 seconds
Started Nov 22 02:14:35 PM PST 23
Finished Nov 22 02:14:42 PM PST 23
Peak memory 203096 kb
Host smart-39c63e05-03ac-4405-8b39-439964be7476
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11296484102765231048813376447482452514425092096527598924723746033742671747210 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.11296484102765231048813376447482452514425092096527598924723746033742671747210
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.103848063293595661815152408095072264703918241081152731495406737000412585420369
Short name T983
Test name
Test status
Simulation time 19913691647 ps
CPU time 468.7 seconds
Started Nov 22 02:14:35 PM PST 23
Finished Nov 22 02:22:24 PM PST 23
Peak memory 372504 kb
Host smart-abfa469d-825a-4702-8f3d-d45e120ace23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103848063293595661815152408095072264703918241081152731495406737000412585420369 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.103848063293595661815152408095072264703918241081152731495406737000412585420369
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.38135125610840429612384831353003471029110882434624191835151514180673908228874
Short name T248
Test name
Test status
Simulation time 988289480 ps
CPU time 17.08 seconds
Started Nov 22 02:14:14 PM PST 23
Finished Nov 22 02:14:32 PM PST 23
Peak memory 245660 kb
Host smart-90126029-39a5-421b-9fcf-1f90d094c75b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38135125610840429612384831353003471029110882434624191835151514180673908228874 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.38135125610840429612384831353003471029110882434624191835151514180673908228874
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.9275550850712727527756341910759490770196977533299614592448012321193314728839
Short name T381
Test name
Test status
Simulation time 624328106 ps
CPU time 2058.14 seconds
Started Nov 22 02:14:35 PM PST 23
Finished Nov 22 02:48:54 PM PST 23
Peak memory 498240 kb
Host smart-d1cdaa8c-f59a-4161-b744-967d258b9bb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=9275550850712727527756341910759490770196977533299614592448012321193314728839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sra
m_ctrl_stress_all_with_rand_reset.9275550850712727527756341910759490770196977533299614592448012321193314728839
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.39653159488151772003749718619305623209835897695865663040838541810176327023330
Short name T663
Test name
Test status
Simulation time 9325508496 ps
CPU time 429.95 seconds
Started Nov 22 02:14:41 PM PST 23
Finished Nov 22 02:21:51 PM PST 23
Peak memory 202892 kb
Host smart-ef82b2f1-ba19-4b30-9b9a-eed3c3b6c8f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39653159488151772003749718619305623209835897695865663040838541810176327023330
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.396531594881517720037497186193056232098358976958656
63040838541810176327023330
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.17982143772372522531366313357905710595984910717468664544798084772172851328638
Short name T893
Test name
Test status
Simulation time 1371125703 ps
CPU time 105.23 seconds
Started Nov 22 02:14:25 PM PST 23
Finished Nov 22 02:16:11 PM PST 23
Peak memory 351212 kb
Host smart-f7364d05-1165-45dd-aa09-3ac2c318581a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179821437723725225313663133579057105959849107174686645
44798084772172851328638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1798214377237252253136
6313357905710595984910717468664544798084772172851328638
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.32214027692825344062780486159594544483279899960056117107994468499431194138472
Short name T292
Test name
Test status
Simulation time 13467153934 ps
CPU time 1082.42 seconds
Started Nov 22 02:07:18 PM PST 23
Finished Nov 22 02:25:22 PM PST 23
Peak memory 378780 kb
Host smart-f8e9ec39-b114-4d01-abeb-c7b5d26632fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32214027692825344062780486159594544483279899960056117107994468499431194138472
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_key_req.3221402769282534406278048615959454448327
9899960056117107994468499431194138472
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.73477378402306336466987833033244630051700527794113511260666068466194689288228
Short name T910
Test name
Test status
Simulation time 16600825 ps
CPU time 0.63 seconds
Started Nov 22 02:07:22 PM PST 23
Finished Nov 22 02:07:23 PM PST 23
Peak memory 202592 kb
Host smart-b06f7b10-f4cd-446e-8492-a9fc036bc042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734773784023063364669878330332446300517005277941135112606660684661
94689288228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.7347737840230633646698783303324463005170052779411351126
0666068466194689288228
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.98712045378617750676628268743574731251461721786196001417806087432204105089889
Short name T251
Test name
Test status
Simulation time 295482808505 ps
CPU time 2752.8 seconds
Started Nov 22 02:07:04 PM PST 23
Finished Nov 22 02:52:59 PM PST 23
Peak memory 202768 kb
Host smart-1ed3f29f-8560-4a16-8666-58c8961c2db3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98712045378617750676628268743574731251461721786196001417806087432204105089889 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.98712045378617750676628268743574731251461721786196001417806087432204105089889
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.70373955163153609951554746866942802028140229150027259656050380304140275761115
Short name T220
Test name
Test status
Simulation time 31712811539 ps
CPU time 959.32 seconds
Started Nov 22 02:07:09 PM PST 23
Finished Nov 22 02:23:12 PM PST 23
Peak memory 368024 kb
Host smart-748c5674-e19b-4e86-920c-b6b2a96c50a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70373955163153609951554746866942802028140229150027259656050380304140275761115 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.70373955163153609951554746866942802028140229150027259656050380304140275761115
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.84705427247150356951693946712708923458174703980861080479312063795493704146451
Short name T716
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.36 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:09:06 PM PST 23
Peak memory 211064 kb
Host smart-be4bdd96-e91a-41d6-8d54-b75733af99d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84705427247150356951693946712708923458174703980861080479312063795493704146451 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.84705427247150356951693946712708923458174703980861080479312063795493704146451
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.58960635882585830013513944938818915805206768296930814233539528890551880208926
Short name T334
Test name
Test status
Simulation time 1342947357 ps
CPU time 124.97 seconds
Started Nov 22 02:07:25 PM PST 23
Finished Nov 22 02:09:31 PM PST 23
Peak memory 351196 kb
Host smart-97a0b3b6-5e94-479d-a4e3-4366f8187945
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5896063588258583001351394493881891580520676829693081423
3539528890551880208926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max_throughput.589606358825858300135139449388189158
05206768296930814233539528890551880208926
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.105025907989423617573331296326744652475459722092215863184617168360131346464653
Short name T392
Test name
Test status
Simulation time 4750777237 ps
CPU time 80.32 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:08:43 PM PST 23
Peak memory 212340 kb
Host smart-f78ca6e9-e763-4931-a894-edfe48c3a39b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502590798942361757333129632674465247545972209221586318461716836013
1346464653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.105025907989423617573331296326744652475459722092
215863184617168360131346464653
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.40698455516425713392716288399395747894667195212657273010290880413125004291911
Short name T518
Test name
Test status
Simulation time 18445453393 ps
CPU time 162.76 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:10:04 PM PST 23
Peak memory 202800 kb
Host smart-59b9a3e9-6563-4e7a-8dbc-46418a157dc4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40698455516425713392716288399395747894667195212657273010290880413125004291911
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.40698455516425713392716288399395747894667195212657273010290880413125004291911
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.99669523554986995117448522075482120764967762871405571944774127915081926985734
Short name T795
Test name
Test status
Simulation time 28731174678 ps
CPU time 862.75 seconds
Started Nov 22 02:07:06 PM PST 23
Finished Nov 22 02:21:35 PM PST 23
Peak memory 378596 kb
Host smart-f7ab8d56-1521-4441-b459-8ca6772bee4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99669523554986995117448522075482120764967762871405571944774127915081926985734 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.99669523554986995117448522075482120764967762871405571944774127915081926985734
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.73950529998517768387635231923234677268642221123251778388257488913101573684742
Short name T107
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.63 seconds
Started Nov 22 02:07:05 PM PST 23
Finished Nov 22 02:07:25 PM PST 23
Peak memory 245692 kb
Host smart-4503e11d-13cb-486c-a78e-e3de7cf599f5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739505299985177683876352319232346772686422211232517783882574889131015
73684742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.7395052999851776838763523192323467726864222112325177838
8257488913101573684742
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.89363462085898431090316707198898096284788245456751924818407620466430588107865
Short name T94
Test name
Test status
Simulation time 45083829570 ps
CPU time 588.45 seconds
Started Nov 22 02:07:23 PM PST 23
Finished Nov 22 02:17:12 PM PST 23
Peak memory 202912 kb
Host smart-9120054b-4a78-4358-ab30-081442e0e051
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893634620858984310903167071988980962847882454567519248184076204664305
88107865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access_b2b.89363462085898431090316707198898096284788
245456751924818407620466430588107865
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.86511347897409308009243449063779776809633524957804356592158579577285252144064
Short name T283
Test name
Test status
Simulation time 607542526 ps
CPU time 6.02 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:07:28 PM PST 23
Peak memory 203124 kb
Host smart-b054806d-4c05-4620-ad5e-72a1b3320203
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86511347897409308009243449063779776809633524957804356592158579577285252144064 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.86511347897409308009243449063779776809633524957804356592158579577285252144064
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.83352148008405772788647614666266808105000387953342324801092549584318765469181
Short name T577
Test name
Test status
Simulation time 19913691647 ps
CPU time 512.3 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:15:52 PM PST 23
Peak memory 372372 kb
Host smart-b092ff66-82f6-4344-bdbc-fed4ff233c47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83352148008405772788647614666266808105000387953342324801092549584318765469181 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.83352148008405772788647614666266808105000387953342324801092549584318765469181
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.11649788384939314101327735162523106162731914603074395343856964757601650411147
Short name T37
Test name
Test status
Simulation time 216402798 ps
CPU time 2.04 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:07:24 PM PST 23
Peak memory 221184 kb
Host smart-4feeecd3-dc53-4997-808d-61ad384b9a13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164978838493931410132773516252310616273191460307439534385696475760
1650411147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.116497883849393141013277351625231061627319146030743953438569
64757601650411147
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.114674890991487967912451468788510589419951411567045988502046987372033308184523
Short name T871
Test name
Test status
Simulation time 988289480 ps
CPU time 16.47 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:07:37 PM PST 23
Peak memory 245664 kb
Host smart-438e73e8-55af-4d78-b463-5da0f79b67f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114674890991487967912451468788510589419951411567045988502046987372033308184523 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.114674890991487967912451468788510589419951411567045988502046987372033308184523
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.59418765429074480685876878977182214398724874284757977447566215218609687959448
Short name T452
Test name
Test status
Simulation time 624328106 ps
CPU time 1939.71 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:39:42 PM PST 23
Peak memory 498188 kb
Host smart-34e230c5-0a4e-446a-8adf-58fae4eb00ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=59418765429074480685876878977182214398724874284757977447566215218609687959448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sra
m_ctrl_stress_all_with_rand_reset.59418765429074480685876878977182214398724874284757977447566215218609687959448
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.91707247974699571964625933480647548979616666667276740832927176817569732120854
Short name T694
Test name
Test status
Simulation time 9325508496 ps
CPU time 428.19 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:14:29 PM PST 23
Peak memory 202868 kb
Host smart-d01badde-73ef-49b7-a3dc-7604394c1e9b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91707247974699571964625933480647548979616666667276740832927176817569732120854
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.9170724797469957196462593348064754897961666666727674
0832927176817569732120854
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.13872810442066626594212591781701397331070361701468308617688617259816032208364
Short name T864
Test name
Test status
Simulation time 1371125703 ps
CPU time 114.61 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:09:17 PM PST 23
Peak memory 351248 kb
Host smart-689cce3d-c466-4aa9-aa50-f4c6d00fd731
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138728104420666265942125917817013973310703617014683086
17688617259816032208364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.13872810442066626594212
591781701397331070361701468308617688617259816032208364
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.17588889393210929877699582787642651193187453482711209697365279856079983294462
Short name T400
Test name
Test status
Simulation time 13467153934 ps
CPU time 980.81 seconds
Started Nov 22 02:14:52 PM PST 23
Finished Nov 22 02:31:18 PM PST 23
Peak memory 378740 kb
Host smart-582fa297-e515-47f1-a0e0-a9611b08b98d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17588889393210929877699582787642651193187453482711209697365279856079983294462
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during_key_req.175888893932109298776995827876426511931
87453482711209697365279856079983294462
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.73594625043195208420977379577087241472491171879037176023731966388954645024023
Short name T412
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:14:54 PM PST 23
Finished Nov 22 02:14:59 PM PST 23
Peak memory 202580 kb
Host smart-206b2d78-c705-4d96-874b-24eb906728ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735946250431952084209773795770872414724911718790371760237319663889
54645024023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.735946250431952084209773795770872414724911718790371760
23731966388954645024023
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.38714949493521046113827897193556493062679604343661264945776478960888512695442
Short name T275
Test name
Test status
Simulation time 295482808505 ps
CPU time 2744.35 seconds
Started Nov 22 02:14:52 PM PST 23
Finished Nov 22 03:00:42 PM PST 23
Peak memory 202784 kb
Host smart-1df9f4e4-6611-4b68-a2cf-0d607e7608ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38714949493521046113827897193556493062679604343661264945776478960888512695442 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.38714949493521046113827897193556493062679604343661264945776478960888512695442
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.21530775677461038870514654964625250795536244932335746653829680982562712321568
Short name T467
Test name
Test status
Simulation time 31712811539 ps
CPU time 756.88 seconds
Started Nov 22 02:14:41 PM PST 23
Finished Nov 22 02:27:18 PM PST 23
Peak memory 367996 kb
Host smart-f3e7874f-fa34-46ff-acc6-889637e6b525
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21530775677461038870514654964625250795536244932335746653829680982562712321568 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.21530775677461038870514654964625250795536244932335746653829680982562712321568
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.23900762091601072627094313169769567068177579881404002573822431497939340006611
Short name T515
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.5 seconds
Started Nov 22 02:14:35 PM PST 23
Finished Nov 22 02:16:21 PM PST 23
Peak memory 211092 kb
Host smart-1e5cd83a-252d-46e5-aa5a-87a41da978f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23900762091601072627094313169769567068177579881404002573822431497939340006611 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.23900762091601072627094313169769567068177579881404002573822431497939340006611
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.7818571356374555986703376786362293905823911022163094566460336339287246132801
Short name T45
Test name
Test status
Simulation time 1342947357 ps
CPU time 124.93 seconds
Started Nov 22 02:14:43 PM PST 23
Finished Nov 22 02:16:49 PM PST 23
Peak memory 351188 kb
Host smart-a1625e13-2879-41b5-94be-860766e7a45b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7818571356374555986703376786362293905823911022163094566
460336339287246132801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_max_throughput.781857135637455598670337678636229390
5823911022163094566460336339287246132801
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.91873407580769837355221183028588564884574386161944765342110292689178822745214
Short name T682
Test name
Test status
Simulation time 4750777237 ps
CPU time 77.02 seconds
Started Nov 22 02:14:51 PM PST 23
Finished Nov 22 02:16:09 PM PST 23
Peak memory 212276 kb
Host smart-34929da2-428c-421c-95a9-a675fc158622
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91873407580769837355221183028588564884574386161944765342110292689178
822745214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.918734075807698373552211830285885648845743861619
44765342110292689178822745214
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.36360675248386450314163217619154966275625980660602274364181812928835135194183
Short name T848
Test name
Test status
Simulation time 18445453393 ps
CPU time 155.07 seconds
Started Nov 22 02:14:55 PM PST 23
Finished Nov 22 02:17:33 PM PST 23
Peak memory 202712 kb
Host smart-4c2d752d-6497-4672-94d6-a3a2a289021c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36360675248386450314163217619154966275625980660602274364181812928835135194183
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.36360675248386450314163217619154966275625980660602274364181812928835135194183
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.95830961083777633588520763343990317676757341197748257529835357487919787394459
Short name T559
Test name
Test status
Simulation time 28731174678 ps
CPU time 798.9 seconds
Started Nov 22 02:14:42 PM PST 23
Finished Nov 22 02:28:01 PM PST 23
Peak memory 378664 kb
Host smart-6940d48b-3435-44bb-b7ee-67ab0b407531
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95830961083777633588520763343990317676757341197748257529835357487919787394459 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.95830961083777633588520763343990317676757341197748257529835357487919787394459
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.72747090408770576403556619829429744086609726464372932489801420852096345188772
Short name T586
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.27 seconds
Started Nov 22 02:14:42 PM PST 23
Finished Nov 22 02:15:02 PM PST 23
Peak memory 245644 kb
Host smart-7aed3652-e49f-45e0-8a38-0bf5e1934bcc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727470904087705764035566198294297440866097264643729324898014208520963
45188772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.727470904087705764035566198294297440866097264643729324
89801420852096345188772
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.24785348461995533982232216723814428534869183869405182300200134469778579203735
Short name T916
Test name
Test status
Simulation time 45083829570 ps
CPU time 587.61 seconds
Started Nov 22 02:14:53 PM PST 23
Finished Nov 22 02:24:46 PM PST 23
Peak memory 202876 kb
Host smart-b6fbe303-4309-4d06-945c-fbc7a78c51f6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247853484619955339822322167238144285348691838694051823002001344697785
79203735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access_b2b.2478534846199553398223221672381442853486
9183869405182300200134469778579203735
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.115293677084918470913324104152563095341597221739206003266245099199641135595512
Short name T974
Test name
Test status
Simulation time 607542526 ps
CPU time 6.05 seconds
Started Nov 22 02:14:52 PM PST 23
Finished Nov 22 02:15:03 PM PST 23
Peak memory 203000 kb
Host smart-f3592a70-b5c4-441d-8066-b68bf5e3afbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115293677084918470913324104152563095341597221739206003266245099199641135595512 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.115293677084918470913324104152563095341597221739206003266245099199641135595512
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.11393104290923828500565518653076225524679638738105050520528101998018421481604
Short name T870
Test name
Test status
Simulation time 19913691647 ps
CPU time 591.95 seconds
Started Nov 22 02:14:42 PM PST 23
Finished Nov 22 02:24:34 PM PST 23
Peak memory 372576 kb
Host smart-5c2cf26b-c653-4009-b11c-5b3365c9a611
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11393104290923828500565518653076225524679638738105050520528101998018421481604 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.11393104290923828500565518653076225524679638738105050520528101998018421481604
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.24265793801018093744796673636541407989197492754895357752807698843943564263513
Short name T333
Test name
Test status
Simulation time 988289480 ps
CPU time 17.28 seconds
Started Nov 22 02:14:55 PM PST 23
Finished Nov 22 02:15:15 PM PST 23
Peak memory 245108 kb
Host smart-2de1f497-52d1-4be2-84ac-14f4da0b0886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24265793801018093744796673636541407989197492754895357752807698843943564263513 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.24265793801018093744796673636541407989197492754895357752807698843943564263513
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.20084946614398365236644662669625655420390325393454562351033970762117812588099
Short name T403
Test name
Test status
Simulation time 624328106 ps
CPU time 1707.63 seconds
Started Nov 22 02:14:54 PM PST 23
Finished Nov 22 02:43:26 PM PST 23
Peak memory 498192 kb
Host smart-de72eed5-2deb-4901-acae-0302a9b7e9bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=20084946614398365236644662669625655420390325393454562351033970762117812588099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sr
am_ctrl_stress_all_with_rand_reset.20084946614398365236644662669625655420390325393454562351033970762117812588099
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.53872919051169979555544128322588059914047669539856133800387765102889773219500
Short name T922
Test name
Test status
Simulation time 9325508496 ps
CPU time 427.82 seconds
Started Nov 22 02:15:27 PM PST 23
Finished Nov 22 02:22:36 PM PST 23
Peak memory 202868 kb
Host smart-d83f639a-2f0d-49ce-b233-ef72c8e543c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53872919051169979555544128322588059914047669539856133800387765102889773219500
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.538729190511699795555441283225880599140476695398561
33800387765102889773219500
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.105570111984086637843990773490401833360978445471503880093187382582627125622217
Short name T268
Test name
Test status
Simulation time 1371125703 ps
CPU time 127.33 seconds
Started Nov 22 02:15:28 PM PST 23
Finished Nov 22 02:17:36 PM PST 23
Peak memory 351260 kb
Host smart-fe4c8b55-7264-475a-8cb1-3634e3d2f2c5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105570111984086637843990773490401833360978445471503880
093187382582627125622217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.105570111984086637843
990773490401833360978445471503880093187382582627125622217
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.22794181751631717761436734434572184271773747005259774961947085411447826701401
Short name T343
Test name
Test status
Simulation time 13467153934 ps
CPU time 944.62 seconds
Started Nov 22 02:14:41 PM PST 23
Finished Nov 22 02:30:27 PM PST 23
Peak memory 378824 kb
Host smart-a9179340-28e9-4299-a21b-46b8b05e2964
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22794181751631717761436734434572184271773747005259774961947085411447826701401
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during_key_req.227941817516317177614367344345721842717
73747005259774961947085411447826701401
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.4308242794931653420655323061114387781305318544751227600785423317831583718176
Short name T447
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:14:56 PM PST 23
Finished Nov 22 02:14:59 PM PST 23
Peak memory 202584 kb
Host smart-689d0c31-55cb-4bb4-80ed-0f8ebbe36a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430824279493165342065532306111438778130531854475122760078542331783
1583718176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.4308242794931653420655323061114387781305318544751227600
785423317831583718176
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.103506454577100922044262633299046514714018634711262633636512367208224399957738
Short name T572
Test name
Test status
Simulation time 295482808505 ps
CPU time 2722.91 seconds
Started Nov 22 02:14:42 PM PST 23
Finished Nov 22 03:00:05 PM PST 23
Peak memory 202828 kb
Host smart-c61f7038-a78a-4ce3-ae10-ae36a91ccc31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103506454577100922044262633299046514714018634711262633636512367208224399957738 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.103506454577100922044262633299046514714018634711262633636512367208224399957738
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.1423801950687985736497072945637831573547945171288318670032767847165448160391
Short name T732
Test name
Test status
Simulation time 31712811539 ps
CPU time 781.03 seconds
Started Nov 22 02:14:55 PM PST 23
Finished Nov 22 02:27:59 PM PST 23
Peak memory 367548 kb
Host smart-82326ad2-9fcc-49c5-9d4a-198e92128315
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423801950687985736497072945637831573547945171288318670032767847165448160391 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.1423801950687985736497072945637831573547945171288318670032767847165448160391
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.106536107355116942162790551467456510328417225619052037218972300398383135953190
Short name T254
Test name
Test status
Simulation time 19084394710 ps
CPU time 108.16 seconds
Started Nov 22 02:14:59 PM PST 23
Finished Nov 22 02:16:49 PM PST 23
Peak memory 211044 kb
Host smart-18636907-f695-41dd-b061-0f090982fb79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106536107355116942162790551467456510328417225619052037218972300398383135953190 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.106536107355116942162790551467456510328417225619052037218972300398383135953190
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.54639721877920763931091341101987609299924503841113766544928541185093510457101
Short name T514
Test name
Test status
Simulation time 1342947357 ps
CPU time 117.91 seconds
Started Nov 22 02:14:42 PM PST 23
Finished Nov 22 02:16:41 PM PST 23
Peak memory 351196 kb
Host smart-42ac0f07-568b-4d48-82cb-f4f5efb09d0d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5463972187792076393109134110198760929992450384111376654
4928541185093510457101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_max_throughput.54639721877920763931091341101987609
299924503841113766544928541185093510457101
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.75805460121964158196241290419503369524304767214454416937247060821131746021177
Short name T717
Test name
Test status
Simulation time 4750777237 ps
CPU time 76.98 seconds
Started Nov 22 02:14:53 PM PST 23
Finished Nov 22 02:16:15 PM PST 23
Peak memory 212380 kb
Host smart-d283b8a4-9071-45bf-bf27-aa31de1cd54d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75805460121964158196241290419503369524304767214454416937247060821131
746021177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.758054601219641581962412904195033695243047672144
54416937247060821131746021177
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.93744793908871203507954898493978743258074630134493650105479826282293283388425
Short name T772
Test name
Test status
Simulation time 18445453393 ps
CPU time 160.56 seconds
Started Nov 22 02:14:52 PM PST 23
Finished Nov 22 02:17:36 PM PST 23
Peak memory 202784 kb
Host smart-de38a24d-a96a-4752-8736-c3b093304400
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93744793908871203507954898493978743258074630134493650105479826282293283388425
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.93744793908871203507954898493978743258074630134493650105479826282293283388425
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.27503611860069054293328027736221983896079219017867057479404630527983799225889
Short name T888
Test name
Test status
Simulation time 28731174678 ps
CPU time 874.88 seconds
Started Nov 22 02:14:42 PM PST 23
Finished Nov 22 02:29:17 PM PST 23
Peak memory 378592 kb
Host smart-19f8e779-3a0f-4fcb-a250-5ccd438ec34d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27503611860069054293328027736221983896079219017867057479404630527983799225889 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.27503611860069054293328027736221983896079219017867057479404630527983799225889
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.81289480902161927610039447347778641600756178511290723803638816377387305561678
Short name T828
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.5 seconds
Started Nov 22 02:14:52 PM PST 23
Finished Nov 22 02:15:14 PM PST 23
Peak memory 245664 kb
Host smart-85777876-29c6-4e46-9636-9b3556a9b9bf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812894809021619276100394473477786416007561785112907238036388163773873
05561678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.812894809021619276100394473477786416007561785112907238
03638816377387305561678
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.76064151858763415194269462099956007007217681226291767583508507880981933655198
Short name T924
Test name
Test status
Simulation time 45083829570 ps
CPU time 577.61 seconds
Started Nov 22 02:14:54 PM PST 23
Finished Nov 22 02:24:36 PM PST 23
Peak memory 202788 kb
Host smart-2c7dc843-871d-4880-bd90-7172bb0d5414
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760641518587634151942694620999560070072176812262917675835085078809819
33655198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access_b2b.7606415185876341519426946209995600700721
7681226291767583508507880981933655198
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.5132577693921704554858969659936640286172202273452657926601937897752281658070
Short name T543
Test name
Test status
Simulation time 607542526 ps
CPU time 6.06 seconds
Started Nov 22 02:14:53 PM PST 23
Finished Nov 22 02:15:04 PM PST 23
Peak memory 203160 kb
Host smart-0643491f-573b-4bbb-a6a0-b9d5fbd352a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5132577693921704554858969659936640286172202273452657926601937897752281658070 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.5132577693921704554858969659936640286172202273452657926601937897752281658070
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.27416228395012778529840119097603835198130931075398828093969139696117930139526
Short name T307
Test name
Test status
Simulation time 19913691647 ps
CPU time 524.6 seconds
Started Nov 22 02:14:55 PM PST 23
Finished Nov 22 02:23:43 PM PST 23
Peak memory 372464 kb
Host smart-abdf6de7-9752-4a7a-93aa-e80831101f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27416228395012778529840119097603835198130931075398828093969139696117930139526 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.27416228395012778529840119097603835198130931075398828093969139696117930139526
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.65577434491513818864292069161705200322458717695473585145056413597983597208849
Short name T244
Test name
Test status
Simulation time 988289480 ps
CPU time 18.17 seconds
Started Nov 22 02:14:56 PM PST 23
Finished Nov 22 02:15:17 PM PST 23
Peak memory 245656 kb
Host smart-cbe33de9-09da-4ed5-a90c-7483f2ec6c3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65577434491513818864292069161705200322458717695473585145056413597983597208849 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.65577434491513818864292069161705200322458717695473585145056413597983597208849
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.77784107997666428795848615936079279784413685456999301646550486950038483213968
Short name T756
Test name
Test status
Simulation time 624328106 ps
CPU time 1768.12 seconds
Started Nov 22 02:14:51 PM PST 23
Finished Nov 22 02:44:20 PM PST 23
Peak memory 498124 kb
Host smart-94c9bcee-189d-4232-8044-fbf340aa7591
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=77784107997666428795848615936079279784413685456999301646550486950038483213968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sr
am_ctrl_stress_all_with_rand_reset.77784107997666428795848615936079279784413685456999301646550486950038483213968
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.15449524847236373348770622966887365580495147619578440166418382002607175020716
Short name T18
Test name
Test status
Simulation time 9325508496 ps
CPU time 422.83 seconds
Started Nov 22 02:14:52 PM PST 23
Finished Nov 22 02:22:01 PM PST 23
Peak memory 202828 kb
Host smart-104cbf17-3a37-49e6-bad6-afc3bb72c313
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15449524847236373348770622966887365580495147619578440166418382002607175020716
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.154495248472363733487706229668873655804951476195784
40166418382002607175020716
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.43594091765730442106609531782725301297777014612431665819336152544024286154603
Short name T771
Test name
Test status
Simulation time 1371125703 ps
CPU time 107.21 seconds
Started Nov 22 02:14:53 PM PST 23
Finished Nov 22 02:16:45 PM PST 23
Peak memory 351228 kb
Host smart-e99e821d-26d3-448d-bfd7-9cd94a8eb6af
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435940917657304421066095317827253012977770146124316658
19336152544024286154603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.4359409176573044210660
9531782725301297777014612431665819336152544024286154603
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.15398330020297284846043576464081542185780409893847828598050766517973473311906
Short name T231
Test name
Test status
Simulation time 13467153934 ps
CPU time 861.7 seconds
Started Nov 22 02:14:52 PM PST 23
Finished Nov 22 02:29:19 PM PST 23
Peak memory 378788 kb
Host smart-ea0ae6e5-34b5-4f9d-89f1-4d7f14b8ef62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15398330020297284846043576464081542185780409893847828598050766517973473311906
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during_key_req.153983300202972848460435764640815421857
80409893847828598050766517973473311906
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.85898214444470970515811055853133366439158120897065140301883410261050163687708
Short name T498
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:15:31 PM PST 23
Finished Nov 22 02:15:32 PM PST 23
Peak memory 202568 kb
Host smart-56de57ab-f31b-4b1e-a92a-cbef3f1158c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858982144444709705158110558531333664391581208970651403018834102610
50163687708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.858982144444709705158110558531333664391581208970651403
01883410261050163687708
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.44134302814279234166247017610546299953564527264094679088336185547175794702009
Short name T883
Test name
Test status
Simulation time 295482808505 ps
CPU time 2761.51 seconds
Started Nov 22 02:14:55 PM PST 23
Finished Nov 22 03:01:00 PM PST 23
Peak memory 202820 kb
Host smart-286ba871-2a80-45b2-b039-ed4febbbf38a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44134302814279234166247017610546299953564527264094679088336185547175794702009 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.44134302814279234166247017610546299953564527264094679088336185547175794702009
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.7126114057613727236095418678439134044936444524005335209818999729228990124121
Short name T628
Test name
Test status
Simulation time 31712811539 ps
CPU time 862.8 seconds
Started Nov 22 02:14:54 PM PST 23
Finished Nov 22 02:29:21 PM PST 23
Peak memory 368040 kb
Host smart-b9849f78-dc4a-4698-a852-c96b6cce0762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7126114057613727236095418678439134044936444524005335209818999729228990124121 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.7126114057613727236095418678439134044936444524005335209818999729228990124121
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.93608229287002883160653796762218367396719347125459635292596903712907594856189
Short name T943
Test name
Test status
Simulation time 19084394710 ps
CPU time 103.52 seconds
Started Nov 22 02:15:12 PM PST 23
Finished Nov 22 02:16:56 PM PST 23
Peak memory 211032 kb
Host smart-91da2362-eade-462c-b0e7-a32095b26182
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93608229287002883160653796762218367396719347125459635292596903712907594856189 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.93608229287002883160653796762218367396719347125459635292596903712907594856189
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.107986098538850129210215130414889583541783908598984924564055420364166540153304
Short name T802
Test name
Test status
Simulation time 1342947357 ps
CPU time 119.55 seconds
Started Nov 22 02:15:28 PM PST 23
Finished Nov 22 02:17:28 PM PST 23
Peak memory 351032 kb
Host smart-9273ad36-c7f1-4bd2-a957-63b609adc2e9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079860985388501292102151304148895835417839085989849245
64055420364166540153304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_max_throughput.1079860985388501292102151304148895
83541783908598984924564055420364166540153304
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3000614722796924193446635959145080751015434392657237206061148384460777560886
Short name T886
Test name
Test status
Simulation time 4750777237 ps
CPU time 82.24 seconds
Started Nov 22 02:15:28 PM PST 23
Finished Nov 22 02:16:51 PM PST 23
Peak memory 212332 kb
Host smart-df532779-c0f5-4666-8e67-fac33ad4c45e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30006147227969241934466359591450807510154343926572372060611483844607
77560886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.3000614722796924193446635959145080751015434392657
237206061148384460777560886
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.22731662865262698177914549503461827896862718397123777972940562015032025278011
Short name T13
Test name
Test status
Simulation time 18445453393 ps
CPU time 148.48 seconds
Started Nov 22 02:15:27 PM PST 23
Finished Nov 22 02:17:57 PM PST 23
Peak memory 202700 kb
Host smart-f737c002-128b-4249-94ef-c0b9ba14ea72
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22731662865262698177914549503461827896862718397123777972940562015032025278011
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.22731662865262698177914549503461827896862718397123777972940562015032025278011
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.62037127939656897368483590963527459053822183206883319789448221820189553179654
Short name T596
Test name
Test status
Simulation time 28731174678 ps
CPU time 747.7 seconds
Started Nov 22 02:15:27 PM PST 23
Finished Nov 22 02:27:55 PM PST 23
Peak memory 378596 kb
Host smart-af1ea59b-3917-413f-840b-17bf2e9d3d27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62037127939656897368483590963527459053822183206883319789448221820189553179654 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.62037127939656897368483590963527459053822183206883319789448221820189553179654
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.60285546051398254619194266005402864635804291555595216735152543545564404598630
Short name T368
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.88 seconds
Started Nov 22 02:15:30 PM PST 23
Finished Nov 22 02:15:49 PM PST 23
Peak memory 245660 kb
Host smart-d3716ef3-1bb0-4256-a00a-fc65dca9400f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602855460513982546191942660054028646358042915555952167351525435455644
04598630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.602855460513982546191942660054028646358042915555952167
35152543545564404598630
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.67431320223298341844455542114738841637730732613408629402609729609139060651872
Short name T778
Test name
Test status
Simulation time 45083829570 ps
CPU time 567.64 seconds
Started Nov 22 02:14:51 PM PST 23
Finished Nov 22 02:24:20 PM PST 23
Peak memory 202872 kb
Host smart-eacf8b25-2b09-4cac-b832-35faa9274009
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674313202232983418444555421147388416377307326134086294026097296091390
60651872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access_b2b.6743132022329834184445554211473884163773
0732613408629402609729609139060651872
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.113012573273461409443896176246560653867384055926289424849046789529037227897399
Short name T369
Test name
Test status
Simulation time 607542526 ps
CPU time 6.29 seconds
Started Nov 22 02:14:55 PM PST 23
Finished Nov 22 02:15:04 PM PST 23
Peak memory 203128 kb
Host smart-600b0ce1-8c21-4f09-8c47-fad88223382d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113012573273461409443896176246560653867384055926289424849046789529037227897399 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.113012573273461409443896176246560653867384055926289424849046789529037227897399
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.63332981488535464755475405332662832742463545729576834721013374549532047177196
Short name T548
Test name
Test status
Simulation time 19913691647 ps
CPU time 578.56 seconds
Started Nov 22 02:14:55 PM PST 23
Finished Nov 22 02:24:37 PM PST 23
Peak memory 372436 kb
Host smart-b133b84f-cb32-4fc7-95e3-e21e4baaec71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63332981488535464755475405332662832742463545729576834721013374549532047177196 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.63332981488535464755475405332662832742463545729576834721013374549532047177196
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.3578768317674469288403406451171549708094897884175535383083414141035667352660
Short name T14
Test name
Test status
Simulation time 988289480 ps
CPU time 19.39 seconds
Started Nov 22 02:14:53 PM PST 23
Finished Nov 22 02:15:17 PM PST 23
Peak memory 245628 kb
Host smart-04fadbb4-f16c-4f33-a6fa-454935dcda9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578768317674469288403406451171549708094897884175535383083414141035667352660 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3578768317674469288403406451171549708094897884175535383083414141035667352660
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.78722191229875160389667114212923345369392557976448968842026365822040484678724
Short name T918
Test name
Test status
Simulation time 624328106 ps
CPU time 1703.3 seconds
Started Nov 22 02:14:52 PM PST 23
Finished Nov 22 02:43:21 PM PST 23
Peak memory 498100 kb
Host smart-40193791-8e5b-40e3-9c9a-075c400265fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=78722191229875160389667114212923345369392557976448968842026365822040484678724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sr
am_ctrl_stress_all_with_rand_reset.78722191229875160389667114212923345369392557976448968842026365822040484678724
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.40830703600054094219408329203665638302601342865174264531737469682359788575008
Short name T840
Test name
Test status
Simulation time 9325508496 ps
CPU time 430.98 seconds
Started Nov 22 02:14:53 PM PST 23
Finished Nov 22 02:22:09 PM PST 23
Peak memory 202964 kb
Host smart-1dbc21d1-0934-4f06-9a54-4a569c02aa07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40830703600054094219408329203665638302601342865174264531737469682359788575008
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.408307036000540942194083292036656383026013428651742
64531737469682359788575008
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.81150740998011153623897760732886764706888931605480030406853587644597828199682
Short name T976
Test name
Test status
Simulation time 1371125703 ps
CPU time 135.04 seconds
Started Nov 22 02:15:29 PM PST 23
Finished Nov 22 02:17:44 PM PST 23
Peak memory 351196 kb
Host smart-9c088149-a3c1-487f-86a8-c65b902ee808
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811507409980111536238977607328867647068889316054800304
06853587644597828199682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.8115074099801115362389
7760732886764706888931605480030406853587644597828199682
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.29899142655805441115723941305157648765651969104306251235976296700527794757831
Short name T613
Test name
Test status
Simulation time 13467153934 ps
CPU time 994.32 seconds
Started Nov 22 02:14:59 PM PST 23
Finished Nov 22 02:31:36 PM PST 23
Peak memory 378792 kb
Host smart-80982169-f858-4b53-a40a-e9179898aacd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29899142655805441115723941305157648765651969104306251235976296700527794757831
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during_key_req.298991426558054411157239413051576487656
51969104306251235976296700527794757831
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.77002416641414423003952225845068557470793380546622735897998674035769469158537
Short name T699
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:15:32 PM PST 23
Finished Nov 22 02:15:33 PM PST 23
Peak memory 202576 kb
Host smart-156f3cab-80be-4b1c-86ec-40f975db0112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770024166414144230039522258450685574707933805466227358979986740357
69469158537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.770024166414144230039522258450685574707933805466227358
97998674035769469158537
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.61592764640079468339838025915002426246511827206570247204701561365830840806082
Short name T324
Test name
Test status
Simulation time 295482808505 ps
CPU time 2649.62 seconds
Started Nov 22 02:15:35 PM PST 23
Finished Nov 22 02:59:45 PM PST 23
Peak memory 202848 kb
Host smart-8a52fe3d-d686-485c-af0e-7f16f2b32d54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61592764640079468339838025915002426246511827206570247204701561365830840806082 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.61592764640079468339838025915002426246511827206570247204701561365830840806082
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.72399948868073070571392281425960498559490103984047570242469233691345140907695
Short name T598
Test name
Test status
Simulation time 31712811539 ps
CPU time 876.93 seconds
Started Nov 22 02:15:30 PM PST 23
Finished Nov 22 02:30:08 PM PST 23
Peak memory 368016 kb
Host smart-b678641e-5de0-4779-97c8-ec8d5ea5e63b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72399948868073070571392281425960498559490103984047570242469233691345140907695 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.72399948868073070571392281425960498559490103984047570242469233691345140907695
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.23739879044926001430174205600269163319013271083128539708440605175448253290194
Short name T4
Test name
Test status
Simulation time 19084394710 ps
CPU time 103.96 seconds
Started Nov 22 02:15:54 PM PST 23
Finished Nov 22 02:17:39 PM PST 23
Peak memory 211044 kb
Host smart-8868b802-5d50-4960-930c-6a7044bc9117
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23739879044926001430174205600269163319013271083128539708440605175448253290194 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.23739879044926001430174205600269163319013271083128539708440605175448253290194
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.51662373707233623303289145674123344167474375507606678709771123168836075396896
Short name T787
Test name
Test status
Simulation time 1342947357 ps
CPU time 123.22 seconds
Started Nov 22 02:15:39 PM PST 23
Finished Nov 22 02:17:43 PM PST 23
Peak memory 351092 kb
Host smart-298c247d-ce7e-44b0-835a-276d105de043
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5166237370723362330328914567412334416747437550760667870
9771123168836075396896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_max_throughput.51662373707233623303289145674123344
167474375507606678709771123168836075396896
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.208257571154743917110747055135652531899129976197213189126403169656009712425
Short name T529
Test name
Test status
Simulation time 4750777237 ps
CPU time 79.43 seconds
Started Nov 22 02:14:59 PM PST 23
Finished Nov 22 02:16:21 PM PST 23
Peak memory 212360 kb
Host smart-8e6ea33e-9f56-4bb7-98a0-4499d648bca7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20825757115474391711074705513565253189912997619721318912640316965600
9712425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.20825757115474391711074705513565253189912997619721
3189126403169656009712425
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.74295683145947341579383154037047914497316095850687096029797242674879222521096
Short name T631
Test name
Test status
Simulation time 18445453393 ps
CPU time 163.3 seconds
Started Nov 22 02:14:58 PM PST 23
Finished Nov 22 02:17:44 PM PST 23
Peak memory 202808 kb
Host smart-e3cf7a9c-397b-41e2-9bdd-f98bfaa44421
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74295683145947341579383154037047914497316095850687096029797242674879222521096
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.74295683145947341579383154037047914497316095850687096029797242674879222521096
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.41335447567461592146112702211846556313294951385470112374700508181886292431124
Short name T282
Test name
Test status
Simulation time 28731174678 ps
CPU time 928.38 seconds
Started Nov 22 02:15:29 PM PST 23
Finished Nov 22 02:30:58 PM PST 23
Peak memory 378640 kb
Host smart-f3bbbbd6-a2b8-40f2-a90d-ee7de9ae23df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41335447567461592146112702211846556313294951385470112374700508181886292431124 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.41335447567461592146112702211846556313294951385470112374700508181886292431124
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.103593411459995085873075130715414254372656234698681892386816909506372437598109
Short name T894
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.63 seconds
Started Nov 22 02:15:30 PM PST 23
Finished Nov 22 02:15:48 PM PST 23
Peak memory 245700 kb
Host smart-d968560d-bda5-4150-a596-2e744d38fd38
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103593411459995085873075130715414254372656234698681892386816909506372
437598109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.10359341145999508587307513071541425437265623469868189
2386816909506372437598109
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.90229773131214919519151734546960748577914425113672080577070120142450876624513
Short name T887
Test name
Test status
Simulation time 45083829570 ps
CPU time 573.24 seconds
Started Nov 22 02:15:41 PM PST 23
Finished Nov 22 02:25:15 PM PST 23
Peak memory 202856 kb
Host smart-135738ec-7e9f-40d4-b782-ef7392c8d1dd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902297731312149195191517345469607485779144251136720805770701201424508
76624513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access_b2b.9022977313121491951915173454696074857791
4425113672080577070120142450876624513
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.106995347456735828003561835885403435556821774837025670550563926985077360031980
Short name T223
Test name
Test status
Simulation time 607542526 ps
CPU time 6.19 seconds
Started Nov 22 02:15:54 PM PST 23
Finished Nov 22 02:16:01 PM PST 23
Peak memory 203104 kb
Host smart-648bceee-4d18-4ed9-a74e-5648beb0bbb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106995347456735828003561835885403435556821774837025670550563926985077360031980 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.106995347456735828003561835885403435556821774837025670550563926985077360031980
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.73651424523608268968747639348874304942392827565087392444708287660349718909096
Short name T459
Test name
Test status
Simulation time 19913691647 ps
CPU time 555.88 seconds
Started Nov 22 02:14:58 PM PST 23
Finished Nov 22 02:24:16 PM PST 23
Peak memory 372508 kb
Host smart-8dc82d53-5df9-4b1a-a180-166aef9d1105
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73651424523608268968747639348874304942392827565087392444708287660349718909096 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.73651424523608268968747639348874304942392827565087392444708287660349718909096
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.109536957068181689899183144703601237937000662077835817219962497591982738574229
Short name T267
Test name
Test status
Simulation time 988289480 ps
CPU time 17.91 seconds
Started Nov 22 02:15:31 PM PST 23
Finished Nov 22 02:15:50 PM PST 23
Peak memory 245660 kb
Host smart-d46a3e72-e11d-44ad-b763-7eca312ac466
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109536957068181689899183144703601237937000662077835817219962497591982738574229 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.109536957068181689899183144703601237937000662077835817219962497591982738574229
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.7286873354261973957700977128628170788988790113325547176992209083850305566571
Short name T946
Test name
Test status
Simulation time 624328106 ps
CPU time 2127.55 seconds
Started Nov 22 02:14:59 PM PST 23
Finished Nov 22 02:50:29 PM PST 23
Peak memory 498160 kb
Host smart-08a641c0-477e-45cf-b0bb-344c98e8a9bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=7286873354261973957700977128628170788988790113325547176992209083850305566571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sra
m_ctrl_stress_all_with_rand_reset.7286873354261973957700977128628170788988790113325547176992209083850305566571
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.54373157071095779754698978417369768721731336134407037661300806494351865752523
Short name T322
Test name
Test status
Simulation time 9325508496 ps
CPU time 439.55 seconds
Started Nov 22 02:15:47 PM PST 23
Finished Nov 22 02:23:07 PM PST 23
Peak memory 202800 kb
Host smart-dba96973-33dc-404b-bacd-9edcbdc7eddd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54373157071095779754698978417369768721731336134407037661300806494351865752523
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.543731570710957797546989784173697687217313361344070
37661300806494351865752523
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.44506422316821263836915088221686559677792474173270636767155308586198527632067
Short name T826
Test name
Test status
Simulation time 1371125703 ps
CPU time 126.28 seconds
Started Nov 22 02:14:57 PM PST 23
Finished Nov 22 02:17:05 PM PST 23
Peak memory 351200 kb
Host smart-907d27f3-6bc4-42e6-b45b-f61ab047e4e4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445064223168212638369150882216865596777924741732706367
67155308586198527632067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.4450642231682126383691
5088221686559677792474173270636767155308586198527632067
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.82190037803333032058365642676694403992969374988455437264198371864495878635289
Short name T9
Test name
Test status
Simulation time 13467153934 ps
CPU time 969.09 seconds
Started Nov 22 02:15:26 PM PST 23
Finished Nov 22 02:31:36 PM PST 23
Peak memory 378776 kb
Host smart-b4f581de-fdd5-471b-816c-dcb75883082b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82190037803333032058365642676694403992969374988455437264198371864495878635289
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during_key_req.821900378033330320583656426766944039929
69374988455437264198371864495878635289
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.52201084803120919030452148415274154848040250622734140865097414797572686676889
Short name T939
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 02:15:30 PM PST 23
Finished Nov 22 02:15:31 PM PST 23
Peak memory 202568 kb
Host smart-9d2d3986-8a55-4b75-9d66-538b79665e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522010848031209190304521484152741548480402506227341408650974147975
72686676889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.522010848031209190304521484152741548480402506227341408
65097414797572686676889
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.87977463917745921286522224736599027829174074932587616683624775391597904593838
Short name T632
Test name
Test status
Simulation time 295482808505 ps
CPU time 2797.02 seconds
Started Nov 22 02:15:31 PM PST 23
Finished Nov 22 03:02:09 PM PST 23
Peak memory 202852 kb
Host smart-9aaf9b4d-7066-490f-889e-6980825e11d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87977463917745921286522224736599027829174074932587616683624775391597904593838 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.87977463917745921286522224736599027829174074932587616683624775391597904593838
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.9498873710822285234970570937535496705038631272043449628796574898660542182948
Short name T242
Test name
Test status
Simulation time 31712811539 ps
CPU time 829.15 seconds
Started Nov 22 02:15:30 PM PST 23
Finished Nov 22 02:29:20 PM PST 23
Peak memory 368072 kb
Host smart-4a6e118e-3c1a-413d-8a49-7c84c5e8b721
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9498873710822285234970570937535496705038631272043449628796574898660542182948 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.9498873710822285234970570937535496705038631272043449628796574898660542182948
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.68578686470665214061876408546985708922726249661382868539244925849345640071059
Short name T5
Test name
Test status
Simulation time 19084394710 ps
CPU time 103.12 seconds
Started Nov 22 02:15:34 PM PST 23
Finished Nov 22 02:17:18 PM PST 23
Peak memory 211048 kb
Host smart-2160429f-3ebf-4afb-9ec8-7fc7fb634b73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68578686470665214061876408546985708922726249661382868539244925849345640071059 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.68578686470665214061876408546985708922726249661382868539244925849345640071059
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.28667884218492239507468629321095040122907566491715398987271174911285430056135
Short name T111
Test name
Test status
Simulation time 1342947357 ps
CPU time 129.66 seconds
Started Nov 22 02:15:39 PM PST 23
Finished Nov 22 02:17:50 PM PST 23
Peak memory 351072 kb
Host smart-6728368a-80c2-40e9-b36c-01a4092add3d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866788421849223950746862932109504012290756649171539898
7271174911285430056135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_max_throughput.28667884218492239507468629321095040
122907566491715398987271174911285430056135
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.52201174756099600630854594348662727755022995266869341676969500946576714770057
Short name T257
Test name
Test status
Simulation time 4750777237 ps
CPU time 77.59 seconds
Started Nov 22 02:15:34 PM PST 23
Finished Nov 22 02:16:53 PM PST 23
Peak memory 212348 kb
Host smart-433c5e0d-b45f-4f8d-aafd-d8dc8823afe9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52201174756099600630854594348662727755022995266869341676969500946576
714770057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.522011747560996006308545943486627277550229952668
69341676969500946576714770057
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.82956360044676677478772562548159297224761738223293200854960098584361576615231
Short name T773
Test name
Test status
Simulation time 18445453393 ps
CPU time 147.13 seconds
Started Nov 22 02:15:33 PM PST 23
Finished Nov 22 02:18:01 PM PST 23
Peak memory 202904 kb
Host smart-aeaba4b7-0885-4b3e-95fa-65650c09461e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82956360044676677478772562548159297224761738223293200854960098584361576615231
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.82956360044676677478772562548159297224761738223293200854960098584361576615231
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.79154898739785819443794038636297594838960729988362692980313608861923444464490
Short name T746
Test name
Test status
Simulation time 28731174678 ps
CPU time 755.59 seconds
Started Nov 22 02:15:31 PM PST 23
Finished Nov 22 02:28:08 PM PST 23
Peak memory 378708 kb
Host smart-54075e88-24b8-43f7-b8ae-724974fe2e12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79154898739785819443794038636297594838960729988362692980313608861923444464490 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.79154898739785819443794038636297594838960729988362692980313608861923444464490
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.79690226011454862946281613515575567198073956246936408383848447269616792176235
Short name T285
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.74 seconds
Started Nov 22 02:15:32 PM PST 23
Finished Nov 22 02:15:50 PM PST 23
Peak memory 245668 kb
Host smart-4cfd53ba-f214-49d8-b09d-bbcc95a2946a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796902260114548629462816135155755671980739562469364083838484472696167
92176235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.796902260114548629462816135155755671980739562469364083
83848447269616792176235
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.32795828260602876389556450352809108622514676417419864044535192387655567620038
Short name T901
Test name
Test status
Simulation time 45083829570 ps
CPU time 574.72 seconds
Started Nov 22 02:15:32 PM PST 23
Finished Nov 22 02:25:07 PM PST 23
Peak memory 202872 kb
Host smart-585014a1-a323-4880-b77e-ec3b24def5f6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327958282606028763895564503528091086225146764174198640445351923876555
67620038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access_b2b.3279582826060287638955645035280910862251
4676417419864044535192387655567620038
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.57227398368148081982930734182262467922063582655702384640579139084968332647560
Short name T34
Test name
Test status
Simulation time 607542526 ps
CPU time 6.36 seconds
Started Nov 22 02:15:11 PM PST 23
Finished Nov 22 02:15:18 PM PST 23
Peak memory 203160 kb
Host smart-5912df59-5d6b-45ae-8408-6c883da2a126
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57227398368148081982930734182262467922063582655702384640579139084968332647560 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.57227398368148081982930734182262467922063582655702384640579139084968332647560
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.24126434444600306550725096595247571987288515048997993938816423256675479835798
Short name T674
Test name
Test status
Simulation time 19913691647 ps
CPU time 534.4 seconds
Started Nov 22 02:16:08 PM PST 23
Finished Nov 22 02:25:03 PM PST 23
Peak memory 372544 kb
Host smart-770da34f-5840-4db8-8426-16d6bd1efc20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24126434444600306550725096595247571987288515048997993938816423256675479835798 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.24126434444600306550725096595247571987288515048997993938816423256675479835798
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.100402601544450098298222369865462294965396361917568535451806958331110526384915
Short name T408
Test name
Test status
Simulation time 988289480 ps
CPU time 16.68 seconds
Started Nov 22 02:15:40 PM PST 23
Finished Nov 22 02:15:58 PM PST 23
Peak memory 245560 kb
Host smart-603ffcdc-6421-4c13-847d-710ae9f76bf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100402601544450098298222369865462294965396361917568535451806958331110526384915 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.100402601544450098298222369865462294965396361917568535451806958331110526384915
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.87243327530353853268668658251934026349918591339641118425769711248784055461616
Short name T629
Test name
Test status
Simulation time 624328106 ps
CPU time 1818.04 seconds
Started Nov 22 02:15:23 PM PST 23
Finished Nov 22 02:45:42 PM PST 23
Peak memory 498100 kb
Host smart-63077eef-25b1-4720-8fea-6044aa4d7f8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=87243327530353853268668658251934026349918591339641118425769711248784055461616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sr
am_ctrl_stress_all_with_rand_reset.87243327530353853268668658251934026349918591339641118425769711248784055461616
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.16921806083075200949920920101092736987679304229285350430219786279608109341899
Short name T831
Test name
Test status
Simulation time 9325508496 ps
CPU time 423.08 seconds
Started Nov 22 02:15:32 PM PST 23
Finished Nov 22 02:22:35 PM PST 23
Peak memory 203024 kb
Host smart-cb769564-822b-4dce-bec1-48692a123177
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16921806083075200949920920101092736987679304229285350430219786279608109341899
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.169218060830752009499209201010927369876793042292853
50430219786279608109341899
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.94292077997172572883449446562125852544876356285313504301196413773916967681251
Short name T645
Test name
Test status
Simulation time 1371125703 ps
CPU time 115.18 seconds
Started Nov 22 02:15:25 PM PST 23
Finished Nov 22 02:17:21 PM PST 23
Peak memory 351156 kb
Host smart-b090e360-9d26-40d8-9696-f39d6919cd42
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942920779971725728834494465621258525448763562853135043
01196413773916967681251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.9429207799717257288344
9446562125852544876356285313504301196413773916967681251
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.11661294588224036361485674111255930206305700129767227834240081854120279801144
Short name T845
Test name
Test status
Simulation time 13467153934 ps
CPU time 991.61 seconds
Started Nov 22 02:15:35 PM PST 23
Finished Nov 22 02:32:07 PM PST 23
Peak memory 378760 kb
Host smart-75d4922d-c6c2-45fd-8f15-650fe447ef17
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11661294588224036361485674111255930206305700129767227834240081854120279801144
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during_key_req.116612945882240363614856741112559302063
05700129767227834240081854120279801144
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.17068106108228267560780613832307307576179674580007919372235563676624204714960
Short name T810
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 02:15:54 PM PST 23
Finished Nov 22 02:15:55 PM PST 23
Peak memory 202588 kb
Host smart-c1ea3a4f-62bc-462b-a47a-5650dec92a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170681061082282675607806138323073075761796745800079193722355636766
24204714960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.170681061082282675607806138323073075761796745800079193
72235563676624204714960
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.100731651320455290594090329194194876996961626055413980943631233468393187412527
Short name T615
Test name
Test status
Simulation time 295482808505 ps
CPU time 2580.5 seconds
Started Nov 22 02:15:44 PM PST 23
Finished Nov 22 02:58:46 PM PST 23
Peak memory 202892 kb
Host smart-f2aedcf3-c720-4f3f-b6c6-d4bcadd9c703
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100731651320455290594090329194194876996961626055413980943631233468393187412527 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.100731651320455290594090329194194876996961626055413980943631233468393187412527
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.75053617968069208460862835801008530319015713191011369967840955623448308417732
Short name T984
Test name
Test status
Simulation time 31712811539 ps
CPU time 1018.67 seconds
Started Nov 22 02:15:29 PM PST 23
Finished Nov 22 02:32:28 PM PST 23
Peak memory 368036 kb
Host smart-90f8f9aa-94e7-4cfb-b7a4-e0944c928ce4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75053617968069208460862835801008530319015713191011369967840955623448308417732 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.75053617968069208460862835801008530319015713191011369967840955623448308417732
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.36315286697769896124129428172773932622111942054747895283622100691607115541728
Short name T437
Test name
Test status
Simulation time 19084394710 ps
CPU time 103.8 seconds
Started Nov 22 02:16:09 PM PST 23
Finished Nov 22 02:17:53 PM PST 23
Peak memory 211072 kb
Host smart-55839676-c08c-4d66-906f-d6895263c446
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36315286697769896124129428172773932622111942054747895283622100691607115541728 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.36315286697769896124129428172773932622111942054747895283622100691607115541728
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.98695052462029185844791697845923642856949208639742803639451263909791699547415
Short name T753
Test name
Test status
Simulation time 1342947357 ps
CPU time 114.73 seconds
Started Nov 22 02:15:55 PM PST 23
Finished Nov 22 02:17:51 PM PST 23
Peak memory 351176 kb
Host smart-2432722f-3942-4d70-9341-9db29bb2abbe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9869505246202918584479169784592364285694920863974280363
9451263909791699547415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_max_throughput.98695052462029185844791697845923642
856949208639742803639451263909791699547415
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.47245868682126866576476338184303603461565579450210072324370923225436553227872
Short name T982
Test name
Test status
Simulation time 4750777237 ps
CPU time 80.79 seconds
Started Nov 22 02:15:41 PM PST 23
Finished Nov 22 02:17:02 PM PST 23
Peak memory 212380 kb
Host smart-312630b0-a176-4702-9dff-15675f4177cf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47245868682126866576476338184303603461565579450210072324370923225436
553227872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.472458686821268665764763381843036034615655794502
10072324370923225436553227872
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.37076414356729749279693114167688840226111712453936597819977196094096802185535
Short name T859
Test name
Test status
Simulation time 18445453393 ps
CPU time 155.38 seconds
Started Nov 22 02:15:35 PM PST 23
Finished Nov 22 02:18:11 PM PST 23
Peak memory 202800 kb
Host smart-0a6f05e1-bd8a-4043-a836-5d3a159c6b63
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37076414356729749279693114167688840226111712453936597819977196094096802185535
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.37076414356729749279693114167688840226111712453936597819977196094096802185535
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.56963274442479364656076181303183696223383675603680843534292155305494275105928
Short name T416
Test name
Test status
Simulation time 28731174678 ps
CPU time 753.04 seconds
Started Nov 22 02:15:44 PM PST 23
Finished Nov 22 02:28:17 PM PST 23
Peak memory 378688 kb
Host smart-7e09a663-b19f-4768-9b69-2c74b1577799
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56963274442479364656076181303183696223383675603680843534292155305494275105928 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.56963274442479364656076181303183696223383675603680843534292155305494275105928
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.1316076884956611263430846668369433890294609719524604101586594594677916100422
Short name T570
Test name
Test status
Simulation time 1006378621 ps
CPU time 19 seconds
Started Nov 22 02:15:10 PM PST 23
Finished Nov 22 02:15:29 PM PST 23
Peak memory 245692 kb
Host smart-6368f578-3f7f-4e98-8ac2-515145111267
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131607688495661126343084666836943389029460971952460410158659459467791
6100422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.1316076884956611263430846668369433890294609719524604101
586594594677916100422
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.85897369651807382915839856006983293793657440980109803057375067056055461825160
Short name T794
Test name
Test status
Simulation time 45083829570 ps
CPU time 570.98 seconds
Started Nov 22 02:15:23 PM PST 23
Finished Nov 22 02:24:55 PM PST 23
Peak memory 202828 kb
Host smart-d623589d-4068-4498-abec-dad8a1715bb1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858973696518073829158398560069832937936574409801098030573750670560554
61825160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access_b2b.8589736965180738291583985600698329379365
7440980109803057375067056055461825160
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.72996725147362958598219311827384973930115721347792952956916415387241519351684
Short name T33
Test name
Test status
Simulation time 607542526 ps
CPU time 5.9 seconds
Started Nov 22 02:15:44 PM PST 23
Finished Nov 22 02:15:50 PM PST 23
Peak memory 203092 kb
Host smart-1d29bcf7-e303-4a1b-ad0b-762d8220f3fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72996725147362958598219311827384973930115721347792952956916415387241519351684 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.72996725147362958598219311827384973930115721347792952956916415387241519351684
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.249095944332486127729293394130891832904205094404766405831946290489203881940
Short name T463
Test name
Test status
Simulation time 19913691647 ps
CPU time 501.24 seconds
Started Nov 22 02:15:41 PM PST 23
Finished Nov 22 02:24:03 PM PST 23
Peak memory 372452 kb
Host smart-7be614b0-d0c2-4e27-8efa-96ad61387cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249095944332486127729293394130891832904205094404766405831946290489203881940 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.249095944332486127729293394130891832904205094404766405831946290489203881940
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.50813585665712812478427933478573113592211039927563619584700856510374705780840
Short name T947
Test name
Test status
Simulation time 988289480 ps
CPU time 17.15 seconds
Started Nov 22 02:15:33 PM PST 23
Finished Nov 22 02:15:50 PM PST 23
Peak memory 245648 kb
Host smart-ed00af72-80d6-4378-a131-b6c5d908d3d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50813585665712812478427933478573113592211039927563619584700856510374705780840 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.50813585665712812478427933478573113592211039927563619584700856510374705780840
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.52122101929598311338855182533226757461958519624688932938978663903749951015361
Short name T907
Test name
Test status
Simulation time 624328106 ps
CPU time 1980.32 seconds
Started Nov 22 02:15:39 PM PST 23
Finished Nov 22 02:48:41 PM PST 23
Peak memory 498132 kb
Host smart-b0922d30-3117-4c78-858f-1f55843d93f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=52122101929598311338855182533226757461958519624688932938978663903749951015361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sr
am_ctrl_stress_all_with_rand_reset.52122101929598311338855182533226757461958519624688932938978663903749951015361
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.52330622628994026425435822093576027872328704636852400648281107642934809908100
Short name T90
Test name
Test status
Simulation time 9325508496 ps
CPU time 420.67 seconds
Started Nov 22 02:15:38 PM PST 23
Finished Nov 22 02:22:41 PM PST 23
Peak memory 202808 kb
Host smart-1c05bbd6-9036-4a68-bca0-c78f2ebcba2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52330622628994026425435822093576027872328704636852400648281107642934809908100
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.523306226289940264254358220935760278723287046368524
00648281107642934809908100
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.89728300076405509086103304650787430289103988395382791923738748133961561031259
Short name T809
Test name
Test status
Simulation time 1371125703 ps
CPU time 130.18 seconds
Started Nov 22 02:16:08 PM PST 23
Finished Nov 22 02:18:19 PM PST 23
Peak memory 351164 kb
Host smart-6de3a910-460b-4c73-908a-0df88cfdc441
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897283000764055090861033046507874302891039883953827919
23738748133961561031259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.8972830007640550908610
3304650787430289103988395382791923738748133961561031259
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.87562193688731191266452594972679877883308362802923228622927635956730978539137
Short name T602
Test name
Test status
Simulation time 13467153934 ps
CPU time 882.85 seconds
Started Nov 22 02:15:29 PM PST 23
Finished Nov 22 02:30:13 PM PST 23
Peak memory 378748 kb
Host smart-a184e6fb-43ec-443a-94e8-59b153e6975e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87562193688731191266452594972679877883308362802923228622927635956730978539137
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during_key_req.875621936887311912664525949726798778833
08362802923228622927635956730978539137
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.84705385896864626927481458058248432955750801364588174053087446182331765645635
Short name T967
Test name
Test status
Simulation time 16600825 ps
CPU time 0.59 seconds
Started Nov 22 02:15:33 PM PST 23
Finished Nov 22 02:15:34 PM PST 23
Peak memory 202704 kb
Host smart-fc905369-83ee-4546-a662-f2e6c257956f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847053858968646269274814580582484329557508013645881740530874461823
31765645635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.847053858968646269274814580582484329557508013645881740
53087446182331765645635
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.105193094535483714844872544281207657801972482491276796861712101581580915129980
Short name T872
Test name
Test status
Simulation time 295482808505 ps
CPU time 2708.35 seconds
Started Nov 22 02:15:41 PM PST 23
Finished Nov 22 03:00:51 PM PST 23
Peak memory 202988 kb
Host smart-a9920e25-4918-49bc-ad15-e265b2a8a3de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105193094535483714844872544281207657801972482491276796861712101581580915129980 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.105193094535483714844872544281207657801972482491276796861712101581580915129980
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.12855434829414845135527653813949338107238080635092199653913476110435834100090
Short name T364
Test name
Test status
Simulation time 31712811539 ps
CPU time 881.89 seconds
Started Nov 22 02:15:39 PM PST 23
Finished Nov 22 02:30:22 PM PST 23
Peak memory 368032 kb
Host smart-82d14e67-ec19-46cf-ac5e-e036a3481a9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12855434829414845135527653813949338107238080635092199653913476110435834100090 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.12855434829414845135527653813949338107238080635092199653913476110435834100090
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.76223199221685896448251480885957819859135364812353216447271908908701538427759
Short name T370
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.74 seconds
Started Nov 22 02:15:40 PM PST 23
Finished Nov 22 02:17:26 PM PST 23
Peak memory 211044 kb
Host smart-1c33a22b-628b-4141-8ff4-9744c6e43069
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76223199221685896448251480885957819859135364812353216447271908908701538427759 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.76223199221685896448251480885957819859135364812353216447271908908701538427759
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.19110897249859128951060721289567038327922173806498756309187778578650545687047
Short name T903
Test name
Test status
Simulation time 1342947357 ps
CPU time 129.92 seconds
Started Nov 22 02:15:57 PM PST 23
Finished Nov 22 02:18:07 PM PST 23
Peak memory 351148 kb
Host smart-f7cbd0a7-615a-424d-99ab-8c1d1f266c40
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911089724985912895106072128956703832792217380649875630
9187778578650545687047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_max_throughput.19110897249859128951060721289567038
327922173806498756309187778578650545687047
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.22043520663430161257414770571493924445718783967910235710911975591919085420353
Short name T72
Test name
Test status
Simulation time 4750777237 ps
CPU time 83.78 seconds
Started Nov 22 02:15:40 PM PST 23
Finished Nov 22 02:17:05 PM PST 23
Peak memory 212284 kb
Host smart-3b73e8be-eb4b-487e-9c1b-9f2979f37a45
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22043520663430161257414770571493924445718783967910235710911975591919
085420353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.220435206634301612574147705714939244457187839679
10235710911975591919085420353
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.74970769801280865540686380466535004765713244638392025304268644361009238207558
Short name T816
Test name
Test status
Simulation time 18445453393 ps
CPU time 155.52 seconds
Started Nov 22 02:15:34 PM PST 23
Finished Nov 22 02:18:10 PM PST 23
Peak memory 202800 kb
Host smart-01bcd85b-b0b6-47a3-8f20-458a37ed463c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74970769801280865540686380466535004765713244638392025304268644361009238207558
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.74970769801280865540686380466535004765713244638392025304268644361009238207558
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.90815727318057904607444491449043072468873097577684081916039275652328261924605
Short name T608
Test name
Test status
Simulation time 28731174678 ps
CPU time 756.01 seconds
Started Nov 22 02:15:39 PM PST 23
Finished Nov 22 02:28:16 PM PST 23
Peak memory 378568 kb
Host smart-b23a6f33-5850-42e3-9917-833025966f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90815727318057904607444491449043072468873097577684081916039275652328261924605 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.90815727318057904607444491449043072468873097577684081916039275652328261924605
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.52150251779741359924693691361012151962035095866283953469890240568344186332943
Short name T738
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.03 seconds
Started Nov 22 02:15:34 PM PST 23
Finished Nov 22 02:15:53 PM PST 23
Peak memory 245648 kb
Host smart-d3973d8f-def8-49c6-a9e4-3345cefccb2f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521502517797413599246936913610121519620350958662839534698902405683441
86332943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.521502517797413599246936913610121519620350958662839534
69890240568344186332943
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.44600697952367689978462185657674990985130999417142434274431303891750948476864
Short name T792
Test name
Test status
Simulation time 45083829570 ps
CPU time 557.42 seconds
Started Nov 22 02:15:34 PM PST 23
Finished Nov 22 02:24:52 PM PST 23
Peak memory 202868 kb
Host smart-bdbe3960-502f-4a6e-a126-c0b823b0977a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446006979523676899784621856576749909851309994171424342744313038917509
48476864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access_b2b.4460069795236768997846218565767499098513
0999417142434274431303891750948476864
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.110110458426339301985127392722856139925481377290108059811435473177848799851259
Short name T765
Test name
Test status
Simulation time 607542526 ps
CPU time 6.31 seconds
Started Nov 22 02:16:07 PM PST 23
Finished Nov 22 02:16:14 PM PST 23
Peak memory 203156 kb
Host smart-c3c8bfaa-4edf-4354-b207-bc8caa71d4f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110110458426339301985127392722856139925481377290108059811435473177848799851259 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.110110458426339301985127392722856139925481377290108059811435473177848799851259
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.62307982455950884751365872066666041332797691274169856575080274753699546199842
Short name T846
Test name
Test status
Simulation time 19913691647 ps
CPU time 612.47 seconds
Started Nov 22 02:15:57 PM PST 23
Finished Nov 22 02:26:10 PM PST 23
Peak memory 372560 kb
Host smart-32906efa-541c-4ab7-9ff8-3fdf5e3dfe2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62307982455950884751365872066666041332797691274169856575080274753699546199842 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.62307982455950884751365872066666041332797691274169856575080274753699546199842
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.108325564920742785734416567968791505710411249868732803551958250075743475702864
Short name T649
Test name
Test status
Simulation time 988289480 ps
CPU time 16.27 seconds
Started Nov 22 02:15:40 PM PST 23
Finished Nov 22 02:15:57 PM PST 23
Peak memory 245672 kb
Host smart-17c74c5a-a5ae-4333-b82f-d827efefb35b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108325564920742785734416567968791505710411249868732803551958250075743475702864 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.108325564920742785734416567968791505710411249868732803551958250075743475702864
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.102368997976555376267361705160721654908356934926699138980328839964676696513767
Short name T534
Test name
Test status
Simulation time 624328106 ps
CPU time 2068.68 seconds
Started Nov 22 02:15:33 PM PST 23
Finished Nov 22 02:50:03 PM PST 23
Peak memory 498188 kb
Host smart-5851047a-a364-4793-beb4-9acd09677e28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=102368997976555376267361705160721654908356934926699138980328839964676696513767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s
ram_ctrl_stress_all_with_rand_reset.102368997976555376267361705160721654908356934926699138980328839964676696513767
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.21603020713033623735238156394542090654470632580767302735065205239098807577520
Short name T91
Test name
Test status
Simulation time 9325508496 ps
CPU time 414.8 seconds
Started Nov 22 02:15:45 PM PST 23
Finished Nov 22 02:22:41 PM PST 23
Peak memory 202868 kb
Host smart-a2a3d1b3-62c1-422f-b7b3-e8c9e7835c1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21603020713033623735238156394542090654470632580767302735065205239098807577520
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.216030207130336237352381563945420906544706325807673
02735065205239098807577520
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.88320076030398873199585699704991634393952664189495241422895066052681096533594
Short name T633
Test name
Test status
Simulation time 1371125703 ps
CPU time 113.89 seconds
Started Nov 22 02:16:10 PM PST 23
Finished Nov 22 02:18:04 PM PST 23
Peak memory 351156 kb
Host smart-64dfd67c-2e8a-46f5-a886-e38d14797115
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883200760303988731995856997049916343939526641894952414
22895066052681096533594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.8832007603039887319958
5699704991634393952664189495241422895066052681096533594
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.114346420042087711565982589589701360225720307282038237338541685755385717936792
Short name T801
Test name
Test status
Simulation time 13467153934 ps
CPU time 1038.94 seconds
Started Nov 22 02:16:10 PM PST 23
Finished Nov 22 02:33:29 PM PST 23
Peak memory 378756 kb
Host smart-2279cbbc-3316-4a58-9cee-a13262b37bc2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11434642004208771156598258958970136022572030728203823733854168575538571793679
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during_key_req.11434642004208771156598258958970136022
5720307282038237338541685755385717936792
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.75657295621288676170368420425066570151633563959994716994329173050897508578492
Short name T874
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:16:27 PM PST 23
Finished Nov 22 02:16:28 PM PST 23
Peak memory 202520 kb
Host smart-2e03382d-4a04-4e04-ad00-771f78e03bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756572956212886761703684204250665701516335639599947169943291730508
97508578492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.756572956212886761703684204250665701516335639599947169
94329173050897508578492
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.44602356180633733702285494857334330019584774211446421271486108674811050564124
Short name T566
Test name
Test status
Simulation time 295482808505 ps
CPU time 2596.01 seconds
Started Nov 22 02:15:40 PM PST 23
Finished Nov 22 02:58:57 PM PST 23
Peak memory 202916 kb
Host smart-ff341cb7-ed02-49ba-a1b2-033b7f1813f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44602356180633733702285494857334330019584774211446421271486108674811050564124 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.44602356180633733702285494857334330019584774211446421271486108674811050564124
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.54432305805330321039037673629734240891761093911063908735109865126806274007877
Short name T599
Test name
Test status
Simulation time 31712811539 ps
CPU time 753.08 seconds
Started Nov 22 02:15:57 PM PST 23
Finished Nov 22 02:28:30 PM PST 23
Peak memory 368048 kb
Host smart-9e7fb9f6-1f66-4d03-ace1-dd8979f109ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54432305805330321039037673629734240891761093911063908735109865126806274007877 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.54432305805330321039037673629734240891761093911063908735109865126806274007877
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.44134011058515930491646826222262648674868965502023744992416183894440472925593
Short name T966
Test name
Test status
Simulation time 19084394710 ps
CPU time 107.13 seconds
Started Nov 22 02:15:56 PM PST 23
Finished Nov 22 02:17:44 PM PST 23
Peak memory 211036 kb
Host smart-f38f2532-9bea-439a-b1f2-65f193f487dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44134011058515930491646826222262648674868965502023744992416183894440472925593 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.44134011058515930491646826222262648674868965502023744992416183894440472925593
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.33303725719218494204346271096983450484305023222147512225931023498853493173474
Short name T681
Test name
Test status
Simulation time 1342947357 ps
CPU time 133.83 seconds
Started Nov 22 02:16:10 PM PST 23
Finished Nov 22 02:18:25 PM PST 23
Peak memory 351160 kb
Host smart-b07dc8d4-c10f-48c2-b108-cbb2c51fcf5b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330372571921849420434627109698345048430502322214751222
5931023498853493173474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_max_throughput.33303725719218494204346271096983450
484305023222147512225931023498853493173474
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.17205778229473446099319106103099986125965617817991942581425988029559745433805
Short name T346
Test name
Test status
Simulation time 4750777237 ps
CPU time 80.34 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:17:57 PM PST 23
Peak memory 212328 kb
Host smart-34f964c7-d91c-4bc4-ba56-a7cf18262ae0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17205778229473446099319106103099986125965617817991942581425988029559
745433805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.172057782294734460993191061030999861259656178179
91942581425988029559745433805
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.103851882710681783369752967406881566141139198216326482875551473249844078618426
Short name T489
Test name
Test status
Simulation time 18445453393 ps
CPU time 156.57 seconds
Started Nov 22 02:16:39 PM PST 23
Finished Nov 22 02:19:17 PM PST 23
Peak memory 202748 kb
Host smart-cabc1b58-0891-4549-96fb-1c8fa08fa97f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103851882710681783369752967406881566141139198216326482875551473249844078618426
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.103851882710681783369752967406881566141139198216326482875551473249844078618426
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.900926893051005991284449800105610208099522215279061189173414384931748957592
Short name T454
Test name
Test status
Simulation time 28731174678 ps
CPU time 807.24 seconds
Started Nov 22 02:15:42 PM PST 23
Finished Nov 22 02:29:10 PM PST 23
Peak memory 378656 kb
Host smart-8ba2373e-3bde-41a3-9acc-3da8af93fe8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900926893051005991284449800105610208099522215279061189173414384931748957592 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.900926893051005991284449800105610208099522215279061189173414384931748957592
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.43754925797754263790345646227920119121546918138416808676181810018664281742209
Short name T393
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.9 seconds
Started Nov 22 02:15:57 PM PST 23
Finished Nov 22 02:16:16 PM PST 23
Peak memory 245652 kb
Host smart-53930729-b6c9-454c-b8d5-f958a21d7964
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437549257977542637903456462279201191215469181384168086761818100186642
81742209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.437549257977542637903456462279201191215469181384168086
76181810018664281742209
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3381712537472595842095161957008492340346944109855315742166551121666800378702
Short name T791
Test name
Test status
Simulation time 45083829570 ps
CPU time 556.94 seconds
Started Nov 22 02:16:11 PM PST 23
Finished Nov 22 02:25:28 PM PST 23
Peak memory 202796 kb
Host smart-45d43703-8287-4a8e-b6e8-97844d325a82
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338171253747259584209516195700849234034694410985531574216655112166680
0378702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access_b2b.33817125374725958420951619570084923403469
44109855315742166551121666800378702
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.78463973383072057189214075432218576056975208160017616562191973177016033658088
Short name T556
Test name
Test status
Simulation time 607542526 ps
CPU time 6.18 seconds
Started Nov 22 02:16:40 PM PST 23
Finished Nov 22 02:16:47 PM PST 23
Peak memory 203048 kb
Host smart-c8d04e6d-0594-4d92-9b40-d4a0b6b1c247
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78463973383072057189214075432218576056975208160017616562191973177016033658088 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.78463973383072057189214075432218576056975208160017616562191973177016033658088
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.86395880569733162336951939425182209671510236742075413851979181162844710060220
Short name T468
Test name
Test status
Simulation time 19913691647 ps
CPU time 487.46 seconds
Started Nov 22 02:16:33 PM PST 23
Finished Nov 22 02:24:41 PM PST 23
Peak memory 372536 kb
Host smart-dba5e462-e8bd-4d71-adc0-313f70eb054c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86395880569733162336951939425182209671510236742075413851979181162844710060220 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.86395880569733162336951939425182209671510236742075413851979181162844710060220
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.65367019345679478419857375450005750387657099640465995761082446777600735533712
Short name T219
Test name
Test status
Simulation time 988289480 ps
CPU time 18.51 seconds
Started Nov 22 02:15:39 PM PST 23
Finished Nov 22 02:15:59 PM PST 23
Peak memory 245760 kb
Host smart-0ae0a377-3d47-492a-9768-c1770226a4db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65367019345679478419857375450005750387657099640465995761082446777600735533712 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.65367019345679478419857375450005750387657099640465995761082446777600735533712
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.66854663679532477894743093357594428564817598992256046596781194500252828030532
Short name T807
Test name
Test status
Simulation time 624328106 ps
CPU time 2062.22 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:50:58 PM PST 23
Peak memory 498188 kb
Host smart-b766512c-73dd-4c05-94df-5703d920422d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=66854663679532477894743093357594428564817598992256046596781194500252828030532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sr
am_ctrl_stress_all_with_rand_reset.66854663679532477894743093357594428564817598992256046596781194500252828030532
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.19608932683205075364089915578041697891498560757897379659382393292333542186904
Short name T647
Test name
Test status
Simulation time 9325508496 ps
CPU time 421.5 seconds
Started Nov 22 02:16:06 PM PST 23
Finished Nov 22 02:23:08 PM PST 23
Peak memory 202852 kb
Host smart-98178a9a-3885-44af-8672-2531f97fa8e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19608932683205075364089915578041697891498560757897379659382393292333542186904
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.196089326832050753640899155780416978914985607578973
79659382393292333542186904
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.114751904522240563823415875018483432625682716427760108686365024668403508533821
Short name T466
Test name
Test status
Simulation time 1371125703 ps
CPU time 133.09 seconds
Started Nov 22 02:15:40 PM PST 23
Finished Nov 22 02:17:54 PM PST 23
Peak memory 351208 kb
Host smart-da38354b-99be-45ba-9d62-7d49f40f0188
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114751904522240563823415875018483432625682716427760108
686365024668403508533821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.114751904522240563823
415875018483432625682716427760108686365024668403508533821
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.19328237840184942201790055183128751134008240216242445550563566742584880626374
Short name T519
Test name
Test status
Simulation time 13467153934 ps
CPU time 776.68 seconds
Started Nov 22 02:16:29 PM PST 23
Finished Nov 22 02:29:26 PM PST 23
Peak memory 378752 kb
Host smart-da011381-e2ae-4852-b6b2-d80972a45b3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19328237840184942201790055183128751134008240216242445550563566742584880626374
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during_key_req.193282378401849422017900551831287511340
08240216242445550563566742584880626374
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.86580180762063962361962053069156801817757226393996422296676863535951323950741
Short name T538
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:16:37 PM PST 23
Peak memory 202560 kb
Host smart-2172f7d6-d2e5-430a-a5b2-76af6468f901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865801807620639623619620530691568018177572263939964222966768635359
51323950741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.865801807620639623619620530691568018177572263939964222
96676863535951323950741
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.110771919754261677022545992248119452891857259762349262972088850591899679749741
Short name T617
Test name
Test status
Simulation time 295482808505 ps
CPU time 2696.21 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 03:01:33 PM PST 23
Peak memory 202872 kb
Host smart-10f0edd1-f845-4fe0-aaad-f8867e7739a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110771919754261677022545992248119452891857259762349262972088850591899679749741 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.110771919754261677022545992248119452891857259762349262972088850591899679749741
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.72084163875470856898064728419751495286333367190841305246749749348384032623593
Short name T505
Test name
Test status
Simulation time 31712811539 ps
CPU time 804.82 seconds
Started Nov 22 02:15:47 PM PST 23
Finished Nov 22 02:29:12 PM PST 23
Peak memory 368000 kb
Host smart-2bb1aaeb-5536-45c9-94ae-680674c6966c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72084163875470856898064728419751495286333367190841305246749749348384032623593 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.72084163875470856898064728419751495286333367190841305246749749348384032623593
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.51791548675083148346517323207151823302144100660802798912886071735858946704661
Short name T289
Test name
Test status
Simulation time 19084394710 ps
CPU time 102.35 seconds
Started Nov 22 02:16:33 PM PST 23
Finished Nov 22 02:18:16 PM PST 23
Peak memory 211088 kb
Host smart-8d07ce97-5fdd-4f18-9a18-a92b10a577d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51791548675083148346517323207151823302144100660802798912886071735858946704661 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.51791548675083148346517323207151823302144100660802798912886071735858946704661
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.70121227276988698262618321374438300728651712041346335420145451585145600332286
Short name T263
Test name
Test status
Simulation time 1342947357 ps
CPU time 130.21 seconds
Started Nov 22 02:16:29 PM PST 23
Finished Nov 22 02:18:40 PM PST 23
Peak memory 351092 kb
Host smart-2bb00b13-cf5c-415f-852c-99d3a12f72a9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7012122727698869826261832137443830072865171204134633542
0145451585145600332286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_max_throughput.70121227276988698262618321374438300
728651712041346335420145451585145600332286
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.44265874371442963590998448772182683807760902034973303618497922682391871407247
Short name T315
Test name
Test status
Simulation time 4750777237 ps
CPU time 77.64 seconds
Started Nov 22 02:16:30 PM PST 23
Finished Nov 22 02:17:48 PM PST 23
Peak memory 212328 kb
Host smart-daaa42be-ebb3-49c1-a2c2-7303a99ee12b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44265874371442963590998448772182683807760902034973303618497922682391
871407247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.442658743714429635909984487721826838077609020349
73303618497922682391871407247
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.39754068259059653937449656862943416085762014304626448758293620615079595834133
Short name T656
Test name
Test status
Simulation time 18445453393 ps
CPU time 157.69 seconds
Started Nov 22 02:16:15 PM PST 23
Finished Nov 22 02:18:54 PM PST 23
Peak memory 202760 kb
Host smart-33a91b1d-c3cd-4497-ae61-8acd97e2c9ca
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754068259059653937449656862943416085762014304626448758293620615079595834133
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.39754068259059653937449656862943416085762014304626448758293620615079595834133
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.45884557439662093237824619866388004235413777549810610529736598853441084750864
Short name T767
Test name
Test status
Simulation time 28731174678 ps
CPU time 733.98 seconds
Started Nov 22 02:16:17 PM PST 23
Finished Nov 22 02:28:32 PM PST 23
Peak memory 378608 kb
Host smart-9e269660-6681-4e7c-82e2-f2fd5b641ac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45884557439662093237824619866388004235413777549810610529736598853441084750864 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.45884557439662093237824619866388004235413777549810610529736598853441084750864
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.89148292826568407425882032098855544508955327521114279739457566404026792122171
Short name T16
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.61 seconds
Started Nov 22 02:16:37 PM PST 23
Finished Nov 22 02:16:56 PM PST 23
Peak memory 245700 kb
Host smart-0ec009b9-fecc-42ff-8a86-ace41f848a06
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891482928265684074258820320988555445089553275211142797394575664040267
92122171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.891482928265684074258820320988555445089553275211142797
39457566404026792122171
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.59015011173049538936240159346923575589672958507370985891103977813337040319831
Short name T532
Test name
Test status
Simulation time 45083829570 ps
CPU time 580.38 seconds
Started Nov 22 02:15:47 PM PST 23
Finished Nov 22 02:25:28 PM PST 23
Peak memory 202820 kb
Host smart-89b376cf-d508-495d-80d8-68e1c5782e1d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590150111730495389362401593469235755896729585073709858911039778133370
40319831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access_b2b.5901501117304953893624015934692357558967
2958507370985891103977813337040319831
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.49920883607760877312706712563492771093697173221931315061922057109293219155150
Short name T484
Test name
Test status
Simulation time 607542526 ps
CPU time 6.09 seconds
Started Nov 22 02:16:12 PM PST 23
Finished Nov 22 02:16:19 PM PST 23
Peak memory 203096 kb
Host smart-b288d39e-8102-4140-99ba-9ef8f6d68209
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49920883607760877312706712563492771093697173221931315061922057109293219155150 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.49920883607760877312706712563492771093697173221931315061922057109293219155150
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.108018975213382549280179418836203037511847801945515954825803910566195485126689
Short name T222
Test name
Test status
Simulation time 19913691647 ps
CPU time 582.59 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:26:20 PM PST 23
Peak memory 372528 kb
Host smart-802ec4f8-16bb-4bc7-8c53-f05a5f9907ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108018975213382549280179418836203037511847801945515954825803910566195485126689 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.108018975213382549280179418836203037511847801945515954825803910566195485126689
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.81668904463587375157435643687697582545863517586637447336894144303543512038504
Short name T563
Test name
Test status
Simulation time 988289480 ps
CPU time 17.64 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:16:54 PM PST 23
Peak memory 245612 kb
Host smart-aa91c7dc-73c6-4faf-9b48-675fa1ff2b9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81668904463587375157435643687697582545863517586637447336894144303543512038504 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.81668904463587375157435643687697582545863517586637447336894144303543512038504
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.81817349645573421206024420298262545856333806326504897595070196359659190142030
Short name T536
Test name
Test status
Simulation time 9325508496 ps
CPU time 423.86 seconds
Started Nov 22 02:16:29 PM PST 23
Finished Nov 22 02:23:33 PM PST 23
Peak memory 202892 kb
Host smart-8a87ed78-d023-4b7d-8860-9aee456fa5ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81817349645573421206024420298262545856333806326504897595070196359659190142030
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.818173496455734212060244202982625458563338063265048
97595070196359659190142030
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.17904989559326418779320820254947316233572194466000368756912468147830491171113
Short name T731
Test name
Test status
Simulation time 1371125703 ps
CPU time 106.02 seconds
Started Nov 22 02:16:38 PM PST 23
Finished Nov 22 02:18:25 PM PST 23
Peak memory 351152 kb
Host smart-547a8ff9-7fda-4b0e-8979-f77ab84a490c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179049895593264187793208202549473162335721944660003687
56912468147830491171113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.1790498955932641877932
0820254947316233572194466000368756912468147830491171113
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.17576526508777412180660126583946173617506772596571048410707033963447109799904
Short name T757
Test name
Test status
Simulation time 13467153934 ps
CPU time 839.78 seconds
Started Nov 22 02:16:30 PM PST 23
Finished Nov 22 02:30:30 PM PST 23
Peak memory 378740 kb
Host smart-6883b8c8-3c44-49cc-8bb8-1f9a4d8c1c0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17576526508777412180660126583946173617506772596571048410707033963447109799904
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during_key_req.175765265087774121806601265839461736175
06772596571048410707033963447109799904
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.20553349979514760296853788944258794058438211014435538841053446829063562528476
Short name T909
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:16:37 PM PST 23
Peak memory 202528 kb
Host smart-0867ad68-939d-4448-9779-0624921a79a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205533499795147602968537889442587940584382110144355388410534468290
63562528476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.205533499795147602968537889442587940584382110144355388
41053446829063562528476
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.32968259489382438196346535577488404782488573182385831785699700767027199877499
Short name T806
Test name
Test status
Simulation time 295482808505 ps
CPU time 2807.46 seconds
Started Nov 22 02:16:30 PM PST 23
Finished Nov 22 03:03:18 PM PST 23
Peak memory 202852 kb
Host smart-26849969-cfaa-42ba-8fdc-328b6ea8e426
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32968259489382438196346535577488404782488573182385831785699700767027199877499 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.32968259489382438196346535577488404782488573182385831785699700767027199877499
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.60816276539070885268144314143501002571136613908952331842111003440400775812383
Short name T407
Test name
Test status
Simulation time 31712811539 ps
CPU time 779.51 seconds
Started Nov 22 02:16:17 PM PST 23
Finished Nov 22 02:29:17 PM PST 23
Peak memory 367968 kb
Host smart-073d5769-6b26-4614-b452-5519efcf9289
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60816276539070885268144314143501002571136613908952331842111003440400775812383 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.60816276539070885268144314143501002571136613908952331842111003440400775812383
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.46455225594263558323970738618487204582986815920175819038778529027261073003640
Short name T421
Test name
Test status
Simulation time 19084394710 ps
CPU time 103.11 seconds
Started Nov 22 02:16:33 PM PST 23
Finished Nov 22 02:18:17 PM PST 23
Peak memory 211064 kb
Host smart-f4b2323b-eaf1-4b35-80fe-1a1a265d8b40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46455225594263558323970738618487204582986815920175819038778529027261073003640 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.46455225594263558323970738618487204582986815920175819038778529027261073003640
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.98548593667592119031598439451159085611166679020696862644940852675680934829415
Short name T594
Test name
Test status
Simulation time 1342947357 ps
CPU time 121.51 seconds
Started Nov 22 02:16:16 PM PST 23
Finished Nov 22 02:18:18 PM PST 23
Peak memory 351156 kb
Host smart-cb9ddfd7-f70f-4f13-a322-9c788e2a6581
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9854859366759211903159843945115908561116667902069686264
4940852675680934829415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_max_throughput.98548593667592119031598439451159085
611166679020696862644940852675680934829415
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.48869948700450274565363325836072421677170893126698253756135140083752742354041
Short name T390
Test name
Test status
Simulation time 4750777237 ps
CPU time 77.36 seconds
Started Nov 22 02:15:55 PM PST 23
Finished Nov 22 02:17:13 PM PST 23
Peak memory 212384 kb
Host smart-08b9a909-f6a8-4aef-ac71-eba52f987285
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48869948700450274565363325836072421677170893126698253756135140083752
742354041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.488699487004502745653633258360724216771708931266
98253756135140083752742354041
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.22239616931141311000666627986256954588423158076955429168544292685138784901522
Short name T432
Test name
Test status
Simulation time 18445453393 ps
CPU time 162.4 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:19:18 PM PST 23
Peak memory 202736 kb
Host smart-ac27dc74-98f8-4616-9e03-2bfd74207426
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22239616931141311000666627986256954588423158076955429168544292685138784901522
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.22239616931141311000666627986256954588423158076955429168544292685138784901522
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.42551197099507480740930915472839066110086032701629148166307304764192704929520
Short name T92
Test name
Test status
Simulation time 28731174678 ps
CPU time 892.33 seconds
Started Nov 22 02:16:39 PM PST 23
Finished Nov 22 02:31:32 PM PST 23
Peak memory 378608 kb
Host smart-d074c554-f500-4d1e-9df4-2a599a46d3f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42551197099507480740930915472839066110086032701629148166307304764192704929520 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.42551197099507480740930915472839066110086032701629148166307304764192704929520
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.5412085516736960284211680810206859439661726142591168226545514999150128919261
Short name T863
Test name
Test status
Simulation time 1006378621 ps
CPU time 20.49 seconds
Started Nov 22 02:16:29 PM PST 23
Finished Nov 22 02:16:50 PM PST 23
Peak memory 245728 kb
Host smart-d56fc6c3-60ab-475a-9183-576ef2851eec
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541208551673696028421168081020685943966172614259116822654551499915012
8919261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.5412085516736960284211680810206859439661726142591168226
545514999150128919261
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.25873578498341103532309778636349489537888402650520699001742666069652420492002
Short name T43
Test name
Test status
Simulation time 45083829570 ps
CPU time 578.56 seconds
Started Nov 22 02:16:28 PM PST 23
Finished Nov 22 02:26:08 PM PST 23
Peak memory 202852 kb
Host smart-bef0e9e6-b068-44d4-9114-07a416fddd7a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258735784983411035323097786363494895378884026505206990017426660696524
20492002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access_b2b.2587357849834110353230977863634948953788
8402650520699001742666069652420492002
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.103895272733032074793231045357004878586427414792840984783180957394603103988239
Short name T304
Test name
Test status
Simulation time 607542526 ps
CPU time 6.1 seconds
Started Nov 22 02:16:38 PM PST 23
Finished Nov 22 02:16:45 PM PST 23
Peak memory 203064 kb
Host smart-c2b9282c-dca5-4ce6-88bb-c24498f1f19c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103895272733032074793231045357004878586427414792840984783180957394603103988239 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.103895272733032074793231045357004878586427414792840984783180957394603103988239
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.30742445205885625517637163976937298712401923044942903643110818927352830519968
Short name T680
Test name
Test status
Simulation time 19913691647 ps
CPU time 536.86 seconds
Started Nov 22 02:16:30 PM PST 23
Finished Nov 22 02:25:28 PM PST 23
Peak memory 372528 kb
Host smart-13e4bbdc-4292-4f88-b724-cf5ed8ac042f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30742445205885625517637163976937298712401923044942903643110818927352830519968 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.30742445205885625517637163976937298712401923044942903643110818927352830519968
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.94261125006198334714919928581322008179434518021362837208571967467889195724864
Short name T592
Test name
Test status
Simulation time 988289480 ps
CPU time 17.17 seconds
Started Nov 22 02:16:18 PM PST 23
Finished Nov 22 02:16:35 PM PST 23
Peak memory 245660 kb
Host smart-fa63c78c-72b8-4558-9617-e34be6607b6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94261125006198334714919928581322008179434518021362837208571967467889195724864 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.94261125006198334714919928581322008179434518021362837208571967467889195724864
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.47044178176370285875022113477906748836019063274715862115242036959400066512873
Short name T29
Test name
Test status
Simulation time 624328106 ps
CPU time 2057.49 seconds
Started Nov 22 02:16:32 PM PST 23
Finished Nov 22 02:50:50 PM PST 23
Peak memory 498188 kb
Host smart-f51bbb1e-0755-4702-9c73-4dd63f8e6735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=47044178176370285875022113477906748836019063274715862115242036959400066512873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sr
am_ctrl_stress_all_with_rand_reset.47044178176370285875022113477906748836019063274715862115242036959400066512873
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.84719006454999921081753048856301739903396775876462484569633047679864014240736
Short name T708
Test name
Test status
Simulation time 9325508496 ps
CPU time 436.95 seconds
Started Nov 22 02:15:47 PM PST 23
Finished Nov 22 02:23:04 PM PST 23
Peak memory 202824 kb
Host smart-38998eb2-e51a-449f-be07-5d2e1b5ccfee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84719006454999921081753048856301739903396775876462484569633047679864014240736
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.847190064549999210817530488563017399033967758764624
84569633047679864014240736
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.55672454685500271081098256860801444396039491953514338040830518729305503476966
Short name T262
Test name
Test status
Simulation time 1371125703 ps
CPU time 108.84 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:18:26 PM PST 23
Peak memory 351288 kb
Host smart-ad44c614-b6d6-4268-b578-b147f373fe92
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556724546855002710810982568608014443960394919535143380
40830518729305503476966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.5567245468550027108109
8256860801444396039491953514338040830518729305503476966
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.53276804272455960131596773357186180467866883197140343377423496132752830330701
Short name T728
Test name
Test status
Simulation time 13467153934 ps
CPU time 1111.06 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:25:52 PM PST 23
Peak memory 378756 kb
Host smart-f89307b5-f963-40f8-a914-502d6b44e81f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53276804272455960131596773357186180467866883197140343377423496132752830330701
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_key_req.5327680427245596013159677335718618046786
6883197140343377423496132752830330701
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.17567089085791457701283252175618353479915605661995422175673613501514155737795
Short name T326
Test name
Test status
Simulation time 16600825 ps
CPU time 0.66 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:07:38 PM PST 23
Peak memory 202700 kb
Host smart-e5d9ce12-6917-4e1e-9328-4ceb4634cd75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175670890857914577012832521756183534799156056619954221756736135015
14155737795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.1756708908579145770128325217561835347991560566199542217
5673613501514155737795
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.81493687150881062315197486123772082202435413509324700149127004368114148721826
Short name T319
Test name
Test status
Simulation time 295482808505 ps
CPU time 2764.88 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:53:26 PM PST 23
Peak memory 202852 kb
Host smart-fc204b81-131f-436c-8141-6ebfe9901f76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81493687150881062315197486123772082202435413509324700149127004368114148721826 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.81493687150881062315197486123772082202435413509324700149127004368114148721826
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.91231296166581456973120500402960554362365301669725968516301878006635898182062
Short name T636
Test name
Test status
Simulation time 31712811539 ps
CPU time 779.71 seconds
Started Nov 22 02:07:22 PM PST 23
Finished Nov 22 02:20:22 PM PST 23
Peak memory 368032 kb
Host smart-7e09860c-8b15-48e0-bf59-bd5aca4fe4ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91231296166581456973120500402960554362365301669725968516301878006635898182062 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.91231296166581456973120500402960554362365301669725968516301878006635898182062
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.85879920270239234296237992465392637311792927516480550187132522145257591206581
Short name T406
Test name
Test status
Simulation time 19084394710 ps
CPU time 102.29 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:09:02 PM PST 23
Peak memory 211044 kb
Host smart-f05fe1a0-b2c9-42c3-81d3-0524154c185e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85879920270239234296237992465392637311792927516480550187132522145257591206581 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.85879920270239234296237992465392637311792927516480550187132522145257591206581
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.33417121669638035989610098003270704078733397101518369626099125120892188946970
Short name T410
Test name
Test status
Simulation time 1342947357 ps
CPU time 112.69 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:09:15 PM PST 23
Peak memory 351184 kb
Host smart-097b30ab-247e-4a94-8207-b336ad6174d0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341712166963803598961009800327070407873339710151836962
6099125120892188946970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max_throughput.334171216696380359896100980032707040
78733397101518369626099125120892188946970
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.29918625018118436882535956124933733737891396940139441782534773977732346271344
Short name T486
Test name
Test status
Simulation time 4750777237 ps
CPU time 79.72 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:08:41 PM PST 23
Peak memory 212332 kb
Host smart-41b06144-fca0-49d0-99d7-99732b0d010f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29918625018118436882535956124933733737891396940139441782534773977732
346271344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.2991862501811843688253595612493373373789139694013
9441782534773977732346271344
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.86559821670723081194281807155427630786073954644061637225324375654696814914974
Short name T549
Test name
Test status
Simulation time 18445453393 ps
CPU time 155.7 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:09:57 PM PST 23
Peak memory 202784 kb
Host smart-27f65db2-7898-4ff4-9e54-81882263aad8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86559821670723081194281807155427630786073954644061637225324375654696814914974
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.86559821670723081194281807155427630786073954644061637225324375654696814914974
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.103787441265129693181933545611904629022010010324664441538671940904208013731392
Short name T605
Test name
Test status
Simulation time 28731174678 ps
CPU time 977.12 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:23:37 PM PST 23
Peak memory 378784 kb
Host smart-92fd301e-e3c3-4faf-a354-3d444268c4c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103787441265129693181933545611904629022010010324664441538671940904208013731392 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.103787441265129693181933545611904629022010010324664441538671940904208013731392
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.25531637686081075642291501355951970986988056103206612673842244790880558727232
Short name T686
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.28 seconds
Started Nov 22 02:07:20 PM PST 23
Finished Nov 22 02:07:41 PM PST 23
Peak memory 245636 kb
Host smart-2d89bc69-c05b-4248-a6eb-0132c8a37644
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255316376860810756422915013559519709869880561032066126738422447908805
58727232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.2553163768608107564229150135595197098698805610320661267
3842244790880558727232
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.73338947530284451646132270999938009753354384537854434305400727515757753196099
Short name T439
Test name
Test status
Simulation time 45083829570 ps
CPU time 563.02 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:16:45 PM PST 23
Peak memory 202920 kb
Host smart-0c86212d-456e-4eef-9e3a-e0064bb059fe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733389475302844516461322709999380097533543845378544343054007275157577
53196099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access_b2b.73338947530284451646132270999938009753354
384537854434305400727515757753196099
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.23544183102529801035311026988898207791938329870035770129049304437683965416387
Short name T340
Test name
Test status
Simulation time 607542526 ps
CPU time 6.28 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:07:29 PM PST 23
Peak memory 203088 kb
Host smart-2b1ef237-e067-4ebf-8cf2-7c1a052f1f19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23544183102529801035311026988898207791938329870035770129049304437683965416387 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.23544183102529801035311026988898207791938329870035770129049304437683965416387
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.85052753629445687767015557897398219625568939811271210667177656422214538750627
Short name T722
Test name
Test status
Simulation time 19913691647 ps
CPU time 530.89 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:16:13 PM PST 23
Peak memory 372492 kb
Host smart-222c4617-5c18-4dc5-b0b9-c14edbee2a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85052753629445687767015557897398219625568939811271210667177656422214538750627 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.85052753629445687767015557897398219625568939811271210667177656422214538750627
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.94862616190992729263057295706826492395745614968360716304602738992705684462267
Short name T24
Test name
Test status
Simulation time 216402798 ps
CPU time 1.91 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:07:40 PM PST 23
Peak memory 221076 kb
Host smart-b0cc2673-ffae-4c10-b317-fbe97f4d1e64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9486261619099272926305729570682649239574561496836071630460273899270
5684462267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.948626161909927292630572957068264923957456149683607163046027
38992705684462267
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.70167178323678993264300057179126396012806735295723911889731673079760023308258
Short name T882
Test name
Test status
Simulation time 988289480 ps
CPU time 18.25 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:07:38 PM PST 23
Peak memory 245544 kb
Host smart-13f45fa7-cfda-4d9d-997b-9fc84a486a59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70167178323678993264300057179126396012806735295723911889731673079760023308258 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.70167178323678993264300057179126396012806735295723911889731673079760023308258
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.43320943159546433670105093199957010620578722692140357934667982145912590333332
Short name T371
Test name
Test status
Simulation time 624328106 ps
CPU time 1882.05 seconds
Started Nov 22 02:07:21 PM PST 23
Finished Nov 22 02:38:45 PM PST 23
Peak memory 498160 kb
Host smart-16319089-43f4-4f35-aebc-7c3a8decff70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=43320943159546433670105093199957010620578722692140357934667982145912590333332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sra
m_ctrl_stress_all_with_rand_reset.43320943159546433670105093199957010620578722692140357934667982145912590333332
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.45783218660530032571917965237479938475955886911087427097371182437614847547922
Short name T260
Test name
Test status
Simulation time 9325508496 ps
CPU time 433.71 seconds
Started Nov 22 02:07:19 PM PST 23
Finished Nov 22 02:14:34 PM PST 23
Peak memory 202864 kb
Host smart-33a9b9ee-60bf-4dfc-8813-fa2faf157917
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45783218660530032571917965237479938475955886911087427097371182437614847547922
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.4578321866053003257191796523747993847595588691108742
7097371182437614847547922
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.77060691526591415744016096133051562746257959009826663340760492877953539715221
Short name T494
Test name
Test status
Simulation time 1371125703 ps
CPU time 113.74 seconds
Started Nov 22 02:07:22 PM PST 23
Finished Nov 22 02:09:16 PM PST 23
Peak memory 351188 kb
Host smart-40cadeaf-d789-405a-8a34-adf00b0d25d1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770606915265914157440160961330515627462579590098266633
40760492877953539715221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.77060691526591415744016
096133051562746257959009826663340760492877953539715221
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.107201670992146482473667604447335184950176483344613467371784522811649488138025
Short name T293
Test name
Test status
Simulation time 13467153934 ps
CPU time 938.15 seconds
Started Nov 22 02:16:14 PM PST 23
Finished Nov 22 02:31:53 PM PST 23
Peak memory 378748 kb
Host smart-84a5b0a1-3df5-4cb2-bc7b-7bc0d5342153
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10720167099214648247366760444733518495017648334461346737178452281164948813802
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during_key_req.10720167099214648247366760444733518495
0176483344613467371784522811649488138025
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.61636101433488135313113484038512219639931351743227083105606283856221370119931
Short name T620
Test name
Test status
Simulation time 16600825 ps
CPU time 0.69 seconds
Started Nov 22 02:16:14 PM PST 23
Finished Nov 22 02:16:16 PM PST 23
Peak memory 202564 kb
Host smart-26554cb1-02fb-4bc5-816d-959aedf560cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616361014334881353131134840385122196399313517432270831056062838562
21370119931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.616361014334881353131134840385122196399313517432270831
05606283856221370119931
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.81108153299753179696564026456400937391596269862294071083266482765719565572197
Short name T389
Test name
Test status
Simulation time 295482808505 ps
CPU time 2715.51 seconds
Started Nov 22 02:16:31 PM PST 23
Finished Nov 22 03:01:48 PM PST 23
Peak memory 202880 kb
Host smart-f07133b9-8abe-421f-8f5d-a3cd3d7929fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81108153299753179696564026456400937391596269862294071083266482765719565572197 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.81108153299753179696564026456400937391596269862294071083266482765719565572197
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.20834879841020864713704555881652947334000795972107671918433113178548282858823
Short name T243
Test name
Test status
Simulation time 31712811539 ps
CPU time 695.67 seconds
Started Nov 22 02:16:28 PM PST 23
Finished Nov 22 02:28:05 PM PST 23
Peak memory 368144 kb
Host smart-9c63b966-1f43-4400-84ff-56b150500251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20834879841020864713704555881652947334000795972107671918433113178548282858823 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.20834879841020864713704555881652947334000795972107671918433113178548282858823
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.11148056542127265053661292916756651358526812686661409996596598200949057092081
Short name T797
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.65 seconds
Started Nov 22 02:16:16 PM PST 23
Finished Nov 22 02:18:01 PM PST 23
Peak memory 211044 kb
Host smart-99c7695d-a268-4eb8-9ffc-c96003f58626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11148056542127265053661292916756651358526812686661409996596598200949057092081 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.11148056542127265053661292916756651358526812686661409996596598200949057092081
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.1391789905303654615558701302244845933707226877432167007960379021537863762831
Short name T677
Test name
Test status
Simulation time 1342947357 ps
CPU time 101.94 seconds
Started Nov 22 02:16:10 PM PST 23
Finished Nov 22 02:17:53 PM PST 23
Peak memory 351096 kb
Host smart-b49b9169-8085-4f08-abab-f0899e3da397
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391789905303654615558701302244845933707226877432167007
960379021537863762831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_max_throughput.139178990530365461555870130224484593
3707226877432167007960379021537863762831
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.48437189816544566373340210398352915614997231282704164173442983400460606422663
Short name T384
Test name
Test status
Simulation time 4750777237 ps
CPU time 79.92 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:17:56 PM PST 23
Peak memory 212280 kb
Host smart-5d6cf744-113d-444c-bec5-b0ba8f0cace9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48437189816544566373340210398352915614997231282704164173442983400460
606422663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.484371898165445663733402103983529156149972312827
04164173442983400460606422663
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.13724513492180425006469210074286003374175706832904607416022493430280825678651
Short name T396
Test name
Test status
Simulation time 18445453393 ps
CPU time 160.13 seconds
Started Nov 22 02:16:19 PM PST 23
Finished Nov 22 02:19:00 PM PST 23
Peak memory 202752 kb
Host smart-78d6ae21-9c59-4f08-b0db-76cc8baaa417
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13724513492180425006469210074286003374175706832904607416022493430280825678651
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.13724513492180425006469210074286003374175706832904607416022493430280825678651
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.52554916513604576865022613543792651613663550473655947591745842569294463299933
Short name T785
Test name
Test status
Simulation time 28731174678 ps
CPU time 786.95 seconds
Started Nov 22 02:16:29 PM PST 23
Finished Nov 22 02:29:36 PM PST 23
Peak memory 378640 kb
Host smart-77387d68-89d3-4d40-b2a4-505bbc565ed8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52554916513604576865022613543792651613663550473655947591745842569294463299933 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.52554916513604576865022613543792651613663550473655947591745842569294463299933
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.27148801290965838874803931818627324611960760488671217615471711273445965637530
Short name T711
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.6 seconds
Started Nov 22 02:16:01 PM PST 23
Finished Nov 22 02:16:20 PM PST 23
Peak memory 245584 kb
Host smart-1a66d071-0fa9-4436-b649-7ebde086cb3b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271488012909658388748039318186273246119607604886712176154717112734459
65637530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.271488012909658388748039318186273246119607604886712176
15471711273445965637530
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.46367048847650477155887575591136320492647244408526273689233148848320445695698
Short name T821
Test name
Test status
Simulation time 45083829570 ps
CPU time 585.32 seconds
Started Nov 22 02:16:31 PM PST 23
Finished Nov 22 02:26:17 PM PST 23
Peak memory 202936 kb
Host smart-2b6e2aab-265c-414e-9889-a1e180f46da4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463670488476504771558875755911363204926472444085262736892331488483204
45695698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access_b2b.4636704884765047715588757559113632049264
7244408526273689233148848320445695698
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.76689190498658819692025059610073734264295842670954446719792118342926033341610
Short name T230
Test name
Test status
Simulation time 607542526 ps
CPU time 6.18 seconds
Started Nov 22 02:16:30 PM PST 23
Finished Nov 22 02:16:37 PM PST 23
Peak memory 203128 kb
Host smart-6d66171e-14cd-4157-bd60-7a8422398cb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76689190498658819692025059610073734264295842670954446719792118342926033341610 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.76689190498658819692025059610073734264295842670954446719792118342926033341610
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.33671592663780506484187779661683428052119130143215088926596109679151155631807
Short name T531
Test name
Test status
Simulation time 19913691647 ps
CPU time 524.5 seconds
Started Nov 22 02:16:17 PM PST 23
Finished Nov 22 02:25:02 PM PST 23
Peak memory 372480 kb
Host smart-6a044c00-37ae-4799-9670-491bfeba65db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33671592663780506484187779661683428052119130143215088926596109679151155631807 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.33671592663780506484187779661683428052119130143215088926596109679151155631807
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.43698978876317467424344775476383738792538643679796437664203448387100835683179
Short name T342
Test name
Test status
Simulation time 988289480 ps
CPU time 18.82 seconds
Started Nov 22 02:16:12 PM PST 23
Finished Nov 22 02:16:31 PM PST 23
Peak memory 245648 kb
Host smart-f384fa67-2445-4396-8aea-b040974c5440
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43698978876317467424344775476383738792538643679796437664203448387100835683179 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.43698978876317467424344775476383738792538643679796437664203448387100835683179
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.20787457245158070061187041479544195945603802595047817619859837811704823658869
Short name T385
Test name
Test status
Simulation time 624328106 ps
CPU time 1745.24 seconds
Started Nov 22 02:16:28 PM PST 23
Finished Nov 22 02:45:35 PM PST 23
Peak memory 498196 kb
Host smart-10a276e1-9b0c-4c35-a321-5909a9d3e738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=20787457245158070061187041479544195945603802595047817619859837811704823658869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sr
am_ctrl_stress_all_with_rand_reset.20787457245158070061187041479544195945603802595047817619859837811704823658869
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.90981264123470559164011072456608307314117931913063698010278467525939192418980
Short name T842
Test name
Test status
Simulation time 9325508496 ps
CPU time 431.21 seconds
Started Nov 22 02:16:16 PM PST 23
Finished Nov 22 02:23:28 PM PST 23
Peak memory 202892 kb
Host smart-0564fdbc-1ff3-4a5d-96d1-d6dc856e4f35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90981264123470559164011072456608307314117931913063698010278467525939192418980
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.909812641234705591640110724566083073141179319130636
98010278467525939192418980
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.89375234650950147384113434632117571164702383324817190552060838041804308765081
Short name T948
Test name
Test status
Simulation time 1371125703 ps
CPU time 98.86 seconds
Started Nov 22 02:16:17 PM PST 23
Finished Nov 22 02:17:56 PM PST 23
Peak memory 351152 kb
Host smart-3adfab01-80ae-429c-a983-a686767b9fbb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893752346509501473841134346321175711647023833248171905
52060838041804308765081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.8937523465095014738411
3434632117571164702383324817190552060838041804308765081
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.81813567286114882489926477698917233205423423409735740926145129581817848310767
Short name T436
Test name
Test status
Simulation time 13467153934 ps
CPU time 893.61 seconds
Started Nov 22 02:16:30 PM PST 23
Finished Nov 22 02:31:24 PM PST 23
Peak memory 378772 kb
Host smart-006a9ae6-0a91-4485-a862-fe7ec4864eac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81813567286114882489926477698917233205423423409735740926145129581817848310767
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during_key_req.818135672861148824899264776989172332054
23423409735740926145129581817848310767
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.74661918891317525212334162876016954846047189935705520235960487574766296359582
Short name T752
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:16:39 PM PST 23
Finished Nov 22 02:16:40 PM PST 23
Peak memory 202548 kb
Host smart-42b1ed2d-f805-4c87-82ce-27dc3316f50c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746619188913175252123341628760169548460471899357055202359604875747
66296359582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.746619188913175252123341628760169548460471899357055202
35960487574766296359582
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.103123802111579255018085555572488500996053592934193285259871826750007756439185
Short name T743
Test name
Test status
Simulation time 295482808505 ps
CPU time 2751.84 seconds
Started Nov 22 02:16:39 PM PST 23
Finished Nov 22 03:02:32 PM PST 23
Peak memory 202828 kb
Host smart-d1126264-b8a3-4107-9eaf-2efad7028b00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103123802111579255018085555572488500996053592934193285259871826750007756439185 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.103123802111579255018085555572488500996053592934193285259871826750007756439185
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.9207852291945114986506082862439692220643467444837742436176791899823091349533
Short name T923
Test name
Test status
Simulation time 31712811539 ps
CPU time 824.02 seconds
Started Nov 22 02:16:29 PM PST 23
Finished Nov 22 02:30:13 PM PST 23
Peak memory 368040 kb
Host smart-4c1eb5a8-fcbc-4bda-b215-de87cd1ad1c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9207852291945114986506082862439692220643467444837742436176791899823091349533 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.9207852291945114986506082862439692220643467444837742436176791899823091349533
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.78579896755877094086952294071991157473671985203145277584862155886541026080093
Short name T606
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.68 seconds
Started Nov 22 02:16:41 PM PST 23
Finished Nov 22 02:18:26 PM PST 23
Peak memory 211012 kb
Host smart-6b0a5503-4498-4baf-9f33-3a5376ea7017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78579896755877094086952294071991157473671985203145277584862155886541026080093 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.78579896755877094086952294071991157473671985203145277584862155886541026080093
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.115236525092740361979088392488218156599720202435683570905982193951658598250016
Short name T895
Test name
Test status
Simulation time 1342947357 ps
CPU time 117.61 seconds
Started Nov 22 02:16:50 PM PST 23
Finished Nov 22 02:18:48 PM PST 23
Peak memory 351184 kb
Host smart-afc6e4d8-dd04-472c-a54d-440de0e8f664
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152365250927403619790883924882181565997202024356835709
05982193951658598250016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_max_throughput.1152365250927403619790883924882181
56599720202435683570905982193951658598250016
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.25732866058195862692473390119177763595835934093235118213634009885663687052248
Short name T464
Test name
Test status
Simulation time 4750777237 ps
CPU time 75.39 seconds
Started Nov 22 02:16:31 PM PST 23
Finished Nov 22 02:17:47 PM PST 23
Peak memory 212240 kb
Host smart-a0c842fb-a268-43e9-94ac-e5ea20a8b0f3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25732866058195862692473390119177763595835934093235118213634009885663
687052248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.257328660581958626924733901191777635958359340932
35118213634009885663687052248
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.33557788446502920470996585444194899035678574748786547592716882803061781666281
Short name T917
Test name
Test status
Simulation time 18445453393 ps
CPU time 154.52 seconds
Started Nov 22 02:16:40 PM PST 23
Finished Nov 22 02:19:15 PM PST 23
Peak memory 202836 kb
Host smart-6772cf0d-adcb-46ed-9505-50b97970fb11
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33557788446502920470996585444194899035678574748786547592716882803061781666281
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.33557788446502920470996585444194899035678574748786547592716882803061781666281
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.32122242900849580456427354527195404919152151570957329457098675972801631791866
Short name T234
Test name
Test status
Simulation time 28731174678 ps
CPU time 722.53 seconds
Started Nov 22 02:16:29 PM PST 23
Finished Nov 22 02:28:32 PM PST 23
Peak memory 378684 kb
Host smart-fb0e8d7f-227e-4a73-b8b7-ac14fb79cc5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32122242900849580456427354527195404919152151570957329457098675972801631791866 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.32122242900849580456427354527195404919152151570957329457098675972801631791866
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.59716614613485936166952464457906400211785858228314758102861286149652012715452
Short name T913
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.98 seconds
Started Nov 22 02:16:39 PM PST 23
Finished Nov 22 02:16:58 PM PST 23
Peak memory 245732 kb
Host smart-233ca891-beb9-413c-9314-f67393948776
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597166146134859361669524644579064002117858582283147581028612861496520
12715452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.597166146134859361669524644579064002117858582283147581
02861286149652012715452
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.90944555222722784184390002244702682658988105576254809183323325468716580255641
Short name T735
Test name
Test status
Simulation time 45083829570 ps
CPU time 571.37 seconds
Started Nov 22 02:16:32 PM PST 23
Finished Nov 22 02:26:04 PM PST 23
Peak memory 202868 kb
Host smart-71f8207d-1815-4212-a4f0-a7f6b3c31702
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909445552227227841843900022447026826589881055762548091833233254687165
80255641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access_b2b.9094455522272278418439000224470268265898
8105576254809183323325468716580255641
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.50033937734227916439050514969389958742160617180796022890233361715859292124566
Short name T783
Test name
Test status
Simulation time 607542526 ps
CPU time 6.09 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:16:41 PM PST 23
Peak memory 203124 kb
Host smart-f70709ea-d551-4b30-8f22-c6aaf162fa0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50033937734227916439050514969389958742160617180796022890233361715859292124566 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.50033937734227916439050514969389958742160617180796022890233361715859292124566
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.5489070818668393457906265752680159512661812127531365002948269425257982288955
Short name T784
Test name
Test status
Simulation time 19913691647 ps
CPU time 505.6 seconds
Started Nov 22 02:16:31 PM PST 23
Finished Nov 22 02:24:57 PM PST 23
Peak memory 372580 kb
Host smart-f4a2ccc8-91dc-40a9-a158-6c0171919ab9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5489070818668393457906265752680159512661812127531365002948269425257982288955 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.5489070818668393457906265752680159512661812127531365002948269425257982288955
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.13946639589127913900452834002414677958282991052313625588463639708247695469713
Short name T121
Test name
Test status
Simulation time 988289480 ps
CPU time 15.61 seconds
Started Nov 22 02:16:29 PM PST 23
Finished Nov 22 02:16:46 PM PST 23
Peak memory 245624 kb
Host smart-014d495d-2693-4370-b2b4-8e41a902743d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13946639589127913900452834002414677958282991052313625588463639708247695469713 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.13946639589127913900452834002414677958282991052313625588463639708247695469713
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.52550108142396070677858716695431826313322645886976701424453715590924320135560
Short name T388
Test name
Test status
Simulation time 624328106 ps
CPU time 1943.1 seconds
Started Nov 22 02:16:29 PM PST 23
Finished Nov 22 02:48:53 PM PST 23
Peak memory 498264 kb
Host smart-c29e6179-9fa4-412f-b68a-84bb57944455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=52550108142396070677858716695431826313322645886976701424453715590924320135560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sr
am_ctrl_stress_all_with_rand_reset.52550108142396070677858716695431826313322645886976701424453715590924320135560
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.28730897555928499362853426347202410038105083220374336307039974026964826754549
Short name T724
Test name
Test status
Simulation time 9325508496 ps
CPU time 422.74 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:23:38 PM PST 23
Peak memory 202864 kb
Host smart-ee4dad1c-04f8-4400-bdd1-eeea0884ebbe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28730897555928499362853426347202410038105083220374336307039974026964826754549
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.287308975559284993628534263472024100381050832203743
36307039974026964826754549
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.69913545251791849862830654501886831135963317677415935824136715302852960862108
Short name T737
Test name
Test status
Simulation time 1371125703 ps
CPU time 141.41 seconds
Started Nov 22 02:16:40 PM PST 23
Finished Nov 22 02:19:02 PM PST 23
Peak memory 351116 kb
Host smart-c0a2c972-a885-4be8-86ee-d87d8e0817dd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699135452517918498628306545018868311359633176774159358
24136715302852960862108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.6991354525179184986283
0654501886831135963317677415935824136715302852960862108
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.10357539733983662590471830319031583037332584577758030130387331362622119072025
Short name T898
Test name
Test status
Simulation time 13467153934 ps
CPU time 888.09 seconds
Started Nov 22 02:16:30 PM PST 23
Finished Nov 22 02:31:19 PM PST 23
Peak memory 378616 kb
Host smart-087e6631-4612-4742-ae8a-d74f5afa2d35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10357539733983662590471830319031583037332584577758030130387331362622119072025
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during_key_req.103575397339836625904718303190315830373
32584577758030130387331362622119072025
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.48147010184622431322357868887134670754244819785718647322925651538795459535933
Short name T687
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:16:32 PM PST 23
Finished Nov 22 02:16:33 PM PST 23
Peak memory 202572 kb
Host smart-56b0917a-1eaf-43df-a6da-49b7aeaaefe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481470101846224313223578688871346707542448197857186473229256515387
95459535933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.481470101846224313223578688871346707542448197857186473
22925651538795459535933
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.26554778980327317510376231654076838504831068937244878634244259824810579825344
Short name T305
Test name
Test status
Simulation time 295482808505 ps
CPU time 2707.48 seconds
Started Nov 22 02:16:40 PM PST 23
Finished Nov 22 03:01:48 PM PST 23
Peak memory 202812 kb
Host smart-81487c72-2fd8-4f67-9e2b-d979ee821041
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26554778980327317510376231654076838504831068937244878634244259824810579825344 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.26554778980327317510376231654076838504831068937244878634244259824810579825344
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.98527383043194447457253207251360695343688393240048080022996785513721515537416
Short name T956
Test name
Test status
Simulation time 31712811539 ps
CPU time 800.9 seconds
Started Nov 22 02:16:39 PM PST 23
Finished Nov 22 02:30:00 PM PST 23
Peak memory 367980 kb
Host smart-1fad5934-b62b-4943-8df7-10de3dba1cf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98527383043194447457253207251360695343688393240048080022996785513721515537416 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.98527383043194447457253207251360695343688393240048080022996785513721515537416
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.42938404189725941993755645437285453429847474520951528199593496133174577262496
Short name T373
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.84 seconds
Started Nov 22 02:16:27 PM PST 23
Finished Nov 22 02:18:13 PM PST 23
Peak memory 211072 kb
Host smart-7b395801-c72a-49df-a1b4-156d729cc5e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42938404189725941993755645437285453429847474520951528199593496133174577262496 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.42938404189725941993755645437285453429847474520951528199593496133174577262496
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.66150211890001667082202689680778824692154911244116097916977993845686128598803
Short name T969
Test name
Test status
Simulation time 1342947357 ps
CPU time 138.51 seconds
Started Nov 22 02:16:27 PM PST 23
Finished Nov 22 02:18:46 PM PST 23
Peak memory 351176 kb
Host smart-fa96c10b-920f-4961-bc3d-07cae3ded09a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6615021189000166708220268968077882469215491124411609791
6977993845686128598803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_max_throughput.66150211890001667082202689680778824
692154911244116097916977993845686128598803
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.52412802430688189175713955931554012624415696188234865168914811301780543173446
Short name T733
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.42 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:17:54 PM PST 23
Peak memory 212028 kb
Host smart-db83c51a-32cf-4292-97fe-de8223af66af
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52412802430688189175713955931554012624415696188234865168914811301780
543173446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.524128024306881891757139559315540126244156961882
34865168914811301780543173446
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.37837651801430289550191506322963282088238884893261492805358112331738844654668
Short name T679
Test name
Test status
Simulation time 18445453393 ps
CPU time 155.5 seconds
Started Nov 22 02:16:37 PM PST 23
Finished Nov 22 02:19:14 PM PST 23
Peak memory 202804 kb
Host smart-1ed9ccb5-6462-4236-b557-e379c4a5a61f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37837651801430289550191506322963282088238884893261492805358112331738844654668
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.37837651801430289550191506322963282088238884893261492805358112331738844654668
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.23309389073774053300987657847071660297473896051058607948442378967399969863687
Short name T953
Test name
Test status
Simulation time 28731174678 ps
CPU time 652.43 seconds
Started Nov 22 02:16:32 PM PST 23
Finished Nov 22 02:27:25 PM PST 23
Peak memory 378652 kb
Host smart-643a3727-1dc0-4024-a412-4734131bc50c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23309389073774053300987657847071660297473896051058607948442378967399969863687 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.23309389073774053300987657847071660297473896051058607948442378967399969863687
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.38700000725089547732228726924581501624056841887228594812372592300899275568205
Short name T560
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.45 seconds
Started Nov 22 02:16:16 PM PST 23
Finished Nov 22 02:16:34 PM PST 23
Peak memory 245644 kb
Host smart-4695d758-7b6e-49c5-b870-f317f07d61ec
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387000007250895477322287269245815016240568418872285948123725923008992
75568205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.387000007250895477322287269245815016240568418872285948
12372592300899275568205
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.12009702370980687489173292276593207000183184115557048912629876173600869836784
Short name T427
Test name
Test status
Simulation time 45083829570 ps
CPU time 576.1 seconds
Started Nov 22 02:16:28 PM PST 23
Finished Nov 22 02:26:05 PM PST 23
Peak memory 202912 kb
Host smart-4b840c7d-1590-45a0-bdca-3a301b94644c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120097023709806874891732922765932070001831841155570489126298761736008
69836784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access_b2b.1200970237098068748917329227659320700018
3184115557048912629876173600869836784
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.19387482073610279008477401016235139746083860753517595769098411107588309063527
Short name T479
Test name
Test status
Simulation time 607542526 ps
CPU time 5.97 seconds
Started Nov 22 02:16:39 PM PST 23
Finished Nov 22 02:16:45 PM PST 23
Peak memory 203072 kb
Host smart-0f2a2c7f-68ac-45a1-ab15-b645e27d7598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19387482073610279008477401016235139746083860753517595769098411107588309063527 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.19387482073610279008477401016235139746083860753517595769098411107588309063527
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.137730516076642370989709231641699550276875186435603475818428795252839687746
Short name T868
Test name
Test status
Simulation time 19913691647 ps
CPU time 595.28 seconds
Started Nov 22 02:16:18 PM PST 23
Finished Nov 22 02:26:13 PM PST 23
Peak memory 372456 kb
Host smart-8a80bae1-dcb5-4d86-a87a-db13f3f82d1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137730516076642370989709231641699550276875186435603475818428795252839687746 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.137730516076642370989709231641699550276875186435603475818428795252839687746
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.93935149631149575777560804004870117365124250252141642798027529481334177391558
Short name T879
Test name
Test status
Simulation time 988289480 ps
CPU time 18.8 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:16:56 PM PST 23
Peak memory 245644 kb
Host smart-f8a61f6d-9c6f-4a16-aa03-702bab2f459f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93935149631149575777560804004870117365124250252141642798027529481334177391558 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.93935149631149575777560804004870117365124250252141642798027529481334177391558
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.111589572823822414375847944635928814080721615319557463735099939497582709168919
Short name T481
Test name
Test status
Simulation time 624328106 ps
CPU time 2106.19 seconds
Started Nov 22 02:16:18 PM PST 23
Finished Nov 22 02:51:25 PM PST 23
Peak memory 498192 kb
Host smart-ad6bb3f7-a683-47c4-b7af-3965be398811
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=111589572823822414375847944635928814080721615319557463735099939497582709168919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s
ram_ctrl_stress_all_with_rand_reset.111589572823822414375847944635928814080721615319557463735099939497582709168919
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.13921134411191487329787517974406047123365909027816343310569751039706637663326
Short name T236
Test name
Test status
Simulation time 9325508496 ps
CPU time 426.28 seconds
Started Nov 22 02:16:28 PM PST 23
Finished Nov 22 02:23:35 PM PST 23
Peak memory 202912 kb
Host smart-bb6a5290-5b0c-4e0c-bbff-b1d04ee1f4e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13921134411191487329787517974406047123365909027816343310569751039706637663326
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.139211344111914873297875179744060471233659090278163
43310569751039706637663326
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.100448248408629527269210811065442291462832915861908290159529317469710873771231
Short name T666
Test name
Test status
Simulation time 1371125703 ps
CPU time 131.97 seconds
Started Nov 22 02:16:34 PM PST 23
Finished Nov 22 02:18:46 PM PST 23
Peak memory 351176 kb
Host smart-0df82292-353d-4da1-a8d3-880b04a67c39
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100448248408629527269210811065442291462832915861908290
159529317469710873771231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.100448248408629527269
210811065442291462832915861908290159529317469710873771231
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.69354047678141778331902502834216526978046309372010089758735065426373319907733
Short name T485
Test name
Test status
Simulation time 13467153934 ps
CPU time 1031.75 seconds
Started Nov 22 02:16:18 PM PST 23
Finished Nov 22 02:33:30 PM PST 23
Peak memory 378780 kb
Host smart-48d958b4-26dc-4aa7-81b9-7e241e2a061e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69354047678141778331902502834216526978046309372010089758735065426373319907733
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during_key_req.693540476781417783319025028342165269780
46309372010089758735065426373319907733
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.11677680995045534522873307454067886256657889721969617609217304296809166323783
Short name T419
Test name
Test status
Simulation time 16600825 ps
CPU time 0.67 seconds
Started Nov 22 02:16:33 PM PST 23
Finished Nov 22 02:16:34 PM PST 23
Peak memory 202564 kb
Host smart-e7e27a18-c660-4b7b-9eac-e37f85819253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116776809950455345228733074540678862566578897219696176092173042968
09166323783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.116776809950455345228733074540678862566578897219696176
09217304296809166323783
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.32671346467957841022105067713129227906475949970470872362794108785261087495641
Short name T742
Test name
Test status
Simulation time 295482808505 ps
CPU time 2679.66 seconds
Started Nov 22 02:16:38 PM PST 23
Finished Nov 22 03:01:18 PM PST 23
Peak memory 202820 kb
Host smart-481f1c50-e717-4ab4-aeeb-218c0de1b624
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32671346467957841022105067713129227906475949970470872362794108785261087495641 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.32671346467957841022105067713129227906475949970470872362794108785261087495641
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.90172692597022359026582731206386559224002438225512207214059509126037627385936
Short name T934
Test name
Test status
Simulation time 31712811539 ps
CPU time 798.12 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:29:53 PM PST 23
Peak memory 368016 kb
Host smart-d9a12c1f-545a-4da0-b36f-3b7770f0455e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90172692597022359026582731206386559224002438225512207214059509126037627385936 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.90172692597022359026582731206386559224002438225512207214059509126037627385936
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.111043014605477921377464576042413020723297909952933548906405478589872230626863
Short name T272
Test name
Test status
Simulation time 19084394710 ps
CPU time 102.73 seconds
Started Nov 22 02:16:13 PM PST 23
Finished Nov 22 02:17:56 PM PST 23
Peak memory 211000 kb
Host smart-3a37919d-98eb-45d2-8a22-36a981923f18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111043014605477921377464576042413020723297909952933548906405478589872230626863 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.111043014605477921377464576042413020723297909952933548906405478589872230626863
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.42020294284426308119504911889793537696808098847335852589066536704484710676555
Short name T665
Test name
Test status
Simulation time 1342947357 ps
CPU time 120.22 seconds
Started Nov 22 02:16:16 PM PST 23
Finished Nov 22 02:18:17 PM PST 23
Peak memory 351132 kb
Host smart-9f678553-9445-4919-a964-01ce154ea0de
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202029428442630811950491188979353769680809884733585258
9066536704484710676555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_max_throughput.42020294284426308119504911889793537
696808098847335852589066536704484710676555
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.40029441951695429704949316490693307756025349476479444668324150011205978858512
Short name T583
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.64 seconds
Started Nov 22 02:16:40 PM PST 23
Finished Nov 22 02:18:00 PM PST 23
Peak memory 212384 kb
Host smart-43d7c1c0-495f-49af-aa5d-04e48aa8ff36
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40029441951695429704949316490693307756025349476479444668324150011205
978858512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.400294419516954297049493164906933077560253494764
79444668324150011205978858512
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.13909226387064132200367668789459834270552476160863614668812986645290148322329
Short name T546
Test name
Test status
Simulation time 18445453393 ps
CPU time 159.51 seconds
Started Nov 22 02:16:31 PM PST 23
Finished Nov 22 02:19:11 PM PST 23
Peak memory 202780 kb
Host smart-a32aff28-09c6-4b32-a457-37ec4d018ead
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13909226387064132200367668789459834270552476160863614668812986645290148322329
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.13909226387064132200367668789459834270552476160863614668812986645290148322329
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.55066225346670846363135770793631066721052803903965224245944138751494240317030
Short name T105
Test name
Test status
Simulation time 28731174678 ps
CPU time 785.13 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:29:40 PM PST 23
Peak memory 378612 kb
Host smart-eb77c7d9-cd0e-4e84-903a-f1e61df2be43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55066225346670846363135770793631066721052803903965224245944138751494240317030 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.55066225346670846363135770793631066721052803903965224245944138751494240317030
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.3118250718077209793733441169074779027424959943285676217246303403947254510202
Short name T314
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.32 seconds
Started Nov 22 02:16:18 PM PST 23
Finished Nov 22 02:16:37 PM PST 23
Peak memory 245688 kb
Host smart-3cdb962d-49e6-43a1-b1fb-4cbb8fda2ab8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311825071807720979373344116907477902742495994328567621724630340394725
4510202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.3118250718077209793733441169074779027424959943285676217
246303403947254510202
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.47030040766206898390652754985531755095215694810065439383717092985803395115791
Short name T483
Test name
Test status
Simulation time 45083829570 ps
CPU time 580.26 seconds
Started Nov 22 02:16:16 PM PST 23
Finished Nov 22 02:25:57 PM PST 23
Peak memory 202832 kb
Host smart-dfc1786d-845d-4eb6-aeec-ad54d852350d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470300407662068983906527549855317550952156948100654393837170929858033
95115791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access_b2b.4703004076620689839065275498553175509521
5694810065439383717092985803395115791
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.103066189151984872390176728502471511915040567746949777249714653555568109390553
Short name T650
Test name
Test status
Simulation time 607542526 ps
CPU time 6.26 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:16:42 PM PST 23
Peak memory 203104 kb
Host smart-28ff313b-187e-44e4-90e4-a9a35fb771ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103066189151984872390176728502471511915040567746949777249714653555568109390553 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.103066189151984872390176728502471511915040567746949777249714653555568109390553
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.106547785855157451305923607429301661716403521612485981403791946861733663828933
Short name T584
Test name
Test status
Simulation time 19913691647 ps
CPU time 534.9 seconds
Started Nov 22 02:16:33 PM PST 23
Finished Nov 22 02:25:29 PM PST 23
Peak memory 372544 kb
Host smart-b6fe4dd5-7ae6-4a58-9614-796d81b5e98e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106547785855157451305923607429301661716403521612485981403791946861733663828933 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.106547785855157451305923607429301661716403521612485981403791946861733663828933
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.13302040049934794721027685970819328572359480040380452372558963580493798528481
Short name T881
Test name
Test status
Simulation time 988289480 ps
CPU time 17.08 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:16:53 PM PST 23
Peak memory 245660 kb
Host smart-b3b803fd-8220-4fe2-9799-c142c8837f3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13302040049934794721027685970819328572359480040380452372558963580493798528481 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.13302040049934794721027685970819328572359480040380452372558963580493798528481
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.112147665134793346556775463086493777370039872534181186296953305741118203920336
Short name T625
Test name
Test status
Simulation time 624328106 ps
CPU time 1921.63 seconds
Started Nov 22 02:16:40 PM PST 23
Finished Nov 22 02:48:43 PM PST 23
Peak memory 498252 kb
Host smart-7b456fd2-384e-415e-a5cc-c590d5cd04df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=112147665134793346556775463086493777370039872534181186296953305741118203920336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s
ram_ctrl_stress_all_with_rand_reset.112147665134793346556775463086493777370039872534181186296953305741118203920336
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.32988869547217264149296037700408827475226082724612759851666419516453335898135
Short name T684
Test name
Test status
Simulation time 9325508496 ps
CPU time 422.17 seconds
Started Nov 22 02:16:39 PM PST 23
Finished Nov 22 02:23:42 PM PST 23
Peak memory 202864 kb
Host smart-89ef24cd-913f-40e6-9d85-8084b5b4635e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32988869547217264149296037700408827475226082724612759851666419516453335898135
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.329888695472172641492960377004088274752260827246127
59851666419516453335898135
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.60321064134651552250741169738813711231346782524877088302290996733303667266943
Short name T706
Test name
Test status
Simulation time 1371125703 ps
CPU time 109.8 seconds
Started Nov 22 02:16:39 PM PST 23
Finished Nov 22 02:18:30 PM PST 23
Peak memory 351232 kb
Host smart-85a0c8b4-3c53-41e1-9eeb-5d3f35485512
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603210641346515522507411697388137112313467825248770883
02290996733303667266943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.6032106413465155225074
1169738813711231346782524877088302290996733303667266943
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.107196578770366991636238925440818077513741074208142730388540771229226644205062
Short name T758
Test name
Test status
Simulation time 13467153934 ps
CPU time 1013.87 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:33:31 PM PST 23
Peak memory 378856 kb
Host smart-99d832a0-e973-442c-9e55-362ed84febdb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10719657877036699163623892544081807751374107420814273038854077122922664420506
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during_key_req.10719657877036699163623892544081807751
3741074208142730388540771229226644205062
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.98711589901653226013508476118207529846384481314377257086278905787051956601731
Short name T981
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:16:41 PM PST 23
Finished Nov 22 02:16:42 PM PST 23
Peak memory 202568 kb
Host smart-8057b20b-2673-423b-8f1e-467ecc506191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987115899016532260135084761182075298463844813143772570862789057870
51956601731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.987115899016532260135084761182075298463844813143772570
86278905787051956601731
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.96007243982652836601371269325025900220413773965827005160526220948828816719636
Short name T940
Test name
Test status
Simulation time 295482808505 ps
CPU time 2696.76 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 03:01:33 PM PST 23
Peak memory 202508 kb
Host smart-6e32fb6a-a7ef-43b5-adad-0fe0931f1240
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96007243982652836601371269325025900220413773965827005160526220948828816719636 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.96007243982652836601371269325025900220413773965827005160526220948828816719636
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.4517579085897255043001857427785304814289510075833768435257426840090151058332
Short name T703
Test name
Test status
Simulation time 31712811539 ps
CPU time 907.78 seconds
Started Nov 22 02:16:34 PM PST 23
Finished Nov 22 02:31:43 PM PST 23
Peak memory 368004 kb
Host smart-8f7a4e1a-83f0-4d45-bd46-e65be10d775c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4517579085897255043001857427785304814289510075833768435257426840090151058332 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.4517579085897255043001857427785304814289510075833768435257426840090151058332
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.72392220264116461258506030909398013869573392271264975777628661044586530164451
Short name T793
Test name
Test status
Simulation time 19084394710 ps
CPU time 101.9 seconds
Started Nov 22 02:16:38 PM PST 23
Finished Nov 22 02:18:21 PM PST 23
Peak memory 211028 kb
Host smart-d646f4d2-dc1b-4ce8-8c90-ee4fa2e6d9dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72392220264116461258506030909398013869573392271264975777628661044586530164451 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.72392220264116461258506030909398013869573392271264975777628661044586530164451
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.12315340759943355512664984839500356621025098150738939932871525650973484545539
Short name T327
Test name
Test status
Simulation time 1342947357 ps
CPU time 95.55 seconds
Started Nov 22 02:16:39 PM PST 23
Finished Nov 22 02:18:15 PM PST 23
Peak memory 351228 kb
Host smart-9b1d8b8e-658a-4555-abc1-810050e1524a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231534075994335551266498483950035662102509815073893993
2871525650973484545539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_max_throughput.12315340759943355512664984839500356
621025098150738939932871525650973484545539
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3986536056053191272460467963061897930032325192255645457141799998927660795273
Short name T291
Test name
Test status
Simulation time 4750777237 ps
CPU time 79.14 seconds
Started Nov 22 02:16:44 PM PST 23
Finished Nov 22 02:18:04 PM PST 23
Peak memory 212444 kb
Host smart-26993012-c9ca-4fa5-8fa0-9760e5668bfb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39865360560531912724604679630618979300323251922556454571417999989276
60795273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.3986536056053191272460467963061897930032325192255
645457141799998927660795273
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.58092729646422406524979646571195565119543125356136836407184926249843554552797
Short name T288
Test name
Test status
Simulation time 18445453393 ps
CPU time 155.22 seconds
Started Nov 22 02:16:33 PM PST 23
Finished Nov 22 02:19:08 PM PST 23
Peak memory 202780 kb
Host smart-fd8a231b-a680-419e-b167-f915544eda3c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58092729646422406524979646571195565119543125356136836407184926249843554552797
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.58092729646422406524979646571195565119543125356136836407184926249843554552797
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.48704958079615834002534685589970371121806111759073502282844496069101530674468
Short name T630
Test name
Test status
Simulation time 28731174678 ps
CPU time 708.01 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:28:24 PM PST 23
Peak memory 378608 kb
Host smart-41e8cf1c-32cc-460a-b195-597f58e897cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48704958079615834002534685589970371121806111759073502282844496069101530674468 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.48704958079615834002534685589970371121806111759073502282844496069101530674468
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.112854553273973187734226024846935513008006300514554102474908929244994645274971
Short name T759
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.45 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:16:56 PM PST 23
Peak memory 245700 kb
Host smart-5e61aa92-f1fb-4b2b-b39f-886798d8679e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112854553273973187734226024846935513008006300514554102474908929244994
645274971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.11285455327397318773422602484693551300800630051455410
2474908929244994645274971
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.58070683195160400829391589217265215483910686162472156596691381508730226854262
Short name T834
Test name
Test status
Simulation time 45083829570 ps
CPU time 556.74 seconds
Started Nov 22 02:16:38 PM PST 23
Finished Nov 22 02:25:56 PM PST 23
Peak memory 202832 kb
Host smart-bce0bc64-6a1c-4c05-8d5a-bd14a5c795ed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580706831951604008293915892172652154839106861624721565966913815087302
26854262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access_b2b.5807068319516040082939158921726521548391
0686162472156596691381508730226854262
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.100830790360376088529903978790832541392689458078075258287335173612117600622262
Short name T912
Test name
Test status
Simulation time 607542526 ps
CPU time 5.99 seconds
Started Nov 22 02:16:35 PM PST 23
Finished Nov 22 02:16:41 PM PST 23
Peak memory 203056 kb
Host smart-a049fce5-0f4c-4843-a108-39e46851553d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100830790360376088529903978790832541392689458078075258287335173612117600622262 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.100830790360376088529903978790832541392689458078075258287335173612117600622262
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.28766242378867504035591456851740980803989163576831979194442836504280771110052
Short name T517
Test name
Test status
Simulation time 19913691647 ps
CPU time 539.16 seconds
Started Nov 22 02:16:30 PM PST 23
Finished Nov 22 02:25:30 PM PST 23
Peak memory 372484 kb
Host smart-de5d0b60-ca5d-402c-bff5-bb66bb438025
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28766242378867504035591456851740980803989163576831979194442836504280771110052 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.28766242378867504035591456851740980803989163576831979194442836504280771110052
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.43275286209630884567179477552151673080133975674667090992499407887445394585952
Short name T838
Test name
Test status
Simulation time 988289480 ps
CPU time 18.41 seconds
Started Nov 22 02:16:33 PM PST 23
Finished Nov 22 02:16:52 PM PST 23
Peak memory 245644 kb
Host smart-40ccc3e5-80c3-41bd-8deb-c07a4ec40574
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43275286209630884567179477552151673080133975674667090992499407887445394585952 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.43275286209630884567179477552151673080133975674667090992499407887445394585952
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.76394143259891863188544599407180068362641105178892201617539781165286417766697
Short name T866
Test name
Test status
Simulation time 624328106 ps
CPU time 1667.89 seconds
Started Nov 22 02:16:37 PM PST 23
Finished Nov 22 02:44:25 PM PST 23
Peak memory 498160 kb
Host smart-a9f511ca-4b1a-43be-9ae0-35578224bc08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=76394143259891863188544599407180068362641105178892201617539781165286417766697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sr
am_ctrl_stress_all_with_rand_reset.76394143259891863188544599407180068362641105178892201617539781165286417766697
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.31347206366021660731453737456107027459606764578762180700925590624509028939414
Short name T730
Test name
Test status
Simulation time 9325508496 ps
CPU time 420.03 seconds
Started Nov 22 02:16:40 PM PST 23
Finished Nov 22 02:23:41 PM PST 23
Peak memory 202864 kb
Host smart-6467bd6f-0e39-49f3-9943-d82a435785d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31347206366021660731453737456107027459606764578762180700925590624509028939414
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.313472063660216607314537374561070274596067645787621
80700925590624509028939414
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.57401241000720770747446001600806665883940054648410914673226326176224114005190
Short name T112
Test name
Test status
Simulation time 1371125703 ps
CPU time 136.2 seconds
Started Nov 22 02:16:40 PM PST 23
Finished Nov 22 02:18:57 PM PST 23
Peak memory 351116 kb
Host smart-e00d3e86-7561-4a9d-9de7-9a387bb5a3bc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574012410007207707474460016008066658839400546484109146
73226326176224114005190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.5740124100072077074744
6001600806665883940054648410914673226326176224114005190
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.10166387311563545568446565678934943598689530522108952290518255170624536479509
Short name T42
Test name
Test status
Simulation time 13467153934 ps
CPU time 918.68 seconds
Started Nov 22 02:16:42 PM PST 23
Finished Nov 22 02:32:01 PM PST 23
Peak memory 378760 kb
Host smart-400b7ce2-fc90-47b7-ad19-938b933d604a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10166387311563545568446565678934943598689530522108952290518255170624536479509
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during_key_req.101663873115635455684465656789349435986
89530522108952290518255170624536479509
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.51961321166367206588312203808665332835765747319983165048039364380690170500216
Short name T653
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 02:16:37 PM PST 23
Finished Nov 22 02:16:38 PM PST 23
Peak memory 202608 kb
Host smart-719bc109-dee0-4153-86f9-ae4a1a76f8a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519613211663672065883122038086653328357657473199831650480393643806
90170500216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.519613211663672065883122038086653328357657473199831650
48039364380690170500216
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.1921377752269692838661618528114667518818760175566460363144359772185299323188
Short name T435
Test name
Test status
Simulation time 295482808505 ps
CPU time 2725.94 seconds
Started Nov 22 02:16:40 PM PST 23
Finished Nov 22 03:02:08 PM PST 23
Peak memory 202844 kb
Host smart-19a51328-bf81-479d-8226-b2c30652d5b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921377752269692838661618528114667518818760175566460363144359772185299323188 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.1921377752269692838661618528114667518818760175566460363144359772185299323188
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.106317762880479615883226399605694337070550342522907051405774205667351597689940
Short name T379
Test name
Test status
Simulation time 31712811539 ps
CPU time 805.27 seconds
Started Nov 22 02:16:37 PM PST 23
Finished Nov 22 02:30:03 PM PST 23
Peak memory 368012 kb
Host smart-ab6aa6d7-8720-4c03-b9ac-6da27e4e2a41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106317762880479615883226399605694337070550342522907051405774205667351597689940 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.106317762880479615883226399605694337070550342522907051405774205667351597689940
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.4559139940114826572017761608795074876499918477233135673954866060913813560906
Short name T376
Test name
Test status
Simulation time 19084394710 ps
CPU time 106.73 seconds
Started Nov 22 02:16:37 PM PST 23
Finished Nov 22 02:18:25 PM PST 23
Peak memory 211044 kb
Host smart-141f2f0d-15f9-49d5-b69e-b1aeab141850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4559139940114826572017761608795074876499918477233135673954866060913813560906 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.4559139940114826572017761608795074876499918477233135673954866060913813560906
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.86393279049904485760086648458139612815170816527078749987899057479346080347627
Short name T61
Test name
Test status
Simulation time 1342947357 ps
CPU time 122.85 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:18:39 PM PST 23
Peak memory 351188 kb
Host smart-6c219542-e9e1-4176-acec-6cb05a38ea4c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8639327904990448576008664845813961281517081652707874998
7899057479346080347627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_max_throughput.86393279049904485760086648458139612
815170816527078749987899057479346080347627
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.69095453795686027252599683541337856182713758982764598212630790831412075216069
Short name T75
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.82 seconds
Started Nov 22 02:16:38 PM PST 23
Finished Nov 22 02:17:58 PM PST 23
Peak memory 212256 kb
Host smart-6b7f3cdf-1c0e-49e1-9149-2876a8a8f605
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69095453795686027252599683541337856182713758982764598212630790831412
075216069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.690954537956860272525996835413378561827137589827
64598212630790831412075216069
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.60712173949020285879648534426662503152958863028646769795404168457320327012117
Short name T812
Test name
Test status
Simulation time 18445453393 ps
CPU time 158.47 seconds
Started Nov 22 02:16:44 PM PST 23
Finished Nov 22 02:19:23 PM PST 23
Peak memory 202216 kb
Host smart-ea17d546-6652-44ee-b1a6-f5bc429386ba
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60712173949020285879648534426662503152958863028646769795404168457320327012117
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.60712173949020285879648534426662503152958863028646769795404168457320327012117
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.48046143105038044094534615695898361307841067942130326794125951879835366630524
Short name T12
Test name
Test status
Simulation time 28731174678 ps
CPU time 766.06 seconds
Started Nov 22 02:16:36 PM PST 23
Finished Nov 22 02:29:23 PM PST 23
Peak memory 378552 kb
Host smart-d75de934-d207-4de5-bc69-d0e38be5fb7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48046143105038044094534615695898361307841067942130326794125951879835366630524 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.48046143105038044094534615695898361307841067942130326794125951879835366630524
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.46306390380069756061212966388990231237489052511815211915348629679738345665747
Short name T232
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.86 seconds
Started Nov 22 02:16:43 PM PST 23
Finished Nov 22 02:17:02 PM PST 23
Peak memory 245768 kb
Host smart-ccbb44b5-5ecc-40f9-875d-3f9be32e78be
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463063903800697560612129663889902312374890525118152119153486296797383
45665747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.463063903800697560612129663889902312374890525118152119
15348629679738345665747
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.63153675436842114804874307210651498193549230656077143570357180378131978125982
Short name T394
Test name
Test status
Simulation time 45083829570 ps
CPU time 566.23 seconds
Started Nov 22 02:16:43 PM PST 23
Finished Nov 22 02:26:10 PM PST 23
Peak memory 202960 kb
Host smart-15cbde71-3612-40ec-bc52-384a8409e9a4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631536754368421148048743072106514981935492306560771435703571803781319
78125982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access_b2b.6315367543684211480487430721065149819354
9230656077143570357180378131978125982
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.112672165140608483232100512925327916459788915715284291154197857370497004450048
Short name T338
Test name
Test status
Simulation time 607542526 ps
CPU time 6.17 seconds
Started Nov 22 02:16:43 PM PST 23
Finished Nov 22 02:16:50 PM PST 23
Peak memory 203092 kb
Host smart-92f23ab3-afb5-46e6-9f89-8902240bb4a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112672165140608483232100512925327916459788915715284291154197857370497004450048 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.112672165140608483232100512925327916459788915715284291154197857370497004450048
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.86631821222482795546772661218730889584473999562640194345378268031657798870704
Short name T225
Test name
Test status
Simulation time 19913691647 ps
CPU time 587.39 seconds
Started Nov 22 02:16:43 PM PST 23
Finished Nov 22 02:26:31 PM PST 23
Peak memory 372524 kb
Host smart-ac666664-a104-4725-9e17-ad0da0904455
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86631821222482795546772661218730889584473999562640194345378268031657798870704 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.86631821222482795546772661218730889584473999562640194345378268031657798870704
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.95125434252259660796512650567017678885114179199485607708501082707537648516663
Short name T415
Test name
Test status
Simulation time 988289480 ps
CPU time 17.54 seconds
Started Nov 22 02:16:41 PM PST 23
Finished Nov 22 02:16:59 PM PST 23
Peak memory 245644 kb
Host smart-d3072f21-07ed-4e51-9ffd-77d237aca0fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95125434252259660796512650567017678885114179199485607708501082707537648516663 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.95125434252259660796512650567017678885114179199485607708501082707537648516663
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.33736115873766677796347744859418466660986994699192669943269458770709260932104
Short name T959
Test name
Test status
Simulation time 624328106 ps
CPU time 1746.12 seconds
Started Nov 22 02:16:38 PM PST 23
Finished Nov 22 02:45:45 PM PST 23
Peak memory 498160 kb
Host smart-59e566ba-5d29-4d74-b1de-0296ccd0514f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=33736115873766677796347744859418466660986994699192669943269458770709260932104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sr
am_ctrl_stress_all_with_rand_reset.33736115873766677796347744859418466660986994699192669943269458770709260932104
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.10657166697164871967077600534942605322214486456591667255297721196023224974802
Short name T440
Test name
Test status
Simulation time 9325508496 ps
CPU time 422.67 seconds
Started Nov 22 02:16:41 PM PST 23
Finished Nov 22 02:23:44 PM PST 23
Peak memory 202876 kb
Host smart-1f0ad241-2c6b-481e-860f-267a7da1432e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10657166697164871967077600534942605322214486456591667255297721196023224974802
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.106571666971648719670776005349426053222144864565916
67255297721196023224974802
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.10917571167172060674681843982468791425248426540234734159005483067763069260161
Short name T387
Test name
Test status
Simulation time 1371125703 ps
CPU time 127.72 seconds
Started Nov 22 02:16:37 PM PST 23
Finished Nov 22 02:18:45 PM PST 23
Peak memory 351200 kb
Host smart-2e8c65b4-5b5d-492e-b652-a52a540c0042
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109175711671720606746818439824687914252484265402347341
59005483067763069260161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1091757116717206067468
1843982468791425248426540234734159005483067763069260161
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.112829128829711642317724159369852398728715725769411620516587812646518300708037
Short name T648
Test name
Test status
Simulation time 13467153934 ps
CPU time 894.4 seconds
Started Nov 22 02:17:07 PM PST 23
Finished Nov 22 02:32:07 PM PST 23
Peak memory 378824 kb
Host smart-0571cf7e-fcca-4323-86ef-33cf8ea0a100
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11282912882971164231772415936985239872871572576941162051658781264651830070803
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during_key_req.11282912882971164231772415936985239872
8715725769411620516587812646518300708037
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.76047902680570177148929634640193701899205845793433931271511946487876694409108
Short name T671
Test name
Test status
Simulation time 16600825 ps
CPU time 0.67 seconds
Started Nov 22 02:17:04 PM PST 23
Finished Nov 22 02:17:11 PM PST 23
Peak memory 202604 kb
Host smart-658a9e99-871c-4c06-831a-51cebe3cc1f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760479026805701771489296346401937018992058457934339312715119464878
76694409108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.760479026805701771489296346401937018992058457934339312
71511946487876694409108
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.46380155454824362851517129777515245574048075828564421388916744018871601213754
Short name T362
Test name
Test status
Simulation time 295482808505 ps
CPU time 2763.32 seconds
Started Nov 22 02:16:38 PM PST 23
Finished Nov 22 03:02:42 PM PST 23
Peak memory 202808 kb
Host smart-bd9824b6-c930-4f6b-b3fd-cd229cccd13d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46380155454824362851517129777515245574048075828564421388916744018871601213754 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.46380155454824362851517129777515245574048075828564421388916744018871601213754
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.107628686823709468994739473634154098952601528798725235326838085164508659231068
Short name T40
Test name
Test status
Simulation time 31712811539 ps
CPU time 768.09 seconds
Started Nov 22 02:17:08 PM PST 23
Finished Nov 22 02:30:01 PM PST 23
Peak memory 367996 kb
Host smart-585c64e9-d9d9-4e89-9655-539dabef2ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107628686823709468994739473634154098952601528798725235326838085164508659231068 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.107628686823709468994739473634154098952601528798725235326838085164508659231068
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.106834389152398109472086770783951321355412188890936175993758817011393377784632
Short name T965
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.24 seconds
Started Nov 22 02:16:53 PM PST 23
Finished Nov 22 02:18:39 PM PST 23
Peak memory 211092 kb
Host smart-c8678db7-50da-4df3-ae6a-193282e4bd1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106834389152398109472086770783951321355412188890936175993758817011393377784632 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.106834389152398109472086770783951321355412188890936175993758817011393377784632
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.92276119218079078362731226048003704234020400553813572841563246669535427783833
Short name T915
Test name
Test status
Simulation time 1342947357 ps
CPU time 135.61 seconds
Started Nov 22 02:17:01 PM PST 23
Finished Nov 22 02:19:21 PM PST 23
Peak memory 351200 kb
Host smart-e6f0b442-6d2d-4f6a-8c95-c41afd45b3c0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9227611921807907836273122604800370423402040055381357284
1563246669535427783833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_max_throughput.92276119218079078362731226048003704
234020400553813572841563246669535427783833
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.104193429715012263762290357885815748723612938461484837431989328674297183572371
Short name T271
Test name
Test status
Simulation time 4750777237 ps
CPU time 76.53 seconds
Started Nov 22 02:17:02 PM PST 23
Finished Nov 22 02:18:22 PM PST 23
Peak memory 212356 kb
Host smart-b93868fb-c745-4827-bfd9-e81b33e06efe
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10419342971501226376229035788581574872361293846148483743198932867429
7183572371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.10419342971501226376229035788581574872361293846
1484837431989328674297183572371
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.105394243876632214032652293376253321025963192931630367845188387757800613633907
Short name T862
Test name
Test status
Simulation time 18445453393 ps
CPU time 158.08 seconds
Started Nov 22 02:16:52 PM PST 23
Finished Nov 22 02:19:30 PM PST 23
Peak memory 202836 kb
Host smart-c0b22dea-e235-4f8f-9196-8e2afaf904e7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105394243876632214032652293376253321025963192931630367845188387757800613633907
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.105394243876632214032652293376253321025963192931630367845188387757800613633907
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.111072205059559223484432933873198032882943240129951526142190211135515753587693
Short name T120
Test name
Test status
Simulation time 28731174678 ps
CPU time 687.11 seconds
Started Nov 22 02:16:43 PM PST 23
Finished Nov 22 02:28:11 PM PST 23
Peak memory 378780 kb
Host smart-0dafbabe-b8af-4d59-9948-40b7315cad41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111072205059559223484432933873198032882943240129951526142190211135515753587693 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.111072205059559223484432933873198032882943240129951526142190211135515753587693
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.21081992262738602977289610060099171952648638136795500546091632948281800580861
Short name T522
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.55 seconds
Started Nov 22 02:17:06 PM PST 23
Finished Nov 22 02:17:31 PM PST 23
Peak memory 245664 kb
Host smart-fdc2ae32-5c1e-4100-857a-722de63faaed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210819922627386029772896100600991719526486381367955005460916329482818
00580861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.210819922627386029772896100600991719526486381367955005
46091632948281800580861
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.62521797604419582756554224442469152689709004307806924390303946255032872554998
Short name T446
Test name
Test status
Simulation time 45083829570 ps
CPU time 568.93 seconds
Started Nov 22 02:17:06 PM PST 23
Finished Nov 22 02:26:42 PM PST 23
Peak memory 202852 kb
Host smart-b84ff186-4b0b-4d45-b2f8-2afa5475e173
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625217976044195827565542244424691526897090043078069243903039462550328
72554998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access_b2b.6252179760441958275655422444246915268970
9004307806924390303946255032872554998
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.93069926518663622756814547426112659359943664379758443989513316529975424704826
Short name T286
Test name
Test status
Simulation time 607542526 ps
CPU time 5.96 seconds
Started Nov 22 02:17:02 PM PST 23
Finished Nov 22 02:17:11 PM PST 23
Peak memory 203048 kb
Host smart-ce9884cf-8f3a-4b2d-b14a-bf9693e173a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93069926518663622756814547426112659359943664379758443989513316529975424704826 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.93069926518663622756814547426112659359943664379758443989513316529975424704826
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.64877377778536679717295382968723974669323211709705431909488710480975691771864
Short name T713
Test name
Test status
Simulation time 19913691647 ps
CPU time 631.96 seconds
Started Nov 22 02:17:07 PM PST 23
Finished Nov 22 02:27:45 PM PST 23
Peak memory 372500 kb
Host smart-be96ceb3-23d7-453d-bf07-da63ce4955c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64877377778536679717295382968723974669323211709705431909488710480975691771864 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.64877377778536679717295382968723974669323211709705431909488710480975691771864
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.104804472716365616289650838809990992570863649214669135223777508578479119023977
Short name T950
Test name
Test status
Simulation time 988289480 ps
CPU time 17.22 seconds
Started Nov 22 02:16:44 PM PST 23
Finished Nov 22 02:17:01 PM PST 23
Peak memory 245056 kb
Host smart-b4c1887a-3eb4-453c-a106-9b69c358f5a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104804472716365616289650838809990992570863649214669135223777508578479119023977 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.104804472716365616289650838809990992570863649214669135223777508578479119023977
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3109839682380101941845871417334310444698122262889432160282066338647757870286
Short name T391
Test name
Test status
Simulation time 624328106 ps
CPU time 1922.56 seconds
Started Nov 22 02:17:02 PM PST 23
Finished Nov 22 02:49:08 PM PST 23
Peak memory 498196 kb
Host smart-2e9dbadc-d9af-468d-bc65-ef71a2c8ad09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3109839682380101941845871417334310444698122262889432160282066338647757870286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sra
m_ctrl_stress_all_with_rand_reset.3109839682380101941845871417334310444698122262889432160282066338647757870286
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.79434631846857001781614325995551939336171966829792152671381812560744338863500
Short name T101
Test name
Test status
Simulation time 9325508496 ps
CPU time 417.85 seconds
Started Nov 22 02:16:59 PM PST 23
Finished Nov 22 02:24:03 PM PST 23
Peak memory 202876 kb
Host smart-10c7427f-3abe-483a-9ba2-acfb3c62f250
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79434631846857001781614325995551939336171966829792152671381812560744338863500
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.794346318468570017816143259955519393361719668297921
52671381812560744338863500
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.88568583036330028144548720247768801486029628467373765022688020228661875596857
Short name T616
Test name
Test status
Simulation time 1371125703 ps
CPU time 117.87 seconds
Started Nov 22 02:16:58 PM PST 23
Finished Nov 22 02:19:02 PM PST 23
Peak memory 351180 kb
Host smart-daa90723-cd38-42fd-bb2a-04ce430012a3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885685830363300281445487202477688014860296284673737650
22688020228661875596857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.8856858303633002814454
8720247768801486029628467373765022688020228661875596857
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.76412885372498138021850435258278869437648852566943916200603248471582690971383
Short name T445
Test name
Test status
Simulation time 13467153934 ps
CPU time 1045.67 seconds
Started Nov 22 02:17:03 PM PST 23
Finished Nov 22 02:34:31 PM PST 23
Peak memory 378800 kb
Host smart-8e73b8f4-8286-41b5-b407-655828451718
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76412885372498138021850435258278869437648852566943916200603248471582690971383
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during_key_req.764128853724981380218504352582788694376
48852566943916200603248471582690971383
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.22342060555500297485253501114614226475212180356454190038950338826913203272214
Short name T478
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 02:17:02 PM PST 23
Finished Nov 22 02:17:06 PM PST 23
Peak memory 202608 kb
Host smart-7183e900-daa0-4e34-8780-fbe5e5176537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223420605555002974852535011146142264752121803564541900389503388269
13203272214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.223420605555002974852535011146142264752121803564541900
38950338826913203272214
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.84420512045173481293129304159186337980092371204087528985850583797793822741140
Short name T978
Test name
Test status
Simulation time 295482808505 ps
CPU time 2706.37 seconds
Started Nov 22 02:17:02 PM PST 23
Finished Nov 22 03:02:12 PM PST 23
Peak memory 202788 kb
Host smart-ce48aac1-d117-4d92-8d8e-ddc1e414123e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84420512045173481293129304159186337980092371204087528985850583797793822741140 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.84420512045173481293129304159186337980092371204087528985850583797793822741140
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.52696245884594912039411789052627636990867442142783394043989686848315465855320
Short name T418
Test name
Test status
Simulation time 31712811539 ps
CPU time 706.49 seconds
Started Nov 22 02:17:06 PM PST 23
Finished Nov 22 02:28:59 PM PST 23
Peak memory 368024 kb
Host smart-806d5184-8662-428f-90ff-e959d388797f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52696245884594912039411789052627636990867442142783394043989686848315465855320 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.52696245884594912039411789052627636990867442142783394043989686848315465855320
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.77090052606012925286491248360510387322968705906100091716303691985995068917427
Short name T377
Test name
Test status
Simulation time 19084394710 ps
CPU time 102.36 seconds
Started Nov 22 02:17:02 PM PST 23
Finished Nov 22 02:18:48 PM PST 23
Peak memory 211088 kb
Host smart-8813179c-5d0c-4405-810e-718b391d2196
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77090052606012925286491248360510387322968705906100091716303691985995068917427 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.77090052606012925286491248360510387322968705906100091716303691985995068917427
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.97464425940267751668362965850674356875411904402131985080545038535454184802607
Short name T760
Test name
Test status
Simulation time 1342947357 ps
CPU time 110.04 seconds
Started Nov 22 02:16:56 PM PST 23
Finished Nov 22 02:18:48 PM PST 23
Peak memory 351280 kb
Host smart-ccd1e711-e809-4d7a-a182-95c6fde80e9a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9746442594026775166836296585067435687541190440213198508
0545038535454184802607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_max_throughput.97464425940267751668362965850674356
875411904402131985080545038535454184802607
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.37566966840750595155796128065359667250276728982624196007890719813038455684885
Short name T448
Test name
Test status
Simulation time 4750777237 ps
CPU time 81.48 seconds
Started Nov 22 02:17:08 PM PST 23
Finished Nov 22 02:18:34 PM PST 23
Peak memory 212376 kb
Host smart-45ee3c0b-3397-4804-a8ce-c2b414f849d4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37566966840750595155796128065359667250276728982624196007890719813038
455684885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.375669668407505951557961280653596672502767289826
24196007890719813038455684885
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.5286087994287677523214287374611530177545488732647372885375999274936884723593
Short name T15
Test name
Test status
Simulation time 18445453393 ps
CPU time 156.7 seconds
Started Nov 22 02:17:07 PM PST 23
Finished Nov 22 02:19:50 PM PST 23
Peak memory 202748 kb
Host smart-423bdd6f-c195-4d9b-9c77-b04723058a25
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5286087994287677523214287374611530177545488732647372885375999274936884723593 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.5286087994287677523214287374611530177545488732647372885375999274936884723593
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.81298309424623664525568047960716248997246619035782835211575162398444273551038
Short name T348
Test name
Test status
Simulation time 28731174678 ps
CPU time 921.61 seconds
Started Nov 22 02:17:02 PM PST 23
Finished Nov 22 02:32:27 PM PST 23
Peak memory 378684 kb
Host smart-9a36f48b-8283-4156-85c5-b4ad28af0bcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81298309424623664525568047960716248997246619035782835211575162398444273551038 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.81298309424623664525568047960716248997246619035782835211575162398444273551038
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.71938657414100530351895506547118377513607437510947641446286718454496477382411
Short name T741
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.67 seconds
Started Nov 22 02:17:08 PM PST 23
Finished Nov 22 02:17:33 PM PST 23
Peak memory 245724 kb
Host smart-b81e2e68-cbef-49ec-8c44-10e75a0fd421
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719386574141005303518955065471183775136074375109476414462867184544964
77382411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.719386574141005303518955065471183775136074375109476414
46286718454496477382411
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3553927664429362214543277242600463551041236528238157113159220887372098272101
Short name T987
Test name
Test status
Simulation time 45083829570 ps
CPU time 559.36 seconds
Started Nov 22 02:16:59 PM PST 23
Finished Nov 22 02:26:24 PM PST 23
Peak memory 202860 kb
Host smart-e4bff3d4-c5ed-492d-ac77-acb5a9c0f991
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355392766442936221454327724260046355104123652823815711315922088737209
8272101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access_b2b.35539276644293622145432772426004635510412
36528238157113159220887372098272101
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.97762740373290348467905550490106329625789706590870675206561151010909785917051
Short name T852
Test name
Test status
Simulation time 607542526 ps
CPU time 6.18 seconds
Started Nov 22 02:17:09 PM PST 23
Finished Nov 22 02:17:19 PM PST 23
Peak memory 203140 kb
Host smart-91306004-eaa2-46e2-90e0-6f5ccc9b222a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97762740373290348467905550490106329625789706590870675206561151010909785917051 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.97762740373290348467905550490106329625789706590870675206561151010909785917051
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.5658685198424597079133859482076375498682968395603671282020683530376282491349
Short name T610
Test name
Test status
Simulation time 19913691647 ps
CPU time 614.82 seconds
Started Nov 22 02:16:52 PM PST 23
Finished Nov 22 02:27:08 PM PST 23
Peak memory 372440 kb
Host smart-78379092-21e9-4098-a729-970e1d2ccba5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5658685198424597079133859482076375498682968395603671282020683530376282491349 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.5658685198424597079133859482076375498682968395603671282020683530376282491349
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.78973204064977986635302584271311953285112101963451396102922803140560962281627
Short name T914
Test name
Test status
Simulation time 988289480 ps
CPU time 18.7 seconds
Started Nov 22 02:16:50 PM PST 23
Finished Nov 22 02:17:10 PM PST 23
Peak memory 245616 kb
Host smart-5227bb38-ccf0-48b1-ae49-7a5f1bd470d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78973204064977986635302584271311953285112101963451396102922803140560962281627 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.78973204064977986635302584271311953285112101963451396102922803140560962281627
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.48412645814854914783746376973973472992258429319833668595426475817379994666286
Short name T320
Test name
Test status
Simulation time 624328106 ps
CPU time 1996.48 seconds
Started Nov 22 02:17:01 PM PST 23
Finished Nov 22 02:50:22 PM PST 23
Peak memory 498192 kb
Host smart-6fe82b93-1660-4e23-936d-2ad5d0842f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=48412645814854914783746376973973472992258429319833668595426475817379994666286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sr
am_ctrl_stress_all_with_rand_reset.48412645814854914783746376973973472992258429319833668595426475817379994666286
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.41899765179820596960047493353545848183078511028252526000742819029449875243957
Short name T654
Test name
Test status
Simulation time 9325508496 ps
CPU time 426.75 seconds
Started Nov 22 02:16:59 PM PST 23
Finished Nov 22 02:24:11 PM PST 23
Peak memory 202876 kb
Host smart-a3f2ce1e-c2ed-4f00-8e35-98d4da16fa0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41899765179820596960047493353545848183078511028252526000742819029449875243957
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.418997651798205969600474933535458481830785110282525
26000742819029449875243957
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.45354731109821598571378094607771769872629069219167841505177482596015180688590
Short name T578
Test name
Test status
Simulation time 1371125703 ps
CPU time 106.9 seconds
Started Nov 22 02:17:03 PM PST 23
Finished Nov 22 02:18:52 PM PST 23
Peak memory 351204 kb
Host smart-714b1e96-6b84-4cef-8fb5-27c8811f9e8b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453547311098215985713780946077717698726290692191678415
05177482596015180688590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.4535473110982159857137
8094607771769872629069219167841505177482596015180688590
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.78590107220036670872765928053200098765802184476858040141131284504018726613558
Short name T745
Test name
Test status
Simulation time 13467153934 ps
CPU time 848.14 seconds
Started Nov 22 02:17:32 PM PST 23
Finished Nov 22 02:31:41 PM PST 23
Peak memory 378828 kb
Host smart-820fe099-871a-47c2-a75d-ce4b0bbe2339
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78590107220036670872765928053200098765802184476858040141131284504018726613558
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during_key_req.785901072200366708727659280532000987658
02184476858040141131284504018726613558
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.104088809827073130036936858285966753704450228344335938996328119715219913777349
Short name T21
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 02:17:29 PM PST 23
Finished Nov 22 02:17:30 PM PST 23
Peak memory 202596 kb
Host smart-56c6dafc-a136-4e5f-a8e3-7d23df6d85d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104088809827073130036936858285966753704450228344335938996328119715
219913777349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.10408880982707313003693685828596675370445022834433593
8996328119715219913777349
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.89811061634449675443139165128447771184483183587815725400730601054482132890114
Short name T545
Test name
Test status
Simulation time 295482808505 ps
CPU time 2800.18 seconds
Started Nov 22 02:17:17 PM PST 23
Finished Nov 22 03:03:59 PM PST 23
Peak memory 202860 kb
Host smart-31e7df97-0a3a-4a38-adb6-5adfaa2d6786
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89811061634449675443139165128447771184483183587815725400730601054482132890114 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.89811061634449675443139165128447771184483183587815725400730601054482132890114
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.41149178694468628462684995744734376752219213707358845142709826837042087597477
Short name T274
Test name
Test status
Simulation time 31712811539 ps
CPU time 826.82 seconds
Started Nov 22 02:18:08 PM PST 23
Finished Nov 22 02:31:55 PM PST 23
Peak memory 368044 kb
Host smart-a6c73de2-7af3-4036-a1ac-842218fb7ec5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41149178694468628462684995744734376752219213707358845142709826837042087597477 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.41149178694468628462684995744734376752219213707358845142709826837042087597477
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.2098239010684946790612084963890981095143942798605545730283818383041837486085
Short name T378
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.23 seconds
Started Nov 22 02:17:32 PM PST 23
Finished Nov 22 02:19:18 PM PST 23
Peak memory 210972 kb
Host smart-3a1c1ea3-e77a-4533-bde0-e47d68f7490b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098239010684946790612084963890981095143942798605545730283818383041837486085 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.2098239010684946790612084963890981095143942798605545730283818383041837486085
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.64647420309797065029237542367658563373508035537234565777947909139069953511332
Short name T501
Test name
Test status
Simulation time 1342947357 ps
CPU time 122.19 seconds
Started Nov 22 02:17:34 PM PST 23
Finished Nov 22 02:19:37 PM PST 23
Peak memory 351196 kb
Host smart-b524ab5b-1cb9-42e6-96bb-412cec778ec9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6464742030979706502923754236765856337350803553723456577
7947909139069953511332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_max_throughput.64647420309797065029237542367658563
373508035537234565777947909139069953511332
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4992841181409713679703256779701040642924192936897093423434251113341104583033
Short name T335
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.96 seconds
Started Nov 22 02:17:41 PM PST 23
Finished Nov 22 02:19:00 PM PST 23
Peak memory 212320 kb
Host smart-64c1fd73-5500-48a4-80dc-8e0fa6fa9f4e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49928411814097136797032567797010406429241929368970934234342511133411
04583033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.4992841181409713679703256779701040642924192936897
093423434251113341104583033
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.28044681112341300684347415165322074731020726563321117763875162249260318271248
Short name T815
Test name
Test status
Simulation time 18445453393 ps
CPU time 157.71 seconds
Started Nov 22 02:17:16 PM PST 23
Finished Nov 22 02:19:56 PM PST 23
Peak memory 202760 kb
Host smart-850747a7-5992-4129-8663-49796893fe55
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28044681112341300684347415165322074731020726563321117763875162249260318271248
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.28044681112341300684347415165322074731020726563321117763875162249260318271248
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.40011869501420242255201735992675675110751763521243586244222704019541139234577
Short name T582
Test name
Test status
Simulation time 28731174678 ps
CPU time 875.72 seconds
Started Nov 22 02:16:52 PM PST 23
Finished Nov 22 02:31:29 PM PST 23
Peak memory 378660 kb
Host smart-6e2304ab-0164-4875-8524-454c72a8001b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40011869501420242255201735992675675110751763521243586244222704019541139234577 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.40011869501420242255201735992675675110751763521243586244222704019541139234577
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.24567878638505232062756135635310790579735409788006607561501719171318509233247
Short name T316
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.35 seconds
Started Nov 22 02:17:31 PM PST 23
Finished Nov 22 02:17:50 PM PST 23
Peak memory 245644 kb
Host smart-996c12ab-060a-46be-a4ef-4fe17f19bb99
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245678786385052320627561356353107905797354097880066075615017191713185
09233247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.245678786385052320627561356353107905797354097880066075
61501719171318509233247
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3691624191321070142278266637718006606902331353866526680452535118482157851675
Short name T341
Test name
Test status
Simulation time 45083829570 ps
CPU time 551.13 seconds
Started Nov 22 02:17:48 PM PST 23
Finished Nov 22 02:27:00 PM PST 23
Peak memory 202924 kb
Host smart-31cccdeb-b8b9-44ac-97d3-531180a8c418
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369162419132107014227826663771800660690233135386652668045253511848215
7851675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access_b2b.36916241913210701422782666377180066069023
31353866526680452535118482157851675
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.4615850392545358122187005024774353204588776035953841574632898575425804318594
Short name T957
Test name
Test status
Simulation time 607542526 ps
CPU time 6.15 seconds
Started Nov 22 02:17:41 PM PST 23
Finished Nov 22 02:17:47 PM PST 23
Peak memory 203132 kb
Host smart-43d59aa2-f785-4de6-8411-ee50520dc3f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4615850392545358122187005024774353204588776035953841574632898575425804318594 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.4615850392545358122187005024774353204588776035953841574632898575425804318594
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.50271664782769172079447091745961925820341678214431959719570310391788288174915
Short name T1
Test name
Test status
Simulation time 19913691647 ps
CPU time 606.76 seconds
Started Nov 22 02:17:32 PM PST 23
Finished Nov 22 02:27:40 PM PST 23
Peak memory 372608 kb
Host smart-07724c4f-32b2-40d0-9243-1b04e256a914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50271664782769172079447091745961925820341678214431959719570310391788288174915 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.50271664782769172079447091745961925820341678214431959719570310391788288174915
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.69099818452968902168928869380570811139665720143796435244220711294208203827906
Short name T587
Test name
Test status
Simulation time 988289480 ps
CPU time 16.33 seconds
Started Nov 22 02:17:02 PM PST 23
Finished Nov 22 02:17:21 PM PST 23
Peak memory 245652 kb
Host smart-c838a1e0-b577-4283-88ac-d9e1cc2560a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69099818452968902168928869380570811139665720143796435244220711294208203827906 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.69099818452968902168928869380570811139665720143796435244220711294208203827906
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.7442252227346184195671398787544675368356971417780599551839123890543518082513
Short name T336
Test name
Test status
Simulation time 624328106 ps
CPU time 2132.8 seconds
Started Nov 22 02:17:15 PM PST 23
Finished Nov 22 02:52:50 PM PST 23
Peak memory 498172 kb
Host smart-4e5c4c3a-c1b5-43ef-8040-c0e2c2fc35b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=7442252227346184195671398787544675368356971417780599551839123890543518082513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sra
m_ctrl_stress_all_with_rand_reset.7442252227346184195671398787544675368356971417780599551839123890543518082513
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.14234033645597402799100310123012769508515924949764897004684959542983080546663
Short name T571
Test name
Test status
Simulation time 9325508496 ps
CPU time 406.98 seconds
Started Nov 22 02:17:33 PM PST 23
Finished Nov 22 02:24:21 PM PST 23
Peak memory 202860 kb
Host smart-bbeb3b25-bfc2-4b42-91d3-f14f29a6cfab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14234033645597402799100310123012769508515924949764897004684959542983080546663
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.142340336455974027991003101230127695085159249497648
97004684959542983080546663
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.89808313137886991356097375445137986817629222033992155640329155966729567060012
Short name T672
Test name
Test status
Simulation time 1371125703 ps
CPU time 117.55 seconds
Started Nov 22 02:18:10 PM PST 23
Finished Nov 22 02:20:08 PM PST 23
Peak memory 351180 kb
Host smart-5c5e5f99-c2f1-4236-80c5-4558d1761582
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898083131378869913560973754451379868176292220339921556
40329155966729567060012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.8980831313788699135609
7375445137986817629222033992155640329155966729567060012
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.108767298176388597187350584688388943845700835102983536038829219917848332996376
Short name T383
Test name
Test status
Simulation time 13467153934 ps
CPU time 1012.18 seconds
Started Nov 22 02:17:31 PM PST 23
Finished Nov 22 02:34:23 PM PST 23
Peak memory 378756 kb
Host smart-32cf54ea-dba8-4d46-90d0-3002aabb1aa2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10876729817638859718735058468838894384570083510298353603882921991784833299637
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during_key_req.10876729817638859718735058468838894384
5700835102983536038829219917848332996376
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.90886941699910329589604253058268331435167948038507840110367476489532052137786
Short name T424
Test name
Test status
Simulation time 16600825 ps
CPU time 0.63 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:18:09 PM PST 23
Peak memory 202632 kb
Host smart-cbaaeb81-3fae-4fa8-ba0d-e1e76445dc82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908869416999103295896042530582683314351679480385078401103674764895
32052137786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.908869416999103295896042530582683314351679480385078401
10367476489532052137786
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.58348131086001003563326618354558374665730579997604546132012407656969775036763
Short name T657
Test name
Test status
Simulation time 295482808505 ps
CPU time 2787.67 seconds
Started Nov 22 02:17:49 PM PST 23
Finished Nov 22 03:04:17 PM PST 23
Peak memory 202892 kb
Host smart-01eecac1-df2a-4b25-a091-1c7576e505f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58348131086001003563326618354558374665730579997604546132012407656969775036763 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.58348131086001003563326618354558374665730579997604546132012407656969775036763
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.10843331122080262486161841996059669080454382406793046456754119853817717910139
Short name T221
Test name
Test status
Simulation time 31712811539 ps
CPU time 777.24 seconds
Started Nov 22 02:17:32 PM PST 23
Finished Nov 22 02:30:30 PM PST 23
Peak memory 368008 kb
Host smart-4db313e6-c1aa-4573-8a84-376958356dfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843331122080262486161841996059669080454382406793046456754119853817717910139 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.10843331122080262486161841996059669080454382406793046456754119853817717910139
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.52226390314423620070253765244112940505359500385325868108106596468291532671461
Short name T972
Test name
Test status
Simulation time 19084394710 ps
CPU time 106.6 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:19:54 PM PST 23
Peak memory 211056 kb
Host smart-d80d2449-8f9a-4b1d-963a-0b5b1b293d7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52226390314423620070253765244112940505359500385325868108106596468291532671461 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.52226390314423620070253765244112940505359500385325868108106596468291532671461
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.18003198491722677836428836853728474060225642734898218081892344038699016926332
Short name T780
Test name
Test status
Simulation time 1342947357 ps
CPU time 113.19 seconds
Started Nov 22 02:17:49 PM PST 23
Finished Nov 22 02:19:43 PM PST 23
Peak memory 351104 kb
Host smart-fda79cbc-5355-453c-8579-3a9ed48b0549
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800319849172267783642883685372847406022564273489821808
1892344038699016926332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_max_throughput.18003198491722677836428836853728474
060225642734898218081892344038699016926332
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.107152840507035618865148839583928174571245360355104590656041417639827502608780
Short name T552
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.4 seconds
Started Nov 22 02:17:41 PM PST 23
Finished Nov 22 02:19:00 PM PST 23
Peak memory 212324 kb
Host smart-1db9f996-dfd3-460c-81c2-6cba11f0acdf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10715284050703561886514883958392817457124536035510459065604141763982
7502608780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.10715284050703561886514883958392817457124536035
5104590656041417639827502608780
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.115603393235978463129376258675199154966027194181021762610970725077124888050216
Short name T880
Test name
Test status
Simulation time 18445453393 ps
CPU time 155 seconds
Started Nov 22 02:17:16 PM PST 23
Finished Nov 22 02:19:53 PM PST 23
Peak memory 202768 kb
Host smart-557d0929-7b3a-4e48-b36a-bab2f8a6e3b1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115603393235978463129376258675199154966027194181021762610970725077124888050216
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.115603393235978463129376258675199154966027194181021762610970725077124888050216
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.70586391532034761857273383149262828399695045484056633265495423769725171337959
Short name T451
Test name
Test status
Simulation time 28731174678 ps
CPU time 847.11 seconds
Started Nov 22 02:17:15 PM PST 23
Finished Nov 22 02:31:25 PM PST 23
Peak memory 378636 kb
Host smart-8d61bf7d-cab3-43c9-b946-f605ee1f3193
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70586391532034761857273383149262828399695045484056633265495423769725171337959 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.70586391532034761857273383149262828399695045484056633265495423769725171337959
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.75843620366666554589457024463829575509106801391863781296313324614097004348257
Short name T937
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.03 seconds
Started Nov 22 02:17:33 PM PST 23
Finished Nov 22 02:17:53 PM PST 23
Peak memory 245728 kb
Host smart-ef2aa22c-7cd9-4596-bacc-0280d103a46a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758436203666665545894570244638295755091068013918637812963133246140970
04348257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.758436203666665545894570244638295755091068013918637812
96313324614097004348257
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.65244728499427050398585401189204721566523540157703533875757165108568184166623
Short name T689
Test name
Test status
Simulation time 45083829570 ps
CPU time 566.45 seconds
Started Nov 22 02:18:05 PM PST 23
Finished Nov 22 02:27:32 PM PST 23
Peak memory 202860 kb
Host smart-ee640662-6aaf-468f-bfa2-2a8fc31700c7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652447284994270503985854011892047215665235401577035338757571651085681
84166623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access_b2b.6524472849942705039858540118920472156652
3540157703533875757165108568184166623
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.43008476459499284227224041666811383809525118990032511111811914453776698560024
Short name T349
Test name
Test status
Simulation time 607542526 ps
CPU time 6.27 seconds
Started Nov 22 02:17:51 PM PST 23
Finished Nov 22 02:17:57 PM PST 23
Peak memory 203108 kb
Host smart-66f4e7c4-0d25-4464-bcec-fa90dd558711
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43008476459499284227224041666811383809525118990032511111811914453776698560024 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.43008476459499284227224041666811383809525118990032511111811914453776698560024
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.65136745524426823013695220452767464518589255437491267131155694836854492848069
Short name T502
Test name
Test status
Simulation time 19913691647 ps
CPU time 628.36 seconds
Started Nov 22 02:17:16 PM PST 23
Finished Nov 22 02:27:46 PM PST 23
Peak memory 372520 kb
Host smart-b7b80f49-8f05-4f36-a7bb-66970646e532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65136745524426823013695220452767464518589255437491267131155694836854492848069 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.65136745524426823013695220452767464518589255437491267131155694836854492848069
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.53743558366974966682160792969840176812339087246351580258314061135144850193665
Short name T380
Test name
Test status
Simulation time 988289480 ps
CPU time 16.08 seconds
Started Nov 22 02:17:12 PM PST 23
Finished Nov 22 02:17:30 PM PST 23
Peak memory 245712 kb
Host smart-da7d3265-8407-413d-b898-f2f8d8a740b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53743558366974966682160792969840176812339087246351580258314061135144850193665 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.53743558366974966682160792969840176812339087246351580258314061135144850193665
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1419254284051700224128733722599549630159848685259732068869802020218899312667
Short name T357
Test name
Test status
Simulation time 624328106 ps
CPU time 1682.58 seconds
Started Nov 22 02:17:41 PM PST 23
Finished Nov 22 02:45:45 PM PST 23
Peak memory 498200 kb
Host smart-5302be9b-6af4-446c-ab38-d63d55161af6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1419254284051700224128733722599549630159848685259732068869802020218899312667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sra
m_ctrl_stress_all_with_rand_reset.1419254284051700224128733722599549630159848685259732068869802020218899312667
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.54238847366030347195305921511681504467898201371467168269914218009362952263897
Short name T308
Test name
Test status
Simulation time 9325508496 ps
CPU time 420.48 seconds
Started Nov 22 02:17:40 PM PST 23
Finished Nov 22 02:24:41 PM PST 23
Peak memory 202932 kb
Host smart-888b9bc2-0293-43d7-95a8-7935270c33cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54238847366030347195305921511681504467898201371467168269914218009362952263897
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.542388473660303471953059215116815044678982013714671
68269914218009362952263897
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.112653607518444256768650824095321067464890033491846586314556317132098107094382
Short name T401
Test name
Test status
Simulation time 1371125703 ps
CPU time 123.91 seconds
Started Nov 22 02:17:19 PM PST 23
Finished Nov 22 02:19:24 PM PST 23
Peak memory 351148 kb
Host smart-c06efbc6-6e9a-4528-be4b-6b2dd32ab843
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112653607518444256768650824095321067464890033491846586
314556317132098107094382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.112653607518444256768
650824095321067464890033491846586314556317132098107094382
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.34120419841211027920056112560723199252494243983140705124147854622779166319401
Short name T20
Test name
Test status
Simulation time 13467153934 ps
CPU time 925.58 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:23:03 PM PST 23
Peak memory 378768 kb
Host smart-baf730c0-f382-4a2e-a14e-b1bcfa823ce5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34120419841211027920056112560723199252494243983140705124147854622779166319401
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_key_req.3412041984121102792005611256072319925249
4243983140705124147854622779166319401
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.43920589289279934344790675281418879049520608168748007887334928363453170977284
Short name T619
Test name
Test status
Simulation time 16600825 ps
CPU time 0.65 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:07:41 PM PST 23
Peak memory 202624 kb
Host smart-d0cf21b3-8d83-415e-819e-a87afd0760f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439205892892799343447906752814188790495206081687480078873349283634
53170977284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.4392058928927993434479067528141887904952060816874800788
7334928363453170977284
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.20557991652474699150635211045452630704752669606939458118117546001053797623174
Short name T805
Test name
Test status
Simulation time 295482808505 ps
CPU time 2757.01 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:53:38 PM PST 23
Peak memory 202852 kb
Host smart-a73d99d1-3975-46fc-800c-97366fdb0220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20557991652474699150635211045452630704752669606939458118117546001053797623174 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.20557991652474699150635211045452630704752669606939458118117546001053797623174
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.91776827247244288881392354337845331073978723515427290965230787407627823736548
Short name T104
Test name
Test status
Simulation time 31712811539 ps
CPU time 973.62 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:23:51 PM PST 23
Peak memory 367976 kb
Host smart-04be4c4b-508b-43f1-806e-2dd2721a6d3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91776827247244288881392354337845331073978723515427290965230787407627823736548 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.91776827247244288881392354337845331073978723515427290965230787407627823736548
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.84571802172034863713122680112928596206633416699385322828348310498328367903310
Short name T933
Test name
Test status
Simulation time 19084394710 ps
CPU time 107.64 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:09:25 PM PST 23
Peak memory 211020 kb
Host smart-5d7e2531-5572-413c-acac-dfbdefdd9119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84571802172034863713122680112928596206633416699385322828348310498328367903310 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.84571802172034863713122680112928596206633416699385322828348310498328367903310
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.87180035477830084964338814972079665862590378776554254783759911963579368773718
Short name T510
Test name
Test status
Simulation time 1342947357 ps
CPU time 117.81 seconds
Started Nov 22 02:07:25 PM PST 23
Finished Nov 22 02:09:24 PM PST 23
Peak memory 351168 kb
Host smart-4565334b-0a6c-492c-a0da-b7a26eb907fb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8718003547783008496433881497207966586259037877655425478
3759911963579368773718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max_throughput.871800354778300849643388149720796658
62590378776554254783759911963579368773718
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.35833620963117231667787188645963267319686189090017733101146468112930405175755
Short name T954
Test name
Test status
Simulation time 4750777237 ps
CPU time 79.53 seconds
Started Nov 22 02:07:24 PM PST 23
Finished Nov 22 02:08:45 PM PST 23
Peak memory 212272 kb
Host smart-9a3298da-5735-404a-9cd7-36fe9a238466
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35833620963117231667787188645963267319686189090017733101146468112930
405175755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.3583362096311723166778718864596326731968618909001
7733101146468112930405175755
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.41407746302284660528217387702065578912362682412930551864894188718835805025625
Short name T561
Test name
Test status
Simulation time 18445453393 ps
CPU time 166.19 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:10:24 PM PST 23
Peak memory 202868 kb
Host smart-0f855301-f9f7-4d7a-b582-f7b1035538ba
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41407746302284660528217387702065578912362682412930551864894188718835805025625
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.41407746302284660528217387702065578912362682412930551864894188718835805025625
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.107907240717704071074667170415711036680416472249873398212699980841010925907443
Short name T442
Test name
Test status
Simulation time 28731174678 ps
CPU time 1012.25 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:24:33 PM PST 23
Peak memory 378672 kb
Host smart-8dfd2f94-b6ae-4da0-80f2-5c95f9dd07ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107907240717704071074667170415711036680416472249873398212699980841010925907443 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.107907240717704071074667170415711036680416472249873398212699980841010925907443
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.8445774694325154530674045486235214190224832361833223485454550401391562092370
Short name T646
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.49 seconds
Started Nov 22 02:07:39 PM PST 23
Finished Nov 22 02:07:59 PM PST 23
Peak memory 245680 kb
Host smart-3ab75b66-f075-4851-a1e6-1f8db9b63812
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844577469432515453067404548623521419022483236183322348545455040139156
2092370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.84457746943251545306740454862352141902248323618332234854
54550401391562092370
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.54713373240759441902078367458752323423257830798342892552236353391454838761691
Short name T564
Test name
Test status
Simulation time 607542526 ps
CPU time 6.16 seconds
Started Nov 22 02:07:22 PM PST 23
Finished Nov 22 02:07:30 PM PST 23
Peak memory 203124 kb
Host smart-e26a01f6-563d-4483-8b7b-4a43d165b76a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54713373240759441902078367458752323423257830798342892552236353391454838761691 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.54713373240759441902078367458752323423257830798342892552236353391454838761691
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.22478793642770209803943369672576002111575714404824752711847557614835206466952
Short name T299
Test name
Test status
Simulation time 19913691647 ps
CPU time 742.06 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:20:00 PM PST 23
Peak memory 372464 kb
Host smart-319e9bc4-f44d-4e79-9748-e75a2b93a1ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22478793642770209803943369672576002111575714404824752711847557614835206466952 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.22478793642770209803943369672576002111575714404824752711847557614835206466952
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.8956970619679677708599784527456026146613907139684334030281938822954967523131
Short name T537
Test name
Test status
Simulation time 988289480 ps
CPU time 17.9 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:07:56 PM PST 23
Peak memory 245648 kb
Host smart-22a1dd4a-ab40-4050-912e-de35a48c4651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8956970619679677708599784527456026146613907139684334030281938822954967523131 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.8956970619679677708599784527456026146613907139684334030281938822954967523131
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.45344416460221750361013200076000972846866650674626384013083906695774141301124
Short name T2
Test name
Test status
Simulation time 624328106 ps
CPU time 1995.4 seconds
Started Nov 22 02:07:34 PM PST 23
Finished Nov 22 02:40:52 PM PST 23
Peak memory 498196 kb
Host smart-79b54cc8-fb88-4e16-b197-07a2c0c16be5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=45344416460221750361013200076000972846866650674626384013083906695774141301124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sra
m_ctrl_stress_all_with_rand_reset.45344416460221750361013200076000972846866650674626384013083906695774141301124
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.85828727901509455345763046026384688337261776839413274636025061863637599900457
Short name T102
Test name
Test status
Simulation time 9325508496 ps
CPU time 426.14 seconds
Started Nov 22 02:07:37 PM PST 23
Finished Nov 22 02:14:45 PM PST 23
Peak memory 202896 kb
Host smart-03d5c051-7bd5-4527-a6ff-d53ff1568655
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85828727901509455345763046026384688337261776839413274636025061863637599900457
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.8582872790150945534576304602638468833726177683941327
4636025061863637599900457
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.81164926440714900944250202222477735949535612010529507896385923011495516967713
Short name T480
Test name
Test status
Simulation time 1371125703 ps
CPU time 116.52 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:09:34 PM PST 23
Peak memory 351132 kb
Host smart-6a07d1b3-65f2-4a04-99f0-ef14c963d976
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811649264407149009442502022224777359495356120105295078
96385923011495516967713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.81164926440714900944250
202222477735949535612010529507896385923011495516967713
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.53495168289895495218886579714740186949293969901327736879624417580143644319971
Short name T290
Test name
Test status
Simulation time 13467153934 ps
CPU time 1051.48 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:25:09 PM PST 23
Peak memory 378732 kb
Host smart-e7edc27c-8dc7-40e0-89bb-8678c485d6b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53495168289895495218886579714740186949293969901327736879624417580143644319971
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_key_req.5349516828989549521888657971474018694929
3969901327736879624417580143644319971
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.5616802863889510673594583480712683351768576954011780755040991659145609068462
Short name T932
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:07:24 PM PST 23
Finished Nov 22 02:07:26 PM PST 23
Peak memory 202548 kb
Host smart-43038ff1-bea3-470d-975c-6b73f5856cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561680286388951067359458348071268335176857695401178075504099165914
5609068462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.56168028638895106735945834807126833517685769540117807550
40991659145609068462
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.102748158618039133091634252200586740617455684010858829559040778094405829115102
Short name T386
Test name
Test status
Simulation time 295482808505 ps
CPU time 2749.11 seconds
Started Nov 22 02:07:42 PM PST 23
Finished Nov 22 02:53:33 PM PST 23
Peak memory 202924 kb
Host smart-953281a0-0fe6-4b1f-8a37-9c09221a3bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102748158618039133091634252200586740617455684010858829559040778094405829115102 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.102748158618039133091634252200586740617455684010858829559040778094405829115102
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.67115242294128130532754715715254747254249536910416760414468155273498923832474
Short name T363
Test name
Test status
Simulation time 31712811539 ps
CPU time 876.16 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:22:16 PM PST 23
Peak memory 367916 kb
Host smart-7674b351-3fc6-4cbb-b499-87d5f1ec1071
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67115242294128130532754715715254747254249536910416760414468155273498923832474 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.67115242294128130532754715715254747254249536910416760414468155273498923832474
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.45676316894798971622451815964755312881383040844059310665579417952272754044570
Short name T751
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.2 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:09:23 PM PST 23
Peak memory 211072 kb
Host smart-e3160193-2127-40f4-bfd6-b65c46a325eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45676316894798971622451815964755312881383040844059310665579417952272754044570 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.45676316894798971622451815964755312881383040844059310665579417952272754044570
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.88620919540147095445186739418184537606555046568364243035781742984869161638621
Short name T443
Test name
Test status
Simulation time 1342947357 ps
CPU time 128.08 seconds
Started Nov 22 02:07:24 PM PST 23
Finished Nov 22 02:09:33 PM PST 23
Peak memory 351180 kb
Host smart-571a6fbe-e6e5-4002-9b92-8a4727bf5aa7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8862091954014709544518673941818453760655504656836424303
5781742984869161638621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max_throughput.886209195401470954451867394181845376
06555046568364243035781742984869161638621
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.48011374824075938714111374739357047895004338311964244052673223575895809149199
Short name T589
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.59 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:08:59 PM PST 23
Peak memory 212384 kb
Host smart-ea2eec30-cccc-48d1-ba1e-eab7a9c7ad46
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48011374824075938714111374739357047895004338311964244052673223575895
809149199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.4801137482407593871411137473935704789500433831196
4244052673223575895809149199
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.95889045330545241430044198529172259115391201664297222909761381102490650178975
Short name T38
Test name
Test status
Simulation time 18445453393 ps
CPU time 159.48 seconds
Started Nov 22 02:07:34 PM PST 23
Finished Nov 22 02:10:16 PM PST 23
Peak memory 202764 kb
Host smart-6ab77106-e8d3-4f6a-8595-f33388c654fb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95889045330545241430044198529172259115391201664297222909761381102490650178975
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.95889045330545241430044198529172259115391201664297222909761381102490650178975
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.73709710915786807133773723448611371686224262009984286658431576614490049245307
Short name T612
Test name
Test status
Simulation time 28731174678 ps
CPU time 955.96 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:23:34 PM PST 23
Peak memory 378612 kb
Host smart-c5c69634-7ee4-415c-8ace-af988d3db17a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73709710915786807133773723448611371686224262009984286658431576614490049245307 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.73709710915786807133773723448611371686224262009984286658431576614490049245307
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.10255021083601663162926901658845296391188374288493341690300566477421138298713
Short name T955
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.41 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:07:55 PM PST 23
Peak memory 245768 kb
Host smart-8603db0d-0d23-47ac-863b-f11b9c691b30
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102550210836016631629269016588452963911883742884933416903005664774211
38298713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.1025502108360166316292690165884529639118837428849334169
0300566477421138298713
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.30322514275796336139321951335578151797100446032233660466199313204728111929667
Short name T276
Test name
Test status
Simulation time 45083829570 ps
CPU time 562.47 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:17:04 PM PST 23
Peak memory 202856 kb
Host smart-f4e5a4ae-6573-40af-8792-f35c104c7c60
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303225142757963361393219513355781517971004460322336604661993132047281
11929667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access_b2b.30322514275796336139321951335578151797100
446032233660466199313204728111929667
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.81192753793892655224272644402494780125740403450963153649216175966865144232829
Short name T635
Test name
Test status
Simulation time 607542526 ps
CPU time 6.25 seconds
Started Nov 22 02:07:26 PM PST 23
Finished Nov 22 02:07:33 PM PST 23
Peak memory 203144 kb
Host smart-659a8520-bd9c-470a-a256-04c469a09651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81192753793892655224272644402494780125740403450963153649216175966865144232829 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.81192753793892655224272644402494780125740403450963153649216175966865144232829
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.13354317017420224409285386887133055062061748711906211399413125731182473615870
Short name T664
Test name
Test status
Simulation time 19913691647 ps
CPU time 525.96 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:16:24 PM PST 23
Peak memory 372572 kb
Host smart-f951413f-82ba-483a-8fb9-2aed5a8ca002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13354317017420224409285386887133055062061748711906211399413125731182473615870 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.13354317017420224409285386887133055062061748711906211399413125731182473615870
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.85897682959419541130346706608501654673341479460401171833431376666351335264765
Short name T942
Test name
Test status
Simulation time 988289480 ps
CPU time 17.23 seconds
Started Nov 22 02:07:37 PM PST 23
Finished Nov 22 02:07:56 PM PST 23
Peak memory 245480 kb
Host smart-2e8bcbf0-78fa-490b-91da-c413ecd5fe12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85897682959419541130346706608501654673341479460401171833431376666351335264765 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.85897682959419541130346706608501654673341479460401171833431376666351335264765
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.35865417501885320436376053190256772302916723705429979906486923567454798972139
Short name T614
Test name
Test status
Simulation time 624328106 ps
CPU time 1726.48 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:36:25 PM PST 23
Peak memory 498196 kb
Host smart-c0c6ceb2-577d-4da9-b012-3bc07e4a7b5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=35865417501885320436376053190256772302916723705429979906486923567454798972139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sra
m_ctrl_stress_all_with_rand_reset.35865417501885320436376053190256772302916723705429979906486923567454798972139
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2857311998563646903301929970316430515443928033074045545387733516550099513960
Short name T860
Test name
Test status
Simulation time 9325508496 ps
CPU time 418.77 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:14:37 PM PST 23
Peak memory 202880 kb
Host smart-402b8ef5-f0e5-44e1-b40f-6be22795f376
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857311998563646903301929970316430515443928033074045545387733516550099513960
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.28573119985636469033019299703164305154439280330740455
45387733516550099513960
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.106681548153619422267918595478159181602815068447625709651404535389973404531158
Short name T829
Test name
Test status
Simulation time 1371125703 ps
CPU time 130.52 seconds
Started Nov 22 02:07:33 PM PST 23
Finished Nov 22 02:09:45 PM PST 23
Peak memory 351180 kb
Host smart-6c1bb305-69da-41f1-b6f2-c958e71a0248
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106681548153619422267918595478159181602815068447625709
651404535389973404531158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.1066815481536194222679
18595478159181602815068447625709651404535389973404531158
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.80554517119117779950336760462864058390311212480092005929725901909156755005205
Short name T328
Test name
Test status
Simulation time 13467153934 ps
CPU time 1078.02 seconds
Started Nov 22 02:07:37 PM PST 23
Finished Nov 22 02:25:38 PM PST 23
Peak memory 378780 kb
Host smart-111b046b-a478-4ae6-aff4-532ae16c0685
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80554517119117779950336760462864058390311212480092005929725901909156755005205
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_key_req.8055451711911777995033676046286405839031
1212480092005929725901909156755005205
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.103117777682120731127160767191492593568299340030099959761419697659610657987301
Short name T465
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 02:07:37 PM PST 23
Finished Nov 22 02:07:40 PM PST 23
Peak memory 202492 kb
Host smart-0dee1587-6c3b-4dd2-9b73-9151ded54775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103117777682120731127160767191492593568299340030099959761419697659
610657987301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.103117777682120731127160767191492593568299340030099959
761419697659610657987301
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.80653019179698410878847121789814288910781857385770212367376496972816188216839
Short name T986
Test name
Test status
Simulation time 295482808505 ps
CPU time 2812.75 seconds
Started Nov 22 02:07:39 PM PST 23
Finished Nov 22 02:54:34 PM PST 23
Peak memory 202888 kb
Host smart-c7d57944-7f52-457d-9dfe-8776b8bb5a39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80653019179698410878847121789814288910781857385770212367376496972816188216839 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.80653019179698410878847121789814288910781857385770212367376496972816188216839
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.34703884317013749011097324182525146990707591105695545003967351423053957475247
Short name T224
Test name
Test status
Simulation time 31712811539 ps
CPU time 1206.89 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:27:45 PM PST 23
Peak memory 368056 kb
Host smart-3aa35fd0-2f10-4799-85ad-efe7e1bd03b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34703884317013749011097324182525146990707591105695545003967351423053957475247 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.34703884317013749011097324182525146990707591105695545003967351423053957475247
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.91254950241665991464675668583585965950767583698744623927800901769963777778683
Short name T287
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.32 seconds
Started Nov 22 02:07:24 PM PST 23
Finished Nov 22 02:09:10 PM PST 23
Peak memory 211068 kb
Host smart-195bcdf0-69ac-467d-8977-72901c17879d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91254950241665991464675668583585965950767583698744623927800901769963777778683 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.91254950241665991464675668583585965950767583698744623927800901769963777778683
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.61217523742951322401416630921632399718726622538522529410188349868183935006112
Short name T352
Test name
Test status
Simulation time 1342947357 ps
CPU time 137.56 seconds
Started Nov 22 02:07:39 PM PST 23
Finished Nov 22 02:09:59 PM PST 23
Peak memory 351092 kb
Host smart-8ebaca96-c058-4183-8858-7945a3a9e657
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6121752374295132240141663092163239971872662253852252941
0188349868183935006112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max_throughput.612175237429513224014166309216323997
18726622538522529410188349868183935006112
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.45536119367762557210849307372321160607238676808056940760740762619865276749404
Short name T891
Test name
Test status
Simulation time 4750777237 ps
CPU time 75.82 seconds
Started Nov 22 02:07:23 PM PST 23
Finished Nov 22 02:08:40 PM PST 23
Peak memory 212340 kb
Host smart-59ff30d8-cad8-4b8f-8878-304040b745bf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45536119367762557210849307372321160607238676808056940760740762619865
276749404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.4553611936776255721084930737232116060723867680805
6940760740762619865276749404
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.67843821570140716484230787818925369540354935821849187812431876746542162853995
Short name T952
Test name
Test status
Simulation time 18445453393 ps
CPU time 157.94 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:10:16 PM PST 23
Peak memory 202764 kb
Host smart-3eaee82f-fb09-4bc6-a3c7-3d62bea023b9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67843821570140716484230787818925369540354935821849187812431876746542162853995
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.67843821570140716484230787818925369540354935821849187812431876746542162853995
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.37753964046954261283273524911555402460253328344492159262321250681329923198753
Short name T241
Test name
Test status
Simulation time 28731174678 ps
CPU time 1087.78 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:25:45 PM PST 23
Peak memory 378620 kb
Host smart-0336d5c1-db27-4550-a9f0-7b033fa06649
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37753964046954261283273524911555402460253328344492159262321250681329923198753 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.37753964046954261283273524911555402460253328344492159262321250681329923198753
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.107726063779450903645603128660894891532453477091858776619378002812487360624737
Short name T835
Test name
Test status
Simulation time 1006378621 ps
CPU time 17.93 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:07:58 PM PST 23
Peak memory 245628 kb
Host smart-78f85178-ee90-4d76-951a-c8a28125ec66
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107726063779450903645603128660894891532453477091858776619378002812487
360624737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.107726063779450903645603128660894891532453477091858776
619378002812487360624737
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.110273451304064873710996005335786531066357471261188320984051256845104031901127
Short name T500
Test name
Test status
Simulation time 45083829570 ps
CPU time 576.99 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:17:14 PM PST 23
Peak memory 202812 kb
Host smart-ee39c6e6-e82f-41fd-a8db-5405d79198e1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110273451304064873710996005335786531066357471261188320984051256845104
031901127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access_b2b.1102734513040648737109960053357865310663
57471261188320984051256845104031901127
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.22750460037948897447172697665182002184666201687601630579879644737299558766466
Short name T539
Test name
Test status
Simulation time 607542526 ps
CPU time 6.26 seconds
Started Nov 22 02:07:23 PM PST 23
Finished Nov 22 02:07:30 PM PST 23
Peak memory 203096 kb
Host smart-c50bbd5e-23eb-4069-bec2-a7574355ca8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22750460037948897447172697665182002184666201687601630579879644737299558766466 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.22750460037948897447172697665182002184666201687601630579879644737299558766466
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.16856735281406054645348807017000601961323573657577744066211393274982138764524
Short name T712
Test name
Test status
Simulation time 19913691647 ps
CPU time 504.76 seconds
Started Nov 22 02:07:37 PM PST 23
Finished Nov 22 02:16:03 PM PST 23
Peak memory 372440 kb
Host smart-36bedb5c-ed20-4a06-baac-06ee3ae13171
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16856735281406054645348807017000601961323573657577744066211393274982138764524 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.16856735281406054645348807017000601961323573657577744066211393274982138764524
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.49274818990814182145567366411305697340028874606429047186414772665315503489400
Short name T423
Test name
Test status
Simulation time 988289480 ps
CPU time 17.56 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:07:56 PM PST 23
Peak memory 245664 kb
Host smart-5e138bba-57b1-4658-af3f-849df3f65fc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49274818990814182145567366411305697340028874606429047186414772665315503489400 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.49274818990814182145567366411305697340028874606429047186414772665315503489400
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.23942114466852152539118429011544036496898449487297745103727195104343435442920
Short name T312
Test name
Test status
Simulation time 624328106 ps
CPU time 1860.29 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:38:38 PM PST 23
Peak memory 498192 kb
Host smart-f262bbfc-7dad-4575-b6fd-de7a5efac3d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=23942114466852152539118429011544036496898449487297745103727195104343435442920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sra
m_ctrl_stress_all_with_rand_reset.23942114466852152539118429011544036496898449487297745103727195104343435442920
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.111923358358096233328857323004579321898655044287622959861171728884148908406997
Short name T989
Test name
Test status
Simulation time 9325508496 ps
CPU time 430.18 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:14:50 PM PST 23
Peak memory 202892 kb
Host smart-58dd6fb9-566e-468b-9642-c72bfdfeea49
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11192335835809623332885732300457932189865504428762295986117172888414890840699
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.111923358358096233328857323004579321898655044287622
959861171728884148908406997
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.85370606620458465883172396608660312553064483507858223226030590639402740600363
Short name T417
Test name
Test status
Simulation time 1371125703 ps
CPU time 103.98 seconds
Started Nov 22 02:07:35 PM PST 23
Finished Nov 22 02:09:22 PM PST 23
Peak memory 351192 kb
Host smart-4db7a01a-c46e-4911-9bd5-04a81325c39f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853706066204584658831723966086603125530644835078582232
26030590639402740600363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.85370606620458465883172
396608660312553064483507858223226030590639402740600363
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.64557439827211654479280264208085562666855043217713299780882554004478271845065
Short name T229
Test name
Test status
Simulation time 13467153934 ps
CPU time 782.09 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:20:42 PM PST 23
Peak memory 378664 kb
Host smart-6a1e6274-3730-4429-af77-2a7595bcddc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64557439827211654479280264208085562666855043217713299780882554004478271845065
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_key_req.6455743982721165447928026420808556266685
5043217713299780882554004478271845065
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.58868226841140420814303030061128741325886505847789086712827595799550602723971
Short name T569
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:07:39 PM PST 23
Finished Nov 22 02:07:42 PM PST 23
Peak memory 202432 kb
Host smart-3f33f0e5-da20-48ae-a78a-50829726ecf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588682268411404208143030300611287413258865058477890867128275957995
50602723971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.5886822684114042081430303006112874132588650584778908671
2827595799550602723971
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.110588816197534379543431587038314225551266690238346125881947750972371774572226
Short name T580
Test name
Test status
Simulation time 295482808505 ps
CPU time 2739.65 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:53:21 PM PST 23
Peak memory 202892 kb
Host smart-631f6880-b323-48cf-96fa-90ff34d79b47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110588816197534379543431587038314225551266690238346125881947750972371774572226 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.110588816197534379543431587038314225551266690238346125881947750972371774572226
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.49718127222531008794938160482443964698618156651165122610686419527224577096688
Short name T919
Test name
Test status
Simulation time 19084394710 ps
CPU time 104.73 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:09:27 PM PST 23
Peak memory 210972 kb
Host smart-14319f8d-49d4-4654-a77a-018bbbbd18fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49718127222531008794938160482443964698618156651165122610686419527224577096688 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.49718127222531008794938160482443964698618156651165122610686419527224577096688
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.60491345243873118829721253598950216596410034923990286611024069135258093169060
Short name T660
Test name
Test status
Simulation time 1342947357 ps
CPU time 124.02 seconds
Started Nov 22 02:07:42 PM PST 23
Finished Nov 22 02:09:47 PM PST 23
Peak memory 351116 kb
Host smart-47f23968-9858-4904-bcf9-f8ef3af1e32a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6049134524387311882972125359895021659641003492399028661
1024069135258093169060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max_throughput.604913452438731188297212535989502165
96410034923990286611024069135258093169060
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.68943269224889721396809569387695478344831068603136987543808251126803016447762
Short name T641
Test name
Test status
Simulation time 4750777237 ps
CPU time 73.78 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:08:56 PM PST 23
Peak memory 212252 kb
Host smart-f524d79d-bfac-4c5b-83da-87c89f66c842
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68943269224889721396809569387695478344831068603136987543808251126803
016447762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.6894326922488972139680956938769547834483106860313
6987543808251126803016447762
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.73905393019677193319027534263085933463403242322548875865214509110332891680581
Short name T804
Test name
Test status
Simulation time 18445453393 ps
CPU time 153.84 seconds
Started Nov 22 02:07:41 PM PST 23
Finished Nov 22 02:10:17 PM PST 23
Peak memory 202792 kb
Host smart-b5f9fab8-b4c8-4c32-afca-cdd064d56a4b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73905393019677193319027534263085933463403242322548875865214509110332891680581
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.73905393019677193319027534263085933463403242322548875865214509110332891680581
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.49437811064726166490889540056226098020410136422037098325286746641435106737580
Short name T867
Test name
Test status
Simulation time 28731174678 ps
CPU time 855.23 seconds
Started Nov 22 02:07:41 PM PST 23
Finished Nov 22 02:21:58 PM PST 23
Peak memory 378596 kb
Host smart-1c4fe386-2a03-42b6-8114-4353cf7c951b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49437811064726166490889540056226098020410136422037098325286746641435106737580 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.49437811064726166490889540056226098020410136422037098325286746641435106737580
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.26907112141761533076842496653985896466865168388208385831067226835046170405673
Short name T726
Test name
Test status
Simulation time 1006378621 ps
CPU time 18.82 seconds
Started Nov 22 02:07:39 PM PST 23
Finished Nov 22 02:08:00 PM PST 23
Peak memory 245604 kb
Host smart-6c03757d-bfd3-4569-a1cd-a7d196309a7c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269071121417615330768424966539858964668651683882083858310672268350461
70405673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.2690711214176153307684249665398589646686516838820838583
1067226835046170405673
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.15872728761108321294140322603314761871442902031063939080993452645648657163751
Short name T301
Test name
Test status
Simulation time 45083829570 ps
CPU time 579.04 seconds
Started Nov 22 02:07:41 PM PST 23
Finished Nov 22 02:17:22 PM PST 23
Peak memory 202848 kb
Host smart-963c4fa0-52fe-4f19-99b1-4fca4d299bce
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158727287611083212941403226033147618714429020310639390809934526456486
57163751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access_b2b.15872728761108321294140322603314761871442
902031063939080993452645648657163751
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.107455684456372683761354706811648322859688661890272983608068990292835805242104
Short name T692
Test name
Test status
Simulation time 607542526 ps
CPU time 6.17 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:07:48 PM PST 23
Peak memory 203104 kb
Host smart-1a8bf309-bf99-4aca-aab9-b471e4faefb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107455684456372683761354706811648322859688661890272983608068990292835805242104 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.107455684456372683761354706811648322859688661890272983608068990292835805242104
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.35083582902593981736161477598249890810051085796491287924269636194772554881258
Short name T685
Test name
Test status
Simulation time 19913691647 ps
CPU time 536.92 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:16:39 PM PST 23
Peak memory 372600 kb
Host smart-4b713beb-a02d-4aeb-ad77-fc85ab0be35a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35083582902593981736161477598249890810051085796491287924269636194772554881258 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.35083582902593981736161477598249890810051085796491287924269636194772554881258
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.24057397384362640996312320591079873172944216252875204398778786823304368887383
Short name T428
Test name
Test status
Simulation time 988289480 ps
CPU time 18.14 seconds
Started Nov 22 02:07:36 PM PST 23
Finished Nov 22 02:07:56 PM PST 23
Peak memory 245604 kb
Host smart-16f875f6-1eae-4694-a622-3e5c00199262
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057397384362640996312320591079873172944216252875204398778786823304368887383 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.24057397384362640996312320591079873172944216252875204398778786823304368887383
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.11186575957337992417559818269987989479723419728397937844005088649060051286094
Short name T675
Test name
Test status
Simulation time 624328106 ps
CPU time 1736.5 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:36:38 PM PST 23
Peak memory 498256 kb
Host smart-8c2b6d44-775a-4fa1-9bca-565502eac391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=11186575957337992417559818269987989479723419728397937844005088649060051286094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sra
m_ctrl_stress_all_with_rand_reset.11186575957337992417559818269987989479723419728397937844005088649060051286094
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.78390510014279599467128156663048627367535654878486394548239254163431849791171
Short name T235
Test name
Test status
Simulation time 9325508496 ps
CPU time 414.47 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:14:35 PM PST 23
Peak memory 202828 kb
Host smart-ce28907d-6bbb-45c8-9d67-a92182d015d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78390510014279599467128156663048627367535654878486394548239254163431849791171
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.7839051001427959946712815666304862736753565487848639
4548239254163431849791171
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.82679850675700304010031660038021365963759141586672492314969135232950789164965
Short name T216
Test name
Test status
Simulation time 1371125703 ps
CPU time 112.61 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:09:33 PM PST 23
Peak memory 351208 kb
Host smart-aeb01e93-0069-4ab5-ab42-b0ef8874f997
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826798506757003040100316600380213659637591415866724923
14969135232950789164965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.82679850675700304010031
660038021365963759141586672492314969135232950789164965
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.99939464111403080113419014884989131292834851244718533631100589569792513913984
Short name T652
Test name
Test status
Simulation time 13467153934 ps
CPU time 1016.38 seconds
Started Nov 22 02:07:34 PM PST 23
Finished Nov 22 02:24:33 PM PST 23
Peak memory 378772 kb
Host smart-ee773812-b9e5-46cc-9ba3-0e9004842028
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99939464111403080113419014884989131292834851244718533631100589569792513913984
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_key_req.9993946411140308011341901488498913129283
4851244718533631100589569792513913984
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.107021559134521326914093253985917695878937632483501998550102514952374875516480
Short name T425
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:07:41 PM PST 23
Peak memory 202572 kb
Host smart-6203ac0d-11c2-4f1f-8f29-dc2a9a01c361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107021559134521326914093253985917695878937632483501998550102514952
374875516480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.107021559134521326914093253985917695878937632483501998
550102514952374875516480
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.106162974465322553943267040471880687709510015802976279838745609335064059623706
Short name T908
Test name
Test status
Simulation time 295482808505 ps
CPU time 2661.91 seconds
Started Nov 22 02:07:41 PM PST 23
Finished Nov 22 02:52:05 PM PST 23
Peak memory 202784 kb
Host smart-e6a15fa3-3464-4bb1-b90a-caf7edd5f3f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106162974465322553943267040471880687709510015802976279838745609335064059623706 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.106162974465322553943267040471880687709510015802976279838745609335064059623706
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.84656631706031949332650161683363264379777477520476938178189582940856530936391
Short name T372
Test name
Test status
Simulation time 31712811539 ps
CPU time 730.89 seconds
Started Nov 22 02:07:41 PM PST 23
Finished Nov 22 02:19:53 PM PST 23
Peak memory 368040 kb
Host smart-4579f4f5-a018-4212-bfee-8e0a92512651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84656631706031949332650161683363264379777477520476938178189582940856530936391 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.84656631706031949332650161683363264379777477520476938178189582940856530936391
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.48828288761404446478051592908007224188191042739184545928698125269898885023426
Short name T661
Test name
Test status
Simulation time 19084394710 ps
CPU time 105.07 seconds
Started Nov 22 02:07:33 PM PST 23
Finished Nov 22 02:09:19 PM PST 23
Peak memory 211036 kb
Host smart-5017e313-237b-4769-a8be-cf45e7dd8ffe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48828288761404446478051592908007224188191042739184545928698125269898885023426 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.48828288761404446478051592908007224188191042739184545928698125269898885023426
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.63201650053887317123639725312807564955655432599834499600336355940846780273742
Short name T611
Test name
Test status
Simulation time 1342947357 ps
CPU time 112.09 seconds
Started Nov 22 02:07:45 PM PST 23
Finished Nov 22 02:09:37 PM PST 23
Peak memory 351188 kb
Host smart-a45168e2-a132-4943-b5b0-3355cdf741be
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6320165005388731712363972531280756495565543259983449960
0336355940846780273742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max_throughput.632016500538873171236397253128075649
55655432599834499600336355940846780273742
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.43709487604813468034780113281576947316344043413179523001524247471378435113247
Short name T973
Test name
Test status
Simulation time 4750777237 ps
CPU time 78.54 seconds
Started Nov 22 02:07:39 PM PST 23
Finished Nov 22 02:09:00 PM PST 23
Peak memory 212288 kb
Host smart-076dd2b8-1ea7-4763-abd1-7db18e1b98c0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43709487604813468034780113281576947316344043413179523001524247471378
435113247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.4370948760481346803478011328157694731634404341317
9523001524247471378435113247
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.74387499023917631561761947029301335891050939120758801768215378658433542102011
Short name T402
Test name
Test status
Simulation time 18445453393 ps
CPU time 156.54 seconds
Started Nov 22 02:07:42 PM PST 23
Finished Nov 22 02:10:20 PM PST 23
Peak memory 202756 kb
Host smart-e40af5bb-239a-4627-8f99-249320934f2e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74387499023917631561761947029301335891050939120758801768215378658433542102011
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.74387499023917631561761947029301335891050939120758801768215378658433542102011
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.69206360245227235123579508156949936616673429802657122883581764522811840558499
Short name T749
Test name
Test status
Simulation time 28731174678 ps
CPU time 748.02 seconds
Started Nov 22 02:07:42 PM PST 23
Finished Nov 22 02:20:12 PM PST 23
Peak memory 378564 kb
Host smart-1e50005d-d85b-44b5-9f71-2ffa57d644b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69206360245227235123579508156949936616673429802657122883581764522811840558499 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.69206360245227235123579508156949936616673429802657122883581764522811840558499
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.92883366273055736551786963827548085496065485475613441385851584863629509636727
Short name T790
Test name
Test status
Simulation time 1006378621 ps
CPU time 19.26 seconds
Started Nov 22 02:07:43 PM PST 23
Finished Nov 22 02:08:03 PM PST 23
Peak memory 245728 kb
Host smart-a8a1af23-cffe-4938-b38f-46e6594fdc5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928833662730557365517869638275480854960654854756134413858515848636295
09636727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.9288336627305573655178696382754808549606548547561344138
5851584863629509636727
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.76998529219532656419025408170431130945961905598149045809808715766775050171766
Short name T296
Test name
Test status
Simulation time 45083829570 ps
CPU time 584.77 seconds
Started Nov 22 02:07:45 PM PST 23
Finished Nov 22 02:17:31 PM PST 23
Peak memory 202868 kb
Host smart-9857faf7-ac3d-4c54-86b2-2bba887dd8f6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769985292195326564190254081704311309459619055981490458098087157667750
50171766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access_b2b.76998529219532656419025408170431130945961
905598149045809808715766775050171766
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.35178251220130458365693986129317196602541927516718996865908960882249439334565
Short name T345
Test name
Test status
Simulation time 607542526 ps
CPU time 6.01 seconds
Started Nov 22 02:07:34 PM PST 23
Finished Nov 22 02:07:43 PM PST 23
Peak memory 203108 kb
Host smart-2535ef5b-0ede-4754-83a2-df3adcedd818
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35178251220130458365693986129317196602541927516718996865908960882249439334565 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.35178251220130458365693986129317196602541927516718996865908960882249439334565
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.63613966651725075347927428427625827333870372824522713616653838992611344626684
Short name T460
Test name
Test status
Simulation time 19913691647 ps
CPU time 640.8 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:18:22 PM PST 23
Peak memory 372512 kb
Host smart-df7f9dfb-1cfc-4479-aec8-0de658b37a4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63613966651725075347927428427625827333870372824522713616653838992611344626684 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.63613966651725075347927428427625827333870372824522713616653838992611344626684
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.69447544078274979803609783971991648896250584342837855026990414537026897415584
Short name T719
Test name
Test status
Simulation time 988289480 ps
CPU time 17.71 seconds
Started Nov 22 02:07:42 PM PST 23
Finished Nov 22 02:08:02 PM PST 23
Peak memory 245484 kb
Host smart-fedc44fa-e9a5-4b88-bde7-36ff4b979417
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69447544078274979803609783971991648896250584342837855026990414537026897415584 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.69447544078274979803609783971991648896250584342837855026990414537026897415584
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.40024797387935235223021140138397670723697742919450088490983982907599114694681
Short name T900
Test name
Test status
Simulation time 624328106 ps
CPU time 1929.11 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:39:50 PM PST 23
Peak memory 498100 kb
Host smart-b0e3136f-6e10-4fbb-abf9-a2be7ea98b9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=40024797387935235223021140138397670723697742919450088490983982907599114694681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sra
m_ctrl_stress_all_with_rand_reset.40024797387935235223021140138397670723697742919450088490983982907599114694681
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.41715627464580945268088517399409070983093463365156512661940723560636067979259
Short name T493
Test name
Test status
Simulation time 9325508496 ps
CPU time 408.38 seconds
Started Nov 22 02:07:40 PM PST 23
Finished Nov 22 02:14:30 PM PST 23
Peak memory 202820 kb
Host smart-0c6d7f38-2714-45ba-9470-9d67af3c8efd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41715627464580945268088517399409070983093463365156512661940723560636067979259
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.4171562746458094526808851739940907098309346336515651
2661940723560636067979259
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.79727569459398508121987715344607116486629117696046918641472234718164675511243
Short name T270
Test name
Test status
Simulation time 1371125703 ps
CPU time 102.67 seconds
Started Nov 22 02:07:38 PM PST 23
Finished Nov 22 02:09:23 PM PST 23
Peak memory 351204 kb
Host smart-da8043c4-51d5-401d-a93d-b2eedaa9ee8a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797275694593985081219877153446071164866291176960469186
41472234718164675511243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.79727569459398508121987
715344607116486629117696046918641472234718164675511243
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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