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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.76 100.00 97.98 99.15 100.00 99.71 99.70 94.75


Total test records in report: 990
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T505 /workspace/coverage/default/38.sram_ctrl_executable.72084163875470856898064728419751495286333367190841305246749749348384032623593 Nov 22 02:15:47 PM PST 23 Nov 22 02:29:12 PM PST 23 31712811539 ps
T506 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.109107868646612364844910763729269436320529295076598876184620902407870757465634 Nov 22 02:12:53 PM PST 23 Nov 22 02:41:40 PM PST 23 624328106 ps
T507 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.63876671114010302730337387881594155563683167269132519333392668586837317898956 Nov 22 02:11:16 PM PST 23 Nov 22 02:18:21 PM PST 23 9325508496 ps
T508 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.45300542004848483107714264862310996003520060989240096293365018819707382032655 Nov 22 02:13:16 PM PST 23 Nov 22 02:31:45 PM PST 23 13467153934 ps
T509 /workspace/coverage/default/24.sram_ctrl_max_throughput.43422598264552219197252824198045238425661466275795939094855708537789576397420 Nov 22 02:13:51 PM PST 23 Nov 22 02:15:57 PM PST 23 1342947357 ps
T510 /workspace/coverage/default/5.sram_ctrl_max_throughput.87180035477830084964338814972079665862590378776554254783759911963579368773718 Nov 22 02:07:25 PM PST 23 Nov 22 02:09:24 PM PST 23 1342947357 ps
T511 /workspace/coverage/default/19.sram_ctrl_multiple_keys.113785817895634857736813058919558253354553865166435367511141612116699158819547 Nov 22 02:12:19 PM PST 23 Nov 22 02:28:12 PM PST 23 28731174678 ps
T512 /workspace/coverage/default/18.sram_ctrl_ram_cfg.94381856655303101560505734898047770691233103500797858422532853340380472035463 Nov 22 02:12:21 PM PST 23 Nov 22 02:12:28 PM PST 23 607542526 ps
T513 /workspace/coverage/default/29.sram_ctrl_multiple_keys.2342544793525473240990331617739839227778934531659200880022252094697387980274 Nov 22 02:14:35 PM PST 23 Nov 22 02:28:28 PM PST 23 28731174678 ps
T514 /workspace/coverage/default/31.sram_ctrl_max_throughput.54639721877920763931091341101987609299924503841113766544928541185093510457101 Nov 22 02:14:42 PM PST 23 Nov 22 02:16:41 PM PST 23 1342947357 ps
T515 /workspace/coverage/default/30.sram_ctrl_lc_escalation.23900762091601072627094313169769567068177579881404002573822431497939340006611 Nov 22 02:14:35 PM PST 23 Nov 22 02:16:21 PM PST 23 19084394710 ps
T516 /workspace/coverage/default/20.sram_ctrl_executable.85363066048326301784789382061960063199987850837889198856006753302135514450941 Nov 22 02:12:32 PM PST 23 Nov 22 02:26:55 PM PST 23 31712811539 ps
T517 /workspace/coverage/default/44.sram_ctrl_regwen.28766242378867504035591456851740980803989163576831979194442836504280771110052 Nov 22 02:16:30 PM PST 23 Nov 22 02:25:30 PM PST 23 19913691647 ps
T518 /workspace/coverage/default/3.sram_ctrl_mem_walk.40698455516425713392716288399395747894667195212657273010290880413125004291911 Nov 22 02:07:20 PM PST 23 Nov 22 02:10:04 PM PST 23 18445453393 ps
T519 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.19328237840184942201790055183128751134008240216242445550563566742584880626374 Nov 22 02:16:29 PM PST 23 Nov 22 02:29:26 PM PST 23 13467153934 ps
T520 /workspace/coverage/default/13.sram_ctrl_max_throughput.8561102205623849734430862651063193566483682170986383036830440878285300564020 Nov 22 02:11:17 PM PST 23 Nov 22 02:13:01 PM PST 23 1342947357 ps
T521 /workspace/coverage/default/0.sram_ctrl_regwen.107297785454567685038307186258119697339366234560768921711455021964528067944913 Nov 22 02:07:23 PM PST 23 Nov 22 02:16:29 PM PST 23 19913691647 ps
T522 /workspace/coverage/default/46.sram_ctrl_partial_access.21081992262738602977289610060099171952648638136795500546091632948281800580861 Nov 22 02:17:06 PM PST 23 Nov 22 02:17:31 PM PST 23 1006378621 ps
T523 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.66779462821097208800694726783957806909832144979360577696364894981957680547016 Nov 22 02:13:01 PM PST 23 Nov 22 02:44:26 PM PST 23 624328106 ps
T524 /workspace/coverage/default/11.sram_ctrl_mem_walk.113358069922254369363955964460283425350072815025673393060721049060599403786989 Nov 22 02:11:17 PM PST 23 Nov 22 02:14:04 PM PST 23 18445453393 ps
T525 /workspace/coverage/default/25.sram_ctrl_mem_walk.3787605747663566589653501336423557669704648376062180293613486594139466630314 Nov 22 02:13:53 PM PST 23 Nov 22 02:16:29 PM PST 23 18445453393 ps
T526 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.92297796798872436447988990897439193602217678520393545007065640586490984709178 Nov 22 02:11:16 PM PST 23 Nov 22 02:38:57 PM PST 23 624328106 ps
T527 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.30663530816260711234860790461112851246668083223002720215699564777756787117923 Nov 22 02:14:41 PM PST 23 Nov 22 02:29:40 PM PST 23 13467153934 ps
T528 /workspace/coverage/default/26.sram_ctrl_multiple_keys.68130848788928886928546010829478924491658255496206760688048741083185055707381 Nov 22 02:13:54 PM PST 23 Nov 22 02:26:37 PM PST 23 28731174678 ps
T529 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.208257571154743917110747055135652531899129976197213189126403169656009712425 Nov 22 02:14:59 PM PST 23 Nov 22 02:16:21 PM PST 23 4750777237 ps
T530 /workspace/coverage/default/23.sram_ctrl_partial_access.83600253138806848663026411176868948544752890812342804393257793126116297235181 Nov 22 02:13:14 PM PST 23 Nov 22 02:13:34 PM PST 23 1006378621 ps
T531 /workspace/coverage/default/40.sram_ctrl_regwen.33671592663780506484187779661683428052119130143215088926596109679151155631807 Nov 22 02:16:17 PM PST 23 Nov 22 02:25:02 PM PST 23 19913691647 ps
T532 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.59015011173049538936240159346923575589672958507370985891103977813337040319831 Nov 22 02:15:47 PM PST 23 Nov 22 02:25:28 PM PST 23 45083829570 ps
T533 /workspace/coverage/default/18.sram_ctrl_max_throughput.66752410564357833543903843467688781678702079569266988927211629705917381883336 Nov 22 02:12:18 PM PST 23 Nov 22 02:14:27 PM PST 23 1342947357 ps
T534 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.102368997976555376267361705160721654908356934926699138980328839964676696513767 Nov 22 02:15:33 PM PST 23 Nov 22 02:50:03 PM PST 23 624328106 ps
T535 /workspace/coverage/default/25.sram_ctrl_max_throughput.82542735823679971968124154923093732584354056901400777369656096718520420624167 Nov 22 02:13:56 PM PST 23 Nov 22 02:15:51 PM PST 23 1342947357 ps
T536 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.81817349645573421206024420298262545856333806326504897595070196359659190142030 Nov 22 02:16:29 PM PST 23 Nov 22 02:23:33 PM PST 23 9325508496 ps
T537 /workspace/coverage/default/5.sram_ctrl_smoke.8956970619679677708599784527456026146613907139684334030281938822954967523131 Nov 22 02:07:36 PM PST 23 Nov 22 02:07:56 PM PST 23 988289480 ps
T538 /workspace/coverage/default/38.sram_ctrl_alert_test.86580180762063962361962053069156801817757226393996422296676863535951323950741 Nov 22 02:16:36 PM PST 23 Nov 22 02:16:37 PM PST 23 16600825 ps
T539 /workspace/coverage/default/7.sram_ctrl_ram_cfg.22750460037948897447172697665182002184666201687601630579879644737299558766466 Nov 22 02:07:23 PM PST 23 Nov 22 02:07:30 PM PST 23 607542526 ps
T540 /workspace/coverage/default/11.sram_ctrl_smoke.89670178055763676321883738736013322575073595869931205174563048315926115777305 Nov 22 02:07:43 PM PST 23 Nov 22 02:08:03 PM PST 23 988289480 ps
T25 /workspace/coverage/default/0.sram_ctrl_sec_cm.84423835779181357535424951568718653075447971542744866599249987674449978198657 Nov 22 02:07:19 PM PST 23 Nov 22 02:07:23 PM PST 23 216402798 ps
T541 /workspace/coverage/default/28.sram_ctrl_mem_walk.43445554546756780472162189314871689616694950558740811654575175739403566550351 Nov 22 02:14:15 PM PST 23 Nov 22 02:16:53 PM PST 23 18445453393 ps
T542 /workspace/coverage/default/13.sram_ctrl_regwen.32420283149322171653664428401156253841442633912899655379807728212429412885575 Nov 22 02:11:19 PM PST 23 Nov 22 02:20:16 PM PST 23 19913691647 ps
T543 /workspace/coverage/default/31.sram_ctrl_ram_cfg.5132577693921704554858969659936640286172202273452657926601937897752281658070 Nov 22 02:14:53 PM PST 23 Nov 22 02:15:04 PM PST 23 607542526 ps
T544 /workspace/coverage/default/17.sram_ctrl_smoke.31377705510593371987571525973129561643318701721527740271834935700920167889489 Nov 22 02:12:02 PM PST 23 Nov 22 02:12:20 PM PST 23 988289480 ps
T545 /workspace/coverage/default/48.sram_ctrl_bijection.89811061634449675443139165128447771184483183587815725400730601054482132890114 Nov 22 02:17:17 PM PST 23 Nov 22 03:03:59 PM PST 23 295482808505 ps
T546 /workspace/coverage/default/43.sram_ctrl_mem_walk.13909226387064132200367668789459834270552476160863614668812986645290148322329 Nov 22 02:16:31 PM PST 23 Nov 22 02:19:11 PM PST 23 18445453393 ps
T547 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.78295387342906768555146807273939534448140297905591086790721603898014902142558 Nov 22 02:07:40 PM PST 23 Nov 22 02:24:14 PM PST 23 13467153934 ps
T548 /workspace/coverage/default/32.sram_ctrl_regwen.63332981488535464755475405332662832742463545729576834721013374549532047177196 Nov 22 02:14:55 PM PST 23 Nov 22 02:24:37 PM PST 23 19913691647 ps
T549 /workspace/coverage/default/4.sram_ctrl_mem_walk.86559821670723081194281807155427630786073954644061637225324375654696814914974 Nov 22 02:07:20 PM PST 23 Nov 22 02:09:57 PM PST 23 18445453393 ps
T550 /workspace/coverage/default/19.sram_ctrl_alert_test.39481370189828629188896668598739101327862579460391290613931920115007515374009 Nov 22 02:12:48 PM PST 23 Nov 22 02:12:49 PM PST 23 16600825 ps
T551 /workspace/coverage/default/14.sram_ctrl_max_throughput.2004531777933684782330822211369183975811376453689667297314477522701219094616 Nov 22 02:11:27 PM PST 23 Nov 22 02:13:30 PM PST 23 1342947357 ps
T552 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.107152840507035618865148839583928174571245360355104590656041417639827502608780 Nov 22 02:17:41 PM PST 23 Nov 22 02:19:00 PM PST 23 4750777237 ps
T553 /workspace/coverage/default/19.sram_ctrl_bijection.7488803540532577937460679299969233099995371334751721410288304089866089043687 Nov 22 02:12:34 PM PST 23 Nov 22 02:59:32 PM PST 23 295482808505 ps
T554 /workspace/coverage/default/18.sram_ctrl_mem_walk.41449909161355230882121405665017221315236279220240264034032780773373610327769 Nov 22 02:12:53 PM PST 23 Nov 22 02:15:34 PM PST 23 18445453393 ps
T555 /workspace/coverage/default/0.sram_ctrl_smoke.97672599528330236192942045119989877698878615016547966009305707559228181242001 Nov 22 02:07:20 PM PST 23 Nov 22 02:07:40 PM PST 23 988289480 ps
T556 /workspace/coverage/default/37.sram_ctrl_ram_cfg.78463973383072057189214075432218576056975208160017616562191973177016033658088 Nov 22 02:16:40 PM PST 23 Nov 22 02:16:47 PM PST 23 607542526 ps
T557 /workspace/coverage/default/14.sram_ctrl_regwen.35510907709521384062067732414387727522505459133560525432189440763208088507929 Nov 22 02:11:28 PM PST 23 Nov 22 02:21:01 PM PST 23 19913691647 ps
T558 /workspace/coverage/default/20.sram_ctrl_alert_test.81038312005076686062904662127424311099887466279261974599003092754770193948802 Nov 22 02:13:00 PM PST 23 Nov 22 02:13:01 PM PST 23 16600825 ps
T559 /workspace/coverage/default/30.sram_ctrl_multiple_keys.95830961083777633588520763343990317676757341197748257529835357487919787394459 Nov 22 02:14:42 PM PST 23 Nov 22 02:28:01 PM PST 23 28731174678 ps
T560 /workspace/coverage/default/42.sram_ctrl_partial_access.38700000725089547732228726924581501624056841887228594812372592300899275568205 Nov 22 02:16:16 PM PST 23 Nov 22 02:16:34 PM PST 23 1006378621 ps
T561 /workspace/coverage/default/5.sram_ctrl_mem_walk.41407746302284660528217387702065578912362682412930551864894188718835805025625 Nov 22 02:07:36 PM PST 23 Nov 22 02:10:24 PM PST 23 18445453393 ps
T562 /workspace/coverage/default/18.sram_ctrl_executable.6108544153117086010118348244899762563141001846304611105988222024043734546849 Nov 22 02:12:33 PM PST 23 Nov 22 02:27:27 PM PST 23 31712811539 ps
T563 /workspace/coverage/default/38.sram_ctrl_smoke.81668904463587375157435643687697582545863517586637447336894144303543512038504 Nov 22 02:16:36 PM PST 23 Nov 22 02:16:54 PM PST 23 988289480 ps
T564 /workspace/coverage/default/5.sram_ctrl_ram_cfg.54713373240759441902078367458752323423257830798342892552236353391454838761691 Nov 22 02:07:22 PM PST 23 Nov 22 02:07:30 PM PST 23 607542526 ps
T565 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.41953776197155724946430497963750665750240538822234664464651326112983930614787 Nov 22 02:12:49 PM PST 23 Nov 22 02:29:51 PM PST 23 13467153934 ps
T566 /workspace/coverage/default/37.sram_ctrl_bijection.44602356180633733702285494857334330019584774211446421271486108674811050564124 Nov 22 02:15:40 PM PST 23 Nov 22 02:58:57 PM PST 23 295482808505 ps
T567 /workspace/coverage/default/10.sram_ctrl_regwen.16698653681883382364484455777460293154610756022955893569678272473688855478200 Nov 22 02:07:40 PM PST 23 Nov 22 02:17:22 PM PST 23 19913691647 ps
T568 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3966901297996731689350867286084208421775509841119222539361240825291728535947 Nov 22 02:14:10 PM PST 23 Nov 22 02:23:56 PM PST 23 45083829570 ps
T569 /workspace/coverage/default/8.sram_ctrl_alert_test.58868226841140420814303030061128741325886505847789086712827595799550602723971 Nov 22 02:07:39 PM PST 23 Nov 22 02:07:42 PM PST 23 16600825 ps
T570 /workspace/coverage/default/35.sram_ctrl_partial_access.1316076884956611263430846668369433890294609719524604101586594594677916100422 Nov 22 02:15:10 PM PST 23 Nov 22 02:15:29 PM PST 23 1006378621 ps
T571 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.14234033645597402799100310123012769508515924949764897004684959542983080546663 Nov 22 02:17:33 PM PST 23 Nov 22 02:24:21 PM PST 23 9325508496 ps
T572 /workspace/coverage/default/31.sram_ctrl_bijection.103506454577100922044262633299046514714018634711262633636512367208224399957738 Nov 22 02:14:42 PM PST 23 Nov 22 03:00:05 PM PST 23 295482808505 ps
T573 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.5706782459546526096897190274077471077833478831086848447494360801591444830491 Nov 22 02:11:34 PM PST 23 Nov 22 02:21:17 PM PST 23 45083829570 ps
T574 /workspace/coverage/default/21.sram_ctrl_regwen.30218398886526219127427501308770666935269123411816508797937106938723464036315 Nov 22 02:13:00 PM PST 23 Nov 22 02:22:49 PM PST 23 19913691647 ps
T575 /workspace/coverage/default/11.sram_ctrl_bijection.94567558145300147761921332221055391419187896041212940157421527266307624918430 Nov 22 02:07:39 PM PST 23 Nov 22 02:51:43 PM PST 23 295482808505 ps
T576 /workspace/coverage/default/20.sram_ctrl_multiple_keys.20402959751433360530044875468736197282173733133224801406507280190660384319092 Nov 22 02:12:33 PM PST 23 Nov 22 02:27:16 PM PST 23 28731174678 ps
T577 /workspace/coverage/default/3.sram_ctrl_regwen.83352148008405772788647614666266808105000387953342324801092549584318765469181 Nov 22 02:07:19 PM PST 23 Nov 22 02:15:52 PM PST 23 19913691647 ps
T578 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.45354731109821598571378094607771769872629069219167841505177482596015180688590 Nov 22 02:17:03 PM PST 23 Nov 22 02:18:52 PM PST 23 1371125703 ps
T579 /workspace/coverage/default/11.sram_ctrl_partial_access.76563944905194740929275334525420659083036828293580270629282502547220811481142 Nov 22 02:07:43 PM PST 23 Nov 22 02:08:03 PM PST 23 1006378621 ps
T580 /workspace/coverage/default/8.sram_ctrl_bijection.110588816197534379543431587038314225551266690238346125881947750972371774572226 Nov 22 02:07:38 PM PST 23 Nov 22 02:53:21 PM PST 23 295482808505 ps
T581 /workspace/coverage/default/19.sram_ctrl_regwen.110683447596910266133685514971535421813563860031818983920630544968903923575475 Nov 22 02:12:51 PM PST 23 Nov 22 02:22:23 PM PST 23 19913691647 ps
T582 /workspace/coverage/default/48.sram_ctrl_multiple_keys.40011869501420242255201735992675675110751763521243586244222704019541139234577 Nov 22 02:16:52 PM PST 23 Nov 22 02:31:29 PM PST 23 28731174678 ps
T583 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.40029441951695429704949316490693307756025349476479444668324150011205978858512 Nov 22 02:16:40 PM PST 23 Nov 22 02:18:00 PM PST 23 4750777237 ps
T584 /workspace/coverage/default/43.sram_ctrl_regwen.106547785855157451305923607429301661716403521612485981403791946861733663828933 Nov 22 02:16:33 PM PST 23 Nov 22 02:25:29 PM PST 23 19913691647 ps
T585 /workspace/coverage/default/13.sram_ctrl_executable.114588513386423180282663990401324484932130176186593739206631566854726767328374 Nov 22 02:11:20 PM PST 23 Nov 22 02:25:40 PM PST 23 31712811539 ps
T586 /workspace/coverage/default/30.sram_ctrl_partial_access.72747090408770576403556619829429744086609726464372932489801420852096345188772 Nov 22 02:14:42 PM PST 23 Nov 22 02:15:02 PM PST 23 1006378621 ps
T587 /workspace/coverage/default/48.sram_ctrl_smoke.69099818452968902168928869380570811139665720143796435244220711294208203827906 Nov 22 02:17:02 PM PST 23 Nov 22 02:17:21 PM PST 23 988289480 ps
T588 /workspace/coverage/default/0.sram_ctrl_multiple_keys.103813192958839404615839212678928050024085286358311912008590536902985794078392 Nov 22 02:07:04 PM PST 23 Nov 22 02:20:06 PM PST 23 28731174678 ps
T589 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.48011374824075938714111374739357047895004338311964244052673223575895809149199 Nov 22 02:07:38 PM PST 23 Nov 22 02:08:59 PM PST 23 4750777237 ps
T590 /workspace/coverage/default/26.sram_ctrl_ram_cfg.90064635712808067412079882097767192872270137362768380461657575604886466813141 Nov 22 02:13:56 PM PST 23 Nov 22 02:14:03 PM PST 23 607542526 ps
T591 /workspace/coverage/default/22.sram_ctrl_max_throughput.34048450681017480580066035426612861224344785977502090976074876426973209628910 Nov 22 02:13:13 PM PST 23 Nov 22 02:15:25 PM PST 23 1342947357 ps
T592 /workspace/coverage/default/39.sram_ctrl_smoke.94261125006198334714919928581322008179434518021362837208571967467889195724864 Nov 22 02:16:18 PM PST 23 Nov 22 02:16:35 PM PST 23 988289480 ps
T593 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.84780865084192019883012583638088589753961438307488715880844004994238214197599 Nov 22 02:11:27 PM PST 23 Nov 22 02:18:25 PM PST 23 9325508496 ps
T594 /workspace/coverage/default/39.sram_ctrl_max_throughput.98548593667592119031598439451159085611166679020696862644940852675680934829415 Nov 22 02:16:16 PM PST 23 Nov 22 02:18:18 PM PST 23 1342947357 ps
T595 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.114933525505018457542553349484964217492102511163555677704625760087811960908481 Nov 22 02:14:15 PM PST 23 Nov 22 02:16:00 PM PST 23 1371125703 ps
T596 /workspace/coverage/default/32.sram_ctrl_multiple_keys.62037127939656897368483590963527459053822183206883319789448221820189553179654 Nov 22 02:15:27 PM PST 23 Nov 22 02:27:55 PM PST 23 28731174678 ps
T597 /workspace/coverage/default/28.sram_ctrl_ram_cfg.38992787188562896944100470688980070434798143572461016918544391810603204104673 Nov 22 02:14:12 PM PST 23 Nov 22 02:14:19 PM PST 23 607542526 ps
T26 /workspace/coverage/default/1.sram_ctrl_sec_cm.78697229452657256874857329639802786284763244256602691738185079493550208149396 Nov 22 02:07:05 PM PST 23 Nov 22 02:07:13 PM PST 23 216402798 ps
T598 /workspace/coverage/default/33.sram_ctrl_executable.72399948868073070571392281425960498559490103984047570242469233691345140907695 Nov 22 02:15:30 PM PST 23 Nov 22 02:30:08 PM PST 23 31712811539 ps
T599 /workspace/coverage/default/37.sram_ctrl_executable.54432305805330321039037673629734240891761093911063908735109865126806274007877 Nov 22 02:15:57 PM PST 23 Nov 22 02:28:30 PM PST 23 31712811539 ps
T600 /workspace/coverage/default/14.sram_ctrl_lc_escalation.4590356316745180477694680870202857654060134108769071485927132325883624928166 Nov 22 02:11:27 PM PST 23 Nov 22 02:13:12 PM PST 23 19084394710 ps
T601 /workspace/coverage/default/26.sram_ctrl_lc_escalation.67329332952058922945642249174726527429766224749108391727788495556164746876486 Nov 22 02:13:56 PM PST 23 Nov 22 02:15:45 PM PST 23 19084394710 ps
T602 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.87562193688731191266452594972679877883308362802923228622927635956730978539137 Nov 22 02:15:29 PM PST 23 Nov 22 02:30:13 PM PST 23 13467153934 ps
T603 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.77821556652183158434885703203431830311048665593510389441885105509597914690848 Nov 22 02:12:14 PM PST 23 Nov 22 02:19:22 PM PST 23 9325508496 ps
T604 /workspace/coverage/default/21.sram_ctrl_lc_escalation.43994856128588555525273055961296683220065455778841762636991650823090089085651 Nov 22 02:12:36 PM PST 23 Nov 22 02:14:21 PM PST 23 19084394710 ps
T605 /workspace/coverage/default/4.sram_ctrl_multiple_keys.103787441265129693181933545611904629022010010324664441538671940904208013731392 Nov 22 02:07:19 PM PST 23 Nov 22 02:23:37 PM PST 23 28731174678 ps
T606 /workspace/coverage/default/41.sram_ctrl_lc_escalation.78579896755877094086952294071991157473671985203145277584862155886541026080093 Nov 22 02:16:41 PM PST 23 Nov 22 02:18:26 PM PST 23 19084394710 ps
T607 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.102703595264357632224481482077335011584028716240925251558581324616384711343246 Nov 22 02:11:59 PM PST 23 Nov 22 02:28:30 PM PST 23 13467153934 ps
T608 /workspace/coverage/default/36.sram_ctrl_multiple_keys.90815727318057904607444491449043072468873097577684081916039275652328261924605 Nov 22 02:15:39 PM PST 23 Nov 22 02:28:16 PM PST 23 28731174678 ps
T609 /workspace/coverage/default/27.sram_ctrl_smoke.59130077269332144754624207384779390510731667630577599282406785677226398531904 Nov 22 02:13:57 PM PST 23 Nov 22 02:14:14 PM PST 23 988289480 ps
T610 /workspace/coverage/default/47.sram_ctrl_regwen.5658685198424597079133859482076375498682968395603671282020683530376282491349 Nov 22 02:16:52 PM PST 23 Nov 22 02:27:08 PM PST 23 19913691647 ps
T611 /workspace/coverage/default/9.sram_ctrl_max_throughput.63201650053887317123639725312807564955655432599834499600336355940846780273742 Nov 22 02:07:45 PM PST 23 Nov 22 02:09:37 PM PST 23 1342947357 ps
T612 /workspace/coverage/default/6.sram_ctrl_multiple_keys.73709710915786807133773723448611371686224262009984286658431576614490049245307 Nov 22 02:07:35 PM PST 23 Nov 22 02:23:34 PM PST 23 28731174678 ps
T613 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.29899142655805441115723941305157648765651969104306251235976296700527794757831 Nov 22 02:14:59 PM PST 23 Nov 22 02:31:36 PM PST 23 13467153934 ps
T614 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.35865417501885320436376053190256772302916723705429979906486923567454798972139 Nov 22 02:07:36 PM PST 23 Nov 22 02:36:25 PM PST 23 624328106 ps
T615 /workspace/coverage/default/35.sram_ctrl_bijection.100731651320455290594090329194194876996961626055413980943631233468393187412527 Nov 22 02:15:44 PM PST 23 Nov 22 02:58:46 PM PST 23 295482808505 ps
T616 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.88568583036330028144548720247768801486029628467373765022688020228661875596857 Nov 22 02:16:58 PM PST 23 Nov 22 02:19:02 PM PST 23 1371125703 ps
T617 /workspace/coverage/default/38.sram_ctrl_bijection.110771919754261677022545992248119452891857259762349262972088850591899679749741 Nov 22 02:16:36 PM PST 23 Nov 22 03:01:33 PM PST 23 295482808505 ps
T618 /workspace/coverage/default/1.sram_ctrl_smoke.35212588445775237340485611638125259500683250865409133677951932658538244423109 Nov 22 02:07:09 PM PST 23 Nov 22 02:07:32 PM PST 23 988289480 ps
T619 /workspace/coverage/default/5.sram_ctrl_alert_test.43920589289279934344790675281418879049520608168748007887334928363453170977284 Nov 22 02:07:38 PM PST 23 Nov 22 02:07:41 PM PST 23 16600825 ps
T620 /workspace/coverage/default/40.sram_ctrl_alert_test.61636101433488135313113484038512219639931351743227083105606283856221370119931 Nov 22 02:16:14 PM PST 23 Nov 22 02:16:16 PM PST 23 16600825 ps
T621 /workspace/coverage/default/22.sram_ctrl_mem_walk.60332625588961380605464988759955797232267163517443960741982021080486071559153 Nov 22 02:13:20 PM PST 23 Nov 22 02:15:54 PM PST 23 18445453393 ps
T622 /workspace/coverage/default/24.sram_ctrl_bijection.90025672945876178608009589305346524391740509088008383048339726684972658725476 Nov 22 02:13:44 PM PST 23 Nov 22 03:01:39 PM PST 23 295482808505 ps
T623 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.49928978493105519676685769231456321046800597078989649589400634428131004832590 Nov 22 02:12:18 PM PST 23 Nov 22 02:21:58 PM PST 23 45083829570 ps
T624 /workspace/coverage/default/23.sram_ctrl_alert_test.40112574239276150679232205024462922440169366073088670972693242233351416207775 Nov 22 02:13:49 PM PST 23 Nov 22 02:13:50 PM PST 23 16600825 ps
T625 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.112147665134793346556775463086493777370039872534181186296953305741118203920336 Nov 22 02:16:40 PM PST 23 Nov 22 02:48:43 PM PST 23 624328106 ps
T626 /workspace/coverage/default/15.sram_ctrl_ram_cfg.110465380861960047015989230244116002702120677891286488985293252698021411367025 Nov 22 02:11:39 PM PST 23 Nov 22 02:11:46 PM PST 23 607542526 ps
T627 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.13268264982215206276778147542145249668781680441815245666726115094576849400234 Nov 22 02:13:00 PM PST 23 Nov 22 02:14:18 PM PST 23 4750777237 ps
T628 /workspace/coverage/default/32.sram_ctrl_executable.7126114057613727236095418678439134044936444524005335209818999729228990124121 Nov 22 02:14:54 PM PST 23 Nov 22 02:29:21 PM PST 23 31712811539 ps
T629 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.87243327530353853268668658251934026349918591339641118425769711248784055461616 Nov 22 02:15:23 PM PST 23 Nov 22 02:45:42 PM PST 23 624328106 ps
T630 /workspace/coverage/default/44.sram_ctrl_multiple_keys.48704958079615834002534685589970371121806111759073502282844496069101530674468 Nov 22 02:16:36 PM PST 23 Nov 22 02:28:24 PM PST 23 28731174678 ps
T631 /workspace/coverage/default/33.sram_ctrl_mem_walk.74295683145947341579383154037047914497316095850687096029797242674879222521096 Nov 22 02:14:58 PM PST 23 Nov 22 02:17:44 PM PST 23 18445453393 ps
T632 /workspace/coverage/default/34.sram_ctrl_bijection.87977463917745921286522224736599027829174074932587616683624775391597904593838 Nov 22 02:15:31 PM PST 23 Nov 22 03:02:09 PM PST 23 295482808505 ps
T633 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.88320076030398873199585699704991634393952664189495241422895066052681096533594 Nov 22 02:16:10 PM PST 23 Nov 22 02:18:04 PM PST 23 1371125703 ps
T634 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.75545058730503344163066596134556164355251182179712674697812385207382092657156 Nov 22 02:11:27 PM PST 23 Nov 22 02:13:29 PM PST 23 1371125703 ps
T635 /workspace/coverage/default/6.sram_ctrl_ram_cfg.81192753793892655224272644402494780125740403450963153649216175966865144232829 Nov 22 02:07:26 PM PST 23 Nov 22 02:07:33 PM PST 23 607542526 ps
T636 /workspace/coverage/default/4.sram_ctrl_executable.91231296166581456973120500402960554362365301669725968516301878006635898182062 Nov 22 02:07:22 PM PST 23 Nov 22 02:20:22 PM PST 23 31712811539 ps
T637 /workspace/coverage/default/18.sram_ctrl_smoke.46144317135586959411519535913193286956987105147681974697741738777348722024355 Nov 22 02:12:18 PM PST 23 Nov 22 02:12:39 PM PST 23 988289480 ps
T638 /workspace/coverage/default/22.sram_ctrl_lc_escalation.50280806647767012242414628701299182613613945969423241292411933440182576109679 Nov 22 02:13:13 PM PST 23 Nov 22 02:14:58 PM PST 23 19084394710 ps
T639 /workspace/coverage/default/19.sram_ctrl_smoke.24652599586261991848906881999306354103917182373254167424342372172608046061887 Nov 22 02:12:21 PM PST 23 Nov 22 02:12:38 PM PST 23 988289480 ps
T640 /workspace/coverage/default/22.sram_ctrl_multiple_keys.50780868758909995715816472527083983392890962046176981924413088604943299530356 Nov 22 02:13:00 PM PST 23 Nov 22 02:26:07 PM PST 23 28731174678 ps
T641 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.68943269224889721396809569387695478344831068603136987543808251126803016447762 Nov 22 02:07:40 PM PST 23 Nov 22 02:08:56 PM PST 23 4750777237 ps
T642 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.104374162890066184764856889487323050134984476502831978645826577925100163868538 Nov 22 02:07:07 PM PST 23 Nov 22 02:17:10 PM PST 23 45083829570 ps
T643 /workspace/coverage/default/26.sram_ctrl_smoke.27704790670124467001105854140054500124803481838083736108649035019460982657045 Nov 22 02:13:52 PM PST 23 Nov 22 02:14:11 PM PST 23 988289480 ps
T644 /workspace/coverage/default/27.sram_ctrl_lc_escalation.13922202754422007563679635669044858673985856476183440229687729762609455301476 Nov 22 02:14:00 PM PST 23 Nov 22 02:15:46 PM PST 23 19084394710 ps
T645 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.94292077997172572883449446562125852544876356285313504301196413773916967681251 Nov 22 02:15:25 PM PST 23 Nov 22 02:17:21 PM PST 23 1371125703 ps
T646 /workspace/coverage/default/5.sram_ctrl_partial_access.8445774694325154530674045486235214190224832361833223485454550401391562092370 Nov 22 02:07:39 PM PST 23 Nov 22 02:07:59 PM PST 23 1006378621 ps
T647 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.19608932683205075364089915578041697891498560757897379659382393292333542186904 Nov 22 02:16:06 PM PST 23 Nov 22 02:23:08 PM PST 23 9325508496 ps
T648 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.112829128829711642317724159369852398728715725769411620516587812646518300708037 Nov 22 02:17:07 PM PST 23 Nov 22 02:32:07 PM PST 23 13467153934 ps
T649 /workspace/coverage/default/36.sram_ctrl_smoke.108325564920742785734416567968791505710411249868732803551958250075743475702864 Nov 22 02:15:40 PM PST 23 Nov 22 02:15:57 PM PST 23 988289480 ps
T650 /workspace/coverage/default/43.sram_ctrl_ram_cfg.103066189151984872390176728502471511915040567746949777249714653555568109390553 Nov 22 02:16:35 PM PST 23 Nov 22 02:16:42 PM PST 23 607542526 ps
T651 /workspace/coverage/default/22.sram_ctrl_executable.71563913326519892822028640137520369132629392939645287227117133477806660235257 Nov 22 02:13:13 PM PST 23 Nov 22 02:28:33 PM PST 23 31712811539 ps
T652 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.99939464111403080113419014884989131292834851244718533631100589569792513913984 Nov 22 02:07:34 PM PST 23 Nov 22 02:24:33 PM PST 23 13467153934 ps
T653 /workspace/coverage/default/45.sram_ctrl_alert_test.51961321166367206588312203808665332835765747319983165048039364380690170500216 Nov 22 02:16:37 PM PST 23 Nov 22 02:16:38 PM PST 23 16600825 ps
T654 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.41899765179820596960047493353545848183078511028252526000742819029449875243957 Nov 22 02:16:59 PM PST 23 Nov 22 02:24:11 PM PST 23 9325508496 ps
T655 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.24313659124725377436310875378817160362214016990333398726375481454907415410461 Nov 22 02:13:54 PM PST 23 Nov 22 02:31:08 PM PST 23 13467153934 ps
T656 /workspace/coverage/default/38.sram_ctrl_mem_walk.39754068259059653937449656862943416085762014304626448758293620615079595834133 Nov 22 02:16:15 PM PST 23 Nov 22 02:18:54 PM PST 23 18445453393 ps
T657 /workspace/coverage/default/49.sram_ctrl_bijection.58348131086001003563326618354558374665730579997604546132012407656969775036763 Nov 22 02:17:49 PM PST 23 Nov 22 03:04:17 PM PST 23 295482808505 ps
T658 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3912857692180187091634343275057729694712985576983234506400826128209271071454 Nov 22 02:13:56 PM PST 23 Nov 22 02:23:28 PM PST 23 45083829570 ps
T659 /workspace/coverage/default/17.sram_ctrl_bijection.114535423405506613323558216844113594371317987526751552470072597427945562488926 Nov 22 02:12:17 PM PST 23 Nov 22 02:58:47 PM PST 23 295482808505 ps
T660 /workspace/coverage/default/8.sram_ctrl_max_throughput.60491345243873118829721253598950216596410034923990286611024069135258093169060 Nov 22 02:07:42 PM PST 23 Nov 22 02:09:47 PM PST 23 1342947357 ps
T661 /workspace/coverage/default/9.sram_ctrl_lc_escalation.48828288761404446478051592908007224188191042739184545928698125269898885023426 Nov 22 02:07:33 PM PST 23 Nov 22 02:09:19 PM PST 23 19084394710 ps
T662 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.29300716446572105425899103246774172552581449230974231690264115150399148413246 Nov 22 02:13:50 PM PST 23 Nov 22 02:23:36 PM PST 23 45083829570 ps
T663 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.39653159488151772003749718619305623209835897695865663040838541810176327023330 Nov 22 02:14:41 PM PST 23 Nov 22 02:21:51 PM PST 23 9325508496 ps
T664 /workspace/coverage/default/6.sram_ctrl_regwen.13354317017420224409285386887133055062061748711906211399413125731182473615870 Nov 22 02:07:36 PM PST 23 Nov 22 02:16:24 PM PST 23 19913691647 ps
T665 /workspace/coverage/default/43.sram_ctrl_max_throughput.42020294284426308119504911889793537696808098847335852589066536704484710676555 Nov 22 02:16:16 PM PST 23 Nov 22 02:18:17 PM PST 23 1342947357 ps
T666 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.100448248408629527269210811065442291462832915861908290159529317469710873771231 Nov 22 02:16:34 PM PST 23 Nov 22 02:18:46 PM PST 23 1371125703 ps
T667 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.50820689106156364250526105498521638840896272198827071661969277832583220051116 Nov 22 02:14:09 PM PST 23 Nov 22 02:21:16 PM PST 23 9325508496 ps
T668 /workspace/coverage/default/17.sram_ctrl_executable.107049778849075706080363240220934224086138464596641515169404588908462648002406 Nov 22 02:12:18 PM PST 23 Nov 22 02:26:11 PM PST 23 31712811539 ps
T669 /workspace/coverage/default/12.sram_ctrl_smoke.100730811282970285803723010683339137397127523689577803644912050872074606985742 Nov 22 02:11:16 PM PST 23 Nov 22 02:11:35 PM PST 23 988289480 ps
T670 /workspace/coverage/default/14.sram_ctrl_partial_access.53199036150544922024386070323716599472574357562983982570180713656799238482650 Nov 22 02:11:28 PM PST 23 Nov 22 02:11:47 PM PST 23 1006378621 ps
T671 /workspace/coverage/default/46.sram_ctrl_alert_test.76047902680570177148929634640193701899205845793433931271511946487876694409108 Nov 22 02:17:04 PM PST 23 Nov 22 02:17:11 PM PST 23 16600825 ps
T672 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.89808313137886991356097375445137986817629222033992155640329155966729567060012 Nov 22 02:18:10 PM PST 23 Nov 22 02:20:08 PM PST 23 1371125703 ps
T673 /workspace/coverage/default/17.sram_ctrl_partial_access.24892313832722449785825377964237069533578869167489468057940172077356142357121 Nov 22 02:12:17 PM PST 23 Nov 22 02:12:39 PM PST 23 1006378621 ps
T674 /workspace/coverage/default/34.sram_ctrl_regwen.24126434444600306550725096595247571987288515048997993938816423256675479835798 Nov 22 02:16:08 PM PST 23 Nov 22 02:25:03 PM PST 23 19913691647 ps
T675 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.11186575957337992417559818269987989479723419728397937844005088649060051286094 Nov 22 02:07:40 PM PST 23 Nov 22 02:36:38 PM PST 23 624328106 ps
T676 /workspace/coverage/default/21.sram_ctrl_ram_cfg.14041097237628763952611545808716246664724584401093342282041253484302015198069 Nov 22 02:12:58 PM PST 23 Nov 22 02:13:05 PM PST 23 607542526 ps
T677 /workspace/coverage/default/40.sram_ctrl_max_throughput.1391789905303654615558701302244845933707226877432167007960379021537863762831 Nov 22 02:16:10 PM PST 23 Nov 22 02:17:53 PM PST 23 1342947357 ps
T678 /workspace/coverage/default/1.sram_ctrl_multiple_keys.8181650315877850080548491325064569744762337523649434429218517889801716275628 Nov 22 02:07:21 PM PST 23 Nov 22 02:24:40 PM PST 23 28731174678 ps
T679 /workspace/coverage/default/42.sram_ctrl_mem_walk.37837651801430289550191506322963282088238884893261492805358112331738844654668 Nov 22 02:16:37 PM PST 23 Nov 22 02:19:14 PM PST 23 18445453393 ps
T680 /workspace/coverage/default/39.sram_ctrl_regwen.30742445205885625517637163976937298712401923044942903643110818927352830519968 Nov 22 02:16:30 PM PST 23 Nov 22 02:25:28 PM PST 23 19913691647 ps
T681 /workspace/coverage/default/37.sram_ctrl_max_throughput.33303725719218494204346271096983450484305023222147512225931023498853493173474 Nov 22 02:16:10 PM PST 23 Nov 22 02:18:25 PM PST 23 1342947357 ps
T682 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.91873407580769837355221183028588564884574386161944765342110292689178822745214 Nov 22 02:14:51 PM PST 23 Nov 22 02:16:09 PM PST 23 4750777237 ps
T683 /workspace/coverage/default/15.sram_ctrl_lc_escalation.29873461971224156052629564868349722822614900877385018048097453918016809391452 Nov 22 02:11:35 PM PST 23 Nov 22 02:13:22 PM PST 23 19084394710 ps
T684 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.32988869547217264149296037700408827475226082724612759851666419516453335898135 Nov 22 02:16:39 PM PST 23 Nov 22 02:23:42 PM PST 23 9325508496 ps
T685 /workspace/coverage/default/8.sram_ctrl_regwen.35083582902593981736161477598249890810051085796491287924269636194772554881258 Nov 22 02:07:40 PM PST 23 Nov 22 02:16:39 PM PST 23 19913691647 ps
T686 /workspace/coverage/default/4.sram_ctrl_partial_access.25531637686081075642291501355951970986988056103206612673842244790880558727232 Nov 22 02:07:20 PM PST 23 Nov 22 02:07:41 PM PST 23 1006378621 ps
T687 /workspace/coverage/default/42.sram_ctrl_alert_test.48147010184622431322357868887134670754244819785718647322925651538795459535933 Nov 22 02:16:32 PM PST 23 Nov 22 02:16:33 PM PST 23 16600825 ps
T688 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.57841287435760943475030617422491507418047484714906900206727074407154369053488 Nov 22 02:13:44 PM PST 23 Nov 22 02:28:01 PM PST 23 13467153934 ps
T689 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.65244728499427050398585401189204721566523540157703533875757165108568184166623 Nov 22 02:18:05 PM PST 23 Nov 22 02:27:32 PM PST 23 45083829570 ps
T690 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.39976662087478753278685201731720148200670744756107484754664912030121228433107 Nov 22 02:14:14 PM PST 23 Nov 22 02:30:53 PM PST 23 13467153934 ps
T691 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.4978206322932935475132483877512764175713461242087225247722178851174867586336 Nov 22 02:12:15 PM PST 23 Nov 22 02:44:58 PM PST 23 624328106 ps
T692 /workspace/coverage/default/8.sram_ctrl_ram_cfg.107455684456372683761354706811648322859688661890272983608068990292835805242104 Nov 22 02:07:40 PM PST 23 Nov 22 02:07:48 PM PST 23 607542526 ps
T693 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.48739311568081635918883939726971405210993705835650790358163928921537980401455 Nov 22 02:11:15 PM PST 23 Nov 22 02:12:33 PM PST 23 4750777237 ps
T694 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.91707247974699571964625933480647548979616666667276740832927176817569732120854 Nov 22 02:07:20 PM PST 23 Nov 22 02:14:29 PM PST 23 9325508496 ps
T695 /workspace/coverage/default/1.sram_ctrl_max_throughput.61163402776535538230857521363775249160778641809063539061045292897798968275286 Nov 22 02:07:19 PM PST 23 Nov 22 02:09:23 PM PST 23 1342947357 ps
T696 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.32251814890815425101713039508760785658414571067421583345450416916288317157924 Nov 22 02:13:57 PM PST 23 Nov 22 02:29:33 PM PST 23 13467153934 ps
T697 /workspace/coverage/default/24.sram_ctrl_regwen.70499092221266894607616050484857890638629600176435354811222638997285105301227 Nov 22 02:13:44 PM PST 23 Nov 22 02:24:49 PM PST 23 19913691647 ps
T698 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.22665604742996489002441929973296033405497085532902709442354661475882292943423 Nov 22 02:11:20 PM PST 23 Nov 22 02:20:44 PM PST 23 45083829570 ps
T699 /workspace/coverage/default/33.sram_ctrl_alert_test.77002416641414423003952225845068557470793380546622735897998674035769469158537 Nov 22 02:15:32 PM PST 23 Nov 22 02:15:33 PM PST 23 16600825 ps
T700 /workspace/coverage/default/22.sram_ctrl_bijection.59782266868987338606195520368936906557864729103549503881119867098082984943543 Nov 22 02:12:59 PM PST 23 Nov 22 02:58:23 PM PST 23 295482808505 ps
T701 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.92108622493368827305875768906779651274836009463198247923116920920583327395969 Nov 22 02:11:19 PM PST 23 Nov 22 02:39:51 PM PST 23 624328106 ps
T702 /workspace/coverage/default/18.sram_ctrl_lc_escalation.85955272828484431602817142999735276025496440474100728213663987543318306648878 Nov 22 02:12:17 PM PST 23 Nov 22 02:14:04 PM PST 23 19084394710 ps
T703 /workspace/coverage/default/44.sram_ctrl_executable.4517579085897255043001857427785304814289510075833768435257426840090151058332 Nov 22 02:16:34 PM PST 23 Nov 22 02:31:43 PM PST 23 31712811539 ps
T704 /workspace/coverage/default/23.sram_ctrl_executable.23672169165983942869688336583350555320526685259825489231026442356703682246139 Nov 22 02:13:15 PM PST 23 Nov 22 02:28:25 PM PST 23 31712811539 ps
T705 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.86449957788710387246433180365943389279850804715818089217761387546567262228108 Nov 22 02:13:54 PM PST 23 Nov 22 02:21:06 PM PST 23 9325508496 ps
T706 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.60321064134651552250741169738813711231346782524877088302290996733303667266943 Nov 22 02:16:39 PM PST 23 Nov 22 02:18:30 PM PST 23 1371125703 ps
T707 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.82594608290622981656886664116019337970390838767514373096132369432183153320509 Nov 22 02:13:54 PM PST 23 Nov 22 02:23:13 PM PST 23 45083829570 ps
T708 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.84719006454999921081753048856301739903396775876462484569633047679864014240736 Nov 22 02:15:47 PM PST 23 Nov 22 02:23:04 PM PST 23 9325508496 ps
T709 /workspace/coverage/default/1.sram_ctrl_regwen.97581121378408147199760825372724387577701015050083311031617585739317200246662 Nov 22 02:07:19 PM PST 23 Nov 22 02:15:46 PM PST 23 19913691647 ps
T710 /workspace/coverage/default/13.sram_ctrl_smoke.27254529455110058827891803311150852312365404008806724003663392767044543673677 Nov 22 02:11:20 PM PST 23 Nov 22 02:11:39 PM PST 23 988289480 ps
T711 /workspace/coverage/default/40.sram_ctrl_partial_access.27148801290965838874803931818627324611960760488671217615471711273445965637530 Nov 22 02:16:01 PM PST 23 Nov 22 02:16:20 PM PST 23 1006378621 ps
T712 /workspace/coverage/default/7.sram_ctrl_regwen.16856735281406054645348807017000601961323573657577744066211393274982138764524 Nov 22 02:07:37 PM PST 23 Nov 22 02:16:03 PM PST 23 19913691647 ps
T713 /workspace/coverage/default/46.sram_ctrl_regwen.64877377778536679717295382968723974669323211709705431909488710480975691771864 Nov 22 02:17:07 PM PST 23 Nov 22 02:27:45 PM PST 23 19913691647 ps
T714 /workspace/coverage/default/20.sram_ctrl_regwen.61669075240175882145540177414045291532733876611704292110849414594322095994638 Nov 22 02:12:53 PM PST 23 Nov 22 02:23:35 PM PST 23 19913691647 ps
T715 /workspace/coverage/default/13.sram_ctrl_alert_test.62061697479568573998675581668803202481556467315997405760843130387615448053772 Nov 22 02:11:27 PM PST 23 Nov 22 02:11:28 PM PST 23 16600825 ps
T716 /workspace/coverage/default/3.sram_ctrl_lc_escalation.84705427247150356951693946712708923458174703980861080479312063795493704146451 Nov 22 02:07:19 PM PST 23 Nov 22 02:09:06 PM PST 23 19084394710 ps
T717 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.75805460121964158196241290419503369524304767214454416937247060821131746021177 Nov 22 02:14:53 PM PST 23 Nov 22 02:16:15 PM PST 23 4750777237 ps
T718 /workspace/coverage/default/2.sram_ctrl_mem_walk.15012098295363177823845164163961866402139229468513485193180744588144304497224 Nov 22 02:07:07 PM PST 23 Nov 22 02:09:49 PM PST 23 18445453393 ps
T719 /workspace/coverage/default/9.sram_ctrl_smoke.69447544078274979803609783971991648896250584342837855026990414537026897415584 Nov 22 02:07:42 PM PST 23 Nov 22 02:08:02 PM PST 23 988289480 ps
T720 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.92676551723609765351919628593224785630783488136129682761241577651247746940723 Nov 22 02:14:06 PM PST 23 Nov 22 02:46:53 PM PST 23 624328106 ps
T721 /workspace/coverage/default/20.sram_ctrl_ram_cfg.77205332449846106363383983845960975436321745440888347756694133632699537437556 Nov 22 02:12:50 PM PST 23 Nov 22 02:12:57 PM PST 23 607542526 ps
T722 /workspace/coverage/default/4.sram_ctrl_regwen.85052753629445687767015557897398219625568939811271210667177656422214538750627 Nov 22 02:07:21 PM PST 23 Nov 22 02:16:13 PM PST 23 19913691647 ps
T723 /workspace/coverage/default/29.sram_ctrl_lc_escalation.28484581239370797324375690251957330449168672778999545682949627047408333501558 Nov 22 02:14:40 PM PST 23 Nov 22 02:16:23 PM PST 23 19084394710 ps
T724 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.28730897555928499362853426347202410038105083220374336307039974026964826754549 Nov 22 02:16:35 PM PST 23 Nov 22 02:23:38 PM PST 23 9325508496 ps
T725 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.52976986384827756141646158154957112644369480703274485987565608689977404484814 Nov 22 02:13:12 PM PST 23 Nov 22 02:22:46 PM PST 23 45083829570 ps
T726 /workspace/coverage/default/8.sram_ctrl_partial_access.26907112141761533076842496653985896466865168388208385831067226835046170405673 Nov 22 02:07:39 PM PST 23 Nov 22 02:08:00 PM PST 23 1006378621 ps
T727 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.37856441497490735232772385923192005821807448481636337015073599833146732624949 Nov 22 02:13:44 PM PST 23 Nov 22 02:15:03 PM PST 23 4750777237 ps
T728 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.53276804272455960131596773357186180467866883197140343377423496132752830330701 Nov 22 02:07:19 PM PST 23 Nov 22 02:25:52 PM PST 23 13467153934 ps
T729 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.65767587816148386748878622607329826489370748418893207071675035948014465317603 Nov 22 02:12:50 PM PST 23 Nov 22 02:14:11 PM PST 23 4750777237 ps
T730 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.31347206366021660731453737456107027459606764578762180700925590624509028939414 Nov 22 02:16:40 PM PST 23 Nov 22 02:23:41 PM PST 23 9325508496 ps
T731 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.17904989559326418779320820254947316233572194466000368756912468147830491171113 Nov 22 02:16:38 PM PST 23 Nov 22 02:18:25 PM PST 23 1371125703 ps
T732 /workspace/coverage/default/31.sram_ctrl_executable.1423801950687985736497072945637831573547945171288318670032767847165448160391 Nov 22 02:14:55 PM PST 23 Nov 22 02:27:59 PM PST 23 31712811539 ps
T733 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.52412802430688189175713955931554012624415696188234865168914811301780543173446 Nov 22 02:16:35 PM PST 23 Nov 22 02:17:54 PM PST 23 4750777237 ps
T734 /workspace/coverage/default/26.sram_ctrl_executable.19162857130371756830822059441080555334183144800423173168107226046942689626600 Nov 22 02:13:54 PM PST 23 Nov 22 02:30:01 PM PST 23 31712811539 ps
T735 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.90944555222722784184390002244702682658988105576254809183323325468716580255641 Nov 22 02:16:32 PM PST 23 Nov 22 02:26:04 PM PST 23 45083829570 ps
T736 /workspace/coverage/default/11.sram_ctrl_lc_escalation.36730963147197501108298017079648655583959453028983281362662620015478363287176 Nov 22 02:11:15 PM PST 23 Nov 22 02:13:02 PM PST 23 19084394710 ps
T737 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.69913545251791849862830654501886831135963317677415935824136715302852960862108 Nov 22 02:16:40 PM PST 23 Nov 22 02:19:02 PM PST 23 1371125703 ps
T738 /workspace/coverage/default/36.sram_ctrl_partial_access.52150251779741359924693691361012151962035095866283953469890240568344186332943 Nov 22 02:15:34 PM PST 23 Nov 22 02:15:53 PM PST 23 1006378621 ps
T739 /workspace/coverage/default/21.sram_ctrl_partial_access.18152810040112457980884965760832168778159691643678979616247765076335008824332 Nov 22 02:12:54 PM PST 23 Nov 22 02:13:15 PM PST 23 1006378621 ps
T740 /workspace/coverage/default/10.sram_ctrl_smoke.71569320930495032181545335246410134007879804239601298913866140691067188519629 Nov 22 02:07:36 PM PST 23 Nov 22 02:07:56 PM PST 23 988289480 ps
T741 /workspace/coverage/default/47.sram_ctrl_partial_access.71938657414100530351895506547118377513607437510947641446286718454496477382411 Nov 22 02:17:08 PM PST 23 Nov 22 02:17:33 PM PST 23 1006378621 ps
T742 /workspace/coverage/default/43.sram_ctrl_bijection.32671346467957841022105067713129227906475949970470872362794108785261087495641 Nov 22 02:16:38 PM PST 23 Nov 22 03:01:18 PM PST 23 295482808505 ps
T743 /workspace/coverage/default/41.sram_ctrl_bijection.103123802111579255018085555572488500996053592934193285259871826750007756439185 Nov 22 02:16:39 PM PST 23 Nov 22 03:02:32 PM PST 23 295482808505 ps
T744 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.7513280565685746618685806259552349153634068672198503890950758988337329467749 Nov 22 02:11:35 PM PST 23 Nov 22 02:42:27 PM PST 23 624328106 ps
T745 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.78590107220036670872765928053200098765802184476858040141131284504018726613558 Nov 22 02:17:32 PM PST 23 Nov 22 02:31:41 PM PST 23 13467153934 ps
T746 /workspace/coverage/default/34.sram_ctrl_multiple_keys.79154898739785819443794038636297594838960729988362692980313608861923444464490 Nov 22 02:15:31 PM PST 23 Nov 22 02:28:08 PM PST 23 28731174678 ps
T747 /workspace/coverage/default/21.sram_ctrl_max_throughput.114428881117759822274332829858417188683914053283653169309775787642761818623445 Nov 22 02:13:00 PM PST 23 Nov 22 02:15:29 PM PST 23 1342947357 ps
T748 /workspace/coverage/default/25.sram_ctrl_ram_cfg.16422829074147680226309656381506859755731452506845646241199584519875679319436 Nov 22 02:13:50 PM PST 23 Nov 22 02:13:57 PM PST 23 607542526 ps
T749 /workspace/coverage/default/9.sram_ctrl_multiple_keys.69206360245227235123579508156949936616673429802657122883581764522811840558499 Nov 22 02:07:42 PM PST 23 Nov 22 02:20:12 PM PST 23 28731174678 ps
T36 /workspace/coverage/default/2.sram_ctrl_sec_cm.75668097987430080264928916519636709144575755584681963209520445000737793668255 Nov 22 02:07:06 PM PST 23 Nov 22 02:07:13 PM PST 23 216402798 ps
T750 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.94231334619638750995141052919221984316091131512873616191567031615977783644816 Nov 22 02:11:41 PM PST 23 Nov 22 02:41:18 PM PST 23 624328106 ps
T751 /workspace/coverage/default/6.sram_ctrl_lc_escalation.45676316894798971622451815964755312881383040844059310665579417952272754044570 Nov 22 02:07:35 PM PST 23 Nov 22 02:09:23 PM PST 23 19084394710 ps
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