| T503 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.659954420 |
|
|
Dec 24 01:27:11 PM PST 23 |
Dec 24 01:31:27 PM PST 23 |
223125330541 ps |
| T504 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2128604084 |
|
|
Dec 24 01:26:45 PM PST 23 |
Dec 24 01:27:19 PM PST 23 |
1394669084 ps |
| T505 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.879332505 |
|
|
Dec 24 01:22:05 PM PST 23 |
Dec 24 01:22:40 PM PST 23 |
2225707030 ps |
| T506 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3176479992 |
|
|
Dec 24 01:26:06 PM PST 23 |
Dec 24 01:28:24 PM PST 23 |
6739550122 ps |
| T507 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3047660845 |
|
|
Dec 24 01:26:34 PM PST 23 |
Dec 24 01:31:39 PM PST 23 |
28705987249 ps |
| T508 |
/workspace/coverage/default/31.sram_ctrl_regwen.3982506182 |
|
|
Dec 24 01:25:31 PM PST 23 |
Dec 24 01:31:26 PM PST 23 |
1778039277 ps |
| T509 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2501839583 |
|
|
Dec 24 01:27:09 PM PST 23 |
Dec 24 01:56:49 PM PST 23 |
44241117031 ps |
| T510 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.705165129 |
|
|
Dec 24 01:26:48 PM PST 23 |
Dec 24 01:27:23 PM PST 23 |
3587379549 ps |
| T511 |
/workspace/coverage/default/24.sram_ctrl_executable.259387939 |
|
|
Dec 24 01:24:40 PM PST 23 |
Dec 24 01:34:57 PM PST 23 |
12872392158 ps |
| T512 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.745982101 |
|
|
Dec 24 01:27:01 PM PST 23 |
Dec 24 01:33:05 PM PST 23 |
22760261455 ps |
| T513 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3132682806 |
|
|
Dec 24 01:26:04 PM PST 23 |
Dec 24 02:57:10 PM PST 23 |
8768977218 ps |
| T514 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.631777419 |
|
|
Dec 24 01:25:25 PM PST 23 |
Dec 24 01:57:46 PM PST 23 |
42418422239 ps |
| T515 |
/workspace/coverage/default/41.sram_ctrl_smoke.1708003409 |
|
|
Dec 24 01:27:00 PM PST 23 |
Dec 24 01:27:31 PM PST 23 |
750287048 ps |
| T516 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3370354707 |
|
|
Dec 24 01:24:46 PM PST 23 |
Dec 24 01:38:18 PM PST 23 |
3470447984 ps |
| T517 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.1754673806 |
|
|
Dec 24 01:24:32 PM PST 23 |
Dec 24 01:35:24 PM PST 23 |
16165058466 ps |
| T518 |
/workspace/coverage/default/48.sram_ctrl_bijection.3380078574 |
|
|
Dec 24 01:27:30 PM PST 23 |
Dec 24 01:47:03 PM PST 23 |
47159044583 ps |
| T519 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2250191218 |
|
|
Dec 24 01:27:01 PM PST 23 |
Dec 24 01:28:49 PM PST 23 |
755245171 ps |
| T520 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.2518096690 |
|
|
Dec 24 01:26:06 PM PST 23 |
Dec 24 02:01:08 PM PST 23 |
11335438606 ps |
| T521 |
/workspace/coverage/default/25.sram_ctrl_smoke.381842332 |
|
|
Dec 24 01:24:32 PM PST 23 |
Dec 24 01:26:22 PM PST 23 |
2254419867 ps |
| T522 |
/workspace/coverage/default/32.sram_ctrl_alert_test.87495985 |
|
|
Dec 24 01:25:50 PM PST 23 |
Dec 24 01:25:54 PM PST 23 |
18400309 ps |
| T523 |
/workspace/coverage/default/23.sram_ctrl_smoke.476619262 |
|
|
Dec 24 01:24:30 PM PST 23 |
Dec 24 01:24:48 PM PST 23 |
373358484 ps |
| T524 |
/workspace/coverage/default/47.sram_ctrl_bijection.431257112 |
|
|
Dec 24 01:27:16 PM PST 23 |
Dec 24 01:48:33 PM PST 23 |
213162768483 ps |
| T525 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2299791092 |
|
|
Dec 24 01:25:35 PM PST 23 |
Dec 24 01:42:51 PM PST 23 |
8068102686 ps |
| T526 |
/workspace/coverage/default/42.sram_ctrl_partial_access.1317797053 |
|
|
Dec 24 01:26:46 PM PST 23 |
Dec 24 01:26:56 PM PST 23 |
465106510 ps |
| T527 |
/workspace/coverage/default/45.sram_ctrl_regwen.3408440014 |
|
|
Dec 24 01:27:12 PM PST 23 |
Dec 24 01:48:24 PM PST 23 |
34675980091 ps |
| T528 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.697599579 |
|
|
Dec 24 01:26:11 PM PST 23 |
Dec 24 01:28:55 PM PST 23 |
20340639475 ps |
| T529 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2623434666 |
|
|
Dec 24 01:23:34 PM PST 23 |
Dec 24 01:39:59 PM PST 23 |
19680638622 ps |
| T530 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1795925220 |
|
|
Dec 24 01:24:34 PM PST 23 |
Dec 24 02:02:48 PM PST 23 |
13937952315 ps |
| T531 |
/workspace/coverage/default/21.sram_ctrl_bijection.2883403759 |
|
|
Dec 24 01:24:30 PM PST 23 |
Dec 24 01:54:03 PM PST 23 |
24940397240 ps |
| T532 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2728627499 |
|
|
Dec 24 01:24:36 PM PST 23 |
Dec 24 01:25:58 PM PST 23 |
2454812966 ps |
| T533 |
/workspace/coverage/default/7.sram_ctrl_partial_access.1182678296 |
|
|
Dec 24 01:22:19 PM PST 23 |
Dec 24 01:22:48 PM PST 23 |
1243568846 ps |
| T534 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.3560038974 |
|
|
Dec 24 01:22:03 PM PST 23 |
Dec 24 01:22:11 PM PST 23 |
1770672244 ps |
| T535 |
/workspace/coverage/default/2.sram_ctrl_bijection.1151482558 |
|
|
Dec 24 01:21:58 PM PST 23 |
Dec 24 01:39:40 PM PST 23 |
192360899536 ps |
| T536 |
/workspace/coverage/default/4.sram_ctrl_regwen.2886200976 |
|
|
Dec 24 01:22:04 PM PST 23 |
Dec 24 01:30:30 PM PST 23 |
3069175693 ps |
| T537 |
/workspace/coverage/default/10.sram_ctrl_regwen.1493173272 |
|
|
Dec 24 01:23:01 PM PST 23 |
Dec 24 01:34:03 PM PST 23 |
35559717437 ps |
| T538 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2064326602 |
|
|
Dec 24 01:21:59 PM PST 23 |
Dec 24 01:25:14 PM PST 23 |
3128374294 ps |
| T539 |
/workspace/coverage/default/27.sram_ctrl_stress_all.1785415034 |
|
|
Dec 24 01:26:17 PM PST 23 |
Dec 24 02:56:50 PM PST 23 |
240744407130 ps |
| T540 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2119566183 |
|
|
Dec 24 01:23:32 PM PST 23 |
Dec 24 01:24:05 PM PST 23 |
719187628 ps |
| T541 |
/workspace/coverage/default/9.sram_ctrl_regwen.2385469219 |
|
|
Dec 24 01:22:40 PM PST 23 |
Dec 24 01:31:11 PM PST 23 |
23580098497 ps |
| T542 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3679607297 |
|
|
Dec 24 01:24:47 PM PST 23 |
Dec 24 01:25:16 PM PST 23 |
755842406 ps |
| T543 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3521582912 |
|
|
Dec 24 01:27:05 PM PST 23 |
Dec 24 01:31:00 PM PST 23 |
14653879925 ps |
| T544 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2636550313 |
|
|
Dec 24 01:24:53 PM PST 23 |
Dec 24 01:31:03 PM PST 23 |
2068551758 ps |
| T545 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.1464789463 |
|
|
Dec 24 01:27:30 PM PST 23 |
Dec 24 01:32:18 PM PST 23 |
49187538085 ps |
| T546 |
/workspace/coverage/default/1.sram_ctrl_executable.587476712 |
|
|
Dec 24 01:22:00 PM PST 23 |
Dec 24 01:46:07 PM PST 23 |
217653253715 ps |
| T547 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3894358414 |
|
|
Dec 24 01:22:05 PM PST 23 |
Dec 24 01:36:43 PM PST 23 |
43739500841 ps |
| T548 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.515394910 |
|
|
Dec 24 01:22:04 PM PST 23 |
Dec 24 01:53:10 PM PST 23 |
603263771 ps |
| T549 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.4277404291 |
|
|
Dec 24 01:23:41 PM PST 23 |
Dec 24 01:26:01 PM PST 23 |
6266150441 ps |
| T550 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2141320308 |
|
|
Dec 24 01:26:09 PM PST 23 |
Dec 24 02:00:59 PM PST 23 |
1972685804 ps |
| T551 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3939479361 |
|
|
Dec 24 01:24:36 PM PST 23 |
Dec 24 01:27:08 PM PST 23 |
20783351688 ps |
| T552 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1150388314 |
|
|
Dec 24 01:23:34 PM PST 23 |
Dec 24 02:47:28 PM PST 23 |
6304343084 ps |
| T553 |
/workspace/coverage/default/26.sram_ctrl_executable.1946144885 |
|
|
Dec 24 01:24:33 PM PST 23 |
Dec 24 01:39:29 PM PST 23 |
61594879356 ps |
| T554 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.1146617300 |
|
|
Dec 24 01:25:24 PM PST 23 |
Dec 24 01:29:56 PM PST 23 |
15761159281 ps |
| T555 |
/workspace/coverage/default/39.sram_ctrl_smoke.1579433227 |
|
|
Dec 24 01:26:33 PM PST 23 |
Dec 24 01:26:47 PM PST 23 |
2515947874 ps |
| T556 |
/workspace/coverage/default/43.sram_ctrl_bijection.1674350861 |
|
|
Dec 24 01:26:47 PM PST 23 |
Dec 24 01:36:32 PM PST 23 |
8554436827 ps |
| T557 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.1844827466 |
|
|
Dec 24 01:24:36 PM PST 23 |
Dec 24 01:29:03 PM PST 23 |
21896911658 ps |
| T558 |
/workspace/coverage/default/37.sram_ctrl_executable.3818410735 |
|
|
Dec 24 01:26:07 PM PST 23 |
Dec 24 01:29:43 PM PST 23 |
3156238179 ps |
| T559 |
/workspace/coverage/default/14.sram_ctrl_alert_test.1337663882 |
|
|
Dec 24 01:23:29 PM PST 23 |
Dec 24 01:23:33 PM PST 23 |
20699488 ps |
| T36 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.2836654865 |
|
|
Dec 24 01:21:57 PM PST 23 |
Dec 24 01:22:00 PM PST 23 |
113079164 ps |
| T560 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.519792092 |
|
|
Dec 24 01:25:52 PM PST 23 |
Dec 24 01:26:34 PM PST 23 |
13850119068 ps |
| T561 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1490771502 |
|
|
Dec 24 01:24:32 PM PST 23 |
Dec 24 01:25:13 PM PST 23 |
2226568648 ps |
| T562 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2167808279 |
|
|
Dec 24 01:22:07 PM PST 23 |
Dec 24 01:22:23 PM PST 23 |
1351684546 ps |
| T563 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.356322672 |
|
|
Dec 24 01:21:30 PM PST 23 |
Dec 24 01:27:09 PM PST 23 |
6903269792 ps |
| T564 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2352474546 |
|
|
Dec 24 01:22:45 PM PST 23 |
Dec 24 01:26:37 PM PST 23 |
66023184881 ps |
| T565 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2103811223 |
|
|
Dec 24 01:23:12 PM PST 23 |
Dec 24 01:23:24 PM PST 23 |
6419313804 ps |
| T566 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.82358727 |
|
|
Dec 24 01:27:01 PM PST 23 |
Dec 24 01:30:04 PM PST 23 |
4004937888 ps |
| T567 |
/workspace/coverage/default/32.sram_ctrl_regwen.254303626 |
|
|
Dec 24 01:25:52 PM PST 23 |
Dec 24 01:45:41 PM PST 23 |
15213168992 ps |
| T568 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.1681740336 |
|
|
Dec 24 01:24:27 PM PST 23 |
Dec 24 01:27:10 PM PST 23 |
61113743579 ps |
| T569 |
/workspace/coverage/default/12.sram_ctrl_bijection.1889449156 |
|
|
Dec 24 01:22:56 PM PST 23 |
Dec 24 01:56:24 PM PST 23 |
29030419525 ps |
| T570 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3558702514 |
|
|
Dec 24 01:22:06 PM PST 23 |
Dec 24 01:24:33 PM PST 23 |
30975210100 ps |
| T571 |
/workspace/coverage/default/15.sram_ctrl_partial_access.375058013 |
|
|
Dec 24 01:23:29 PM PST 23 |
Dec 24 01:24:16 PM PST 23 |
1216311276 ps |
| T572 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2248631462 |
|
|
Dec 24 01:25:50 PM PST 23 |
Dec 24 02:17:01 PM PST 23 |
2262747129 ps |
| T573 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2604879234 |
|
|
Dec 24 01:23:42 PM PST 23 |
Dec 24 01:33:28 PM PST 23 |
37411239890 ps |
| T574 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2996993020 |
|
|
Dec 24 01:21:26 PM PST 23 |
Dec 24 01:27:30 PM PST 23 |
141167662220 ps |
| T575 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.185684430 |
|
|
Dec 24 01:26:47 PM PST 23 |
Dec 24 02:46:27 PM PST 23 |
400168897 ps |
| T576 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3324733718 |
|
|
Dec 24 01:22:08 PM PST 23 |
Dec 24 01:24:15 PM PST 23 |
20864646289 ps |
| T577 |
/workspace/coverage/default/17.sram_ctrl_partial_access.2385623251 |
|
|
Dec 24 01:23:27 PM PST 23 |
Dec 24 01:24:05 PM PST 23 |
814100532 ps |
| T578 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3631590035 |
|
|
Dec 24 01:26:45 PM PST 23 |
Dec 24 02:15:22 PM PST 23 |
5891862148 ps |
| T579 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.3762267266 |
|
|
Dec 24 01:26:17 PM PST 23 |
Dec 24 01:28:07 PM PST 23 |
836294466 ps |
| T580 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.404486660 |
|
|
Dec 24 01:26:04 PM PST 23 |
Dec 24 01:26:13 PM PST 23 |
362392733 ps |
| T581 |
/workspace/coverage/default/47.sram_ctrl_alert_test.3949251364 |
|
|
Dec 24 01:27:27 PM PST 23 |
Dec 24 01:27:29 PM PST 23 |
168451017 ps |
| T582 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.3704347323 |
|
|
Dec 24 01:23:12 PM PST 23 |
Dec 24 01:33:11 PM PST 23 |
24124612503 ps |
| T583 |
/workspace/coverage/default/4.sram_ctrl_alert_test.3022215030 |
|
|
Dec 24 01:22:06 PM PST 23 |
Dec 24 01:22:09 PM PST 23 |
14069282 ps |
| T584 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.3496787262 |
|
|
Dec 24 01:26:07 PM PST 23 |
Dec 24 01:27:34 PM PST 23 |
4072514670 ps |
| T585 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3367792919 |
|
|
Dec 24 01:23:25 PM PST 23 |
Dec 24 01:24:35 PM PST 23 |
771347410 ps |
| T586 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.2279255108 |
|
|
Dec 24 01:22:09 PM PST 23 |
Dec 24 01:22:38 PM PST 23 |
2304738524 ps |
| T587 |
/workspace/coverage/default/22.sram_ctrl_regwen.127264704 |
|
|
Dec 24 01:24:27 PM PST 23 |
Dec 24 01:38:18 PM PST 23 |
24693096320 ps |
| T588 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.1635679833 |
|
|
Dec 24 01:22:05 PM PST 23 |
Dec 24 01:22:56 PM PST 23 |
11455678637 ps |
| T589 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.4232546821 |
|
|
Dec 24 01:26:33 PM PST 23 |
Dec 24 01:36:24 PM PST 23 |
21450782735 ps |
| T590 |
/workspace/coverage/default/29.sram_ctrl_partial_access.40673244 |
|
|
Dec 24 01:26:17 PM PST 23 |
Dec 24 01:26:42 PM PST 23 |
1362585219 ps |
| T591 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.954183199 |
|
|
Dec 24 01:27:02 PM PST 23 |
Dec 24 01:28:10 PM PST 23 |
1878265920 ps |
| T592 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1592264172 |
|
|
Dec 24 01:23:31 PM PST 23 |
Dec 24 01:23:40 PM PST 23 |
360663976 ps |
| T593 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1541904973 |
|
|
Dec 24 01:24:46 PM PST 23 |
Dec 24 01:25:18 PM PST 23 |
2827297397 ps |
| T594 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.328267020 |
|
|
Dec 24 01:27:26 PM PST 23 |
Dec 24 01:29:43 PM PST 23 |
808363398 ps |
| T595 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.3695430758 |
|
|
Dec 24 01:24:47 PM PST 23 |
Dec 24 01:27:00 PM PST 23 |
22963835046 ps |
| T596 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.740510756 |
|
|
Dec 24 01:23:05 PM PST 23 |
Dec 24 01:23:13 PM PST 23 |
1350434853 ps |
| T597 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2616090404 |
|
|
Dec 24 01:26:47 PM PST 23 |
Dec 24 01:29:22 PM PST 23 |
9204983892 ps |
| T598 |
/workspace/coverage/default/7.sram_ctrl_regwen.397054742 |
|
|
Dec 24 01:22:18 PM PST 23 |
Dec 24 01:44:29 PM PST 23 |
10604547180 ps |
| T599 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3554393162 |
|
|
Dec 24 01:25:49 PM PST 23 |
Dec 24 01:31:11 PM PST 23 |
14770374993 ps |
| T600 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1504060095 |
|
|
Dec 24 01:22:17 PM PST 23 |
Dec 24 01:55:29 PM PST 23 |
54038593209 ps |
| T601 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3539923677 |
|
|
Dec 24 01:23:34 PM PST 23 |
Dec 24 01:24:46 PM PST 23 |
1514987091 ps |
| T602 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.1874878564 |
|
|
Dec 24 01:25:26 PM PST 23 |
Dec 24 01:26:57 PM PST 23 |
8924357305 ps |
| T603 |
/workspace/coverage/default/24.sram_ctrl_smoke.792285261 |
|
|
Dec 24 01:24:34 PM PST 23 |
Dec 24 01:26:49 PM PST 23 |
1566166935 ps |
| T604 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1883684805 |
|
|
Dec 24 01:24:34 PM PST 23 |
Dec 24 01:25:00 PM PST 23 |
2433952287 ps |
| T605 |
/workspace/coverage/default/22.sram_ctrl_bijection.1126745104 |
|
|
Dec 24 01:24:27 PM PST 23 |
Dec 24 01:43:37 PM PST 23 |
62520309661 ps |
| T606 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.691139351 |
|
|
Dec 24 01:24:52 PM PST 23 |
Dec 24 01:44:24 PM PST 23 |
7341886644 ps |
| T607 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.788126995 |
|
|
Dec 24 01:22:08 PM PST 23 |
Dec 24 01:40:39 PM PST 23 |
468313884 ps |
| T608 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1125778127 |
|
|
Dec 24 01:23:29 PM PST 23 |
Dec 24 01:25:30 PM PST 23 |
3300476727 ps |
| T609 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1357004140 |
|
|
Dec 24 01:25:50 PM PST 23 |
Dec 24 01:26:41 PM PST 23 |
733282839 ps |
| T610 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.2546534626 |
|
|
Dec 24 01:26:47 PM PST 23 |
Dec 24 01:27:47 PM PST 23 |
1124499431 ps |
| T611 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4102552094 |
|
|
Dec 24 01:27:41 PM PST 23 |
Dec 24 01:58:47 PM PST 23 |
12299305330 ps |
| T612 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.782316218 |
|
|
Dec 24 01:26:05 PM PST 23 |
Dec 24 01:32:40 PM PST 23 |
38461958174 ps |
| T613 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.606427897 |
|
|
Dec 24 01:23:27 PM PST 23 |
Dec 24 01:25:55 PM PST 23 |
789015870 ps |
| T614 |
/workspace/coverage/default/37.sram_ctrl_smoke.988544268 |
|
|
Dec 24 01:26:04 PM PST 23 |
Dec 24 01:26:36 PM PST 23 |
2509406774 ps |
| T615 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1899036727 |
|
|
Dec 24 01:22:21 PM PST 23 |
Dec 24 01:28:30 PM PST 23 |
87493577753 ps |
| T616 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1351367602 |
|
|
Dec 24 01:22:55 PM PST 23 |
Dec 24 01:24:37 PM PST 23 |
1455981298 ps |
| T617 |
/workspace/coverage/default/23.sram_ctrl_regwen.1408799943 |
|
|
Dec 24 01:24:35 PM PST 23 |
Dec 24 01:51:20 PM PST 23 |
18748340386 ps |
| T618 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.803253188 |
|
|
Dec 24 01:21:58 PM PST 23 |
Dec 24 01:27:44 PM PST 23 |
4516086800 ps |
| T619 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.1155056952 |
|
|
Dec 24 01:23:26 PM PST 23 |
Dec 24 01:28:16 PM PST 23 |
14354110668 ps |
| T620 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2466646190 |
|
|
Dec 24 01:23:12 PM PST 23 |
Dec 24 01:26:28 PM PST 23 |
9902465236 ps |
| T621 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.290691591 |
|
|
Dec 24 01:24:35 PM PST 23 |
Dec 24 02:08:27 PM PST 23 |
589283621 ps |
| T622 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1105617306 |
|
|
Dec 24 01:23:12 PM PST 23 |
Dec 24 02:33:19 PM PST 23 |
39974150762 ps |
| T623 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2660852887 |
|
|
Dec 24 01:26:11 PM PST 23 |
Dec 24 01:28:47 PM PST 23 |
528126631 ps |
| T624 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1245083194 |
|
|
Dec 24 01:22:55 PM PST 23 |
Dec 24 01:22:57 PM PST 23 |
14077114 ps |
| T625 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.228915561 |
|
|
Dec 24 01:25:50 PM PST 23 |
Dec 24 01:30:06 PM PST 23 |
4108972932 ps |
| T626 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1201742641 |
|
|
Dec 24 01:23:26 PM PST 23 |
Dec 24 01:29:02 PM PST 23 |
4070682218 ps |
| T627 |
/workspace/coverage/default/44.sram_ctrl_alert_test.650949134 |
|
|
Dec 24 01:27:01 PM PST 23 |
Dec 24 01:27:03 PM PST 23 |
113830326 ps |
| T628 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.4126792388 |
|
|
Dec 24 01:23:00 PM PST 23 |
Dec 24 01:24:22 PM PST 23 |
5515178783 ps |
| T629 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1578126917 |
|
|
Dec 24 01:22:07 PM PST 23 |
Dec 24 01:22:24 PM PST 23 |
1406937014 ps |
| T630 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2383800020 |
|
|
Dec 24 01:26:12 PM PST 23 |
Dec 24 01:31:40 PM PST 23 |
14334255449 ps |
| T631 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.794759960 |
|
|
Dec 24 01:23:49 PM PST 23 |
Dec 24 01:24:28 PM PST 23 |
1886279302 ps |
| T632 |
/workspace/coverage/default/40.sram_ctrl_stress_all.2305157346 |
|
|
Dec 24 01:26:51 PM PST 23 |
Dec 24 02:48:39 PM PST 23 |
657425819152 ps |
| T633 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.935908575 |
|
|
Dec 24 01:24:14 PM PST 23 |
Dec 24 01:24:49 PM PST 23 |
2999118866 ps |
| T634 |
/workspace/coverage/default/12.sram_ctrl_regwen.167565266 |
|
|
Dec 24 01:23:13 PM PST 23 |
Dec 24 01:32:44 PM PST 23 |
8004318765 ps |
| T635 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2796852516 |
|
|
Dec 24 01:26:09 PM PST 23 |
Dec 24 01:27:05 PM PST 23 |
17842184603 ps |
| T636 |
/workspace/coverage/default/26.sram_ctrl_smoke.3820893936 |
|
|
Dec 24 01:24:34 PM PST 23 |
Dec 24 01:25:25 PM PST 23 |
2694285374 ps |
| T637 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2995228282 |
|
|
Dec 24 01:27:06 PM PST 23 |
Dec 24 01:47:27 PM PST 23 |
16825186344 ps |
| T638 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.235675034 |
|
|
Dec 24 01:22:41 PM PST 23 |
Dec 24 01:42:57 PM PST 23 |
69059652802 ps |
| T639 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3033833568 |
|
|
Dec 24 01:27:16 PM PST 23 |
Dec 24 01:27:23 PM PST 23 |
1248033605 ps |
| T640 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.525917245 |
|
|
Dec 24 01:26:48 PM PST 23 |
Dec 24 01:28:14 PM PST 23 |
785832385 ps |
| T641 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.587124506 |
|
|
Dec 24 01:26:59 PM PST 23 |
Dec 24 01:29:45 PM PST 23 |
28434761500 ps |
| T642 |
/workspace/coverage/default/23.sram_ctrl_bijection.2832288299 |
|
|
Dec 24 01:24:35 PM PST 23 |
Dec 24 01:47:35 PM PST 23 |
249899117064 ps |
| T643 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1268696274 |
|
|
Dec 24 01:22:07 PM PST 23 |
Dec 24 01:31:28 PM PST 23 |
45657855327 ps |
| T644 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1300131012 |
|
|
Dec 24 01:23:29 PM PST 23 |
Dec 24 01:29:03 PM PST 23 |
18131237468 ps |
| T645 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2951922040 |
|
|
Dec 24 01:22:06 PM PST 23 |
Dec 24 01:23:30 PM PST 23 |
2549473883 ps |
| T646 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.3981624964 |
|
|
Dec 24 01:25:24 PM PST 23 |
Dec 24 01:27:34 PM PST 23 |
785072782 ps |
| T647 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2404687490 |
|
|
Dec 24 01:22:19 PM PST 23 |
Dec 24 01:27:00 PM PST 23 |
4092872184 ps |
| T648 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4079315386 |
|
|
Dec 24 01:24:36 PM PST 23 |
Dec 24 02:02:45 PM PST 23 |
598242563 ps |
| T649 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3942688474 |
|
|
Dec 24 01:23:50 PM PST 23 |
Dec 24 02:31:53 PM PST 23 |
1156414059 ps |
| T650 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.525058296 |
|
|
Dec 24 01:22:17 PM PST 23 |
Dec 24 01:24:17 PM PST 23 |
2139870263 ps |
| T651 |
/workspace/coverage/default/0.sram_ctrl_smoke.1333050764 |
|
|
Dec 24 01:21:30 PM PST 23 |
Dec 24 01:21:48 PM PST 23 |
1470494840 ps |
| T652 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3324465044 |
|
|
Dec 24 01:22:59 PM PST 23 |
Dec 24 01:36:06 PM PST 23 |
17175801762 ps |
| T653 |
/workspace/coverage/default/8.sram_ctrl_bijection.2610886178 |
|
|
Dec 24 01:22:18 PM PST 23 |
Dec 24 01:30:18 PM PST 23 |
28717743067 ps |
| T654 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4197675586 |
|
|
Dec 24 01:25:51 PM PST 23 |
Dec 24 01:33:08 PM PST 23 |
7187656380 ps |
| T655 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1411636797 |
|
|
Dec 24 01:23:49 PM PST 23 |
Dec 24 01:28:54 PM PST 23 |
86094697900 ps |
| T656 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.2161700140 |
|
|
Dec 24 01:25:24 PM PST 23 |
Dec 24 01:32:40 PM PST 23 |
19238362369 ps |
| T657 |
/workspace/coverage/default/29.sram_ctrl_alert_test.658317525 |
|
|
Dec 24 01:25:17 PM PST 23 |
Dec 24 01:25:18 PM PST 23 |
57703101 ps |
| T658 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.2417356796 |
|
|
Dec 24 01:24:37 PM PST 23 |
Dec 24 01:24:52 PM PST 23 |
3804080774 ps |
| T659 |
/workspace/coverage/default/22.sram_ctrl_alert_test.1084865193 |
|
|
Dec 24 01:24:31 PM PST 23 |
Dec 24 01:24:32 PM PST 23 |
22086187 ps |
| T660 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1044219620 |
|
|
Dec 24 01:23:26 PM PST 23 |
Dec 24 01:23:34 PM PST 23 |
2389168071 ps |
| T661 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3649024713 |
|
|
Dec 24 01:23:28 PM PST 23 |
Dec 24 01:24:27 PM PST 23 |
2911875393 ps |
| T662 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2209719319 |
|
|
Dec 24 01:22:19 PM PST 23 |
Dec 24 01:24:37 PM PST 23 |
7892913106 ps |
| T663 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2200968601 |
|
|
Dec 24 01:25:53 PM PST 23 |
Dec 24 01:27:09 PM PST 23 |
2980278490 ps |
| T664 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2486950309 |
|
|
Dec 24 01:26:06 PM PST 23 |
Dec 24 01:58:52 PM PST 23 |
200738029924 ps |
| T665 |
/workspace/coverage/default/10.sram_ctrl_executable.2903845786 |
|
|
Dec 24 01:23:00 PM PST 23 |
Dec 24 01:36:05 PM PST 23 |
63776495064 ps |
| T666 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4063503109 |
|
|
Dec 24 01:22:07 PM PST 23 |
Dec 24 01:23:08 PM PST 23 |
5562696280 ps |
| T667 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2697657731 |
|
|
Dec 24 01:26:47 PM PST 23 |
Dec 24 01:28:04 PM PST 23 |
1505663707 ps |
| T668 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.219149499 |
|
|
Dec 24 01:22:17 PM PST 23 |
Dec 24 01:30:32 PM PST 23 |
9033672654 ps |
| T669 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.931495612 |
|
|
Dec 24 01:23:30 PM PST 23 |
Dec 24 01:23:47 PM PST 23 |
3036938456 ps |
| T670 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.1218357228 |
|
|
Dec 24 01:24:32 PM PST 23 |
Dec 24 01:25:09 PM PST 23 |
724143024 ps |
| T671 |
/workspace/coverage/default/28.sram_ctrl_partial_access.2058205565 |
|
|
Dec 24 01:26:34 PM PST 23 |
Dec 24 01:26:57 PM PST 23 |
1140240341 ps |
| T672 |
/workspace/coverage/default/35.sram_ctrl_regwen.1358136753 |
|
|
Dec 24 01:26:11 PM PST 23 |
Dec 24 01:41:38 PM PST 23 |
10713632118 ps |
| T673 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2842613000 |
|
|
Dec 24 01:23:30 PM PST 23 |
Dec 24 01:23:47 PM PST 23 |
360999754 ps |
| T674 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3396496396 |
|
|
Dec 24 01:24:46 PM PST 23 |
Dec 24 02:20:14 PM PST 23 |
638828049 ps |
| T675 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1632982539 |
|
|
Dec 24 01:22:58 PM PST 23 |
Dec 24 01:27:18 PM PST 23 |
6716225105 ps |
| T676 |
/workspace/coverage/default/2.sram_ctrl_regwen.1116183546 |
|
|
Dec 24 01:22:01 PM PST 23 |
Dec 24 01:34:30 PM PST 23 |
72347115722 ps |
| T677 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.847260632 |
|
|
Dec 24 01:27:27 PM PST 23 |
Dec 24 02:46:50 PM PST 23 |
2958645171 ps |
| T678 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1465195561 |
|
|
Dec 24 01:24:32 PM PST 23 |
Dec 24 01:25:10 PM PST 23 |
1396728469 ps |
| T679 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.4268138246 |
|
|
Dec 24 01:26:05 PM PST 23 |
Dec 24 01:39:24 PM PST 23 |
8068584538 ps |
| T680 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.726243066 |
|
|
Dec 24 01:22:47 PM PST 23 |
Dec 24 01:24:16 PM PST 23 |
2538098780 ps |
| T681 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3227839069 |
|
|
Dec 24 01:27:16 PM PST 23 |
Dec 24 01:27:45 PM PST 23 |
2767404972 ps |
| T682 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.691861434 |
|
|
Dec 24 01:21:24 PM PST 23 |
Dec 24 01:24:01 PM PST 23 |
4625300039 ps |
| T683 |
/workspace/coverage/default/15.sram_ctrl_regwen.4025684864 |
|
|
Dec 24 01:23:29 PM PST 23 |
Dec 24 01:42:45 PM PST 23 |
3910511011 ps |
| T37 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1260371639 |
|
|
Dec 24 01:21:58 PM PST 23 |
Dec 24 01:22:03 PM PST 23 |
254879705 ps |
| T684 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1301396824 |
|
|
Dec 24 01:26:46 PM PST 23 |
Dec 24 01:26:55 PM PST 23 |
394266669 ps |
| T685 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.416694914 |
|
|
Dec 24 01:24:41 PM PST 23 |
Dec 24 01:29:12 PM PST 23 |
12924551284 ps |
| T686 |
/workspace/coverage/default/34.sram_ctrl_smoke.2527374656 |
|
|
Dec 24 01:25:50 PM PST 23 |
Dec 24 01:27:58 PM PST 23 |
2930037151 ps |
| T687 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3664891110 |
|
|
Dec 24 01:22:03 PM PST 23 |
Dec 24 01:25:50 PM PST 23 |
6773005458 ps |
| T688 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3246201033 |
|
|
Dec 24 01:27:28 PM PST 23 |
Dec 24 01:43:53 PM PST 23 |
33085101327 ps |
| T689 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.4109013538 |
|
|
Dec 24 01:24:35 PM PST 23 |
Dec 24 01:29:43 PM PST 23 |
20668450004 ps |
| T690 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2078826305 |
|
|
Dec 24 01:22:08 PM PST 23 |
Dec 24 01:28:26 PM PST 23 |
5012052526 ps |
| T691 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.633870638 |
|
|
Dec 24 01:25:53 PM PST 23 |
Dec 24 01:31:04 PM PST 23 |
21518016394 ps |
| T692 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3370763998 |
|
|
Dec 24 01:26:58 PM PST 23 |
Dec 24 01:27:14 PM PST 23 |
1411814687 ps |
| T693 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2614112097 |
|
|
Dec 24 01:21:51 PM PST 23 |
Dec 24 01:22:30 PM PST 23 |
15416849379 ps |
| T694 |
/workspace/coverage/default/32.sram_ctrl_executable.1403295429 |
|
|
Dec 24 01:25:33 PM PST 23 |
Dec 24 01:48:09 PM PST 23 |
81577065850 ps |
| T695 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.136412677 |
|
|
Dec 24 01:25:55 PM PST 23 |
Dec 24 01:27:14 PM PST 23 |
962819222 ps |
| T696 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3774451256 |
|
|
Dec 24 01:23:14 PM PST 23 |
Dec 24 01:23:16 PM PST 23 |
33303309 ps |
| T697 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1471635767 |
|
|
Dec 24 01:25:50 PM PST 23 |
Dec 24 01:33:48 PM PST 23 |
31933410686 ps |
| T698 |
/workspace/coverage/default/36.sram_ctrl_regwen.4114505177 |
|
|
Dec 24 01:25:52 PM PST 23 |
Dec 24 01:48:12 PM PST 23 |
29498226335 ps |
| T699 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4109403975 |
|
|
Dec 24 01:27:14 PM PST 23 |
Dec 24 01:28:09 PM PST 23 |
747767649 ps |
| T700 |
/workspace/coverage/default/36.sram_ctrl_bijection.2039202370 |
|
|
Dec 24 01:25:52 PM PST 23 |
Dec 24 01:38:26 PM PST 23 |
693970161100 ps |
| T701 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1061636045 |
|
|
Dec 24 01:21:59 PM PST 23 |
Dec 24 01:53:56 PM PST 23 |
12528316091 ps |
| T702 |
/workspace/coverage/default/6.sram_ctrl_smoke.350030618 |
|
|
Dec 24 01:22:10 PM PST 23 |
Dec 24 01:22:29 PM PST 23 |
744198677 ps |
| T703 |
/workspace/coverage/default/24.sram_ctrl_alert_test.508385067 |
|
|
Dec 24 01:24:30 PM PST 23 |
Dec 24 01:24:32 PM PST 23 |
38954268 ps |
| T704 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.4231660859 |
|
|
Dec 24 01:26:17 PM PST 23 |
Dec 24 01:31:59 PM PST 23 |
53290471994 ps |
| T705 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.645681177 |
|
|
Dec 24 01:27:08 PM PST 23 |
Dec 24 01:31:50 PM PST 23 |
7591930958 ps |
| T706 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2100225998 |
|
|
Dec 24 01:23:28 PM PST 23 |
Dec 24 01:26:06 PM PST 23 |
2835355676 ps |
| T707 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.944374051 |
|
|
Dec 24 01:22:59 PM PST 23 |
Dec 24 01:28:13 PM PST 23 |
19702646546 ps |
| T708 |
/workspace/coverage/default/27.sram_ctrl_smoke.1329946120 |
|
|
Dec 24 01:24:36 PM PST 23 |
Dec 24 01:25:14 PM PST 23 |
2639199866 ps |
| T709 |
/workspace/coverage/default/32.sram_ctrl_bijection.2589241763 |
|
|
Dec 24 01:25:49 PM PST 23 |
Dec 24 02:03:08 PM PST 23 |
127230483576 ps |
| T710 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3167448732 |
|
|
Dec 24 01:22:05 PM PST 23 |
Dec 24 01:27:25 PM PST 23 |
18686161057 ps |
| T711 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.3897192217 |
|
|
Dec 24 01:21:58 PM PST 23 |
Dec 24 01:27:04 PM PST 23 |
20667017644 ps |
| T712 |
/workspace/coverage/default/31.sram_ctrl_smoke.3679015312 |
|
|
Dec 24 01:25:34 PM PST 23 |
Dec 24 01:25:43 PM PST 23 |
1466715874 ps |
| T713 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.143679522 |
|
|
Dec 24 01:26:32 PM PST 23 |
Dec 24 01:27:22 PM PST 23 |
713136936 ps |
| T714 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1653813008 |
|
|
Dec 24 01:23:01 PM PST 23 |
Dec 24 01:29:54 PM PST 23 |
20568424774 ps |
| T715 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1294546087 |
|
|
Dec 24 01:21:59 PM PST 23 |
Dec 24 01:27:55 PM PST 23 |
4176208615 ps |
| T716 |
/workspace/coverage/default/33.sram_ctrl_partial_access.780639191 |
|
|
Dec 24 01:25:50 PM PST 23 |
Dec 24 01:26:40 PM PST 23 |
744403104 ps |
| T717 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1554205247 |
|
|
Dec 24 01:26:47 PM PST 23 |
Dec 24 02:38:03 PM PST 23 |
2021083338 ps |
| T718 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1957737001 |
|
|
Dec 24 01:22:45 PM PST 23 |
Dec 24 01:24:06 PM PST 23 |
1551969012 ps |
| T719 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3486548603 |
|
|
Dec 24 01:22:17 PM PST 23 |
Dec 24 01:23:26 PM PST 23 |
1461132055 ps |
| T720 |
/workspace/coverage/default/40.sram_ctrl_regwen.792933739 |
|
|
Dec 24 01:26:47 PM PST 23 |
Dec 24 01:33:13 PM PST 23 |
7485082961 ps |
| T721 |
/workspace/coverage/default/10.sram_ctrl_partial_access.3222325815 |
|
|
Dec 24 01:23:02 PM PST 23 |
Dec 24 01:23:48 PM PST 23 |
668871631 ps |
| T722 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.4094066942 |
|
|
Dec 24 01:27:00 PM PST 23 |
Dec 24 01:35:44 PM PST 23 |
95692068605 ps |
| T723 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2367337310 |
|
|
Dec 24 01:27:06 PM PST 23 |
Dec 24 01:27:07 PM PST 23 |
29958472 ps |
| T724 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2192230232 |
|
|
Dec 24 01:25:51 PM PST 23 |
Dec 24 01:28:11 PM PST 23 |
1595914306 ps |
| T725 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1618005114 |
|
|
Dec 24 01:27:41 PM PST 23 |
Dec 24 01:30:05 PM PST 23 |
14367983293 ps |
| T726 |
/workspace/coverage/default/40.sram_ctrl_partial_access.2688269375 |
|
|
Dec 24 01:26:46 PM PST 23 |
Dec 24 01:27:09 PM PST 23 |
2055781821 ps |
| T727 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2714302125 |
|
|
Dec 24 01:27:28 PM PST 23 |
Dec 24 01:29:40 PM PST 23 |
8228991147 ps |
| T728 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2032471612 |
|
|
Dec 24 01:26:46 PM PST 23 |
Dec 24 01:31:47 PM PST 23 |
24577054068 ps |
| T729 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3823981254 |
|
|
Dec 24 01:23:13 PM PST 23 |
Dec 24 01:25:23 PM PST 23 |
7902126384 ps |
| T730 |
/workspace/coverage/default/29.sram_ctrl_smoke.3981539349 |
|
|
Dec 24 01:26:35 PM PST 23 |
Dec 24 01:27:54 PM PST 23 |
2499733496 ps |
| T731 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1444147096 |
|
|
Dec 24 01:23:28 PM PST 23 |
Dec 24 01:25:01 PM PST 23 |
763305044 ps |
| T732 |
/workspace/coverage/default/20.sram_ctrl_regwen.3337731766 |
|
|
Dec 24 01:24:26 PM PST 23 |
Dec 24 01:34:04 PM PST 23 |
8770100083 ps |
| T733 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1764185072 |
|
|
Dec 24 01:26:55 PM PST 23 |
Dec 24 01:29:54 PM PST 23 |
23976599685 ps |
| T734 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2769222514 |
|
|
Dec 24 01:23:25 PM PST 23 |
Dec 24 01:30:27 PM PST 23 |
25848640329 ps |
| T735 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4272453512 |
|
|
Dec 24 01:26:58 PM PST 23 |
Dec 24 01:48:01 PM PST 23 |
15528735025 ps |
| T736 |
/workspace/coverage/default/37.sram_ctrl_partial_access.3181619584 |
|
|
Dec 24 01:26:06 PM PST 23 |
Dec 24 01:26:39 PM PST 23 |
1727064820 ps |
| T737 |
/workspace/coverage/default/42.sram_ctrl_executable.570334241 |
|
|
Dec 24 01:26:49 PM PST 23 |
Dec 24 01:56:46 PM PST 23 |
101502828345 ps |
| T738 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2164687150 |
|
|
Dec 24 01:26:58 PM PST 23 |
Dec 24 01:27:53 PM PST 23 |
2977578307 ps |
| T739 |
/workspace/coverage/default/27.sram_ctrl_executable.2221031567 |
|
|
Dec 24 01:24:46 PM PST 23 |
Dec 24 01:44:57 PM PST 23 |
27543882654 ps |
| T740 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.2390166747 |
|
|
Dec 24 01:24:26 PM PST 23 |
Dec 24 01:27:01 PM PST 23 |
10322016798 ps |
| T741 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2169286440 |
|
|
Dec 24 01:24:46 PM PST 23 |
Dec 24 01:27:00 PM PST 23 |
3186846525 ps |
| T742 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2153420284 |
|
|
Dec 24 01:23:00 PM PST 23 |
Dec 24 01:26:10 PM PST 23 |
5269600762 ps |
| T743 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2393424380 |
|
|
Dec 24 01:26:05 PM PST 23 |
Dec 24 01:28:54 PM PST 23 |
819441513 ps |
| T744 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1604171993 |
|
|
Dec 24 01:23:14 PM PST 23 |
Dec 24 01:44:35 PM PST 23 |
38794550903 ps |
| T745 |
/workspace/coverage/default/19.sram_ctrl_partial_access.1166211327 |
|
|
Dec 24 01:23:50 PM PST 23 |
Dec 24 01:24:07 PM PST 23 |
812984713 ps |
| T746 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.353917004 |
|
|
Dec 24 01:23:39 PM PST 23 |
Dec 24 01:24:17 PM PST 23 |
724253230 ps |
| T747 |
/workspace/coverage/default/45.sram_ctrl_partial_access.1429081969 |
|
|
Dec 24 01:27:02 PM PST 23 |
Dec 24 01:27:26 PM PST 23 |
1185751258 ps |
| T748 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2080556080 |
|
|
Dec 24 01:26:45 PM PST 23 |
Dec 24 01:26:48 PM PST 23 |
18770316 ps |
| T749 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.1573225115 |
|
|
Dec 24 01:26:05 PM PST 23 |
Dec 24 01:28:50 PM PST 23 |
270865234277 ps |
| T750 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3738204159 |
|
|
Dec 24 01:23:29 PM PST 23 |
Dec 24 01:40:47 PM PST 23 |
24030381074 ps |