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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total test records in report: 983
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T751 /workspace/coverage/default/16.sram_ctrl_lc_escalation.442341233 Dec 24 01:23:32 PM PST 23 Dec 24 01:24:32 PM PST 23 12063339435 ps
T752 /workspace/coverage/default/49.sram_ctrl_multiple_keys.2617411980 Dec 24 01:27:28 PM PST 23 Dec 24 01:48:36 PM PST 23 51351806008 ps
T753 /workspace/coverage/default/36.sram_ctrl_executable.169222321 Dec 24 01:25:53 PM PST 23 Dec 24 01:54:50 PM PST 23 150808508313 ps
T754 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3767025006 Dec 24 01:24:33 PM PST 23 Dec 24 01:25:55 PM PST 23 9379611254 ps
T755 /workspace/coverage/default/38.sram_ctrl_regwen.2023758764 Dec 24 01:26:04 PM PST 23 Dec 24 01:42:24 PM PST 23 2901665492 ps
T756 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2606375805 Dec 24 01:24:34 PM PST 23 Dec 24 01:28:42 PM PST 23 6130003561 ps
T757 /workspace/coverage/default/2.sram_ctrl_mem_walk.597073436 Dec 24 01:21:58 PM PST 23 Dec 24 01:24:24 PM PST 23 14368348429 ps
T758 /workspace/coverage/default/1.sram_ctrl_bijection.945286837 Dec 24 01:22:03 PM PST 23 Dec 24 01:39:53 PM PST 23 216143278258 ps
T759 /workspace/coverage/default/39.sram_ctrl_partial_access.3445208519 Dec 24 01:26:32 PM PST 23 Dec 24 01:28:38 PM PST 23 1652206056 ps
T760 /workspace/coverage/default/16.sram_ctrl_multiple_keys.4156657693 Dec 24 01:23:29 PM PST 23 Dec 24 01:46:29 PM PST 23 10035728384 ps
T761 /workspace/coverage/default/42.sram_ctrl_smoke.2782549547 Dec 24 01:26:47 PM PST 23 Dec 24 01:27:05 PM PST 23 2010522923 ps
T762 /workspace/coverage/default/34.sram_ctrl_bijection.2447028450 Dec 24 01:25:50 PM PST 23 Dec 24 01:41:19 PM PST 23 92400361972 ps
T763 /workspace/coverage/default/49.sram_ctrl_bijection.131793787 Dec 24 01:27:28 PM PST 23 Dec 24 01:50:06 PM PST 23 82990171180 ps
T764 /workspace/coverage/default/10.sram_ctrl_mem_walk.3676810092 Dec 24 01:23:02 PM PST 23 Dec 24 01:25:25 PM PST 23 7183643581 ps
T765 /workspace/coverage/default/0.sram_ctrl_regwen.1236076247 Dec 24 01:21:30 PM PST 23 Dec 24 01:46:20 PM PST 23 3858748732 ps
T766 /workspace/coverage/default/16.sram_ctrl_bijection.1337934406 Dec 24 01:23:29 PM PST 23 Dec 24 02:08:12 PM PST 23 160201960304 ps
T767 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1906185618 Dec 24 01:23:32 PM PST 23 Dec 24 01:26:16 PM PST 23 4537143791 ps
T768 /workspace/coverage/default/28.sram_ctrl_regwen.357592772 Dec 24 01:24:47 PM PST 23 Dec 24 01:51:39 PM PST 23 8838879109 ps
T769 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1053296656 Dec 24 01:23:14 PM PST 23 Dec 24 01:23:54 PM PST 23 731936294 ps
T770 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2157202785 Dec 24 01:26:05 PM PST 23 Dec 24 01:27:12 PM PST 23 1468598849 ps
T771 /workspace/coverage/default/49.sram_ctrl_stress_all.2580419151 Dec 24 01:27:43 PM PST 23 Dec 24 02:21:39 PM PST 23 63363483246 ps
T772 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1991177560 Dec 24 01:23:30 PM PST 23 Dec 24 01:31:27 PM PST 23 40081205334 ps
T773 /workspace/coverage/default/5.sram_ctrl_alert_test.865016981 Dec 24 01:22:07 PM PST 23 Dec 24 01:22:10 PM PST 23 38853055 ps
T774 /workspace/coverage/default/34.sram_ctrl_mem_walk.3743365016 Dec 24 01:26:05 PM PST 23 Dec 24 01:28:21 PM PST 23 7594641469 ps
T775 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2761658517 Dec 24 01:23:01 PM PST 23 Dec 24 01:26:46 PM PST 23 7215792293 ps
T776 /workspace/coverage/default/40.sram_ctrl_executable.1442616401 Dec 24 01:26:47 PM PST 23 Dec 24 01:54:23 PM PST 23 72986445191 ps
T777 /workspace/coverage/default/27.sram_ctrl_ram_cfg.1167149945 Dec 24 01:24:47 PM PST 23 Dec 24 01:24:55 PM PST 23 1342704891 ps
T778 /workspace/coverage/default/25.sram_ctrl_lc_escalation.3152927800 Dec 24 01:24:31 PM PST 23 Dec 24 01:26:23 PM PST 23 44953789966 ps
T779 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1009119161 Dec 24 01:26:45 PM PST 23 Dec 24 01:35:14 PM PST 23 23928142001 ps
T780 /workspace/coverage/default/8.sram_ctrl_stress_all.1337761516 Dec 24 01:22:46 PM PST 23 Dec 24 02:41:31 PM PST 23 73479933136 ps
T781 /workspace/coverage/default/47.sram_ctrl_partial_access.1904992885 Dec 24 01:27:12 PM PST 23 Dec 24 01:28:35 PM PST 23 1124156614 ps
T782 /workspace/coverage/default/49.sram_ctrl_lc_escalation.3004468930 Dec 24 01:27:42 PM PST 23 Dec 24 01:28:57 PM PST 23 38470985345 ps
T783 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2426038609 Dec 24 01:22:41 PM PST 23 Dec 24 01:28:28 PM PST 23 24628477870 ps
T784 /workspace/coverage/default/5.sram_ctrl_max_throughput.150229360 Dec 24 01:22:06 PM PST 23 Dec 24 01:25:03 PM PST 23 2008733107 ps
T785 /workspace/coverage/default/18.sram_ctrl_alert_test.4215516753 Dec 24 01:23:34 PM PST 23 Dec 24 01:23:37 PM PST 23 50926220 ps
T786 /workspace/coverage/default/31.sram_ctrl_max_throughput.1160021033 Dec 24 01:25:26 PM PST 23 Dec 24 01:28:26 PM PST 23 3062797951 ps
T787 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2410151991 Dec 24 01:26:45 PM PST 23 Dec 24 01:55:30 PM PST 23 32725460798 ps
T788 /workspace/coverage/default/5.sram_ctrl_bijection.3987297113 Dec 24 01:22:06 PM PST 23 Dec 24 01:35:38 PM PST 23 154594914894 ps
T789 /workspace/coverage/default/32.sram_ctrl_ram_cfg.1676236725 Dec 24 01:25:51 PM PST 23 Dec 24 01:26:00 PM PST 23 358594677 ps
T790 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1273369048 Dec 24 01:24:53 PM PST 23 Dec 24 01:25:21 PM PST 23 3980545993 ps
T791 /workspace/coverage/default/19.sram_ctrl_alert_test.3946053274 Dec 24 01:23:50 PM PST 23 Dec 24 01:23:52 PM PST 23 30954685 ps
T792 /workspace/coverage/default/43.sram_ctrl_partial_access.893335453 Dec 24 01:26:48 PM PST 23 Dec 24 01:27:17 PM PST 23 1333934782 ps
T793 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.4184746799 Dec 24 01:25:24 PM PST 23 Dec 24 01:27:06 PM PST 23 1552892185 ps
T794 /workspace/coverage/default/9.sram_ctrl_mem_walk.512980431 Dec 24 01:22:56 PM PST 23 Dec 24 01:25:06 PM PST 23 2081106031 ps
T795 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1868813840 Dec 24 01:22:56 PM PST 23 Dec 24 01:25:49 PM PST 23 1286361826 ps
T796 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3879079317 Dec 24 01:24:35 PM PST 23 Dec 24 01:33:14 PM PST 23 47229272011 ps
T797 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2269435862 Dec 24 01:22:06 PM PST 23 Dec 24 01:22:45 PM PST 23 2799677194 ps
T798 /workspace/coverage/default/8.sram_ctrl_max_throughput.4001330818 Dec 24 01:22:18 PM PST 23 Dec 24 01:23:05 PM PST 23 732890836 ps
T799 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1086940938 Dec 24 01:23:46 PM PST 23 Dec 24 01:24:42 PM PST 23 3014511591 ps
T800 /workspace/coverage/default/4.sram_ctrl_smoke.1946937452 Dec 24 01:22:04 PM PST 23 Dec 24 01:22:33 PM PST 23 648799016 ps
T801 /workspace/coverage/default/11.sram_ctrl_partial_access.3907931672 Dec 24 01:23:03 PM PST 23 Dec 24 01:25:31 PM PST 23 1004731039 ps
T802 /workspace/coverage/default/7.sram_ctrl_stress_all.1374701088 Dec 24 01:22:18 PM PST 23 Dec 24 02:01:02 PM PST 23 145595045512 ps
T803 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3121415702 Dec 24 01:22:10 PM PST 23 Dec 24 02:31:05 PM PST 23 7613510755 ps
T804 /workspace/coverage/default/48.sram_ctrl_lc_escalation.594636044 Dec 24 01:27:26 PM PST 23 Dec 24 01:28:40 PM PST 23 7923026825 ps
T805 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.869971113 Dec 24 01:26:47 PM PST 23 Dec 24 02:22:21 PM PST 23 729172230 ps
T806 /workspace/coverage/default/27.sram_ctrl_partial_access.4082859449 Dec 24 01:24:36 PM PST 23 Dec 24 01:25:46 PM PST 23 799403281 ps
T807 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.804252113 Dec 24 01:23:35 PM PST 23 Dec 24 01:30:50 PM PST 23 98854386269 ps
T808 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1671417883 Dec 24 01:26:40 PM PST 23 Dec 24 01:30:25 PM PST 23 2843349500 ps
T809 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3308036753 Dec 24 01:22:45 PM PST 23 Dec 24 01:24:12 PM PST 23 1752676584 ps
T810 /workspace/coverage/default/1.sram_ctrl_max_throughput.613015460 Dec 24 01:22:00 PM PST 23 Dec 24 01:22:36 PM PST 23 13573652554 ps
T811 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.60305671 Dec 24 01:22:57 PM PST 23 Dec 24 01:49:16 PM PST 23 3447554709 ps
T812 /workspace/coverage/default/44.sram_ctrl_partial_access.1306773430 Dec 24 01:26:59 PM PST 23 Dec 24 01:27:34 PM PST 23 1788311035 ps
T813 /workspace/coverage/default/33.sram_ctrl_alert_test.2250871210 Dec 24 01:25:50 PM PST 23 Dec 24 01:25:54 PM PST 23 37802234 ps
T814 /workspace/coverage/default/25.sram_ctrl_mem_walk.455327724 Dec 24 01:24:35 PM PST 23 Dec 24 01:30:57 PM PST 23 229324529574 ps
T815 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.279336761 Dec 24 01:26:11 PM PST 23 Dec 24 01:31:54 PM PST 23 19000270692 ps
T816 /workspace/coverage/default/27.sram_ctrl_mem_walk.1580898139 Dec 24 01:24:51 PM PST 23 Dec 24 01:27:18 PM PST 23 24566299473 ps
T817 /workspace/coverage/default/24.sram_ctrl_bijection.3534452529 Dec 24 01:24:32 PM PST 23 Dec 24 01:32:32 PM PST 23 13272747491 ps
T818 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.4082735776 Dec 24 01:24:51 PM PST 23 Dec 24 02:57:09 PM PST 23 947104301 ps
T819 /workspace/coverage/default/10.sram_ctrl_smoke.3514595916 Dec 24 01:22:39 PM PST 23 Dec 24 01:23:07 PM PST 23 7637096356 ps
T820 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.849171414 Dec 24 01:26:04 PM PST 23 Dec 24 01:27:22 PM PST 23 9444469127 ps
T821 /workspace/coverage/default/31.sram_ctrl_ram_cfg.1411096860 Dec 24 01:25:50 PM PST 23 Dec 24 01:26:00 PM PST 23 345911693 ps
T822 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1618555439 Dec 24 01:21:56 PM PST 23 Dec 24 01:23:11 PM PST 23 998386297 ps
T823 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3391767270 Dec 24 01:26:45 PM PST 23 Dec 24 01:29:10 PM PST 23 4370421706 ps
T824 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3503052569 Dec 24 01:23:27 PM PST 23 Dec 24 01:31:19 PM PST 23 7526210936 ps
T825 /workspace/coverage/default/36.sram_ctrl_mem_walk.3470404395 Dec 24 01:26:15 PM PST 23 Dec 24 01:28:15 PM PST 23 2025876141 ps
T826 /workspace/coverage/default/10.sram_ctrl_alert_test.2541967473 Dec 24 01:22:56 PM PST 23 Dec 24 01:22:58 PM PST 23 79894752 ps
T827 /workspace/coverage/default/0.sram_ctrl_max_throughput.3754858246 Dec 24 01:21:29 PM PST 23 Dec 24 01:22:30 PM PST 23 761513642 ps
T828 /workspace/coverage/default/6.sram_ctrl_alert_test.2293342710 Dec 24 01:22:20 PM PST 23 Dec 24 01:22:25 PM PST 23 20443703 ps
T829 /workspace/coverage/default/5.sram_ctrl_mem_walk.986595257 Dec 24 01:22:06 PM PST 23 Dec 24 01:24:44 PM PST 23 27609607694 ps
T830 /workspace/coverage/default/4.sram_ctrl_bijection.1597221082 Dec 24 01:22:03 PM PST 23 Dec 24 01:42:33 PM PST 23 17392485150 ps
T831 /workspace/coverage/default/45.sram_ctrl_max_throughput.428821275 Dec 24 01:27:01 PM PST 23 Dec 24 01:29:17 PM PST 23 3987818285 ps
T832 /workspace/coverage/default/28.sram_ctrl_ram_cfg.2441495037 Dec 24 01:24:47 PM PST 23 Dec 24 01:25:02 PM PST 23 994013662 ps
T833 /workspace/coverage/default/5.sram_ctrl_smoke.4208566217 Dec 24 01:22:06 PM PST 23 Dec 24 01:22:36 PM PST 23 1047787952 ps
T834 /workspace/coverage/default/31.sram_ctrl_stress_all.2686831989 Dec 24 01:25:49 PM PST 23 Dec 24 02:12:26 PM PST 23 257387240671 ps
T835 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2716579593 Dec 24 01:23:27 PM PST 23 Dec 24 02:21:32 PM PST 23 3207351656 ps
T836 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1290970762 Dec 24 01:25:50 PM PST 23 Dec 24 02:25:48 PM PST 23 236170512 ps
T837 /workspace/coverage/default/21.sram_ctrl_smoke.61518712 Dec 24 01:24:33 PM PST 23 Dec 24 01:25:03 PM PST 23 6472254828 ps
T838 /workspace/coverage/default/0.sram_ctrl_ram_cfg.182142004 Dec 24 01:21:30 PM PST 23 Dec 24 01:21:37 PM PST 23 698694600 ps
T839 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.780181836 Dec 24 01:23:26 PM PST 23 Dec 24 01:43:12 PM PST 23 27900974105 ps
T840 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1908082662 Dec 24 01:23:41 PM PST 23 Dec 24 01:24:59 PM PST 23 993973898 ps
T841 /workspace/coverage/default/19.sram_ctrl_multiple_keys.810720988 Dec 24 01:23:50 PM PST 23 Dec 24 01:42:07 PM PST 23 89627020202 ps
T842 /workspace/coverage/default/26.sram_ctrl_stress_all.1111018714 Dec 24 01:24:37 PM PST 23 Dec 24 01:58:00 PM PST 23 22074357019 ps
T843 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.924302327 Dec 24 01:22:19 PM PST 23 Dec 24 01:23:45 PM PST 23 5349887788 ps
T844 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3128949071 Dec 24 01:27:40 PM PST 23 Dec 24 01:34:00 PM PST 23 20963300420 ps
T845 /workspace/coverage/default/38.sram_ctrl_smoke.47417337 Dec 24 01:26:09 PM PST 23 Dec 24 01:29:11 PM PST 23 807844742 ps
T846 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3065689021 Dec 24 01:23:49 PM PST 23 Dec 24 01:25:21 PM PST 23 1513194123 ps
T847 /workspace/coverage/default/32.sram_ctrl_partial_access.3845137871 Dec 24 01:25:33 PM PST 23 Dec 24 01:26:03 PM PST 23 1694516259 ps
T848 /workspace/coverage/default/0.sram_ctrl_mem_walk.2044381473 Dec 24 01:21:29 PM PST 23 Dec 24 01:26:11 PM PST 23 14368120893 ps
T849 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2282414565 Dec 24 01:26:33 PM PST 23 Dec 24 01:28:46 PM PST 23 3159489464 ps
T850 /workspace/coverage/default/7.sram_ctrl_max_throughput.3781946701 Dec 24 01:22:18 PM PST 23 Dec 24 01:23:16 PM PST 23 1490672560 ps
T851 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.289632561 Dec 24 01:23:14 PM PST 23 Dec 24 01:27:32 PM PST 23 38585033357 ps
T852 /workspace/coverage/default/18.sram_ctrl_mem_walk.703344667 Dec 24 01:23:36 PM PST 23 Dec 24 01:28:34 PM PST 23 55057356157 ps
T853 /workspace/coverage/default/11.sram_ctrl_max_throughput.3152799740 Dec 24 01:23:13 PM PST 23 Dec 24 01:24:18 PM PST 23 1539369384 ps
T854 /workspace/coverage/default/12.sram_ctrl_smoke.341891378 Dec 24 01:23:03 PM PST 23 Dec 24 01:24:07 PM PST 23 3622932223 ps
T855 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3414706227 Dec 24 01:27:00 PM PST 23 Dec 24 01:30:45 PM PST 23 2738038340 ps
T856 /workspace/coverage/default/24.sram_ctrl_ram_cfg.2459376543 Dec 24 01:24:33 PM PST 23 Dec 24 01:24:41 PM PST 23 1357031305 ps
T857 /workspace/coverage/default/11.sram_ctrl_alert_test.3482318110 Dec 24 01:22:58 PM PST 23 Dec 24 01:23:00 PM PST 23 191259381 ps
T858 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2744435910 Dec 24 01:23:29 PM PST 23 Dec 24 01:29:15 PM PST 23 21450171537 ps
T859 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.4267182060 Dec 24 01:23:32 PM PST 23 Dec 24 02:59:15 PM PST 23 1116827095 ps
T860 /workspace/coverage/default/49.sram_ctrl_smoke.136600681 Dec 24 01:27:27 PM PST 23 Dec 24 01:27:48 PM PST 23 1646145069 ps
T861 /workspace/coverage/default/12.sram_ctrl_max_throughput.3736197895 Dec 24 01:23:13 PM PST 23 Dec 24 01:24:49 PM PST 23 783374712 ps
T862 /workspace/coverage/default/49.sram_ctrl_max_throughput.1641985314 Dec 24 01:27:43 PM PST 23 Dec 24 01:28:42 PM PST 23 2388582878 ps
T863 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.4255554580 Dec 24 01:26:57 PM PST 23 Dec 24 01:41:24 PM PST 23 8620518532 ps
T864 /workspace/coverage/default/41.sram_ctrl_stress_all.896179932 Dec 24 01:26:47 PM PST 23 Dec 24 03:19:15 PM PST 23 924760988848 ps
T865 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.4077198490 Dec 24 01:25:32 PM PST 23 Dec 24 01:26:12 PM PST 23 2944184506 ps
T866 /workspace/coverage/default/8.sram_ctrl_multiple_keys.2485641764 Dec 24 01:22:18 PM PST 23 Dec 24 01:33:36 PM PST 23 7643935705 ps
T867 /workspace/coverage/default/20.sram_ctrl_mem_walk.245920614 Dec 24 01:24:25 PM PST 23 Dec 24 01:26:29 PM PST 23 8591576153 ps
T868 /workspace/coverage/default/20.sram_ctrl_lc_escalation.3660158893 Dec 24 01:23:40 PM PST 23 Dec 24 01:25:13 PM PST 23 37007362034 ps
T869 /workspace/coverage/default/17.sram_ctrl_smoke.2353486952 Dec 24 01:23:29 PM PST 23 Dec 24 01:26:05 PM PST 23 6021110768 ps
T870 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3999670906 Dec 24 01:24:31 PM PST 23 Dec 24 01:30:56 PM PST 23 52703310360 ps
T871 /workspace/coverage/default/22.sram_ctrl_lc_escalation.3183202648 Dec 24 01:24:27 PM PST 23 Dec 24 01:26:14 PM PST 23 9838747775 ps
T872 /workspace/coverage/default/20.sram_ctrl_partial_access.4225813496 Dec 24 01:23:41 PM PST 23 Dec 24 01:24:08 PM PST 23 5088271884 ps
T873 /workspace/coverage/default/10.sram_ctrl_bijection.3021222361 Dec 24 01:22:48 PM PST 23 Dec 24 01:51:27 PM PST 23 73751611474 ps
T874 /workspace/coverage/default/1.sram_ctrl_multiple_keys.1763799174 Dec 24 01:21:52 PM PST 23 Dec 24 01:36:54 PM PST 23 72039825826 ps
T875 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2072390226 Dec 24 01:26:47 PM PST 23 Dec 24 01:48:51 PM PST 23 14305110783 ps
T876 /workspace/coverage/default/0.sram_ctrl_bijection.1420865751 Dec 24 01:21:30 PM PST 23 Dec 24 02:03:55 PM PST 23 230297862509 ps
T877 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.559869931 Dec 24 01:22:04 PM PST 23 Dec 24 01:23:15 PM PST 23 7164350012 ps
T878 /workspace/coverage/default/41.sram_ctrl_ram_cfg.2564193742 Dec 24 01:26:48 PM PST 23 Dec 24 01:27:05 PM PST 23 358585599 ps
T879 /workspace/coverage/default/17.sram_ctrl_regwen.1995562737 Dec 24 01:23:25 PM PST 23 Dec 24 01:32:13 PM PST 23 37535882106 ps
T880 /workspace/coverage/default/23.sram_ctrl_multiple_keys.1363583124 Dec 24 01:24:31 PM PST 23 Dec 24 01:31:44 PM PST 23 21541355304 ps
T881 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2752743508 Dec 24 01:21:23 PM PST 23 Dec 24 02:32:01 PM PST 23 3945283981 ps
T882 /workspace/coverage/default/5.sram_ctrl_executable.2761221153 Dec 24 01:22:07 PM PST 23 Dec 24 01:26:04 PM PST 23 3053420362 ps
T883 /workspace/coverage/default/49.sram_ctrl_executable.459597569 Dec 24 01:27:41 PM PST 23 Dec 24 01:37:11 PM PST 23 31342140433 ps
T884 /workspace/coverage/default/40.sram_ctrl_lc_escalation.3194343517 Dec 24 01:26:46 PM PST 23 Dec 24 01:28:10 PM PST 23 64397798861 ps
T885 /workspace/coverage/default/17.sram_ctrl_mem_walk.1437573843 Dec 24 01:23:27 PM PST 23 Dec 24 01:28:51 PM PST 23 121461313122 ps
T886 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3542891741 Dec 24 01:25:16 PM PST 23 Dec 24 02:15:31 PM PST 23 17437535445 ps
T887 /workspace/coverage/default/11.sram_ctrl_lc_escalation.805238652 Dec 24 01:23:05 PM PST 23 Dec 24 01:26:40 PM PST 23 18813960853 ps
T888 /workspace/coverage/default/3.sram_ctrl_max_throughput.2961239946 Dec 24 01:22:04 PM PST 23 Dec 24 01:23:34 PM PST 23 740091329 ps
T889 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.4252784346 Dec 24 01:23:46 PM PST 23 Dec 24 01:34:33 PM PST 23 8370349829 ps
T890 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4029981212 Dec 24 01:25:53 PM PST 23 Dec 24 02:09:23 PM PST 23 278252062 ps
T891 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2774256920 Dec 24 01:23:33 PM PST 23 Dec 24 01:26:09 PM PST 23 16325801347 ps
T892 /workspace/coverage/default/27.sram_ctrl_alert_test.1863834730 Dec 24 01:24:46 PM PST 23 Dec 24 01:24:48 PM PST 23 67030758 ps
T893 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2928297749 Dec 24 01:22:18 PM PST 23 Dec 24 01:24:51 PM PST 23 1740122637 ps
T894 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1223825217 Dec 24 01:23:00 PM PST 23 Dec 24 01:23:39 PM PST 23 2792486550 ps
T895 /workspace/coverage/default/14.sram_ctrl_partial_access.1230378426 Dec 24 01:23:29 PM PST 23 Dec 24 01:25:45 PM PST 23 1694020795 ps
T896 /workspace/coverage/default/14.sram_ctrl_executable.4094508465 Dec 24 01:23:28 PM PST 23 Dec 24 01:53:39 PM PST 23 48763998203 ps
T897 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2048129187 Dec 24 01:25:52 PM PST 23 Dec 24 01:27:58 PM PST 23 28207042623 ps
T898 /workspace/coverage/default/34.sram_ctrl_regwen.467800838 Dec 24 01:26:04 PM PST 23 Dec 24 01:42:51 PM PST 23 9213072327 ps
T899 /workspace/coverage/default/28.sram_ctrl_bijection.1520028091 Dec 24 01:24:48 PM PST 23 Dec 24 02:08:40 PM PST 23 920316526810 ps
T900 /workspace/coverage/default/20.sram_ctrl_alert_test.1814025228 Dec 24 01:24:26 PM PST 23 Dec 24 01:24:27 PM PST 23 23782687 ps
T901 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3151295695 Dec 24 01:23:29 PM PST 23 Dec 24 01:23:45 PM PST 23 1348265373 ps
T902 /workspace/coverage/default/36.sram_ctrl_stress_all.3001317703 Dec 24 01:26:06 PM PST 23 Dec 24 02:46:33 PM PST 23 183554634941 ps
T903 /workspace/coverage/default/42.sram_ctrl_alert_test.502743899 Dec 24 01:26:48 PM PST 23 Dec 24 01:26:52 PM PST 23 115467256 ps
T904 /workspace/coverage/default/34.sram_ctrl_alert_test.3151764195 Dec 24 01:26:05 PM PST 23 Dec 24 01:26:08 PM PST 23 51636400 ps
T905 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3038256684 Dec 24 01:25:49 PM PST 23 Dec 24 01:27:30 PM PST 23 1433129229 ps
T906 /workspace/coverage/default/25.sram_ctrl_ram_cfg.4052435239 Dec 24 01:24:33 PM PST 23 Dec 24 01:24:48 PM PST 23 1303429913 ps
T907 /workspace/coverage/default/28.sram_ctrl_multiple_keys.3928270947 Dec 24 01:26:32 PM PST 23 Dec 24 01:40:25 PM PST 23 24997609806 ps
T908 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1677972851 Dec 24 01:24:30 PM PST 23 Dec 24 01:29:04 PM PST 23 3651964271 ps
T909 /workspace/coverage/default/46.sram_ctrl_regwen.1944803275 Dec 24 01:27:08 PM PST 23 Dec 24 01:53:51 PM PST 23 69479230567 ps
T910 /workspace/coverage/default/17.sram_ctrl_alert_test.3980925003 Dec 24 01:23:30 PM PST 23 Dec 24 01:23:34 PM PST 23 16490390 ps
T911 /workspace/coverage/default/9.sram_ctrl_lc_escalation.1444275042 Dec 24 01:22:40 PM PST 23 Dec 24 01:24:13 PM PST 23 32867115496 ps
T912 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.757863420 Dec 24 01:24:30 PM PST 23 Dec 24 01:55:23 PM PST 23 118083803 ps
T913 /workspace/coverage/default/42.sram_ctrl_ram_cfg.3475261475 Dec 24 01:26:45 PM PST 23 Dec 24 01:27:00 PM PST 23 1403201894 ps
T914 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2914485235 Dec 24 01:25:26 PM PST 23 Dec 24 02:02:24 PM PST 23 34389538353 ps
T915 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.821608283 Dec 24 01:21:24 PM PST 23 Dec 24 01:22:51 PM PST 23 3413779941 ps
T916 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.168719130 Dec 24 01:27:00 PM PST 23 Dec 24 01:28:41 PM PST 23 15074723224 ps
T917 /workspace/coverage/default/37.sram_ctrl_regwen.32561341 Dec 24 01:26:13 PM PST 23 Dec 24 01:45:52 PM PST 23 36369004351 ps
T918 /workspace/coverage/default/30.sram_ctrl_alert_test.1085570241 Dec 24 01:25:23 PM PST 23 Dec 24 01:25:27 PM PST 23 17380159 ps
T919 /workspace/coverage/default/40.sram_ctrl_smoke.766146625 Dec 24 01:26:32 PM PST 23 Dec 24 01:26:55 PM PST 23 5184215264 ps
T920 /workspace/coverage/default/1.sram_ctrl_alert_test.1322148141 Dec 24 01:21:58 PM PST 23 Dec 24 01:22:00 PM PST 23 17695274 ps
T921 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4142386458 Dec 24 01:24:35 PM PST 23 Dec 24 01:26:22 PM PST 23 1774854736 ps
T922 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2950661400 Dec 24 01:27:27 PM PST 23 Dec 24 01:32:35 PM PST 23 5999640844 ps
T923 /workspace/coverage/default/48.sram_ctrl_alert_test.3342898186 Dec 24 01:27:27 PM PST 23 Dec 24 01:27:28 PM PST 23 18248243 ps
T924 /workspace/coverage/default/8.sram_ctrl_mem_walk.2570209667 Dec 24 01:22:44 PM PST 23 Dec 24 01:25:30 PM PST 23 49134782651 ps
T925 /workspace/coverage/default/7.sram_ctrl_smoke.1733098439 Dec 24 01:22:20 PM PST 23 Dec 24 01:22:45 PM PST 23 597623397 ps
T926 /workspace/coverage/default/22.sram_ctrl_stress_all.1690390180 Dec 24 01:24:33 PM PST 23 Dec 24 02:44:43 PM PST 23 72900758147 ps
T927 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.822997796 Dec 24 01:27:28 PM PST 23 Dec 24 01:29:39 PM PST 23 1618491278 ps
T928 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2591099050 Dec 24 01:24:33 PM PST 23 Dec 24 01:33:25 PM PST 23 81189033126 ps
T929 /workspace/coverage/default/1.sram_ctrl_smoke.3857728164 Dec 24 01:21:57 PM PST 23 Dec 24 01:22:11 PM PST 23 763522344 ps
T930 /workspace/coverage/default/16.sram_ctrl_partial_access.229114250 Dec 24 01:23:29 PM PST 23 Dec 24 01:24:23 PM PST 23 2054258299 ps
T931 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2834280995 Dec 24 01:22:57 PM PST 23 Dec 24 01:28:39 PM PST 23 26533425937 ps
T932 /workspace/coverage/default/18.sram_ctrl_regwen.1615197401 Dec 24 01:23:41 PM PST 23 Dec 24 01:30:45 PM PST 23 2969841108 ps
T933 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.4103658648 Dec 24 01:26:05 PM PST 23 Dec 24 01:27:30 PM PST 23 8664957756 ps
T934 /workspace/coverage/default/7.sram_ctrl_multiple_keys.4206165098 Dec 24 01:22:17 PM PST 23 Dec 24 01:33:18 PM PST 23 27627096066 ps
T935 /workspace/coverage/default/29.sram_ctrl_max_throughput.3062283767 Dec 24 01:24:49 PM PST 23 Dec 24 01:28:15 PM PST 23 784541881 ps
T936 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1428785766 Dec 24 01:27:02 PM PST 23 Dec 24 01:33:56 PM PST 23 5481236289 ps
T937 /workspace/coverage/default/23.sram_ctrl_executable.1343103591 Dec 24 01:24:36 PM PST 23 Dec 24 01:45:42 PM PST 23 97968020947 ps
T938 /workspace/coverage/default/49.sram_ctrl_regwen.2680318742 Dec 24 01:27:40 PM PST 23 Dec 24 01:50:27 PM PST 23 22000554297 ps
T939 /workspace/coverage/default/46.sram_ctrl_mem_walk.1913431731 Dec 24 01:27:16 PM PST 23 Dec 24 01:32:28 PM PST 23 62576305193 ps
T940 /workspace/coverage/default/19.sram_ctrl_smoke.2440467962 Dec 24 01:23:35 PM PST 23 Dec 24 01:23:43 PM PST 23 755717149 ps
T941 /workspace/coverage/default/46.sram_ctrl_alert_test.2105275474 Dec 24 01:27:06 PM PST 23 Dec 24 01:27:07 PM PST 23 155962835 ps
T942 /workspace/coverage/default/14.sram_ctrl_stress_all.3705509124 Dec 24 01:23:32 PM PST 23 Dec 24 02:42:06 PM PST 23 233894217277 ps
T943 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.709725063 Dec 24 01:26:09 PM PST 23 Dec 24 01:53:49 PM PST 23 13196136960 ps
T944 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2003453348 Dec 24 01:23:12 PM PST 23 Dec 24 01:25:35 PM PST 23 4464226120 ps
T945 /workspace/coverage/default/20.sram_ctrl_ram_cfg.1805042507 Dec 24 01:24:33 PM PST 23 Dec 24 01:24:39 PM PST 23 381568186 ps
T946 /workspace/coverage/default/48.sram_ctrl_partial_access.2897413687 Dec 24 01:27:27 PM PST 23 Dec 24 01:27:57 PM PST 23 970104944 ps
T947 /workspace/coverage/default/36.sram_ctrl_ram_cfg.2159440376 Dec 24 01:25:53 PM PST 23 Dec 24 01:26:02 PM PST 23 361594090 ps
T948 /workspace/coverage/default/21.sram_ctrl_multiple_keys.2921481921 Dec 24 01:24:36 PM PST 23 Dec 24 01:40:47 PM PST 23 6522382422 ps
T949 /workspace/coverage/default/42.sram_ctrl_mem_walk.2906222222 Dec 24 01:26:44 PM PST 23 Dec 24 01:29:09 PM PST 23 40470058395 ps
T950 /workspace/coverage/default/16.sram_ctrl_mem_walk.3266183407 Dec 24 01:23:32 PM PST 23 Dec 24 01:27:50 PM PST 23 4026991659 ps
T951 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1834848865 Dec 24 01:24:30 PM PST 23 Dec 24 01:29:50 PM PST 23 14768980095 ps
T952 /workspace/coverage/default/2.sram_ctrl_ram_cfg.4258711729 Dec 24 01:21:58 PM PST 23 Dec 24 01:22:12 PM PST 23 366162133 ps
T953 /workspace/coverage/default/29.sram_ctrl_ram_cfg.3719581348 Dec 24 01:24:46 PM PST 23 Dec 24 01:24:54 PM PST 23 706949771 ps
T954 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1640305659 Dec 24 01:22:00 PM PST 23 Dec 24 01:26:29 PM PST 23 45851243239 ps
T955 /workspace/coverage/default/12.sram_ctrl_executable.4147644987 Dec 24 01:23:13 PM PST 23 Dec 24 01:43:07 PM PST 23 121462908350 ps
T956 /workspace/coverage/default/11.sram_ctrl_multiple_keys.408913500 Dec 24 01:22:59 PM PST 23 Dec 24 01:36:50 PM PST 23 51834192466 ps
T957 /workspace/coverage/default/40.sram_ctrl_alert_test.38506795 Dec 24 01:26:49 PM PST 23 Dec 24 01:26:52 PM PST 23 33808438 ps
T958 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2977696894 Dec 24 01:23:35 PM PST 23 Dec 24 01:41:41 PM PST 23 22964403855 ps
T959 /workspace/coverage/default/30.sram_ctrl_ram_cfg.3904853335 Dec 24 01:25:37 PM PST 23 Dec 24 01:25:44 PM PST 23 368260763 ps
T960 /workspace/coverage/default/18.sram_ctrl_ram_cfg.3111330303 Dec 24 01:23:50 PM PST 23 Dec 24 01:23:57 PM PST 23 370729656 ps
T961 /workspace/coverage/default/22.sram_ctrl_mem_walk.956873570 Dec 24 01:24:36 PM PST 23 Dec 24 01:27:10 PM PST 23 9335099023 ps
T962 /workspace/coverage/default/37.sram_ctrl_stress_all.4211210094 Dec 24 01:26:06 PM PST 23 Dec 24 03:01:43 PM PST 23 192486300104 ps
T963 /workspace/coverage/default/44.sram_ctrl_bijection.2291472275 Dec 24 01:27:00 PM PST 23 Dec 24 02:08:41 PM PST 23 161010949832 ps
T964 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3199321593 Dec 24 01:27:11 PM PST 23 Dec 24 02:32:06 PM PST 23 536180406 ps
T965 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.480174278 Dec 24 01:26:33 PM PST 23 Dec 24 01:28:39 PM PST 23 6521298173 ps
T966 /workspace/coverage/default/2.sram_ctrl_alert_test.610561664 Dec 24 01:22:03 PM PST 23 Dec 24 01:22:05 PM PST 23 40543277 ps
T967 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.378624850 Dec 24 01:26:47 PM PST 23 Dec 24 01:33:39 PM PST 23 20553042130 ps
T968 /workspace/coverage/default/8.sram_ctrl_partial_access.4093791320 Dec 24 01:22:18 PM PST 23 Dec 24 01:23:41 PM PST 23 1544759441 ps
T969 /workspace/coverage/default/7.sram_ctrl_bijection.503819408 Dec 24 01:22:18 PM PST 23 Dec 24 02:02:13 PM PST 23 287412649814 ps
T970 /workspace/coverage/default/42.sram_ctrl_multiple_keys.3391957164 Dec 24 01:26:45 PM PST 23 Dec 24 01:40:33 PM PST 23 5375664172 ps
T971 /workspace/coverage/default/14.sram_ctrl_regwen.1224813284 Dec 24 01:23:29 PM PST 23 Dec 24 01:30:40 PM PST 23 2012527268 ps
T972 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.518699579 Dec 24 01:27:01 PM PST 23 Dec 24 01:54:43 PM PST 23 1216418781 ps
T973 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1736429431 Dec 24 01:26:46 PM PST 23 Dec 24 01:32:20 PM PST 23 54404799718 ps
T974 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2704778699 Dec 24 01:25:49 PM PST 23 Dec 24 01:29:10 PM PST 23 6170240631 ps
T975 /workspace/coverage/default/9.sram_ctrl_ram_cfg.2351462428 Dec 24 01:22:41 PM PST 23 Dec 24 01:22:58 PM PST 23 1531720693 ps
T976 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3428254784 Dec 24 01:24:32 PM PST 23 Dec 24 01:31:21 PM PST 23 6884548484 ps
T977 /workspace/coverage/default/45.sram_ctrl_ram_cfg.475756607 Dec 24 01:27:14 PM PST 23 Dec 24 01:27:23 PM PST 23 3737796174 ps
T978 /workspace/coverage/default/49.sram_ctrl_alert_test.3435796918 Dec 24 01:27:40 PM PST 23 Dec 24 01:27:41 PM PST 23 19428795 ps
T979 /workspace/coverage/default/21.sram_ctrl_alert_test.962399270 Dec 24 01:24:31 PM PST 23 Dec 24 01:24:33 PM PST 23 39431635 ps
T980 /workspace/coverage/default/44.sram_ctrl_executable.3905943418 Dec 24 01:26:58 PM PST 23 Dec 24 01:34:27 PM PST 23 51685349637 ps
T981 /workspace/coverage/default/34.sram_ctrl_multiple_keys.3739402500 Dec 24 01:25:50 PM PST 23 Dec 24 01:40:03 PM PST 23 17207941814 ps
T982 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3460077233 Dec 24 01:26:47 PM PST 23 Dec 24 01:31:11 PM PST 23 6510190356 ps
T983 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2701365858 Dec 24 01:22:17 PM PST 23 Dec 24 02:44:13 PM PST 23 1476368790 ps

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1731146856
Short name T3
Test name
Test status
Simulation time 6550840955 ps
CPU time 5941.05 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 03:03:40 PM PST 23
Peak memory 740024 kb
Host smart-f035fb82-6a84-4416-9e9c-3b1e6548e228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1731146856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1731146856
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.2646601684
Short name T5
Test name
Test status
Simulation time 10372926813 ps
CPU time 24.04 seconds
Started Dec 24 01:26:07 PM PST 23
Finished Dec 24 01:26:33 PM PST 23
Peak memory 202072 kb
Host smart-b42ff5e1-c496-4c98-9869-cfaf9d0f8719
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646601684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.2646601684
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.1937969471
Short name T13
Test name
Test status
Simulation time 3378023574 ps
CPU time 758.46 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:37:16 PM PST 23
Peak memory 372844 kb
Host smart-d01a894c-af84-4ce3-8af7-ef111399133d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937969471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1937969471
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.817950873
Short name T51
Test name
Test status
Simulation time 318758871 ps
CPU time 2.39 seconds
Started Dec 24 12:57:10 PM PST 23
Finished Dec 24 12:57:19 PM PST 23
Peak memory 202336 kb
Host smart-be7e47aa-98f8-4416-b010-52a1f917c271
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817950873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.sram_ctrl_tl_intg_err.817950873
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3197500095
Short name T2
Test name
Test status
Simulation time 61803041497 ps
CPU time 1276.5 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:47:09 PM PST 23
Peak memory 360708 kb
Host smart-e014f7d6-ac22-4ec2-aeba-3503d08577cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197500095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.3197500095
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.1285079774
Short name T24
Test name
Test status
Simulation time 683490999 ps
CPU time 2.72 seconds
Started Dec 24 01:21:59 PM PST 23
Finished Dec 24 01:22:03 PM PST 23
Peak memory 220988 kb
Host smart-ed6a05e7-6809-4a69-a4b1-c3b1ff3fc116
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285079774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.1285079774
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1127976003
Short name T16
Test name
Test status
Simulation time 56248886313 ps
CPU time 260.47 seconds
Started Dec 24 01:25:49 PM PST 23
Finished Dec 24 01:30:13 PM PST 23
Peak memory 202156 kb
Host smart-ac6657ef-c4c9-485a-9bca-913deefbacb6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127976003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.1127976003
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.1764605642
Short name T48
Test name
Test status
Simulation time 11734402046 ps
CPU time 645.92 seconds
Started Dec 24 01:24:27 PM PST 23
Finished Dec 24 01:35:14 PM PST 23
Peak memory 374044 kb
Host smart-9e9fc009-d290-4832-8005-7f91d7ee3fe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764605642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.1764605642
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.2899554716
Short name T141
Test name
Test status
Simulation time 1785035462593 ps
CPU time 6138.58 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 03:05:50 PM PST 23
Peak memory 378048 kb
Host smart-4ff05774-057e-4720-9c0a-06957b921be8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899554716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.2899554716
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3254342768
Short name T67
Test name
Test status
Simulation time 33507209 ps
CPU time 0.64 seconds
Started Dec 24 12:56:02 PM PST 23
Finished Dec 24 12:56:06 PM PST 23
Peak memory 201748 kb
Host smart-5f8adeed-43d3-4720-bb63-c509dabffd5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254342768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.3254342768
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.2274067422
Short name T34
Test name
Test status
Simulation time 355411630 ps
CPU time 5.48 seconds
Started Dec 24 01:23:24 PM PST 23
Finished Dec 24 01:23:30 PM PST 23
Peak memory 202456 kb
Host smart-c08b8c2e-718c-42f2-a337-1587f945e1cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274067422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2274067422
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3157580818
Short name T117
Test name
Test status
Simulation time 350295696 ps
CPU time 1.5 seconds
Started Dec 24 12:56:24 PM PST 23
Finished Dec 24 12:56:27 PM PST 23
Peak memory 202444 kb
Host smart-8176ce23-82fe-4228-b7a7-95aec12ed573
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157580818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.3157580818
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.2530298023
Short name T29
Test name
Test status
Simulation time 1536068085788 ps
CPU time 5039.57 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 02:46:05 PM PST 23
Peak memory 375964 kb
Host smart-f2ddfb39-47a4-48ff-9ee3-27fea7a0eaef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530298023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.2530298023
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.2663195368
Short name T23
Test name
Test status
Simulation time 24945099 ps
CPU time 0.66 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:22:06 PM PST 23
Peak memory 201884 kb
Host smart-cc1166d6-9a0c-4156-b042-f6c46f7193be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663195368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.2663195368
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3273589669
Short name T75
Test name
Test status
Simulation time 7155940520 ps
CPU time 277.27 seconds
Started Dec 24 12:56:18 PM PST 23
Finished Dec 24 01:00:59 PM PST 23
Peak memory 202652 kb
Host smart-035840a9-bcbd-4031-aab5-9a4b91570a3c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273589669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.3273589669
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2467865953
Short name T161
Test name
Test status
Simulation time 713322068 ps
CPU time 13.32 seconds
Started Dec 24 12:56:12 PM PST 23
Finished Dec 24 12:56:29 PM PST 23
Peak memory 210696 kb
Host smart-75fb5e30-e969-4acd-9adc-d97960c69a81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467865953 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2467865953
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1769514020
Short name T119
Test name
Test status
Simulation time 80511092 ps
CPU time 1.34 seconds
Started Dec 24 12:56:26 PM PST 23
Finished Dec 24 12:56:29 PM PST 23
Peak memory 202460 kb
Host smart-13a2330d-c1ba-4937-8b35-176b4c45ac01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769514020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.1769514020
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2559355948
Short name T127
Test name
Test status
Simulation time 197069041 ps
CPU time 2.44 seconds
Started Dec 24 12:56:58 PM PST 23
Finished Dec 24 12:57:07 PM PST 23
Peak memory 202440 kb
Host smart-8c2a04c2-e6eb-419f-831b-f331ae2bb7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559355948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.2559355948
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.3354085288
Short name T361
Test name
Test status
Simulation time 388251688487 ps
CPU time 4269.6 seconds
Started Dec 24 01:21:24 PM PST 23
Finished Dec 24 02:32:35 PM PST 23
Peak memory 376032 kb
Host smart-e91f69f8-5cec-469b-83a8-d679f74bc3ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354085288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.3354085288
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2749516664
Short name T72
Test name
Test status
Simulation time 48265875 ps
CPU time 0.68 seconds
Started Dec 24 12:56:04 PM PST 23
Finished Dec 24 12:56:09 PM PST 23
Peak memory 202140 kb
Host smart-dec22944-5208-4082-84cd-ba0af2e201b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749516664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.2749516664
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4289729744
Short name T173
Test name
Test status
Simulation time 110585051 ps
CPU time 1.8 seconds
Started Dec 24 12:56:02 PM PST 23
Finished Dec 24 12:56:08 PM PST 23
Peak memory 202428 kb
Host smart-7f113d92-4934-47f6-ac78-78131857db7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289729744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.4289729744
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3760592758
Short name T151
Test name
Test status
Simulation time 32760295 ps
CPU time 0.68 seconds
Started Dec 24 12:56:01 PM PST 23
Finished Dec 24 12:56:03 PM PST 23
Peak memory 201352 kb
Host smart-6b05250b-29b7-4a28-bbe5-fddc64a352ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760592758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.3760592758
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.407754856
Short name T172
Test name
Test status
Simulation time 15359073 ps
CPU time 0.64 seconds
Started Dec 24 12:56:04 PM PST 23
Finished Dec 24 12:56:10 PM PST 23
Peak memory 201476 kb
Host smart-73b94735-dce2-4357-b865-48368d0455d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407754856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.sram_ctrl_csr_rw.407754856
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1339174053
Short name T78
Test name
Test status
Simulation time 30717591243 ps
CPU time 262.31 seconds
Started Dec 24 12:56:02 PM PST 23
Finished Dec 24 01:00:28 PM PST 23
Peak memory 202544 kb
Host smart-e494019c-d9de-439d-8818-bdf5d794b2cf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339174053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1339174053
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.930530295
Short name T218
Test name
Test status
Simulation time 36157014 ps
CPU time 0.72 seconds
Started Dec 24 12:56:02 PM PST 23
Finished Dec 24 12:56:07 PM PST 23
Peak memory 201964 kb
Host smart-f411fc8e-4463-46cf-9dcd-cda646d1809f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930530295 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.930530295
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3645021463
Short name T170
Test name
Test status
Simulation time 53006178 ps
CPU time 1.97 seconds
Started Dec 24 12:56:07 PM PST 23
Finished Dec 24 12:56:14 PM PST 23
Peak memory 202524 kb
Host smart-871262ef-5fd7-4c1c-ad98-cc9a8e93c4dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645021463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.3645021463
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4010862868
Short name T179
Test name
Test status
Simulation time 19803964 ps
CPU time 0.67 seconds
Started Dec 24 12:56:05 PM PST 23
Finished Dec 24 12:56:11 PM PST 23
Peak memory 201160 kb
Host smart-dcbbb4b6-0962-49ae-9be2-0b6f674bf1c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010862868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.4010862868
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2613023143
Short name T200
Test name
Test status
Simulation time 301694068 ps
CPU time 1.45 seconds
Started Dec 24 12:56:11 PM PST 23
Finished Dec 24 12:56:16 PM PST 23
Peak memory 202292 kb
Host smart-2544fbcf-a417-4f0b-ba4f-7c70b2a74a1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613023143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.2613023143
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2280569740
Short name T115
Test name
Test status
Simulation time 24150748 ps
CPU time 0.68 seconds
Started Dec 24 12:56:02 PM PST 23
Finished Dec 24 12:56:07 PM PST 23
Peak memory 201484 kb
Host smart-c25bcdb5-da1c-47bc-886f-e77e670f8d6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280569740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.2280569740
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3307074167
Short name T116
Test name
Test status
Simulation time 3894867610 ps
CPU time 5.71 seconds
Started Dec 24 12:56:09 PM PST 23
Finished Dec 24 12:56:18 PM PST 23
Peak memory 210708 kb
Host smart-222e3962-53fd-4896-9b61-6d783765097f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307074167 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3307074167
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.168157083
Short name T99
Test name
Test status
Simulation time 7431373218 ps
CPU time 272.95 seconds
Started Dec 24 12:56:01 PM PST 23
Finished Dec 24 01:00:37 PM PST 23
Peak memory 202460 kb
Host smart-81cb6ed5-086f-407b-a354-1cf22314e318
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168157083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.168157083
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3827332477
Short name T185
Test name
Test status
Simulation time 15672996 ps
CPU time 0.66 seconds
Started Dec 24 12:56:10 PM PST 23
Finished Dec 24 12:56:13 PM PST 23
Peak memory 201796 kb
Host smart-f1590b23-4d64-4f78-b1b1-7337a58f2c99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827332477 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3827332477
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3330244408
Short name T62
Test name
Test status
Simulation time 44901660 ps
CPU time 2.47 seconds
Started Dec 24 12:56:04 PM PST 23
Finished Dec 24 12:56:10 PM PST 23
Peak memory 202448 kb
Host smart-1364a390-1a5e-479e-b3c9-85c29447ea32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330244408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.3330244408
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.380691665
Short name T208
Test name
Test status
Simulation time 275992566 ps
CPU time 2.09 seconds
Started Dec 24 12:56:09 PM PST 23
Finished Dec 24 12:56:14 PM PST 23
Peak memory 202304 kb
Host smart-4738865c-a4bd-4f04-a13d-2ad4c2e8b8b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380691665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.sram_ctrl_tl_intg_err.380691665
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2120471516
Short name T174
Test name
Test status
Simulation time 745304386 ps
CPU time 4.89 seconds
Started Dec 24 12:56:26 PM PST 23
Finished Dec 24 12:56:32 PM PST 23
Peak memory 202400 kb
Host smart-fb2b86f4-7840-4182-9574-d063fb463c83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120471516 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2120471516
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1186036639
Short name T207
Test name
Test status
Simulation time 26373974 ps
CPU time 0.69 seconds
Started Dec 24 12:56:20 PM PST 23
Finished Dec 24 12:56:23 PM PST 23
Peak memory 201940 kb
Host smart-1893915a-eb4c-4eb0-9cf5-cdd248237e37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186036639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.1186036639
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1223693648
Short name T70
Test name
Test status
Simulation time 3893281535 ps
CPU time 140.18 seconds
Started Dec 24 12:56:14 PM PST 23
Finished Dec 24 12:58:38 PM PST 23
Peak memory 202428 kb
Host smart-58063d57-9218-43ec-964f-a20235e83294
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223693648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.1223693648
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2829893410
Short name T182
Test name
Test status
Simulation time 39286005 ps
CPU time 0.67 seconds
Started Dec 24 12:56:21 PM PST 23
Finished Dec 24 12:56:24 PM PST 23
Peak memory 201824 kb
Host smart-3322a168-7e55-497e-bd18-ac5c796dcb28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829893410 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2829893410
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.100723328
Short name T169
Test name
Test status
Simulation time 70244104 ps
CPU time 2.65 seconds
Started Dec 24 12:56:23 PM PST 23
Finished Dec 24 12:56:27 PM PST 23
Peak memory 202444 kb
Host smart-757ed2c8-fc8c-42fc-ab54-00fed2c5bcc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100723328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_tl_errors.100723328
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3173439074
Short name T50
Test name
Test status
Simulation time 190213392 ps
CPU time 1.41 seconds
Started Dec 24 12:56:16 PM PST 23
Finished Dec 24 12:56:21 PM PST 23
Peak memory 202412 kb
Host smart-6a4bdd5e-7483-49c4-92e9-1e46bf785b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173439074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.3173439074
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2258601897
Short name T201
Test name
Test status
Simulation time 1459936826 ps
CPU time 5.92 seconds
Started Dec 24 12:56:25 PM PST 23
Finished Dec 24 12:56:32 PM PST 23
Peak memory 210604 kb
Host smart-a87585d2-3057-41fb-939c-eef8f9c3dd15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258601897 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2258601897
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3037254632
Short name T166
Test name
Test status
Simulation time 14755503 ps
CPU time 0.65 seconds
Started Dec 24 12:56:23 PM PST 23
Finished Dec 24 12:56:25 PM PST 23
Peak memory 201372 kb
Host smart-fd197c44-b385-4d62-b528-21eb11ee7d9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037254632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.3037254632
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1388977085
Short name T163
Test name
Test status
Simulation time 15367763120 ps
CPU time 61.82 seconds
Started Dec 24 12:56:20 PM PST 23
Finished Dec 24 12:57:24 PM PST 23
Peak memory 202560 kb
Host smart-1dd689cb-8f74-4be7-840b-81a0e17fc06a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388977085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1388977085
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4151286334
Short name T105
Test name
Test status
Simulation time 18200944 ps
CPU time 0.73 seconds
Started Dec 24 12:56:20 PM PST 23
Finished Dec 24 12:56:23 PM PST 23
Peak memory 202200 kb
Host smart-60e9649c-583a-46c4-bd4a-c10fffdd40c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151286334 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.4151286334
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2580134832
Short name T193
Test name
Test status
Simulation time 59639186 ps
CPU time 2.18 seconds
Started Dec 24 12:56:29 PM PST 23
Finished Dec 24 12:56:32 PM PST 23
Peak memory 202392 kb
Host smart-0253fded-ccad-4804-9014-0a2142ee2db3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580134832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.2580134832
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1040150498
Short name T191
Test name
Test status
Simulation time 360328896 ps
CPU time 1.45 seconds
Started Dec 24 12:56:13 PM PST 23
Finished Dec 24 12:56:19 PM PST 23
Peak memory 202392 kb
Host smart-848699d8-23c1-4251-8810-20a835ec36c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040150498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.1040150498
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3747397312
Short name T56
Test name
Test status
Simulation time 696487262 ps
CPU time 5.98 seconds
Started Dec 24 12:56:57 PM PST 23
Finished Dec 24 12:57:09 PM PST 23
Peak memory 202328 kb
Host smart-a2118579-6d5c-4452-a117-0159b31ea726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747397312 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3747397312
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2559981286
Short name T152
Test name
Test status
Simulation time 13597937 ps
CPU time 0.68 seconds
Started Dec 24 12:56:56 PM PST 23
Finished Dec 24 12:57:00 PM PST 23
Peak memory 201488 kb
Host smart-7bdf0633-2112-4955-8959-72da60146e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559981286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.2559981286
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.162923130
Short name T194
Test name
Test status
Simulation time 20065263 ps
CPU time 0.71 seconds
Started Dec 24 12:56:56 PM PST 23
Finished Dec 24 12:57:01 PM PST 23
Peak memory 202156 kb
Host smart-9a82707e-bc74-4afc-8100-60ee3a0cb751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162923130 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.162923130
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3532061767
Short name T177
Test name
Test status
Simulation time 29162558 ps
CPU time 2.37 seconds
Started Dec 24 12:56:29 PM PST 23
Finished Dec 24 12:56:33 PM PST 23
Peak memory 202448 kb
Host smart-4ccc5f03-8ffc-4f9e-ae93-d1d516b75f91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532061767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.3532061767
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1653313878
Short name T124
Test name
Test status
Simulation time 131976225 ps
CPU time 2 seconds
Started Dec 24 12:57:16 PM PST 23
Finished Dec 24 12:57:26 PM PST 23
Peak memory 202444 kb
Host smart-eaca51b5-b03a-4f59-96c1-b8b9791b6718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653313878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.1653313878
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2756543615
Short name T188
Test name
Test status
Simulation time 3111630575 ps
CPU time 14.6 seconds
Started Dec 24 12:56:55 PM PST 23
Finished Dec 24 12:57:13 PM PST 23
Peak memory 210644 kb
Host smart-3bd1a409-fb89-4fe3-9f56-c25ca5b3e050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756543615 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2756543615
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.647267471
Short name T159
Test name
Test status
Simulation time 42949729 ps
CPU time 0.63 seconds
Started Dec 24 12:56:53 PM PST 23
Finished Dec 24 12:56:55 PM PST 23
Peak memory 202012 kb
Host smart-1be875fc-0c69-4065-9778-b3a4542f44f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647267471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 13.sram_ctrl_csr_rw.647267471
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.999987520
Short name T97
Test name
Test status
Simulation time 58687927530 ps
CPU time 126.69 seconds
Started Dec 24 12:56:56 PM PST 23
Finished Dec 24 12:59:07 PM PST 23
Peak memory 210732 kb
Host smart-06064292-64b1-4e41-98c8-7b121bde228b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999987520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.999987520
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1248452247
Short name T156
Test name
Test status
Simulation time 24165912 ps
CPU time 0.73 seconds
Started Dec 24 12:57:09 PM PST 23
Finished Dec 24 12:57:17 PM PST 23
Peak memory 202192 kb
Host smart-77df2119-8c4d-4562-ab35-491e31bb5794
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248452247 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.1248452247
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2218435395
Short name T65
Test name
Test status
Simulation time 314971079 ps
CPU time 3.15 seconds
Started Dec 24 12:56:56 PM PST 23
Finished Dec 24 12:57:02 PM PST 23
Peak memory 202392 kb
Host smart-809b1dcd-2d36-4d51-a227-5208d1fed86d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218435395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.2218435395
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.233346026
Short name T121
Test name
Test status
Simulation time 105583154 ps
CPU time 1.44 seconds
Started Dec 24 12:57:17 PM PST 23
Finished Dec 24 12:57:26 PM PST 23
Peak memory 202428 kb
Host smart-7c940e6d-dce1-4340-b68a-a1ee7819a15c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233346026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.sram_ctrl_tl_intg_err.233346026
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2884751515
Short name T197
Test name
Test status
Simulation time 347171070 ps
CPU time 5.28 seconds
Started Dec 24 12:56:58 PM PST 23
Finished Dec 24 12:57:09 PM PST 23
Peak memory 210664 kb
Host smart-76597fc1-a049-4433-ae08-45c9f8484538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884751515 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2884751515
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2651427211
Short name T221
Test name
Test status
Simulation time 14696973 ps
CPU time 0.65 seconds
Started Dec 24 12:56:57 PM PST 23
Finished Dec 24 12:57:02 PM PST 23
Peak memory 201376 kb
Host smart-cfc47be8-4467-4ae1-98e0-dc6cb8c8611c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651427211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.2651427211
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2270345133
Short name T202
Test name
Test status
Simulation time 7243613013 ps
CPU time 125.54 seconds
Started Dec 24 12:56:59 PM PST 23
Finished Dec 24 12:59:11 PM PST 23
Peak memory 210764 kb
Host smart-cd907d2d-3dd6-4731-9b94-fffa2ceff6fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270345133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2270345133
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3249127968
Short name T198
Test name
Test status
Simulation time 58296159 ps
CPU time 0.71 seconds
Started Dec 24 12:57:09 PM PST 23
Finished Dec 24 12:57:17 PM PST 23
Peak memory 201864 kb
Host smart-932962d5-9439-430d-8b45-ea849d958b21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249127968 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.3249127968
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4176170553
Short name T158
Test name
Test status
Simulation time 21454174 ps
CPU time 1.56 seconds
Started Dec 24 12:56:57 PM PST 23
Finished Dec 24 12:57:05 PM PST 23
Peak memory 202432 kb
Host smart-347719c9-908d-44d5-a43e-eff8cb073beb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176170553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.4176170553
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1514730
Short name T214
Test name
Test status
Simulation time 701518855 ps
CPU time 1.91 seconds
Started Dec 24 12:56:56 PM PST 23
Finished Dec 24 12:57:01 PM PST 23
Peak memory 202352 kb
Host smart-028d389a-f5f8-49cb-840c-4e6a9bf7a28b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.sram_ctrl_tl_intg_err.1514730
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2944346639
Short name T209
Test name
Test status
Simulation time 1361731156 ps
CPU time 4.51 seconds
Started Dec 24 12:57:01 PM PST 23
Finished Dec 24 12:57:11 PM PST 23
Peak memory 202420 kb
Host smart-b4a39dc7-820f-4cdf-8bcd-b627777743d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944346639 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2944346639
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3923521211
Short name T69
Test name
Test status
Simulation time 32771980 ps
CPU time 0.65 seconds
Started Dec 24 12:56:57 PM PST 23
Finished Dec 24 12:57:02 PM PST 23
Peak memory 201312 kb
Host smart-d5cc7fe8-b560-4a2b-a835-9337b916cf37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923521211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3923521211
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3117814838
Short name T211
Test name
Test status
Simulation time 117355208479 ps
CPU time 122.27 seconds
Started Dec 24 12:56:59 PM PST 23
Finished Dec 24 12:59:07 PM PST 23
Peak memory 202396 kb
Host smart-5661a279-7a44-408c-b17b-3b5c34c951a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117814838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3117814838
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.365443162
Short name T32
Test name
Test status
Simulation time 43220727 ps
CPU time 0.75 seconds
Started Dec 24 12:56:54 PM PST 23
Finished Dec 24 12:56:58 PM PST 23
Peak memory 202228 kb
Host smart-425ed137-daa0-41a3-9ca2-5cbdaadfcd4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365443162 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.365443162
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1660335131
Short name T157
Test name
Test status
Simulation time 1251443742 ps
CPU time 4.72 seconds
Started Dec 24 12:56:58 PM PST 23
Finished Dec 24 12:57:08 PM PST 23
Peak memory 202360 kb
Host smart-90e3b344-6c42-40d3-8f00-a3d59e6dd493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660335131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.1660335131
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.281072254
Short name T189
Test name
Test status
Simulation time 325000078 ps
CPU time 1.93 seconds
Started Dec 24 12:56:59 PM PST 23
Finished Dec 24 12:57:07 PM PST 23
Peak memory 202284 kb
Host smart-894bda79-9a93-46a3-bcb3-5d40b69551ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281072254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.sram_ctrl_tl_intg_err.281072254
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2611489415
Short name T195
Test name
Test status
Simulation time 696477290 ps
CPU time 11.96 seconds
Started Dec 24 12:56:55 PM PST 23
Finished Dec 24 12:57:10 PM PST 23
Peak memory 210576 kb
Host smart-d06f5c19-81e7-4016-bb4d-a7b88c1a4ca9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611489415 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2611489415
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3283516659
Short name T94
Test name
Test status
Simulation time 13223083 ps
CPU time 0.63 seconds
Started Dec 24 12:56:56 PM PST 23
Finished Dec 24 12:57:00 PM PST 23
Peak memory 201348 kb
Host smart-8d09a58e-ea63-4351-a077-86a6dd1a5c25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283516659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.3283516659
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2373430159
Short name T68
Test name
Test status
Simulation time 7536768487 ps
CPU time 276.03 seconds
Started Dec 24 12:57:01 PM PST 23
Finished Dec 24 01:01:43 PM PST 23
Peak memory 202480 kb
Host smart-2c5b5062-ccd3-4c79-8829-f0c5292208d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373430159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2373430159
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1771920277
Short name T186
Test name
Test status
Simulation time 103311673 ps
CPU time 0.71 seconds
Started Dec 24 12:56:56 PM PST 23
Finished Dec 24 12:57:01 PM PST 23
Peak memory 202168 kb
Host smart-d10dc9ac-b7f6-47be-954d-de2c68ae4d42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771920277 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.1771920277
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.260120329
Short name T58
Test name
Test status
Simulation time 163310270 ps
CPU time 3.6 seconds
Started Dec 24 12:56:59 PM PST 23
Finished Dec 24 12:57:09 PM PST 23
Peak memory 202364 kb
Host smart-49665d5f-2e94-4090-b13b-29f1d87f33e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260120329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_tl_errors.260120329
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3337751087
Short name T123
Test name
Test status
Simulation time 1775300785 ps
CPU time 2.86 seconds
Started Dec 24 12:56:59 PM PST 23
Finished Dec 24 12:57:08 PM PST 23
Peak memory 202396 kb
Host smart-f3a4ec0f-e9a9-41af-aa7b-4b4fdf94afcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337751087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.3337751087
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1899459212
Short name T190
Test name
Test status
Simulation time 352573354 ps
CPU time 13.11 seconds
Started Dec 24 12:56:57 PM PST 23
Finished Dec 24 12:57:14 PM PST 23
Peak memory 210580 kb
Host smart-9fce821d-a598-482d-b41a-c83d098e6f64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899459212 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1899459212
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.721458199
Short name T96
Test name
Test status
Simulation time 79824807 ps
CPU time 0.65 seconds
Started Dec 24 12:57:00 PM PST 23
Finished Dec 24 12:57:07 PM PST 23
Peak memory 201476 kb
Host smart-8c3ff895-e8d6-4383-82c2-d818011957f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721458199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 17.sram_ctrl_csr_rw.721458199
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3804328565
Short name T86
Test name
Test status
Simulation time 3848609407 ps
CPU time 62.05 seconds
Started Dec 24 12:57:00 PM PST 23
Finished Dec 24 12:58:08 PM PST 23
Peak memory 210648 kb
Host smart-d2fcbb45-cc95-4317-bc8d-2db15ddd99a2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804328565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3804328565
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1296628114
Short name T222
Test name
Test status
Simulation time 126033700 ps
CPU time 0.74 seconds
Started Dec 24 12:57:04 PM PST 23
Finished Dec 24 12:57:12 PM PST 23
Peak memory 202164 kb
Host smart-3e10aabf-6e76-4ade-8164-f9070271296e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296628114 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1296628114
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3924724881
Short name T204
Test name
Test status
Simulation time 462238281 ps
CPU time 4.94 seconds
Started Dec 24 12:57:00 PM PST 23
Finished Dec 24 12:57:11 PM PST 23
Peak memory 202368 kb
Host smart-46912aee-e7c1-448e-899b-188685cefb2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924724881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.3924724881
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3230958087
Short name T205
Test name
Test status
Simulation time 1465721464 ps
CPU time 5.45 seconds
Started Dec 24 12:57:11 PM PST 23
Finished Dec 24 12:57:24 PM PST 23
Peak memory 202400 kb
Host smart-46a2f91d-8fd5-41de-a325-afbe0e3eb7c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230958087 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3230958087
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3115003739
Short name T104
Test name
Test status
Simulation time 195237851 ps
CPU time 0.7 seconds
Started Dec 24 12:56:58 PM PST 23
Finished Dec 24 12:57:05 PM PST 23
Peak memory 201520 kb
Host smart-697d07a2-9ec2-42e6-8881-483aa87de0e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115003739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.3115003739
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2498299529
Short name T85
Test name
Test status
Simulation time 7729199742 ps
CPU time 51.03 seconds
Started Dec 24 12:56:59 PM PST 23
Finished Dec 24 12:57:56 PM PST 23
Peak memory 202560 kb
Host smart-bdc2664d-958c-41d7-94cc-c0911c2be16c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498299529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.2498299529
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3210244815
Short name T178
Test name
Test status
Simulation time 38919644 ps
CPU time 0.64 seconds
Started Dec 24 12:57:05 PM PST 23
Finished Dec 24 12:57:13 PM PST 23
Peak memory 201452 kb
Host smart-32f1325e-342b-4542-a6ca-66a2f4c1867d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210244815 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3210244815
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4048097277
Short name T203
Test name
Test status
Simulation time 155309154 ps
CPU time 3.55 seconds
Started Dec 24 12:56:56 PM PST 23
Finished Dec 24 12:57:03 PM PST 23
Peak memory 202492 kb
Host smart-c9d3e825-8c64-4470-a250-96cc4d4c2cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048097277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.4048097277
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1068191708
Short name T54
Test name
Test status
Simulation time 369294224 ps
CPU time 11.62 seconds
Started Dec 24 12:57:10 PM PST 23
Finished Dec 24 12:57:29 PM PST 23
Peak memory 202496 kb
Host smart-0d2fcd25-f0dd-494a-a5ae-d58419ee7848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068191708 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1068191708
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1765300590
Short name T82
Test name
Test status
Simulation time 13062836 ps
CPU time 0.64 seconds
Started Dec 24 12:57:02 PM PST 23
Finished Dec 24 12:57:08 PM PST 23
Peak memory 202024 kb
Host smart-7d50b3c1-24dc-4724-9d88-dc5704b569bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765300590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.1765300590
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2928315233
Short name T84
Test name
Test status
Simulation time 33633777192 ps
CPU time 58.09 seconds
Started Dec 24 12:57:05 PM PST 23
Finished Dec 24 12:58:11 PM PST 23
Peak memory 210792 kb
Host smart-78144de8-03ec-4287-b9ad-aa70987d3be5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928315233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2928315233
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1618713707
Short name T73
Test name
Test status
Simulation time 30183783 ps
CPU time 0.73 seconds
Started Dec 24 12:56:57 PM PST 23
Finished Dec 24 12:57:04 PM PST 23
Peak memory 202116 kb
Host smart-365218e7-787b-4222-8e60-4f50cc7833ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618713707 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1618713707
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2123628948
Short name T176
Test name
Test status
Simulation time 275912591 ps
CPU time 2.73 seconds
Started Dec 24 12:57:07 PM PST 23
Finished Dec 24 12:57:18 PM PST 23
Peak memory 202372 kb
Host smart-86e64af1-7c94-4392-ae06-837f37fdf821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123628948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.2123628948
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1059119661
Short name T52
Test name
Test status
Simulation time 395686321 ps
CPU time 1.64 seconds
Started Dec 24 12:57:01 PM PST 23
Finished Dec 24 12:57:08 PM PST 23
Peak memory 202440 kb
Host smart-75f3102b-928d-4b64-8785-b4d96d716b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059119661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.1059119661
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.779041439
Short name T83
Test name
Test status
Simulation time 22357171 ps
CPU time 0.68 seconds
Started Dec 24 12:56:12 PM PST 23
Finished Dec 24 12:56:16 PM PST 23
Peak memory 201256 kb
Host smart-353beb1c-5ff4-40c9-aadd-8ac1476df5be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779041439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_aliasing.779041439
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.566649855
Short name T217
Test name
Test status
Simulation time 592072363 ps
CPU time 1.36 seconds
Started Dec 24 12:56:25 PM PST 23
Finished Dec 24 12:56:28 PM PST 23
Peak memory 201840 kb
Host smart-9f6a0a8f-d3da-44b7-a2db-557ad6f0794b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566649855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_bit_bash.566649855
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2955258854
Short name T113
Test name
Test status
Simulation time 45291524 ps
CPU time 0.64 seconds
Started Dec 24 12:56:13 PM PST 23
Finished Dec 24 12:56:18 PM PST 23
Peak memory 201136 kb
Host smart-86d1a981-6ced-40fa-a7ec-904d3475bedf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955258854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.2955258854
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2008335095
Short name T165
Test name
Test status
Simulation time 361919476 ps
CPU time 5.17 seconds
Started Dec 24 12:56:14 PM PST 23
Finished Dec 24 12:56:23 PM PST 23
Peak memory 202360 kb
Host smart-9fb8924a-f7a5-4164-8fab-ed15012c6881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008335095 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.2008335095
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4127948239
Short name T206
Test name
Test status
Simulation time 14414194 ps
CPU time 0.66 seconds
Started Dec 24 12:56:14 PM PST 23
Finished Dec 24 12:56:18 PM PST 23
Peak memory 201288 kb
Host smart-6de7579a-c691-43cc-8856-6c1e1083dc36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127948239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.4127948239
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4055455906
Short name T183
Test name
Test status
Simulation time 16077069196 ps
CPU time 64.59 seconds
Started Dec 24 12:56:11 PM PST 23
Finished Dec 24 12:57:18 PM PST 23
Peak memory 210680 kb
Host smart-4db087a8-e67f-45b2-b64f-5335d5a81a4a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055455906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.4055455906
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2499417450
Short name T162
Test name
Test status
Simulation time 16057468 ps
CPU time 0.67 seconds
Started Dec 24 12:56:19 PM PST 23
Finished Dec 24 12:56:23 PM PST 23
Peak memory 201684 kb
Host smart-b346b0e8-223f-4903-b242-56b8ad714345
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499417450 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.2499417450
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.596993857
Short name T212
Test name
Test status
Simulation time 143034798 ps
CPU time 3.36 seconds
Started Dec 24 12:56:10 PM PST 23
Finished Dec 24 12:56:16 PM PST 23
Peak memory 202404 kb
Host smart-5e85f83a-7fc8-4cd7-bae4-d34afb99c178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596993857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_tl_errors.596993857
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2100334199
Short name T184
Test name
Test status
Simulation time 366162471 ps
CPU time 2.36 seconds
Started Dec 24 12:56:22 PM PST 23
Finished Dec 24 12:56:27 PM PST 23
Peak memory 202404 kb
Host smart-62eae3e4-c482-4484-9961-6083f8e0589f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100334199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.2100334199
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3397001884
Short name T90
Test name
Test status
Simulation time 38126287 ps
CPU time 0.66 seconds
Started Dec 24 12:56:28 PM PST 23
Finished Dec 24 12:56:30 PM PST 23
Peak memory 202040 kb
Host smart-f0421f98-8bf1-4790-82d1-d5b89143e45e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397001884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.3397001884
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4103636883
Short name T187
Test name
Test status
Simulation time 60403650 ps
CPU time 1.22 seconds
Started Dec 24 12:56:11 PM PST 23
Finished Dec 24 12:56:14 PM PST 23
Peak memory 202048 kb
Host smart-8545528b-0d51-4a86-9263-35fe8aff44b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103636883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.4103636883
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2182268546
Short name T114
Test name
Test status
Simulation time 30500358 ps
CPU time 0.67 seconds
Started Dec 24 12:56:14 PM PST 23
Finished Dec 24 12:56:18 PM PST 23
Peak memory 202060 kb
Host smart-187b48cc-baa6-4ba9-8b98-9d84d9653988
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182268546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.2182268546
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3240978122
Short name T61
Test name
Test status
Simulation time 651230904 ps
CPU time 6.07 seconds
Started Dec 24 12:56:22 PM PST 23
Finished Dec 24 12:56:30 PM PST 23
Peak memory 202388 kb
Host smart-b9d1162f-dff4-4567-b3a4-850e303cff97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240978122 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3240978122
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1619489637
Short name T112
Test name
Test status
Simulation time 22026002 ps
CPU time 0.64 seconds
Started Dec 24 12:56:13 PM PST 23
Finished Dec 24 12:56:17 PM PST 23
Peak memory 201392 kb
Host smart-fafb633f-b52a-4763-89da-a3e9ceee5442
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619489637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.1619489637
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2662148371
Short name T199
Test name
Test status
Simulation time 14765215972 ps
CPU time 52.47 seconds
Started Dec 24 12:56:11 PM PST 23
Finished Dec 24 12:57:06 PM PST 23
Peak memory 202516 kb
Host smart-addc2cce-5fa5-4a63-8430-e33a7b9d94be
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662148371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.2662148371
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.455348630
Short name T216
Test name
Test status
Simulation time 44963952 ps
CPU time 0.81 seconds
Started Dec 24 12:56:17 PM PST 23
Finished Dec 24 12:56:21 PM PST 23
Peak memory 202140 kb
Host smart-9550f762-7f7e-4bc6-b537-644e736aa388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455348630 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.455348630
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3943408093
Short name T64
Test name
Test status
Simulation time 296732979 ps
CPU time 3 seconds
Started Dec 24 12:56:30 PM PST 23
Finished Dec 24 12:56:35 PM PST 23
Peak memory 210664 kb
Host smart-17c5a943-34ba-4750-bb02-471839bb4b70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943408093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.3943408093
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4195905747
Short name T57
Test name
Test status
Simulation time 512369036 ps
CPU time 2.19 seconds
Started Dec 24 12:56:24 PM PST 23
Finished Dec 24 12:56:28 PM PST 23
Peak memory 202360 kb
Host smart-7601d929-d503-48ca-83b6-a4bbe93b7305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195905747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.4195905747
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3039456934
Short name T220
Test name
Test status
Simulation time 17482803 ps
CPU time 0.68 seconds
Started Dec 24 12:56:15 PM PST 23
Finished Dec 24 12:56:20 PM PST 23
Peak memory 201216 kb
Host smart-46f5e561-76e0-4ed5-b65e-ec9ff3bbe535
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039456934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.3039456934
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4149469091
Short name T192
Test name
Test status
Simulation time 224409825 ps
CPU time 1.64 seconds
Started Dec 24 12:56:11 PM PST 23
Finished Dec 24 12:56:15 PM PST 23
Peak memory 202332 kb
Host smart-4b7635fc-cc89-4f28-b1cf-c8d39e24b53b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149469091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.4149469091
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3349665956
Short name T181
Test name
Test status
Simulation time 49268979 ps
CPU time 0.65 seconds
Started Dec 24 12:56:17 PM PST 23
Finished Dec 24 12:56:21 PM PST 23
Peak memory 202164 kb
Host smart-c121da14-eb1b-4d90-9503-233474c22976
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349665956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.3349665956
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3374083541
Short name T160
Test name
Test status
Simulation time 539346012 ps
CPU time 13.95 seconds
Started Dec 24 12:56:30 PM PST 23
Finished Dec 24 12:56:46 PM PST 23
Peak memory 210652 kb
Host smart-410a89a0-9374-40d1-82f7-8a4d29dbca72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374083541 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3374083541
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3661778891
Short name T154
Test name
Test status
Simulation time 47128545 ps
CPU time 0.62 seconds
Started Dec 24 12:56:14 PM PST 23
Finished Dec 24 12:56:18 PM PST 23
Peak memory 201284 kb
Host smart-45cae937-bad0-4367-bbe0-0e0f234bd2eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661778891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.3661778891
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.649964792
Short name T79
Test name
Test status
Simulation time 70441528607 ps
CPU time 146.92 seconds
Started Dec 24 12:56:22 PM PST 23
Finished Dec 24 12:58:51 PM PST 23
Peak memory 210676 kb
Host smart-4bd0446a-32f7-4303-aba9-20d67f2379a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649964792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.649964792
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.174016670
Short name T66
Test name
Test status
Simulation time 55945819 ps
CPU time 0.68 seconds
Started Dec 24 12:56:12 PM PST 23
Finished Dec 24 12:56:17 PM PST 23
Peak memory 202168 kb
Host smart-9e81766f-d4da-4c91-be78-f98fe173c705
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174016670 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.174016670
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4123015756
Short name T180
Test name
Test status
Simulation time 87801049 ps
CPU time 1.96 seconds
Started Dec 24 12:56:09 PM PST 23
Finished Dec 24 12:56:14 PM PST 23
Peak memory 202388 kb
Host smart-d0a6e473-99a3-433c-8643-38d6bcce4f69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123015756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.4123015756
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4054610407
Short name T120
Test name
Test status
Simulation time 296650793 ps
CPU time 2.44 seconds
Started Dec 24 12:56:29 PM PST 23
Finished Dec 24 12:56:33 PM PST 23
Peak memory 202440 kb
Host smart-3470333e-3d4f-4c88-9820-88fd8b1fd479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054610407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.4054610407
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2979840497
Short name T55
Test name
Test status
Simulation time 706764052 ps
CPU time 6.37 seconds
Started Dec 24 12:56:11 PM PST 23
Finished Dec 24 12:56:20 PM PST 23
Peak memory 202668 kb
Host smart-8ae838c1-b65a-459e-9661-6f0a46d067a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979840497 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2979840497
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2087956452
Short name T92
Test name
Test status
Simulation time 40402871 ps
CPU time 0.64 seconds
Started Dec 24 12:56:17 PM PST 23
Finished Dec 24 12:56:21 PM PST 23
Peak memory 202120 kb
Host smart-5e3fe39d-394e-43ee-92aa-fe735b852b1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087956452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.2087956452
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1930566130
Short name T95
Test name
Test status
Simulation time 31253001229 ps
CPU time 269.51 seconds
Started Dec 24 12:56:30 PM PST 23
Finished Dec 24 01:01:02 PM PST 23
Peak memory 202368 kb
Host smart-43c7870e-2532-4b01-9b3e-ae6f9a8719bc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930566130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.1930566130
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2996297884
Short name T210
Test name
Test status
Simulation time 15371470 ps
CPU time 0.68 seconds
Started Dec 24 12:56:23 PM PST 23
Finished Dec 24 12:56:25 PM PST 23
Peak memory 202264 kb
Host smart-7dd95b6f-e08e-4681-996e-32d5a225aa66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996297884 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.2996297884
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3149658103
Short name T168
Test name
Test status
Simulation time 279908878 ps
CPU time 2.62 seconds
Started Dec 24 12:56:11 PM PST 23
Finished Dec 24 12:56:17 PM PST 23
Peak memory 202376 kb
Host smart-eb7604d1-634f-4e95-a4cf-851e1d965b54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149658103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.3149658103
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.260909851
Short name T213
Test name
Test status
Simulation time 729616943 ps
CPU time 15.11 seconds
Started Dec 24 12:56:15 PM PST 23
Finished Dec 24 12:56:34 PM PST 23
Peak memory 210540 kb
Host smart-69c0d88f-cf41-49de-811d-ea63d46992d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260909851 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.260909851
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1975872385
Short name T153
Test name
Test status
Simulation time 57831528 ps
CPU time 0.64 seconds
Started Dec 24 12:56:10 PM PST 23
Finished Dec 24 12:56:13 PM PST 23
Peak memory 202156 kb
Host smart-b0e4fa49-3770-4379-ab18-c96e48d0ae65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975872385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.1975872385
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2366952425
Short name T93
Test name
Test status
Simulation time 117657487333 ps
CPU time 118.49 seconds
Started Dec 24 12:56:29 PM PST 23
Finished Dec 24 12:58:29 PM PST 23
Peak memory 210628 kb
Host smart-efd59874-cef2-43e5-81d5-52c169a1481e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366952425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2366952425
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1712741781
Short name T167
Test name
Test status
Simulation time 20293448 ps
CPU time 0.72 seconds
Started Dec 24 12:56:15 PM PST 23
Finished Dec 24 12:56:19 PM PST 23
Peak memory 201988 kb
Host smart-ed5cb04b-74a3-4184-b266-bb5af8c47b0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712741781 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1712741781
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2270912160
Short name T171
Test name
Test status
Simulation time 438355888 ps
CPU time 4.57 seconds
Started Dec 24 12:56:12 PM PST 23
Finished Dec 24 12:56:20 PM PST 23
Peak memory 202356 kb
Host smart-c92a71f4-a131-4c19-9f2d-48ba1c76e294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270912160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.2270912160
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1300429271
Short name T126
Test name
Test status
Simulation time 85015075 ps
CPU time 1.39 seconds
Started Dec 24 12:56:11 PM PST 23
Finished Dec 24 12:56:15 PM PST 23
Peak memory 202408 kb
Host smart-8fda5a26-0168-45ae-8b09-dfbe8317ef2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300429271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.1300429271
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.968166863
Short name T219
Test name
Test status
Simulation time 358929031 ps
CPU time 6.09 seconds
Started Dec 24 12:56:21 PM PST 23
Finished Dec 24 12:56:29 PM PST 23
Peak memory 210684 kb
Host smart-cc8f8501-b104-4133-82b6-ed0dffd05728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968166863 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.968166863
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2051040664
Short name T196
Test name
Test status
Simulation time 12418045 ps
CPU time 0.66 seconds
Started Dec 24 12:56:15 PM PST 23
Finished Dec 24 12:56:19 PM PST 23
Peak memory 202000 kb
Host smart-a8fca8f2-1e19-447c-b7b4-701d547de37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051040664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.2051040664
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2475975299
Short name T91
Test name
Test status
Simulation time 29715147244 ps
CPU time 97.7 seconds
Started Dec 24 12:56:13 PM PST 23
Finished Dec 24 12:57:54 PM PST 23
Peak memory 210632 kb
Host smart-e444f17b-afe2-4c91-9059-258f09dd4fc5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475975299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2475975299
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.21676817
Short name T76
Test name
Test status
Simulation time 44362105 ps
CPU time 0.67 seconds
Started Dec 24 12:56:31 PM PST 23
Finished Dec 24 12:56:34 PM PST 23
Peak memory 201868 kb
Host smart-265f2b3b-7e29-4a3e-b925-9ada4b51c805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21676817 -assert nopostproc +UVM_TESTNAME=sram_ctr
l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.21676817
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2507963586
Short name T60
Test name
Test status
Simulation time 264503722 ps
CPU time 4.01 seconds
Started Dec 24 12:56:14 PM PST 23
Finished Dec 24 12:56:22 PM PST 23
Peak memory 202416 kb
Host smart-7b547e33-d370-48d6-ad3b-0ce032a9c252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507963586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.2507963586
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.234431713
Short name T122
Test name
Test status
Simulation time 326766210 ps
CPU time 1.44 seconds
Started Dec 24 12:56:10 PM PST 23
Finished Dec 24 12:56:15 PM PST 23
Peak memory 202356 kb
Host smart-14442564-884a-4dbf-a8b1-0d2687aa31da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234431713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.sram_ctrl_tl_intg_err.234431713
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.563782360
Short name T175
Test name
Test status
Simulation time 702434733 ps
CPU time 4.84 seconds
Started Dec 24 12:56:17 PM PST 23
Finished Dec 24 12:56:25 PM PST 23
Peak memory 202412 kb
Host smart-301cc85b-840b-4fa2-8c33-90c6b1098f61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563782360 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.563782360
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.874377028
Short name T155
Test name
Test status
Simulation time 14147862 ps
CPU time 0.66 seconds
Started Dec 24 12:56:12 PM PST 23
Finished Dec 24 12:56:16 PM PST 23
Peak memory 202072 kb
Host smart-04e9e62a-0c06-4127-9325-bb1732f03160
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874377028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 8.sram_ctrl_csr_rw.874377028
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1600853695
Short name T100
Test name
Test status
Simulation time 3778646420 ps
CPU time 52.04 seconds
Started Dec 24 12:56:12 PM PST 23
Finished Dec 24 12:57:07 PM PST 23
Peak memory 202552 kb
Host smart-5a6e4e1b-c616-437b-9af6-fa4d3f491769
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600853695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.1600853695
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.385699631
Short name T77
Test name
Test status
Simulation time 19151645 ps
CPU time 0.71 seconds
Started Dec 24 12:56:15 PM PST 23
Finished Dec 24 12:56:19 PM PST 23
Peak memory 202332 kb
Host smart-3b25c43d-ec59-4d01-87b4-d0aafeeb61b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385699631 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.385699631
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.379286394
Short name T215
Test name
Test status
Simulation time 449542317 ps
CPU time 3.74 seconds
Started Dec 24 12:56:11 PM PST 23
Finished Dec 24 12:56:18 PM PST 23
Peak memory 202460 kb
Host smart-f8dda43e-2ad2-44bf-b121-97ddae109d92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379286394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_tl_errors.379286394
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1317835332
Short name T125
Test name
Test status
Simulation time 524049174 ps
CPU time 2.44 seconds
Started Dec 24 12:56:11 PM PST 23
Finished Dec 24 12:56:16 PM PST 23
Peak memory 202300 kb
Host smart-8e4f59c4-683f-4030-a79d-94d27f81bec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317835332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.1317835332
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4081130905
Short name T53
Test name
Test status
Simulation time 1387383464 ps
CPU time 14.02 seconds
Started Dec 24 12:56:16 PM PST 23
Finished Dec 24 12:56:34 PM PST 23
Peak memory 210476 kb
Host smart-ffde8284-c7e0-490d-9d31-68c700886c2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081130905 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.4081130905
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.767978127
Short name T164
Test name
Test status
Simulation time 24119218 ps
CPU time 0.65 seconds
Started Dec 24 12:56:16 PM PST 23
Finished Dec 24 12:56:20 PM PST 23
Peak memory 202132 kb
Host smart-305d155a-d417-46aa-8410-5f8f8de2a35c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767978127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_csr_rw.767978127
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2845878591
Short name T98
Test name
Test status
Simulation time 3959496052 ps
CPU time 60.06 seconds
Started Dec 24 12:56:17 PM PST 23
Finished Dec 24 12:57:20 PM PST 23
Peak memory 210700 kb
Host smart-63355c21-d781-4358-868c-74ae1d1daf45
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845878591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.2845878591
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3015961303
Short name T71
Test name
Test status
Simulation time 78168908 ps
CPU time 0.76 seconds
Started Dec 24 12:56:14 PM PST 23
Finished Dec 24 12:56:18 PM PST 23
Peak memory 202172 kb
Host smart-225c85d7-c0b3-4090-ab98-ad865acf593f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015961303 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3015961303
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1881889732
Short name T59
Test name
Test status
Simulation time 147642013 ps
CPU time 4.21 seconds
Started Dec 24 12:56:25 PM PST 23
Finished Dec 24 12:56:31 PM PST 23
Peak memory 210596 kb
Host smart-551f7c0e-5df3-4c0b-a16f-7d03e616cfb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881889732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.1881889732
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1544129645
Short name T63
Test name
Test status
Simulation time 79595889 ps
CPU time 1.4 seconds
Started Dec 24 12:56:24 PM PST 23
Finished Dec 24 12:56:28 PM PST 23
Peak memory 202316 kb
Host smart-dd5a33bb-07d1-4103-b1da-0ee481936176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544129645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.1544129645
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2782381546
Short name T80
Test name
Test status
Simulation time 68047672822 ps
CPU time 619.77 seconds
Started Dec 24 01:21:23 PM PST 23
Finished Dec 24 01:31:44 PM PST 23
Peak memory 357976 kb
Host smart-89e196bf-816e-4fad-b72a-f27f3e50e757
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782381546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.2782381546
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.1420865751
Short name T876
Test name
Test status
Simulation time 230297862509 ps
CPU time 2543.16 seconds
Started Dec 24 01:21:30 PM PST 23
Finished Dec 24 02:03:55 PM PST 23
Peak memory 202084 kb
Host smart-90f7779f-023f-4919-83bb-bc6f46b0e14e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420865751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
1420865751
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.3221829728
Short name T38
Test name
Test status
Simulation time 11140403845 ps
CPU time 70.73 seconds
Started Dec 24 01:21:30 PM PST 23
Finished Dec 24 01:22:42 PM PST 23
Peak memory 202064 kb
Host smart-0a3d22c1-9a8e-4316-ab55-c80c25471957
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221829728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.3221829728
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.3754858246
Short name T827
Test name
Test status
Simulation time 761513642 ps
CPU time 59.91 seconds
Started Dec 24 01:21:29 PM PST 23
Finished Dec 24 01:22:30 PM PST 23
Peak memory 310460 kb
Host smart-f1b6a7b3-4f88-4978-88fc-87b941a6d77a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754858246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.3754858246
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.691861434
Short name T682
Test name
Test status
Simulation time 4625300039 ps
CPU time 155.24 seconds
Started Dec 24 01:21:24 PM PST 23
Finished Dec 24 01:24:01 PM PST 23
Peak memory 211164 kb
Host smart-e710c7e1-b8c0-46e0-8398-e76e37024135
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691861434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_mem_partial_access.691861434
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.2044381473
Short name T848
Test name
Test status
Simulation time 14368120893 ps
CPU time 280.58 seconds
Started Dec 24 01:21:29 PM PST 23
Finished Dec 24 01:26:11 PM PST 23
Peak memory 202128 kb
Host smart-1b50124a-f101-4583-ad91-0c1043e65381
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044381473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.2044381473
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.356322672
Short name T563
Test name
Test status
Simulation time 6903269792 ps
CPU time 337.55 seconds
Started Dec 24 01:21:30 PM PST 23
Finished Dec 24 01:27:09 PM PST 23
Peak memory 350400 kb
Host smart-abd441a4-3576-4d2d-ad5e-d10bc9bc8542
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356322672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multipl
e_keys.356322672
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.3527731766
Short name T245
Test name
Test status
Simulation time 502476572 ps
CPU time 90.99 seconds
Started Dec 24 01:21:30 PM PST 23
Finished Dec 24 01:23:02 PM PST 23
Peak memory 346076 kb
Host smart-10dbac66-fdb8-4a8a-bff2-9c604dde031a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527731766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.3527731766
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2996993020
Short name T574
Test name
Test status
Simulation time 141167662220 ps
CPU time 362.67 seconds
Started Dec 24 01:21:26 PM PST 23
Finished Dec 24 01:27:30 PM PST 23
Peak memory 202160 kb
Host smart-c17e12a9-4849-411d-ba9b-439540a458b3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996993020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.2996993020
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.182142004
Short name T838
Test name
Test status
Simulation time 698694600 ps
CPU time 5.41 seconds
Started Dec 24 01:21:30 PM PST 23
Finished Dec 24 01:21:37 PM PST 23
Peak memory 202288 kb
Host smart-f7584c80-a731-46e3-9b23-135e32cd103d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182142004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.182142004
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.1236076247
Short name T765
Test name
Test status
Simulation time 3858748732 ps
CPU time 1488.81 seconds
Started Dec 24 01:21:30 PM PST 23
Finished Dec 24 01:46:20 PM PST 23
Peak memory 375996 kb
Host smart-7a7f2f1d-5acc-4167-ae36-f139de6971a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236076247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.1236076247
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.1333050764
Short name T651
Test name
Test status
Simulation time 1470494840 ps
CPU time 17.28 seconds
Started Dec 24 01:21:30 PM PST 23
Finished Dec 24 01:21:48 PM PST 23
Peak memory 217352 kb
Host smart-0c03c833-ec3e-40cd-87c6-b4c36233fd39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333050764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1333050764
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2752743508
Short name T881
Test name
Test status
Simulation time 3945283981 ps
CPU time 4237.24 seconds
Started Dec 24 01:21:23 PM PST 23
Finished Dec 24 02:32:01 PM PST 23
Peak memory 698468 kb
Host smart-5a4fd1b6-4e33-46b0-91c4-67607b0119d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2752743508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.2752743508
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2546445170
Short name T330
Test name
Test status
Simulation time 2597046487 ps
CPU time 192.57 seconds
Started Dec 24 01:21:24 PM PST 23
Finished Dec 24 01:24:38 PM PST 23
Peak memory 202056 kb
Host smart-b79cd448-f093-46d3-98b3-184b98b21447
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546445170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.2546445170
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.821608283
Short name T915
Test name
Test status
Simulation time 3413779941 ps
CPU time 85.21 seconds
Started Dec 24 01:21:24 PM PST 23
Finished Dec 24 01:22:51 PM PST 23
Peak memory 325996 kb
Host smart-b8ce9229-c86f-45af-b52b-ebcfbe7f2fdc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821608283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_throughput_w_partial_write.821608283
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.48404111
Short name T464
Test name
Test status
Simulation time 147515962253 ps
CPU time 988.29 seconds
Started Dec 24 01:21:57 PM PST 23
Finished Dec 24 01:38:27 PM PST 23
Peak memory 380012 kb
Host smart-7785b495-fd75-4c6d-a05c-1df4331f13ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48404111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.sram_ctrl_access_during_key_req.48404111
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.1322148141
Short name T920
Test name
Test status
Simulation time 17695274 ps
CPU time 0.62 seconds
Started Dec 24 01:21:58 PM PST 23
Finished Dec 24 01:22:00 PM PST 23
Peak memory 201888 kb
Host smart-8620b02f-9d19-4237-9077-a5c232caadfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322148141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.1322148141
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.945286837
Short name T758
Test name
Test status
Simulation time 216143278258 ps
CPU time 1068.86 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:39:53 PM PST 23
Peak memory 210240 kb
Host smart-a0d4dea5-c9c0-446b-82b3-bee5f813957b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945286837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.945286837
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.587476712
Short name T546
Test name
Test status
Simulation time 217653253715 ps
CPU time 1445.87 seconds
Started Dec 24 01:22:00 PM PST 23
Finished Dec 24 01:46:07 PM PST 23
Peak memory 379092 kb
Host smart-a95c7de2-1c8d-47c1-a739-5a414a67f86c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587476712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable
.587476712
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.2614112097
Short name T693
Test name
Test status
Simulation time 15416849379 ps
CPU time 38.25 seconds
Started Dec 24 01:21:51 PM PST 23
Finished Dec 24 01:22:30 PM PST 23
Peak memory 213268 kb
Host smart-5f1607ae-8dbc-4b2d-94d6-ac2f3595218c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614112097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.2614112097
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.613015460
Short name T810
Test name
Test status
Simulation time 13573652554 ps
CPU time 34.11 seconds
Started Dec 24 01:22:00 PM PST 23
Finished Dec 24 01:22:36 PM PST 23
Peak memory 220756 kb
Host smart-af272176-bd71-4648-822b-2e6ef424374a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613015460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.sram_ctrl_max_throughput.613015460
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1618555439
Short name T822
Test name
Test status
Simulation time 998386297 ps
CPU time 74.18 seconds
Started Dec 24 01:21:56 PM PST 23
Finished Dec 24 01:23:11 PM PST 23
Peak memory 211220 kb
Host smart-7d831f92-d560-43fd-b962-9a0ffa59f200
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618555439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.1618555439
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.3897192217
Short name T711
Test name
Test status
Simulation time 20667017644 ps
CPU time 304.1 seconds
Started Dec 24 01:21:58 PM PST 23
Finished Dec 24 01:27:04 PM PST 23
Peak memory 202124 kb
Host smart-325c85ff-106e-4dd0-9ec4-520deed7bcf6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897192217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.3897192217
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.1763799174
Short name T874
Test name
Test status
Simulation time 72039825826 ps
CPU time 901.15 seconds
Started Dec 24 01:21:52 PM PST 23
Finished Dec 24 01:36:54 PM PST 23
Peak memory 358724 kb
Host smart-9a97d7a6-d557-4b65-9f29-ccf22a6e70c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763799174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.1763799174
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.3040100319
Short name T357
Test name
Test status
Simulation time 367334199 ps
CPU time 14 seconds
Started Dec 24 01:22:10 PM PST 23
Finished Dec 24 01:22:31 PM PST 23
Peak memory 201960 kb
Host smart-c7fe6966-e223-430b-a124-28c234180d7c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040100319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.3040100319
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1640305659
Short name T954
Test name
Test status
Simulation time 45851243239 ps
CPU time 268.6 seconds
Started Dec 24 01:22:00 PM PST 23
Finished Dec 24 01:26:29 PM PST 23
Peak memory 202160 kb
Host smart-40166ec9-e010-4b7c-aaba-46b5731c26d5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640305659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.1640305659
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.131545225
Short name T485
Test name
Test status
Simulation time 362603387 ps
CPU time 6.74 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:22:12 PM PST 23
Peak memory 202416 kb
Host smart-40cf0d15-1d7f-424b-83f1-5b709d7d8d03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131545225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.131545225
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.2728728753
Short name T129
Test name
Test status
Simulation time 26099912994 ps
CPU time 518.09 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:30:46 PM PST 23
Peak memory 351216 kb
Host smart-eed43e62-9aca-43b6-b924-6014f2ab0ea7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728728753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2728728753
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.2836654865
Short name T36
Test name
Test status
Simulation time 113079164 ps
CPU time 1.7 seconds
Started Dec 24 01:21:57 PM PST 23
Finished Dec 24 01:22:00 PM PST 23
Peak memory 221892 kb
Host smart-be97f307-12e2-4d6f-8c39-de61ef898b4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836654865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.2836654865
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.3857728164
Short name T929
Test name
Test status
Simulation time 763522344 ps
CPU time 13.06 seconds
Started Dec 24 01:21:57 PM PST 23
Finished Dec 24 01:22:11 PM PST 23
Peak memory 211392 kb
Host smart-4dc384cc-6ffd-4a3b-a2b6-b2e373ff4a1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857728164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3857728164
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1916192662
Short name T417
Test name
Test status
Simulation time 741851566 ps
CPU time 2098.78 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:57:05 PM PST 23
Peak memory 404024 kb
Host smart-fe20b6e0-9630-4b03-b1e7-28eea4bb935a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1916192662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.1916192662
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2744155794
Short name T260
Test name
Test status
Simulation time 14050835433 ps
CPU time 273.13 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:26:39 PM PST 23
Peak memory 202160 kb
Host smart-e41e5ab4-a70f-41bc-81d0-3da63f6ee755
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744155794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.2744155794
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2148607186
Short name T462
Test name
Test status
Simulation time 1513091772 ps
CPU time 78.21 seconds
Started Dec 24 01:21:59 PM PST 23
Finished Dec 24 01:23:19 PM PST 23
Peak memory 322720 kb
Host smart-2600b9c3-dcf2-4ad6-8055-d8b97b4482d8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148607186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.2148607186
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1868813840
Short name T795
Test name
Test status
Simulation time 1286361826 ps
CPU time 172.05 seconds
Started Dec 24 01:22:56 PM PST 23
Finished Dec 24 01:25:49 PM PST 23
Peak memory 355444 kb
Host smart-3bc3d406-c64e-4bd0-9aa7-d8d9b0656ba1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868813840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.1868813840
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.2541967473
Short name T826
Test name
Test status
Simulation time 79894752 ps
CPU time 0.62 seconds
Started Dec 24 01:22:56 PM PST 23
Finished Dec 24 01:22:58 PM PST 23
Peak memory 201536 kb
Host smart-a7f992c7-81fc-4d5b-9f09-1af4328092e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541967473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.2541967473
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.3021222361
Short name T873
Test name
Test status
Simulation time 73751611474 ps
CPU time 1717.1 seconds
Started Dec 24 01:22:48 PM PST 23
Finished Dec 24 01:51:27 PM PST 23
Peak memory 202136 kb
Host smart-25269ebd-5512-4d82-b1e2-3cfb9e7a31e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021222361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.3021222361
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.2903845786
Short name T665
Test name
Test status
Simulation time 63776495064 ps
CPU time 783.4 seconds
Started Dec 24 01:23:00 PM PST 23
Finished Dec 24 01:36:05 PM PST 23
Peak memory 359628 kb
Host smart-187bd441-403d-4069-95d0-b5c979b8c5ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903845786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.2903845786
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.1217999631
Short name T414
Test name
Test status
Simulation time 44151305145 ps
CPU time 101.93 seconds
Started Dec 24 01:23:01 PM PST 23
Finished Dec 24 01:24:44 PM PST 23
Peak memory 210392 kb
Host smart-073773bd-1b95-45bc-8f36-c0dfd22f8274
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217999631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.1217999631
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.3912831119
Short name T294
Test name
Test status
Simulation time 788057595 ps
CPU time 100.44 seconds
Started Dec 24 01:23:03 PM PST 23
Finished Dec 24 01:24:44 PM PST 23
Peak memory 348320 kb
Host smart-4451b32b-f904-4ced-b96c-f83cbceb4e3e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912831119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.3912831119
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3719329200
Short name T264
Test name
Test status
Simulation time 2455215523 ps
CPU time 81.12 seconds
Started Dec 24 01:23:13 PM PST 23
Finished Dec 24 01:24:35 PM PST 23
Peak memory 211344 kb
Host smart-3eb03c6a-3fb5-43cd-8aca-506b087c69c7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719329200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.3719329200
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.3676810092
Short name T764
Test name
Test status
Simulation time 7183643581 ps
CPU time 141.94 seconds
Started Dec 24 01:23:02 PM PST 23
Finished Dec 24 01:25:25 PM PST 23
Peak memory 202012 kb
Host smart-71679813-732e-432f-911a-4c7d8d349dfd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676810092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.3676810092
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.941872488
Short name T253
Test name
Test status
Simulation time 16935132157 ps
CPU time 462.93 seconds
Started Dec 24 01:22:59 PM PST 23
Finished Dec 24 01:30:44 PM PST 23
Peak memory 373984 kb
Host smart-4959c48c-385c-4f86-b5e8-5ef25ebdbedc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941872488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multip
le_keys.941872488
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.3222325815
Short name T721
Test name
Test status
Simulation time 668871631 ps
CPU time 44.66 seconds
Started Dec 24 01:23:02 PM PST 23
Finished Dec 24 01:23:48 PM PST 23
Peak memory 283912 kb
Host smart-8e0778d2-3d6f-4e7c-9c07-df5aaad473b5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222325815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.3222325815
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2834280995
Short name T931
Test name
Test status
Simulation time 26533425937 ps
CPU time 340.92 seconds
Started Dec 24 01:22:57 PM PST 23
Finished Dec 24 01:28:39 PM PST 23
Peak memory 202024 kb
Host smart-6d57b55a-78c3-4be8-a4c5-8cf2f38a2f5b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834280995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.2834280995
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.1606685228
Short name T456
Test name
Test status
Simulation time 353860674 ps
CPU time 5.9 seconds
Started Dec 24 01:23:03 PM PST 23
Finished Dec 24 01:23:10 PM PST 23
Peak memory 202392 kb
Host smart-b7e3ea45-9ee0-4a7c-906b-76a9fbe0da84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606685228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1606685228
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.1493173272
Short name T537
Test name
Test status
Simulation time 35559717437 ps
CPU time 661.25 seconds
Started Dec 24 01:23:01 PM PST 23
Finished Dec 24 01:34:03 PM PST 23
Peak memory 372924 kb
Host smart-cfe70c2d-6ffe-43ef-9171-52a93afb6d9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493173272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1493173272
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.3514595916
Short name T819
Test name
Test status
Simulation time 7637096356 ps
CPU time 23.44 seconds
Started Dec 24 01:22:39 PM PST 23
Finished Dec 24 01:23:07 PM PST 23
Peak memory 202140 kb
Host smart-31831d97-ec31-4313-909d-69904eeae863
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514595916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3514595916
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.60305671
Short name T811
Test name
Test status
Simulation time 3447554709 ps
CPU time 1577.39 seconds
Started Dec 24 01:22:57 PM PST 23
Finished Dec 24 01:49:16 PM PST 23
Peak memory 536280 kb
Host smart-509f78a4-be16-4af6-b8e9-9981967a75c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=60305671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.60305671
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1632982539
Short name T675
Test name
Test status
Simulation time 6716225105 ps
CPU time 259.22 seconds
Started Dec 24 01:22:58 PM PST 23
Finished Dec 24 01:27:18 PM PST 23
Peak memory 202088 kb
Host smart-aba8c719-6e93-40a8-96b2-6acac6740bf9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632982539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.1632982539
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2313450978
Short name T363
Test name
Test status
Simulation time 6430961149 ps
CPU time 40.56 seconds
Started Dec 24 01:23:00 PM PST 23
Finished Dec 24 01:23:42 PM PST 23
Peak memory 261436 kb
Host smart-26d4bf9e-7e0c-4199-a054-86174fb348e0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313450978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2313450978
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1351367602
Short name T616
Test name
Test status
Simulation time 1455981298 ps
CPU time 100.86 seconds
Started Dec 24 01:22:55 PM PST 23
Finished Dec 24 01:24:37 PM PST 23
Peak memory 305444 kb
Host smart-171c413d-6e28-4633-97e9-507a907769a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351367602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.1351367602
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.3482318110
Short name T857
Test name
Test status
Simulation time 191259381 ps
CPU time 0.71 seconds
Started Dec 24 01:22:58 PM PST 23
Finished Dec 24 01:23:00 PM PST 23
Peak memory 201800 kb
Host smart-a0355ac8-8120-4e95-9864-7a2d6a6a48dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482318110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.3482318110
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.3116960152
Short name T324
Test name
Test status
Simulation time 273942273059 ps
CPU time 2557.53 seconds
Started Dec 24 01:22:59 PM PST 23
Finished Dec 24 02:05:38 PM PST 23
Peak memory 202236 kb
Host smart-a5a51c1a-d6a6-4bcb-a415-ccbd9118c940
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116960152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.3116960152
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.805238652
Short name T887
Test name
Test status
Simulation time 18813960853 ps
CPU time 214.47 seconds
Started Dec 24 01:23:05 PM PST 23
Finished Dec 24 01:26:40 PM PST 23
Peak memory 210300 kb
Host smart-c79211fd-039a-4d17-91de-8bac974c4e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805238652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_esc
alation.805238652
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.3152799740
Short name T853
Test name
Test status
Simulation time 1539369384 ps
CPU time 63.4 seconds
Started Dec 24 01:23:13 PM PST 23
Finished Dec 24 01:24:18 PM PST 23
Peak memory 297092 kb
Host smart-e53bac2d-841c-4541-ad3c-90598127aa5e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152799740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.3152799740
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.4126792388
Short name T628
Test name
Test status
Simulation time 5515178783 ps
CPU time 79.8 seconds
Started Dec 24 01:23:00 PM PST 23
Finished Dec 24 01:24:22 PM PST 23
Peak memory 218532 kb
Host smart-b4f75a9c-45ec-433c-9697-8808a9d90868
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126792388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.4126792388
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.944374051
Short name T707
Test name
Test status
Simulation time 19702646546 ps
CPU time 312.96 seconds
Started Dec 24 01:22:59 PM PST 23
Finished Dec 24 01:28:13 PM PST 23
Peak memory 202416 kb
Host smart-bddad90e-ed22-4151-9268-a92291e6ce6f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944374051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_mem_walk.944374051
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.408913500
Short name T956
Test name
Test status
Simulation time 51834192466 ps
CPU time 829.62 seconds
Started Dec 24 01:22:59 PM PST 23
Finished Dec 24 01:36:50 PM PST 23
Peak memory 371988 kb
Host smart-3b027156-01d4-42df-842d-737490f0b908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408913500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multip
le_keys.408913500
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.3907931672
Short name T801
Test name
Test status
Simulation time 1004731039 ps
CPU time 146.43 seconds
Started Dec 24 01:23:03 PM PST 23
Finished Dec 24 01:25:31 PM PST 23
Peak memory 373884 kb
Host smart-f9a07b3c-add5-4412-87f1-45e342d487f2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907931672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.3907931672
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1653813008
Short name T714
Test name
Test status
Simulation time 20568424774 ps
CPU time 412.03 seconds
Started Dec 24 01:23:01 PM PST 23
Finished Dec 24 01:29:54 PM PST 23
Peak memory 202248 kb
Host smart-47d4378b-d3cd-4b1f-98bb-9a8eb4124898
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653813008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.1653813008
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.740510756
Short name T596
Test name
Test status
Simulation time 1350434853 ps
CPU time 7.18 seconds
Started Dec 24 01:23:05 PM PST 23
Finished Dec 24 01:23:13 PM PST 23
Peak memory 202320 kb
Host smart-983bc065-881e-4c7e-89e8-0223ea44e6f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740510756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.740510756
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.2675456383
Short name T458
Test name
Test status
Simulation time 3111251305 ps
CPU time 678.87 seconds
Started Dec 24 01:23:03 PM PST 23
Finished Dec 24 01:34:23 PM PST 23
Peak memory 379040 kb
Host smart-5c8759be-2f88-49a3-b29b-4581069dc46c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675456383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2675456383
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.3524857504
Short name T233
Test name
Test status
Simulation time 24019591781 ps
CPU time 26.02 seconds
Started Dec 24 01:22:56 PM PST 23
Finished Dec 24 01:23:23 PM PST 23
Peak memory 202164 kb
Host smart-e8e4cead-31dc-48d3-bda4-98539b8eb90e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524857504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3524857504
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1514049718
Short name T291
Test name
Test status
Simulation time 3530248925 ps
CPU time 4990.25 seconds
Started Dec 24 01:23:02 PM PST 23
Finished Dec 24 02:46:14 PM PST 23
Peak memory 690888 kb
Host smart-bc522502-cbe0-4335-b71b-c3ed6922971c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1514049718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1514049718
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2153420284
Short name T742
Test name
Test status
Simulation time 5269600762 ps
CPU time 187.8 seconds
Started Dec 24 01:23:00 PM PST 23
Finished Dec 24 01:26:10 PM PST 23
Peak memory 202176 kb
Host smart-b173724f-232e-48ea-84d4-0104d3dfe1da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153420284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.2153420284
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1053296656
Short name T769
Test name
Test status
Simulation time 731936294 ps
CPU time 38.79 seconds
Started Dec 24 01:23:14 PM PST 23
Finished Dec 24 01:23:54 PM PST 23
Peak memory 253328 kb
Host smart-2a4842f3-f8fa-450f-907b-47cde03af316
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053296656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.1053296656
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1604171993
Short name T744
Test name
Test status
Simulation time 38794550903 ps
CPU time 1279.64 seconds
Started Dec 24 01:23:14 PM PST 23
Finished Dec 24 01:44:35 PM PST 23
Peak memory 375956 kb
Host smart-e4fbea0b-8045-46df-890d-16b496053cfa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604171993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.1604171993
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.3774451256
Short name T696
Test name
Test status
Simulation time 33303309 ps
CPU time 0.63 seconds
Started Dec 24 01:23:14 PM PST 23
Finished Dec 24 01:23:16 PM PST 23
Peak memory 201756 kb
Host smart-189ade6a-c309-47f9-81aa-c1470d75b54c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774451256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.3774451256
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.1889449156
Short name T569
Test name
Test status
Simulation time 29030419525 ps
CPU time 2007.37 seconds
Started Dec 24 01:22:56 PM PST 23
Finished Dec 24 01:56:24 PM PST 23
Peak memory 202132 kb
Host smart-2c1aaa7a-dbe1-48ce-b6c3-a66c5c0459a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889449156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.1889449156
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.4147644987
Short name T955
Test name
Test status
Simulation time 121462908350 ps
CPU time 1192.25 seconds
Started Dec 24 01:23:13 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 374888 kb
Host smart-e488c71a-f48b-46b3-a592-412624c36d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147644987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab
le.4147644987
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.2466646190
Short name T620
Test name
Test status
Simulation time 9902465236 ps
CPU time 195.07 seconds
Started Dec 24 01:23:12 PM PST 23
Finished Dec 24 01:26:28 PM PST 23
Peak memory 210316 kb
Host smart-a3a8dfa6-46f4-404b-9f4d-fa2ebb315b23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466646190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.2466646190
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.3736197895
Short name T861
Test name
Test status
Simulation time 783374712 ps
CPU time 94.54 seconds
Started Dec 24 01:23:13 PM PST 23
Finished Dec 24 01:24:49 PM PST 23
Peak memory 348228 kb
Host smart-cddc1376-be2b-485e-8ca8-619213b39bff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736197895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.3736197895
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2003453348
Short name T944
Test name
Test status
Simulation time 4464226120 ps
CPU time 141.01 seconds
Started Dec 24 01:23:12 PM PST 23
Finished Dec 24 01:25:35 PM PST 23
Peak memory 210608 kb
Host smart-fae72c45-cdd5-4d76-b5fc-31c005641d30
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003453348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.2003453348
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.3823981254
Short name T729
Test name
Test status
Simulation time 7902126384 ps
CPU time 128 seconds
Started Dec 24 01:23:13 PM PST 23
Finished Dec 24 01:25:23 PM PST 23
Peak memory 202372 kb
Host smart-e7b3fa3e-be9a-45b9-a25b-6cd7838bb082
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823981254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.3823981254
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.3324465044
Short name T652
Test name
Test status
Simulation time 17175801762 ps
CPU time 785.97 seconds
Started Dec 24 01:22:59 PM PST 23
Finished Dec 24 01:36:06 PM PST 23
Peak memory 379108 kb
Host smart-530eb9e0-0722-4a02-836b-7da66bdd9c6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324465044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.3324465044
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.2133521693
Short name T401
Test name
Test status
Simulation time 759336428 ps
CPU time 39.16 seconds
Started Dec 24 01:23:00 PM PST 23
Finished Dec 24 01:23:40 PM PST 23
Peak memory 252372 kb
Host smart-04f2a676-04e5-4143-aa20-fed3aaab0ecd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133521693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.2133521693
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2761658517
Short name T775
Test name
Test status
Simulation time 7215792293 ps
CPU time 222.93 seconds
Started Dec 24 01:23:01 PM PST 23
Finished Dec 24 01:26:46 PM PST 23
Peak memory 202180 kb
Host smart-6e800470-9e44-45f3-b6f1-a8361d040b07
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761658517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.2761658517
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.167565266
Short name T634
Test name
Test status
Simulation time 8004318765 ps
CPU time 569.24 seconds
Started Dec 24 01:23:13 PM PST 23
Finished Dec 24 01:32:44 PM PST 23
Peak memory 375912 kb
Host smart-1ceaff8d-829a-42dc-8adb-726adb5186b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167565266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.167565266
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.341891378
Short name T854
Test name
Test status
Simulation time 3622932223 ps
CPU time 63.43 seconds
Started Dec 24 01:23:03 PM PST 23
Finished Dec 24 01:24:07 PM PST 23
Peak memory 301300 kb
Host smart-25d9f4b5-e682-4128-b0dd-6aac04c3050f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341891378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.341891378
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.1105617306
Short name T622
Test name
Test status
Simulation time 39974150762 ps
CPU time 4205.57 seconds
Started Dec 24 01:23:12 PM PST 23
Finished Dec 24 02:33:19 PM PST 23
Peak memory 382204 kb
Host smart-ce0449e3-7e0e-439a-97c4-5e02162b5019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105617306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.1105617306
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3057272478
Short name T238
Test name
Test status
Simulation time 364655743 ps
CPU time 3287.86 seconds
Started Dec 24 01:23:11 PM PST 23
Finished Dec 24 02:18:01 PM PST 23
Peak memory 448244 kb
Host smart-f4b9511b-c841-4068-a72a-58b8bd551d1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3057272478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3057272478
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3499037722
Short name T297
Test name
Test status
Simulation time 4201918164 ps
CPU time 307.06 seconds
Started Dec 24 01:23:12 PM PST 23
Finished Dec 24 01:28:20 PM PST 23
Peak memory 202092 kb
Host smart-02eeaf86-9c6d-4548-9052-9ba93ccc05d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499037722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.3499037722
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1223825217
Short name T894
Test name
Test status
Simulation time 2792486550 ps
CPU time 37.09 seconds
Started Dec 24 01:23:00 PM PST 23
Finished Dec 24 01:23:39 PM PST 23
Peak memory 242112 kb
Host smart-e15afcd3-b7a2-46da-9918-91a24e19d930
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223825217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1223825217
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.780181836
Short name T839
Test name
Test status
Simulation time 27900974105 ps
CPU time 1183.51 seconds
Started Dec 24 01:23:26 PM PST 23
Finished Dec 24 01:43:12 PM PST 23
Peak memory 377988 kb
Host smart-adfcf2e2-7e83-4f88-9d27-1018d6fc698c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780181836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.sram_ctrl_access_during_key_req.780181836
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.279349834
Short name T22
Test name
Test status
Simulation time 95274434 ps
CPU time 0.62 seconds
Started Dec 24 01:23:26 PM PST 23
Finished Dec 24 01:23:28 PM PST 23
Peak memory 201808 kb
Host smart-017326b9-7871-4fc6-b558-1b36a2637195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279349834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.279349834
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.3230309209
Short name T499
Test name
Test status
Simulation time 10941126859 ps
CPU time 481.36 seconds
Started Dec 24 01:23:24 PM PST 23
Finished Dec 24 01:31:26 PM PST 23
Peak memory 202064 kb
Host smart-5de25ddf-9f28-4a40-9a17-440b4d936d12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230309209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.3230309209
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.4051835839
Short name T378
Test name
Test status
Simulation time 48415560616 ps
CPU time 255.08 seconds
Started Dec 24 01:23:16 PM PST 23
Finished Dec 24 01:27:32 PM PST 23
Peak memory 211492 kb
Host smart-989aa4fc-3e6b-4155-aa47-29ad598c799a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051835839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.4051835839
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.805335434
Short name T457
Test name
Test status
Simulation time 3117004555 ps
CPU time 102.49 seconds
Started Dec 24 01:23:13 PM PST 23
Finished Dec 24 01:24:57 PM PST 23
Peak memory 320800 kb
Host smart-a745f890-c3c6-41ef-91c1-763acd9628e8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805335434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.sram_ctrl_max_throughput.805335434
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1906185618
Short name T767
Test name
Test status
Simulation time 4537143791 ps
CPU time 160.78 seconds
Started Dec 24 01:23:32 PM PST 23
Finished Dec 24 01:26:16 PM PST 23
Peak memory 211544 kb
Host smart-973a5aa0-57c9-4b0b-8492-0b48a6d4774e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906185618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.1906185618
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.1155056952
Short name T619
Test name
Test status
Simulation time 14354110668 ps
CPU time 289.16 seconds
Started Dec 24 01:23:26 PM PST 23
Finished Dec 24 01:28:16 PM PST 23
Peak memory 202200 kb
Host smart-2acc0e03-5f76-48a0-a6d7-22bf1459e6df
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155056952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.1155056952
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.3704347323
Short name T582
Test name
Test status
Simulation time 24124612503 ps
CPU time 597.05 seconds
Started Dec 24 01:23:12 PM PST 23
Finished Dec 24 01:33:11 PM PST 23
Peak memory 375956 kb
Host smart-07736d39-0e32-4d46-87d7-e952584a62f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704347323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.3704347323
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.2103811223
Short name T565
Test name
Test status
Simulation time 6419313804 ps
CPU time 10.69 seconds
Started Dec 24 01:23:12 PM PST 23
Finished Dec 24 01:23:24 PM PST 23
Peak memory 219676 kb
Host smart-62f95e1b-002a-4367-b493-1721970aad5d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103811223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.2103811223
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.289632561
Short name T851
Test name
Test status
Simulation time 38585033357 ps
CPU time 256.43 seconds
Started Dec 24 01:23:14 PM PST 23
Finished Dec 24 01:27:32 PM PST 23
Peak memory 202140 kb
Host smart-99303d69-7c3f-46eb-be9f-c733a5766a1b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289632561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.sram_ctrl_partial_access_b2b.289632561
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.2842613000
Short name T673
Test name
Test status
Simulation time 360999754 ps
CPU time 14.23 seconds
Started Dec 24 01:23:30 PM PST 23
Finished Dec 24 01:23:47 PM PST 23
Peak memory 202416 kb
Host smart-994dc842-8781-4b29-a8a3-678ed9ac8722
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842613000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2842613000
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.3679793084
Short name T49
Test name
Test status
Simulation time 20665971284 ps
CPU time 1202.12 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:43:33 PM PST 23
Peak memory 378272 kb
Host smart-90b8d0e8-4c4f-4380-abf2-5c00b1aabcfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679793084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3679793084
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.2022376043
Short name T315
Test name
Test status
Simulation time 857322270 ps
CPU time 37.19 seconds
Started Dec 24 01:23:13 PM PST 23
Finished Dec 24 01:23:52 PM PST 23
Peak memory 202012 kb
Host smart-b403beff-9e72-4265-be01-cca4149dad89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022376043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2022376043
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.3313167737
Short name T345
Test name
Test status
Simulation time 249664535542 ps
CPU time 6252.23 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 03:07:44 PM PST 23
Peak memory 380292 kb
Host smart-2bd2a17a-0e67-48a5-82a6-35ee71504670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313167737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.3313167737
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3595690671
Short name T481
Test name
Test status
Simulation time 5390304682 ps
CPU time 3425.99 seconds
Started Dec 24 01:23:27 PM PST 23
Finished Dec 24 02:20:36 PM PST 23
Peak memory 732124 kb
Host smart-cf935b5c-3d7c-4a0f-93bb-9332a61ed275
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3595690671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3595690671
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.790097704
Short name T111
Test name
Test status
Simulation time 5068248661 ps
CPU time 342.71 seconds
Started Dec 24 01:23:13 PM PST 23
Finished Dec 24 01:28:57 PM PST 23
Peak memory 210312 kb
Host smart-21022910-3c71-40cf-a054-4af92731f00e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790097704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.sram_ctrl_stress_pipeline.790097704
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3367792919
Short name T585
Test name
Test status
Simulation time 771347410 ps
CPU time 68.42 seconds
Started Dec 24 01:23:25 PM PST 23
Finished Dec 24 01:24:35 PM PST 23
Peak memory 291896 kb
Host smart-ec2303e3-1b5a-47d1-b9ed-651f2e6fad55
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367792919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3367792919
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2486331341
Short name T495
Test name
Test status
Simulation time 113943885185 ps
CPU time 1282.77 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:44:55 PM PST 23
Peak memory 378968 kb
Host smart-8b74acb0-4be1-4bb0-a5b0-71cabd4e212f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486331341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.2486331341
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.1337663882
Short name T559
Test name
Test status
Simulation time 20699488 ps
CPU time 0.63 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:23:33 PM PST 23
Peak memory 201852 kb
Host smart-357d2758-f3c5-4666-b8b1-3042d7c9bff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337663882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.1337663882
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.4094508465
Short name T896
Test name
Test status
Simulation time 48763998203 ps
CPU time 1807.59 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:53:39 PM PST 23
Peak memory 379008 kb
Host smart-91debfc1-5296-4432-8541-bd07703a3d73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094508465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.4094508465
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.2483359786
Short name T421
Test name
Test status
Simulation time 6518587310 ps
CPU time 75.81 seconds
Started Dec 24 01:23:30 PM PST 23
Finished Dec 24 01:24:49 PM PST 23
Peak memory 213788 kb
Host smart-8a08f980-b7d7-460a-b011-ed99c8842f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483359786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.2483359786
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.1444147096
Short name T731
Test name
Test status
Simulation time 763305044 ps
CPU time 90.54 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:25:01 PM PST 23
Peak memory 322756 kb
Host smart-31b00dbe-127b-45c3-bb89-c79287b3218f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444147096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.1444147096
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2085501669
Short name T451
Test name
Test status
Simulation time 14038394766 ps
CPU time 138.4 seconds
Started Dec 24 01:23:31 PM PST 23
Finished Dec 24 01:25:52 PM PST 23
Peak memory 218496 kb
Host smart-bf424619-939c-4bea-8d45-107ed94d3188
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085501669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.2085501669
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.428097888
Short name T489
Test name
Test status
Simulation time 7048287198 ps
CPU time 141.79 seconds
Started Dec 24 01:23:31 PM PST 23
Finished Dec 24 01:25:56 PM PST 23
Peak memory 202276 kb
Host smart-fc738770-f48b-4bae-95fe-f0b28e8b53ee
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428097888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl
_mem_walk.428097888
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.3738204159
Short name T750
Test name
Test status
Simulation time 24030381074 ps
CPU time 1033.89 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 366680 kb
Host smart-7726ffbd-e85f-49e0-b7a2-8161cedf575c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738204159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.3738204159
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.1230378426
Short name T895
Test name
Test status
Simulation time 1694020795 ps
CPU time 132.49 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:25:45 PM PST 23
Peak memory 346328 kb
Host smart-6442dab5-0303-4fdf-b78c-fb7045c34959
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230378426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.1230378426
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1991177560
Short name T772
Test name
Test status
Simulation time 40081205334 ps
CPU time 472.97 seconds
Started Dec 24 01:23:30 PM PST 23
Finished Dec 24 01:31:27 PM PST 23
Peak memory 202160 kb
Host smart-a644f579-e075-4c98-ac6e-56fef9d13ad3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991177560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.1991177560
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.1592264172
Short name T592
Test name
Test status
Simulation time 360663976 ps
CPU time 5.6 seconds
Started Dec 24 01:23:31 PM PST 23
Finished Dec 24 01:23:40 PM PST 23
Peak memory 202416 kb
Host smart-dc8de579-fede-41c2-bb67-f17a3ad40493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592264172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1592264172
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.1224813284
Short name T971
Test name
Test status
Simulation time 2012527268 ps
CPU time 427.67 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:30:40 PM PST 23
Peak memory 351256 kb
Host smart-2f65f048-6a2d-4b4e-b7ef-7dceee909cfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224813284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1224813284
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.1342606973
Short name T296
Test name
Test status
Simulation time 4551765345 ps
CPU time 115.47 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:25:27 PM PST 23
Peak memory 372252 kb
Host smart-9d7d17cb-079c-49ef-b1f4-27c0e1bf085a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342606973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1342606973
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.3705509124
Short name T942
Test name
Test status
Simulation time 233894217277 ps
CPU time 4711.07 seconds
Started Dec 24 01:23:32 PM PST 23
Finished Dec 24 02:42:06 PM PST 23
Peak memory 376088 kb
Host smart-89ae27c2-622e-4e6d-b06a-ad4aed60fe56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705509124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.3705509124
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.4267182060
Short name T859
Test name
Test status
Simulation time 1116827095 ps
CPU time 5739.78 seconds
Started Dec 24 01:23:32 PM PST 23
Finished Dec 24 02:59:15 PM PST 23
Peak memory 654316 kb
Host smart-3f7c09fe-e907-4400-95cb-b3bde2fca465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4267182060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.4267182060
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2840599490
Short name T302
Test name
Test status
Simulation time 9339390188 ps
CPU time 367.2 seconds
Started Dec 24 01:23:27 PM PST 23
Finished Dec 24 01:29:36 PM PST 23
Peak memory 202092 kb
Host smart-e279a7f6-3b96-4b47-b921-59fa87adf7bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840599490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.2840599490
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3649024713
Short name T661
Test name
Test status
Simulation time 2911875393 ps
CPU time 57.36 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:24:27 PM PST 23
Peak memory 283912 kb
Host smart-73306ced-ac1e-4c12-aef7-f8e2b396f991
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649024713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3649024713
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1209699673
Short name T318
Test name
Test status
Simulation time 39557040609 ps
CPU time 1127.2 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:42:17 PM PST 23
Peak memory 378164 kb
Host smart-fd7f1341-1964-470f-bef5-006121984017
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209699673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.1209699673
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.1529521877
Short name T356
Test name
Test status
Simulation time 34078705 ps
CPU time 0.62 seconds
Started Dec 24 01:23:30 PM PST 23
Finished Dec 24 01:23:34 PM PST 23
Peak memory 201872 kb
Host smart-5f47c485-affe-4039-81b2-5552d3dffda1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529521877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.1529521877
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.703245584
Short name T18
Test name
Test status
Simulation time 253299068418 ps
CPU time 2003.36 seconds
Started Dec 24 01:23:27 PM PST 23
Finished Dec 24 01:56:52 PM PST 23
Peak memory 202168 kb
Host smart-e8e30d89-b59f-41dd-b799-5b40980dcfb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703245584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.
703245584
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.572966529
Short name T396
Test name
Test status
Simulation time 4498713747 ps
CPU time 166 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:26:17 PM PST 23
Peak memory 367780 kb
Host smart-15f2ac19-30a9-4324-8d59-534ec26d37ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572966529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.sram_ctrl_max_throughput.572966529
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.4019418733
Short name T81
Test name
Test status
Simulation time 26111489138 ps
CPU time 144.35 seconds
Started Dec 24 01:23:26 PM PST 23
Finished Dec 24 01:25:52 PM PST 23
Peak memory 214544 kb
Host smart-dc583a0b-4d66-425b-9185-19845655165a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019418733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.4019418733
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.4217347543
Short name T280
Test name
Test status
Simulation time 13789720889 ps
CPU time 140.56 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:25:50 PM PST 23
Peak memory 202128 kb
Host smart-27029445-da29-46ab-abb0-36a5a936a287
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217347543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.4217347543
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.1125778127
Short name T608
Test name
Test status
Simulation time 3300476727 ps
CPU time 118.24 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:25:30 PM PST 23
Peak memory 328864 kb
Host smart-5047fa6a-342a-4dbe-b9db-231725026c2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125778127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.1125778127
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.375058013
Short name T571
Test name
Test status
Simulation time 1216311276 ps
CPU time 43.6 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:24:16 PM PST 23
Peak memory 202304 kb
Host smart-9759c368-a3d1-4916-a597-7c82da691162
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375058013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s
ram_ctrl_partial_access.375058013
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2466905773
Short name T266
Test name
Test status
Simulation time 5714564033 ps
CPU time 342.96 seconds
Started Dec 24 01:23:26 PM PST 23
Finished Dec 24 01:29:11 PM PST 23
Peak memory 202164 kb
Host smart-a11a901b-a2d5-4f34-8f83-fd09a7e64716
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466905773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.2466905773
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.3151295695
Short name T901
Test name
Test status
Simulation time 1348265373 ps
CPU time 13.34 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:23:45 PM PST 23
Peak memory 202332 kb
Host smart-be5cc4fd-3044-4c9b-8265-f65da243f66e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151295695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3151295695
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.4025684864
Short name T683
Test name
Test status
Simulation time 3910511011 ps
CPU time 1153.15 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:42:45 PM PST 23
Peak memory 374808 kb
Host smart-1f28b1c6-0b81-4da0-9e91-ac7c5532d6db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025684864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.4025684864
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.944027029
Short name T450
Test name
Test status
Simulation time 2601804980 ps
CPU time 104.03 seconds
Started Dec 24 01:23:27 PM PST 23
Finished Dec 24 01:25:14 PM PST 23
Peak memory 352376 kb
Host smart-287a29fb-ab7b-41f8-811a-4377e145ad5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944027029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.944027029
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2716579593
Short name T835
Test name
Test status
Simulation time 3207351656 ps
CPU time 3481.46 seconds
Started Dec 24 01:23:27 PM PST 23
Finished Dec 24 02:21:32 PM PST 23
Peak memory 529380 kb
Host smart-d28a7ae1-9045-40ba-859f-273b95151f7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2716579593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2716579593
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2769222514
Short name T734
Test name
Test status
Simulation time 25848640329 ps
CPU time 420.35 seconds
Started Dec 24 01:23:25 PM PST 23
Finished Dec 24 01:30:27 PM PST 23
Peak memory 202084 kb
Host smart-8799bf40-203b-43e2-8161-d05d1f3c9386
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769222514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.2769222514
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2945350128
Short name T299
Test name
Test status
Simulation time 737328337 ps
CPU time 50.52 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:24:21 PM PST 23
Peak memory 273080 kb
Host smart-be349589-f37f-47f5-bc4d-a4049708af02
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945350128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2945350128
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1201742641
Short name T626
Test name
Test status
Simulation time 4070682218 ps
CPU time 334.51 seconds
Started Dec 24 01:23:26 PM PST 23
Finished Dec 24 01:29:02 PM PST 23
Peak memory 338104 kb
Host smart-ebd07e4e-ed8f-4961-bf32-f809ebe9dd36
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201742641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.1201742641
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.1788085271
Short name T423
Test name
Test status
Simulation time 84864987 ps
CPU time 0.63 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:23:33 PM PST 23
Peak memory 201860 kb
Host smart-4bac7d01-6500-4238-93f6-0f2406073422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788085271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.1788085271
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.1337934406
Short name T766
Test name
Test status
Simulation time 160201960304 ps
CPU time 2679.35 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 02:08:12 PM PST 23
Peak memory 202216 kb
Host smart-e9fbdb29-8018-4c41-9dd1-6973383120a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337934406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.1337934406
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.442341233
Short name T751
Test name
Test status
Simulation time 12063339435 ps
CPU time 57.42 seconds
Started Dec 24 01:23:32 PM PST 23
Finished Dec 24 01:24:32 PM PST 23
Peak memory 210312 kb
Host smart-0da21f21-d23c-4fd6-8003-6b009dcd7bb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442341233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_esc
alation.442341233
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.4242130715
Short name T311
Test name
Test status
Simulation time 2689004708 ps
CPU time 28.22 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:24:00 PM PST 23
Peak memory 215904 kb
Host smart-f298c0fc-6964-41eb-a563-376def21e9e3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242130715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.4242130715
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.390613277
Short name T258
Test name
Test status
Simulation time 9177833628 ps
CPU time 147.62 seconds
Started Dec 24 01:23:34 PM PST 23
Finished Dec 24 01:26:03 PM PST 23
Peak memory 210564 kb
Host smart-4c694094-1df5-4a82-aba6-67be9432f63a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390613277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.sram_ctrl_mem_partial_access.390613277
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.3266183407
Short name T950
Test name
Test status
Simulation time 4026991659 ps
CPU time 255.6 seconds
Started Dec 24 01:23:32 PM PST 23
Finished Dec 24 01:27:50 PM PST 23
Peak memory 202036 kb
Host smart-e9dc3ad2-b066-4876-8aa1-9f5253a721cb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266183407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.3266183407
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.4156657693
Short name T760
Test name
Test status
Simulation time 10035728384 ps
CPU time 1375.98 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:46:29 PM PST 23
Peak memory 378916 kb
Host smart-bc5e7fef-bd48-4126-b16c-064d1e915924
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156657693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.4156657693
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.229114250
Short name T930
Test name
Test status
Simulation time 2054258299 ps
CPU time 50.81 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:24:23 PM PST 23
Peak memory 289636 kb
Host smart-2ef350bc-7b5b-4836-be21-74ecce4a10c2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229114250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s
ram_ctrl_partial_access.229114250
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2744435910
Short name T858
Test name
Test status
Simulation time 21450171537 ps
CPU time 342.34 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:29:15 PM PST 23
Peak memory 202340 kb
Host smart-72df87a0-0d72-4be7-8a0f-85115512cc4b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744435910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.2744435910
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.1044219620
Short name T660
Test name
Test status
Simulation time 2389168071 ps
CPU time 5.86 seconds
Started Dec 24 01:23:26 PM PST 23
Finished Dec 24 01:23:34 PM PST 23
Peak memory 202492 kb
Host smart-ee3be467-09db-4d7b-b807-438deaede73d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044219620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1044219620
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.1795553859
Short name T360
Test name
Test status
Simulation time 15822733748 ps
CPU time 1003.67 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:40:16 PM PST 23
Peak memory 378068 kb
Host smart-c3b459c1-1ba1-4a31-812b-f9686a754319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795553859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1795553859
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.1118203324
Short name T241
Test name
Test status
Simulation time 1066359358 ps
CPU time 27.11 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:23:58 PM PST 23
Peak memory 202008 kb
Host smart-ecc09ec4-056a-4d07-8bae-5bb8dd8eb6c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118203324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1118203324
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.283382335
Short name T284
Test name
Test status
Simulation time 1278852974 ps
CPU time 5488.53 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 02:55:02 PM PST 23
Peak memory 698920 kb
Host smart-88df7702-c5e4-4ad5-926e-0bacfb364ee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=283382335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.283382335
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1403174494
Short name T460
Test name
Test status
Simulation time 21840174376 ps
CPU time 400.07 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:30:12 PM PST 23
Peak memory 202124 kb
Host smart-5d361e9f-ef8f-487a-9c0f-2e7d026e85d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403174494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.1403174494
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2119566183
Short name T540
Test name
Test status
Simulation time 719187628 ps
CPU time 30.65 seconds
Started Dec 24 01:23:32 PM PST 23
Finished Dec 24 01:24:05 PM PST 23
Peak memory 226032 kb
Host smart-a9bd5bbf-ee6c-4f64-8a51-2f76ef9d693b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119566183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2119566183
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2623434666
Short name T529
Test name
Test status
Simulation time 19680638622 ps
CPU time 983.03 seconds
Started Dec 24 01:23:34 PM PST 23
Finished Dec 24 01:39:59 PM PST 23
Peak memory 379104 kb
Host smart-992b050a-990c-4a19-b0e9-61961b373ee3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623434666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.2623434666
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.3980925003
Short name T910
Test name
Test status
Simulation time 16490390 ps
CPU time 0.66 seconds
Started Dec 24 01:23:30 PM PST 23
Finished Dec 24 01:23:34 PM PST 23
Peak memory 201788 kb
Host smart-df6c9e78-b6e7-4e40-b74a-7df3b5b84782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980925003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.3980925003
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.1755126728
Short name T466
Test name
Test status
Simulation time 5251732521 ps
CPU time 42.56 seconds
Started Dec 24 01:23:27 PM PST 23
Finished Dec 24 01:24:11 PM PST 23
Peak memory 210396 kb
Host smart-f928a075-8dbe-4a3b-a2d7-2f4759b2b84c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755126728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.1755126728
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.80910768
Short name T322
Test name
Test status
Simulation time 1231779784 ps
CPU time 186.37 seconds
Started Dec 24 01:23:34 PM PST 23
Finished Dec 24 01:26:42 PM PST 23
Peak memory 360504 kb
Host smart-818c333c-67db-41b0-8254-16a546398850
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80910768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_max_throughput.80910768
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2774256920
Short name T891
Test name
Test status
Simulation time 16325801347 ps
CPU time 154.22 seconds
Started Dec 24 01:23:33 PM PST 23
Finished Dec 24 01:26:09 PM PST 23
Peak memory 218424 kb
Host smart-36fa1705-0c8a-4d7e-9f73-ebdd809f561f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774256920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.2774256920
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.1437573843
Short name T885
Test name
Test status
Simulation time 121461313122 ps
CPU time 322.29 seconds
Started Dec 24 01:23:27 PM PST 23
Finished Dec 24 01:28:51 PM PST 23
Peak memory 202080 kb
Host smart-06c34b18-e16b-424f-b07e-0d5b2d8cce16
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437573843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.1437573843
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.2100225998
Short name T706
Test name
Test status
Simulation time 2835355676 ps
CPU time 154.2 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:26:06 PM PST 23
Peak memory 280980 kb
Host smart-28ace822-fdf2-473f-9492-ba33726cf86b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100225998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.2100225998
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.2385623251
Short name T577
Test name
Test status
Simulation time 814100532 ps
CPU time 36.42 seconds
Started Dec 24 01:23:27 PM PST 23
Finished Dec 24 01:24:05 PM PST 23
Peak memory 202076 kb
Host smart-ba9e9315-961d-4397-a3c9-afef9b567d9c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385623251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.2385623251
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3503052569
Short name T824
Test name
Test status
Simulation time 7526210936 ps
CPU time 470.13 seconds
Started Dec 24 01:23:27 PM PST 23
Finished Dec 24 01:31:19 PM PST 23
Peak memory 202068 kb
Host smart-92faa1c2-b403-4f2a-9b48-3341cb701464
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503052569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.3503052569
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.931495612
Short name T669
Test name
Test status
Simulation time 3036938456 ps
CPU time 14.03 seconds
Started Dec 24 01:23:30 PM PST 23
Finished Dec 24 01:23:47 PM PST 23
Peak memory 202456 kb
Host smart-c4bf196f-3de5-4556-aa90-3294b79ca49f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931495612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.931495612
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.1995562737
Short name T879
Test name
Test status
Simulation time 37535882106 ps
CPU time 527.73 seconds
Started Dec 24 01:23:25 PM PST 23
Finished Dec 24 01:32:13 PM PST 23
Peak memory 355500 kb
Host smart-397c6928-2565-4ccb-9e3a-eb284c8d04ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995562737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1995562737
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.2353486952
Short name T869
Test name
Test status
Simulation time 6021110768 ps
CPU time 152.51 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:26:05 PM PST 23
Peak memory 364752 kb
Host smart-ce14a611-b853-405b-ab44-09dda8c7abbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353486952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2353486952
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.3286149228
Short name T459
Test name
Test status
Simulation time 1574808646430 ps
CPU time 6418.3 seconds
Started Dec 24 01:23:32 PM PST 23
Finished Dec 24 03:10:34 PM PST 23
Peak memory 378008 kb
Host smart-b50262bb-5114-4781-b700-f8c818cba20b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286149228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.sram_ctrl_stress_all.3286149228
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1345964936
Short name T298
Test name
Test status
Simulation time 1894135919 ps
CPU time 5271.05 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 02:51:22 PM PST 23
Peak memory 696312 kb
Host smart-f40a7201-4fbd-4ec9-a797-9c9795ab3597
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1345964936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1345964936
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3364283671
Short name T108
Test name
Test status
Simulation time 18666927672 ps
CPU time 339.21 seconds
Started Dec 24 01:23:26 PM PST 23
Finished Dec 24 01:29:06 PM PST 23
Peak memory 202188 kb
Host smart-d998094b-ac07-4f60-a2c0-b1eed7d3c29b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364283671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.3364283671
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.606427897
Short name T613
Test name
Test status
Simulation time 789015870 ps
CPU time 145.96 seconds
Started Dec 24 01:23:27 PM PST 23
Finished Dec 24 01:25:55 PM PST 23
Peak memory 366664 kb
Host smart-334c67db-2d53-46dc-9044-3f60166dbc44
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606427897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_throughput_w_partial_write.606427897
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2977696894
Short name T958
Test name
Test status
Simulation time 22964403855 ps
CPU time 1084.52 seconds
Started Dec 24 01:23:35 PM PST 23
Finished Dec 24 01:41:41 PM PST 23
Peak memory 377012 kb
Host smart-982f751e-9779-475f-a02f-5b645992603f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977696894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.2977696894
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.4215516753
Short name T785
Test name
Test status
Simulation time 50926220 ps
CPU time 0.67 seconds
Started Dec 24 01:23:34 PM PST 23
Finished Dec 24 01:23:37 PM PST 23
Peak memory 201912 kb
Host smart-1eff8744-db7c-4230-a06a-613f20183c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215516753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.4215516753
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.647708252
Short name T250
Test name
Test status
Simulation time 105185511673 ps
CPU time 1811.96 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:53:43 PM PST 23
Peak memory 202048 kb
Host smart-a7e5dd51-fbc1-4e15-89ad-d98b9f1be07d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647708252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.
647708252
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.2256848895
Short name T385
Test name
Test status
Simulation time 29848523374 ps
CPU time 1299.27 seconds
Started Dec 24 01:23:40 PM PST 23
Finished Dec 24 01:45:21 PM PST 23
Peak memory 377968 kb
Host smart-f7bcda00-8892-4c31-b8bc-6c528273d68a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256848895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.2256848895
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.2660836601
Short name T128
Test name
Test status
Simulation time 4620787790 ps
CPU time 107.57 seconds
Started Dec 24 01:23:40 PM PST 23
Finished Dec 24 01:25:29 PM PST 23
Peak memory 211296 kb
Host smart-25259fb6-1998-4aef-a61f-d497d4d23295
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660836601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.2660836601
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.3539923677
Short name T601
Test name
Test status
Simulation time 1514987091 ps
CPU time 70.85 seconds
Started Dec 24 01:23:34 PM PST 23
Finished Dec 24 01:24:46 PM PST 23
Peak memory 300232 kb
Host smart-5bd38785-b0d4-419b-bf7a-9290093d25dc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539923677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.3539923677
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1908082662
Short name T840
Test name
Test status
Simulation time 993973898 ps
CPU time 75.96 seconds
Started Dec 24 01:23:41 PM PST 23
Finished Dec 24 01:24:59 PM PST 23
Peak memory 211024 kb
Host smart-42c4df3a-67f2-45be-af21-94adcbbaad07
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908082662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.1908082662
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.703344667
Short name T852
Test name
Test status
Simulation time 55057356157 ps
CPU time 297.23 seconds
Started Dec 24 01:23:36 PM PST 23
Finished Dec 24 01:28:34 PM PST 23
Peak memory 202116 kb
Host smart-a2acb64f-8d24-4cca-8cf1-421dc41c9084
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703344667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_mem_walk.703344667
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.347981384
Short name T484
Test name
Test status
Simulation time 21396161540 ps
CPU time 355.55 seconds
Started Dec 24 01:23:34 PM PST 23
Finished Dec 24 01:29:31 PM PST 23
Peak memory 340176 kb
Host smart-634f9f24-71e7-4906-97eb-3e867f818e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347981384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip
le_keys.347981384
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.3450613940
Short name T12
Test name
Test status
Simulation time 4004452226 ps
CPU time 21.6 seconds
Started Dec 24 01:23:35 PM PST 23
Finished Dec 24 01:23:58 PM PST 23
Peak memory 202048 kb
Host smart-9748e738-2b4e-4887-8baf-8b07ca2a55c1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450613940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.3450613940
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.804252113
Short name T807
Test name
Test status
Simulation time 98854386269 ps
CPU time 433.81 seconds
Started Dec 24 01:23:35 PM PST 23
Finished Dec 24 01:30:50 PM PST 23
Peak memory 210356 kb
Host smart-726d451a-66f6-46f7-973c-62e47f8a8aef
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804252113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.sram_ctrl_partial_access_b2b.804252113
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.3111330303
Short name T960
Test name
Test status
Simulation time 370729656 ps
CPU time 5.59 seconds
Started Dec 24 01:23:50 PM PST 23
Finished Dec 24 01:23:57 PM PST 23
Peak memory 202412 kb
Host smart-7e9a5e8f-055a-4bc2-87a9-106f54f4258f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111330303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.3111330303
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.1615197401
Short name T932
Test name
Test status
Simulation time 2969841108 ps
CPU time 421.9 seconds
Started Dec 24 01:23:41 PM PST 23
Finished Dec 24 01:30:45 PM PST 23
Peak memory 346332 kb
Host smart-f0755f1c-39c9-43bd-aeda-4928a409d426
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615197401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1615197401
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.966443391
Short name T251
Test name
Test status
Simulation time 1353282834 ps
CPU time 36.73 seconds
Started Dec 24 01:23:28 PM PST 23
Finished Dec 24 01:24:07 PM PST 23
Peak memory 282788 kb
Host smart-fa8cf8a7-93b9-4926-ab27-3c0167be3d4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966443391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.966443391
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.1265081160
Short name T373
Test name
Test status
Simulation time 35449904655 ps
CPU time 4549.25 seconds
Started Dec 24 01:23:41 PM PST 23
Finished Dec 24 02:39:32 PM PST 23
Peak memory 380036 kb
Host smart-8f5b81fa-9262-47b2-9e4b-ac2ad2199dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265081160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.1265081160
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1150388314
Short name T552
Test name
Test status
Simulation time 6304343084 ps
CPU time 5031.33 seconds
Started Dec 24 01:23:34 PM PST 23
Finished Dec 24 02:47:28 PM PST 23
Peak memory 459616 kb
Host smart-657c8b9d-eee9-4fe7-a3a7-5669539bd2a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1150388314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1150388314
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1300131012
Short name T644
Test name
Test status
Simulation time 18131237468 ps
CPU time 331.37 seconds
Started Dec 24 01:23:29 PM PST 23
Finished Dec 24 01:29:03 PM PST 23
Peak memory 202096 kb
Host smart-0f98cf69-e9b7-4fc4-9b69-21ba3709b94f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300131012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.1300131012
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3065689021
Short name T846
Test name
Test status
Simulation time 1513194123 ps
CPU time 90.43 seconds
Started Dec 24 01:23:49 PM PST 23
Finished Dec 24 01:25:21 PM PST 23
Peak memory 335088 kb
Host smart-b23963fb-9f98-4017-b1e8-f942e4b9c34c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065689021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3065689021
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3375309733
Short name T332
Test name
Test status
Simulation time 25844957881 ps
CPU time 651.75 seconds
Started Dec 24 01:23:46 PM PST 23
Finished Dec 24 01:34:39 PM PST 23
Peak memory 370868 kb
Host smart-6dd5509e-d2bb-4bb8-9559-6c4d70580422
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375309733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3375309733
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.3946053274
Short name T791
Test name
Test status
Simulation time 30954685 ps
CPU time 0.62 seconds
Started Dec 24 01:23:50 PM PST 23
Finished Dec 24 01:23:52 PM PST 23
Peak memory 201800 kb
Host smart-06f5870c-f602-4241-90ec-ef212dbd738f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946053274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.3946053274
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.2298745495
Short name T468
Test name
Test status
Simulation time 64157041998 ps
CPU time 1025.29 seconds
Started Dec 24 01:23:37 PM PST 23
Finished Dec 24 01:40:43 PM PST 23
Peak memory 202164 kb
Host smart-0b7f6e2b-7556-42df-86a3-dba832f2607a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298745495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.2298745495
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.636455457
Short name T47
Test name
Test status
Simulation time 36649793725 ps
CPU time 1101.6 seconds
Started Dec 24 01:23:50 PM PST 23
Finished Dec 24 01:42:13 PM PST 23
Peak memory 378016 kb
Host smart-052466f9-0c85-499c-a6de-c1f4e196af9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636455457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executabl
e.636455457
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.823512892
Short name T411
Test name
Test status
Simulation time 3430958975 ps
CPU time 117.37 seconds
Started Dec 24 01:23:49 PM PST 23
Finished Dec 24 01:25:48 PM PST 23
Peak memory 352456 kb
Host smart-5fc33ee8-d478-4f1a-a8ad-6186b3c231d4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823512892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.sram_ctrl_max_throughput.823512892
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.4277404291
Short name T549
Test name
Test status
Simulation time 6266150441 ps
CPU time 138.32 seconds
Started Dec 24 01:23:41 PM PST 23
Finished Dec 24 01:26:01 PM PST 23
Peak memory 211164 kb
Host smart-e6d3376f-ba33-4ed5-a4af-a60f1a95167e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277404291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.4277404291
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.1411636797
Short name T655
Test name
Test status
Simulation time 86094697900 ps
CPU time 304.21 seconds
Started Dec 24 01:23:49 PM PST 23
Finished Dec 24 01:28:54 PM PST 23
Peak memory 202132 kb
Host smart-1f03fc9f-2cfd-44b3-a249-4e73f03db299
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411636797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.1411636797
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.810720988
Short name T841
Test name
Test status
Simulation time 89627020202 ps
CPU time 1095.91 seconds
Started Dec 24 01:23:50 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 372972 kb
Host smart-745a204d-1287-4efe-8e8a-60e86fad55d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810720988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multip
le_keys.810720988
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.1166211327
Short name T745
Test name
Test status
Simulation time 812984713 ps
CPU time 15.18 seconds
Started Dec 24 01:23:50 PM PST 23
Finished Dec 24 01:24:07 PM PST 23
Peak memory 213540 kb
Host smart-26b86236-ec14-4d8c-8f9f-534b3fb9fa64
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166211327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.1166211327
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.57180984
Short name T392
Test name
Test status
Simulation time 8925731681 ps
CPU time 394.59 seconds
Started Dec 24 01:23:38 PM PST 23
Finished Dec 24 01:30:14 PM PST 23
Peak memory 202180 kb
Host smart-37601a60-2e43-40bc-abf4-415eebfcbd66
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57180984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_partial_access_b2b.57180984
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.2366818602
Short name T271
Test name
Test status
Simulation time 710700836 ps
CPU time 5.58 seconds
Started Dec 24 01:23:46 PM PST 23
Finished Dec 24 01:23:53 PM PST 23
Peak memory 202452 kb
Host smart-d022c822-c129-47b0-8488-955fdc3f0807
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366818602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2366818602
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.2592161604
Short name T289
Test name
Test status
Simulation time 5394659151 ps
CPU time 488.11 seconds
Started Dec 24 01:23:46 PM PST 23
Finished Dec 24 01:31:55 PM PST 23
Peak memory 380100 kb
Host smart-1d98d6e0-bb00-49a0-9500-68c40269ff2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592161604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2592161604
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.2440467962
Short name T940
Test name
Test status
Simulation time 755717149 ps
CPU time 6.77 seconds
Started Dec 24 01:23:35 PM PST 23
Finished Dec 24 01:23:43 PM PST 23
Peak memory 202100 kb
Host smart-71bd5a92-2d81-4f2f-a1e4-9966bf643b15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440467962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2440467962
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3942688474
Short name T649
Test name
Test status
Simulation time 1156414059 ps
CPU time 4080.92 seconds
Started Dec 24 01:23:50 PM PST 23
Finished Dec 24 02:31:53 PM PST 23
Peak memory 676016 kb
Host smart-8ded08a1-f6db-4215-9b45-6ad0a8ffa652
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3942688474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3942688474
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3152768369
Short name T342
Test name
Test status
Simulation time 8531409274 ps
CPU time 316.95 seconds
Started Dec 24 01:23:34 PM PST 23
Finished Dec 24 01:28:53 PM PST 23
Peak memory 202184 kb
Host smart-278986b6-bc5a-42a2-a22e-15ed1a3e5704
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152768369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.3152768369
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1086940938
Short name T799
Test name
Test status
Simulation time 3014511591 ps
CPU time 55.31 seconds
Started Dec 24 01:23:46 PM PST 23
Finished Dec 24 01:24:42 PM PST 23
Peak memory 284080 kb
Host smart-28b1f801-3492-48be-a97e-2f543a93c6c2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086940938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1086940938
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1061636045
Short name T701
Test name
Test status
Simulation time 12528316091 ps
CPU time 1916.06 seconds
Started Dec 24 01:21:59 PM PST 23
Finished Dec 24 01:53:56 PM PST 23
Peak memory 380308 kb
Host smart-1c1f61cd-e99c-4933-9fcb-48c07b0a4f8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061636045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.1061636045
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.610561664
Short name T966
Test name
Test status
Simulation time 40543277 ps
CPU time 0.64 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:22:05 PM PST 23
Peak memory 201812 kb
Host smart-e19d4f96-59e9-4ac1-83e1-4e1120ada365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610561664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.610561664
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.1151482558
Short name T535
Test name
Test status
Simulation time 192360899536 ps
CPU time 1060.47 seconds
Started Dec 24 01:21:58 PM PST 23
Finished Dec 24 01:39:40 PM PST 23
Peak memory 202056 kb
Host smart-a131f8be-93a0-423a-a4c2-7023aa419d67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151482558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
1151482558
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.2134854098
Short name T406
Test name
Test status
Simulation time 26382856239 ps
CPU time 163.36 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:24:48 PM PST 23
Peak memory 214212 kb
Host smart-17516869-a12b-47ac-aaf4-2d228b6c5430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134854098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.2134854098
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.879332505
Short name T505
Test name
Test status
Simulation time 2225707030 ps
CPU time 32.96 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:22:40 PM PST 23
Peak memory 238268 kb
Host smart-d9ac9805-1d5c-4d2d-aeeb-da43b90585c5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879332505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.sram_ctrl_max_throughput.879332505
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.120548311
Short name T474
Test name
Test status
Simulation time 4118996893 ps
CPU time 76.96 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:23:22 PM PST 23
Peak memory 211140 kb
Host smart-24587118-3943-4977-81de-ac2533fc4bb7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120548311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
sram_ctrl_mem_partial_access.120548311
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.597073436
Short name T757
Test name
Test status
Simulation time 14368348429 ps
CPU time 144.82 seconds
Started Dec 24 01:21:58 PM PST 23
Finished Dec 24 01:24:24 PM PST 23
Peak memory 202168 kb
Host smart-e7bf230e-543f-47e9-9266-f4e46e14221d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597073436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_
mem_walk.597073436
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.338791401
Short name T247
Test name
Test status
Simulation time 13319743654 ps
CPU time 659.89 seconds
Started Dec 24 01:22:01 PM PST 23
Finished Dec 24 01:33:02 PM PST 23
Peak memory 376976 kb
Host smart-d872e64d-d990-4880-bc4b-820818337d94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338791401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multipl
e_keys.338791401
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.3709497191
Short name T231
Test name
Test status
Simulation time 2636428649 ps
CPU time 13.31 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:22:17 PM PST 23
Peak memory 202136 kb
Host smart-a7b7d606-2823-4c13-a4b9-60921a2b9e9a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709497191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.3709497191
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3959629100
Short name T471
Test name
Test status
Simulation time 57751254846 ps
CPU time 359.89 seconds
Started Dec 24 01:22:00 PM PST 23
Finished Dec 24 01:28:01 PM PST 23
Peak memory 202084 kb
Host smart-dec40975-721b-43d0-8a99-bf21d1540795
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959629100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.3959629100
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.4258711729
Short name T952
Test name
Test status
Simulation time 366162133 ps
CPU time 12.56 seconds
Started Dec 24 01:21:58 PM PST 23
Finished Dec 24 01:22:12 PM PST 23
Peak memory 202400 kb
Host smart-9af75558-1b3c-47a7-a186-5610b82774a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258711729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.4258711729
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.1116183546
Short name T676
Test name
Test status
Simulation time 72347115722 ps
CPU time 748 seconds
Started Dec 24 01:22:01 PM PST 23
Finished Dec 24 01:34:30 PM PST 23
Peak memory 374976 kb
Host smart-986cd1e7-7cfd-4804-9078-14856495379b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116183546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1116183546
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.1260371639
Short name T37
Test name
Test status
Simulation time 254879705 ps
CPU time 3.49 seconds
Started Dec 24 01:21:58 PM PST 23
Finished Dec 24 01:22:03 PM PST 23
Peak memory 220992 kb
Host smart-e39c818e-7f6f-41ac-b97c-6df038bb7164
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260371639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.1260371639
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.1661039551
Short name T359
Test name
Test status
Simulation time 2064681465 ps
CPU time 18.76 seconds
Started Dec 24 01:21:58 PM PST 23
Finished Dec 24 01:22:17 PM PST 23
Peak memory 202056 kb
Host smart-77f90d50-c82d-4707-bb79-3cbc100d7f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661039551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1661039551
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.569132504
Short name T447
Test name
Test status
Simulation time 61633768804 ps
CPU time 3813.02 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 02:25:39 PM PST 23
Peak memory 380880 kb
Host smart-a451cfd5-fe4f-4f43-a392-749ecc5bcb9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569132504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_stress_all.569132504
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.515394910
Short name T548
Test name
Test status
Simulation time 603263771 ps
CPU time 1863.57 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:53:10 PM PST 23
Peak memory 607192 kb
Host smart-05176cd6-d5ff-4f5e-8549-93280fdc72f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=515394910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.515394910
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1294546087
Short name T715
Test name
Test status
Simulation time 4176208615 ps
CPU time 354.68 seconds
Started Dec 24 01:21:59 PM PST 23
Finished Dec 24 01:27:55 PM PST 23
Peak memory 202196 kb
Host smart-34abe1e7-f570-4478-a0a1-535bd87d4049
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294546087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.1294546087
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2269435862
Short name T797
Test name
Test status
Simulation time 2799677194 ps
CPU time 37.04 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:22:45 PM PST 23
Peak memory 251316 kb
Host smart-5b05d4cd-4220-453c-82b5-c0df57553b7c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269435862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.2269435862
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.4252784346
Short name T889
Test name
Test status
Simulation time 8370349829 ps
CPU time 646.76 seconds
Started Dec 24 01:23:46 PM PST 23
Finished Dec 24 01:34:33 PM PST 23
Peak memory 369916 kb
Host smart-925143fe-9a8d-4a26-9e33-44f83a2eb148
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252784346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.4252784346
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.1814025228
Short name T900
Test name
Test status
Simulation time 23782687 ps
CPU time 0.64 seconds
Started Dec 24 01:24:26 PM PST 23
Finished Dec 24 01:24:27 PM PST 23
Peak memory 201432 kb
Host smart-30a229a3-d70c-49fe-9b65-b7f2ab457289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814025228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.1814025228
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.1847273128
Short name T404
Test name
Test status
Simulation time 165892829715 ps
CPU time 2667.06 seconds
Started Dec 24 01:23:33 PM PST 23
Finished Dec 24 02:08:02 PM PST 23
Peak memory 202144 kb
Host smart-2d8ba524-8eee-41d0-98fe-4b5a3f259b88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847273128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.1847273128
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.4167148894
Short name T42
Test name
Test status
Simulation time 16530752019 ps
CPU time 791.35 seconds
Started Dec 24 01:24:31 PM PST 23
Finished Dec 24 01:37:43 PM PST 23
Peak memory 376952 kb
Host smart-fbde7015-6f07-4d91-8848-9897e4d7442a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167148894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.4167148894
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.3660158893
Short name T868
Test name
Test status
Simulation time 37007362034 ps
CPU time 91.54 seconds
Started Dec 24 01:23:40 PM PST 23
Finished Dec 24 01:25:13 PM PST 23
Peak memory 210256 kb
Host smart-dd14aea8-7427-4f26-af34-5951d9c4d29f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660158893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.3660158893
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.353917004
Short name T746
Test name
Test status
Simulation time 724253230 ps
CPU time 36.66 seconds
Started Dec 24 01:23:39 PM PST 23
Finished Dec 24 01:24:17 PM PST 23
Peak memory 250960 kb
Host smart-5d611d80-fc85-4b07-bd39-c7fd1176a27e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353917004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.sram_ctrl_max_throughput.353917004
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2555339494
Short name T263
Test name
Test status
Simulation time 1586108930 ps
CPU time 136.55 seconds
Started Dec 24 01:24:29 PM PST 23
Finished Dec 24 01:26:46 PM PST 23
Peak memory 210544 kb
Host smart-0d71fb84-e8b5-4609-b283-b3396a6a2a52
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555339494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.2555339494
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.245920614
Short name T867
Test name
Test status
Simulation time 8591576153 ps
CPU time 123.22 seconds
Started Dec 24 01:24:25 PM PST 23
Finished Dec 24 01:26:29 PM PST 23
Peak memory 202116 kb
Host smart-8e416e6b-18df-40c3-a1fe-ed788dc0c7eb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245920614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl
_mem_walk.245920614
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.2532823070
Short name T379
Test name
Test status
Simulation time 3951389921 ps
CPU time 71.93 seconds
Started Dec 24 01:23:39 PM PST 23
Finished Dec 24 01:24:53 PM PST 23
Peak memory 255064 kb
Host smart-fa1bbda6-29d0-4ac1-b644-b8b4f5e3ef38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532823070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.2532823070
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.4225813496
Short name T872
Test name
Test status
Simulation time 5088271884 ps
CPU time 26.44 seconds
Started Dec 24 01:23:41 PM PST 23
Finished Dec 24 01:24:08 PM PST 23
Peak memory 202028 kb
Host smart-55bc73d6-b497-4017-b140-07acc8743834
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225813496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.4225813496
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2604879234
Short name T573
Test name
Test status
Simulation time 37411239890 ps
CPU time 584.65 seconds
Started Dec 24 01:23:42 PM PST 23
Finished Dec 24 01:33:28 PM PST 23
Peak memory 202132 kb
Host smart-3e55aed0-0287-4a9f-9c67-1a165d3ae81b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604879234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.2604879234
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.1805042507
Short name T945
Test name
Test status
Simulation time 381568186 ps
CPU time 5.43 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:24:39 PM PST 23
Peak memory 202412 kb
Host smart-61fff87f-44b4-4299-8513-f313d8ab4f79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805042507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1805042507
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.3337731766
Short name T732
Test name
Test status
Simulation time 8770100083 ps
CPU time 576.77 seconds
Started Dec 24 01:24:26 PM PST 23
Finished Dec 24 01:34:04 PM PST 23
Peak memory 362660 kb
Host smart-5c315467-3a7b-4962-8568-d0db09cd723a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337731766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3337731766
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.264599903
Short name T15
Test name
Test status
Simulation time 1243160175 ps
CPU time 111.39 seconds
Started Dec 24 01:23:41 PM PST 23
Finished Dec 24 01:25:34 PM PST 23
Peak memory 349300 kb
Host smart-c55908b1-04e4-4b02-97e9-325f0f092683
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264599903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.264599903
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4595110
Short name T303
Test name
Test status
Simulation time 6781719652 ps
CPU time 5900.47 seconds
Started Dec 24 01:24:27 PM PST 23
Finished Dec 24 03:02:49 PM PST 23
Peak memory 447972 kb
Host smart-b24fe565-c126-47a7-895e-4d5007cbf5ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4595110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.4595110
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3612142996
Short name T355
Test name
Test status
Simulation time 72803679846 ps
CPU time 345.46 seconds
Started Dec 24 01:23:40 PM PST 23
Finished Dec 24 01:29:27 PM PST 23
Peak memory 202008 kb
Host smart-18bda87c-e340-474c-a673-e6b80aac5a23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612142996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.3612142996
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.794759960
Short name T631
Test name
Test status
Simulation time 1886279302 ps
CPU time 37.48 seconds
Started Dec 24 01:23:49 PM PST 23
Finished Dec 24 01:24:28 PM PST 23
Peak memory 251192 kb
Host smart-7e499110-b38c-4aaf-a75f-fe72efeb4e0a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794759960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.794759960
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1795925220
Short name T530
Test name
Test status
Simulation time 13937952315 ps
CPU time 2290.48 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 02:02:48 PM PST 23
Peak memory 380220 kb
Host smart-6ebdc9cc-3420-4162-b956-40b9ba06a3f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795925220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.1795925220
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.962399270
Short name T979
Test name
Test status
Simulation time 39431635 ps
CPU time 0.62 seconds
Started Dec 24 01:24:31 PM PST 23
Finished Dec 24 01:24:33 PM PST 23
Peak memory 201832 kb
Host smart-e176cbc8-1815-46d7-bb5f-b02840249fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962399270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.962399270
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.2883403759
Short name T531
Test name
Test status
Simulation time 24940397240 ps
CPU time 1771.48 seconds
Started Dec 24 01:24:30 PM PST 23
Finished Dec 24 01:54:03 PM PST 23
Peak memory 202144 kb
Host smart-e2e04c3e-cefe-4b6b-8989-8481ed4e74cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883403759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.2883403759
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.1681740336
Short name T568
Test name
Test status
Simulation time 61113743579 ps
CPU time 162.76 seconds
Started Dec 24 01:24:27 PM PST 23
Finished Dec 24 01:27:10 PM PST 23
Peak memory 213808 kb
Host smart-600e1345-41e8-47f4-b19c-9ebd251bcae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681740336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.1681740336
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.935908575
Short name T633
Test name
Test status
Simulation time 2999118866 ps
CPU time 34.47 seconds
Started Dec 24 01:24:14 PM PST 23
Finished Dec 24 01:24:49 PM PST 23
Peak memory 236164 kb
Host smart-ac2ed36d-20ec-465f-9998-f7e525574058
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935908575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.sram_ctrl_max_throughput.935908575
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2366082317
Short name T300
Test name
Test status
Simulation time 8740230082 ps
CPU time 149.75 seconds
Started Dec 24 01:24:29 PM PST 23
Finished Dec 24 01:26:59 PM PST 23
Peak memory 214336 kb
Host smart-6c1796a0-e913-4d5e-85e1-f581c28997e8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366082317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.2366082317
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.2390166747
Short name T740
Test name
Test status
Simulation time 10322016798 ps
CPU time 154.49 seconds
Started Dec 24 01:24:26 PM PST 23
Finished Dec 24 01:27:01 PM PST 23
Peak memory 202220 kb
Host smart-6f72dde1-db97-4ee0-8b34-e0d9cffb251e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390166747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.2390166747
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.2921481921
Short name T948
Test name
Test status
Simulation time 6522382422 ps
CPU time 968.82 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 380076 kb
Host smart-026d372e-2ab5-4b21-bfb6-f98117802a42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921481921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.2921481921
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.3259398875
Short name T377
Test name
Test status
Simulation time 3784028647 ps
CPU time 35.44 seconds
Started Dec 24 01:24:26 PM PST 23
Finished Dec 24 01:25:03 PM PST 23
Peak memory 202148 kb
Host smart-c04498e3-45dc-4da0-9c2f-3acd0c8363ac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259398875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.3259398875
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2392817677
Short name T371
Test name
Test status
Simulation time 20138345192 ps
CPU time 327.27 seconds
Started Dec 24 01:24:31 PM PST 23
Finished Dec 24 01:29:59 PM PST 23
Peak memory 202032 kb
Host smart-0a35e80f-b001-4ee9-82f1-92464468e445
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392817677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.2392817677
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.2041763760
Short name T390
Test name
Test status
Simulation time 4182998162 ps
CPU time 6.25 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:24:41 PM PST 23
Peak memory 202472 kb
Host smart-083a9c73-1393-4a6c-8efe-e9f1934ddb3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041763760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2041763760
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.1787206329
Short name T246
Test name
Test status
Simulation time 3864887182 ps
CPU time 406.47 seconds
Started Dec 24 01:24:27 PM PST 23
Finished Dec 24 01:31:15 PM PST 23
Peak memory 357608 kb
Host smart-d87a4579-50e7-4267-9d11-03a1749f4eea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787206329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1787206329
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.61518712
Short name T837
Test name
Test status
Simulation time 6472254828 ps
CPU time 29.16 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:25:03 PM PST 23
Peak memory 202184 kb
Host smart-632ab0a5-37ac-4570-bd18-f3a48c9d82ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61518712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.61518712
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.757863420
Short name T912
Test name
Test status
Simulation time 118083803 ps
CPU time 1852.71 seconds
Started Dec 24 01:24:30 PM PST 23
Finished Dec 24 01:55:23 PM PST 23
Peak memory 420376 kb
Host smart-bd8049d1-ff89-4c15-a7b6-8627e184d510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=757863420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.757863420
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3999670906
Short name T870
Test name
Test status
Simulation time 52703310360 ps
CPU time 384.45 seconds
Started Dec 24 01:24:31 PM PST 23
Finished Dec 24 01:30:56 PM PST 23
Peak memory 202192 kb
Host smart-4edab7a5-afd0-4226-9146-5acd593dbd46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999670906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.3999670906
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.358078400
Short name T288
Test name
Test status
Simulation time 1597604456 ps
CPU time 36.87 seconds
Started Dec 24 01:24:12 PM PST 23
Finished Dec 24 01:24:50 PM PST 23
Peak memory 253272 kb
Host smart-3fd420a1-7fa8-4221-b0cb-e8de7e207803
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358078400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.358078400
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.251908565
Short name T402
Test name
Test status
Simulation time 7981061899 ps
CPU time 1186.56 seconds
Started Dec 24 01:24:27 PM PST 23
Finished Dec 24 01:44:15 PM PST 23
Peak memory 380156 kb
Host smart-6b94c00a-1182-4516-8b7f-9c7aa05c1603
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251908565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 22.sram_ctrl_access_during_key_req.251908565
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.1084865193
Short name T659
Test name
Test status
Simulation time 22086187 ps
CPU time 0.65 seconds
Started Dec 24 01:24:31 PM PST 23
Finished Dec 24 01:24:32 PM PST 23
Peak memory 201900 kb
Host smart-819deead-f16e-42ab-b7e2-7798c7131103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084865193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.1084865193
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.1126745104
Short name T605
Test name
Test status
Simulation time 62520309661 ps
CPU time 1149.55 seconds
Started Dec 24 01:24:27 PM PST 23
Finished Dec 24 01:43:37 PM PST 23
Peak memory 202144 kb
Host smart-dfc1a8ed-4ba2-4f77-ab45-4f9da2d35644
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126745104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.1126745104
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.3183202648
Short name T871
Test name
Test status
Simulation time 9838747775 ps
CPU time 105.48 seconds
Started Dec 24 01:24:27 PM PST 23
Finished Dec 24 01:26:14 PM PST 23
Peak memory 213808 kb
Host smart-e45b1335-03db-46e0-b43c-e431c4c26ce4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183202648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.3183202648
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.1538909599
Short name T473
Test name
Test status
Simulation time 2825850792 ps
CPU time 149.62 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:27:05 PM PST 23
Peak memory 365792 kb
Host smart-4dae3537-b4a8-4804-a1c3-6eb0b302c9e7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538909599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.1538909599
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2371516492
Short name T277
Test name
Test status
Simulation time 18109360766 ps
CPU time 155.39 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:27:08 PM PST 23
Peak memory 211088 kb
Host smart-c736e759-995c-4c74-b568-eea58ddaa6a0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371516492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.2371516492
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.956873570
Short name T961
Test name
Test status
Simulation time 9335099023 ps
CPU time 151.47 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:27:10 PM PST 23
Peak memory 202208 kb
Host smart-7356453c-74e6-41f5-a15a-d7afe1cb3898
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956873570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl
_mem_walk.956873570
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.2843877299
Short name T502
Test name
Test status
Simulation time 1890212946 ps
CPU time 339.62 seconds
Started Dec 24 01:24:30 PM PST 23
Finished Dec 24 01:30:11 PM PST 23
Peak memory 375884 kb
Host smart-c7dc1067-7102-4693-84b9-95aab1e441e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843877299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.2843877299
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.1493931386
Short name T142
Test name
Test status
Simulation time 2374641677 ps
CPU time 100.44 seconds
Started Dec 24 01:24:28 PM PST 23
Finished Dec 24 01:26:09 PM PST 23
Peak memory 345488 kb
Host smart-0b69f534-cb77-41a1-bccd-260164b5e2e7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493931386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.1493931386
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.4251727966
Short name T477
Test name
Test status
Simulation time 39875612001 ps
CPU time 430.36 seconds
Started Dec 24 01:24:27 PM PST 23
Finished Dec 24 01:31:38 PM PST 23
Peak memory 202136 kb
Host smart-d943a0e2-fb8b-42f8-a8e7-3e5fd4b3debd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251727966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.4251727966
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.2804716680
Short name T313
Test name
Test status
Simulation time 419550972 ps
CPU time 5.79 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:24:40 PM PST 23
Peak memory 202248 kb
Host smart-d0e72156-0bb4-4d29-ac4b-13c4262bf173
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804716680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2804716680
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.127264704
Short name T587
Test name
Test status
Simulation time 24693096320 ps
CPU time 829.51 seconds
Started Dec 24 01:24:27 PM PST 23
Finished Dec 24 01:38:18 PM PST 23
Peak memory 375928 kb
Host smart-638b5986-c7d1-4f6d-a981-28c1833c7d9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127264704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.127264704
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.3031983413
Short name T439
Test name
Test status
Simulation time 1534070198 ps
CPU time 15.26 seconds
Started Dec 24 01:24:25 PM PST 23
Finished Dec 24 01:24:41 PM PST 23
Peak memory 202044 kb
Host smart-3f614ef4-f46b-478a-bdbd-ac98170df297
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031983413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3031983413
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.1690390180
Short name T926
Test name
Test status
Simulation time 72900758147 ps
CPU time 4808.7 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 02:44:43 PM PST 23
Peak memory 380892 kb
Host smart-1e4fdf03-26a6-404b-a861-83c05f89819b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690390180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.1690390180
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.290691591
Short name T621
Test name
Test status
Simulation time 589283621 ps
CPU time 2629.43 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 02:08:27 PM PST 23
Peak memory 654748 kb
Host smart-c6bdd0a8-3041-4356-b481-924419f61790
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=290691591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.290691591
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.3373964077
Short name T107
Test name
Test status
Simulation time 2031597852 ps
CPU time 153.87 seconds
Started Dec 24 01:24:13 PM PST 23
Finished Dec 24 01:26:48 PM PST 23
Peak memory 202096 kb
Host smart-455b2c19-7091-4269-93be-68a2afe814e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373964077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.3373964077
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1465195561
Short name T678
Test name
Test status
Simulation time 1396728469 ps
CPU time 36.89 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:25:10 PM PST 23
Peak memory 251172 kb
Host smart-d31c77c4-21a6-4396-9ac4-9e14981a2951
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465195561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.1465195561
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3150251302
Short name T20
Test name
Test status
Simulation time 33805938005 ps
CPU time 1339.94 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:46:57 PM PST 23
Peak memory 379028 kb
Host smart-d561b0d1-56d3-4fed-a551-91807330cd67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150251302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.3150251302
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.2754512671
Short name T8
Test name
Test status
Simulation time 12905186 ps
CPU time 0.63 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:24:35 PM PST 23
Peak memory 201784 kb
Host smart-96d9ca8e-ab1e-413a-bd5c-d12b39d68ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754512671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.2754512671
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.2832288299
Short name T642
Test name
Test status
Simulation time 249899117064 ps
CPU time 1378.05 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:47:35 PM PST 23
Peak memory 202268 kb
Host smart-927385f3-54ce-4bd7-b92d-203d32f47ffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832288299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.2832288299
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.1343103591
Short name T937
Test name
Test status
Simulation time 97968020947 ps
CPU time 1263.4 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:45:42 PM PST 23
Peak memory 376236 kb
Host smart-8d362786-9917-4699-93ee-daae21e2bef1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343103591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.1343103591
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.2093415926
Short name T488
Test name
Test status
Simulation time 7555970405 ps
CPU time 172.36 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:27:31 PM PST 23
Peak memory 214516 kb
Host smart-2d3730ad-02c2-4999-b0fc-6375466b7a30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093415926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.2093415926
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.888676996
Short name T492
Test name
Test status
Simulation time 2473755862 ps
CPU time 28.28 seconds
Started Dec 24 01:24:40 PM PST 23
Finished Dec 24 01:25:09 PM PST 23
Peak memory 210400 kb
Host smart-a535ab73-acc6-40ba-b1ed-be93f91981a1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888676996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.sram_ctrl_max_throughput.888676996
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3939479361
Short name T551
Test name
Test status
Simulation time 20783351688 ps
CPU time 149.98 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:27:08 PM PST 23
Peak memory 211260 kb
Host smart-0e5efca9-5d20-4985-b567-1b0244c5bee0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939479361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.3939479361
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.1844827466
Short name T557
Test name
Test status
Simulation time 21896911658 ps
CPU time 264.41 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:29:03 PM PST 23
Peak memory 202156 kb
Host smart-3a795db9-88e4-41af-bfe0-8cc14003c358
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844827466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.1844827466
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.1363583124
Short name T880
Test name
Test status
Simulation time 21541355304 ps
CPU time 431.34 seconds
Started Dec 24 01:24:31 PM PST 23
Finished Dec 24 01:31:44 PM PST 23
Peak memory 311672 kb
Host smart-d381a70f-7574-49c6-bb23-1dab33446bbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363583124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.1363583124
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.626282022
Short name T248
Test name
Test status
Simulation time 1735015077 ps
CPU time 16.57 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:24:54 PM PST 23
Peak memory 201992 kb
Host smart-e94c0e78-67d6-4880-88f2-28467c7bf6c5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626282022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s
ram_ctrl_partial_access.626282022
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.650647864
Short name T395
Test name
Test status
Simulation time 11004748241 ps
CPU time 271.3 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:29:09 PM PST 23
Peak memory 202168 kb
Host smart-aa1aebb2-0af8-410d-bae7-4775f7369342
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650647864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.sram_ctrl_partial_access_b2b.650647864
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2417356796
Short name T658
Test name
Test status
Simulation time 3804080774 ps
CPU time 13.62 seconds
Started Dec 24 01:24:37 PM PST 23
Finished Dec 24 01:24:52 PM PST 23
Peak memory 202520 kb
Host smart-92f7f9de-0fb2-4cb0-a266-5202e5981d3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417356796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2417356796
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.1408799943
Short name T617
Test name
Test status
Simulation time 18748340386 ps
CPU time 1601.87 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:51:20 PM PST 23
Peak memory 382188 kb
Host smart-873d2322-32c0-4c5c-8258-7543dd0acfc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408799943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1408799943
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.476619262
Short name T523
Test name
Test status
Simulation time 373358484 ps
CPU time 17.02 seconds
Started Dec 24 01:24:30 PM PST 23
Finished Dec 24 01:24:48 PM PST 23
Peak memory 220392 kb
Host smart-2e7c44d5-9842-4ffd-ab6c-61036daf51c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476619262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.476619262
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.416694914
Short name T685
Test name
Test status
Simulation time 12924551284 ps
CPU time 270.11 seconds
Started Dec 24 01:24:41 PM PST 23
Finished Dec 24 01:29:12 PM PST 23
Peak memory 202172 kb
Host smart-25f65821-fa64-4523-9e65-f22ef3e44b55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416694914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.sram_ctrl_stress_pipeline.416694914
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.693271862
Short name T409
Test name
Test status
Simulation time 1579670000 ps
CPU time 54.2 seconds
Started Dec 24 01:24:40 PM PST 23
Finished Dec 24 01:25:36 PM PST 23
Peak memory 278948 kb
Host smart-15673dd3-694a-4a9d-bcae-b40e76102735
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693271862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.693271862
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1678003377
Short name T482
Test name
Test status
Simulation time 12972849106 ps
CPU time 1338.05 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:46:54 PM PST 23
Peak memory 376968 kb
Host smart-ca100d3b-19e3-4052-a509-e08fa774ba4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678003377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.1678003377
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.508385067
Short name T703
Test name
Test status
Simulation time 38954268 ps
CPU time 0.64 seconds
Started Dec 24 01:24:30 PM PST 23
Finished Dec 24 01:24:32 PM PST 23
Peak memory 201780 kb
Host smart-e8f3e6a5-4144-42b6-a43d-fe1dfd46927a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508385067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.508385067
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.3534452529
Short name T817
Test name
Test status
Simulation time 13272747491 ps
CPU time 479.33 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:32:32 PM PST 23
Peak memory 202136 kb
Host smart-b415b0a7-021f-4ef5-8c19-81b0f2a2e85b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534452529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.3534452529
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.259387939
Short name T511
Test name
Test status
Simulation time 12872392158 ps
CPU time 615.72 seconds
Started Dec 24 01:24:40 PM PST 23
Finished Dec 24 01:34:57 PM PST 23
Peak memory 369820 kb
Host smart-734e19bb-1462-4940-971d-940c0635c3bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259387939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executabl
e.259387939
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.1490771502
Short name T561
Test name
Test status
Simulation time 2226568648 ps
CPU time 39.58 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:25:13 PM PST 23
Peak memory 210328 kb
Host smart-355a8620-1bf7-463a-8af5-75236f8c43ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490771502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.1490771502
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.3547596678
Short name T10
Test name
Test status
Simulation time 2554004402 ps
CPU time 191.89 seconds
Started Dec 24 01:24:30 PM PST 23
Finished Dec 24 01:27:43 PM PST 23
Peak memory 365684 kb
Host smart-d0cb6c11-66df-4b5b-bdeb-bdbbc338f689
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547596678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.3547596678
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3767025006
Short name T754
Test name
Test status
Simulation time 9379611254 ps
CPU time 80.46 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:25:55 PM PST 23
Peak memory 212152 kb
Host smart-139b287b-f175-4f2c-921d-404df9550209
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767025006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.3767025006
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.4013497051
Short name T236
Test name
Test status
Simulation time 20625065807 ps
CPU time 152.57 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:27:06 PM PST 23
Peak memory 202120 kb
Host smart-f5991acc-c7f0-4ca5-bc27-35a9cd7dff76
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013497051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.4013497051
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.2423209717
Short name T430
Test name
Test status
Simulation time 5012251948 ps
CPU time 395.07 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:31:08 PM PST 23
Peak memory 371916 kb
Host smart-1ad4bd88-cce3-4609-87fa-8c63655fe48e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423209717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.2423209717
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.1883684805
Short name T604
Test name
Test status
Simulation time 2433952287 ps
CPU time 23.76 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:25:00 PM PST 23
Peak memory 202060 kb
Host smart-16103a0e-601d-473f-8127-64dcae6ee022
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883684805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.1883684805
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2266634154
Short name T249
Test name
Test status
Simulation time 8148097473 ps
CPU time 498.01 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:32:54 PM PST 23
Peak memory 202152 kb
Host smart-c0549f9c-79bc-4580-898d-f3e66ebb9578
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266634154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.2266634154
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.2459376543
Short name T856
Test name
Test status
Simulation time 1357031305 ps
CPU time 6.77 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:24:41 PM PST 23
Peak memory 202416 kb
Host smart-f56ed223-5a3e-46ab-8bee-f9cf8e0c60dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459376543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2459376543
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.538371483
Short name T347
Test name
Test status
Simulation time 6088571733 ps
CPU time 890.86 seconds
Started Dec 24 01:24:48 PM PST 23
Finished Dec 24 01:39:40 PM PST 23
Peak memory 378116 kb
Host smart-a1d6f26d-58ee-438b-b365-f02109bdb7ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538371483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.538371483
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.792285261
Short name T603
Test name
Test status
Simulation time 1566166935 ps
CPU time 132.76 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:26:49 PM PST 23
Peak memory 354328 kb
Host smart-ca36c6d7-41b9-4850-9ca3-2431ba892b9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792285261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.792285261
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2656324116
Short name T230
Test name
Test status
Simulation time 851578343 ps
CPU time 2891.59 seconds
Started Dec 24 01:24:31 PM PST 23
Finished Dec 24 02:12:44 PM PST 23
Peak memory 676300 kb
Host smart-dbd2266c-efa8-4255-8fde-84e9452d7355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2656324116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2656324116
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1834848865
Short name T951
Test name
Test status
Simulation time 14768980095 ps
CPU time 318.92 seconds
Started Dec 24 01:24:30 PM PST 23
Finished Dec 24 01:29:50 PM PST 23
Peak memory 202176 kb
Host smart-bf5d37c7-75d5-46a3-866b-45a5b2dcbe18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834848865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.1834848865
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1467396622
Short name T380
Test name
Test status
Simulation time 3259658276 ps
CPU time 176.87 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:27:32 PM PST 23
Peak memory 366788 kb
Host smart-ed286352-38f7-4810-a45e-68423297be75
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467396622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1467396622
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.731903329
Short name T465
Test name
Test status
Simulation time 9412617444 ps
CPU time 1246.97 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:45:26 PM PST 23
Peak memory 380048 kb
Host smart-83f3a2c8-d70d-45b4-98ef-9a056f99faef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731903329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.sram_ctrl_access_during_key_req.731903329
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.805551925
Short name T244
Test name
Test status
Simulation time 25819208 ps
CPU time 0.66 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:24:36 PM PST 23
Peak memory 201756 kb
Host smart-72351a89-40d3-407d-a639-2275146e7799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805551925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.805551925
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.1959329532
Short name T144
Test name
Test status
Simulation time 115052134579 ps
CPU time 2553.08 seconds
Started Dec 24 01:24:31 PM PST 23
Finished Dec 24 02:07:06 PM PST 23
Peak memory 202124 kb
Host smart-1abcce7c-53b9-44f6-a03f-ebbf0b51f1bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959329532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.1959329532
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.3152927800
Short name T778
Test name
Test status
Simulation time 44953789966 ps
CPU time 110.47 seconds
Started Dec 24 01:24:31 PM PST 23
Finished Dec 24 01:26:23 PM PST 23
Peak memory 210384 kb
Host smart-b188261a-3975-44c8-a103-d7bdcee9f0c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152927800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.3152927800
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.1218357228
Short name T670
Test name
Test status
Simulation time 724143024 ps
CPU time 35.21 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:25:09 PM PST 23
Peak memory 251104 kb
Host smart-c0388e28-f682-4f4b-9291-d8800fe0ca2b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218357228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.1218357228
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2728627499
Short name T532
Test name
Test status
Simulation time 2454812966 ps
CPU time 80.12 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:25:58 PM PST 23
Peak memory 211132 kb
Host smart-cf986b77-0663-4f92-8e76-aa71ec98cfb2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728627499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.2728627499
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.455327724
Short name T814
Test name
Test status
Simulation time 229324529574 ps
CPU time 379.79 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:30:57 PM PST 23
Peak memory 202232 kb
Host smart-d01732af-a6cf-40a6-97e3-8c5fccfea847
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455327724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl
_mem_walk.455327724
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.1754673806
Short name T517
Test name
Test status
Simulation time 16165058466 ps
CPU time 650.17 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:35:24 PM PST 23
Peak memory 368784 kb
Host smart-43a2bdb5-af45-4bc6-b8fd-8b1de8568da1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754673806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.1754673806
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.2683298549
Short name T138
Test name
Test status
Simulation time 2070227887 ps
CPU time 8.38 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:24:44 PM PST 23
Peak memory 210272 kb
Host smart-753e6bb1-f73f-4957-9282-da9c634efe1e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683298549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.2683298549
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2591099050
Short name T928
Test name
Test status
Simulation time 81189033126 ps
CPU time 530.01 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:33:25 PM PST 23
Peak memory 202172 kb
Host smart-68124e1d-9df7-4903-b052-55b8e3103fbf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591099050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.2591099050
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.4052435239
Short name T906
Test name
Test status
Simulation time 1303429913 ps
CPU time 13.23 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:24:48 PM PST 23
Peak memory 202344 kb
Host smart-c6c42ca6-b3be-4118-8d58-4b07e93a403f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052435239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.4052435239
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.381842332
Short name T521
Test name
Test status
Simulation time 2254419867 ps
CPU time 108.39 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:26:22 PM PST 23
Peak memory 348328 kb
Host smart-88a82d53-8e0c-478a-b40a-99323ac88a61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381842332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.381842332
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.357714308
Short name T31
Test name
Test status
Simulation time 546348113471 ps
CPU time 4109.91 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 02:33:04 PM PST 23
Peak memory 380128 kb
Host smart-208aa8c5-6d78-4ed4-8c92-1708e844d3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357714308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_stress_all.357714308
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4079315386
Short name T648
Test name
Test status
Simulation time 598242563 ps
CPU time 2286.46 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 02:02:45 PM PST 23
Peak memory 417748 kb
Host smart-f9d612ed-b13c-483a-a446-97a01a2f4141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4079315386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.4079315386
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1677972851
Short name T908
Test name
Test status
Simulation time 3651964271 ps
CPU time 273.35 seconds
Started Dec 24 01:24:30 PM PST 23
Finished Dec 24 01:29:04 PM PST 23
Peak memory 202108 kb
Host smart-d523265b-b35e-4057-b611-e90ec5c54ecf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677972851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.1677972851
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1969247324
Short name T429
Test name
Test status
Simulation time 714468045 ps
CPU time 29.76 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:25:05 PM PST 23
Peak memory 222300 kb
Host smart-73376fd8-3f16-44d4-8207-6551106bd4d7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969247324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1969247324
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.2372750007
Short name T234
Test name
Test status
Simulation time 3332130021 ps
CPU time 615.9 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:34:54 PM PST 23
Peak memory 380040 kb
Host smart-9fd69488-8f35-43a6-969c-75b5cc75294c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372750007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.2372750007
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.2148775783
Short name T366
Test name
Test status
Simulation time 39297080 ps
CPU time 0.63 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:24:38 PM PST 23
Peak memory 201848 kb
Host smart-e58147af-97e4-4a7e-92c3-d84bc28061b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148775783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.2148775783
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.2873004781
Short name T232
Test name
Test status
Simulation time 132580881820 ps
CPU time 1387.88 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:47:45 PM PST 23
Peak memory 202084 kb
Host smart-f50feaa1-f284-4638-a823-bade2b744fcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873004781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.2873004781
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.1946144885
Short name T553
Test name
Test status
Simulation time 61594879356 ps
CPU time 894.44 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:39:29 PM PST 23
Peak memory 373112 kb
Host smart-743aa6c2-0ccf-4806-99c3-aa73ebbce5b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946144885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.1946144885
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.3068596461
Short name T30
Test name
Test status
Simulation time 5410373466 ps
CPU time 65.17 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:25:42 PM PST 23
Peak memory 210380 kb
Host smart-0e3c2935-6951-4f51-a27c-00dd1c796cd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068596461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.3068596461
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.3810185255
Short name T331
Test name
Test status
Simulation time 3941275873 ps
CPU time 165.42 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:27:19 PM PST 23
Peak memory 372980 kb
Host smart-87f804d8-6628-4b16-a0ed-5315884e46b8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810185255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.3810185255
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1310739631
Short name T87
Test name
Test status
Simulation time 1629521153 ps
CPU time 133.29 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:26:49 PM PST 23
Peak memory 211020 kb
Host smart-26255e99-4cf6-45c0-8d0e-8f22c19b2687
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310739631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.1310739631
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.4109013538
Short name T689
Test name
Test status
Simulation time 20668450004 ps
CPU time 304.94 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:29:43 PM PST 23
Peak memory 202100 kb
Host smart-aef916eb-24bc-447a-990b-7cab21353fe8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109013538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.4109013538
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.840170349
Short name T269
Test name
Test status
Simulation time 70142099869 ps
CPU time 925.44 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:40:02 PM PST 23
Peak memory 379100 kb
Host smart-2f05d4ee-2093-4e27-85a3-dfffc7cdac9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840170349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip
le_keys.840170349
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.3977349990
Short name T39
Test name
Test status
Simulation time 11718470169 ps
CPU time 35.13 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:25:09 PM PST 23
Peak memory 273008 kb
Host smart-c05fa29f-af98-4974-aee9-850e5b62c36f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977349990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.3977349990
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3428254784
Short name T976
Test name
Test status
Simulation time 6884548484 ps
CPU time 407.18 seconds
Started Dec 24 01:24:32 PM PST 23
Finished Dec 24 01:31:21 PM PST 23
Peak memory 202152 kb
Host smart-ac7d9647-0b37-4985-9d1b-aa13a58dea5b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428254784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.3428254784
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.2034509248
Short name T475
Test name
Test status
Simulation time 666013196 ps
CPU time 6.53 seconds
Started Dec 24 01:24:33 PM PST 23
Finished Dec 24 01:24:41 PM PST 23
Peak memory 202432 kb
Host smart-7a24a5df-51f8-480d-a253-d0028e3c8c24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034509248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2034509248
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.2543406432
Short name T11
Test name
Test status
Simulation time 1422360425 ps
CPU time 393.99 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:31:12 PM PST 23
Peak memory 371788 kb
Host smart-61dffaa7-bd53-446f-b139-829f614bd3fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543406432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2543406432
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.3820893936
Short name T636
Test name
Test status
Simulation time 2694285374 ps
CPU time 48.16 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:25:25 PM PST 23
Peak memory 299256 kb
Host smart-e0b9a5ab-e5bf-4f4e-af28-7d777d6b11ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820893936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3820893936
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.1111018714
Short name T842
Test name
Test status
Simulation time 22074357019 ps
CPU time 2001.33 seconds
Started Dec 24 01:24:37 PM PST 23
Finished Dec 24 01:58:00 PM PST 23
Peak memory 376944 kb
Host smart-3491fb94-d453-45aa-9eb7-5c3f7af17089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111018714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.1111018714
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1355311324
Short name T501
Test name
Test status
Simulation time 4932232747 ps
CPU time 1682.15 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:52:40 PM PST 23
Peak memory 417396 kb
Host smart-b4163eaa-ae4e-46fb-b9b6-363a05644254
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1355311324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1355311324
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.753531435
Short name T323
Test name
Test status
Simulation time 3605111176 ps
CPU time 255.74 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:28:52 PM PST 23
Peak memory 202164 kb
Host smart-23a43c72-c4a0-4ad5-8e2c-851749a49e11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753531435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.sram_ctrl_stress_pipeline.753531435
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4142386458
Short name T921
Test name
Test status
Simulation time 1774854736 ps
CPU time 105.05 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:26:22 PM PST 23
Peak memory 349420 kb
Host smart-2821c9ec-245d-4d5d-b509-9ec08e3c8844
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142386458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.4142386458
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3370354707
Short name T516
Test name
Test status
Simulation time 3470447984 ps
CPU time 811.4 seconds
Started Dec 24 01:24:46 PM PST 23
Finished Dec 24 01:38:18 PM PST 23
Peak memory 378028 kb
Host smart-bfc6aca2-a2cc-4d98-930a-c14296512d27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370354707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.3370354707
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.1863834730
Short name T892
Test name
Test status
Simulation time 67030758 ps
CPU time 0.64 seconds
Started Dec 24 01:24:46 PM PST 23
Finished Dec 24 01:24:48 PM PST 23
Peak memory 201804 kb
Host smart-9ca7755d-1226-4d3a-855f-c8a9eb166797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863834730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.1863834730
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.4234935215
Short name T255
Test name
Test status
Simulation time 77103806407 ps
CPU time 1686.29 seconds
Started Dec 24 01:24:41 PM PST 23
Finished Dec 24 01:52:49 PM PST 23
Peak memory 202232 kb
Host smart-daec1187-c0a8-4cab-8151-8979a1574153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234935215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.4234935215
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.2221031567
Short name T739
Test name
Test status
Simulation time 27543882654 ps
CPU time 1210.63 seconds
Started Dec 24 01:24:46 PM PST 23
Finished Dec 24 01:44:57 PM PST 23
Peak memory 371000 kb
Host smart-44a9c61c-d8ee-4710-b4da-e8a56016a24f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221031567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.2221031567
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.3695430758
Short name T595
Test name
Test status
Simulation time 22963835046 ps
CPU time 131.64 seconds
Started Dec 24 01:24:47 PM PST 23
Finished Dec 24 01:27:00 PM PST 23
Peak memory 210380 kb
Host smart-7b6d906c-a423-4f04-aa70-e6f826896cc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695430758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.3695430758
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.2169286440
Short name T741
Test name
Test status
Simulation time 3186846525 ps
CPU time 132.36 seconds
Started Dec 24 01:24:46 PM PST 23
Finished Dec 24 01:27:00 PM PST 23
Peak memory 365644 kb
Host smart-566075cf-2ac0-4025-ac07-8e23121114cd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169286440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.2169286440
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.90554351
Short name T283
Test name
Test status
Simulation time 9348174633 ps
CPU time 85.34 seconds
Started Dec 24 01:24:48 PM PST 23
Finished Dec 24 01:26:14 PM PST 23
Peak memory 211608 kb
Host smart-90da8f62-7f32-42bd-b04f-287785a8b308
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90554351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_mem_partial_access.90554351
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.1580898139
Short name T816
Test name
Test status
Simulation time 24566299473 ps
CPU time 146.14 seconds
Started Dec 24 01:24:51 PM PST 23
Finished Dec 24 01:27:18 PM PST 23
Peak memory 202588 kb
Host smart-5bdfa350-d876-4fc8-b627-1a87138956a3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580898139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.1580898139
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.3310837667
Short name T1
Test name
Test status
Simulation time 35646513191 ps
CPU time 1130.67 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:43:29 PM PST 23
Peak memory 380040 kb
Host smart-ec0f478a-bbcf-4e57-9435-76de32377dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310837667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.3310837667
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.4082859449
Short name T806
Test name
Test status
Simulation time 799403281 ps
CPU time 67.7 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:25:46 PM PST 23
Peak memory 325304 kb
Host smart-274d99c4-9357-44d2-a066-db7d88db7ccd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082859449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.4082859449
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3879079317
Short name T796
Test name
Test status
Simulation time 47229272011 ps
CPU time 515.87 seconds
Started Dec 24 01:24:35 PM PST 23
Finished Dec 24 01:33:14 PM PST 23
Peak memory 202160 kb
Host smart-2d46d497-4053-42ce-950b-ee6b8b67711b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879079317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.3879079317
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.1167149945
Short name T777
Test name
Test status
Simulation time 1342704891 ps
CPU time 6.91 seconds
Started Dec 24 01:24:47 PM PST 23
Finished Dec 24 01:24:55 PM PST 23
Peak memory 202364 kb
Host smart-60e1017f-411f-43fd-80aa-e89d98661102
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167149945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.1167149945
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.1770349645
Short name T415
Test name
Test status
Simulation time 38555508730 ps
CPU time 489.91 seconds
Started Dec 24 01:24:47 PM PST 23
Finished Dec 24 01:32:58 PM PST 23
Peak memory 374948 kb
Host smart-58ee74d1-e035-48e6-9446-284e302bf6a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770349645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1770349645
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.1329946120
Short name T708
Test name
Test status
Simulation time 2639199866 ps
CPU time 36.15 seconds
Started Dec 24 01:24:36 PM PST 23
Finished Dec 24 01:25:14 PM PST 23
Peak memory 210356 kb
Host smart-3a30e44e-d374-4c51-a852-afe4c10cac65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329946120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1329946120
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.1785415034
Short name T539
Test name
Test status
Simulation time 240744407130 ps
CPU time 5429.57 seconds
Started Dec 24 01:26:17 PM PST 23
Finished Dec 24 02:56:50 PM PST 23
Peak memory 380056 kb
Host smart-53f4c25b-dde5-42c4-a916-048b23d8e15e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785415034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.1785415034
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3396496396
Short name T674
Test name
Test status
Simulation time 638828049 ps
CPU time 3327.07 seconds
Started Dec 24 01:24:46 PM PST 23
Finished Dec 24 02:20:14 PM PST 23
Peak memory 757644 kb
Host smart-419bb88a-4d3c-4960-968a-4e8b6052794d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3396496396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3396496396
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2606375805
Short name T756
Test name
Test status
Simulation time 6130003561 ps
CPU time 245.74 seconds
Started Dec 24 01:24:34 PM PST 23
Finished Dec 24 01:28:42 PM PST 23
Peak memory 202168 kb
Host smart-6fc8b9a2-341c-4805-94ec-ab148065c367
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606375805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.2606375805
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1541904973
Short name T593
Test name
Test status
Simulation time 2827297397 ps
CPU time 30.44 seconds
Started Dec 24 01:24:46 PM PST 23
Finished Dec 24 01:25:18 PM PST 23
Peak memory 218584 kb
Host smart-c4491202-a4ab-4622-a926-46730af6e64d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541904973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.1541904973
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.691139351
Short name T606
Test name
Test status
Simulation time 7341886644 ps
CPU time 1171.64 seconds
Started Dec 24 01:24:52 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 377928 kb
Host smart-06491698-d348-4d13-8cca-930289ec2f85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691139351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 28.sram_ctrl_access_during_key_req.691139351
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.259985463
Short name T305
Test name
Test status
Simulation time 14495354 ps
CPU time 0.63 seconds
Started Dec 24 01:26:34 PM PST 23
Finished Dec 24 01:26:36 PM PST 23
Peak memory 200932 kb
Host smart-591c0856-45bc-4e43-be53-2947ef19364b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259985463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.259985463
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.1520028091
Short name T899
Test name
Test status
Simulation time 920316526810 ps
CPU time 2630.65 seconds
Started Dec 24 01:24:48 PM PST 23
Finished Dec 24 02:08:40 PM PST 23
Peak memory 202168 kb
Host smart-a7acad9e-010d-4505-97e7-f73f344cf8e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520028091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.1520028091
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.918445660
Short name T496
Test name
Test status
Simulation time 107932711773 ps
CPU time 1325.71 seconds
Started Dec 24 01:24:48 PM PST 23
Finished Dec 24 01:46:55 PM PST 23
Peak memory 371828 kb
Host smart-8481e9eb-4f47-4686-91dc-383609061dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918445660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executabl
e.918445660
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.3762267266
Short name T579
Test name
Test status
Simulation time 836294466 ps
CPU time 107.69 seconds
Started Dec 24 01:26:17 PM PST 23
Finished Dec 24 01:28:07 PM PST 23
Peak memory 357612 kb
Host smart-be43feb8-7c72-45f1-8491-fa694c6f115a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762267266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.3762267266
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.480174278
Short name T965
Test name
Test status
Simulation time 6521298173 ps
CPU time 124.6 seconds
Started Dec 24 01:26:33 PM PST 23
Finished Dec 24 01:28:39 PM PST 23
Peak memory 210664 kb
Host smart-52696a59-081e-4096-8a94-4f7c620791e6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480174278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_mem_partial_access.480174278
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.4007357721
Short name T467
Test name
Test status
Simulation time 16432625732 ps
CPU time 121.25 seconds
Started Dec 24 01:24:50 PM PST 23
Finished Dec 24 01:26:53 PM PST 23
Peak memory 202068 kb
Host smart-a7cd1c02-c9f8-4856-8ea5-eef51f7917d7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007357721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.4007357721
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.3928270947
Short name T907
Test name
Test status
Simulation time 24997609806 ps
CPU time 831.52 seconds
Started Dec 24 01:26:32 PM PST 23
Finished Dec 24 01:40:25 PM PST 23
Peak memory 375504 kb
Host smart-03333a09-e9ec-495b-a2ed-d730cc5b9805
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928270947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.3928270947
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.2058205565
Short name T671
Test name
Test status
Simulation time 1140240341 ps
CPU time 21.48 seconds
Started Dec 24 01:26:34 PM PST 23
Finished Dec 24 01:26:57 PM PST 23
Peak memory 259664 kb
Host smart-a8832a95-0545-4c4c-8430-db16c175a3b1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058205565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.2058205565
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3733648171
Short name T408
Test name
Test status
Simulation time 82165837463 ps
CPU time 300.95 seconds
Started Dec 24 01:24:49 PM PST 23
Finished Dec 24 01:29:51 PM PST 23
Peak memory 202056 kb
Host smart-77a7cfb1-e288-4275-b79f-bee953f35de2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733648171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.3733648171
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.2441495037
Short name T832
Test name
Test status
Simulation time 994013662 ps
CPU time 14.21 seconds
Started Dec 24 01:24:47 PM PST 23
Finished Dec 24 01:25:02 PM PST 23
Peak memory 202452 kb
Host smart-0834650d-a486-4a14-a004-9375c43a4b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441495037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2441495037
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.357592772
Short name T768
Test name
Test status
Simulation time 8838879109 ps
CPU time 1610.91 seconds
Started Dec 24 01:24:47 PM PST 23
Finished Dec 24 01:51:39 PM PST 23
Peak memory 380144 kb
Host smart-f9a6bf53-79f0-4fcc-b865-b40e607da08d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357592772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.357592772
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.967123329
Short name T304
Test name
Test status
Simulation time 1437183595 ps
CPU time 5.65 seconds
Started Dec 24 01:24:51 PM PST 23
Finished Dec 24 01:24:57 PM PST 23
Peak memory 202092 kb
Host smart-04d3d6e5-627f-41fe-8379-3bfa9e34137c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967123329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.967123329
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.4082735776
Short name T818
Test name
Test status
Simulation time 947104301 ps
CPU time 5536.75 seconds
Started Dec 24 01:24:51 PM PST 23
Finished Dec 24 02:57:09 PM PST 23
Peak memory 750156 kb
Host smart-d482e1a4-4616-42a2-a173-1e645728c1a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4082735776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.4082735776
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.595874589
Short name T278
Test name
Test status
Simulation time 18519343041 ps
CPU time 352.09 seconds
Started Dec 24 01:24:51 PM PST 23
Finished Dec 24 01:30:44 PM PST 23
Peak memory 202176 kb
Host smart-207e11f0-36af-46b5-842e-00bd0ae4e254
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595874589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_stress_pipeline.595874589
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3679607297
Short name T542
Test name
Test status
Simulation time 755842406 ps
CPU time 27.67 seconds
Started Dec 24 01:24:47 PM PST 23
Finished Dec 24 01:25:16 PM PST 23
Peak memory 210380 kb
Host smart-e85d6320-6bf9-4144-ba3a-e657d443e9e1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679607297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.3679607297
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2636550313
Short name T544
Test name
Test status
Simulation time 2068551758 ps
CPU time 369.84 seconds
Started Dec 24 01:24:53 PM PST 23
Finished Dec 24 01:31:03 PM PST 23
Peak memory 375432 kb
Host smart-3eeaa043-16c7-42fa-bd3a-c2fc65c86796
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636550313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.2636550313
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.658317525
Short name T657
Test name
Test status
Simulation time 57703101 ps
CPU time 0.66 seconds
Started Dec 24 01:25:17 PM PST 23
Finished Dec 24 01:25:18 PM PST 23
Peak memory 201444 kb
Host smart-4dd29cfa-eb4f-4db2-80de-0d330ec04d97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658317525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.658317525
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.1967441920
Short name T339
Test name
Test status
Simulation time 383542484305 ps
CPU time 2322.43 seconds
Started Dec 24 01:24:51 PM PST 23
Finished Dec 24 02:03:35 PM PST 23
Peak memory 210356 kb
Host smart-6ebed424-8724-4b5f-9777-ae6e05b655c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967441920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.1967441920
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.3062283767
Short name T935
Test name
Test status
Simulation time 784541881 ps
CPU time 205.51 seconds
Started Dec 24 01:24:49 PM PST 23
Finished Dec 24 01:28:15 PM PST 23
Peak memory 365744 kb
Host smart-e27d3cf2-e776-471c-b471-384f1aedcdd9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062283767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.3062283767
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1607979037
Short name T237
Test name
Test status
Simulation time 1602407557 ps
CPU time 142.21 seconds
Started Dec 24 01:25:20 PM PST 23
Finished Dec 24 01:27:45 PM PST 23
Peak memory 213836 kb
Host smart-1b89e59d-8197-41b0-9c89-bf66d6626dd1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607979037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.1607979037
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.2424514617
Short name T262
Test name
Test status
Simulation time 21511506429 ps
CPU time 303.08 seconds
Started Dec 24 01:25:38 PM PST 23
Finished Dec 24 01:30:44 PM PST 23
Peak memory 202072 kb
Host smart-12d0a6d0-ca2f-41b5-953e-278884f06aac
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424514617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.2424514617
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.736320725
Short name T256
Test name
Test status
Simulation time 23535422008 ps
CPU time 1361.16 seconds
Started Dec 24 01:24:48 PM PST 23
Finished Dec 24 01:47:30 PM PST 23
Peak memory 368816 kb
Host smart-d75e2f4c-d4cf-41aa-87e8-a87b5cb3d3e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736320725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multip
le_keys.736320725
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.40673244
Short name T590
Test name
Test status
Simulation time 1362585219 ps
CPU time 22.96 seconds
Started Dec 24 01:26:17 PM PST 23
Finished Dec 24 01:26:42 PM PST 23
Peak memory 208052 kb
Host smart-b2f7ffad-28d4-49dd-9e8d-9b9c5a32ee6a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40673244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sr
am_ctrl_partial_access.40673244
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.4231660859
Short name T704
Test name
Test status
Simulation time 53290471994 ps
CPU time 339.3 seconds
Started Dec 24 01:26:17 PM PST 23
Finished Dec 24 01:31:59 PM PST 23
Peak memory 200208 kb
Host smart-4f0b9083-1f5d-43f4-a6e0-c2109d7548a6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231660859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.4231660859
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.3719581348
Short name T953
Test name
Test status
Simulation time 706949771 ps
CPU time 7.05 seconds
Started Dec 24 01:24:46 PM PST 23
Finished Dec 24 01:24:54 PM PST 23
Peak memory 202404 kb
Host smart-767b6589-241c-45d8-ba84-4c03ce089e32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719581348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3719581348
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.1014315636
Short name T416
Test name
Test status
Simulation time 8569847555 ps
CPU time 370.93 seconds
Started Dec 24 01:24:46 PM PST 23
Finished Dec 24 01:30:58 PM PST 23
Peak memory 367536 kb
Host smart-1b06c629-42f6-49d3-9910-903bac03a61e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014315636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1014315636
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.3981539349
Short name T730
Test name
Test status
Simulation time 2499733496 ps
CPU time 77.89 seconds
Started Dec 24 01:26:35 PM PST 23
Finished Dec 24 01:27:54 PM PST 23
Peak memory 342668 kb
Host smart-e035524d-6146-4a1a-9d93-b4a70fe299b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981539349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3981539349
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.3127458142
Short name T424
Test name
Test status
Simulation time 328555149036 ps
CPU time 4139.11 seconds
Started Dec 24 01:25:26 PM PST 23
Finished Dec 24 02:34:33 PM PST 23
Peak memory 371972 kb
Host smart-0410b5c6-369a-4ae7-a6ff-fe84e99bc726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127458142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.sram_ctrl_stress_all.3127458142
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3542891741
Short name T886
Test name
Test status
Simulation time 17437535445 ps
CPU time 3013.63 seconds
Started Dec 24 01:25:16 PM PST 23
Finished Dec 24 02:15:31 PM PST 23
Peak memory 555764 kb
Host smart-0cb7f311-a4b4-4256-b2d2-f304bdfe9acd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3542891741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3542891741
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2813967750
Short name T267
Test name
Test status
Simulation time 2559138879 ps
CPU time 160.54 seconds
Started Dec 24 01:26:34 PM PST 23
Finished Dec 24 01:29:16 PM PST 23
Peak memory 201672 kb
Host smart-0cec74b8-4000-48b3-ad9f-cd1be51d5442
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813967750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.2813967750
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1273369048
Short name T790
Test name
Test status
Simulation time 3980545993 ps
CPU time 27.51 seconds
Started Dec 24 01:24:53 PM PST 23
Finished Dec 24 01:25:21 PM PST 23
Peak memory 216988 kb
Host smart-12ad9717-23dd-4c7a-aaaa-7182e7dc1602
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273369048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1273369048
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.559869931
Short name T877
Test name
Test status
Simulation time 7164350012 ps
CPU time 68.75 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:23:15 PM PST 23
Peak memory 269580 kb
Host smart-0e610c40-c647-4412-a7a1-3be8a5cf9737
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559869931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_access_during_key_req.559869931
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.3217725956
Short name T452
Test name
Test status
Simulation time 120537089 ps
CPU time 0.66 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:22:10 PM PST 23
Peak memory 201248 kb
Host smart-11b6f8e2-7a96-47d6-9610-55ea4432d77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217725956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.3217725956
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.1138476225
Short name T469
Test name
Test status
Simulation time 76781030366 ps
CPU time 1732.9 seconds
Started Dec 24 01:22:00 PM PST 23
Finished Dec 24 01:50:54 PM PST 23
Peak memory 202168 kb
Host smart-1e2eed51-0ad6-469c-b5e3-380c3d999dfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138476225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
1138476225
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.3276521174
Short name T426
Test name
Test status
Simulation time 29766641401 ps
CPU time 736.74 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:34:20 PM PST 23
Peak memory 355700 kb
Host smart-88f5d988-31f8-4287-9b09-91d1884ee255
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276521174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.3276521174
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.1576040383
Short name T333
Test name
Test status
Simulation time 40791499878 ps
CPU time 102.94 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:23:48 PM PST 23
Peak memory 210320 kb
Host smart-49cdc93f-bba5-4ffd-9dfe-88a2c33c70ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576040383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.1576040383
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.2961239946
Short name T888
Test name
Test status
Simulation time 740091329 ps
CPU time 88.09 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:23:34 PM PST 23
Peak memory 319672 kb
Host smart-013f318a-f577-422e-9739-ba294b180af9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961239946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.2961239946
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1479685445
Short name T442
Test name
Test status
Simulation time 9413522869 ps
CPU time 77.73 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:23:25 PM PST 23
Peak memory 211132 kb
Host smart-7a66e08a-94cd-438f-a3d3-21571949e13a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479685445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.1479685445
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.3332274970
Short name T227
Test name
Test status
Simulation time 10550538640 ps
CPU time 158.53 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:24:44 PM PST 23
Peak memory 202124 kb
Host smart-df725fdc-8bd5-4df6-87d0-5dbdd9b93bd1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332274970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.3332274970
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.2740074912
Short name T381
Test name
Test status
Simulation time 10559360001 ps
CPU time 160.77 seconds
Started Dec 24 01:22:02 PM PST 23
Finished Dec 24 01:24:44 PM PST 23
Peak memory 289584 kb
Host smart-00a5f3b8-63e2-4047-845e-6a3a7d84258b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740074912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.2740074912
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.1189409031
Short name T272
Test name
Test status
Simulation time 3294006654 ps
CPU time 64.5 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:23:10 PM PST 23
Peak memory 314552 kb
Host smart-043a96f4-0142-414a-b3ac-dec6d005ab7f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189409031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.1189409031
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3664891110
Short name T687
Test name
Test status
Simulation time 6773005458 ps
CPU time 224.95 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:25:50 PM PST 23
Peak memory 202144 kb
Host smart-ac7ec0c5-62e2-4a47-a848-232ccfc05591
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664891110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.3664891110
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.3560038974
Short name T534
Test name
Test status
Simulation time 1770672244 ps
CPU time 6.93 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:22:11 PM PST 23
Peak memory 202448 kb
Host smart-e4da53c9-26f5-4bd5-b7c8-a40d63aac51a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560038974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3560038974
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1882351848
Short name T433
Test name
Test status
Simulation time 13477649130 ps
CPU time 1640.44 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:49:28 PM PST 23
Peak memory 380120 kb
Host smart-2f83a756-f23f-4173-8936-984e8475e1c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882351848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1882351848
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.3983446191
Short name T25
Test name
Test status
Simulation time 115574572 ps
CPU time 2.08 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:22:09 PM PST 23
Peak memory 220964 kb
Host smart-7034085d-4ccf-416c-8a24-becb0357708d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983446191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.3983446191
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.2745445212
Short name T325
Test name
Test status
Simulation time 27340725187 ps
CPU time 37.17 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:22:44 PM PST 23
Peak memory 202144 kb
Host smart-eb9e8b1c-516d-4452-ba14-805d38dd9fe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745445212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2745445212
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2407201278
Short name T335
Test name
Test status
Simulation time 1314950236 ps
CPU time 4168.29 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 02:31:36 PM PST 23
Peak memory 508436 kb
Host smart-0e2b997f-a551-422c-a3a1-1c423cd1d17d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2407201278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2407201278
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.803253188
Short name T618
Test name
Test status
Simulation time 4516086800 ps
CPU time 344.85 seconds
Started Dec 24 01:21:58 PM PST 23
Finished Dec 24 01:27:44 PM PST 23
Peak memory 202160 kb
Host smart-88e4b5b8-c80e-48a5-aefa-2fb832a16296
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803253188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
sram_ctrl_stress_pipeline.803253188
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2064326602
Short name T538
Test name
Test status
Simulation time 3128374294 ps
CPU time 194.18 seconds
Started Dec 24 01:21:59 PM PST 23
Finished Dec 24 01:25:14 PM PST 23
Peak memory 361616 kb
Host smart-369ddb40-d56a-43a6-8bdc-56a10977810c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064326602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2064326602
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2299791092
Short name T525
Test name
Test status
Simulation time 8068102686 ps
CPU time 1034.11 seconds
Started Dec 24 01:25:35 PM PST 23
Finished Dec 24 01:42:51 PM PST 23
Peak memory 376008 kb
Host smart-e244d54b-459d-4542-9140-d76e54ab2be0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299791092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.2299791092
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.1085570241
Short name T918
Test name
Test status
Simulation time 17380159 ps
CPU time 0.68 seconds
Started Dec 24 01:25:23 PM PST 23
Finished Dec 24 01:25:27 PM PST 23
Peak memory 201336 kb
Host smart-e45ee1d6-ffb6-41ff-889c-6456c1450028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085570241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.1085570241
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.73316209
Short name T420
Test name
Test status
Simulation time 100206329437 ps
CPU time 908.86 seconds
Started Dec 24 01:25:35 PM PST 23
Finished Dec 24 01:40:46 PM PST 23
Peak memory 202220 kb
Host smart-fa7a8730-c6b7-4b57-8ffe-b44255cd7360
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73316209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.73316209
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.1874878564
Short name T602
Test name
Test status
Simulation time 8924357305 ps
CPU time 83.66 seconds
Started Dec 24 01:25:26 PM PST 23
Finished Dec 24 01:26:57 PM PST 23
Peak memory 210288 kb
Host smart-8b9b15f9-65cc-4fb6-bab0-bd86fc6e6a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874878564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.1874878564
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.3981624964
Short name T646
Test name
Test status
Simulation time 785072782 ps
CPU time 128.63 seconds
Started Dec 24 01:25:24 PM PST 23
Finished Dec 24 01:27:34 PM PST 23
Peak memory 365684 kb
Host smart-3b514d27-d584-471a-af40-f95613d56569
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981624964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.3981624964
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2411804393
Short name T89
Test name
Test status
Simulation time 22657319306 ps
CPU time 163.18 seconds
Started Dec 24 01:25:40 PM PST 23
Finished Dec 24 01:28:25 PM PST 23
Peak memory 214336 kb
Host smart-58083476-b812-486e-bec6-0be59914e3ce
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411804393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.2411804393
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.1146617300
Short name T554
Test name
Test status
Simulation time 15761159281 ps
CPU time 270.44 seconds
Started Dec 24 01:25:24 PM PST 23
Finished Dec 24 01:29:56 PM PST 23
Peak memory 202200 kb
Host smart-692928e6-1858-4ba6-9aac-a88e9b255fa4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146617300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.1146617300
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.631777419
Short name T514
Test name
Test status
Simulation time 42418422239 ps
CPU time 1933.05 seconds
Started Dec 24 01:25:25 PM PST 23
Finished Dec 24 01:57:46 PM PST 23
Peak memory 380124 kb
Host smart-ebce2ab9-81e9-47f6-b1e1-a58c5702bfc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631777419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multip
le_keys.631777419
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.1641760838
Short name T150
Test name
Test status
Simulation time 4345252210 ps
CPU time 19.7 seconds
Started Dec 24 01:25:24 PM PST 23
Finished Dec 24 01:25:51 PM PST 23
Peak memory 202124 kb
Host smart-fca896d8-a2b0-4a84-a465-f22f2891930c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641760838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.1641760838
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1985700700
Short name T384
Test name
Test status
Simulation time 25233520540 ps
CPU time 434.81 seconds
Started Dec 24 01:25:32 PM PST 23
Finished Dec 24 01:32:49 PM PST 23
Peak memory 202172 kb
Host smart-cd99e30b-7ebe-42b6-abb4-65fa01570965
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985700700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.1985700700
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.3904853335
Short name T959
Test name
Test status
Simulation time 368260763 ps
CPU time 5.65 seconds
Started Dec 24 01:25:37 PM PST 23
Finished Dec 24 01:25:44 PM PST 23
Peak memory 202432 kb
Host smart-601894fe-5c7f-41b7-8a1d-a8e17e2c9cf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904853335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3904853335
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.2264730169
Short name T135
Test name
Test status
Simulation time 35361588234 ps
CPU time 1470.32 seconds
Started Dec 24 01:25:17 PM PST 23
Finished Dec 24 01:49:53 PM PST 23
Peak memory 372900 kb
Host smart-d3441122-b367-46e8-8e1b-3d749fbc14d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264730169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2264730169
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.2833264792
Short name T375
Test name
Test status
Simulation time 1974578979 ps
CPU time 43.57 seconds
Started Dec 24 01:25:32 PM PST 23
Finished Dec 24 01:26:18 PM PST 23
Peak memory 288860 kb
Host smart-9b2b3ed7-d381-45e0-8ab3-1e1f79081b3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833264792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2833264792
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3411826640
Short name T444
Test name
Test status
Simulation time 1069967539 ps
CPU time 3613.41 seconds
Started Dec 24 01:25:32 PM PST 23
Finished Dec 24 02:25:48 PM PST 23
Peak memory 697972 kb
Host smart-87b8b51a-0a1d-48c4-919f-a53ef2da9ba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3411826640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3411826640
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.3413282713
Short name T370
Test name
Test status
Simulation time 26613449520 ps
CPU time 549.18 seconds
Started Dec 24 01:25:26 PM PST 23
Finished Dec 24 01:34:42 PM PST 23
Peak memory 202180 kb
Host smart-c7985d3e-7d67-49af-9031-5c4795a62c12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413282713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.3413282713
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.4077198490
Short name T865
Test name
Test status
Simulation time 2944184506 ps
CPU time 37.86 seconds
Started Dec 24 01:25:32 PM PST 23
Finished Dec 24 01:26:12 PM PST 23
Peak memory 256856 kb
Host smart-0bd6386c-54c0-499d-a620-fe00c5f434ed
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077198490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.4077198490
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2914485235
Short name T914
Test name
Test status
Simulation time 34389538353 ps
CPU time 2211.13 seconds
Started Dec 24 01:25:26 PM PST 23
Finished Dec 24 02:02:24 PM PST 23
Peak memory 375992 kb
Host smart-ef619bbb-df0f-40dd-bdc0-49c42ac98cb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914485235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.2914485235
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.2853848576
Short name T446
Test name
Test status
Simulation time 15304481 ps
CPU time 0.69 seconds
Started Dec 24 01:25:51 PM PST 23
Finished Dec 24 01:25:55 PM PST 23
Peak memory 201784 kb
Host smart-c91a18dc-abd4-4371-8782-55767de8e693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853848576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.2853848576
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.3351836610
Short name T239
Test name
Test status
Simulation time 392423311716 ps
CPU time 2542.06 seconds
Started Dec 24 01:25:25 PM PST 23
Finished Dec 24 02:07:54 PM PST 23
Peak memory 202216 kb
Host smart-bc1bcd69-71fd-452d-9623-2ef0af272ca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351836610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.3351836610
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.1160021033
Short name T786
Test name
Test status
Simulation time 3062797951 ps
CPU time 173.13 seconds
Started Dec 24 01:25:26 PM PST 23
Finished Dec 24 01:28:26 PM PST 23
Peak memory 366756 kb
Host smart-aa3fefc1-46a5-436b-aaff-59316f0c7949
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160021033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.1160021033
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2401750447
Short name T9
Test name
Test status
Simulation time 4298092307 ps
CPU time 79.85 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:27:16 PM PST 23
Peak memory 218536 kb
Host smart-4f84358e-dec6-4a34-b493-937d4fe93bd8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401750447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.2401750447
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.1942367522
Short name T493
Test name
Test status
Simulation time 129094667223 ps
CPU time 320 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:31:13 PM PST 23
Peak memory 202072 kb
Host smart-16c1ed7e-37af-4f75-94ef-1bb1a3cc1f61
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942367522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.1942367522
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.2161700140
Short name T656
Test name
Test status
Simulation time 19238362369 ps
CPU time 428.36 seconds
Started Dec 24 01:25:24 PM PST 23
Finished Dec 24 01:32:40 PM PST 23
Peak memory 362332 kb
Host smart-bb5c2f1e-edfd-49aa-bfbf-d4b57192033a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161700140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.2161700140
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.3039058473
Short name T276
Test name
Test status
Simulation time 3720098442 ps
CPU time 18.14 seconds
Started Dec 24 01:25:32 PM PST 23
Finished Dec 24 01:25:52 PM PST 23
Peak memory 202132 kb
Host smart-2dc2c1e4-623e-43b3-b7d8-b93bb2a5ea24
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039058473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.3039058473
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.869352784
Short name T461
Test name
Test status
Simulation time 42726166841 ps
CPU time 248.46 seconds
Started Dec 24 01:25:37 PM PST 23
Finished Dec 24 01:29:49 PM PST 23
Peak memory 202156 kb
Host smart-6b1941be-adff-4706-841d-12916959aa89
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869352784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.sram_ctrl_partial_access_b2b.869352784
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.1411096860
Short name T821
Test name
Test status
Simulation time 345911693 ps
CPU time 6.59 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:26:00 PM PST 23
Peak memory 202332 kb
Host smart-50c5cfa1-b701-487f-9d5e-d1b7522d9169
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411096860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1411096860
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.3982506182
Short name T508
Test name
Test status
Simulation time 1778039277 ps
CPU time 353.14 seconds
Started Dec 24 01:25:31 PM PST 23
Finished Dec 24 01:31:26 PM PST 23
Peak memory 365676 kb
Host smart-3c1dbd75-7499-45df-886c-5bf847b5d659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982506182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3982506182
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.3679015312
Short name T712
Test name
Test status
Simulation time 1466715874 ps
CPU time 6.49 seconds
Started Dec 24 01:25:34 PM PST 23
Finished Dec 24 01:25:43 PM PST 23
Peak memory 202088 kb
Host smart-6e6adf31-6853-488f-994b-6142ad6ba4f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679015312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3679015312
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.2686831989
Short name T834
Test name
Test status
Simulation time 257387240671 ps
CPU time 2793.03 seconds
Started Dec 24 01:25:49 PM PST 23
Finished Dec 24 02:12:26 PM PST 23
Peak memory 377084 kb
Host smart-30b82f8b-ec1b-4f36-8979-2b0a2a19e5b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686831989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.2686831989
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2248631462
Short name T572
Test name
Test status
Simulation time 2262747129 ps
CPU time 3068.18 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 02:17:01 PM PST 23
Peak memory 699224 kb
Host smart-3311c00a-4a7d-4388-b66f-2b17d841771d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2248631462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2248631462
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1865554518
Short name T435
Test name
Test status
Simulation time 19896660074 ps
CPU time 363.39 seconds
Started Dec 24 01:25:37 PM PST 23
Finished Dec 24 01:31:42 PM PST 23
Peak memory 202176 kb
Host smart-96df662b-8663-4003-b66d-1af8c549d70b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865554518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.1865554518
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.4184746799
Short name T793
Test name
Test status
Simulation time 1552892185 ps
CPU time 100.68 seconds
Started Dec 24 01:25:24 PM PST 23
Finished Dec 24 01:27:06 PM PST 23
Peak memory 332112 kb
Host smart-d1a08443-ed8c-4291-9bd5-3456b8c635d4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184746799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.4184746799
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.87495985
Short name T522
Test name
Test status
Simulation time 18400309 ps
CPU time 0.62 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:25:54 PM PST 23
Peak memory 201568 kb
Host smart-dc7cf99c-c03d-45d0-867d-11f8d076ab67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87495985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_alert_test.87495985
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.2589241763
Short name T709
Test name
Test status
Simulation time 127230483576 ps
CPU time 2235.41 seconds
Started Dec 24 01:25:49 PM PST 23
Finished Dec 24 02:03:08 PM PST 23
Peak memory 202132 kb
Host smart-b91a5654-2338-4943-846d-123e25f3897a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589241763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.2589241763
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.1403295429
Short name T694
Test name
Test status
Simulation time 81577065850 ps
CPU time 1354.4 seconds
Started Dec 24 01:25:33 PM PST 23
Finished Dec 24 01:48:09 PM PST 23
Peak memory 373864 kb
Host smart-fceaab81-d02f-4f2e-8748-5363575adc4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403295429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.1403295429
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.2048129187
Short name T897
Test name
Test status
Simulation time 28207042623 ps
CPU time 121.95 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:27:58 PM PST 23
Peak memory 213972 kb
Host smart-3da5306c-2a22-4721-a9ba-522b68bdaea9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048129187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.2048129187
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.1608790768
Short name T43
Test name
Test status
Simulation time 3020847750 ps
CPU time 27.69 seconds
Started Dec 24 01:25:51 PM PST 23
Finished Dec 24 01:26:22 PM PST 23
Peak memory 210468 kb
Host smart-4dc8038a-86fc-44c6-a9c2-2032ea7e6418
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608790768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.1608790768
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2192230232
Short name T724
Test name
Test status
Simulation time 1595914306 ps
CPU time 137.5 seconds
Started Dec 24 01:25:51 PM PST 23
Finished Dec 24 01:28:11 PM PST 23
Peak memory 211548 kb
Host smart-1ebed5c4-0ee8-4d18-ae0a-78ee1f9f7bff
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192230232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.2192230232
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.228915561
Short name T625
Test name
Test status
Simulation time 4108972932 ps
CPU time 252.33 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:30:06 PM PST 23
Peak memory 201960 kb
Host smart-5e3b0eed-1638-40a6-be7a-07f18cdb59c2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228915561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl
_mem_walk.228915561
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.1498714669
Short name T476
Test name
Test status
Simulation time 14144688929 ps
CPU time 1768.57 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:55:22 PM PST 23
Peak memory 379052 kb
Host smart-2eaefb61-d005-48a5-a365-7d4572ea93e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498714669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.1498714669
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.3845137871
Short name T847
Test name
Test status
Simulation time 1694516259 ps
CPU time 27.31 seconds
Started Dec 24 01:25:33 PM PST 23
Finished Dec 24 01:26:03 PM PST 23
Peak memory 259284 kb
Host smart-2152bf86-976b-49f6-9c00-e360dcb239d4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845137871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.3845137871
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.1676236725
Short name T789
Test name
Test status
Simulation time 358594677 ps
CPU time 5.37 seconds
Started Dec 24 01:25:51 PM PST 23
Finished Dec 24 01:26:00 PM PST 23
Peak memory 202416 kb
Host smart-55388144-8693-4b44-8ad0-d17be501e761
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676236725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1676236725
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.254303626
Short name T567
Test name
Test status
Simulation time 15213168992 ps
CPU time 1184.52 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:45:41 PM PST 23
Peak memory 375884 kb
Host smart-9159782d-a458-4c97-aa27-49db30917e0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254303626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.254303626
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.3209415704
Short name T364
Test name
Test status
Simulation time 695674224 ps
CPU time 14.14 seconds
Started Dec 24 01:25:51 PM PST 23
Finished Dec 24 01:26:08 PM PST 23
Peak memory 201924 kb
Host smart-82f5cfec-e2b9-4694-856f-7fda2bf574fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209415704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3209415704
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1290970762
Short name T836
Test name
Test status
Simulation time 236170512 ps
CPU time 3594.83 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 02:25:48 PM PST 23
Peak memory 431684 kb
Host smart-6faffe61-0241-4743-9712-c4923e2ebf20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1290970762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1290970762
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.131371347
Short name T106
Test name
Test status
Simulation time 18067890810 ps
CPU time 345.58 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:31:42 PM PST 23
Peak memory 202064 kb
Host smart-c5c85778-5df7-4959-9649-70b9f902c313
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131371347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_stress_pipeline.131371347
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1357004140
Short name T609
Test name
Test status
Simulation time 733282839 ps
CPU time 48.49 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:26:41 PM PST 23
Peak memory 267584 kb
Host smart-62b50609-7b25-4c2c-9730-dc694d6e273d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357004140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1357004140
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2062376530
Short name T498
Test name
Test status
Simulation time 20236320293 ps
CPU time 1558.76 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:51:55 PM PST 23
Peak memory 379944 kb
Host smart-4ad02d0a-e6c2-48e6-9f68-b71a8cbd153b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062376530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.2062376530
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.2250871210
Short name T813
Test name
Test status
Simulation time 37802234 ps
CPU time 0.63 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:25:54 PM PST 23
Peak memory 201444 kb
Host smart-ca65a463-3682-474c-bfc2-5ac0fdc0309d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250871210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.2250871210
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.1323940335
Short name T449
Test name
Test status
Simulation time 76067773100 ps
CPU time 1225.23 seconds
Started Dec 24 01:25:49 PM PST 23
Finished Dec 24 01:46:18 PM PST 23
Peak memory 202180 kb
Host smart-9d59e603-8cb9-4b3b-9ad9-d0d9d6149bda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323940335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.1323940335
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.1881845819
Short name T441
Test name
Test status
Simulation time 1237218387 ps
CPU time 17.79 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:26:14 PM PST 23
Peak memory 210336 kb
Host smart-b1f48c8e-9668-4e5f-816d-7d51a13512b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881845819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.1881845819
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.3573403115
Short name T240
Test name
Test status
Simulation time 1360854233 ps
CPU time 27.27 seconds
Started Dec 24 01:25:32 PM PST 23
Finished Dec 24 01:26:01 PM PST 23
Peak memory 220324 kb
Host smart-92e2f7d5-a438-4665-a3ef-72d689d29ad8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573403115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.3573403115
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1416212218
Short name T140
Test name
Test status
Simulation time 18260716838 ps
CPU time 154.57 seconds
Started Dec 24 01:25:49 PM PST 23
Finished Dec 24 01:28:26 PM PST 23
Peak memory 211780 kb
Host smart-6fc05bc8-051f-4b60-ae30-418340a3129f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416212218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.1416212218
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.3990978058
Short name T434
Test name
Test status
Simulation time 8046408125 ps
CPU time 247.98 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:30:01 PM PST 23
Peak memory 202148 kb
Host smart-22bc2d67-f5d1-49b4-925c-e8d67a88e7c9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990978058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.3990978058
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.780639191
Short name T716
Test name
Test status
Simulation time 744403104 ps
CPU time 47.14 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:26:40 PM PST 23
Peak memory 287476 kb
Host smart-855a1aa5-d824-4006-9d35-319d709a068d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780639191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s
ram_ctrl_partial_access.780639191
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4197675586
Short name T654
Test name
Test status
Simulation time 7187656380 ps
CPU time 433.33 seconds
Started Dec 24 01:25:51 PM PST 23
Finished Dec 24 01:33:08 PM PST 23
Peak memory 202196 kb
Host smart-d9d5e558-94a4-440e-8858-8c157a4f8ac1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197675586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.4197675586
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.3969137359
Short name T486
Test name
Test status
Simulation time 366647372 ps
CPU time 5.35 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:25:58 PM PST 23
Peak memory 202412 kb
Host smart-535a116d-bf02-46a3-a411-0fb5a7c3a4e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969137359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3969137359
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.1547016562
Short name T132
Test name
Test status
Simulation time 3948018537 ps
CPU time 1122.8 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:44:36 PM PST 23
Peak memory 369344 kb
Host smart-f1a62edd-e3d0-4d5f-886c-525414fc4c8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547016562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1547016562
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.77518612
Short name T398
Test name
Test status
Simulation time 4069926802 ps
CPU time 41.02 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:26:34 PM PST 23
Peak memory 202224 kb
Host smart-b8ddfecb-50f2-4b9d-88b4-c159b6f1869b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77518612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.77518612
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1209893905
Short name T352
Test name
Test status
Simulation time 186902651 ps
CPU time 2090.13 seconds
Started Dec 24 01:25:48 PM PST 23
Finished Dec 24 02:00:42 PM PST 23
Peak memory 605632 kb
Host smart-9fa8125c-684f-4663-b27c-be668076bd59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1209893905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1209893905
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2704778699
Short name T974
Test name
Test status
Simulation time 6170240631 ps
CPU time 197.63 seconds
Started Dec 24 01:25:49 PM PST 23
Finished Dec 24 01:29:10 PM PST 23
Peak memory 202168 kb
Host smart-948a2a30-fbfc-421f-95b1-beb5f5988632
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704778699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.2704778699
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3038256684
Short name T905
Test name
Test status
Simulation time 1433129229 ps
CPU time 97.36 seconds
Started Dec 24 01:25:49 PM PST 23
Finished Dec 24 01:27:30 PM PST 23
Peak memory 330868 kb
Host smart-51d2293f-61e8-4bba-b8bf-901695edca79
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038256684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3038256684
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3960933382
Short name T321
Test name
Test status
Simulation time 37784009231 ps
CPU time 402.47 seconds
Started Dec 24 01:26:08 PM PST 23
Finished Dec 24 01:32:53 PM PST 23
Peak memory 339136 kb
Host smart-2cde618e-40cc-4ac9-8cc4-093230fc3ef9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960933382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.3960933382
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.3151764195
Short name T904
Test name
Test status
Simulation time 51636400 ps
CPU time 0.64 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:26:08 PM PST 23
Peak memory 201836 kb
Host smart-6e7671d5-11a3-41aa-8bca-eb509e130fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151764195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.3151764195
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.2447028450
Short name T762
Test name
Test status
Simulation time 92400361972 ps
CPU time 925.38 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:41:19 PM PST 23
Peak memory 202072 kb
Host smart-7337d14d-9da4-4140-b263-0e50e44b49a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447028450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.2447028450
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.2393424380
Short name T743
Test name
Test status
Simulation time 819441513 ps
CPU time 167.58 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:28:54 PM PST 23
Peak memory 366764 kb
Host smart-20fdb727-588e-4586-942e-850b670688d1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393424380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.2393424380
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3176479992
Short name T506
Test name
Test status
Simulation time 6739550122 ps
CPU time 135.92 seconds
Started Dec 24 01:26:06 PM PST 23
Finished Dec 24 01:28:24 PM PST 23
Peak memory 211252 kb
Host smart-5683b6b7-71e9-4865-a5a0-8f0b188246f6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176479992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.3176479992
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.3743365016
Short name T774
Test name
Test status
Simulation time 7594641469 ps
CPU time 134.37 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:28:21 PM PST 23
Peak memory 202312 kb
Host smart-aaf09b6a-ff48-4c67-8543-391b46a953f2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743365016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.3743365016
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.3739402500
Short name T981
Test name
Test status
Simulation time 17207941814 ps
CPU time 850.18 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:40:03 PM PST 23
Peak memory 369252 kb
Host smart-cf30ff78-2778-4cbc-ac04-8dfdf03740c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739402500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.3739402500
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.2651600517
Short name T261
Test name
Test status
Simulation time 2261266926 ps
CPU time 20.14 seconds
Started Dec 24 01:26:15 PM PST 23
Finished Dec 24 01:26:36 PM PST 23
Peak memory 202100 kb
Host smart-478278d9-23a3-4363-87dc-946c49a8b033
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651600517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.2651600517
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.782316218
Short name T612
Test name
Test status
Simulation time 38461958174 ps
CPU time 393.28 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:32:40 PM PST 23
Peak memory 202176 kb
Host smart-24dcb99a-e86d-402b-8aa8-de63aaa2ae9f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782316218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.sram_ctrl_partial_access_b2b.782316218
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.1232487032
Short name T500
Test name
Test status
Simulation time 1409192497 ps
CPU time 6.66 seconds
Started Dec 24 01:26:06 PM PST 23
Finished Dec 24 01:26:15 PM PST 23
Peak memory 202440 kb
Host smart-55e17e7c-c783-4f9c-a36f-dae7408cca64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232487032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1232487032
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.467800838
Short name T898
Test name
Test status
Simulation time 9213072327 ps
CPU time 1005.17 seconds
Started Dec 24 01:26:04 PM PST 23
Finished Dec 24 01:42:51 PM PST 23
Peak memory 380120 kb
Host smart-7adc42e4-393e-4ebd-ac63-0f649f4bf338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467800838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.467800838
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.2527374656
Short name T686
Test name
Test status
Simulation time 2930037151 ps
CPU time 124.54 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:27:58 PM PST 23
Peak memory 366656 kb
Host smart-1ae0d900-677e-4302-82bb-d9510a143a0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527374656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2527374656
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3799570589
Short name T275
Test name
Test status
Simulation time 3843063076 ps
CPU time 3476.49 seconds
Started Dec 24 01:26:09 PM PST 23
Finished Dec 24 02:24:08 PM PST 23
Peak memory 674440 kb
Host smart-47192869-0523-4883-b757-3b04be4ceda4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3799570589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3799570589
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1471635767
Short name T697
Test name
Test status
Simulation time 31933410686 ps
CPU time 475.46 seconds
Started Dec 24 01:25:50 PM PST 23
Finished Dec 24 01:33:48 PM PST 23
Peak memory 202168 kb
Host smart-a744e9b0-35a3-4399-81ea-ec3031c17f9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471635767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.1471635767
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2157202785
Short name T770
Test name
Test status
Simulation time 1468598849 ps
CPU time 64.2 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:27:12 PM PST 23
Peak memory 296116 kb
Host smart-77bce963-78ec-4e55-9dc1-6ae615eda909
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157202785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2157202785
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1313603013
Short name T367
Test name
Test status
Simulation time 23002423405 ps
CPU time 1664.94 seconds
Started Dec 24 01:26:12 PM PST 23
Finished Dec 24 01:53:58 PM PST 23
Peak memory 368908 kb
Host smart-69890cc0-5f27-4242-a199-4e0c2f8a51ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313603013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.1313603013
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.678287562
Short name T494
Test name
Test status
Simulation time 33540783 ps
CPU time 0.65 seconds
Started Dec 24 01:25:53 PM PST 23
Finished Dec 24 01:25:57 PM PST 23
Peak memory 201396 kb
Host smart-b1347b4a-0189-4434-8d03-85627eb6d03b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678287562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.678287562
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.3687920109
Short name T320
Test name
Test status
Simulation time 215215743777 ps
CPU time 1485.32 seconds
Started Dec 24 01:26:08 PM PST 23
Finished Dec 24 01:50:55 PM PST 23
Peak memory 202044 kb
Host smart-badf7379-ddc1-4790-a328-6194c861a7f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687920109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.3687920109
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.3496787262
Short name T584
Test name
Test status
Simulation time 4072514670 ps
CPU time 85.29 seconds
Started Dec 24 01:26:07 PM PST 23
Finished Dec 24 01:27:34 PM PST 23
Peak memory 210396 kb
Host smart-52d7fe48-72b7-46e5-9dcd-a1171c9a1577
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496787262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.3496787262
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.3319803059
Short name T273
Test name
Test status
Simulation time 2954617281 ps
CPU time 48.36 seconds
Started Dec 24 01:26:12 PM PST 23
Finished Dec 24 01:27:02 PM PST 23
Peak memory 274984 kb
Host smart-85146b02-94ef-41e6-afab-70c600ef0e5c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319803059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.3319803059
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.849171414
Short name T820
Test name
Test status
Simulation time 9444469127 ps
CPU time 76.59 seconds
Started Dec 24 01:26:04 PM PST 23
Finished Dec 24 01:27:22 PM PST 23
Peak memory 218508 kb
Host smart-63c7ebca-208b-483b-bda3-05a0e4b0fb00
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849171414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_mem_partial_access.849171414
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.633870638
Short name T691
Test name
Test status
Simulation time 21518016394 ps
CPU time 307.38 seconds
Started Dec 24 01:25:53 PM PST 23
Finished Dec 24 01:31:04 PM PST 23
Peak memory 202156 kb
Host smart-7299fc7c-a9ed-4243-9fbb-5fbffef5862f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633870638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl
_mem_walk.633870638
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.3733100363
Short name T490
Test name
Test status
Simulation time 24597491628 ps
CPU time 897.77 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:41:05 PM PST 23
Peak memory 378116 kb
Host smart-bd29e262-26f3-450f-9096-cafacddc69db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733100363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.3733100363
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.2796852516
Short name T635
Test name
Test status
Simulation time 17842184603 ps
CPU time 54.9 seconds
Started Dec 24 01:26:09 PM PST 23
Finished Dec 24 01:27:05 PM PST 23
Peak memory 306368 kb
Host smart-c39c68ac-f26f-4b49-851a-61ef68fc1535
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796852516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.2796852516
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2751361539
Short name T109
Test name
Test status
Simulation time 7950774374 ps
CPU time 515.44 seconds
Started Dec 24 01:26:07 PM PST 23
Finished Dec 24 01:34:45 PM PST 23
Peak memory 202068 kb
Host smart-38a6864a-ca06-4f22-92be-baaab961c143
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751361539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.2751361539
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.4128462551
Short name T425
Test name
Test status
Simulation time 717885988 ps
CPU time 13.43 seconds
Started Dec 24 01:26:06 PM PST 23
Finished Dec 24 01:26:22 PM PST 23
Peak memory 202372 kb
Host smart-b07a6860-1d46-4c67-89a1-94b43c137b82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128462551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.4128462551
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.1358136753
Short name T672
Test name
Test status
Simulation time 10713632118 ps
CPU time 925.16 seconds
Started Dec 24 01:26:11 PM PST 23
Finished Dec 24 01:41:38 PM PST 23
Peak memory 381120 kb
Host smart-7db76d57-b4d5-4ba1-b872-e1c405e12c6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358136753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1358136753
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.1884539343
Short name T382
Test name
Test status
Simulation time 1093764704 ps
CPU time 33.08 seconds
Started Dec 24 01:26:08 PM PST 23
Finished Dec 24 01:26:43 PM PST 23
Peak memory 268628 kb
Host smart-4c0a9cef-f0fc-411e-9585-938d31f333a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884539343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.1884539343
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4029981212
Short name T890
Test name
Test status
Simulation time 278252062 ps
CPU time 2606.13 seconds
Started Dec 24 01:25:53 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 422284 kb
Host smart-01e6fc81-539b-434c-8304-20f49d8ee1ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4029981212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.4029981212
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1935091190
Short name T472
Test name
Test status
Simulation time 12464347201 ps
CPU time 239.82 seconds
Started Dec 24 01:26:11 PM PST 23
Finished Dec 24 01:30:13 PM PST 23
Peak memory 202184 kb
Host smart-4045b46b-554f-4af2-96de-239c6e84b49e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935091190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.1935091190
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2622969456
Short name T146
Test name
Test status
Simulation time 1004166684 ps
CPU time 106.69 seconds
Started Dec 24 01:26:09 PM PST 23
Finished Dec 24 01:27:57 PM PST 23
Peak memory 338068 kb
Host smart-56099f92-5d8b-4410-89b2-d67f1639fab8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622969456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.2622969456
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2088999178
Short name T40
Test name
Test status
Simulation time 9065503548 ps
CPU time 239.31 seconds
Started Dec 24 01:25:53 PM PST 23
Finished Dec 24 01:29:56 PM PST 23
Peak memory 325784 kb
Host smart-4e6be66f-6406-49d5-ae52-607c42bfd8fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088999178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.2088999178
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.35586680
Short name T265
Test name
Test status
Simulation time 37718350 ps
CPU time 0.62 seconds
Started Dec 24 01:26:03 PM PST 23
Finished Dec 24 01:26:05 PM PST 23
Peak memory 201856 kb
Host smart-c1ea8f5d-a732-4d95-8152-7d98167efaa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35586680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_alert_test.35586680
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.2039202370
Short name T700
Test name
Test status
Simulation time 693970161100 ps
CPU time 750.02 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:38:26 PM PST 23
Peak memory 202036 kb
Host smart-cb208df9-ec13-4c91-a1e2-56bdc76ee083
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039202370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.2039202370
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.169222321
Short name T753
Test name
Test status
Simulation time 150808508313 ps
CPU time 1733.38 seconds
Started Dec 24 01:25:53 PM PST 23
Finished Dec 24 01:54:50 PM PST 23
Peak memory 377856 kb
Host smart-ed89b055-6214-4476-bdf5-d23e63c1bca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169222321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executabl
e.169222321
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.519792092
Short name T560
Test name
Test status
Simulation time 13850119068 ps
CPU time 38.37 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:26:34 PM PST 23
Peak memory 251144 kb
Host smart-eb7dcf96-882b-43a0-806c-1697fa9d3824
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519792092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.sram_ctrl_max_throughput.519792092
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.136412677
Short name T695
Test name
Test status
Simulation time 962819222 ps
CPU time 76.77 seconds
Started Dec 24 01:25:55 PM PST 23
Finished Dec 24 01:27:14 PM PST 23
Peak memory 211128 kb
Host smart-07ad47d3-be8d-47e3-956e-38207d93b2ef
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136412677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_mem_partial_access.136412677
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.3470404395
Short name T825
Test name
Test status
Simulation time 2025876141 ps
CPU time 118.33 seconds
Started Dec 24 01:26:15 PM PST 23
Finished Dec 24 01:28:15 PM PST 23
Peak memory 201320 kb
Host smart-c13a1a36-0cfb-4909-8563-2af275baf647
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470404395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.3470404395
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.4268138246
Short name T679
Test name
Test status
Simulation time 8068584538 ps
CPU time 797.3 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:39:24 PM PST 23
Peak memory 355552 kb
Host smart-08c66ac1-6876-4278-ad52-bf886b2ae0cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268138246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.4268138246
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.3839733680
Short name T412
Test name
Test status
Simulation time 3123359370 ps
CPU time 65.25 seconds
Started Dec 24 01:25:51 PM PST 23
Finished Dec 24 01:26:59 PM PST 23
Peak memory 320700 kb
Host smart-bddefed2-2cf5-4874-a1c9-bab2ef66a582
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839733680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.3839733680
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3554393162
Short name T599
Test name
Test status
Simulation time 14770374993 ps
CPU time 318.04 seconds
Started Dec 24 01:25:49 PM PST 23
Finished Dec 24 01:31:11 PM PST 23
Peak memory 202064 kb
Host smart-81acdb61-ab72-44cd-a4c1-ca28c36fed6c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554393162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.3554393162
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.2159440376
Short name T947
Test name
Test status
Simulation time 361594090 ps
CPU time 5.47 seconds
Started Dec 24 01:25:53 PM PST 23
Finished Dec 24 01:26:02 PM PST 23
Peak memory 202372 kb
Host smart-795435d5-047d-4a3b-91d3-34c3e6fc3ff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159440376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.2159440376
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.4114505177
Short name T698
Test name
Test status
Simulation time 29498226335 ps
CPU time 1335.58 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:48:12 PM PST 23
Peak memory 382184 kb
Host smart-a3aa1fc8-e3c1-485a-81ba-340760a81f14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114505177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.4114505177
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.3516748828
Short name T4
Test name
Test status
Simulation time 4984945455 ps
CPU time 37.67 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:26:34 PM PST 23
Peak memory 249208 kb
Host smart-2ef22041-67c2-4744-8f6a-4aded373dca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516748828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3516748828
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.3001317703
Short name T902
Test name
Test status
Simulation time 183554634941 ps
CPU time 4824.34 seconds
Started Dec 24 01:26:06 PM PST 23
Finished Dec 24 02:46:33 PM PST 23
Peak memory 381080 kb
Host smart-932a0b94-a051-43b6-a592-c18d36b8ad93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001317703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.3001317703
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.354321476
Short name T376
Test name
Test status
Simulation time 2928328403 ps
CPU time 5970.34 seconds
Started Dec 24 01:26:04 PM PST 23
Finished Dec 24 03:05:37 PM PST 23
Peak memory 698720 kb
Host smart-b7655882-d089-428d-98f2-c4cfffd2ec16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=354321476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.354321476
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3596647554
Short name T228
Test name
Test status
Simulation time 14569017081 ps
CPU time 304.14 seconds
Started Dec 24 01:25:52 PM PST 23
Finished Dec 24 01:31:00 PM PST 23
Peak memory 202100 kb
Host smart-9e1e3c21-ab08-4c05-a50f-f2eeb0bafff5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596647554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.3596647554
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2200968601
Short name T663
Test name
Test status
Simulation time 2980278490 ps
CPU time 72.37 seconds
Started Dec 24 01:25:53 PM PST 23
Finished Dec 24 01:27:09 PM PST 23
Peak memory 318784 kb
Host smart-b364412d-9e37-4c72-af3c-d322c99949a6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200968601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2200968601
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.709725063
Short name T943
Test name
Test status
Simulation time 13196136960 ps
CPU time 1658.32 seconds
Started Dec 24 01:26:09 PM PST 23
Finished Dec 24 01:53:49 PM PST 23
Peak memory 377896 kb
Host smart-f376e3bb-9524-453f-b799-b3357d427695
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709725063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.sram_ctrl_access_during_key_req.709725063
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.879695275
Short name T268
Test name
Test status
Simulation time 15334827 ps
CPU time 0.68 seconds
Started Dec 24 01:26:15 PM PST 23
Finished Dec 24 01:26:17 PM PST 23
Peak memory 200640 kb
Host smart-edf1a9a3-4a20-4597-a0e4-2127cbcbfff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879695275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.879695275
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.1492735783
Short name T428
Test name
Test status
Simulation time 101294092995 ps
CPU time 2220.22 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 02:03:07 PM PST 23
Peak memory 202160 kb
Host smart-0f431428-f803-4299-b0f9-8cd6350f57c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492735783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.1492735783
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.3818410735
Short name T558
Test name
Test status
Simulation time 3156238179 ps
CPU time 214.01 seconds
Started Dec 24 01:26:07 PM PST 23
Finished Dec 24 01:29:43 PM PST 23
Peak memory 353500 kb
Host smart-296eb1a9-6324-425a-81e5-72bb8a2ea2f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818410735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.3818410735
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.1573225115
Short name T749
Test name
Test status
Simulation time 270865234277 ps
CPU time 162.95 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:28:50 PM PST 23
Peak memory 210300 kb
Host smart-2201b6df-ab2f-4ca3-bac2-b016097f9df8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573225115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.1573225115
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.660007455
Short name T329
Test name
Test status
Simulation time 1915395692 ps
CPU time 26.34 seconds
Started Dec 24 01:26:15 PM PST 23
Finished Dec 24 01:26:43 PM PST 23
Peak memory 210300 kb
Host smart-7e705685-b45d-40fc-88c2-2ed260313e91
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660007455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.sram_ctrl_max_throughput.660007455
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.697599579
Short name T528
Test name
Test status
Simulation time 20340639475 ps
CPU time 161.96 seconds
Started Dec 24 01:26:11 PM PST 23
Finished Dec 24 01:28:55 PM PST 23
Peak memory 213648 kb
Host smart-413144c9-11e0-43e3-9fa5-b595ec94d417
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697599579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.sram_ctrl_mem_partial_access.697599579
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.2905192196
Short name T314
Test name
Test status
Simulation time 14334867022 ps
CPU time 296.89 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:31:04 PM PST 23
Peak memory 202172 kb
Host smart-b8a903cc-ab97-4dd1-a266-bd3e7676e1ec
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905192196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.2905192196
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.926654315
Short name T448
Test name
Test status
Simulation time 5962830634 ps
CPU time 395.05 seconds
Started Dec 24 01:26:04 PM PST 23
Finished Dec 24 01:32:40 PM PST 23
Peak memory 353664 kb
Host smart-e157f17e-1b5e-461f-bbbf-33bbf0086672
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926654315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multip
le_keys.926654315
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.3181619584
Short name T736
Test name
Test status
Simulation time 1727064820 ps
CPU time 30.41 seconds
Started Dec 24 01:26:06 PM PST 23
Finished Dec 24 01:26:39 PM PST 23
Peak memory 202036 kb
Host smart-54f07873-a96d-4af8-a9a9-0533ba93daa3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181619584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.3181619584
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2383800020
Short name T630
Test name
Test status
Simulation time 14334255449 ps
CPU time 326.59 seconds
Started Dec 24 01:26:12 PM PST 23
Finished Dec 24 01:31:40 PM PST 23
Peak memory 202168 kb
Host smart-87e38980-338b-4249-a3fb-38ce22fda87d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383800020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.2383800020
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.404486660
Short name T580
Test name
Test status
Simulation time 362392733 ps
CPU time 6.77 seconds
Started Dec 24 01:26:04 PM PST 23
Finished Dec 24 01:26:13 PM PST 23
Peak memory 202420 kb
Host smart-eaf5f7a2-8e9a-4fdc-8c04-ef425fc1c583
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404486660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.404486660
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.32561341
Short name T917
Test name
Test status
Simulation time 36369004351 ps
CPU time 1176.99 seconds
Started Dec 24 01:26:13 PM PST 23
Finished Dec 24 01:45:52 PM PST 23
Peak memory 376980 kb
Host smart-cafc8779-dfae-4d8a-a545-bc6d238c9c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32561341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.32561341
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.988544268
Short name T614
Test name
Test status
Simulation time 2509406774 ps
CPU time 31.33 seconds
Started Dec 24 01:26:04 PM PST 23
Finished Dec 24 01:26:36 PM PST 23
Peak memory 216968 kb
Host smart-5fda4852-b8db-4bf4-800c-e6af2edd1979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988544268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.988544268
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.4211210094
Short name T962
Test name
Test status
Simulation time 192486300104 ps
CPU time 5734.1 seconds
Started Dec 24 01:26:06 PM PST 23
Finished Dec 24 03:01:43 PM PST 23
Peak memory 379028 kb
Host smart-c72512f3-aa6e-40d6-b32c-0ad80a7ff619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211210094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.4211210094
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3132682806
Short name T513
Test name
Test status
Simulation time 8768977218 ps
CPU time 5464.02 seconds
Started Dec 24 01:26:04 PM PST 23
Finished Dec 24 02:57:10 PM PST 23
Peak memory 469224 kb
Host smart-e3681c02-73f8-4f5f-b941-071220afd9f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3132682806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3132682806
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2621369024
Short name T306
Test name
Test status
Simulation time 4309926157 ps
CPU time 205.54 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:29:32 PM PST 23
Peak memory 202168 kb
Host smart-27cd2580-0e77-4e03-8fcc-b9b71a451ebf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621369024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.2621369024
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4095931564
Short name T149
Test name
Test status
Simulation time 714045541 ps
CPU time 28.41 seconds
Started Dec 24 01:26:15 PM PST 23
Finished Dec 24 01:26:45 PM PST 23
Peak memory 218428 kb
Host smart-afd73ad9-bb19-4062-9823-5a1cea1763ed
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095931564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.4095931564
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2518096690
Short name T520
Test name
Test status
Simulation time 11335438606 ps
CPU time 2100.19 seconds
Started Dec 24 01:26:06 PM PST 23
Finished Dec 24 02:01:08 PM PST 23
Peak memory 380036 kb
Host smart-35a7cc98-2acd-48e1-ae36-388191e8ffb5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518096690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.2518096690
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.8287983
Short name T292
Test name
Test status
Simulation time 52072741 ps
CPU time 0.63 seconds
Started Dec 24 01:26:34 PM PST 23
Finished Dec 24 01:26:37 PM PST 23
Peak memory 201852 kb
Host smart-9a79e163-a411-4f16-9fa7-64c9483dcad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8287983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_alert_test.8287983
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.317603888
Short name T252
Test name
Test status
Simulation time 26561739926 ps
CPU time 1940.96 seconds
Started Dec 24 01:26:06 PM PST 23
Finished Dec 24 01:58:30 PM PST 23
Peak memory 202136 kb
Host smart-916686df-a229-4f4f-b639-8ede9a3505fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317603888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.
317603888
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.1123122602
Short name T400
Test name
Test status
Simulation time 8023233015 ps
CPU time 166.69 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:28:53 PM PST 23
Peak memory 210300 kb
Host smart-b92fc71f-8ebf-4306-ab24-1faf96af0b18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123122602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.1123122602
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.1908668830
Short name T344
Test name
Test status
Simulation time 3157158737 ps
CPU time 77.68 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:27:25 PM PST 23
Peak memory 309984 kb
Host smart-8486e1e0-5880-4a29-95ef-c1a28c66789c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908668830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.1908668830
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.4103658648
Short name T933
Test name
Test status
Simulation time 8664957756 ps
CPU time 83.84 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:27:30 PM PST 23
Peak memory 211844 kb
Host smart-e695d020-41da-4e53-a55e-b04ceb518f52
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103658648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.4103658648
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.1966471229
Short name T242
Test name
Test status
Simulation time 7670676284 ps
CPU time 149.61 seconds
Started Dec 24 01:26:10 PM PST 23
Finished Dec 24 01:28:42 PM PST 23
Peak memory 202264 kb
Host smart-9761431c-8842-452f-bd1c-8deb2bca04af
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966471229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.1966471229
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.3580305444
Short name T354
Test name
Test status
Simulation time 42887354474 ps
CPU time 507.04 seconds
Started Dec 24 01:26:07 PM PST 23
Finished Dec 24 01:34:36 PM PST 23
Peak memory 373948 kb
Host smart-397741ad-30ad-411f-bafc-5e4ef0ee0022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580305444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.3580305444
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.2660852887
Short name T623
Test name
Test status
Simulation time 528126631 ps
CPU time 154.24 seconds
Started Dec 24 01:26:11 PM PST 23
Finished Dec 24 01:28:47 PM PST 23
Peak memory 364616 kb
Host smart-7caf0dce-944c-445d-870c-c80287abad6a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660852887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.2660852887
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2758293645
Short name T316
Test name
Test status
Simulation time 14647235082 ps
CPU time 428.97 seconds
Started Dec 24 01:26:04 PM PST 23
Finished Dec 24 01:33:15 PM PST 23
Peak memory 202168 kb
Host smart-0d6e0a43-1a89-47f5-975c-f093ebf863e9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758293645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.2758293645
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.832969680
Short name T282
Test name
Test status
Simulation time 348757234 ps
CPU time 5.24 seconds
Started Dec 24 01:26:05 PM PST 23
Finished Dec 24 01:26:13 PM PST 23
Peak memory 202444 kb
Host smart-c2daea6f-3fdd-40b8-904c-7976af704019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832969680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.832969680
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.2023758764
Short name T755
Test name
Test status
Simulation time 2901665492 ps
CPU time 979.21 seconds
Started Dec 24 01:26:04 PM PST 23
Finished Dec 24 01:42:24 PM PST 23
Peak memory 375040 kb
Host smart-89dca421-5fe9-417b-8dcf-175de7d7cee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023758764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2023758764
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.47417337
Short name T845
Test name
Test status
Simulation time 807844742 ps
CPU time 180.02 seconds
Started Dec 24 01:26:09 PM PST 23
Finished Dec 24 01:29:11 PM PST 23
Peak memory 375036 kb
Host smart-1fc6085b-a9b2-4569-b733-0b7430407b78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47417337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.47417337
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.2486950309
Short name T664
Test name
Test status
Simulation time 200738029924 ps
CPU time 1963.57 seconds
Started Dec 24 01:26:06 PM PST 23
Finished Dec 24 01:58:52 PM PST 23
Peak memory 379000 kb
Host smart-9c659bb3-3e31-4b5e-98f2-6c53911fdd10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486950309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.2486950309
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2141320308
Short name T550
Test name
Test status
Simulation time 1972685804 ps
CPU time 2088.59 seconds
Started Dec 24 01:26:09 PM PST 23
Finished Dec 24 02:00:59 PM PST 23
Peak memory 519336 kb
Host smart-77f8a49a-eb52-4b19-9baf-13a375bdffc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2141320308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2141320308
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.279336761
Short name T815
Test name
Test status
Simulation time 19000270692 ps
CPU time 341.51 seconds
Started Dec 24 01:26:11 PM PST 23
Finished Dec 24 01:31:54 PM PST 23
Peak memory 202160 kb
Host smart-afb0ff6c-0e53-4dca-8c20-e343950dc5ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279336761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_stress_pipeline.279336761
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2591010079
Short name T226
Test name
Test status
Simulation time 1695304818 ps
CPU time 125.94 seconds
Started Dec 24 01:26:09 PM PST 23
Finished Dec 24 01:28:17 PM PST 23
Peak memory 335416 kb
Host smart-1c2a01b6-3c17-4d45-a5de-b84ec577464b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591010079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2591010079
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3711989242
Short name T21
Test name
Test status
Simulation time 28682175710 ps
CPU time 1034.96 seconds
Started Dec 24 01:26:38 PM PST 23
Finished Dec 24 01:43:54 PM PST 23
Peak memory 380048 kb
Host smart-cab5e3f7-08ed-4ce4-8dbf-b59727849ea7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711989242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.3711989242
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.1203421987
Short name T368
Test name
Test status
Simulation time 52276773 ps
CPU time 0.69 seconds
Started Dec 24 01:26:32 PM PST 23
Finished Dec 24 01:26:34 PM PST 23
Peak memory 201872 kb
Host smart-f8aacf68-db51-4f5d-a08f-54c7dba40e6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203421987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.1203421987
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.3316577326
Short name T235
Test name
Test status
Simulation time 173772849749 ps
CPU time 1250.27 seconds
Started Dec 24 01:26:31 PM PST 23
Finished Dec 24 01:47:23 PM PST 23
Peak memory 202064 kb
Host smart-47c12d65-d2cf-456d-afc8-491c30e58f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316577326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.3316577326
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.2464623086
Short name T334
Test name
Test status
Simulation time 3432259165 ps
CPU time 213.07 seconds
Started Dec 24 01:26:34 PM PST 23
Finished Dec 24 01:30:09 PM PST 23
Peak memory 332856 kb
Host smart-24cbf63e-b996-495d-8b94-be39738d5871
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464623086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.2464623086
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.298140950
Short name T455
Test name
Test status
Simulation time 29319180758 ps
CPU time 138.41 seconds
Started Dec 24 01:26:33 PM PST 23
Finished Dec 24 01:28:52 PM PST 23
Peak memory 210380 kb
Host smart-b1d3bd48-178e-4ec5-b119-549497e97d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298140950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_esc
alation.298140950
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.143679522
Short name T713
Test name
Test status
Simulation time 713136936 ps
CPU time 49.3 seconds
Started Dec 24 01:26:32 PM PST 23
Finished Dec 24 01:27:22 PM PST 23
Peak memory 274668 kb
Host smart-e28978e0-2e13-4c54-8a0c-44517016b6af
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143679522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.sram_ctrl_max_throughput.143679522
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2282414565
Short name T849
Test name
Test status
Simulation time 3159489464 ps
CPU time 132.41 seconds
Started Dec 24 01:26:33 PM PST 23
Finished Dec 24 01:28:46 PM PST 23
Peak memory 211168 kb
Host smart-0e36bb2e-fef5-48a0-a751-85d8e40245bc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282414565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.2282414565
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.3047660845
Short name T507
Test name
Test status
Simulation time 28705987249 ps
CPU time 303.07 seconds
Started Dec 24 01:26:34 PM PST 23
Finished Dec 24 01:31:39 PM PST 23
Peak memory 202180 kb
Host smart-db3c774f-d752-412e-99f5-412a18a1b397
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047660845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.3047660845
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.4232546821
Short name T589
Test name
Test status
Simulation time 21450782735 ps
CPU time 590.13 seconds
Started Dec 24 01:26:33 PM PST 23
Finished Dec 24 01:36:24 PM PST 23
Peak memory 379140 kb
Host smart-d0d06798-535d-4c75-874d-476576a0f0cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232546821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.4232546821
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.3445208519
Short name T759
Test name
Test status
Simulation time 1652206056 ps
CPU time 124.94 seconds
Started Dec 24 01:26:32 PM PST 23
Finished Dec 24 01:28:38 PM PST 23
Peak memory 350224 kb
Host smart-d122072c-dfd1-44c1-a76d-586bad863cd0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445208519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.3445208519
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3970541942
Short name T136
Test name
Test status
Simulation time 27829008287 ps
CPU time 328.58 seconds
Started Dec 24 01:26:34 PM PST 23
Finished Dec 24 01:32:04 PM PST 23
Peak memory 202168 kb
Host smart-eb375de2-4b6e-49e1-bce9-d33c61f1ae3b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970541942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.3970541942
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.2916428117
Short name T33
Test name
Test status
Simulation time 2275345810 ps
CPU time 13.53 seconds
Started Dec 24 01:26:33 PM PST 23
Finished Dec 24 01:26:48 PM PST 23
Peak memory 202400 kb
Host smart-df7e210f-75dc-4488-b8cd-19a43dbb23fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916428117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2916428117
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.4237952215
Short name T438
Test name
Test status
Simulation time 50181757566 ps
CPU time 1956.98 seconds
Started Dec 24 01:26:32 PM PST 23
Finished Dec 24 01:59:10 PM PST 23
Peak memory 380116 kb
Host smart-f7ff441b-1824-43d8-be13-592eea623408
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237952215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.4237952215
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.1579433227
Short name T555
Test name
Test status
Simulation time 2515947874 ps
CPU time 13.17 seconds
Started Dec 24 01:26:33 PM PST 23
Finished Dec 24 01:26:47 PM PST 23
Peak memory 202064 kb
Host smart-37986028-763d-4991-b262-8449fdcca550
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579433227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1579433227
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.3996056047
Short name T348
Test name
Test status
Simulation time 28524304115 ps
CPU time 4447.88 seconds
Started Dec 24 01:26:31 PM PST 23
Finished Dec 24 02:40:40 PM PST 23
Peak memory 381140 kb
Host smart-b618fd46-c488-41d6-9fd9-6a4561ce8f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996056047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.3996056047
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.534886550
Short name T27
Test name
Test status
Simulation time 10072209171 ps
CPU time 5339.63 seconds
Started Dec 24 01:26:31 PM PST 23
Finished Dec 24 02:55:32 PM PST 23
Peak memory 636068 kb
Host smart-bb608730-ae75-4748-9019-86f810602564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=534886550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.534886550
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1671417883
Short name T808
Test name
Test status
Simulation time 2843349500 ps
CPU time 223.75 seconds
Started Dec 24 01:26:40 PM PST 23
Finished Dec 24 01:30:25 PM PST 23
Peak memory 202156 kb
Host smart-d887692b-3a21-421e-9126-7e30df07e529
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671417883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.1671417883
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.594408416
Short name T383
Test name
Test status
Simulation time 763666628 ps
CPU time 100.68 seconds
Started Dec 24 01:26:33 PM PST 23
Finished Dec 24 01:28:16 PM PST 23
Peak memory 331836 kb
Host smart-0cac767c-7f36-445a-b6d9-14a6db89dcf3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594408416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_throughput_w_partial_write.594408416
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3894358414
Short name T547
Test name
Test status
Simulation time 43739500841 ps
CPU time 875.29 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:36:43 PM PST 23
Peak memory 379844 kb
Host smart-f0594a79-c7db-4771-a23e-37ec3f122c5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894358414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.3894358414
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.3022215030
Short name T583
Test name
Test status
Simulation time 14069282 ps
CPU time 0.68 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:22:09 PM PST 23
Peak memory 201584 kb
Host smart-a2e8c2fd-40b6-4d83-9005-ce4b959a73eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022215030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.3022215030
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.1597221082
Short name T830
Test name
Test status
Simulation time 17392485150 ps
CPU time 1229.71 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:42:33 PM PST 23
Peak memory 202148 kb
Host smart-0d86d76b-9dd1-48ab-98dc-a59abecc787c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597221082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
1597221082
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.1635679833
Short name T588
Test name
Test status
Simulation time 11455678637 ps
CPU time 48.63 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:22:56 PM PST 23
Peak memory 210580 kb
Host smart-a7f0ee7b-5c95-4358-a530-4d1e72789470
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635679833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.1635679833
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.1557585583
Short name T281
Test name
Test status
Simulation time 731661671 ps
CPU time 69.17 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:23:13 PM PST 23
Peak memory 290880 kb
Host smart-4cdd5e45-5ae0-43e6-8a49-b9c4624b76c8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557585583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.1557585583
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3558702514
Short name T570
Test name
Test status
Simulation time 30975210100 ps
CPU time 145.41 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:24:33 PM PST 23
Peak memory 218508 kb
Host smart-384fa111-fbbc-4cf5-a73a-2c418793c2bf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558702514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.3558702514
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.1182082196
Short name T387
Test name
Test status
Simulation time 65654232954 ps
CPU time 249.41 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:26:18 PM PST 23
Peak memory 202068 kb
Host smart-0dbecd5f-b0f9-4e23-b9de-747e257615c5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182082196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.1182082196
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.3636008709
Short name T143
Test name
Test status
Simulation time 7250883995 ps
CPU time 1196.85 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:42:05 PM PST 23
Peak memory 380032 kb
Host smart-6447a980-38da-487d-861b-fef8435035b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636008709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.3636008709
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.3843217628
Short name T374
Test name
Test status
Simulation time 15654899737 ps
CPU time 77.12 seconds
Started Dec 24 01:22:03 PM PST 23
Finished Dec 24 01:23:22 PM PST 23
Peak memory 310980 kb
Host smart-cb70cf2f-c6ac-4bd1-9ef1-7bf9bfc75307
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843217628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.3843217628
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1979099070
Short name T369
Test name
Test status
Simulation time 48718682639 ps
CPU time 327.62 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:27:34 PM PST 23
Peak memory 202072 kb
Host smart-609e78ef-5724-4266-9dc1-1c4da5c57d5b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979099070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.1979099070
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.2134118224
Short name T309
Test name
Test status
Simulation time 365030827 ps
CPU time 5.67 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:22:12 PM PST 23
Peak memory 202376 kb
Host smart-40cc9749-51e8-48b3-b899-cd2be9c342ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134118224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2134118224
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.2886200976
Short name T536
Test name
Test status
Simulation time 3069175693 ps
CPU time 504.32 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:30:30 PM PST 23
Peak memory 352404 kb
Host smart-d428426f-9cba-4c84-9261-1ef6f16c7b21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886200976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.2886200976
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.4208280415
Short name T26
Test name
Test status
Simulation time 487973018 ps
CPU time 2.24 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:22:10 PM PST 23
Peak memory 220896 kb
Host smart-0067d403-38dd-4eea-8113-836af5508833
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208280415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.4208280415
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.1946937452
Short name T800
Test name
Test status
Simulation time 648799016 ps
CPU time 27.48 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 01:22:33 PM PST 23
Peak memory 271152 kb
Host smart-98b97218-5c1e-4a66-ace5-2845d84081ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946937452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1946937452
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.3274672355
Short name T453
Test name
Test status
Simulation time 142460214333 ps
CPU time 3946.4 seconds
Started Dec 24 01:22:04 PM PST 23
Finished Dec 24 02:27:53 PM PST 23
Peak memory 380996 kb
Host smart-7b430e70-e296-48f8-9c19-2886ff264391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274672355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.3274672355
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.137609169
Short name T285
Test name
Test status
Simulation time 2277355395 ps
CPU time 4340.15 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 02:34:28 PM PST 23
Peak memory 414800 kb
Host smart-0a71f524-6b19-43ad-84fd-fcfaeaecc839
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=137609169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.137609169
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2309356728
Short name T101
Test name
Test status
Simulation time 9577995663 ps
CPU time 381.7 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:28:29 PM PST 23
Peak memory 201988 kb
Host smart-e6ac7988-5baa-431e-b6e1-41f298eb1f18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309356728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.2309356728
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.256969791
Short name T148
Test name
Test status
Simulation time 1754914333 ps
CPU time 47.88 seconds
Started Dec 24 01:22:10 PM PST 23
Finished Dec 24 01:23:04 PM PST 23
Peak memory 275568 kb
Host smart-bf201f5c-24d1-41b4-8f79-866cf527a37e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256969791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_throughput_w_partial_write.256969791
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1632515105
Short name T290
Test name
Test status
Simulation time 6717557667 ps
CPU time 1055.96 seconds
Started Dec 24 01:26:48 PM PST 23
Finished Dec 24 01:44:27 PM PST 23
Peak memory 377024 kb
Host smart-6301e944-3c43-400d-95f8-43ceb97982e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632515105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.1632515105
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.38506795
Short name T957
Test name
Test status
Simulation time 33808438 ps
CPU time 0.61 seconds
Started Dec 24 01:26:49 PM PST 23
Finished Dec 24 01:26:52 PM PST 23
Peak memory 201280 kb
Host smart-29e90655-45f8-479d-b79e-e188707ded70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38506795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_alert_test.38506795
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.3173745149
Short name T103
Test name
Test status
Simulation time 39355943378 ps
CPU time 836.56 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 202160 kb
Host smart-75da43af-56f6-4fe2-b6a4-65ecfd190680
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173745149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.3173745149
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.1442616401
Short name T776
Test name
Test status
Simulation time 72986445191 ps
CPU time 1652.94 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:54:23 PM PST 23
Peak memory 375052 kb
Host smart-106765c8-9976-4e24-bb18-6beb152cc88d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442616401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.1442616401
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.3194343517
Short name T884
Test name
Test status
Simulation time 64397798861 ps
CPU time 80.9 seconds
Started Dec 24 01:26:46 PM PST 23
Finished Dec 24 01:28:10 PM PST 23
Peak memory 210380 kb
Host smart-7fd1a087-ef44-4c9c-a90a-3ed4b0716c97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194343517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.3194343517
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.3555925295
Short name T327
Test name
Test status
Simulation time 740170324 ps
CPU time 63.73 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 01:27:51 PM PST 23
Peak memory 304420 kb
Host smart-8b893b71-9b21-4e9a-83af-a66ab9520e7c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555925295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.3555925295
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.9162455
Short name T17
Test name
Test status
Simulation time 6377202745 ps
CPU time 78.43 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:28:08 PM PST 23
Peak memory 211168 kb
Host smart-656b6487-7c26-42f8-b9d4-f74fab80bf96
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9162455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s
ram_ctrl_mem_partial_access.9162455
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.803431999
Short name T394
Test name
Test status
Simulation time 14346305540 ps
CPU time 298.83 seconds
Started Dec 24 01:26:51 PM PST 23
Finished Dec 24 01:31:51 PM PST 23
Peak memory 202092 kb
Host smart-67975e8b-3650-4dcd-ac74-0c358405f409
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803431999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl
_mem_walk.803431999
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.2546534626
Short name T610
Test name
Test status
Simulation time 1124499431 ps
CPU time 56.46 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:27:47 PM PST 23
Peak memory 202064 kb
Host smart-139a021f-58a6-486d-b570-e631bd3f0a91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546534626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.2546534626
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.2688269375
Short name T726
Test name
Test status
Simulation time 2055781821 ps
CPU time 20.06 seconds
Started Dec 24 01:26:46 PM PST 23
Finished Dec 24 01:27:09 PM PST 23
Peak memory 202076 kb
Host smart-d9346842-f24b-4e2e-a7a3-26680d68378b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688269375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.2688269375
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1009119161
Short name T779
Test name
Test status
Simulation time 23928142001 ps
CPU time 507.88 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 01:35:14 PM PST 23
Peak memory 202176 kb
Host smart-3dfb6d8a-dcdc-422b-b96e-894bdd4a35e5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009119161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.1009119161
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.3370763998
Short name T692
Test name
Test status
Simulation time 1411814687 ps
CPU time 14.58 seconds
Started Dec 24 01:26:58 PM PST 23
Finished Dec 24 01:27:14 PM PST 23
Peak memory 202340 kb
Host smart-f99936fb-2642-4643-bfd4-edccf7e69a02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370763998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3370763998
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.792933739
Short name T720
Test name
Test status
Simulation time 7485082961 ps
CPU time 383.16 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:33:13 PM PST 23
Peak memory 360456 kb
Host smart-de6f9bdd-cf24-4b6f-b5b3-7f4e65b1996e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792933739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.792933739
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.766146625
Short name T919
Test name
Test status
Simulation time 5184215264 ps
CPU time 21.27 seconds
Started Dec 24 01:26:32 PM PST 23
Finished Dec 24 01:26:55 PM PST 23
Peak memory 202052 kb
Host smart-e6f5be16-efd6-4218-aa7f-d94a0d5634bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766146625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.766146625
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.2305157346
Short name T632
Test name
Test status
Simulation time 657425819152 ps
CPU time 4906.42 seconds
Started Dec 24 01:26:51 PM PST 23
Finished Dec 24 02:48:39 PM PST 23
Peak memory 382056 kb
Host smart-92c7616c-a120-4e66-b62f-1124f1b530fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305157346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.sram_ctrl_stress_all.2305157346
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1554205247
Short name T717
Test name
Test status
Simulation time 2021083338 ps
CPU time 4271.6 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 02:38:03 PM PST 23
Peak memory 767988 kb
Host smart-1bf1d9ff-1225-4363-8562-7a861a2d5bd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1554205247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1554205247
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.378624850
Short name T967
Test name
Test status
Simulation time 20553042130 ps
CPU time 408.63 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:33:39 PM PST 23
Peak memory 202280 kb
Host smart-1f45ee83-5efa-446c-a384-70dda6324fd0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378624850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.sram_ctrl_stress_pipeline.378624850
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.525917245
Short name T640
Test name
Test status
Simulation time 785832385 ps
CPU time 82.84 seconds
Started Dec 24 01:26:48 PM PST 23
Finished Dec 24 01:28:14 PM PST 23
Peak memory 309452 kb
Host smart-9431df26-74a6-4d20-8c5b-3d2ec3534168
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525917245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_throughput_w_partial_write.525917245
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.4255554580
Short name T863
Test name
Test status
Simulation time 8620518532 ps
CPU time 866.37 seconds
Started Dec 24 01:26:57 PM PST 23
Finished Dec 24 01:41:24 PM PST 23
Peak memory 380052 kb
Host smart-974d4bd8-2554-4475-8abf-818acc63b196
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255554580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.4255554580
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.3350219578
Short name T431
Test name
Test status
Simulation time 23089053 ps
CPU time 0.68 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:26:50 PM PST 23
Peak memory 201852 kb
Host smart-b5f26079-a6a9-4108-b8d8-5347fcd88f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350219578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.3350219578
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.3430631209
Short name T343
Test name
Test status
Simulation time 33491653913 ps
CPU time 2387.18 seconds
Started Dec 24 01:26:49 PM PST 23
Finished Dec 24 02:06:39 PM PST 23
Peak memory 202196 kb
Host smart-3b58e00b-2aa9-4ed6-88ac-a66478972a24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430631209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.3430631209
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.2164687150
Short name T738
Test name
Test status
Simulation time 2977578307 ps
CPU time 53.65 seconds
Started Dec 24 01:26:58 PM PST 23
Finished Dec 24 01:27:53 PM PST 23
Peak memory 277880 kb
Host smart-9337bec3-7447-48ad-86ed-fe0374211362
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164687150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.2164687150
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3391767270
Short name T823
Test name
Test status
Simulation time 4370421706 ps
CPU time 143.34 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 01:29:10 PM PST 23
Peak memory 218508 kb
Host smart-c7b110fe-c35f-4384-8952-0af51fa5cb21
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391767270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.3391767270
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.1657275055
Short name T223
Test name
Test status
Simulation time 10328171893 ps
CPU time 153.28 seconds
Started Dec 24 01:26:48 PM PST 23
Finished Dec 24 01:29:25 PM PST 23
Peak memory 202116 kb
Host smart-caff87c6-5a1d-43ff-aadc-8fac0e95fec7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657275055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.1657275055
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.687623114
Short name T336
Test name
Test status
Simulation time 3961820426 ps
CPU time 1053.34 seconds
Started Dec 24 01:26:49 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 381196 kb
Host smart-2443e1eb-a4c8-428e-b0aa-facbde39cc1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687623114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multip
le_keys.687623114
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.3837282056
Short name T41
Test name
Test status
Simulation time 1396037200 ps
CPU time 16.73 seconds
Started Dec 24 01:27:00 PM PST 23
Finished Dec 24 01:27:18 PM PST 23
Peak memory 217232 kb
Host smart-af05b06b-2695-4d99-9e44-fc31e346f0c7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837282056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.3837282056
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.4094066942
Short name T722
Test name
Test status
Simulation time 95692068605 ps
CPU time 522.88 seconds
Started Dec 24 01:27:00 PM PST 23
Finished Dec 24 01:35:44 PM PST 23
Peak memory 202076 kb
Host smart-438c1de4-caed-4938-8da8-be0df9189d35
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094066942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.4094066942
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.2564193742
Short name T878
Test name
Test status
Simulation time 358585599 ps
CPU time 13.74 seconds
Started Dec 24 01:26:48 PM PST 23
Finished Dec 24 01:27:05 PM PST 23
Peak memory 202372 kb
Host smart-21c8a65f-2391-4780-b492-756479a35d9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564193742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2564193742
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.1379467693
Short name T134
Test name
Test status
Simulation time 31815966713 ps
CPU time 1722.14 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 01:55:29 PM PST 23
Peak memory 372972 kb
Host smart-b5bde3a5-a356-431b-b49a-113810aaa6c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379467693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1379467693
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.1708003409
Short name T515
Test name
Test status
Simulation time 750287048 ps
CPU time 29.17 seconds
Started Dec 24 01:27:00 PM PST 23
Finished Dec 24 01:27:31 PM PST 23
Peak memory 266280 kb
Host smart-acbdd0e4-9701-4e6b-890e-a52dc828e3d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708003409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1708003409
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.896179932
Short name T864
Test name
Test status
Simulation time 924760988848 ps
CPU time 6744.92 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 03:19:15 PM PST 23
Peak memory 380056 kb
Host smart-dc2af079-2809-40d5-8701-3ad5219d539c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896179932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_stress_all.896179932
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.185684430
Short name T575
Test name
Test status
Simulation time 400168897 ps
CPU time 4775.9 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 02:46:27 PM PST 23
Peak memory 448132 kb
Host smart-3fc60345-73d5-48fa-9f44-4a856fd9e19f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=185684430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.185684430
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.587124506
Short name T641
Test name
Test status
Simulation time 28434761500 ps
CPU time 164.24 seconds
Started Dec 24 01:26:59 PM PST 23
Finished Dec 24 01:29:45 PM PST 23
Peak memory 202160 kb
Host smart-7d52f75b-2a77-438e-b6f5-ade67d046c5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587124506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.sram_ctrl_stress_pipeline.587124506
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.168719130
Short name T916
Test name
Test status
Simulation time 15074723224 ps
CPU time 99.8 seconds
Started Dec 24 01:27:00 PM PST 23
Finished Dec 24 01:28:41 PM PST 23
Peak memory 328976 kb
Host smart-9d6d9824-4a68-4927-937b-062df5226b2c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168719130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_throughput_w_partial_write.168719130
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2410151991
Short name T787
Test name
Test status
Simulation time 32725460798 ps
CPU time 1722.38 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 01:55:30 PM PST 23
Peak memory 378984 kb
Host smart-a335ca6f-b217-4332-b3e9-1e48bcb57ea3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410151991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.2410151991
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.502743899
Short name T903
Test name
Test status
Simulation time 115467256 ps
CPU time 0.66 seconds
Started Dec 24 01:26:48 PM PST 23
Finished Dec 24 01:26:52 PM PST 23
Peak memory 201772 kb
Host smart-76c8fc54-8a4e-40ea-8c82-0ec3673c4c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502743899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.502743899
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.1420595026
Short name T293
Test name
Test status
Simulation time 70566138063 ps
CPU time 1595.12 seconds
Started Dec 24 01:26:46 PM PST 23
Finished Dec 24 01:53:24 PM PST 23
Peak memory 202048 kb
Host smart-1166c0dd-de1f-4797-89d8-eb071c830b56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420595026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.1420595026
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.570334241
Short name T737
Test name
Test status
Simulation time 101502828345 ps
CPU time 1794.69 seconds
Started Dec 24 01:26:49 PM PST 23
Finished Dec 24 01:56:46 PM PST 23
Peak memory 374948 kb
Host smart-44923fa3-e805-4cb6-aac1-52967f456d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570334241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executabl
e.570334241
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.1353339882
Short name T7
Test name
Test status
Simulation time 46010228309 ps
CPU time 132.01 seconds
Started Dec 24 01:26:51 PM PST 23
Finished Dec 24 01:29:05 PM PST 23
Peak memory 202060 kb
Host smart-54254d20-e811-4e11-9e12-90b96a697473
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353339882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.1353339882
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.705165129
Short name T510
Test name
Test status
Simulation time 3587379549 ps
CPU time 32.47 seconds
Started Dec 24 01:26:48 PM PST 23
Finished Dec 24 01:27:23 PM PST 23
Peak memory 225772 kb
Host smart-7ee7bc62-4bbd-4cce-9df5-b8aca886f2f0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705165129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.sram_ctrl_max_throughput.705165129
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1261605375
Short name T257
Test name
Test status
Simulation time 2429963257 ps
CPU time 75.76 seconds
Started Dec 24 01:26:56 PM PST 23
Finished Dec 24 01:28:13 PM PST 23
Peak memory 218472 kb
Host smart-d48aa912-15ac-439f-a4bf-f8313bed0568
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261605375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.1261605375
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.2906222222
Short name T949
Test name
Test status
Simulation time 40470058395 ps
CPU time 144.77 seconds
Started Dec 24 01:26:44 PM PST 23
Finished Dec 24 01:29:09 PM PST 23
Peak memory 202196 kb
Host smart-3b3514ee-644d-4238-9569-3a960c6f9487
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906222222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.2906222222
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.3391957164
Short name T970
Test name
Test status
Simulation time 5375664172 ps
CPU time 825.82 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 01:40:33 PM PST 23
Peak memory 380228 kb
Host smart-a1a3ef98-4b68-49a0-816f-31d860c0e5ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391957164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.3391957164
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.1317797053
Short name T526
Test name
Test status
Simulation time 465106510 ps
CPU time 8.25 seconds
Started Dec 24 01:26:46 PM PST 23
Finished Dec 24 01:26:56 PM PST 23
Peak memory 202080 kb
Host smart-dda6dd29-6ecd-4de5-80fa-f5023f397b20
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317797053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.1317797053
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1736429431
Short name T973
Test name
Test status
Simulation time 54404799718 ps
CPU time 331.83 seconds
Started Dec 24 01:26:46 PM PST 23
Finished Dec 24 01:32:20 PM PST 23
Peak memory 202080 kb
Host smart-0bf8222c-147b-4aa9-b85e-5f063e3a03d3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736429431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.1736429431
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.3475261475
Short name T913
Test name
Test status
Simulation time 1403201894 ps
CPU time 13.43 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 01:27:00 PM PST 23
Peak memory 202236 kb
Host smart-a41b7629-2120-439a-b9bf-3ba5c5c1c8e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475261475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3475261475
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.3915556384
Short name T470
Test name
Test status
Simulation time 2557045528 ps
CPU time 165.89 seconds
Started Dec 24 01:26:46 PM PST 23
Finished Dec 24 01:29:34 PM PST 23
Peak memory 325092 kb
Host smart-9ca41254-1e19-4bf0-b627-caf2fd59ebfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915556384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3915556384
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.2782549547
Short name T761
Test name
Test status
Simulation time 2010522923 ps
CPU time 14.12 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:27:05 PM PST 23
Peak memory 234884 kb
Host smart-18f37370-0b77-4028-b071-dab8bba5e48a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782549547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2782549547
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3631590035
Short name T578
Test name
Test status
Simulation time 5891862148 ps
CPU time 2914.2 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 02:15:22 PM PST 23
Peak memory 519332 kb
Host smart-32a6024a-c5d9-4b4d-9be9-6b0b35356270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3631590035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3631590035
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1764185072
Short name T733
Test name
Test status
Simulation time 23976599685 ps
CPU time 177.29 seconds
Started Dec 24 01:26:55 PM PST 23
Finished Dec 24 01:29:54 PM PST 23
Peak memory 202184 kb
Host smart-9ace5dd9-8965-4171-938e-b975070af798
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764185072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.1764185072
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2128604084
Short name T504
Test name
Test status
Simulation time 1394669084 ps
CPU time 32.38 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 01:27:19 PM PST 23
Peak memory 236916 kb
Host smart-3d186871-30f7-45fa-b579-d2ae1d4afb36
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128604084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2128604084
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2072390226
Short name T875
Test name
Test status
Simulation time 14305110783 ps
CPU time 1320.36 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:48:51 PM PST 23
Peak memory 370072 kb
Host smart-0e94c24b-748c-4ce7-8889-a872edbf0d76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072390226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.2072390226
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.2080556080
Short name T748
Test name
Test status
Simulation time 18770316 ps
CPU time 0.68 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 01:26:48 PM PST 23
Peak memory 201880 kb
Host smart-ddaa0a27-05f9-476a-88ea-9360f12507cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080556080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.2080556080
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.1674350861
Short name T556
Test name
Test status
Simulation time 8554436827 ps
CPU time 582.39 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:36:32 PM PST 23
Peak memory 202184 kb
Host smart-3d2c9f47-bd59-4f80-b45c-55e459b9c472
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674350861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.1674350861
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.1398721088
Short name T308
Test name
Test status
Simulation time 42777395289 ps
CPU time 677.24 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:38:08 PM PST 23
Peak memory 332928 kb
Host smart-c22c2825-a887-4d8a-9956-6fe7b8eb4daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398721088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.1398721088
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.884795195
Short name T389
Test name
Test status
Simulation time 747425516 ps
CPU time 92.68 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:28:23 PM PST 23
Peak memory 327960 kb
Host smart-d41726ba-3bb6-432b-9732-70a413d69e76
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884795195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.sram_ctrl_max_throughput.884795195
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2616090404
Short name T597
Test name
Test status
Simulation time 9204983892 ps
CPU time 151.98 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:29:22 PM PST 23
Peak memory 210936 kb
Host smart-e01e9d95-e7c2-446c-bf91-31f6186f9cee
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616090404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.2616090404
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.4087832688
Short name T372
Test name
Test status
Simulation time 3948190370 ps
CPU time 246.36 seconds
Started Dec 24 01:26:48 PM PST 23
Finished Dec 24 01:30:57 PM PST 23
Peak memory 202096 kb
Host smart-e9a1e3fe-7f84-48dd-b8fa-ddf27730e4c3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087832688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.4087832688
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.3322505075
Short name T45
Test name
Test status
Simulation time 18792852497 ps
CPU time 726.71 seconds
Started Dec 24 01:26:56 PM PST 23
Finished Dec 24 01:39:04 PM PST 23
Peak memory 379668 kb
Host smart-c18d44b9-44a0-4ae3-a563-28609762aa0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322505075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.3322505075
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.893335453
Short name T792
Test name
Test status
Simulation time 1333934782 ps
CPU time 26.06 seconds
Started Dec 24 01:26:48 PM PST 23
Finished Dec 24 01:27:17 PM PST 23
Peak memory 202080 kb
Host smart-97666584-146c-4c40-897f-d49851e3a540
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893335453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s
ram_ctrl_partial_access.893335453
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2032471612
Short name T728
Test name
Test status
Simulation time 24577054068 ps
CPU time 299.55 seconds
Started Dec 24 01:26:46 PM PST 23
Finished Dec 24 01:31:47 PM PST 23
Peak memory 202080 kb
Host smart-46d03a27-81cb-4ab9-bff9-c9f7877b1029
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032471612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.2032471612
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.1301396824
Short name T684
Test name
Test status
Simulation time 394266669 ps
CPU time 6.44 seconds
Started Dec 24 01:26:46 PM PST 23
Finished Dec 24 01:26:55 PM PST 23
Peak memory 202356 kb
Host smart-514fe50b-d68e-444d-8207-5535981d2308
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301396824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1301396824
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.2953394343
Short name T440
Test name
Test status
Simulation time 58538119081 ps
CPU time 1367.9 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:49:38 PM PST 23
Peak memory 373916 kb
Host smart-270f7cfc-5533-4f51-85ec-03f60235bc4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953394343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2953394343
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.2761101418
Short name T46
Test name
Test status
Simulation time 4180476785 ps
CPU time 23.4 seconds
Started Dec 24 01:26:45 PM PST 23
Finished Dec 24 01:27:11 PM PST 23
Peak memory 210348 kb
Host smart-91f1f508-1726-4198-86e9-b1a8fce160dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761101418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2761101418
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.869971113
Short name T805
Test name
Test status
Simulation time 729172230 ps
CPU time 3329.9 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 02:22:21 PM PST 23
Peak memory 786456 kb
Host smart-e38061a8-3830-4e8d-ba3c-bf7b508fb884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=869971113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.869971113
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3460077233
Short name T982
Test name
Test status
Simulation time 6510190356 ps
CPU time 260.6 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:31:11 PM PST 23
Peak memory 202144 kb
Host smart-56233be9-d135-4dc7-b47f-af7591725fed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460077233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.3460077233
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2697657731
Short name T667
Test name
Test status
Simulation time 1505663707 ps
CPU time 73.78 seconds
Started Dec 24 01:26:47 PM PST 23
Finished Dec 24 01:28:04 PM PST 23
Peak memory 306480 kb
Host smart-3e1b51ab-5a6d-4565-a9fb-54f098c2c999
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697657731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.2697657731
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2721570310
Short name T88
Test name
Test status
Simulation time 7177939975 ps
CPU time 1037.32 seconds
Started Dec 24 01:26:59 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 376008 kb
Host smart-f69e776a-689c-4d56-8448-123b32771bc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721570310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.2721570310
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.650949134
Short name T627
Test name
Test status
Simulation time 113830326 ps
CPU time 0.64 seconds
Started Dec 24 01:27:01 PM PST 23
Finished Dec 24 01:27:03 PM PST 23
Peak memory 201768 kb
Host smart-4e0d9387-36f2-4c09-8311-62fc5f866aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650949134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.650949134
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.2291472275
Short name T963
Test name
Test status
Simulation time 161010949832 ps
CPU time 2499.44 seconds
Started Dec 24 01:27:00 PM PST 23
Finished Dec 24 02:08:41 PM PST 23
Peak memory 202044 kb
Host smart-e8a04acb-c5c1-456a-bd38-3eb15daf4e89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291472275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.2291472275
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.3905943418
Short name T980
Test name
Test status
Simulation time 51685349637 ps
CPU time 447.51 seconds
Started Dec 24 01:26:58 PM PST 23
Finished Dec 24 01:34:27 PM PST 23
Peak memory 347304 kb
Host smart-43a3fd75-c1fb-4285-ba4b-55e4fa13364b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905943418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab
le.3905943418
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.3045867773
Short name T419
Test name
Test status
Simulation time 4158284653 ps
CPU time 44.95 seconds
Started Dec 24 01:26:58 PM PST 23
Finished Dec 24 01:27:44 PM PST 23
Peak memory 213688 kb
Host smart-f45f35d9-0f47-4333-9fd6-02f85b33592d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045867773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.3045867773
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.2250191218
Short name T519
Test name
Test status
Simulation time 755245171 ps
CPU time 106.13 seconds
Started Dec 24 01:27:01 PM PST 23
Finished Dec 24 01:28:49 PM PST 23
Peak memory 335092 kb
Host smart-2a152e3d-839e-4e8d-8a1c-259ac7e44607
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250191218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.2250191218
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2365477182
Short name T432
Test name
Test status
Simulation time 2548545511 ps
CPU time 82.11 seconds
Started Dec 24 01:27:01 PM PST 23
Finished Dec 24 01:28:24 PM PST 23
Peak memory 211320 kb
Host smart-6a6ba1c5-6ffb-4c8d-b22d-45f1327dea86
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365477182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.2365477182
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.1277461450
Short name T340
Test name
Test status
Simulation time 39396321811 ps
CPU time 268.68 seconds
Started Dec 24 01:27:02 PM PST 23
Finished Dec 24 01:31:32 PM PST 23
Peak memory 202124 kb
Host smart-85989d99-e4b3-4bea-87e3-c9e966119825
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277461450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.1277461450
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.4272453512
Short name T735
Test name
Test status
Simulation time 15528735025 ps
CPU time 1261.11 seconds
Started Dec 24 01:26:58 PM PST 23
Finished Dec 24 01:48:01 PM PST 23
Peak memory 377088 kb
Host smart-70393930-35db-47a0-b286-1f942395682d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272453512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.4272453512
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.1306773430
Short name T812
Test name
Test status
Simulation time 1788311035 ps
CPU time 33.64 seconds
Started Dec 24 01:26:59 PM PST 23
Finished Dec 24 01:27:34 PM PST 23
Peak memory 202092 kb
Host smart-be6fafd5-eb3d-4f8d-8176-e6faf471389e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306773430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.1306773430
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.467164705
Short name T388
Test name
Test status
Simulation time 65993739729 ps
CPU time 426.07 seconds
Started Dec 24 01:27:02 PM PST 23
Finished Dec 24 01:34:09 PM PST 23
Peak memory 202184 kb
Host smart-1fa9aa29-5802-4048-a929-a897603834d9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467164705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.sram_ctrl_partial_access_b2b.467164705
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.2601037996
Short name T491
Test name
Test status
Simulation time 345585949 ps
CPU time 6.67 seconds
Started Dec 24 01:26:57 PM PST 23
Finished Dec 24 01:27:05 PM PST 23
Peak memory 202372 kb
Host smart-da0f0a47-cff3-4eb1-92b8-17ae94479b5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601037996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2601037996
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.952072183
Short name T405
Test name
Test status
Simulation time 1568681578 ps
CPU time 213.62 seconds
Started Dec 24 01:27:00 PM PST 23
Finished Dec 24 01:30:35 PM PST 23
Peak memory 341220 kb
Host smart-11758d29-aa9a-42f7-9f06-480a6095c92a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952072183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.952072183
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.2202933524
Short name T436
Test name
Test status
Simulation time 678234048 ps
CPU time 11.95 seconds
Started Dec 24 01:27:01 PM PST 23
Finished Dec 24 01:27:14 PM PST 23
Peak memory 202000 kb
Host smart-6bfa537b-35b6-4a6b-bb6f-9fce1adc2fd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202933524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2202933524
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.1782869569
Short name T118
Test name
Test status
Simulation time 410176491320 ps
CPU time 8354.51 seconds
Started Dec 24 01:27:01 PM PST 23
Finished Dec 24 03:46:18 PM PST 23
Peak memory 382148 kb
Host smart-afadb06e-3a62-4825-9c11-67a8d0ba2e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782869569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.1782869569
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.518699579
Short name T972
Test name
Test status
Simulation time 1216418781 ps
CPU time 1660.59 seconds
Started Dec 24 01:27:01 PM PST 23
Finished Dec 24 01:54:43 PM PST 23
Peak memory 406304 kb
Host smart-6a880c8e-fecf-475e-93b6-cbb367b38746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=518699579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.518699579
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2613861475
Short name T287
Test name
Test status
Simulation time 3315552849 ps
CPU time 243.12 seconds
Started Dec 24 01:26:58 PM PST 23
Finished Dec 24 01:31:03 PM PST 23
Peak memory 202180 kb
Host smart-c6ee273b-c8da-47d0-97ca-a7a1d42bdbb4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613861475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.2613861475
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1170285821
Short name T307
Test name
Test status
Simulation time 870644227 ps
CPU time 171.51 seconds
Started Dec 24 01:26:58 PM PST 23
Finished Dec 24 01:29:51 PM PST 23
Peak memory 374904 kb
Host smart-3f4c61a1-b72e-49ee-a266-3d1723bf2c2c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170285821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1170285821
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3414706227
Short name T855
Test name
Test status
Simulation time 2738038340 ps
CPU time 223.72 seconds
Started Dec 24 01:27:00 PM PST 23
Finished Dec 24 01:30:45 PM PST 23
Peak memory 342416 kb
Host smart-28799ebb-e1b3-46a5-bcf5-2bd45f4efaa9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414706227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.3414706227
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.2367337310
Short name T723
Test name
Test status
Simulation time 29958472 ps
CPU time 0.62 seconds
Started Dec 24 01:27:06 PM PST 23
Finished Dec 24 01:27:07 PM PST 23
Peak memory 201876 kb
Host smart-85cc7ec2-8464-490b-a878-174f4fe65b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367337310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.2367337310
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.1711098483
Short name T130
Test name
Test status
Simulation time 10279885263 ps
CPU time 771.12 seconds
Started Dec 24 01:27:12 PM PST 23
Finished Dec 24 01:40:04 PM PST 23
Peak memory 375852 kb
Host smart-5206604c-9f64-4b57-81fe-81a17a71d3c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711098483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.1711098483
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.428821275
Short name T831
Test name
Test status
Simulation time 3987818285 ps
CPU time 134.64 seconds
Started Dec 24 01:27:01 PM PST 23
Finished Dec 24 01:29:17 PM PST 23
Peak memory 359632 kb
Host smart-e5d37f73-319e-4885-9086-cc25a9e0d6d5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428821275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.sram_ctrl_max_throughput.428821275
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3242054889
Short name T270
Test name
Test status
Simulation time 3930152769 ps
CPU time 78.47 seconds
Started Dec 24 01:27:08 PM PST 23
Finished Dec 24 01:28:27 PM PST 23
Peak memory 211056 kb
Host smart-08cdff7b-acd7-4bd4-babb-ddc23d6b6c40
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242054889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.3242054889
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.744860403
Short name T346
Test name
Test status
Simulation time 106079188496 ps
CPU time 279.47 seconds
Started Dec 24 01:27:13 PM PST 23
Finished Dec 24 01:31:53 PM PST 23
Peak memory 201620 kb
Host smart-c048c873-d37f-425e-989f-56d96a2c9ef3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744860403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl
_mem_walk.744860403
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.82358727
Short name T566
Test name
Test status
Simulation time 4004937888 ps
CPU time 181.97 seconds
Started Dec 24 01:27:01 PM PST 23
Finished Dec 24 01:30:04 PM PST 23
Peak memory 350356 kb
Host smart-209394b0-9c56-4b23-bc0f-ff50a9d7a1b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82358727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multipl
e_keys.82358727
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.1429081969
Short name T747
Test name
Test status
Simulation time 1185751258 ps
CPU time 22.32 seconds
Started Dec 24 01:27:02 PM PST 23
Finished Dec 24 01:27:26 PM PST 23
Peak memory 202080 kb
Host smart-604ba774-9919-4715-ac7e-fc7c448abb98
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429081969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.1429081969
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.745982101
Short name T512
Test name
Test status
Simulation time 22760261455 ps
CPU time 362.44 seconds
Started Dec 24 01:27:01 PM PST 23
Finished Dec 24 01:33:05 PM PST 23
Peak memory 202176 kb
Host smart-333ceee4-847d-451e-a18f-bffd9bf33136
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745982101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.sram_ctrl_partial_access_b2b.745982101
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.475756607
Short name T977
Test name
Test status
Simulation time 3737796174 ps
CPU time 7.81 seconds
Started Dec 24 01:27:14 PM PST 23
Finished Dec 24 01:27:23 PM PST 23
Peak memory 202512 kb
Host smart-4ea13c5b-839a-4b56-bd9e-6cf7a4558378
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475756607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.475756607
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.3408440014
Short name T527
Test name
Test status
Simulation time 34675980091 ps
CPU time 1270.83 seconds
Started Dec 24 01:27:12 PM PST 23
Finished Dec 24 01:48:24 PM PST 23
Peak memory 378044 kb
Host smart-aeb176bd-9b28-4fa1-a527-7439b292d63e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408440014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3408440014
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.2210150596
Short name T326
Test name
Test status
Simulation time 11451982981 ps
CPU time 36.45 seconds
Started Dec 24 01:27:01 PM PST 23
Finished Dec 24 01:27:39 PM PST 23
Peak memory 202016 kb
Host smart-85facd62-06da-45c1-a372-787a836d7e48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210150596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2210150596
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3199321593
Short name T964
Test name
Test status
Simulation time 536180406 ps
CPU time 3893.86 seconds
Started Dec 24 01:27:11 PM PST 23
Finished Dec 24 02:32:06 PM PST 23
Peak memory 497340 kb
Host smart-39a561d2-f25e-4e28-b384-369f7cfda3a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3199321593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3199321593
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1428785766
Short name T936
Test name
Test status
Simulation time 5481236289 ps
CPU time 412.27 seconds
Started Dec 24 01:27:02 PM PST 23
Finished Dec 24 01:33:56 PM PST 23
Peak memory 202168 kb
Host smart-82eff89b-4855-4ff6-ad0d-b4786e833678
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428785766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.1428785766
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.954183199
Short name T591
Test name
Test status
Simulation time 1878265920 ps
CPU time 66.66 seconds
Started Dec 24 01:27:02 PM PST 23
Finished Dec 24 01:28:10 PM PST 23
Peak memory 296624 kb
Host smart-6bc6ab3c-68e9-485c-a0d9-c95304015595
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954183199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_throughput_w_partial_write.954183199
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2425938579
Short name T422
Test name
Test status
Simulation time 13112502550 ps
CPU time 1914.09 seconds
Started Dec 24 01:27:09 PM PST 23
Finished Dec 24 01:59:04 PM PST 23
Peak memory 379020 kb
Host smart-94af0633-862c-4995-9e8f-3068b5449721
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425938579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.2425938579
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.2105275474
Short name T941
Test name
Test status
Simulation time 155962835 ps
CPU time 0.65 seconds
Started Dec 24 01:27:06 PM PST 23
Finished Dec 24 01:27:07 PM PST 23
Peak memory 201844 kb
Host smart-a46f9ddf-691e-4a19-b3fb-9dc17e1afbda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105275474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.2105275474
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.2543753530
Short name T225
Test name
Test status
Simulation time 34293098786 ps
CPU time 554.87 seconds
Started Dec 24 01:27:11 PM PST 23
Finished Dec 24 01:36:27 PM PST 23
Peak memory 202048 kb
Host smart-b93c9d8c-8c41-43f7-af62-de38286c5eda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543753530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.2543753530
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.1311318632
Short name T295
Test name
Test status
Simulation time 7203077929 ps
CPU time 432 seconds
Started Dec 24 01:27:15 PM PST 23
Finished Dec 24 01:34:28 PM PST 23
Peak memory 365716 kb
Host smart-ef03fc8f-06f7-4e56-a6c3-50db8a351ca2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311318632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.1311318632
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.298926802
Short name T418
Test name
Test status
Simulation time 16192047098 ps
CPU time 240.24 seconds
Started Dec 24 01:27:07 PM PST 23
Finished Dec 24 01:31:08 PM PST 23
Peak memory 202204 kb
Host smart-9810ba20-77fc-4c18-975c-ab25bf01e608
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298926802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_esc
alation.298926802
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.2812175478
Short name T403
Test name
Test status
Simulation time 708183959 ps
CPU time 34.81 seconds
Started Dec 24 01:27:12 PM PST 23
Finished Dec 24 01:27:48 PM PST 23
Peak memory 252284 kb
Host smart-14f6a803-5746-4f28-9a44-16cc75aad8fe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812175478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.2812175478
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1322973709
Short name T274
Test name
Test status
Simulation time 75091232936 ps
CPU time 198.38 seconds
Started Dec 24 01:27:07 PM PST 23
Finished Dec 24 01:30:26 PM PST 23
Peak memory 218452 kb
Host smart-be16df53-b4a9-4f92-b135-6cce785e725c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322973709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.1322973709
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.1913431731
Short name T939
Test name
Test status
Simulation time 62576305193 ps
CPU time 310.8 seconds
Started Dec 24 01:27:16 PM PST 23
Finished Dec 24 01:32:28 PM PST 23
Peak memory 202604 kb
Host smart-f9a81c02-1806-4822-8faf-8442effd48bb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913431731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.1913431731
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.2501839583
Short name T509
Test name
Test status
Simulation time 44241117031 ps
CPU time 1778.82 seconds
Started Dec 24 01:27:09 PM PST 23
Finished Dec 24 01:56:49 PM PST 23
Peak memory 379088 kb
Host smart-aa67810b-2d13-46a0-8f57-adf2bdb11ecd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501839583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.2501839583
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.8566292
Short name T137
Test name
Test status
Simulation time 3702316662 ps
CPU time 117.72 seconds
Started Dec 24 01:27:07 PM PST 23
Finished Dec 24 01:29:05 PM PST 23
Peak memory 351408 kb
Host smart-471137a8-4d98-4d7f-a287-ddc2a1c8babc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8566292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sra
m_ctrl_partial_access.8566292
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3521582912
Short name T543
Test name
Test status
Simulation time 14653879925 ps
CPU time 234.06 seconds
Started Dec 24 01:27:05 PM PST 23
Finished Dec 24 01:31:00 PM PST 23
Peak memory 202172 kb
Host smart-9da7c534-ac07-4308-a0a8-f3a88195fa2b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521582912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.3521582912
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.3033833568
Short name T639
Test name
Test status
Simulation time 1248033605 ps
CPU time 6.35 seconds
Started Dec 24 01:27:16 PM PST 23
Finished Dec 24 01:27:23 PM PST 23
Peak memory 202412 kb
Host smart-fdff3109-c45b-4fc5-a01a-354a894401be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033833568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3033833568
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.1944803275
Short name T909
Test name
Test status
Simulation time 69479230567 ps
CPU time 1602.3 seconds
Started Dec 24 01:27:08 PM PST 23
Finished Dec 24 01:53:51 PM PST 23
Peak memory 371860 kb
Host smart-1bfded81-9c28-46e2-82b0-84471ce8a65e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944803275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1944803275
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.1837857529
Short name T310
Test name
Test status
Simulation time 5603666904 ps
CPU time 105.84 seconds
Started Dec 24 01:27:13 PM PST 23
Finished Dec 24 01:28:59 PM PST 23
Peak memory 365836 kb
Host smart-30e5d46d-cd55-491e-982c-83ee676cdd46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837857529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1837857529
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1293024626
Short name T14
Test name
Test status
Simulation time 9971264067 ps
CPU time 2962.88 seconds
Started Dec 24 01:27:08 PM PST 23
Finished Dec 24 02:16:32 PM PST 23
Peak memory 572832 kb
Host smart-3fd680a2-ccb6-46a4-9a60-3e2f3cf538cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1293024626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1293024626
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.645681177
Short name T705
Test name
Test status
Simulation time 7591930958 ps
CPU time 281.2 seconds
Started Dec 24 01:27:08 PM PST 23
Finished Dec 24 01:31:50 PM PST 23
Peak memory 202236 kb
Host smart-3bc07ac2-c8f9-4a9b-bb61-fc57f56b738b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645681177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.sram_ctrl_stress_pipeline.645681177
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3227839069
Short name T681
Test name
Test status
Simulation time 2767404972 ps
CPU time 28.39 seconds
Started Dec 24 01:27:16 PM PST 23
Finished Dec 24 01:27:45 PM PST 23
Peak memory 210416 kb
Host smart-4b58e2ff-95fa-40bc-b05c-91f974377a97
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227839069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3227839069
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3383225237
Short name T483
Test name
Test status
Simulation time 26191630822 ps
CPU time 962.29 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 01:43:31 PM PST 23
Peak memory 376956 kb
Host smart-b07a9945-667e-4334-a9f5-e668f2a3507f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383225237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.3383225237
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.3949251364
Short name T581
Test name
Test status
Simulation time 168451017 ps
CPU time 0.69 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 01:27:29 PM PST 23
Peak memory 201872 kb
Host smart-4e0c8ccc-e187-4bf7-a8fb-d1e13c496970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949251364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.3949251364
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.431257112
Short name T524
Test name
Test status
Simulation time 213162768483 ps
CPU time 1275.89 seconds
Started Dec 24 01:27:16 PM PST 23
Finished Dec 24 01:48:33 PM PST 23
Peak memory 202132 kb
Host smart-b29c8358-a31f-4f61-9131-7ff216be74c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431257112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.
431257112
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.1850391554
Short name T365
Test name
Test status
Simulation time 18616171935 ps
CPU time 683.84 seconds
Started Dec 24 01:27:28 PM PST 23
Finished Dec 24 01:38:53 PM PST 23
Peak memory 376784 kb
Host smart-99730885-aac6-4160-99b8-e70764fd5b75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850391554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.1850391554
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.659954420
Short name T503
Test name
Test status
Simulation time 223125330541 ps
CPU time 254.92 seconds
Started Dec 24 01:27:11 PM PST 23
Finished Dec 24 01:31:27 PM PST 23
Peak memory 202084 kb
Host smart-6874ef41-c659-4d85-ae5d-22c24c620aa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659954420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esc
alation.659954420
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.1706402953
Short name T286
Test name
Test status
Simulation time 2890496279 ps
CPU time 65.68 seconds
Started Dec 24 01:27:10 PM PST 23
Finished Dec 24 01:28:17 PM PST 23
Peak memory 300220 kb
Host smart-42ebeb3c-d2d9-43ae-9b86-364588825788
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706402953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.1706402953
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1681603516
Short name T410
Test name
Test status
Simulation time 2420343457 ps
CPU time 79.97 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 01:28:48 PM PST 23
Peak memory 211572 kb
Host smart-a3a2b913-14f0-49ba-b545-134a2f7f38ec
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681603516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.1681603516
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.2714302125
Short name T727
Test name
Test status
Simulation time 8228991147 ps
CPU time 130.05 seconds
Started Dec 24 01:27:28 PM PST 23
Finished Dec 24 01:29:40 PM PST 23
Peak memory 202112 kb
Host smart-7baddf92-5c61-464c-96f8-f05020649504
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714302125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.2714302125
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.2995228282
Short name T637
Test name
Test status
Simulation time 16825186344 ps
CPU time 1219.78 seconds
Started Dec 24 01:27:06 PM PST 23
Finished Dec 24 01:47:27 PM PST 23
Peak memory 376996 kb
Host smart-fc26d490-3f0d-4c46-88bd-80ee2df1e34d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995228282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.2995228282
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.1904992885
Short name T781
Test name
Test status
Simulation time 1124156614 ps
CPU time 82.17 seconds
Started Dec 24 01:27:12 PM PST 23
Finished Dec 24 01:28:35 PM PST 23
Peak memory 356420 kb
Host smart-70ed145c-af45-4bfc-a36d-9c5e48623283
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904992885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.1904992885
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2970319731
Short name T224
Test name
Test status
Simulation time 20904366702 ps
CPU time 309.32 seconds
Started Dec 24 01:27:13 PM PST 23
Finished Dec 24 01:32:23 PM PST 23
Peak memory 201600 kb
Host smart-da8372b8-49dd-41cb-a7aa-7e7c933cfa1d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970319731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.2970319731
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.2320803232
Short name T358
Test name
Test status
Simulation time 632111339 ps
CPU time 5.75 seconds
Started Dec 24 01:27:26 PM PST 23
Finished Dec 24 01:27:32 PM PST 23
Peak memory 202464 kb
Host smart-651ac546-c375-41d1-95b0-6adc287d6617
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320803232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2320803232
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.662143185
Short name T28
Test name
Test status
Simulation time 45324377295 ps
CPU time 690.21 seconds
Started Dec 24 01:27:28 PM PST 23
Finished Dec 24 01:39:00 PM PST 23
Peak memory 362616 kb
Host smart-e46922fe-d9fa-48db-aa4b-ec6d5d1870fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662143185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.662143185
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.1806136677
Short name T393
Test name
Test status
Simulation time 854970895 ps
CPU time 21.44 seconds
Started Dec 24 01:27:07 PM PST 23
Finished Dec 24 01:27:29 PM PST 23
Peak memory 243724 kb
Host smart-fbdca430-ffa6-4e34-abc2-6a8249261fb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806136677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1806136677
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1790115531
Short name T479
Test name
Test status
Simulation time 2129381276 ps
CPU time 3613.18 seconds
Started Dec 24 01:27:26 PM PST 23
Finished Dec 24 02:27:41 PM PST 23
Peak memory 523980 kb
Host smart-a634b8a6-f493-49a7-bc4a-2c46e775286c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1790115531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1790115531
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.977272504
Short name T350
Test name
Test status
Simulation time 16980329501 ps
CPU time 294 seconds
Started Dec 24 01:27:12 PM PST 23
Finished Dec 24 01:32:07 PM PST 23
Peak memory 200100 kb
Host smart-3d0551d5-81c5-4d0b-ac86-c6c6c768747e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977272504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.sram_ctrl_stress_pipeline.977272504
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4109403975
Short name T699
Test name
Test status
Simulation time 747767649 ps
CPU time 53.33 seconds
Started Dec 24 01:27:14 PM PST 23
Finished Dec 24 01:28:09 PM PST 23
Peak memory 278964 kb
Host smart-ff8ea9a7-aa47-4333-9b03-6f10ba2c27d8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109403975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.4109403975
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3246201033
Short name T688
Test name
Test status
Simulation time 33085101327 ps
CPU time 983.23 seconds
Started Dec 24 01:27:28 PM PST 23
Finished Dec 24 01:43:53 PM PST 23
Peak memory 368836 kb
Host smart-cf610737-cddc-42a5-a897-8612ec26b370
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246201033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.3246201033
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.3342898186
Short name T923
Test name
Test status
Simulation time 18248243 ps
CPU time 0.62 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 01:27:28 PM PST 23
Peak memory 201432 kb
Host smart-3f0ce649-dc85-4da5-b87d-83e33eb61acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342898186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.3342898186
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.3380078574
Short name T518
Test name
Test status
Simulation time 47159044583 ps
CPU time 1171.98 seconds
Started Dec 24 01:27:30 PM PST 23
Finished Dec 24 01:47:03 PM PST 23
Peak memory 202248 kb
Host smart-ad531318-4edb-4752-be4d-a44d46074da2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380078574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.3380078574
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.594636044
Short name T804
Test name
Test status
Simulation time 7923026825 ps
CPU time 72.69 seconds
Started Dec 24 01:27:26 PM PST 23
Finished Dec 24 01:28:40 PM PST 23
Peak memory 210328 kb
Host smart-c911f406-ab2c-4952-9336-adf5a6533e12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594636044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_esc
alation.594636044
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.3704042728
Short name T454
Test name
Test status
Simulation time 3688109445 ps
CPU time 45.72 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 01:28:14 PM PST 23
Peak memory 267520 kb
Host smart-bb405320-d8c5-4256-8ce0-162cda80b5c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704042728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.3704042728
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.822997796
Short name T927
Test name
Test status
Simulation time 1618491278 ps
CPU time 129.8 seconds
Started Dec 24 01:27:28 PM PST 23
Finished Dec 24 01:29:39 PM PST 23
Peak memory 213740 kb
Host smart-8bdcbc2f-15ea-403b-ba9d-6df40ac80ae7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822997796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_mem_partial_access.822997796
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.1464789463
Short name T545
Test name
Test status
Simulation time 49187538085 ps
CPU time 287.77 seconds
Started Dec 24 01:27:30 PM PST 23
Finished Dec 24 01:32:18 PM PST 23
Peak memory 202220 kb
Host smart-eac35d9f-5c08-4ff1-b15e-50eb75d2a833
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464789463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.1464789463
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.3218096762
Short name T145
Test name
Test status
Simulation time 5197767142 ps
CPU time 258.08 seconds
Started Dec 24 01:27:28 PM PST 23
Finished Dec 24 01:31:47 PM PST 23
Peak memory 354568 kb
Host smart-73cd6a39-6ddb-4e3a-9e1d-00ec8b0dea5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218096762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.3218096762
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.2897413687
Short name T946
Test name
Test status
Simulation time 970104944 ps
CPU time 28.84 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 01:27:57 PM PST 23
Peak memory 202092 kb
Host smart-0d433d03-fbac-4ca2-b6e2-51ddb04559f0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897413687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.2897413687
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.77412495
Short name T110
Test name
Test status
Simulation time 22411737198 ps
CPU time 238.26 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 01:31:26 PM PST 23
Peak memory 202168 kb
Host smart-5f1bfcc0-8122-49f9-b66b-5f446961fa28
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77412495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_partial_access_b2b.77412495
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.2760532900
Short name T399
Test name
Test status
Simulation time 2398819414 ps
CPU time 5.75 seconds
Started Dec 24 01:27:26 PM PST 23
Finished Dec 24 01:27:33 PM PST 23
Peak memory 202380 kb
Host smart-6aaeddef-1c4e-4b60-b1ed-c2c640c9d8b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760532900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2760532900
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.2073837501
Short name T133
Test name
Test status
Simulation time 65859928270 ps
CPU time 857 seconds
Started Dec 24 01:27:28 PM PST 23
Finished Dec 24 01:41:46 PM PST 23
Peak memory 374156 kb
Host smart-eaa492ce-a2b6-46c2-b8ad-e1d268c7b231
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073837501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2073837501
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.2639670504
Short name T437
Test name
Test status
Simulation time 5294424746 ps
CPU time 80.19 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 01:28:48 PM PST 23
Peak memory 311444 kb
Host smart-2b680eaf-b640-41eb-a23d-37a7bf4d1b9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639670504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2639670504
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.2410269146
Short name T427
Test name
Test status
Simulation time 756065918400 ps
CPU time 4717.58 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 02:46:06 PM PST 23
Peak memory 313560 kb
Host smart-10de825b-51dc-4eec-889c-c2f0aad8faf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410269146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.2410269146
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.847260632
Short name T677
Test name
Test status
Simulation time 2958645171 ps
CPU time 4761.63 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 02:46:50 PM PST 23
Peak memory 716456 kb
Host smart-55099528-c853-47f3-9d0a-66373bd830de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=847260632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.847260632
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2950661400
Short name T922
Test name
Test status
Simulation time 5999640844 ps
CPU time 307.34 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 01:32:35 PM PST 23
Peak memory 202092 kb
Host smart-aa9f1e3e-a0cd-4cb3-b28f-64b2e769093a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950661400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.2950661400
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.328267020
Short name T594
Test name
Test status
Simulation time 808363398 ps
CPU time 136.41 seconds
Started Dec 24 01:27:26 PM PST 23
Finished Dec 24 01:29:43 PM PST 23
Peak memory 354472 kb
Host smart-3d68b4f0-570e-4acc-9d00-8e02cf5891a0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328267020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_throughput_w_partial_write.328267020
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1843670291
Short name T353
Test name
Test status
Simulation time 7589868021 ps
CPU time 619.19 seconds
Started Dec 24 01:27:42 PM PST 23
Finished Dec 24 01:38:02 PM PST 23
Peak memory 378320 kb
Host smart-3ca7508c-8552-4e48-a175-4a6f2f67da30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843670291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.1843670291
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.3435796918
Short name T978
Test name
Test status
Simulation time 19428795 ps
CPU time 0.65 seconds
Started Dec 24 01:27:40 PM PST 23
Finished Dec 24 01:27:41 PM PST 23
Peak memory 201824 kb
Host smart-5a3f9a55-ed2e-498f-96ad-e3034e8acc4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435796918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.3435796918
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.131793787
Short name T763
Test name
Test status
Simulation time 82990171180 ps
CPU time 1356.23 seconds
Started Dec 24 01:27:28 PM PST 23
Finished Dec 24 01:50:06 PM PST 23
Peak memory 202092 kb
Host smart-2bfdcbc7-fbb9-481a-b327-24add2b79f89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131793787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.
131793787
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.459597569
Short name T883
Test name
Test status
Simulation time 31342140433 ps
CPU time 569.12 seconds
Started Dec 24 01:27:41 PM PST 23
Finished Dec 24 01:37:11 PM PST 23
Peak memory 364752 kb
Host smart-40c24bd8-8adc-4e92-ada9-6828d7c41a1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459597569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executabl
e.459597569
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.3004468930
Short name T782
Test name
Test status
Simulation time 38470985345 ps
CPU time 74.02 seconds
Started Dec 24 01:27:42 PM PST 23
Finished Dec 24 01:28:57 PM PST 23
Peak memory 210384 kb
Host smart-a650e2f5-1457-4083-9cca-26d364db45c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004468930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.3004468930
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.1641985314
Short name T862
Test name
Test status
Simulation time 2388582878 ps
CPU time 57.96 seconds
Started Dec 24 01:27:43 PM PST 23
Finished Dec 24 01:28:42 PM PST 23
Peak memory 284012 kb
Host smart-0fc59b33-db9e-4345-ab25-0ec411290a6a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641985314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.1641985314
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.4014678380
Short name T349
Test name
Test status
Simulation time 977088177 ps
CPU time 75.01 seconds
Started Dec 24 01:27:40 PM PST 23
Finished Dec 24 01:28:56 PM PST 23
Peak memory 211124 kb
Host smart-8043e4ff-e0d1-4f4e-b9c5-2bb5f7d1d7fc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014678380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.4014678380
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.1618005114
Short name T725
Test name
Test status
Simulation time 14367983293 ps
CPU time 143.3 seconds
Started Dec 24 01:27:41 PM PST 23
Finished Dec 24 01:30:05 PM PST 23
Peak memory 202236 kb
Host smart-19ee1e2d-e2f2-4f88-9323-c0c2ce80d1b6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618005114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.1618005114
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.2617411980
Short name T752
Test name
Test status
Simulation time 51351806008 ps
CPU time 1266.74 seconds
Started Dec 24 01:27:28 PM PST 23
Finished Dec 24 01:48:36 PM PST 23
Peak memory 378200 kb
Host smart-7a15963b-48fa-4e53-b8ff-8833836c5403
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617411980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.2617411980
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.490068547
Short name T362
Test name
Test status
Simulation time 910249176 ps
CPU time 17.63 seconds
Started Dec 24 01:27:41 PM PST 23
Finished Dec 24 01:27:59 PM PST 23
Peak memory 201976 kb
Host smart-c935be09-10d9-48d1-a901-a6dce70eb060
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490068547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.s
ram_ctrl_partial_access.490068547
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3128949071
Short name T844
Test name
Test status
Simulation time 20963300420 ps
CPU time 380.07 seconds
Started Dec 24 01:27:40 PM PST 23
Finished Dec 24 01:34:00 PM PST 23
Peak memory 216608 kb
Host smart-eef726d0-122a-4d58-9aa7-513d3af0a56d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128949071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.3128949071
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.357949357
Short name T301
Test name
Test status
Simulation time 1054940028 ps
CPU time 7.07 seconds
Started Dec 24 01:27:42 PM PST 23
Finished Dec 24 01:27:50 PM PST 23
Peak memory 202428 kb
Host smart-4a0e7bac-25e7-40bc-8efd-a63fd451b4eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357949357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.357949357
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.2680318742
Short name T938
Test name
Test status
Simulation time 22000554297 ps
CPU time 1366.27 seconds
Started Dec 24 01:27:40 PM PST 23
Finished Dec 24 01:50:27 PM PST 23
Peak memory 361756 kb
Host smart-43ce7d1f-7e30-488f-949f-9ffb5a07fee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680318742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2680318742
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.136600681
Short name T860
Test name
Test status
Simulation time 1646145069 ps
CPU time 19.15 seconds
Started Dec 24 01:27:27 PM PST 23
Finished Dec 24 01:27:48 PM PST 23
Peak memory 227256 kb
Host smart-5097727e-c41a-42e5-8cbd-d00f215d7216
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136600681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.136600681
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.2580419151
Short name T771
Test name
Test status
Simulation time 63363483246 ps
CPU time 3235.18 seconds
Started Dec 24 01:27:43 PM PST 23
Finished Dec 24 02:21:39 PM PST 23
Peak memory 380992 kb
Host smart-e7dcb683-6001-4be2-8536-20dbcc152aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580419151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.2580419151
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4102552094
Short name T611
Test name
Test status
Simulation time 12299305330 ps
CPU time 1864.89 seconds
Started Dec 24 01:27:41 PM PST 23
Finished Dec 24 01:58:47 PM PST 23
Peak memory 609144 kb
Host smart-0d7ab954-24cb-4a0a-9cc6-8b85a713e9e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4102552094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.4102552094
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1633490033
Short name T19
Test name
Test status
Simulation time 19580141458 ps
CPU time 426.15 seconds
Started Dec 24 01:27:42 PM PST 23
Finished Dec 24 01:34:49 PM PST 23
Peak memory 202152 kb
Host smart-cec1963c-c4b9-45e9-84fa-66d829259185
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633490033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.1633490033
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4234096164
Short name T478
Test name
Test status
Simulation time 2785252060 ps
CPU time 57.99 seconds
Started Dec 24 01:27:42 PM PST 23
Finished Dec 24 01:28:41 PM PST 23
Peak memory 285064 kb
Host smart-3f98853f-ed2b-4b7f-9c67-a982a27a6355
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234096164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.4234096164
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3167448732
Short name T710
Test name
Test status
Simulation time 18686161057 ps
CPU time 317.42 seconds
Started Dec 24 01:22:05 PM PST 23
Finished Dec 24 01:27:25 PM PST 23
Peak memory 297268 kb
Host smart-6a7b4751-c617-474a-916a-4fb3fae4cd43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167448732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.3167448732
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.865016981
Short name T773
Test name
Test status
Simulation time 38853055 ps
CPU time 0.65 seconds
Started Dec 24 01:22:07 PM PST 23
Finished Dec 24 01:22:10 PM PST 23
Peak memory 201500 kb
Host smart-20b8c7c2-8a11-4f70-a331-fbba5db11f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865016981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.865016981
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.3987297113
Short name T788
Test name
Test status
Simulation time 154594914894 ps
CPU time 809.44 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:35:38 PM PST 23
Peak memory 202160 kb
Host smart-bf2e2611-d85f-4267-abbf-d100544e99e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987297113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
3987297113
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.2761221153
Short name T882
Test name
Test status
Simulation time 3053420362 ps
CPU time 234.47 seconds
Started Dec 24 01:22:07 PM PST 23
Finished Dec 24 01:26:04 PM PST 23
Peak memory 352628 kb
Host smart-c4693bbd-8a98-4566-bb48-4e441fa628d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761221153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.2761221153
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.4063503109
Short name T666
Test name
Test status
Simulation time 5562696280 ps
CPU time 58.5 seconds
Started Dec 24 01:22:07 PM PST 23
Finished Dec 24 01:23:08 PM PST 23
Peak memory 202156 kb
Host smart-5e648e8f-848e-4c86-a28c-028bd7fc81a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063503109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.4063503109
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.150229360
Short name T784
Test name
Test status
Simulation time 2008733107 ps
CPU time 174.9 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:25:03 PM PST 23
Peak memory 362016 kb
Host smart-842246d0-e701-4ae7-a962-581e8828713c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150229360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.sram_ctrl_max_throughput.150229360
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2951922040
Short name T645
Test name
Test status
Simulation time 2549473883 ps
CPU time 80.65 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:23:30 PM PST 23
Peak memory 211132 kb
Host smart-30ecdb97-5981-4251-835e-b2b481e51444
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951922040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.2951922040
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.986595257
Short name T829
Test name
Test status
Simulation time 27609607694 ps
CPU time 155.3 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:24:44 PM PST 23
Peak memory 202236 kb
Host smart-9f123f4e-d127-42e8-957b-01060d83ce79
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986595257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_
mem_walk.986595257
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.3943459140
Short name T147
Test name
Test status
Simulation time 27504779482 ps
CPU time 1116.49 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:40:46 PM PST 23
Peak memory 381224 kb
Host smart-3c56f3d0-91cf-4b7a-a721-73fcf651fa14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943459140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.3943459140
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.2136722087
Short name T243
Test name
Test status
Simulation time 778829187 ps
CPU time 13.98 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:22:23 PM PST 23
Peak memory 235228 kb
Host smart-abc8d11b-5a78-4a78-8a1a-d1970eeb68a9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136722087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.2136722087
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1268696274
Short name T643
Test name
Test status
Simulation time 45657855327 ps
CPU time 558.44 seconds
Started Dec 24 01:22:07 PM PST 23
Finished Dec 24 01:31:28 PM PST 23
Peak memory 202080 kb
Host smart-732f44b2-f8df-4d55-9d65-e286b186ce75
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268696274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.1268696274
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.1578126917
Short name T629
Test name
Test status
Simulation time 1406937014 ps
CPU time 13.77 seconds
Started Dec 24 01:22:07 PM PST 23
Finished Dec 24 01:22:24 PM PST 23
Peak memory 202600 kb
Host smart-3058670e-5225-4454-b6bf-e9b5dc596b94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578126917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1578126917
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.2765682529
Short name T341
Test name
Test status
Simulation time 7944357159 ps
CPU time 633.74 seconds
Started Dec 24 01:22:07 PM PST 23
Finished Dec 24 01:32:44 PM PST 23
Peak memory 375048 kb
Host smart-be158b62-3867-4fd0-957e-0b09a18958e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765682529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2765682529
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.4208566217
Short name T833
Test name
Test status
Simulation time 1047787952 ps
CPU time 27.2 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:22:36 PM PST 23
Peak memory 202000 kb
Host smart-a251a8ed-e804-434a-8360-bc668cfd58a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208566217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.4208566217
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.788126995
Short name T607
Test name
Test status
Simulation time 468313884 ps
CPU time 1108.41 seconds
Started Dec 24 01:22:08 PM PST 23
Finished Dec 24 01:40:39 PM PST 23
Peak memory 413924 kb
Host smart-de78bef3-1a09-4706-8dd8-92b0bcd0dfb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=788126995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.788126995
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.617589301
Short name T338
Test name
Test status
Simulation time 17648243828 ps
CPU time 359.89 seconds
Started Dec 24 01:22:06 PM PST 23
Finished Dec 24 01:28:08 PM PST 23
Peak memory 202168 kb
Host smart-dda9e8b3-b21e-431f-9eae-3f170c189b65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617589301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
sram_ctrl_stress_pipeline.617589301
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.418527525
Short name T445
Test name
Test status
Simulation time 835337383 ps
CPU time 158.02 seconds
Started Dec 24 01:22:07 PM PST 23
Finished Dec 24 01:24:47 PM PST 23
Peak memory 370752 kb
Host smart-6a90f932-30d4-4409-9e08-fa53f2e0738f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418527525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.418527525
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.219149499
Short name T668
Test name
Test status
Simulation time 9033672654 ps
CPU time 489.77 seconds
Started Dec 24 01:22:17 PM PST 23
Finished Dec 24 01:30:32 PM PST 23
Peak memory 362680 kb
Host smart-e205a7d2-6e8c-4c08-bbcb-42fdb4097c7b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219149499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_access_during_key_req.219149499
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.2293342710
Short name T828
Test name
Test status
Simulation time 20443703 ps
CPU time 0.64 seconds
Started Dec 24 01:22:20 PM PST 23
Finished Dec 24 01:22:25 PM PST 23
Peak memory 201808 kb
Host smart-d5c1a034-e77f-4d3b-8e3f-f5afec3ebc68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293342710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.2293342710
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.2088875866
Short name T259
Test name
Test status
Simulation time 156681121917 ps
CPU time 1789.01 seconds
Started Dec 24 01:22:07 PM PST 23
Finished Dec 24 01:51:59 PM PST 23
Peak memory 202096 kb
Host smart-738881e8-0700-4b56-8ade-f8f58dfc4b0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088875866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
2088875866
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.943665241
Short name T397
Test name
Test status
Simulation time 6171521162 ps
CPU time 299.04 seconds
Started Dec 24 01:22:10 PM PST 23
Finished Dec 24 01:27:16 PM PST 23
Peak memory 326028 kb
Host smart-23f6d547-9185-4b4f-874e-bbecfd2a65d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943665241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable
.943665241
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.3324733718
Short name T576
Test name
Test status
Simulation time 20864646289 ps
CPU time 124.49 seconds
Started Dec 24 01:22:08 PM PST 23
Finished Dec 24 01:24:15 PM PST 23
Peak memory 213832 kb
Host smart-7717551c-609c-4099-87c4-58ae1a9b41a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324733718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.3324733718
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.2279255108
Short name T586
Test name
Test status
Simulation time 2304738524 ps
CPU time 26.59 seconds
Started Dec 24 01:22:09 PM PST 23
Finished Dec 24 01:22:38 PM PST 23
Peak memory 210248 kb
Host smart-d1551644-ff79-48e4-9d2b-afe280d8e871
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279255108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.2279255108
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1746413865
Short name T391
Test name
Test status
Simulation time 2344075625 ps
CPU time 76.78 seconds
Started Dec 24 01:22:10 PM PST 23
Finished Dec 24 01:23:30 PM PST 23
Peak memory 210876 kb
Host smart-e18ddb92-5e3f-43f5-a2cd-4447c3c7b8c6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746413865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.1746413865
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.525058296
Short name T650
Test name
Test status
Simulation time 2139870263 ps
CPU time 114.91 seconds
Started Dec 24 01:22:17 PM PST 23
Finished Dec 24 01:24:17 PM PST 23
Peak memory 202056 kb
Host smart-857886df-f31a-4e37-9180-aeb233d55d50
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525058296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_
mem_walk.525058296
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.1009654325
Short name T407
Test name
Test status
Simulation time 20767702889 ps
CPU time 914.13 seconds
Started Dec 24 01:22:10 PM PST 23
Finished Dec 24 01:37:31 PM PST 23
Peak memory 374036 kb
Host smart-043b527a-d58a-42c4-ad13-6b886c7c8930
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009654325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.1009654325
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.2613014541
Short name T351
Test name
Test status
Simulation time 1336268492 ps
CPU time 153.21 seconds
Started Dec 24 01:22:07 PM PST 23
Finished Dec 24 01:24:43 PM PST 23
Peak memory 358464 kb
Host smart-a5d1c2ea-477e-46ac-ba33-b36d2004df35
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613014541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.2613014541
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4173556938
Short name T139
Test name
Test status
Simulation time 61332695326 ps
CPU time 332.46 seconds
Started Dec 24 01:22:08 PM PST 23
Finished Dec 24 01:27:43 PM PST 23
Peak memory 202144 kb
Host smart-48a63307-b62d-4c1a-850a-a819d321a414
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173556938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.4173556938
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.2167808279
Short name T562
Test name
Test status
Simulation time 1351684546 ps
CPU time 13.37 seconds
Started Dec 24 01:22:07 PM PST 23
Finished Dec 24 01:22:23 PM PST 23
Peak memory 202396 kb
Host smart-2dab10d0-cda3-4a9b-8ccc-6bfb8bb1a91e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167808279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2167808279
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.1993164972
Short name T487
Test name
Test status
Simulation time 3552541041 ps
CPU time 132.37 seconds
Started Dec 24 01:22:08 PM PST 23
Finished Dec 24 01:24:23 PM PST 23
Peak memory 299344 kb
Host smart-b5598d20-de43-489d-9a8f-d9bbe7650fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993164972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1993164972
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.350030618
Short name T702
Test name
Test status
Simulation time 744198677 ps
CPU time 12.8 seconds
Started Dec 24 01:22:10 PM PST 23
Finished Dec 24 01:22:29 PM PST 23
Peak memory 202132 kb
Host smart-9f5b2889-70fe-4cef-bd1d-23e69cf8dae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350030618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.350030618
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3121415702
Short name T803
Test name
Test status
Simulation time 7613510755 ps
CPU time 4130.93 seconds
Started Dec 24 01:22:10 PM PST 23
Finished Dec 24 02:31:05 PM PST 23
Peak memory 449692 kb
Host smart-f2aa0697-4ff3-418d-b63d-62b811cd2961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3121415702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3121415702
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2078826305
Short name T690
Test name
Test status
Simulation time 5012052526 ps
CPU time 374.87 seconds
Started Dec 24 01:22:08 PM PST 23
Finished Dec 24 01:28:26 PM PST 23
Peak memory 202168 kb
Host smart-5fb6d594-4c08-4436-b967-a9495b448a6e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078826305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.2078826305
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3486548603
Short name T719
Test name
Test status
Simulation time 1461132055 ps
CPU time 63.87 seconds
Started Dec 24 01:22:17 PM PST 23
Finished Dec 24 01:23:26 PM PST 23
Peak memory 289072 kb
Host smart-101d427e-8085-4de7-8be8-216f128f18d6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486548603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3486548603
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1504060095
Short name T600
Test name
Test status
Simulation time 54038593209 ps
CPU time 1986.76 seconds
Started Dec 24 01:22:17 PM PST 23
Finished Dec 24 01:55:29 PM PST 23
Peak memory 381076 kb
Host smart-50c7329c-ab54-42d2-b208-fac1eb0c5ed9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504060095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.1504060095
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.3506974911
Short name T386
Test name
Test status
Simulation time 14253285 ps
CPU time 0.65 seconds
Started Dec 24 01:22:20 PM PST 23
Finished Dec 24 01:22:25 PM PST 23
Peak memory 201900 kb
Host smart-91f722a4-d478-4715-b490-d39fa70b69ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506974911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.3506974911
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.503819408
Short name T969
Test name
Test status
Simulation time 287412649814 ps
CPU time 2388.62 seconds
Started Dec 24 01:22:18 PM PST 23
Finished Dec 24 02:02:13 PM PST 23
Peak memory 202080 kb
Host smart-233b4ecc-6cd2-470b-aba6-b5119c437390
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503819408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.503819408
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.3781946701
Short name T850
Test name
Test status
Simulation time 1490672560 ps
CPU time 51.31 seconds
Started Dec 24 01:22:18 PM PST 23
Finished Dec 24 01:23:16 PM PST 23
Peak memory 276616 kb
Host smart-7cdb9027-c82f-49e4-9bb7-b40bab9685a2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781946701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.3781946701
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.924302327
Short name T843
Test name
Test status
Simulation time 5349887788 ps
CPU time 80.26 seconds
Started Dec 24 01:22:19 PM PST 23
Finished Dec 24 01:23:45 PM PST 23
Peak memory 211180 kb
Host smart-60968c6a-4f6d-4b71-9c77-7d7421ecb084
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924302327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
sram_ctrl_mem_partial_access.924302327
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.2209719319
Short name T662
Test name
Test status
Simulation time 7892913106 ps
CPU time 132.51 seconds
Started Dec 24 01:22:19 PM PST 23
Finished Dec 24 01:24:37 PM PST 23
Peak memory 202228 kb
Host smart-ed20b234-b3a7-474b-842d-4f68f587d27b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209719319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.2209719319
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.4206165098
Short name T934
Test name
Test status
Simulation time 27627096066 ps
CPU time 655.9 seconds
Started Dec 24 01:22:17 PM PST 23
Finished Dec 24 01:33:18 PM PST 23
Peak memory 376896 kb
Host smart-109f47de-fa34-4aa5-9ef1-38b21730d0c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206165098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.4206165098
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.1182678296
Short name T533
Test name
Test status
Simulation time 1243568846 ps
CPU time 23.39 seconds
Started Dec 24 01:22:19 PM PST 23
Finished Dec 24 01:22:48 PM PST 23
Peak memory 202104 kb
Host smart-64a3cce1-1e2d-4e00-9506-69be0b1ac79b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182678296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.1182678296
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1089698279
Short name T317
Test name
Test status
Simulation time 14467971539 ps
CPU time 248.42 seconds
Started Dec 24 01:22:17 PM PST 23
Finished Dec 24 01:26:31 PM PST 23
Peak memory 202028 kb
Host smart-4bedf777-7a19-4fe3-a2e7-b19f4f456606
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089698279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.1089698279
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3562016026
Short name T35
Test name
Test status
Simulation time 726945450 ps
CPU time 6.93 seconds
Started Dec 24 01:22:18 PM PST 23
Finished Dec 24 01:22:31 PM PST 23
Peak memory 202388 kb
Host smart-ddae3689-541d-413a-bfad-13383b46c260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562016026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3562016026
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.397054742
Short name T598
Test name
Test status
Simulation time 10604547180 ps
CPU time 1324.32 seconds
Started Dec 24 01:22:18 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 378068 kb
Host smart-21a1886d-d36c-496b-80c5-63447b7a52c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397054742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.397054742
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.1733098439
Short name T925
Test name
Test status
Simulation time 597623397 ps
CPU time 20.88 seconds
Started Dec 24 01:22:20 PM PST 23
Finished Dec 24 01:22:45 PM PST 23
Peak memory 260312 kb
Host smart-a6095d97-227a-45d7-ba15-6dbb6a015f17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733098439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.1733098439
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.1374701088
Short name T802
Test name
Test status
Simulation time 145595045512 ps
CPU time 2317.36 seconds
Started Dec 24 01:22:18 PM PST 23
Finished Dec 24 02:01:02 PM PST 23
Peak memory 396716 kb
Host smart-099f05f8-d73d-43bc-a837-f4f2294b2a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374701088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.1374701088
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2701365858
Short name T983
Test name
Test status
Simulation time 1476368790 ps
CPU time 4909.9 seconds
Started Dec 24 01:22:17 PM PST 23
Finished Dec 24 02:44:13 PM PST 23
Peak memory 698908 kb
Host smart-e0b512cd-5759-48dc-9639-1093b3d020a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2701365858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2701365858
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.2404687490
Short name T647
Test name
Test status
Simulation time 4092872184 ps
CPU time 275.86 seconds
Started Dec 24 01:22:19 PM PST 23
Finished Dec 24 01:27:00 PM PST 23
Peak memory 202160 kb
Host smart-70207c11-860b-4858-b419-72cb33a75b05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404687490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.2404687490
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2392494439
Short name T319
Test name
Test status
Simulation time 2760340544 ps
CPU time 36.1 seconds
Started Dec 24 01:22:17 PM PST 23
Finished Dec 24 01:22:58 PM PST 23
Peak memory 234856 kb
Host smart-e1494bfe-82f0-4555-9a4e-5839e70045cc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392494439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2392494439
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2928297749
Short name T893
Test name
Test status
Simulation time 1740122637 ps
CPU time 146.83 seconds
Started Dec 24 01:22:18 PM PST 23
Finished Dec 24 01:24:51 PM PST 23
Peak memory 360572 kb
Host smart-b02489f7-db73-461c-a24f-8e5420f1e099
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928297749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.2928297749
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.1245083194
Short name T624
Test name
Test status
Simulation time 14077114 ps
CPU time 0.64 seconds
Started Dec 24 01:22:55 PM PST 23
Finished Dec 24 01:22:57 PM PST 23
Peak memory 201428 kb
Host smart-99266f2e-249c-4f84-9364-869b25a67528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245083194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.1245083194
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.2610886178
Short name T653
Test name
Test status
Simulation time 28717743067 ps
CPU time 473.78 seconds
Started Dec 24 01:22:18 PM PST 23
Finished Dec 24 01:30:18 PM PST 23
Peak memory 202072 kb
Host smart-bf33ae56-145f-41c8-828c-d66f40b657b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610886178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
2610886178
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.3912046426
Short name T6
Test name
Test status
Simulation time 75745756038 ps
CPU time 183.1 seconds
Started Dec 24 01:22:17 PM PST 23
Finished Dec 24 01:25:26 PM PST 23
Peak memory 210380 kb
Host smart-857563f4-2bab-4c13-8829-6ae167f56314
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912046426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.3912046426
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.4001330818
Short name T798
Test name
Test status
Simulation time 732890836 ps
CPU time 40.51 seconds
Started Dec 24 01:22:18 PM PST 23
Finished Dec 24 01:23:05 PM PST 23
Peak memory 251204 kb
Host smart-21e71eeb-1ad1-4be0-915f-b78238d86878
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001330818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.4001330818
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1957737001
Short name T718
Test name
Test status
Simulation time 1551969012 ps
CPU time 76.61 seconds
Started Dec 24 01:22:45 PM PST 23
Finished Dec 24 01:24:06 PM PST 23
Peak memory 210500 kb
Host smart-3e71741a-d84c-405d-84ba-cd4b84bf45a7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957737001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.1957737001
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.2570209667
Short name T924
Test name
Test status
Simulation time 49134782651 ps
CPU time 160.79 seconds
Started Dec 24 01:22:44 PM PST 23
Finished Dec 24 01:25:30 PM PST 23
Peak memory 202304 kb
Host smart-58615a59-1bdb-464d-b41e-8a01b3c660a3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570209667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.2570209667
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.2485641764
Short name T866
Test name
Test status
Simulation time 7643935705 ps
CPU time 670.99 seconds
Started Dec 24 01:22:18 PM PST 23
Finished Dec 24 01:33:36 PM PST 23
Peak memory 379076 kb
Host smart-3fe54830-8336-4e2b-a9b5-7f03e461aba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485641764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.2485641764
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.4093791320
Short name T968
Test name
Test status
Simulation time 1544759441 ps
CPU time 76.15 seconds
Started Dec 24 01:22:18 PM PST 23
Finished Dec 24 01:23:41 PM PST 23
Peak memory 309528 kb
Host smart-2f21c601-f747-40e3-9c84-832239a4fe2a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093791320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.4093791320
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1899036727
Short name T615
Test name
Test status
Simulation time 87493577753 ps
CPU time 365.45 seconds
Started Dec 24 01:22:21 PM PST 23
Finished Dec 24 01:28:30 PM PST 23
Peak memory 202132 kb
Host smart-a6b9b0a0-ac5e-403b-b586-ddbc151e7a6f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899036727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.1899036727
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.4109984716
Short name T328
Test name
Test status
Simulation time 1355522644 ps
CPU time 13.52 seconds
Started Dec 24 01:22:43 PM PST 23
Finished Dec 24 01:23:02 PM PST 23
Peak memory 202396 kb
Host smart-594a4ef4-ec34-4419-b1fe-dd3eb4c25573
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109984716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.4109984716
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.2021820650
Short name T279
Test name
Test status
Simulation time 7920167562 ps
CPU time 343.4 seconds
Started Dec 24 01:22:19 PM PST 23
Finished Dec 24 01:28:08 PM PST 23
Peak memory 361016 kb
Host smart-2b311900-c311-4ede-bba0-0ddd44ce8da2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021820650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2021820650
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.503989315
Short name T44
Test name
Test status
Simulation time 654432958 ps
CPU time 11.83 seconds
Started Dec 24 01:22:22 PM PST 23
Finished Dec 24 01:22:37 PM PST 23
Peak memory 202044 kb
Host smart-59e6ebe3-8c2d-41bc-b49b-f44710b636fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503989315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.503989315
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.1337761516
Short name T780
Test name
Test status
Simulation time 73479933136 ps
CPU time 4720.33 seconds
Started Dec 24 01:22:46 PM PST 23
Finished Dec 24 02:41:31 PM PST 23
Peak memory 381136 kb
Host smart-1afcf1ed-7951-4764-83c7-ab3533aaa045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337761516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.1337761516
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3774279214
Short name T480
Test name
Test status
Simulation time 836006789 ps
CPU time 2688.25 seconds
Started Dec 24 01:22:40 PM PST 23
Finished Dec 24 02:07:32 PM PST 23
Peak memory 449832 kb
Host smart-236fa6bd-4f49-4742-87cb-e6711ca646ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3774279214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3774279214
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2555082634
Short name T312
Test name
Test status
Simulation time 3330282711 ps
CPU time 234.11 seconds
Started Dec 24 01:22:19 PM PST 23
Finished Dec 24 01:26:19 PM PST 23
Peak memory 202172 kb
Host smart-b6708d40-039a-4a37-b9c7-cbfa09757084
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555082634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.2555082634
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4161276290
Short name T443
Test name
Test status
Simulation time 2729625723 ps
CPU time 30.78 seconds
Started Dec 24 01:22:19 PM PST 23
Finished Dec 24 01:22:55 PM PST 23
Peak memory 220280 kb
Host smart-a316f144-4fc4-42e4-a141-60bc81a5b52d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161276290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.4161276290
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2932719366
Short name T74
Test name
Test status
Simulation time 10183650595 ps
CPU time 1760.62 seconds
Started Dec 24 01:22:44 PM PST 23
Finished Dec 24 01:52:10 PM PST 23
Peak memory 380304 kb
Host smart-39e16e9d-2b9c-46ee-8bae-cea0a6510cde
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932719366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.2932719366
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.944567563
Short name T254
Test name
Test status
Simulation time 19322419 ps
CPU time 0.63 seconds
Started Dec 24 01:22:45 PM PST 23
Finished Dec 24 01:22:50 PM PST 23
Peak memory 201816 kb
Host smart-dd573a7b-0572-40b3-8b13-8afdc7a43a41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944567563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.944567563
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.1866702304
Short name T337
Test name
Test status
Simulation time 38233065437 ps
CPU time 1285.63 seconds
Started Dec 24 01:22:41 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 210368 kb
Host smart-b86324f7-bf30-47d1-b9f9-1c0f95cbc93c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866702304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
1866702304
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.2011629216
Short name T131
Test name
Test status
Simulation time 32046841420 ps
CPU time 2920.64 seconds
Started Dec 24 01:22:44 PM PST 23
Finished Dec 24 02:11:30 PM PST 23
Peak memory 377920 kb
Host smart-bdbd636b-0727-475b-b16a-85ff377ee5ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011629216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.2011629216
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.1444275042
Short name T911
Test name
Test status
Simulation time 32867115496 ps
CPU time 89.21 seconds
Started Dec 24 01:22:40 PM PST 23
Finished Dec 24 01:24:13 PM PST 23
Peak memory 202160 kb
Host smart-aed7d90e-49a6-4fed-88b4-67140a58ed13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444275042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.1444275042
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.1252629805
Short name T102
Test name
Test status
Simulation time 4023497654 ps
CPU time 129.21 seconds
Started Dec 24 01:22:45 PM PST 23
Finished Dec 24 01:24:58 PM PST 23
Peak memory 369196 kb
Host smart-283e8d72-4d4d-4529-8398-6b6e3ba86199
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252629805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.1252629805
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.726243066
Short name T680
Test name
Test status
Simulation time 2538098780 ps
CPU time 86.02 seconds
Started Dec 24 01:22:47 PM PST 23
Finished Dec 24 01:24:16 PM PST 23
Peak memory 211144 kb
Host smart-59b946bf-58cb-44ed-a188-c51f653b314b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726243066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_mem_partial_access.726243066
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.512980431
Short name T794
Test name
Test status
Simulation time 2081106031 ps
CPU time 128.84 seconds
Started Dec 24 01:22:56 PM PST 23
Finished Dec 24 01:25:06 PM PST 23
Peak memory 202148 kb
Host smart-59285f37-1d7b-4c7a-a79f-16c6690c8bc9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512980431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_
mem_walk.512980431
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.235675034
Short name T638
Test name
Test status
Simulation time 69059652802 ps
CPU time 1212.63 seconds
Started Dec 24 01:22:41 PM PST 23
Finished Dec 24 01:42:57 PM PST 23
Peak memory 374936 kb
Host smart-75469e91-ef8b-4b6d-b682-654f2ea36bcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235675034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multipl
e_keys.235675034
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.1261596249
Short name T229
Test name
Test status
Simulation time 7629060376 ps
CPU time 62.18 seconds
Started Dec 24 01:22:42 PM PST 23
Finished Dec 24 01:23:48 PM PST 23
Peak memory 290088 kb
Host smart-6a6a3bf8-0d4f-451f-9f7f-5b18992dfe78
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261596249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.1261596249
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2352474546
Short name T564
Test name
Test status
Simulation time 66023184881 ps
CPU time 228.16 seconds
Started Dec 24 01:22:45 PM PST 23
Finished Dec 24 01:26:37 PM PST 23
Peak memory 202152 kb
Host smart-79447920-055a-4f47-8aa9-be6fcc35c0d6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352474546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.2352474546
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.2351462428
Short name T975
Test name
Test status
Simulation time 1531720693 ps
CPU time 13.88 seconds
Started Dec 24 01:22:41 PM PST 23
Finished Dec 24 01:22:58 PM PST 23
Peak memory 202428 kb
Host smart-dfd66f52-fc51-4f2b-9e00-cb93c279f597
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351462428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2351462428
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.2385469219
Short name T541
Test name
Test status
Simulation time 23580098497 ps
CPU time 506.95 seconds
Started Dec 24 01:22:40 PM PST 23
Finished Dec 24 01:31:11 PM PST 23
Peak memory 361588 kb
Host smart-525e6a6b-df9f-4915-a2c4-52beecd3995c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385469219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2385469219
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.3774375511
Short name T463
Test name
Test status
Simulation time 1604571680 ps
CPU time 23.83 seconds
Started Dec 24 01:22:40 PM PST 23
Finished Dec 24 01:23:08 PM PST 23
Peak memory 202116 kb
Host smart-b31f744b-0d27-46c8-a627-b50a969e1841
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774375511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3774375511
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.3282389486
Short name T413
Test name
Test status
Simulation time 1038965046686 ps
CPU time 4556.45 seconds
Started Dec 24 01:22:43 PM PST 23
Finished Dec 24 02:38:45 PM PST 23
Peak memory 381180 kb
Host smart-91d1f13f-dbc5-4cb3-9d3c-924ad1eb8604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282389486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.3282389486
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3039747076
Short name T497
Test name
Test status
Simulation time 1210644275 ps
CPU time 3631.5 seconds
Started Dec 24 01:22:45 PM PST 23
Finished Dec 24 02:23:21 PM PST 23
Peak memory 507928 kb
Host smart-ab148217-754e-40ec-8ab6-8fb0f7d6f2a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3039747076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3039747076
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2426038609
Short name T783
Test name
Test status
Simulation time 24628477870 ps
CPU time 344.18 seconds
Started Dec 24 01:22:41 PM PST 23
Finished Dec 24 01:28:28 PM PST 23
Peak memory 202168 kb
Host smart-79064108-7335-431f-a092-2af6bd7affce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426038609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.2426038609
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3308036753
Short name T809
Test name
Test status
Simulation time 1752676584 ps
CPU time 82.29 seconds
Started Dec 24 01:22:45 PM PST 23
Finished Dec 24 01:24:12 PM PST 23
Peak memory 296952 kb
Host smart-f73be567-6318-4857-b1e7-e6d746e59f0b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308036753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3308036753
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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