| T504 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1836186019 |
|
|
Dec 31 01:04:26 PM PST 23 |
Dec 31 01:04:42 PM PST 23 |
350121134 ps |
| T505 |
/workspace/coverage/default/22.sram_ctrl_smoke.456284617 |
|
|
Dec 31 01:04:55 PM PST 23 |
Dec 31 01:05:17 PM PST 23 |
4429558807 ps |
| T23 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3941481200 |
|
|
Dec 31 01:04:27 PM PST 23 |
Dec 31 01:04:32 PM PST 23 |
854152483 ps |
| T506 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1074582904 |
|
|
Dec 31 01:06:41 PM PST 23 |
Dec 31 01:08:17 PM PST 23 |
1580312611 ps |
| T507 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3022186266 |
|
|
Dec 31 01:06:03 PM PST 23 |
Dec 31 01:07:55 PM PST 23 |
43415453949 ps |
| T508 |
/workspace/coverage/default/36.sram_ctrl_stress_all.2304950716 |
|
|
Dec 31 01:05:47 PM PST 23 |
Dec 31 02:52:11 PM PST 23 |
1129892386167 ps |
| T509 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.215286322 |
|
|
Dec 31 01:05:06 PM PST 23 |
Dec 31 01:06:32 PM PST 23 |
738536955 ps |
| T510 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1982096063 |
|
|
Dec 31 01:05:44 PM PST 23 |
Dec 31 01:12:37 PM PST 23 |
6096778195 ps |
| T511 |
/workspace/coverage/default/34.sram_ctrl_smoke.2285987898 |
|
|
Dec 31 01:05:41 PM PST 23 |
Dec 31 01:06:27 PM PST 23 |
7266962280 ps |
| T512 |
/workspace/coverage/default/28.sram_ctrl_alert_test.1647623587 |
|
|
Dec 31 01:05:30 PM PST 23 |
Dec 31 01:05:32 PM PST 23 |
42305205 ps |
| T513 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.444345011 |
|
|
Dec 31 01:04:56 PM PST 23 |
Dec 31 01:30:09 PM PST 23 |
122173801091 ps |
| T514 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2568386962 |
|
|
Dec 31 01:05:29 PM PST 23 |
Dec 31 02:26:04 PM PST 23 |
2879427261 ps |
| T515 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.654964474 |
|
|
Dec 31 01:03:53 PM PST 23 |
Dec 31 01:40:37 PM PST 23 |
648047971 ps |
| T516 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3492310379 |
|
|
Dec 31 01:04:50 PM PST 23 |
Dec 31 02:27:32 PM PST 23 |
22428200755 ps |
| T517 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.4143902268 |
|
|
Dec 31 01:05:46 PM PST 23 |
Dec 31 01:07:02 PM PST 23 |
14425048759 ps |
| T518 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3999331031 |
|
|
Dec 31 01:05:42 PM PST 23 |
Dec 31 01:20:38 PM PST 23 |
35132144675 ps |
| T519 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.3945862077 |
|
|
Dec 31 01:05:11 PM PST 23 |
Dec 31 01:07:20 PM PST 23 |
776060714 ps |
| T520 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3639410523 |
|
|
Dec 31 01:04:24 PM PST 23 |
Dec 31 01:04:33 PM PST 23 |
671113717 ps |
| T521 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.821309773 |
|
|
Dec 31 01:04:51 PM PST 23 |
Dec 31 01:13:55 PM PST 23 |
86670112984 ps |
| T33 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1797404151 |
|
|
Dec 31 01:04:09 PM PST 23 |
Dec 31 01:04:13 PM PST 23 |
5224016937 ps |
| T522 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.4257183516 |
|
|
Dec 31 01:05:25 PM PST 23 |
Dec 31 01:28:30 PM PST 23 |
18478094094 ps |
| T523 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2424076251 |
|
|
Dec 31 01:05:31 PM PST 23 |
Dec 31 01:07:44 PM PST 23 |
3175333487 ps |
| T524 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.675359954 |
|
|
Dec 31 01:06:19 PM PST 23 |
Dec 31 01:08:10 PM PST 23 |
1784344604 ps |
| T525 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1081356584 |
|
|
Dec 31 01:04:54 PM PST 23 |
Dec 31 01:05:31 PM PST 23 |
1397602512 ps |
| T526 |
/workspace/coverage/default/0.sram_ctrl_stress_all.4067851699 |
|
|
Dec 31 01:04:08 PM PST 23 |
Dec 31 02:08:29 PM PST 23 |
136151693539 ps |
| T527 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3495545431 |
|
|
Dec 31 01:05:43 PM PST 23 |
Dec 31 01:18:10 PM PST 23 |
10085883342 ps |
| T528 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2954491529 |
|
|
Dec 31 01:06:25 PM PST 23 |
Dec 31 01:07:03 PM PST 23 |
2872002955 ps |
| T529 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.92254757 |
|
|
Dec 31 01:04:47 PM PST 23 |
Dec 31 01:05:03 PM PST 23 |
1293358398 ps |
| T530 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3178683416 |
|
|
Dec 31 01:04:34 PM PST 23 |
Dec 31 01:05:59 PM PST 23 |
9410471222 ps |
| T531 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1284554199 |
|
|
Dec 31 01:04:29 PM PST 23 |
Dec 31 01:04:38 PM PST 23 |
1268186601 ps |
| T532 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.702429421 |
|
|
Dec 31 01:05:44 PM PST 23 |
Dec 31 01:12:37 PM PST 23 |
20113695425 ps |
| T533 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.1398963447 |
|
|
Dec 31 01:05:32 PM PST 23 |
Dec 31 01:08:18 PM PST 23 |
778231302 ps |
| T534 |
/workspace/coverage/default/28.sram_ctrl_bijection.4060467941 |
|
|
Dec 31 01:05:08 PM PST 23 |
Dec 31 01:45:57 PM PST 23 |
158131446999 ps |
| T535 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.332849608 |
|
|
Dec 31 01:06:26 PM PST 23 |
Dec 31 01:23:15 PM PST 23 |
52922012243 ps |
| T536 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.3268088603 |
|
|
Dec 31 01:05:09 PM PST 23 |
Dec 31 01:09:53 PM PST 23 |
6449462470 ps |
| T537 |
/workspace/coverage/default/32.sram_ctrl_stress_all.2845123873 |
|
|
Dec 31 01:05:42 PM PST 23 |
Dec 31 01:59:11 PM PST 23 |
71815728901 ps |
| T538 |
/workspace/coverage/default/28.sram_ctrl_executable.733400138 |
|
|
Dec 31 01:05:04 PM PST 23 |
Dec 31 01:10:03 PM PST 23 |
5695630804 ps |
| T539 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.4112397412 |
|
|
Dec 31 01:04:50 PM PST 23 |
Dec 31 01:04:57 PM PST 23 |
1348430744 ps |
| T540 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4253336084 |
|
|
Dec 31 01:04:18 PM PST 23 |
Dec 31 01:12:10 PM PST 23 |
7128205429 ps |
| T541 |
/workspace/coverage/default/18.sram_ctrl_alert_test.1483857535 |
|
|
Dec 31 01:04:53 PM PST 23 |
Dec 31 01:04:56 PM PST 23 |
13708388 ps |
| T542 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1209783119 |
|
|
Dec 31 01:05:43 PM PST 23 |
Dec 31 01:42:31 PM PST 23 |
1417996270 ps |
| T543 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1389187344 |
|
|
Dec 31 01:06:45 PM PST 23 |
Dec 31 01:06:52 PM PST 23 |
21149564 ps |
| T544 |
/workspace/coverage/default/6.sram_ctrl_partial_access.289825977 |
|
|
Dec 31 01:04:19 PM PST 23 |
Dec 31 01:04:47 PM PST 23 |
4153629376 ps |
| T545 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1608513945 |
|
|
Dec 31 01:06:41 PM PST 23 |
Dec 31 01:07:17 PM PST 23 |
1588595382 ps |
| T546 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.326504344 |
|
|
Dec 31 01:04:25 PM PST 23 |
Dec 31 01:06:43 PM PST 23 |
1578188364 ps |
| T547 |
/workspace/coverage/default/16.sram_ctrl_regwen.1750265326 |
|
|
Dec 31 01:04:37 PM PST 23 |
Dec 31 01:25:34 PM PST 23 |
13984734841 ps |
| T548 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3018692125 |
|
|
Dec 31 01:03:49 PM PST 23 |
Dec 31 01:38:39 PM PST 23 |
14025804008 ps |
| T549 |
/workspace/coverage/default/40.sram_ctrl_stress_all.2604111742 |
|
|
Dec 31 01:06:04 PM PST 23 |
Dec 31 01:40:56 PM PST 23 |
209146998104 ps |
| T550 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3170490346 |
|
|
Dec 31 01:05:10 PM PST 23 |
Dec 31 01:05:18 PM PST 23 |
361111221 ps |
| T551 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3337501864 |
|
|
Dec 31 01:04:23 PM PST 23 |
Dec 31 01:04:32 PM PST 23 |
357862237 ps |
| T552 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3851096213 |
|
|
Dec 31 01:05:43 PM PST 23 |
Dec 31 01:27:35 PM PST 23 |
41055895293 ps |
| T553 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3378415371 |
|
|
Dec 31 01:06:23 PM PST 23 |
Dec 31 01:11:47 PM PST 23 |
12261017533 ps |
| T554 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.471442819 |
|
|
Dec 31 01:05:42 PM PST 23 |
Dec 31 01:08:50 PM PST 23 |
790054874 ps |
| T555 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3564903229 |
|
|
Dec 31 01:04:21 PM PST 23 |
Dec 31 01:22:46 PM PST 23 |
23828118235 ps |
| T556 |
/workspace/coverage/default/35.sram_ctrl_partial_access.1320271390 |
|
|
Dec 31 01:05:31 PM PST 23 |
Dec 31 01:05:53 PM PST 23 |
866682106 ps |
| T557 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3970481792 |
|
|
Dec 31 01:05:30 PM PST 23 |
Dec 31 02:00:49 PM PST 23 |
3007628488 ps |
| T558 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1606876688 |
|
|
Dec 31 01:04:05 PM PST 23 |
Dec 31 02:07:09 PM PST 23 |
105383674583 ps |
| T559 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.3031553319 |
|
|
Dec 31 01:05:11 PM PST 23 |
Dec 31 01:07:18 PM PST 23 |
7889391251 ps |
| T560 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.293985442 |
|
|
Dec 31 01:04:21 PM PST 23 |
Dec 31 01:09:28 PM PST 23 |
9124624919 ps |
| T561 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1397608342 |
|
|
Dec 31 01:06:43 PM PST 23 |
Dec 31 01:22:00 PM PST 23 |
12913610519 ps |
| T562 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.546806696 |
|
|
Dec 31 01:04:43 PM PST 23 |
Dec 31 01:07:02 PM PST 23 |
3025831363 ps |
| T563 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.1324848539 |
|
|
Dec 31 01:04:59 PM PST 23 |
Dec 31 01:06:30 PM PST 23 |
1485775722 ps |
| T564 |
/workspace/coverage/default/40.sram_ctrl_alert_test.2312384652 |
|
|
Dec 31 01:06:04 PM PST 23 |
Dec 31 01:06:15 PM PST 23 |
15641810 ps |
| T565 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2152457775 |
|
|
Dec 31 01:06:42 PM PST 23 |
Dec 31 01:11:44 PM PST 23 |
4736300272 ps |
| T566 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3637651719 |
|
|
Dec 31 01:06:18 PM PST 23 |
Dec 31 01:16:42 PM PST 23 |
110516290630 ps |
| T567 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3740878348 |
|
|
Dec 31 01:06:18 PM PST 23 |
Dec 31 01:06:27 PM PST 23 |
742507560 ps |
| T568 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3562672147 |
|
|
Dec 31 01:06:18 PM PST 23 |
Dec 31 01:06:52 PM PST 23 |
4087765365 ps |
| T569 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1040813519 |
|
|
Dec 31 01:06:21 PM PST 23 |
Dec 31 01:23:04 PM PST 23 |
110353051952 ps |
| T570 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3329120489 |
|
|
Dec 31 01:05:40 PM PST 23 |
Dec 31 01:07:35 PM PST 23 |
41777604183 ps |
| T571 |
/workspace/coverage/default/8.sram_ctrl_smoke.446653590 |
|
|
Dec 31 01:04:15 PM PST 23 |
Dec 31 01:05:38 PM PST 23 |
830757250 ps |
| T572 |
/workspace/coverage/default/1.sram_ctrl_bijection.2593717491 |
|
|
Dec 31 01:04:09 PM PST 23 |
Dec 31 01:24:58 PM PST 23 |
39045369316 ps |
| T573 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.52349846 |
|
|
Dec 31 01:04:49 PM PST 23 |
Dec 31 01:34:44 PM PST 23 |
65055634677 ps |
| T574 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.205546547 |
|
|
Dec 31 01:04:26 PM PST 23 |
Dec 31 01:06:11 PM PST 23 |
1495466184 ps |
| T575 |
/workspace/coverage/default/43.sram_ctrl_partial_access.4125273109 |
|
|
Dec 31 01:06:01 PM PST 23 |
Dec 31 01:06:43 PM PST 23 |
1723670205 ps |
| T34 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2624728443 |
|
|
Dec 31 01:03:56 PM PST 23 |
Dec 31 01:04:00 PM PST 23 |
151961498 ps |
| T576 |
/workspace/coverage/default/49.sram_ctrl_bijection.1518977771 |
|
|
Dec 31 01:06:42 PM PST 23 |
Dec 31 01:30:18 PM PST 23 |
250015021526 ps |
| T577 |
/workspace/coverage/default/47.sram_ctrl_regwen.4022753151 |
|
|
Dec 31 01:06:45 PM PST 23 |
Dec 31 01:30:01 PM PST 23 |
14390134707 ps |
| T578 |
/workspace/coverage/default/3.sram_ctrl_regwen.823406606 |
|
|
Dec 31 01:03:53 PM PST 23 |
Dec 31 01:04:26 PM PST 23 |
679323788 ps |
| T579 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3608723139 |
|
|
Dec 31 01:04:30 PM PST 23 |
Dec 31 01:05:11 PM PST 23 |
735962938 ps |
| T580 |
/workspace/coverage/default/30.sram_ctrl_stress_all.3278356254 |
|
|
Dec 31 01:05:05 PM PST 23 |
Dec 31 01:45:17 PM PST 23 |
191783048013 ps |
| T581 |
/workspace/coverage/default/12.sram_ctrl_alert_test.2368431177 |
|
|
Dec 31 01:04:17 PM PST 23 |
Dec 31 01:04:19 PM PST 23 |
15011823 ps |
| T582 |
/workspace/coverage/default/6.sram_ctrl_bijection.845075631 |
|
|
Dec 31 01:04:10 PM PST 23 |
Dec 31 01:22:36 PM PST 23 |
73034061561 ps |
| T583 |
/workspace/coverage/default/15.sram_ctrl_regwen.1652510124 |
|
|
Dec 31 01:04:36 PM PST 23 |
Dec 31 01:17:58 PM PST 23 |
9211242617 ps |
| T584 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.2303067328 |
|
|
Dec 31 01:04:25 PM PST 23 |
Dec 31 01:05:50 PM PST 23 |
1494014401 ps |
| T585 |
/workspace/coverage/default/1.sram_ctrl_smoke.1799264288 |
|
|
Dec 31 01:04:03 PM PST 23 |
Dec 31 01:04:28 PM PST 23 |
4571896140 ps |
| T586 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1008442944 |
|
|
Dec 31 01:04:17 PM PST 23 |
Dec 31 01:07:32 PM PST 23 |
39510535137 ps |
| T587 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.879703148 |
|
|
Dec 31 01:04:16 PM PST 23 |
Dec 31 01:04:31 PM PST 23 |
682095024 ps |
| T588 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.4183449857 |
|
|
Dec 31 01:04:56 PM PST 23 |
Dec 31 01:21:29 PM PST 23 |
29278830075 ps |
| T589 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.568863656 |
|
|
Dec 31 01:04:42 PM PST 23 |
Dec 31 01:05:07 PM PST 23 |
1764882124 ps |
| T590 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2291229271 |
|
|
Dec 31 01:06:43 PM PST 23 |
Dec 31 01:09:31 PM PST 23 |
8921968491 ps |
| T591 |
/workspace/coverage/default/0.sram_ctrl_alert_test.540052504 |
|
|
Dec 31 01:03:39 PM PST 23 |
Dec 31 01:03:45 PM PST 23 |
54698419 ps |
| T592 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.211397883 |
|
|
Dec 31 01:03:58 PM PST 23 |
Dec 31 01:12:15 PM PST 23 |
73802597050 ps |
| T593 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.57689411 |
|
|
Dec 31 01:04:53 PM PST 23 |
Dec 31 01:05:10 PM PST 23 |
1406224914 ps |
| T594 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.336249857 |
|
|
Dec 31 01:06:25 PM PST 23 |
Dec 31 01:15:54 PM PST 23 |
8822253841 ps |
| T595 |
/workspace/coverage/default/31.sram_ctrl_executable.3882025146 |
|
|
Dec 31 01:05:07 PM PST 23 |
Dec 31 01:16:22 PM PST 23 |
11498868048 ps |
| T596 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2454841726 |
|
|
Dec 31 01:06:44 PM PST 23 |
Dec 31 01:12:13 PM PST 23 |
8860184108 ps |
| T597 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2265506046 |
|
|
Dec 31 01:05:32 PM PST 23 |
Dec 31 01:34:04 PM PST 23 |
828103917 ps |
| T598 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1130539009 |
|
|
Dec 31 01:06:43 PM PST 23 |
Dec 31 01:14:22 PM PST 23 |
112217786426 ps |
| T599 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2235538519 |
|
|
Dec 31 01:05:43 PM PST 23 |
Dec 31 01:05:59 PM PST 23 |
356860147 ps |
| T600 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.321194888 |
|
|
Dec 31 01:04:31 PM PST 23 |
Dec 31 01:05:56 PM PST 23 |
3971796442 ps |
| T601 |
/workspace/coverage/default/2.sram_ctrl_smoke.1291568786 |
|
|
Dec 31 01:04:28 PM PST 23 |
Dec 31 01:06:22 PM PST 23 |
6098406345 ps |
| T602 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1446754657 |
|
|
Dec 31 01:05:41 PM PST 23 |
Dec 31 01:05:49 PM PST 23 |
685026234 ps |
| T603 |
/workspace/coverage/default/18.sram_ctrl_bijection.3477433208 |
|
|
Dec 31 01:04:53 PM PST 23 |
Dec 31 01:34:38 PM PST 23 |
27981604997 ps |
| T604 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3596999552 |
|
|
Dec 31 01:05:01 PM PST 23 |
Dec 31 01:07:17 PM PST 23 |
1618862274 ps |
| T605 |
/workspace/coverage/default/11.sram_ctrl_stress_all.1322573982 |
|
|
Dec 31 01:04:32 PM PST 23 |
Dec 31 03:22:09 PM PST 23 |
2723592728050 ps |
| T606 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1334053753 |
|
|
Dec 31 01:04:37 PM PST 23 |
Dec 31 01:05:09 PM PST 23 |
1343588953 ps |
| T607 |
/workspace/coverage/default/41.sram_ctrl_partial_access.3160206342 |
|
|
Dec 31 01:06:16 PM PST 23 |
Dec 31 01:06:57 PM PST 23 |
7042016127 ps |
| T608 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2523105420 |
|
|
Dec 31 01:05:32 PM PST 23 |
Dec 31 01:05:34 PM PST 23 |
45447975 ps |
| T609 |
/workspace/coverage/default/4.sram_ctrl_alert_test.1511612671 |
|
|
Dec 31 01:04:00 PM PST 23 |
Dec 31 01:04:01 PM PST 23 |
41512150 ps |
| T610 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.2741897903 |
|
|
Dec 31 01:04:48 PM PST 23 |
Dec 31 01:05:03 PM PST 23 |
681991443 ps |
| T611 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1160673942 |
|
|
Dec 31 01:05:29 PM PST 23 |
Dec 31 01:06:21 PM PST 23 |
3284583785 ps |
| T612 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2736403842 |
|
|
Dec 31 01:06:19 PM PST 23 |
Dec 31 01:22:14 PM PST 23 |
8338595386 ps |
| T613 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1069191521 |
|
|
Dec 31 01:05:44 PM PST 23 |
Dec 31 01:26:31 PM PST 23 |
22330766458 ps |
| T614 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2495983039 |
|
|
Dec 31 01:06:19 PM PST 23 |
Dec 31 01:06:39 PM PST 23 |
952700274 ps |
| T615 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2530321074 |
|
|
Dec 31 01:05:44 PM PST 23 |
Dec 31 01:13:22 PM PST 23 |
7714017917 ps |
| T616 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.807504136 |
|
|
Dec 31 01:05:30 PM PST 23 |
Dec 31 01:07:47 PM PST 23 |
4114909854 ps |
| T617 |
/workspace/coverage/default/19.sram_ctrl_alert_test.2447753076 |
|
|
Dec 31 01:04:43 PM PST 23 |
Dec 31 01:04:47 PM PST 23 |
20977367 ps |
| T618 |
/workspace/coverage/default/24.sram_ctrl_alert_test.107376225 |
|
|
Dec 31 01:04:52 PM PST 23 |
Dec 31 01:04:54 PM PST 23 |
17672517 ps |
| T619 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2957469120 |
|
|
Dec 31 01:04:34 PM PST 23 |
Dec 31 01:04:51 PM PST 23 |
1414016877 ps |
| T620 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1827176893 |
|
|
Dec 31 01:05:41 PM PST 23 |
Dec 31 02:09:41 PM PST 23 |
52962409707 ps |
| T621 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.621439699 |
|
|
Dec 31 01:04:58 PM PST 23 |
Dec 31 01:07:17 PM PST 23 |
44252619088 ps |
| T622 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.2444584936 |
|
|
Dec 31 01:05:38 PM PST 23 |
Dec 31 01:06:10 PM PST 23 |
9735341387 ps |
| T623 |
/workspace/coverage/default/49.sram_ctrl_smoke.3321311697 |
|
|
Dec 31 01:06:42 PM PST 23 |
Dec 31 01:07:13 PM PST 23 |
3511049589 ps |
| T624 |
/workspace/coverage/default/5.sram_ctrl_smoke.268527830 |
|
|
Dec 31 01:04:11 PM PST 23 |
Dec 31 01:04:37 PM PST 23 |
4274535847 ps |
| T625 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3418971482 |
|
|
Dec 31 01:05:41 PM PST 23 |
Dec 31 01:08:08 PM PST 23 |
3189513523 ps |
| T626 |
/workspace/coverage/default/8.sram_ctrl_alert_test.584988029 |
|
|
Dec 31 01:04:38 PM PST 23 |
Dec 31 01:04:45 PM PST 23 |
22695425 ps |
| T627 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.970458381 |
|
|
Dec 31 01:06:41 PM PST 23 |
Dec 31 01:12:25 PM PST 23 |
4617808680 ps |
| T628 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.640729002 |
|
|
Dec 31 01:05:06 PM PST 23 |
Dec 31 01:05:14 PM PST 23 |
1407716224 ps |
| T629 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2668364483 |
|
|
Dec 31 01:06:44 PM PST 23 |
Dec 31 01:09:08 PM PST 23 |
3067201790 ps |
| T630 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3632536734 |
|
|
Dec 31 01:03:55 PM PST 23 |
Dec 31 01:07:58 PM PST 23 |
15755744780 ps |
| T631 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1698453089 |
|
|
Dec 31 01:06:42 PM PST 23 |
Dec 31 01:06:57 PM PST 23 |
394688980 ps |
| T632 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1195030907 |
|
|
Dec 31 01:04:52 PM PST 23 |
Dec 31 01:57:48 PM PST 23 |
4861075773 ps |
| T633 |
/workspace/coverage/default/42.sram_ctrl_regwen.769383461 |
|
|
Dec 31 01:06:20 PM PST 23 |
Dec 31 01:25:06 PM PST 23 |
11497590776 ps |
| T634 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.959234267 |
|
|
Dec 31 01:06:45 PM PST 23 |
Dec 31 01:11:13 PM PST 23 |
4333654638 ps |
| T635 |
/workspace/coverage/default/30.sram_ctrl_alert_test.1707058110 |
|
|
Dec 31 01:05:32 PM PST 23 |
Dec 31 01:05:34 PM PST 23 |
12362779 ps |
| T636 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.298947928 |
|
|
Dec 31 01:04:13 PM PST 23 |
Dec 31 01:06:24 PM PST 23 |
1600059392 ps |
| T637 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.4059286352 |
|
|
Dec 31 01:05:44 PM PST 23 |
Dec 31 01:10:36 PM PST 23 |
3624409581 ps |
| T638 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3071560478 |
|
|
Dec 31 01:06:50 PM PST 23 |
Dec 31 01:11:44 PM PST 23 |
9674830561 ps |
| T639 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.2629864615 |
|
|
Dec 31 01:05:40 PM PST 23 |
Dec 31 01:10:54 PM PST 23 |
20671259728 ps |
| T640 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3104218118 |
|
|
Dec 31 01:03:41 PM PST 23 |
Dec 31 01:04:40 PM PST 23 |
1040008824 ps |
| T641 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2646492233 |
|
|
Dec 31 01:06:24 PM PST 23 |
Dec 31 02:36:08 PM PST 23 |
3417484864 ps |
| T642 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3136249612 |
|
|
Dec 31 01:04:44 PM PST 23 |
Dec 31 01:07:20 PM PST 23 |
5359505931 ps |
| T643 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2387966465 |
|
|
Dec 31 01:05:44 PM PST 23 |
Dec 31 01:07:54 PM PST 23 |
8232470766 ps |
| T644 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1685912429 |
|
|
Dec 31 01:04:50 PM PST 23 |
Dec 31 01:12:20 PM PST 23 |
28783390600 ps |
| T645 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.4147088670 |
|
|
Dec 31 01:04:26 PM PST 23 |
Dec 31 01:05:41 PM PST 23 |
2603305379 ps |
| T646 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2321029919 |
|
|
Dec 31 01:05:43 PM PST 23 |
Dec 31 01:10:49 PM PST 23 |
28106848969 ps |
| T647 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3437595391 |
|
|
Dec 31 01:04:34 PM PST 23 |
Dec 31 01:06:59 PM PST 23 |
4766134416 ps |
| T648 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.109389419 |
|
|
Dec 31 01:04:52 PM PST 23 |
Dec 31 01:32:52 PM PST 23 |
41899316014 ps |
| T649 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.407833130 |
|
|
Dec 31 01:05:45 PM PST 23 |
Dec 31 01:08:19 PM PST 23 |
13973790791 ps |
| T650 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2395919152 |
|
|
Dec 31 01:04:40 PM PST 23 |
Dec 31 01:06:11 PM PST 23 |
7443752388 ps |
| T651 |
/workspace/coverage/default/13.sram_ctrl_regwen.3867640882 |
|
|
Dec 31 01:04:35 PM PST 23 |
Dec 31 01:11:23 PM PST 23 |
5171328299 ps |
| T652 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1816032472 |
|
|
Dec 31 01:05:44 PM PST 23 |
Dec 31 01:05:54 PM PST 23 |
4818299241 ps |
| T653 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2919067479 |
|
|
Dec 31 01:04:27 PM PST 23 |
Dec 31 01:22:04 PM PST 23 |
43039123979 ps |
| T654 |
/workspace/coverage/default/42.sram_ctrl_smoke.2765140576 |
|
|
Dec 31 01:06:17 PM PST 23 |
Dec 31 01:06:48 PM PST 23 |
1381022448 ps |
| T655 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.226034646 |
|
|
Dec 31 01:04:47 PM PST 23 |
Dec 31 01:08:47 PM PST 23 |
10681537227 ps |
| T656 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2527225859 |
|
|
Dec 31 01:04:47 PM PST 23 |
Dec 31 01:07:34 PM PST 23 |
1575098045 ps |
| T657 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3881915805 |
|
|
Dec 31 01:05:43 PM PST 23 |
Dec 31 01:11:14 PM PST 23 |
20931430906 ps |
| T658 |
/workspace/coverage/default/38.sram_ctrl_smoke.2799694839 |
|
|
Dec 31 01:05:41 PM PST 23 |
Dec 31 01:08:03 PM PST 23 |
935519252 ps |
| T659 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1688871910 |
|
|
Dec 31 01:04:58 PM PST 23 |
Dec 31 01:05:28 PM PST 23 |
2694580424 ps |
| T660 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1943081127 |
|
|
Dec 31 01:04:51 PM PST 23 |
Dec 31 01:05:23 PM PST 23 |
726333729 ps |
| T661 |
/workspace/coverage/default/35.sram_ctrl_bijection.2078688253 |
|
|
Dec 31 01:05:41 PM PST 23 |
Dec 31 01:25:20 PM PST 23 |
141129077242 ps |
| T662 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3165649599 |
|
|
Dec 31 01:05:41 PM PST 23 |
Dec 31 02:13:18 PM PST 23 |
613698683 ps |
| T663 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2425021225 |
|
|
Dec 31 01:05:00 PM PST 23 |
Dec 31 01:12:29 PM PST 23 |
9228597430 ps |
| T664 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3827506917 |
|
|
Dec 31 01:05:33 PM PST 23 |
Dec 31 01:06:19 PM PST 23 |
797904825 ps |
| T665 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3247735610 |
|
|
Dec 31 01:05:42 PM PST 23 |
Dec 31 01:08:02 PM PST 23 |
1529028421 ps |
| T666 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.905484294 |
|
|
Dec 31 01:04:17 PM PST 23 |
Dec 31 01:05:41 PM PST 23 |
13600541733 ps |
| T667 |
/workspace/coverage/default/30.sram_ctrl_bijection.3402728776 |
|
|
Dec 31 01:05:03 PM PST 23 |
Dec 31 01:26:53 PM PST 23 |
66760316051 ps |
| T668 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.1250506080 |
|
|
Dec 31 01:05:07 PM PST 23 |
Dec 31 01:09:54 PM PST 23 |
49191827833 ps |
| T669 |
/workspace/coverage/default/21.sram_ctrl_alert_test.4212583212 |
|
|
Dec 31 01:04:58 PM PST 23 |
Dec 31 01:05:00 PM PST 23 |
34754370 ps |
| T670 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.495069178 |
|
|
Dec 31 01:04:31 PM PST 23 |
Dec 31 01:06:45 PM PST 23 |
4113221028 ps |
| T671 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3593370996 |
|
|
Dec 31 01:04:54 PM PST 23 |
Dec 31 01:12:15 PM PST 23 |
20379280056 ps |
| T672 |
/workspace/coverage/default/43.sram_ctrl_smoke.4004797889 |
|
|
Dec 31 01:06:25 PM PST 23 |
Dec 31 01:06:43 PM PST 23 |
2144898204 ps |
| T673 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3212887577 |
|
|
Dec 31 01:04:07 PM PST 23 |
Dec 31 01:04:28 PM PST 23 |
4189034907 ps |
| T674 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2054919032 |
|
|
Dec 31 01:04:35 PM PST 23 |
Dec 31 01:04:38 PM PST 23 |
131679785 ps |
| T675 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3839305392 |
|
|
Dec 31 01:06:43 PM PST 23 |
Dec 31 01:09:21 PM PST 23 |
38363876289 ps |
| T676 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2906422830 |
|
|
Dec 31 01:05:43 PM PST 23 |
Dec 31 01:08:41 PM PST 23 |
5237393732 ps |
| T677 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.912210043 |
|
|
Dec 31 01:04:35 PM PST 23 |
Dec 31 01:17:03 PM PST 23 |
6257141879 ps |
| T678 |
/workspace/coverage/default/45.sram_ctrl_stress_all.45465246 |
|
|
Dec 31 01:06:27 PM PST 23 |
Dec 31 02:23:06 PM PST 23 |
602280831010 ps |
| T679 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1901554199 |
|
|
Dec 31 01:05:01 PM PST 23 |
Dec 31 01:34:06 PM PST 23 |
1907261424 ps |
| T680 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3688480437 |
|
|
Dec 31 01:04:34 PM PST 23 |
Dec 31 01:52:04 PM PST 23 |
1863328760 ps |
| T681 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.495030774 |
|
|
Dec 31 01:04:54 PM PST 23 |
Dec 31 01:05:02 PM PST 23 |
1403653700 ps |
| T682 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1981976741 |
|
|
Dec 31 01:06:24 PM PST 23 |
Dec 31 01:06:30 PM PST 23 |
1165237934 ps |
| T683 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2925145522 |
|
|
Dec 31 01:04:33 PM PST 23 |
Dec 31 01:05:49 PM PST 23 |
1973787886 ps |
| T684 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.2044512570 |
|
|
Dec 31 01:03:52 PM PST 23 |
Dec 31 01:09:14 PM PST 23 |
13988821553 ps |
| T685 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.958560723 |
|
|
Dec 31 01:06:24 PM PST 23 |
Dec 31 01:06:38 PM PST 23 |
357076080 ps |
| T686 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4156046991 |
|
|
Dec 31 01:04:23 PM PST 23 |
Dec 31 01:11:32 PM PST 23 |
37888406521 ps |
| T687 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.1680551080 |
|
|
Dec 31 01:05:01 PM PST 23 |
Dec 31 01:09:29 PM PST 23 |
17913046037 ps |
| T688 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3611584689 |
|
|
Dec 31 01:04:39 PM PST 23 |
Dec 31 01:14:14 PM PST 23 |
39949054443 ps |
| T689 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1898653993 |
|
|
Dec 31 01:05:07 PM PST 23 |
Dec 31 01:05:09 PM PST 23 |
25444069 ps |
| T690 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1468604071 |
|
|
Dec 31 01:04:29 PM PST 23 |
Dec 31 01:04:51 PM PST 23 |
3737178279 ps |
| T691 |
/workspace/coverage/default/35.sram_ctrl_smoke.225228614 |
|
|
Dec 31 01:05:42 PM PST 23 |
Dec 31 01:06:14 PM PST 23 |
1446125683 ps |
| T692 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4200582765 |
|
|
Dec 31 01:06:41 PM PST 23 |
Dec 31 01:51:29 PM PST 23 |
1001956830 ps |
| T693 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3199873402 |
|
|
Dec 31 01:03:58 PM PST 23 |
Dec 31 01:06:34 PM PST 23 |
6583064592 ps |
| T694 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2713011030 |
|
|
Dec 31 01:05:05 PM PST 23 |
Dec 31 01:07:57 PM PST 23 |
954823107 ps |
| T695 |
/workspace/coverage/default/11.sram_ctrl_alert_test.519452394 |
|
|
Dec 31 01:04:26 PM PST 23 |
Dec 31 01:04:28 PM PST 23 |
27605318 ps |
| T696 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2794112739 |
|
|
Dec 31 01:04:03 PM PST 23 |
Dec 31 01:04:32 PM PST 23 |
687814590 ps |
| T697 |
/workspace/coverage/default/17.sram_ctrl_alert_test.778691912 |
|
|
Dec 31 01:04:41 PM PST 23 |
Dec 31 01:04:46 PM PST 23 |
20108856 ps |
| T698 |
/workspace/coverage/default/10.sram_ctrl_smoke.962708767 |
|
|
Dec 31 01:04:31 PM PST 23 |
Dec 31 01:05:05 PM PST 23 |
1801276464 ps |
| T699 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.3940221246 |
|
|
Dec 31 01:04:23 PM PST 23 |
Dec 31 01:08:42 PM PST 23 |
16422398569 ps |
| T700 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.2955557239 |
|
|
Dec 31 01:05:42 PM PST 23 |
Dec 31 01:05:51 PM PST 23 |
1460388616 ps |
| T701 |
/workspace/coverage/default/33.sram_ctrl_alert_test.4144911199 |
|
|
Dec 31 01:05:41 PM PST 23 |
Dec 31 01:05:43 PM PST 23 |
18339120 ps |
| T702 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.4015748770 |
|
|
Dec 31 01:04:22 PM PST 23 |
Dec 31 01:06:42 PM PST 23 |
5956365347 ps |
| T703 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2398765856 |
|
|
Dec 31 01:04:33 PM PST 23 |
Dec 31 01:06:10 PM PST 23 |
21368353348 ps |
| T704 |
/workspace/coverage/default/39.sram_ctrl_regwen.2424027733 |
|
|
Dec 31 01:05:44 PM PST 23 |
Dec 31 01:24:29 PM PST 23 |
23390500568 ps |
| T705 |
/workspace/coverage/default/17.sram_ctrl_partial_access.2479542943 |
|
|
Dec 31 01:04:32 PM PST 23 |
Dec 31 01:05:04 PM PST 23 |
2330630548 ps |
| T706 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1619455617 |
|
|
Dec 31 01:04:10 PM PST 23 |
Dec 31 01:06:25 PM PST 23 |
3259732180 ps |
| T707 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.3254947094 |
|
|
Dec 31 01:05:42 PM PST 23 |
Dec 31 01:08:09 PM PST 23 |
6261293307 ps |
| T708 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2053316295 |
|
|
Dec 31 01:05:42 PM PST 23 |
Dec 31 01:58:56 PM PST 23 |
2524715375 ps |
| T709 |
/workspace/coverage/default/12.sram_ctrl_smoke.1947088718 |
|
|
Dec 31 01:04:34 PM PST 23 |
Dec 31 01:05:03 PM PST 23 |
387097591 ps |
| T710 |
/workspace/coverage/default/4.sram_ctrl_partial_access.331135829 |
|
|
Dec 31 01:03:39 PM PST 23 |
Dec 31 01:04:25 PM PST 23 |
4235739236 ps |
| T711 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.1124014047 |
|
|
Dec 31 01:06:41 PM PST 23 |
Dec 31 01:08:14 PM PST 23 |
746931547 ps |
| T712 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1873411854 |
|
|
Dec 31 01:03:48 PM PST 23 |
Dec 31 01:11:43 PM PST 23 |
4343205673 ps |
| T713 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3074700497 |
|
|
Dec 31 01:05:42 PM PST 23 |
Dec 31 01:12:39 PM PST 23 |
6416895403 ps |
| T714 |
/workspace/coverage/default/40.sram_ctrl_partial_access.2851157127 |
|
|
Dec 31 01:05:43 PM PST 23 |
Dec 31 01:06:14 PM PST 23 |
7239720625 ps |
| T715 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.462547267 |
|
|
Dec 31 01:04:53 PM PST 23 |
Dec 31 01:07:09 PM PST 23 |
1586265735 ps |
| T716 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.154441281 |
|
|
Dec 31 01:04:54 PM PST 23 |
Dec 31 01:10:45 PM PST 23 |
33017504491 ps |
| T717 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2940209503 |
|
|
Dec 31 01:04:36 PM PST 23 |
Dec 31 01:22:06 PM PST 23 |
171506040218 ps |
| T718 |
/workspace/coverage/default/23.sram_ctrl_executable.1310307811 |
|
|
Dec 31 01:04:53 PM PST 23 |
Dec 31 01:15:43 PM PST 23 |
6757887445 ps |
| T719 |
/workspace/coverage/default/3.sram_ctrl_smoke.4220007099 |
|
|
Dec 31 01:03:48 PM PST 23 |
Dec 31 01:04:12 PM PST 23 |
2504057177 ps |
| T720 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2028521294 |
|
|
Dec 31 01:04:44 PM PST 23 |
Dec 31 01:10:02 PM PST 23 |
94106355598 ps |
| T721 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3095525380 |
|
|
Dec 31 01:06:46 PM PST 23 |
Dec 31 01:06:52 PM PST 23 |
93968117 ps |
| T722 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.794092359 |
|
|
Dec 31 01:04:14 PM PST 23 |
Dec 31 01:34:40 PM PST 23 |
2107603375 ps |
| T723 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.2731993829 |
|
|
Dec 31 01:04:43 PM PST 23 |
Dec 31 01:19:23 PM PST 23 |
32465111665 ps |
| T724 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3828303930 |
|
|
Dec 31 01:05:40 PM PST 23 |
Dec 31 01:14:39 PM PST 23 |
5006145426 ps |
| T725 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2286465073 |
|
|
Dec 31 01:04:36 PM PST 23 |
Dec 31 01:07:39 PM PST 23 |
1559306192 ps |
| T726 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.449823531 |
|
|
Dec 31 01:05:39 PM PST 23 |
Dec 31 01:05:53 PM PST 23 |
1344031649 ps |
| T727 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3856307305 |
|
|
Dec 31 01:06:20 PM PST 23 |
Dec 31 01:07:44 PM PST 23 |
14142246409 ps |
| T728 |
/workspace/coverage/default/21.sram_ctrl_smoke.1053697684 |
|
|
Dec 31 01:04:51 PM PST 23 |
Dec 31 01:05:14 PM PST 23 |
1295562979 ps |
| T729 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1130993828 |
|
|
Dec 31 01:06:42 PM PST 23 |
Dec 31 01:13:05 PM PST 23 |
122930962591 ps |
| T730 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.462908943 |
|
|
Dec 31 01:05:07 PM PST 23 |
Dec 31 01:06:48 PM PST 23 |
767905579 ps |
| T731 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.1815335609 |
|
|
Dec 31 01:06:42 PM PST 23 |
Dec 31 01:08:38 PM PST 23 |
1995547510 ps |
| T732 |
/workspace/coverage/default/26.sram_ctrl_bijection.3015993934 |
|
|
Dec 31 01:05:04 PM PST 23 |
Dec 31 01:31:59 PM PST 23 |
96643938879 ps |
| T733 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3806894956 |
|
|
Dec 31 01:04:44 PM PST 23 |
Dec 31 01:06:12 PM PST 23 |
14577245749 ps |
| T734 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1012932154 |
|
|
Dec 31 01:05:25 PM PST 23 |
Dec 31 01:07:55 PM PST 23 |
22619464008 ps |
| T735 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.717617750 |
|
|
Dec 31 01:06:21 PM PST 23 |
Dec 31 01:11:00 PM PST 23 |
7428037937 ps |
| T736 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.1993383835 |
|
|
Dec 31 01:04:00 PM PST 23 |
Dec 31 01:06:47 PM PST 23 |
47467862966 ps |
| T737 |
/workspace/coverage/default/45.sram_ctrl_executable.1608166710 |
|
|
Dec 31 01:06:19 PM PST 23 |
Dec 31 01:16:34 PM PST 23 |
36660766557 ps |
| T738 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4232814767 |
|
|
Dec 31 01:03:41 PM PST 23 |
Dec 31 02:10:07 PM PST 23 |
4519047986 ps |
| T739 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.657260832 |
|
|
Dec 31 01:06:44 PM PST 23 |
Dec 31 01:08:39 PM PST 23 |
815565665 ps |
| T740 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1956263053 |
|
|
Dec 31 01:06:43 PM PST 23 |
Dec 31 01:08:35 PM PST 23 |
19226996061 ps |
| T741 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2790583234 |
|
|
Dec 31 01:04:37 PM PST 23 |
Dec 31 01:23:25 PM PST 23 |
65318695243 ps |
| T742 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.3727570037 |
|
|
Dec 31 01:04:49 PM PST 23 |
Dec 31 01:10:01 PM PST 23 |
89932459657 ps |
| T743 |
/workspace/coverage/default/43.sram_ctrl_bijection.3185751174 |
|
|
Dec 31 01:06:03 PM PST 23 |
Dec 31 01:39:41 PM PST 23 |
34336874396 ps |
| T744 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.3101549507 |
|
|
Dec 31 01:04:43 PM PST 23 |
Dec 31 01:09:23 PM PST 23 |
3254451825 ps |
| T745 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.4124180784 |
|
|
Dec 31 01:05:00 PM PST 23 |
Dec 31 01:05:54 PM PST 23 |
2857692251 ps |
| T746 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.4286044717 |
|
|
Dec 31 01:05:29 PM PST 23 |
Dec 31 01:08:03 PM PST 23 |
13944619102 ps |
| T747 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3395989382 |
|
|
Dec 31 01:06:26 PM PST 23 |
Dec 31 01:07:33 PM PST 23 |
743904431 ps |
| T748 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.965737893 |
|
|
Dec 31 01:05:08 PM PST 23 |
Dec 31 01:06:13 PM PST 23 |
717424124 ps |
| T749 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.581560304 |
|
|
Dec 31 01:06:17 PM PST 23 |
Dec 31 01:07:56 PM PST 23 |
4930085507 ps |
| T750 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1961728026 |
|
|
Dec 31 01:04:10 PM PST 23 |
Dec 31 01:05:05 PM PST 23 |
787771404 ps |