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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total test records in report: 979
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T751 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.127972534 Dec 31 01:04:52 PM PST 23 Dec 31 01:07:30 PM PST 23 18966512737 ps
T752 /workspace/coverage/default/22.sram_ctrl_ram_cfg.2793670600 Dec 31 01:04:47 PM PST 23 Dec 31 01:04:56 PM PST 23 366098721 ps
T753 /workspace/coverage/default/45.sram_ctrl_smoke.925201667 Dec 31 01:06:22 PM PST 23 Dec 31 01:06:47 PM PST 23 1320713724 ps
T754 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2954327544 Dec 31 01:06:27 PM PST 23 Dec 31 01:29:39 PM PST 23 1069646839 ps
T755 /workspace/coverage/default/10.sram_ctrl_partial_access.3629458997 Dec 31 01:04:22 PM PST 23 Dec 31 01:07:16 PM PST 23 5276930718 ps
T756 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2497122425 Dec 31 01:04:56 PM PST 23 Dec 31 01:11:36 PM PST 23 19986042302 ps
T757 /workspace/coverage/default/47.sram_ctrl_bijection.3483911329 Dec 31 01:06:48 PM PST 23 Dec 31 01:34:38 PM PST 23 335287939329 ps
T758 /workspace/coverage/default/4.sram_ctrl_stress_all.2913308319 Dec 31 01:04:17 PM PST 23 Dec 31 02:33:20 PM PST 23 396466327358 ps
T759 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1620071438 Dec 31 01:05:05 PM PST 23 Dec 31 01:05:21 PM PST 23 1352567557 ps
T760 /workspace/coverage/default/9.sram_ctrl_bijection.1639553351 Dec 31 01:04:28 PM PST 23 Dec 31 01:17:14 PM PST 23 45120682787 ps
T761 /workspace/coverage/default/48.sram_ctrl_max_throughput.4277632440 Dec 31 01:06:43 PM PST 23 Dec 31 01:09:14 PM PST 23 1530053086 ps
T762 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.515511919 Dec 31 01:04:43 PM PST 23 Dec 31 01:08:03 PM PST 23 2247424830 ps
T763 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1731656714 Dec 31 01:04:07 PM PST 23 Dec 31 01:08:36 PM PST 23 6803962003 ps
T764 /workspace/coverage/default/26.sram_ctrl_regwen.3350349993 Dec 31 01:05:09 PM PST 23 Dec 31 01:08:34 PM PST 23 31344899083 ps
T765 /workspace/coverage/default/5.sram_ctrl_mem_walk.1111300921 Dec 31 01:04:34 PM PST 23 Dec 31 01:07:09 PM PST 23 7094415054 ps
T766 /workspace/coverage/default/9.sram_ctrl_ram_cfg.3811572250 Dec 31 01:04:26 PM PST 23 Dec 31 01:04:42 PM PST 23 361113328 ps
T767 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.936089178 Dec 31 01:04:02 PM PST 23 Dec 31 01:04:32 PM PST 23 5560132534 ps
T768 /workspace/coverage/default/35.sram_ctrl_lc_escalation.2949890749 Dec 31 01:05:44 PM PST 23 Dec 31 01:06:28 PM PST 23 4067902422 ps
T769 /workspace/coverage/default/48.sram_ctrl_bijection.65674261 Dec 31 01:06:44 PM PST 23 Dec 31 01:23:03 PM PST 23 14926807724 ps
T770 /workspace/coverage/default/6.sram_ctrl_mem_walk.617945254 Dec 31 01:04:14 PM PST 23 Dec 31 01:06:38 PM PST 23 9552109326 ps
T771 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2814274434 Dec 31 01:04:53 PM PST 23 Dec 31 01:09:35 PM PST 23 7812663218 ps
T772 /workspace/coverage/default/49.sram_ctrl_ram_cfg.802005859 Dec 31 01:06:46 PM PST 23 Dec 31 01:07:06 PM PST 23 1458833157 ps
T773 /workspace/coverage/default/15.sram_ctrl_multiple_keys.701946842 Dec 31 01:04:29 PM PST 23 Dec 31 01:29:12 PM PST 23 15972419442 ps
T774 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3497362208 Dec 31 01:06:45 PM PST 23 Dec 31 01:50:31 PM PST 23 1314470011 ps
T775 /workspace/coverage/default/21.sram_ctrl_bijection.3876593511 Dec 31 01:04:53 PM PST 23 Dec 31 01:14:12 PM PST 23 48552325364 ps
T776 /workspace/coverage/default/5.sram_ctrl_executable.2788242536 Dec 31 01:04:07 PM PST 23 Dec 31 01:31:00 PM PST 23 92315044070 ps
T777 /workspace/coverage/default/7.sram_ctrl_executable.1255380294 Dec 31 01:04:25 PM PST 23 Dec 31 01:15:37 PM PST 23 26540260577 ps
T778 /workspace/coverage/default/2.sram_ctrl_lc_escalation.2743508494 Dec 31 01:04:32 PM PST 23 Dec 31 01:05:57 PM PST 23 138514052833 ps
T779 /workspace/coverage/default/27.sram_ctrl_bijection.4043366222 Dec 31 01:05:28 PM PST 23 Dec 31 01:43:21 PM PST 23 345406846004 ps
T780 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3540927880 Dec 31 01:05:40 PM PST 23 Dec 31 01:22:40 PM PST 23 30514953564 ps
T781 /workspace/coverage/default/20.sram_ctrl_regwen.3606592222 Dec 31 01:04:51 PM PST 23 Dec 31 01:13:50 PM PST 23 39438986217 ps
T782 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2939491386 Dec 31 01:05:41 PM PST 23 Dec 31 01:09:33 PM PST 23 2899748194 ps
T783 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.245339946 Dec 31 01:04:53 PM PST 23 Dec 31 01:38:56 PM PST 23 1199579528 ps
T784 /workspace/coverage/default/9.sram_ctrl_mem_walk.546717755 Dec 31 01:04:29 PM PST 23 Dec 31 01:06:33 PM PST 23 2061239969 ps
T785 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2874650838 Dec 31 01:05:32 PM PST 23 Dec 31 01:06:03 PM PST 23 5654497623 ps
T786 /workspace/coverage/default/43.sram_ctrl_multiple_keys.4209148328 Dec 31 01:06:31 PM PST 23 Dec 31 01:24:23 PM PST 23 38313714171 ps
T787 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1574597954 Dec 31 01:04:31 PM PST 23 Dec 31 02:09:32 PM PST 23 1099152857 ps
T788 /workspace/coverage/default/15.sram_ctrl_smoke.1700930767 Dec 31 01:04:33 PM PST 23 Dec 31 01:04:53 PM PST 23 948562437 ps
T789 /workspace/coverage/default/1.sram_ctrl_mem_walk.1865622201 Dec 31 01:04:15 PM PST 23 Dec 31 01:06:32 PM PST 23 6899645842 ps
T790 /workspace/coverage/default/1.sram_ctrl_ram_cfg.843487656 Dec 31 01:03:57 PM PST 23 Dec 31 01:04:05 PM PST 23 348467057 ps
T791 /workspace/coverage/default/41.sram_ctrl_bijection.730281498 Dec 31 01:06:26 PM PST 23 Dec 31 01:32:40 PM PST 23 349091148021 ps
T792 /workspace/coverage/default/23.sram_ctrl_smoke.2392343287 Dec 31 01:04:51 PM PST 23 Dec 31 01:07:26 PM PST 23 1768800498 ps
T793 /workspace/coverage/default/25.sram_ctrl_ram_cfg.1632326401 Dec 31 01:05:07 PM PST 23 Dec 31 01:05:22 PM PST 23 719900901 ps
T794 /workspace/coverage/default/21.sram_ctrl_max_throughput.882471632 Dec 31 01:04:54 PM PST 23 Dec 31 01:05:55 PM PST 23 780312874 ps
T795 /workspace/coverage/default/28.sram_ctrl_regwen.2023337552 Dec 31 01:05:27 PM PST 23 Dec 31 01:17:41 PM PST 23 12944816898 ps
T796 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.69083796 Dec 31 01:05:44 PM PST 23 Dec 31 01:14:23 PM PST 23 22941502188 ps
T797 /workspace/coverage/default/39.sram_ctrl_multiple_keys.1323000499 Dec 31 01:05:41 PM PST 23 Dec 31 01:16:40 PM PST 23 6617437062 ps
T798 /workspace/coverage/default/42.sram_ctrl_lc_escalation.3458807082 Dec 31 01:06:31 PM PST 23 Dec 31 01:08:49 PM PST 23 14999743061 ps
T799 /workspace/coverage/default/27.sram_ctrl_executable.1797170336 Dec 31 01:05:43 PM PST 23 Dec 31 01:17:36 PM PST 23 13177850753 ps
T800 /workspace/coverage/default/26.sram_ctrl_smoke.40827714 Dec 31 01:05:31 PM PST 23 Dec 31 01:06:08 PM PST 23 698072353 ps
T801 /workspace/coverage/default/8.sram_ctrl_multiple_keys.2729890453 Dec 31 01:04:17 PM PST 23 Dec 31 01:06:31 PM PST 23 1766303141 ps
T802 /workspace/coverage/default/14.sram_ctrl_lc_escalation.3920341383 Dec 31 01:04:34 PM PST 23 Dec 31 01:05:37 PM PST 23 17314786238 ps
T803 /workspace/coverage/default/37.sram_ctrl_multiple_keys.3445021797 Dec 31 01:05:48 PM PST 23 Dec 31 01:26:06 PM PST 23 14924011053 ps
T804 /workspace/coverage/default/18.sram_ctrl_ram_cfg.875998916 Dec 31 01:04:38 PM PST 23 Dec 31 01:04:48 PM PST 23 385128401 ps
T805 /workspace/coverage/default/48.sram_ctrl_lc_escalation.3026860455 Dec 31 01:06:46 PM PST 23 Dec 31 01:10:42 PM PST 23 12441569414 ps
T806 /workspace/coverage/default/34.sram_ctrl_stress_all.4240220375 Dec 31 01:05:42 PM PST 23 Dec 31 02:00:24 PM PST 23 65108840533 ps
T807 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.107983790 Dec 31 01:04:17 PM PST 23 Dec 31 01:34:44 PM PST 23 47133406242 ps
T808 /workspace/coverage/default/49.sram_ctrl_stress_all.105687938 Dec 31 01:06:46 PM PST 23 Dec 31 02:35:39 PM PST 23 1029907390921 ps
T809 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.4088504497 Dec 31 01:06:16 PM PST 23 Dec 31 01:08:28 PM PST 23 3167887639 ps
T810 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3553167637 Dec 31 01:04:10 PM PST 23 Dec 31 01:05:27 PM PST 23 770494565 ps
T811 /workspace/coverage/default/47.sram_ctrl_smoke.3234634123 Dec 31 01:06:23 PM PST 23 Dec 31 01:07:24 PM PST 23 744365748 ps
T812 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2230547537 Dec 31 01:05:08 PM PST 23 Dec 31 01:11:30 PM PST 23 27798735295 ps
T813 /workspace/coverage/default/29.sram_ctrl_multiple_keys.1158079523 Dec 31 01:05:03 PM PST 23 Dec 31 01:26:56 PM PST 23 14799399232 ps
T814 /workspace/coverage/default/11.sram_ctrl_partial_access.1067173630 Dec 31 01:04:32 PM PST 23 Dec 31 01:04:52 PM PST 23 3361926735 ps
T815 /workspace/coverage/default/8.sram_ctrl_regwen.246486005 Dec 31 01:04:31 PM PST 23 Dec 31 01:19:53 PM PST 23 5969485860 ps
T816 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.376301187 Dec 31 01:05:06 PM PST 23 Dec 31 01:06:22 PM PST 23 767589248 ps
T817 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1577218502 Dec 31 01:05:43 PM PST 23 Dec 31 01:06:22 PM PST 23 11465027187 ps
T818 /workspace/coverage/default/4.sram_ctrl_max_throughput.2688720997 Dec 31 01:04:17 PM PST 23 Dec 31 01:05:55 PM PST 23 758238639 ps
T819 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3479176637 Dec 31 01:04:39 PM PST 23 Dec 31 01:12:12 PM PST 23 6683029977 ps
T820 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2675847624 Dec 31 01:04:54 PM PST 23 Dec 31 01:07:31 PM PST 23 3075297309 ps
T821 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1659747964 Dec 31 01:04:31 PM PST 23 Dec 31 01:06:55 PM PST 23 12865017403 ps
T822 /workspace/coverage/default/9.sram_ctrl_lc_escalation.4258382516 Dec 31 01:04:24 PM PST 23 Dec 31 01:06:37 PM PST 23 29939237001 ps
T823 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2957576149 Dec 31 01:04:55 PM PST 23 Dec 31 01:06:08 PM PST 23 3779130556 ps
T824 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.1690232479 Dec 31 01:06:16 PM PST 23 Dec 31 01:08:37 PM PST 23 6253421480 ps
T825 /workspace/coverage/default/46.sram_ctrl_smoke.3406060038 Dec 31 01:06:45 PM PST 23 Dec 31 01:07:01 PM PST 23 587111369 ps
T826 /workspace/coverage/default/48.sram_ctrl_stress_all.1726070615 Dec 31 01:06:45 PM PST 23 Dec 31 02:22:38 PM PST 23 136707048623 ps
T827 /workspace/coverage/default/24.sram_ctrl_smoke.4216941143 Dec 31 01:04:54 PM PST 23 Dec 31 01:05:07 PM PST 23 456104073 ps
T828 /workspace/coverage/default/17.sram_ctrl_stress_all.3484830138 Dec 31 01:04:22 PM PST 23 Dec 31 01:43:41 PM PST 23 37795095543 ps
T829 /workspace/coverage/default/7.sram_ctrl_partial_access.846628446 Dec 31 01:04:07 PM PST 23 Dec 31 01:04:22 PM PST 23 754574460 ps
T830 /workspace/coverage/default/3.sram_ctrl_bijection.384017241 Dec 31 01:03:39 PM PST 23 Dec 31 01:39:27 PM PST 23 564342250595 ps
T831 /workspace/coverage/default/17.sram_ctrl_bijection.796843239 Dec 31 01:04:37 PM PST 23 Dec 31 01:29:59 PM PST 23 518911125774 ps
T832 /workspace/coverage/default/9.sram_ctrl_alert_test.3660053631 Dec 31 01:04:20 PM PST 23 Dec 31 01:04:22 PM PST 23 12810506 ps
T833 /workspace/coverage/default/11.sram_ctrl_smoke.1133640007 Dec 31 01:04:40 PM PST 23 Dec 31 01:05:17 PM PST 23 6902986382 ps
T834 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.106988317 Dec 31 01:06:19 PM PST 23 Dec 31 01:07:39 PM PST 23 2354572555 ps
T835 /workspace/coverage/default/35.sram_ctrl_regwen.3293730094 Dec 31 01:05:39 PM PST 23 Dec 31 01:16:54 PM PST 23 13727273686 ps
T836 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.2658568810 Dec 31 01:05:05 PM PST 23 Dec 31 01:11:45 PM PST 23 4860275007 ps
T837 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.17526198 Dec 31 01:06:46 PM PST 23 Dec 31 01:09:23 PM PST 23 18986845350 ps
T838 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.4082324526 Dec 31 01:06:41 PM PST 23 Dec 31 01:09:23 PM PST 23 18252954571 ps
T839 /workspace/coverage/default/0.sram_ctrl_max_throughput.2307884060 Dec 31 01:04:08 PM PST 23 Dec 31 01:04:58 PM PST 23 757797840 ps
T840 /workspace/coverage/default/45.sram_ctrl_bijection.3570823034 Dec 31 01:06:27 PM PST 23 Dec 31 01:18:48 PM PST 23 231565510828 ps
T841 /workspace/coverage/default/10.sram_ctrl_mem_walk.1338357036 Dec 31 01:04:21 PM PST 23 Dec 31 01:06:37 PM PST 23 19728870171 ps
T842 /workspace/coverage/default/16.sram_ctrl_mem_walk.4161009375 Dec 31 01:04:36 PM PST 23 Dec 31 01:08:37 PM PST 23 4106674018 ps
T843 /workspace/coverage/default/29.sram_ctrl_lc_escalation.2535022422 Dec 31 01:05:03 PM PST 23 Dec 31 01:05:37 PM PST 23 2332767141 ps
T844 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2731652989 Dec 31 01:04:02 PM PST 23 Dec 31 01:08:46 PM PST 23 44592055847 ps
T845 /workspace/coverage/default/32.sram_ctrl_smoke.987121202 Dec 31 01:05:32 PM PST 23 Dec 31 01:05:56 PM PST 23 5415286074 ps
T846 /workspace/coverage/default/18.sram_ctrl_stress_all.3842059303 Dec 31 01:04:38 PM PST 23 Dec 31 01:47:28 PM PST 23 43323541802 ps
T847 /workspace/coverage/default/21.sram_ctrl_partial_access.1652890199 Dec 31 01:04:47 PM PST 23 Dec 31 01:05:19 PM PST 23 2030190025 ps
T848 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2296947248 Dec 31 01:04:18 PM PST 23 Dec 31 02:18:33 PM PST 23 3211645377 ps
T849 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1693633543 Dec 31 01:05:41 PM PST 23 Dec 31 01:08:06 PM PST 23 7367243182 ps
T850 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.555121473 Dec 31 01:05:42 PM PST 23 Dec 31 01:26:07 PM PST 23 41294396578 ps
T851 /workspace/coverage/default/11.sram_ctrl_regwen.3223554572 Dec 31 01:04:30 PM PST 23 Dec 31 01:14:13 PM PST 23 22807529879 ps
T852 /workspace/coverage/default/32.sram_ctrl_mem_walk.356183264 Dec 31 01:05:32 PM PST 23 Dec 31 01:10:43 PM PST 23 28095171154 ps
T853 /workspace/coverage/default/48.sram_ctrl_smoke.1466954227 Dec 31 01:06:27 PM PST 23 Dec 31 01:07:35 PM PST 23 425894169 ps
T854 /workspace/coverage/default/36.sram_ctrl_mem_walk.1838776846 Dec 31 01:05:43 PM PST 23 Dec 31 01:11:05 PM PST 23 86070594720 ps
T855 /workspace/coverage/default/14.sram_ctrl_multiple_keys.3497508145 Dec 31 01:04:25 PM PST 23 Dec 31 01:14:12 PM PST 23 15208660073 ps
T856 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2301359695 Dec 31 01:05:07 PM PST 23 Dec 31 01:15:30 PM PST 23 5085708331 ps
T857 /workspace/coverage/default/11.sram_ctrl_bijection.1688602999 Dec 31 01:04:31 PM PST 23 Dec 31 01:23:13 PM PST 23 200896199585 ps
T858 /workspace/coverage/default/21.sram_ctrl_multiple_keys.3099661077 Dec 31 01:04:52 PM PST 23 Dec 31 01:06:07 PM PST 23 2506377885 ps
T859 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.4271565423 Dec 31 01:04:52 PM PST 23 Dec 31 01:06:16 PM PST 23 2977474010 ps
T860 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1934619835 Dec 31 01:05:32 PM PST 23 Dec 31 01:12:18 PM PST 23 62632946561 ps
T861 /workspace/coverage/default/44.sram_ctrl_regwen.1211927366 Dec 31 01:06:26 PM PST 23 Dec 31 01:09:20 PM PST 23 1583273558 ps
T862 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.4149336201 Dec 31 01:05:43 PM PST 23 Dec 31 01:07:52 PM PST 23 1637085584 ps
T863 /workspace/coverage/default/26.sram_ctrl_lc_escalation.3810369272 Dec 31 01:05:04 PM PST 23 Dec 31 01:08:27 PM PST 23 66257961332 ps
T864 /workspace/coverage/default/6.sram_ctrl_executable.786688705 Dec 31 01:04:20 PM PST 23 Dec 31 01:07:33 PM PST 23 11037789898 ps
T865 /workspace/coverage/default/24.sram_ctrl_partial_access.889770963 Dec 31 01:04:58 PM PST 23 Dec 31 01:05:13 PM PST 23 1473575081 ps
T866 /workspace/coverage/default/40.sram_ctrl_bijection.440179957 Dec 31 01:05:40 PM PST 23 Dec 31 01:48:57 PM PST 23 161892151400 ps
T867 /workspace/coverage/default/31.sram_ctrl_ram_cfg.3091572022 Dec 31 01:05:09 PM PST 23 Dec 31 01:05:16 PM PST 23 347020244 ps
T868 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.465786670 Dec 31 01:04:30 PM PST 23 Dec 31 02:31:10 PM PST 23 1131063072 ps
T869 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3060319359 Dec 31 01:05:31 PM PST 23 Dec 31 01:08:50 PM PST 23 9596559742 ps
T870 /workspace/coverage/default/47.sram_ctrl_multiple_keys.1101862132 Dec 31 01:06:44 PM PST 23 Dec 31 01:10:45 PM PST 23 26309756813 ps
T871 /workspace/coverage/default/42.sram_ctrl_max_throughput.1544680158 Dec 31 01:06:16 PM PST 23 Dec 31 01:07:44 PM PST 23 2961178272 ps
T872 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2749337298 Dec 31 01:05:43 PM PST 23 Dec 31 01:10:14 PM PST 23 6841064091 ps
T873 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2135056229 Dec 31 01:04:22 PM PST 23 Dec 31 01:09:41 PM PST 23 19922710246 ps
T874 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2807495941 Dec 31 01:04:36 PM PST 23 Dec 31 01:10:54 PM PST 23 9957370515 ps
T875 /workspace/coverage/default/12.sram_ctrl_bijection.402609615 Dec 31 01:04:34 PM PST 23 Dec 31 01:27:53 PM PST 23 71433917387 ps
T876 /workspace/coverage/default/44.sram_ctrl_max_throughput.3239593177 Dec 31 01:06:18 PM PST 23 Dec 31 01:06:53 PM PST 23 721486047 ps
T877 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.911838724 Dec 31 01:04:33 PM PST 23 Dec 31 01:07:17 PM PST 23 3254128400 ps
T878 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2037044482 Dec 31 01:06:05 PM PST 23 Dec 31 01:08:31 PM PST 23 7048854041 ps
T879 /workspace/coverage/default/26.sram_ctrl_stress_all.2876793490 Dec 31 01:05:06 PM PST 23 Dec 31 01:55:24 PM PST 23 321780712278 ps
T880 /workspace/coverage/default/37.sram_ctrl_mem_walk.3030518479 Dec 31 01:05:41 PM PST 23 Dec 31 01:09:58 PM PST 23 8211251765 ps
T881 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2745627705 Dec 31 01:04:23 PM PST 23 Dec 31 01:05:47 PM PST 23 5109953882 ps
T882 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.3128695338 Dec 31 01:05:42 PM PST 23 Dec 31 01:13:09 PM PST 23 23338683250 ps
T883 /workspace/coverage/default/5.sram_ctrl_bijection.1481760605 Dec 31 01:04:03 PM PST 23 Dec 31 01:39:12 PM PST 23 136606883451 ps
T884 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3231616476 Dec 31 01:05:07 PM PST 23 Dec 31 01:09:46 PM PST 23 25777296282 ps
T885 /workspace/coverage/default/9.sram_ctrl_partial_access.2802199588 Dec 31 01:04:23 PM PST 23 Dec 31 01:04:42 PM PST 23 7988709352 ps
T886 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2803936362 Dec 31 01:06:25 PM PST 23 Dec 31 01:26:54 PM PST 23 10721002893 ps
T887 /workspace/coverage/default/15.sram_ctrl_stress_all.561884112 Dec 31 01:04:31 PM PST 23 Dec 31 02:02:31 PM PST 23 354397750654 ps
T888 /workspace/coverage/default/9.sram_ctrl_regwen.3353182291 Dec 31 01:04:32 PM PST 23 Dec 31 01:05:37 PM PST 23 7856615133 ps
T889 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3134075673 Dec 31 01:06:42 PM PST 23 Dec 31 01:09:53 PM PST 23 2313676972 ps
T890 /workspace/coverage/default/20.sram_ctrl_smoke.1092858295 Dec 31 01:04:52 PM PST 23 Dec 31 01:05:57 PM PST 23 3336691303 ps
T891 /workspace/coverage/default/45.sram_ctrl_max_throughput.4070665167 Dec 31 01:06:43 PM PST 23 Dec 31 01:09:34 PM PST 23 1530209910 ps
T892 /workspace/coverage/default/22.sram_ctrl_regwen.3455495496 Dec 31 01:04:46 PM PST 23 Dec 31 01:27:55 PM PST 23 76272798535 ps
T893 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1439294004 Dec 31 01:03:46 PM PST 23 Dec 31 01:11:46 PM PST 23 7542062400 ps
T894 /workspace/coverage/default/16.sram_ctrl_multiple_keys.1872141658 Dec 31 01:04:28 PM PST 23 Dec 31 01:14:40 PM PST 23 13134578439 ps
T895 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1451391923 Dec 31 01:04:48 PM PST 23 Dec 31 01:07:14 PM PST 23 1640659404 ps
T896 /workspace/coverage/default/44.sram_ctrl_partial_access.3464993423 Dec 31 01:06:44 PM PST 23 Dec 31 01:08:01 PM PST 23 1129293258 ps
T897 /workspace/coverage/default/22.sram_ctrl_stress_all.3500340993 Dec 31 01:04:47 PM PST 23 Dec 31 02:56:51 PM PST 23 871849528465 ps
T898 /workspace/coverage/default/31.sram_ctrl_mem_walk.2105427602 Dec 31 01:05:08 PM PST 23 Dec 31 01:10:44 PM PST 23 82655893541 ps
T899 /workspace/coverage/default/36.sram_ctrl_partial_access.2879902511 Dec 31 01:05:45 PM PST 23 Dec 31 01:06:16 PM PST 23 3779026728 ps
T900 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2464960611 Dec 31 01:06:25 PM PST 23 Dec 31 01:11:45 PM PST 23 4896248865 ps
T901 /workspace/coverage/default/28.sram_ctrl_smoke.1972124904 Dec 31 01:05:30 PM PST 23 Dec 31 01:05:59 PM PST 23 754884239 ps
T902 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2785378907 Dec 31 01:06:44 PM PST 23 Dec 31 01:08:03 PM PST 23 1931298380 ps
T903 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1593576680 Dec 31 01:05:47 PM PST 23 Dec 31 02:47:05 PM PST 23 3596361821 ps
T904 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1734046344 Dec 31 01:05:44 PM PST 23 Dec 31 01:06:26 PM PST 23 738287497 ps
T905 /workspace/coverage/default/16.sram_ctrl_partial_access.4167595816 Dec 31 01:04:33 PM PST 23 Dec 31 01:05:07 PM PST 23 3212344369 ps
T906 /workspace/coverage/default/21.sram_ctrl_regwen.2536475031 Dec 31 01:04:48 PM PST 23 Dec 31 01:23:01 PM PST 23 57232774073 ps
T907 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.4076253261 Dec 31 01:04:58 PM PST 23 Dec 31 01:19:55 PM PST 23 6025540943 ps
T908 /workspace/coverage/default/10.sram_ctrl_ram_cfg.1821667050 Dec 31 01:04:19 PM PST 23 Dec 31 01:04:36 PM PST 23 3726570636 ps
T909 /workspace/coverage/default/41.sram_ctrl_alert_test.3938253445 Dec 31 01:06:18 PM PST 23 Dec 31 01:06:23 PM PST 23 21916709 ps
T910 /workspace/coverage/default/17.sram_ctrl_executable.2792804561 Dec 31 01:04:27 PM PST 23 Dec 31 01:35:55 PM PST 23 25286147141 ps
T911 /workspace/coverage/default/8.sram_ctrl_executable.2018051106 Dec 31 01:03:59 PM PST 23 Dec 31 01:27:02 PM PST 23 258856619990 ps
T912 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1648353812 Dec 31 01:04:24 PM PST 23 Dec 31 01:29:37 PM PST 23 22020219226 ps
T913 /workspace/coverage/default/20.sram_ctrl_lc_escalation.1294204499 Dec 31 01:04:58 PM PST 23 Dec 31 01:07:23 PM PST 23 94155406262 ps
T914 /workspace/coverage/default/28.sram_ctrl_partial_access.3883598921 Dec 31 01:05:09 PM PST 23 Dec 31 01:05:38 PM PST 23 1545871480 ps
T915 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.93781670 Dec 31 01:05:31 PM PST 23 Dec 31 01:10:56 PM PST 23 5031428113 ps
T916 /workspace/coverage/default/36.sram_ctrl_regwen.1003453326 Dec 31 01:05:49 PM PST 23 Dec 31 01:27:47 PM PST 23 19836741358 ps
T917 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1472638472 Dec 31 01:05:15 PM PST 23 Dec 31 01:11:45 PM PST 23 10234424840 ps
T918 /workspace/coverage/default/34.sram_ctrl_max_throughput.2450588319 Dec 31 01:05:45 PM PST 23 Dec 31 01:06:54 PM PST 23 2488929559 ps
T919 /workspace/coverage/default/9.sram_ctrl_executable.540058604 Dec 31 01:04:29 PM PST 23 Dec 31 01:07:33 PM PST 23 3527836903 ps
T920 /workspace/coverage/default/32.sram_ctrl_regwen.508542335 Dec 31 01:05:41 PM PST 23 Dec 31 01:18:14 PM PST 23 17072351330 ps
T921 /workspace/coverage/default/37.sram_ctrl_stress_all.173411830 Dec 31 01:05:41 PM PST 23 Dec 31 02:21:29 PM PST 23 75458837155 ps
T922 /workspace/coverage/default/15.sram_ctrl_mem_walk.2158925593 Dec 31 01:04:21 PM PST 23 Dec 31 01:06:30 PM PST 23 3947672534 ps
T923 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.289813627 Dec 31 01:04:23 PM PST 23 Dec 31 01:06:51 PM PST 23 4455348352 ps
T924 /workspace/coverage/default/32.sram_ctrl_multiple_keys.1600024873 Dec 31 01:05:31 PM PST 23 Dec 31 01:27:10 PM PST 23 37748549477 ps
T925 /workspace/coverage/default/0.sram_ctrl_lc_escalation.2784751360 Dec 31 01:03:39 PM PST 23 Dec 31 01:05:23 PM PST 23 18136809770 ps
T926 /workspace/coverage/default/12.sram_ctrl_lc_escalation.3991296232 Dec 31 01:04:23 PM PST 23 Dec 31 01:05:52 PM PST 23 8988380335 ps
T927 /workspace/coverage/default/14.sram_ctrl_bijection.2131873546 Dec 31 01:04:21 PM PST 23 Dec 31 01:25:11 PM PST 23 203278571838 ps
T928 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.427054960 Dec 31 01:04:09 PM PST 23 Dec 31 01:31:35 PM PST 23 10104864709 ps
T929 /workspace/coverage/default/37.sram_ctrl_alert_test.698622887 Dec 31 01:05:42 PM PST 23 Dec 31 01:05:46 PM PST 23 48498377 ps
T930 /workspace/coverage/default/13.sram_ctrl_alert_test.453959174 Dec 31 01:04:38 PM PST 23 Dec 31 01:04:45 PM PST 23 41661438 ps
T931 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3321023334 Dec 31 01:04:45 PM PST 23 Dec 31 01:35:31 PM PST 23 3245525482 ps
T932 /workspace/coverage/default/31.sram_ctrl_smoke.3060458061 Dec 31 01:05:04 PM PST 23 Dec 31 01:05:43 PM PST 23 817819836 ps
T933 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.82294278 Dec 31 01:05:07 PM PST 23 Dec 31 01:06:12 PM PST 23 4917630696 ps
T934 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1055603694 Dec 31 01:06:25 PM PST 23 Dec 31 01:07:29 PM PST 23 3830590452 ps
T935 /workspace/coverage/default/32.sram_ctrl_bijection.50310491 Dec 31 01:05:30 PM PST 23 Dec 31 01:20:14 PM PST 23 217732204421 ps
T936 /workspace/coverage/default/1.sram_ctrl_partial_access.2936971784 Dec 31 01:04:18 PM PST 23 Dec 31 01:05:05 PM PST 23 2018623712 ps
T937 /workspace/coverage/default/0.sram_ctrl_ram_cfg.462648484 Dec 31 01:04:19 PM PST 23 Dec 31 01:04:36 PM PST 23 696296750 ps
T938 /workspace/coverage/default/45.sram_ctrl_regwen.2248426700 Dec 31 01:06:25 PM PST 23 Dec 31 01:16:57 PM PST 23 1689128060 ps
T939 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3451018368 Dec 31 01:04:07 PM PST 23 Dec 31 01:37:17 PM PST 23 1095067334 ps
T940 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.4000281805 Dec 31 01:05:06 PM PST 23 Dec 31 01:07:33 PM PST 23 3499530115 ps
T941 /workspace/coverage/default/33.sram_ctrl_regwen.1468301971 Dec 31 01:05:32 PM PST 23 Dec 31 01:21:26 PM PST 23 14824747070 ps
T942 /workspace/coverage/default/34.sram_ctrl_regwen.2864799389 Dec 31 01:05:42 PM PST 23 Dec 31 01:06:17 PM PST 23 523873296 ps
T943 /workspace/coverage/default/15.sram_ctrl_ram_cfg.59428818 Dec 31 01:04:30 PM PST 23 Dec 31 01:04:40 PM PST 23 1244690452 ps
T944 /workspace/coverage/default/19.sram_ctrl_lc_escalation.1108163772 Dec 31 01:04:48 PM PST 23 Dec 31 01:05:30 PM PST 23 14796063790 ps
T945 /workspace/coverage/default/41.sram_ctrl_regwen.2986502320 Dec 31 01:06:17 PM PST 23 Dec 31 01:09:30 PM PST 23 6400776775 ps
T946 /workspace/coverage/default/23.sram_ctrl_mem_walk.380369691 Dec 31 01:04:55 PM PST 23 Dec 31 01:09:07 PM PST 23 26263021010 ps
T947 /workspace/coverage/default/6.sram_ctrl_smoke.1319606504 Dec 31 01:04:19 PM PST 23 Dec 31 01:04:33 PM PST 23 5911659002 ps
T948 /workspace/coverage/default/16.sram_ctrl_lc_escalation.410110614 Dec 31 01:04:41 PM PST 23 Dec 31 01:05:12 PM PST 23 747983017 ps
T949 /workspace/coverage/default/27.sram_ctrl_alert_test.3845306343 Dec 31 01:05:27 PM PST 23 Dec 31 01:05:28 PM PST 23 35199752 ps
T950 /workspace/coverage/default/14.sram_ctrl_regwen.4115412946 Dec 31 01:04:31 PM PST 23 Dec 31 01:06:07 PM PST 23 1742115914 ps
T951 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.168760242 Dec 31 01:04:37 PM PST 23 Dec 31 01:35:22 PM PST 23 13633936320 ps
T952 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1207703133 Dec 31 01:04:16 PM PST 23 Dec 31 01:09:48 PM PST 23 10765090558 ps
T953 /workspace/coverage/default/17.sram_ctrl_multiple_keys.3106162155 Dec 31 01:04:23 PM PST 23 Dec 31 01:26:00 PM PST 23 58849168022 ps
T954 /workspace/coverage/default/8.sram_ctrl_partial_access.3199656068 Dec 31 01:04:16 PM PST 23 Dec 31 01:04:46 PM PST 23 2373893963 ps
T955 /workspace/coverage/default/48.sram_ctrl_regwen.2830182696 Dec 31 01:06:26 PM PST 23 Dec 31 01:24:10 PM PST 23 6858168453 ps
T956 /workspace/coverage/default/17.sram_ctrl_smoke.1243636463 Dec 31 01:04:34 PM PST 23 Dec 31 01:04:52 PM PST 23 746695152 ps
T957 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3948475680 Dec 31 01:04:18 PM PST 23 Dec 31 01:11:33 PM PST 23 12916352414 ps
T958 /workspace/coverage/default/11.sram_ctrl_executable.843659091 Dec 31 01:04:28 PM PST 23 Dec 31 01:22:07 PM PST 23 158736914570 ps
T959 /workspace/coverage/default/17.sram_ctrl_mem_walk.671352237 Dec 31 01:04:39 PM PST 23 Dec 31 01:06:45 PM PST 23 2061040186 ps
T960 /workspace/coverage/default/27.sram_ctrl_stress_all.1731277902 Dec 31 01:05:30 PM PST 23 Dec 31 01:38:19 PM PST 23 17502779536 ps
T961 /workspace/coverage/default/38.sram_ctrl_alert_test.1015848929 Dec 31 01:05:43 PM PST 23 Dec 31 01:05:46 PM PST 23 20849086 ps
T962 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.436274894 Dec 31 01:06:27 PM PST 23 Dec 31 01:12:22 PM PST 23 65493545046 ps
T963 /workspace/coverage/default/40.sram_ctrl_max_throughput.694626363 Dec 31 01:05:45 PM PST 23 Dec 31 01:07:52 PM PST 23 799068791 ps
T964 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2732114896 Dec 31 01:05:43 PM PST 23 Dec 31 01:07:00 PM PST 23 13026760466 ps
T965 /workspace/coverage/default/3.sram_ctrl_alert_test.221509225 Dec 31 01:04:17 PM PST 23 Dec 31 01:04:19 PM PST 23 27812464 ps
T966 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1765527886 Dec 31 01:05:27 PM PST 23 Dec 31 01:06:46 PM PST 23 3959615382 ps
T967 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.4270480009 Dec 31 01:05:28 PM PST 23 Dec 31 01:17:35 PM PST 23 6115268020 ps
T968 /workspace/coverage/default/28.sram_ctrl_stress_all.3720156750 Dec 31 01:05:05 PM PST 23 Dec 31 01:56:19 PM PST 23 597027709678 ps
T969 /workspace/coverage/default/30.sram_ctrl_mem_walk.1810583323 Dec 31 01:05:03 PM PST 23 Dec 31 01:10:15 PM PST 23 21753199588 ps
T970 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3156435081 Dec 31 01:05:33 PM PST 23 Dec 31 01:11:08 PM PST 23 5552982562 ps
T971 /workspace/coverage/default/34.sram_ctrl_ram_cfg.1723735345 Dec 31 01:05:31 PM PST 23 Dec 31 01:05:39 PM PST 23 349665301 ps
T972 /workspace/coverage/default/30.sram_ctrl_ram_cfg.469643537 Dec 31 01:05:29 PM PST 23 Dec 31 01:05:44 PM PST 23 361538722 ps
T973 /workspace/coverage/default/47.sram_ctrl_lc_escalation.3771282279 Dec 31 01:06:45 PM PST 23 Dec 31 01:08:51 PM PST 23 25425179160 ps
T974 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.999821077 Dec 31 01:06:18 PM PST 23 Dec 31 01:11:19 PM PST 23 4417530189 ps
T975 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3344757235 Dec 31 01:04:50 PM PST 23 Dec 31 02:32:31 PM PST 23 4158168836 ps
T976 /workspace/coverage/default/29.sram_ctrl_regwen.967841612 Dec 31 01:05:31 PM PST 23 Dec 31 01:11:00 PM PST 23 5001990854 ps
T977 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1876884515 Dec 31 01:03:57 PM PST 23 Dec 31 01:10:02 PM PST 23 17459868301 ps
T978 /workspace/coverage/default/17.sram_ctrl_regwen.2567893989 Dec 31 01:04:32 PM PST 23 Dec 31 01:16:16 PM PST 23 9414311937 ps
T979 /workspace/coverage/default/33.sram_ctrl_mem_walk.2742481631 Dec 31 01:05:42 PM PST 23 Dec 31 01:09:42 PM PST 23 8043824040 ps

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.1712591611
Short name T13
Test name
Test status
Simulation time 76368745312 ps
CPU time 1791.58 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 01:34:27 PM PST 23
Peak memory 376076 kb
Host smart-c0600123-c02d-4e41-9d80-10134a93c2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712591611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.1712591611
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.726997098
Short name T5
Test name
Test status
Simulation time 46027309710 ps
CPU time 113.09 seconds
Started Dec 31 01:03:49 PM PST 23
Finished Dec 31 01:05:44 PM PST 23
Peak memory 210336 kb
Host smart-e9f6bea7-af34-43b1-90cc-a7f294d44d80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726997098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esca
lation.726997098
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1953665917
Short name T27
Test name
Test status
Simulation time 323218921 ps
CPU time 2800.2 seconds
Started Dec 31 01:04:57 PM PST 23
Finished Dec 31 01:51:38 PM PST 23
Peak memory 419388 kb
Host smart-49554c88-06bf-47a1-88c7-45d3cf67cb0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1953665917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.1953665917
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1313361670
Short name T45
Test name
Test status
Simulation time 227312157 ps
CPU time 1.29 seconds
Started Dec 31 12:52:04 PM PST 23
Finished Dec 31 12:52:13 PM PST 23
Peak memory 202392 kb
Host smart-520efca2-8553-4440-975d-b939714b57b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313361670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.1313361670
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.3452362217
Short name T14
Test name
Test status
Simulation time 85260009438 ps
CPU time 1529.43 seconds
Started Dec 31 01:06:48 PM PST 23
Finished Dec 31 01:32:26 PM PST 23
Peak memory 377052 kb
Host smart-336255c0-9ef7-45a4-a5e6-3a65bcd52e29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452362217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3452362217
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.3364453552
Short name T21
Test name
Test status
Simulation time 88040104 ps
CPU time 1.69 seconds
Started Dec 31 01:04:03 PM PST 23
Finished Dec 31 01:04:05 PM PST 23
Peak memory 220832 kb
Host smart-631643c4-5ef1-4050-9bf5-8b7a0c4c8e4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364453552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.3364453552
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2426272260
Short name T109
Test name
Test status
Simulation time 39569793156 ps
CPU time 269.98 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:10:03 PM PST 23
Peak memory 202164 kb
Host smart-697f9eff-715c-4c3a-a8f2-834ecb7c73b9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426272260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.2426272260
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1397645439
Short name T3
Test name
Test status
Simulation time 69370794813 ps
CPU time 2164.21 seconds
Started Dec 31 01:06:17 PM PST 23
Finished Dec 31 01:42:25 PM PST 23
Peak memory 381112 kb
Host smart-59e356ef-7fd0-442d-8600-972d96ad383c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397645439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.1397645439
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2526140797
Short name T29
Test name
Test status
Simulation time 14429775143 ps
CPU time 106.91 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:54:10 PM PST 23
Peak memory 202524 kb
Host smart-25b08688-88d2-4839-a39b-fb0873c80787
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526140797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.2526140797
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3884618198
Short name T118
Test name
Test status
Simulation time 175187442 ps
CPU time 1.37 seconds
Started Dec 31 12:51:58 PM PST 23
Finished Dec 31 12:52:07 PM PST 23
Peak memory 202432 kb
Host smart-1ef67374-c013-4a8e-9844-68f97d7ac6ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884618198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.3884618198
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.3188010018
Short name T300
Test name
Test status
Simulation time 199465935546 ps
CPU time 2470.15 seconds
Started Dec 31 01:04:29 PM PST 23
Finished Dec 31 01:45:43 PM PST 23
Peak memory 380364 kb
Host smart-bde87203-4f30-41c2-b0d4-678b462d3944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188010018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.3188010018
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.3729808813
Short name T344
Test name
Test status
Simulation time 354368338 ps
CPU time 6.44 seconds
Started Dec 31 01:04:56 PM PST 23
Finished Dec 31 01:05:04 PM PST 23
Peak memory 202424 kb
Host smart-3f1b5f42-b05b-4810-83d3-a2198438a390
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729808813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3729808813
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2979201137
Short name T117
Test name
Test status
Simulation time 196774055 ps
CPU time 2.2 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:21 PM PST 23
Peak memory 202616 kb
Host smart-28e97197-a644-4f2c-8482-5df509659684
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979201137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.2979201137
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2628379608
Short name T89
Test name
Test status
Simulation time 76554274 ps
CPU time 1.37 seconds
Started Dec 31 12:51:53 PM PST 23
Finished Dec 31 12:52:02 PM PST 23
Peak memory 202484 kb
Host smart-30212c25-85c5-48a8-b8bf-ef14e42afed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628379608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.2628379608
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.2235691826
Short name T244
Test name
Test status
Simulation time 12526338 ps
CPU time 0.64 seconds
Started Dec 31 01:04:27 PM PST 23
Finished Dec 31 01:04:30 PM PST 23
Peak memory 201440 kb
Host smart-dc4f2aaf-24f6-4d99-99ed-ce1753b76632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235691826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.2235691826
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2457688486
Short name T59
Test name
Test status
Simulation time 476355793 ps
CPU time 2.13 seconds
Started Dec 31 12:51:36 PM PST 23
Finished Dec 31 12:51:51 PM PST 23
Peak memory 202340 kb
Host smart-9de014d5-3099-4763-8b63-042b70e87f28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457688486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.2457688486
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1218936307
Short name T120
Test name
Test status
Simulation time 194193033 ps
CPU time 2.25 seconds
Started Dec 31 12:52:00 PM PST 23
Finished Dec 31 12:52:10 PM PST 23
Peak memory 202284 kb
Host smart-dc1f1250-64f9-46d4-bbcd-58d98817ca0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218936307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.1218936307
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3150731427
Short name T46
Test name
Test status
Simulation time 358755407 ps
CPU time 2.25 seconds
Started Dec 31 12:52:00 PM PST 23
Finished Dec 31 12:52:10 PM PST 23
Peak memory 202464 kb
Host smart-bd6f5bb4-b3fd-44bc-b03d-4b5904ba2973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150731427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.3150731427
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.705312266
Short name T307
Test name
Test status
Simulation time 10803567952 ps
CPU time 72.15 seconds
Started Dec 31 01:04:39 PM PST 23
Finished Dec 31 01:05:56 PM PST 23
Peak memory 202176 kb
Host smart-5b8ee770-15da-4282-b8ad-bb902c64c873
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705312266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esc
alation.705312266
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.1322573982
Short name T605
Test name
Test status
Simulation time 2723592728050 ps
CPU time 8252.2 seconds
Started Dec 31 01:04:32 PM PST 23
Finished Dec 31 03:22:09 PM PST 23
Peak memory 381124 kb
Host smart-c38440f5-42b0-47df-94cb-f08258c74fbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322573982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.1322573982
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1191887976
Short name T61
Test name
Test status
Simulation time 45679174 ps
CPU time 1.1 seconds
Started Dec 31 12:51:43 PM PST 23
Finished Dec 31 12:51:57 PM PST 23
Peak memory 202388 kb
Host smart-6730fcde-37b0-4654-8210-d5e260c5c9fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191887976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.1191887976
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1094881599
Short name T79
Test name
Test status
Simulation time 30654145 ps
CPU time 0.65 seconds
Started Dec 31 12:51:34 PM PST 23
Finished Dec 31 12:51:43 PM PST 23
Peak memory 202020 kb
Host smart-f3e627d7-dd29-4ec2-9252-f7d22ab5d248
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094881599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.1094881599
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.369348657
Short name T60
Test name
Test status
Simulation time 14998779 ps
CPU time 0.65 seconds
Started Dec 31 12:51:50 PM PST 23
Finished Dec 31 12:52:00 PM PST 23
Peak memory 201360 kb
Host smart-e3000361-8f88-4922-b653-13488d2abd52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369348657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_hw_reset.369348657
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1242735917
Short name T206
Test name
Test status
Simulation time 378134794 ps
CPU time 14.43 seconds
Started Dec 31 12:51:36 PM PST 23
Finished Dec 31 12:52:02 PM PST 23
Peak memory 210588 kb
Host smart-3941c930-d323-4908-b34f-dee707179aa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242735917 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1242735917
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2804568572
Short name T72
Test name
Test status
Simulation time 40170545 ps
CPU time 0.64 seconds
Started Dec 31 12:52:00 PM PST 23
Finished Dec 31 12:52:08 PM PST 23
Peak memory 201324 kb
Host smart-1a5892a2-7f1e-4d9c-829a-76e19b3021fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804568572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.2804568572
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2515756037
Short name T66
Test name
Test status
Simulation time 40956117585 ps
CPU time 73.98 seconds
Started Dec 31 12:51:39 PM PST 23
Finished Dec 31 12:53:06 PM PST 23
Peak memory 202524 kb
Host smart-c730902a-cb93-44bd-9fa8-fa3b1050c198
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515756037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.2515756037
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.348113442
Short name T156
Test name
Test status
Simulation time 20091537 ps
CPU time 0.69 seconds
Started Dec 31 12:51:54 PM PST 23
Finished Dec 31 12:52:04 PM PST 23
Peak memory 202252 kb
Host smart-83618e30-ec78-4465-8a50-41463c4adca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348113442 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.348113442
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3306312811
Short name T165
Test name
Test status
Simulation time 122060061 ps
CPU time 4.26 seconds
Started Dec 31 12:51:40 PM PST 23
Finished Dec 31 12:51:57 PM PST 23
Peak memory 202340 kb
Host smart-608107df-9482-4fce-8a39-64e130f44586
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306312811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.3306312811
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2719125820
Short name T170
Test name
Test status
Simulation time 146783627 ps
CPU time 2.04 seconds
Started Dec 31 12:51:52 PM PST 23
Finished Dec 31 12:52:02 PM PST 23
Peak memory 202396 kb
Host smart-fda27704-f0eb-4df5-9be0-98f6d3ca6a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719125820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.2719125820
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3747711637
Short name T142
Test name
Test status
Simulation time 25490331 ps
CPU time 0.66 seconds
Started Dec 31 12:51:49 PM PST 23
Finished Dec 31 12:51:59 PM PST 23
Peak memory 202124 kb
Host smart-bb64a9a0-2e63-411b-97ea-c9e90d3e3d16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747711637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.3747711637
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1088790453
Short name T212
Test name
Test status
Simulation time 1057744859 ps
CPU time 1.47 seconds
Started Dec 31 12:51:39 PM PST 23
Finished Dec 31 12:51:53 PM PST 23
Peak memory 202304 kb
Host smart-6e79d9bf-e20a-4748-ac09-fe00ca297db1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088790453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.1088790453
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1719286949
Short name T186
Test name
Test status
Simulation time 42030252 ps
CPU time 0.63 seconds
Started Dec 31 12:51:53 PM PST 23
Finished Dec 31 12:52:03 PM PST 23
Peak memory 201228 kb
Host smart-a7f37142-8d2e-44e2-b704-ca1b2094ee31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719286949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.1719286949
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4023954558
Short name T51
Test name
Test status
Simulation time 1376053787 ps
CPU time 5.81 seconds
Started Dec 31 12:51:54 PM PST 23
Finished Dec 31 12:52:08 PM PST 23
Peak memory 202476 kb
Host smart-13f782f8-b7f0-455c-9f26-7b00a3293d04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023954558 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.4023954558
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2091990901
Short name T199
Test name
Test status
Simulation time 36941312 ps
CPU time 0.65 seconds
Started Dec 31 12:51:52 PM PST 23
Finished Dec 31 12:52:01 PM PST 23
Peak memory 202136 kb
Host smart-74bf9976-ef2a-431d-a072-79ff52a5cb9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091990901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.2091990901
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1739964545
Short name T214
Test name
Test status
Simulation time 16462204698 ps
CPU time 94.79 seconds
Started Dec 31 12:51:43 PM PST 23
Finished Dec 31 12:53:31 PM PST 23
Peak memory 202572 kb
Host smart-93cc192b-3d83-40b3-88c3-f8dbcc7187d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739964545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1739964545
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2476570408
Short name T183
Test name
Test status
Simulation time 39330939 ps
CPU time 0.8 seconds
Started Dec 31 12:51:53 PM PST 23
Finished Dec 31 12:52:02 PM PST 23
Peak memory 202044 kb
Host smart-420948b2-825c-4e41-85b2-f380c9074fa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476570408 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.2476570408
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2100117365
Short name T96
Test name
Test status
Simulation time 70435643 ps
CPU time 1.84 seconds
Started Dec 31 12:51:48 PM PST 23
Finished Dec 31 12:51:59 PM PST 23
Peak memory 202468 kb
Host smart-e8f0cb28-e04c-4a2a-8dd1-c5401f415b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100117365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.2100117365
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.488267104
Short name T169
Test name
Test status
Simulation time 1357269803 ps
CPU time 4.97 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:22 PM PST 23
Peak memory 202460 kb
Host smart-35e8398a-6e90-499a-8655-831901601fc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488267104 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.488267104
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2826650064
Short name T213
Test name
Test status
Simulation time 15339639 ps
CPU time 0.68 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 201456 kb
Host smart-39a8a0ee-57f7-48c3-92f9-25511c9400eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826650064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.2826650064
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.650313587
Short name T64
Test name
Test status
Simulation time 3733377770 ps
CPU time 53.01 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:53:17 PM PST 23
Peak memory 210772 kb
Host smart-11206c3a-95c4-4a7d-a31e-06b33384a587
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650313587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.650313587
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1970613563
Short name T149
Test name
Test status
Simulation time 15754294 ps
CPU time 0.74 seconds
Started Dec 31 12:51:53 PM PST 23
Finished Dec 31 12:52:03 PM PST 23
Peak memory 202176 kb
Host smart-f85bc707-9a26-4825-adbb-eecdf7067bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970613563 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.1970613563
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4141812016
Short name T155
Test name
Test status
Simulation time 221680549 ps
CPU time 2.23 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 202360 kb
Host smart-617f259f-0447-4c76-9934-399c2993b984
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141812016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.4141812016
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2686221198
Short name T98
Test name
Test status
Simulation time 137341362 ps
CPU time 1.39 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 202448 kb
Host smart-24068d3f-560e-4d8b-b9b7-0b9d1368e1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686221198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.2686221198
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.167100802
Short name T162
Test name
Test status
Simulation time 703723240 ps
CPU time 5.71 seconds
Started Dec 31 12:51:59 PM PST 23
Finished Dec 31 12:52:12 PM PST 23
Peak memory 202468 kb
Host smart-cb9b4154-6e0b-4567-9646-37e888837ffe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167100802 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.167100802
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2149219141
Short name T152
Test name
Test status
Simulation time 34551098 ps
CPU time 0.63 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:15 PM PST 23
Peak memory 201300 kb
Host smart-a6fd0ba5-29c6-4cc7-9607-cbd476dfc8fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149219141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.2149219141
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1540561112
Short name T205
Test name
Test status
Simulation time 19130704 ps
CPU time 0.64 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:21 PM PST 23
Peak memory 202208 kb
Host smart-fa710950-3c33-4a48-99ec-04460be8b08f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540561112 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1540561112
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3317898508
Short name T163
Test name
Test status
Simulation time 82791191 ps
CPU time 2.95 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:27 PM PST 23
Peak memory 202432 kb
Host smart-99927416-0bb0-4a0d-8f82-dbde3a7710fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317898508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.3317898508
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3793138324
Short name T99
Test name
Test status
Simulation time 96966678 ps
CPU time 1.47 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:52:12 PM PST 23
Peak memory 202464 kb
Host smart-7833f04e-7aaf-41fc-b61f-1c25b34f3d63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793138324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.3793138324
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2577587783
Short name T184
Test name
Test status
Simulation time 349857779 ps
CPU time 5.42 seconds
Started Dec 31 12:51:59 PM PST 23
Finished Dec 31 12:52:13 PM PST 23
Peak memory 210680 kb
Host smart-90d9acd3-4025-4ab4-81f5-dd0df4d9b919
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577587783 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2577587783
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3138520522
Short name T151
Test name
Test status
Simulation time 21927382 ps
CPU time 0.62 seconds
Started Dec 31 12:51:58 PM PST 23
Finished Dec 31 12:52:07 PM PST 23
Peak memory 202172 kb
Host smart-68c632c5-fb56-4ad2-8939-308e4de03fab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138520522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.3138520522
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1023795980
Short name T200
Test name
Test status
Simulation time 3819970469 ps
CPU time 49.66 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:52:59 PM PST 23
Peak memory 202556 kb
Host smart-ee240f2e-fed5-4e85-8c1e-3bc6bca19173
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023795980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1023795980
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1414395303
Short name T94
Test name
Test status
Simulation time 31244517 ps
CPU time 0.68 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 201912 kb
Host smart-75b5d11b-2e86-4a19-a49c-e3731773ed7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414395303 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1414395303
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2095161001
Short name T179
Test name
Test status
Simulation time 57042916 ps
CPU time 2.5 seconds
Started Dec 31 12:52:03 PM PST 23
Finished Dec 31 12:52:13 PM PST 23
Peak memory 202332 kb
Host smart-a8012aa1-18e4-4e6f-97b5-0f37e1d08ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095161001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.2095161001
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3568051916
Short name T122
Test name
Test status
Simulation time 287023758 ps
CPU time 1.36 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:17 PM PST 23
Peak memory 202324 kb
Host smart-1e7be990-1aeb-4ce3-81c9-58a43e26c9cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568051916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.3568051916
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2106938536
Short name T53
Test name
Test status
Simulation time 1781544594 ps
CPU time 4.86 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:52:14 PM PST 23
Peak memory 202360 kb
Host smart-35e537ee-dd89-4e80-b610-7d2653b1394e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106938536 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2106938536
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1494368745
Short name T187
Test name
Test status
Simulation time 20924250 ps
CPU time 0.62 seconds
Started Dec 31 12:52:04 PM PST 23
Finished Dec 31 12:52:12 PM PST 23
Peak memory 201316 kb
Host smart-6ae176ba-828f-4d57-84ee-3fd496e53adc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494368745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.1494368745
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3019660177
Short name T182
Test name
Test status
Simulation time 14378227194 ps
CPU time 124.64 seconds
Started Dec 31 12:52:03 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 210632 kb
Host smart-f2f44c7c-85a4-4abb-954f-1df82a117f00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019660177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.3019660177
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3440197052
Short name T148
Test name
Test status
Simulation time 25181401 ps
CPU time 0.66 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:52:10 PM PST 23
Peak memory 202212 kb
Host smart-da575d33-54a7-481a-9fac-672271c2badb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440197052 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3440197052
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1863960663
Short name T54
Test name
Test status
Simulation time 28196335 ps
CPU time 1.99 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 202360 kb
Host smart-7df5e647-e7a5-43cc-819d-47590f8cd556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863960663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.1863960663
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.138865500
Short name T157
Test name
Test status
Simulation time 1909106080 ps
CPU time 6.12 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:27 PM PST 23
Peak memory 202344 kb
Host smart-fa0103d5-d7d4-41d1-aa17-46f8d8f7aba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138865500 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.138865500
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2208318364
Short name T113
Test name
Test status
Simulation time 15967458 ps
CPU time 0.68 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:18 PM PST 23
Peak memory 202188 kb
Host smart-6c919ad5-f69f-4cb4-a702-d8e584061b45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208318364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.2208318364
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3176287454
Short name T93
Test name
Test status
Simulation time 15386660775 ps
CPU time 56.58 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:53:24 PM PST 23
Peak memory 202544 kb
Host smart-8839d8e3-75ab-4c8f-94d9-a12771a90263
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176287454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3176287454
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1522865303
Short name T193
Test name
Test status
Simulation time 17125786 ps
CPU time 0.75 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:52:23 PM PST 23
Peak memory 202220 kb
Host smart-2340a042-61e4-44bd-b1c9-8df6f5248d53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522865303 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1522865303
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.604444829
Short name T171
Test name
Test status
Simulation time 45240278 ps
CPU time 3.76 seconds
Started Dec 31 12:52:00 PM PST 23
Finished Dec 31 12:52:12 PM PST 23
Peak memory 202456 kb
Host smart-f5a30583-ef36-403c-be6f-150c2f3f0543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604444829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_tl_errors.604444829
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1133381848
Short name T209
Test name
Test status
Simulation time 213937165 ps
CPU time 2.21 seconds
Started Dec 31 12:52:01 PM PST 23
Finished Dec 31 12:52:11 PM PST 23
Peak memory 202436 kb
Host smart-bef9f70b-ae61-46a8-a1cf-10e252a08f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133381848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.1133381848
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3706176020
Short name T168
Test name
Test status
Simulation time 368342767 ps
CPU time 4.9 seconds
Started Dec 31 12:51:59 PM PST 23
Finished Dec 31 12:52:12 PM PST 23
Peak memory 210656 kb
Host smart-1c128c6f-d696-48c8-a822-ff806dbe9ba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706176020 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.3706176020
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.579294162
Short name T198
Test name
Test status
Simulation time 15375671 ps
CPU time 0.64 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:15 PM PST 23
Peak memory 202160 kb
Host smart-8828e040-b9b1-45d2-9907-291b20d186cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579294162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 15.sram_ctrl_csr_rw.579294162
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4078080866
Short name T204
Test name
Test status
Simulation time 8039107792 ps
CPU time 50.2 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:53:10 PM PST 23
Peak memory 210644 kb
Host smart-1933684c-19c1-4b83-936f-66a36dc7e4c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078080866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.4078080866
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.839703274
Short name T191
Test name
Test status
Simulation time 22987187 ps
CPU time 0.75 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:19 PM PST 23
Peak memory 202500 kb
Host smart-0b56a6ce-9a5f-4fb5-9895-630e4f0c2426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839703274 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.839703274
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1882639375
Short name T58
Test name
Test status
Simulation time 50313376 ps
CPU time 2.12 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:19 PM PST 23
Peak memory 202404 kb
Host smart-2b4de05a-51ec-4115-a87c-d6f417a79237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882639375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.1882639375
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3906145155
Short name T180
Test name
Test status
Simulation time 536988718 ps
CPU time 12.28 seconds
Started Dec 31 12:51:59 PM PST 23
Finished Dec 31 12:52:19 PM PST 23
Peak memory 210640 kb
Host smart-dab9d3a4-8718-4da5-b79a-e68111416043
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906145155 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3906145155
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3458593857
Short name T87
Test name
Test status
Simulation time 10839411 ps
CPU time 0.66 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:20 PM PST 23
Peak memory 202224 kb
Host smart-f8f7763c-7ebd-4129-b9dc-cc92f804d51b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458593857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.3458593857
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2373694817
Short name T208
Test name
Test status
Simulation time 8596877009 ps
CPU time 153.82 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:54:48 PM PST 23
Peak memory 210680 kb
Host smart-56ac04a5-f4b8-4618-828a-e2d55a9bcb6c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373694817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2373694817
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3549482257
Short name T144
Test name
Test status
Simulation time 33191401 ps
CPU time 0.67 seconds
Started Dec 31 12:52:00 PM PST 23
Finished Dec 31 12:52:08 PM PST 23
Peak memory 201812 kb
Host smart-a34832ba-fbbd-4bcd-8a7a-32f06f9b9d42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549482257 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3549482257
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.334170472
Short name T52
Test name
Test status
Simulation time 23871253 ps
CPU time 2.39 seconds
Started Dec 31 12:51:53 PM PST 23
Finished Dec 31 12:52:04 PM PST 23
Peak memory 210596 kb
Host smart-c7fac1ce-ac90-4640-97e4-c67b188fbf7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334170472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_tl_errors.334170472
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.68208195
Short name T91
Test name
Test status
Simulation time 329149558 ps
CPU time 1.38 seconds
Started Dec 31 12:52:11 PM PST 23
Finished Dec 31 12:52:27 PM PST 23
Peak memory 202344 kb
Host smart-1e95ed3b-2c84-411e-98f1-5aa6b0410b55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68208195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te
st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.sram_ctrl_tl_intg_err.68208195
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.417531667
Short name T50
Test name
Test status
Simulation time 346952513 ps
CPU time 5.85 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 202416 kb
Host smart-19de1f44-5ea5-4682-a77a-f55a63650854
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417531667 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.417531667
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3104123573
Short name T102
Test name
Test status
Simulation time 42171355 ps
CPU time 0.64 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:14 PM PST 23
Peak memory 201628 kb
Host smart-c4e49046-4a70-4ad9-bd4a-8966e770694b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104123573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.3104123573
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3408603734
Short name T174
Test name
Test status
Simulation time 28220562757 ps
CPU time 117.94 seconds
Started Dec 31 12:51:53 PM PST 23
Finished Dec 31 12:53:59 PM PST 23
Peak memory 202588 kb
Host smart-9f44cfc1-5280-43f7-8b43-418c66c61818
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408603734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3408603734
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3807313016
Short name T161
Test name
Test status
Simulation time 57358123 ps
CPU time 0.72 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:20 PM PST 23
Peak memory 202092 kb
Host smart-54ab28f5-b543-4ce3-8052-e2e65c7104ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807313016 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3807313016
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1304139466
Short name T159
Test name
Test status
Simulation time 1042174628 ps
CPU time 4.11 seconds
Started Dec 31 12:52:15 PM PST 23
Finished Dec 31 12:52:34 PM PST 23
Peak memory 202420 kb
Host smart-eb1bcf00-09be-4606-8076-bd74474b9a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304139466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.1304139466
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.427693786
Short name T189
Test name
Test status
Simulation time 696110622 ps
CPU time 13 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 210688 kb
Host smart-f75d1f93-afc7-436a-9b3d-9e8b61c2ed4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427693786 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.427693786
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2484408166
Short name T78
Test name
Test status
Simulation time 37706831 ps
CPU time 0.64 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:14 PM PST 23
Peak memory 201276 kb
Host smart-fb1fd6af-e057-494a-9299-3e2b209b24ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484408166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.2484408166
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2708757564
Short name T63
Test name
Test status
Simulation time 20835238362 ps
CPU time 265.68 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:56:35 PM PST 23
Peak memory 202528 kb
Host smart-26fc0c8f-ac8e-4076-95ff-280dce195101
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708757564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.2708757564
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1366349417
Short name T75
Test name
Test status
Simulation time 72043501 ps
CPU time 0.65 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 202164 kb
Host smart-bdd16d48-2f2d-44dd-80b4-2939157d4c69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366349417 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1366349417
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3771237397
Short name T195
Test name
Test status
Simulation time 152047451 ps
CPU time 4.12 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 202440 kb
Host smart-ddbfd531-f241-4359-b4ae-f873683b2c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771237397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.3771237397
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2438514903
Short name T121
Test name
Test status
Simulation time 115943869 ps
CPU time 1.48 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:52:11 PM PST 23
Peak memory 202456 kb
Host smart-72e2238a-feb6-41bb-bd8f-ce2cfc27b75b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438514903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.2438514903
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2349488447
Short name T210
Test name
Test status
Simulation time 1443775971 ps
CPU time 13.84 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:40 PM PST 23
Peak memory 210720 kb
Host smart-9494cc75-3e8f-49aa-8b02-11d068f42edb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349488447 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.2349488447
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2144364934
Short name T112
Test name
Test status
Simulation time 15671520 ps
CPU time 0.62 seconds
Started Dec 31 12:52:01 PM PST 23
Finished Dec 31 12:52:10 PM PST 23
Peak memory 201324 kb
Host smart-f2e6d2b0-e1eb-4b66-bc65-a2b8ec6cee2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144364934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.2144364934
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1785980893
Short name T101
Test name
Test status
Simulation time 15923731452 ps
CPU time 270.04 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:56:53 PM PST 23
Peak memory 202512 kb
Host smart-e649a7b1-d9af-4aee-9e14-2d01d2100f03
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785980893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1785980893
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2384997939
Short name T71
Test name
Test status
Simulation time 36682281 ps
CPU time 0.65 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:52:23 PM PST 23
Peak memory 201584 kb
Host smart-f1a4ad43-f36a-429c-b6e0-9fed230ce72b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384997939 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2384997939
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1606678196
Short name T49
Test name
Test status
Simulation time 108663902 ps
CPU time 3.43 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 202436 kb
Host smart-105c396d-c763-46c5-9f94-0fe503b510e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606678196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.1606678196
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1051879356
Short name T114
Test name
Test status
Simulation time 368851057 ps
CPU time 1.6 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 202392 kb
Host smart-76ac41e7-0457-4369-a7e9-95b5110761c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051879356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.1051879356
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2817362173
Short name T62
Test name
Test status
Simulation time 24736350 ps
CPU time 0.7 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:18 PM PST 23
Peak memory 202144 kb
Host smart-622c0b63-6cb4-48fd-9570-1e3bcc5af476
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817362173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.2817362173
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3521076961
Short name T73
Test name
Test status
Simulation time 156225060 ps
CPU time 1.89 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:21 PM PST 23
Peak memory 202256 kb
Host smart-dec12054-5cad-4bc6-9d21-4435d35515df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521076961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.3521076961
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2184622625
Short name T74
Test name
Test status
Simulation time 38180953 ps
CPU time 0.65 seconds
Started Dec 31 12:52:01 PM PST 23
Finished Dec 31 12:52:10 PM PST 23
Peak memory 201444 kb
Host smart-ad16447f-4ced-4975-bb1e-f8ccda482b3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184622625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.2184622625
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.249343325
Short name T188
Test name
Test status
Simulation time 719870266 ps
CPU time 5.51 seconds
Started Dec 31 12:52:00 PM PST 23
Finished Dec 31 12:52:14 PM PST 23
Peak memory 202388 kb
Host smart-5a251260-5211-4304-b107-1f2936bb2d9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249343325 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.249343325
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3278071552
Short name T104
Test name
Test status
Simulation time 38597430 ps
CPU time 0.64 seconds
Started Dec 31 12:51:55 PM PST 23
Finished Dec 31 12:52:04 PM PST 23
Peak memory 201860 kb
Host smart-95be7c8f-2cb9-4d31-9122-b9b29fc2b5ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278071552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.3278071552
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3620127277
Short name T203
Test name
Test status
Simulation time 10835104679 ps
CPU time 135.16 seconds
Started Dec 31 12:51:51 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 210780 kb
Host smart-ee05be91-1367-405c-96a4-85c1dc216167
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620127277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3620127277
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1749818249
Short name T185
Test name
Test status
Simulation time 40749630 ps
CPU time 0.71 seconds
Started Dec 31 12:52:03 PM PST 23
Finished Dec 31 12:52:11 PM PST 23
Peak memory 202184 kb
Host smart-135ca894-b938-425f-a4f0-75440f47758c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749818249 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1749818249
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.883674441
Short name T48
Test name
Test status
Simulation time 460476715 ps
CPU time 4.16 seconds
Started Dec 31 12:52:01 PM PST 23
Finished Dec 31 12:52:13 PM PST 23
Peak memory 202448 kb
Host smart-15adfb42-1c73-4f18-b24e-cdf3defdb52e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883674441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_tl_errors.883674441
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1248865341
Short name T176
Test name
Test status
Simulation time 31367655 ps
CPU time 0.65 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:19 PM PST 23
Peak memory 202096 kb
Host smart-3e1d1c4b-fb9a-406e-8086-b07a6daae561
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248865341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.1248865341
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3149450531
Short name T202
Test name
Test status
Simulation time 664096959 ps
CPU time 1.29 seconds
Started Dec 31 12:51:56 PM PST 23
Finished Dec 31 12:52:05 PM PST 23
Peak memory 202152 kb
Host smart-a1a5d551-097b-4095-ae4e-68b92d3d5763
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149450531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.3149450531
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.994045914
Short name T197
Test name
Test status
Simulation time 34562116 ps
CPU time 0.63 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:23 PM PST 23
Peak memory 202192 kb
Host smart-03b9de83-2716-4e52-ba9f-866c5240bace
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994045914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_hw_reset.994045914
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3936326067
Short name T141
Test name
Test status
Simulation time 773074078 ps
CPU time 5.84 seconds
Started Dec 31 12:51:56 PM PST 23
Finished Dec 31 12:52:10 PM PST 23
Peak memory 210592 kb
Host smart-a23aed1d-d3a8-4187-9a01-2c965d7bdbd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936326067 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3936326067
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3923463508
Short name T164
Test name
Test status
Simulation time 30659461 ps
CPU time 0.65 seconds
Started Dec 31 12:51:53 PM PST 23
Finished Dec 31 12:52:02 PM PST 23
Peak memory 201624 kb
Host smart-2c61bc6e-021c-479c-a772-45a5c254f439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923463508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.3923463508
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4163821741
Short name T90
Test name
Test status
Simulation time 7193391274 ps
CPU time 118.53 seconds
Started Dec 31 12:51:57 PM PST 23
Finished Dec 31 12:54:03 PM PST 23
Peak memory 202524 kb
Host smart-37830ade-2986-47ef-a9f4-b2f87c86299a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163821741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.4163821741
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.800355773
Short name T173
Test name
Test status
Simulation time 64527299 ps
CPU time 0.67 seconds
Started Dec 31 12:51:49 PM PST 23
Finished Dec 31 12:51:59 PM PST 23
Peak memory 201532 kb
Host smart-46a323dd-cd4a-469c-bbf3-030e43673de8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800355773 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.800355773
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3690977086
Short name T201
Test name
Test status
Simulation time 27464589 ps
CPU time 2.16 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:20 PM PST 23
Peak memory 202364 kb
Host smart-9329e745-82ea-49c3-905c-ae685c94324f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690977086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.3690977086
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.203724813
Short name T47
Test name
Test status
Simulation time 198599042 ps
CPU time 1.51 seconds
Started Dec 31 12:51:56 PM PST 23
Finished Dec 31 12:52:05 PM PST 23
Peak memory 202364 kb
Host smart-3bcd17af-1ceb-4d02-aa6d-0560d3d52b23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203724813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.sram_ctrl_tl_intg_err.203724813
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2425179912
Short name T177
Test name
Test status
Simulation time 38810892 ps
CPU time 0.64 seconds
Started Dec 31 12:51:58 PM PST 23
Finished Dec 31 12:52:07 PM PST 23
Peak memory 201240 kb
Host smart-aa0f901e-8c51-4e48-819a-ef6a281dfea7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425179912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.2425179912
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.345507399
Short name T143
Test name
Test status
Simulation time 215272842 ps
CPU time 1.2 seconds
Started Dec 31 12:51:46 PM PST 23
Finished Dec 31 12:51:58 PM PST 23
Peak memory 202248 kb
Host smart-8e2930dc-d90c-4667-92f4-e02cf5d8c0ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345507399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_bit_bash.345507399
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3780801539
Short name T88
Test name
Test status
Simulation time 38372511 ps
CPU time 0.65 seconds
Started Dec 31 12:52:04 PM PST 23
Finished Dec 31 12:52:13 PM PST 23
Peak memory 202016 kb
Host smart-dd92d020-b70f-4700-8c69-1ae00456bd15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780801539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.3780801539
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3381838094
Short name T158
Test name
Test status
Simulation time 1390325780 ps
CPU time 12.38 seconds
Started Dec 31 12:51:53 PM PST 23
Finished Dec 31 12:52:13 PM PST 23
Peak memory 210620 kb
Host smart-25613e1c-b372-47b1-ac6f-a98e6f936c77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381838094 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3381838094
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1547780631
Short name T153
Test name
Test status
Simulation time 12072445 ps
CPU time 0.65 seconds
Started Dec 31 12:51:59 PM PST 23
Finished Dec 31 12:52:07 PM PST 23
Peak memory 201324 kb
Host smart-890ce219-a54c-4bea-b625-f6241881873e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547780631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.1547780631
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3356776197
Short name T92
Test name
Test status
Simulation time 3987002794 ps
CPU time 152.09 seconds
Started Dec 31 12:51:51 PM PST 23
Finished Dec 31 12:54:31 PM PST 23
Peak memory 202676 kb
Host smart-38fabb1c-ba5e-46d3-adf8-4bf3fc58558d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356776197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3356776197
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2252462819
Short name T105
Test name
Test status
Simulation time 127670483 ps
CPU time 0.66 seconds
Started Dec 31 12:51:52 PM PST 23
Finished Dec 31 12:52:00 PM PST 23
Peak memory 202228 kb
Host smart-f1a0e6ae-fdd7-4884-8b34-989681817daf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252462819 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2252462819
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3663825124
Short name T55
Test name
Test status
Simulation time 134236783 ps
CPU time 3.64 seconds
Started Dec 31 12:51:45 PM PST 23
Finished Dec 31 12:52:00 PM PST 23
Peak memory 202368 kb
Host smart-067223c6-6ce1-449a-85f8-769f2bb916da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663825124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.3663825124
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3864616443
Short name T116
Test name
Test status
Simulation time 381021771 ps
CPU time 2.27 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:52:23 PM PST 23
Peak memory 202388 kb
Host smart-fef21437-845a-4cf5-b68c-201002ec5d19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864616443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.3864616443
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2336147618
Short name T211
Test name
Test status
Simulation time 715757288 ps
CPU time 4.76 seconds
Started Dec 31 12:51:56 PM PST 23
Finished Dec 31 12:52:09 PM PST 23
Peak memory 202452 kb
Host smart-55a12f6c-cee9-4dfb-9cca-698ab5970327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336147618 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2336147618
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1508829913
Short name T77
Test name
Test status
Simulation time 13119991 ps
CPU time 0.68 seconds
Started Dec 31 12:52:00 PM PST 23
Finished Dec 31 12:52:08 PM PST 23
Peak memory 202136 kb
Host smart-0d0222a2-5a3e-43a0-9cfe-37fcd0bb5581
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508829913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.1508829913
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1719834383
Short name T97
Test name
Test status
Simulation time 13692576001 ps
CPU time 56.18 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:53:14 PM PST 23
Peak memory 210756 kb
Host smart-608624ba-4933-4a2b-af37-87755fa5b394
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719834383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.1719834383
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.44360554
Short name T175
Test name
Test status
Simulation time 23037248 ps
CPU time 0.66 seconds
Started Dec 31 12:52:04 PM PST 23
Finished Dec 31 12:52:13 PM PST 23
Peak memory 202220 kb
Host smart-2ceb0fb9-6cd2-4b53-8c12-82d256fce976
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44360554 -assert nopostproc +UVM_TESTNAME=sram_ctr
l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.44360554
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3759728402
Short name T160
Test name
Test status
Simulation time 160397644 ps
CPU time 4.83 seconds
Started Dec 31 12:52:03 PM PST 23
Finished Dec 31 12:52:15 PM PST 23
Peak memory 202400 kb
Host smart-e27e4c75-d899-45d8-af34-f294814514fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759728402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.3759728402
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1176572390
Short name T86
Test name
Test status
Simulation time 639714493 ps
CPU time 1.39 seconds
Started Dec 31 12:51:52 PM PST 23
Finished Dec 31 12:52:02 PM PST 23
Peak memory 202264 kb
Host smart-dc95ca41-cdf4-4072-b425-72b8640abf90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176572390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.1176572390
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.34552757
Short name T150
Test name
Test status
Simulation time 339097699 ps
CPU time 5.35 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:52:14 PM PST 23
Peak memory 202396 kb
Host smart-d3de7f9a-8ed7-4de1-ac7c-2b2c20767bbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34552757 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.34552757
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1863137286
Short name T167
Test name
Test status
Simulation time 13315751 ps
CPU time 0.63 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:19 PM PST 23
Peak memory 201336 kb
Host smart-24907c0e-98b8-4d8d-af6f-ada61ac7282c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863137286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.1863137286
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.616611582
Short name T196
Test name
Test status
Simulation time 7148341017 ps
CPU time 252.13 seconds
Started Dec 31 12:51:53 PM PST 23
Finished Dec 31 12:56:14 PM PST 23
Peak memory 202456 kb
Host smart-c9617c53-391d-4db0-a3e8-576611283d2b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616611582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.616611582
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3149949480
Short name T172
Test name
Test status
Simulation time 96146501 ps
CPU time 0.72 seconds
Started Dec 31 12:51:59 PM PST 23
Finished Dec 31 12:52:08 PM PST 23
Peak memory 202260 kb
Host smart-536bffc9-4843-4757-997d-22f66dd5c62a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149949480 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.3149949480
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1507212416
Short name T154
Test name
Test status
Simulation time 91569127 ps
CPU time 1.78 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 202480 kb
Host smart-31da2205-cef5-4b77-9c36-57fa98407327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507212416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.1507212416
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2595059776
Short name T145
Test name
Test status
Simulation time 2000820140 ps
CPU time 12.42 seconds
Started Dec 31 12:52:01 PM PST 23
Finished Dec 31 12:52:21 PM PST 23
Peak memory 202344 kb
Host smart-6f44ce13-7be8-4866-85de-2bcff5081968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595059776 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2595059776
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1579448823
Short name T192
Test name
Test status
Simulation time 23432699 ps
CPU time 0.69 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:14 PM PST 23
Peak memory 202020 kb
Host smart-f9e6f4a1-4459-491b-aabe-18d6e12dd976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579448823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.1579448823
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2205501977
Short name T100
Test name
Test status
Simulation time 50397395031 ps
CPU time 275 seconds
Started Dec 31 12:52:03 PM PST 23
Finished Dec 31 12:56:46 PM PST 23
Peak memory 202508 kb
Host smart-6c6c3b61-eb1d-410c-b2cc-d6508abf4366
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205501977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2205501977
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.552072265
Short name T166
Test name
Test status
Simulation time 22546879 ps
CPU time 0.76 seconds
Started Dec 31 12:51:53 PM PST 23
Finished Dec 31 12:52:02 PM PST 23
Peak memory 202224 kb
Host smart-b93a69e9-d0ae-43bb-bbcd-7e8e4787d7c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552072265 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.552072265
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1535258184
Short name T207
Test name
Test status
Simulation time 893992857 ps
CPU time 5.26 seconds
Started Dec 31 12:52:04 PM PST 23
Finished Dec 31 12:52:18 PM PST 23
Peak memory 202412 kb
Host smart-4c202f50-46ac-4ee9-9351-83b380d4b30c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535258184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.1535258184
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.806565908
Short name T194
Test name
Test status
Simulation time 285607994 ps
CPU time 2.24 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:16 PM PST 23
Peak memory 202344 kb
Host smart-9104df97-d511-4570-a5e4-3f4d1de8136d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806565908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.sram_ctrl_tl_intg_err.806565908
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1917881828
Short name T65
Test name
Test status
Simulation time 342529052 ps
CPU time 12.21 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:32 PM PST 23
Peak memory 210756 kb
Host smart-16754bfb-46c0-46ee-83c2-b605d4325014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917881828 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1917881828
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1903005138
Short name T95
Test name
Test status
Simulation time 37856683 ps
CPU time 0.64 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:16 PM PST 23
Peak memory 202092 kb
Host smart-e8e352d2-4ac7-4643-a081-deedeb7baad3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903005138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.1903005138
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1388691893
Short name T76
Test name
Test status
Simulation time 7530350344 ps
CPU time 140.92 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:54:35 PM PST 23
Peak memory 210796 kb
Host smart-c4c1ef1f-c605-44b7-9ba7-12f4091e4bec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388691893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.1388691893
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1860918661
Short name T147
Test name
Test status
Simulation time 22086100 ps
CPU time 0.72 seconds
Started Dec 31 12:51:59 PM PST 23
Finished Dec 31 12:52:07 PM PST 23
Peak memory 202236 kb
Host smart-8c56e6a3-aa96-450d-872d-c900c73f6647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860918661 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1860918661
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1019666657
Short name T181
Test name
Test status
Simulation time 125958043 ps
CPU time 2.22 seconds
Started Dec 31 12:51:58 PM PST 23
Finished Dec 31 12:52:08 PM PST 23
Peak memory 202412 kb
Host smart-4a9bb8af-f4fa-4a4d-84fe-e500141b285d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019666657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.1019666657
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2387881859
Short name T119
Test name
Test status
Simulation time 242559192 ps
CPU time 2.26 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 202308 kb
Host smart-e3f45287-773f-4e83-8700-e722920fe61f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387881859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.2387881859
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2131404969
Short name T190
Test name
Test status
Simulation time 413484357 ps
CPU time 5.74 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 202432 kb
Host smart-6ddf51ab-b182-4ee3-89c8-d25f01d0fc2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131404969 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.2131404969
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3006319626
Short name T84
Test name
Test status
Simulation time 27632028 ps
CPU time 0.63 seconds
Started Dec 31 12:51:59 PM PST 23
Finished Dec 31 12:52:08 PM PST 23
Peak memory 201276 kb
Host smart-820bb742-e3d3-4fc6-88c6-16b708e2cb98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006319626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.3006319626
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3350284351
Short name T178
Test name
Test status
Simulation time 15438337346 ps
CPU time 54.42 seconds
Started Dec 31 12:51:51 PM PST 23
Finished Dec 31 12:52:54 PM PST 23
Peak memory 210672 kb
Host smart-45fcc24b-e7ce-414a-a30e-e42430b3b0e2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350284351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3350284351
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.548458902
Short name T103
Test name
Test status
Simulation time 58343727 ps
CPU time 0.68 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:15 PM PST 23
Peak memory 202160 kb
Host smart-87c5b3c8-6a05-4187-9f96-21f62ca0cf16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548458902 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.548458902
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3918557886
Short name T146
Test name
Test status
Simulation time 520865312 ps
CPU time 4.19 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:20 PM PST 23
Peak memory 202352 kb
Host smart-c5c61859-62e7-4f4b-973e-e4fbe0cf51a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918557886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.3918557886
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1274620772
Short name T83
Test name
Test status
Simulation time 5154139905 ps
CPU time 760.33 seconds
Started Dec 31 01:04:05 PM PST 23
Finished Dec 31 01:16:47 PM PST 23
Peak memory 372884 kb
Host smart-1e70a547-c660-4b9a-972a-96d4fcfa55d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274620772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1274620772
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.540052504
Short name T591
Test name
Test status
Simulation time 54698419 ps
CPU time 0.65 seconds
Started Dec 31 01:03:39 PM PST 23
Finished Dec 31 01:03:45 PM PST 23
Peak memory 201876 kb
Host smart-67a8ac5c-96ce-4c64-ba53-c4545b700525
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540052504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.540052504
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.872720544
Short name T216
Test name
Test status
Simulation time 124181218429 ps
CPU time 2036.58 seconds
Started Dec 31 01:04:16 PM PST 23
Finished Dec 31 01:38:15 PM PST 23
Peak memory 202144 kb
Host smart-30a65f74-1a71-44ec-9e21-e67edf2e7b7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872720544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.872720544
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.2784751360
Short name T925
Test name
Test status
Simulation time 18136809770 ps
CPU time 99.39 seconds
Started Dec 31 01:03:39 PM PST 23
Finished Dec 31 01:05:23 PM PST 23
Peak memory 210356 kb
Host smart-14006306-1e21-407c-add7-ac6849a4d358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784751360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.2784751360
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.2307884060
Short name T839
Test name
Test status
Simulation time 757797840 ps
CPU time 49.15 seconds
Started Dec 31 01:04:08 PM PST 23
Finished Dec 31 01:04:58 PM PST 23
Peak memory 274400 kb
Host smart-ea1b5370-fb6b-4bfe-b649-73323f039ec5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307884060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.2307884060
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.191723626
Short name T358
Test name
Test status
Simulation time 11916501762 ps
CPU time 128.97 seconds
Started Dec 31 01:04:07 PM PST 23
Finished Dec 31 01:06:17 PM PST 23
Peak memory 214368 kb
Host smart-cd31bf70-1232-4b24-a15f-41338215a76e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191723626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_mem_partial_access.191723626
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.1767546528
Short name T432
Test name
Test status
Simulation time 4114812848 ps
CPU time 242.65 seconds
Started Dec 31 01:04:05 PM PST 23
Finished Dec 31 01:08:09 PM PST 23
Peak memory 202076 kb
Host smart-b8481b8d-15da-4ddf-a7ac-f2ea7a7f4b0c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767546528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.1767546528
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.997129049
Short name T485
Test name
Test status
Simulation time 56890886488 ps
CPU time 551.3 seconds
Started Dec 31 01:04:14 PM PST 23
Finished Dec 31 01:13:26 PM PST 23
Peak memory 324548 kb
Host smart-f97f75fb-fed8-4b56-ac4f-c9e6fe7c739e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997129049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multipl
e_keys.997129049
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.3212887577
Short name T673
Test name
Test status
Simulation time 4189034907 ps
CPU time 19.77 seconds
Started Dec 31 01:04:07 PM PST 23
Finished Dec 31 01:04:28 PM PST 23
Peak memory 210256 kb
Host smart-f6fed26c-c1cb-4aef-9939-0e6a8690e293
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212887577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.3212887577
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1439294004
Short name T893
Test name
Test status
Simulation time 7542062400 ps
CPU time 477.72 seconds
Started Dec 31 01:03:46 PM PST 23
Finished Dec 31 01:11:46 PM PST 23
Peak memory 202216 kb
Host smart-3498c2c2-ee38-4b2a-81c6-d68d0a139815
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439294004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.1439294004
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.462648484
Short name T937
Test name
Test status
Simulation time 696296750 ps
CPU time 14.28 seconds
Started Dec 31 01:04:19 PM PST 23
Finished Dec 31 01:04:36 PM PST 23
Peak memory 202440 kb
Host smart-b488fe8e-c9a2-4d59-a39b-b495d6a86c3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462648484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.462648484
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.2928452543
Short name T24
Test name
Test status
Simulation time 15575965635 ps
CPU time 782.04 seconds
Started Dec 31 01:04:02 PM PST 23
Finished Dec 31 01:17:05 PM PST 23
Peak memory 380064 kb
Host smart-5dcb13b4-00a8-4f57-9761-cc0fc3a13d6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928452543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2928452543
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.1398259638
Short name T470
Test name
Test status
Simulation time 789955625 ps
CPU time 37.52 seconds
Started Dec 31 01:03:53 PM PST 23
Finished Dec 31 01:04:32 PM PST 23
Peak memory 202068 kb
Host smart-01b4a1a0-ff6f-4cb2-afc3-8d1fc173a121
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398259638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1398259638
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.4067851699
Short name T526
Test name
Test status
Simulation time 136151693539 ps
CPU time 3859.04 seconds
Started Dec 31 01:04:08 PM PST 23
Finished Dec 31 02:08:29 PM PST 23
Peak memory 379060 kb
Host smart-aa68434c-16e2-47cc-9e13-8cb215e7e66d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067851699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.4067851699
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4232814767
Short name T738
Test name
Test status
Simulation time 4519047986 ps
CPU time 3980.58 seconds
Started Dec 31 01:03:41 PM PST 23
Finished Dec 31 02:10:07 PM PST 23
Peak memory 734276 kb
Host smart-5e3be90e-4985-4e49-87de-bc48b0901f40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4232814767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.4232814767
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4233716901
Short name T269
Test name
Test status
Simulation time 3457647989 ps
CPU time 247.82 seconds
Started Dec 31 01:04:27 PM PST 23
Finished Dec 31 01:08:37 PM PST 23
Peak memory 202176 kb
Host smart-8a0fd10b-52b3-4f8a-a518-b6eb5df084b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233716901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.4233716901
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1692721595
Short name T408
Test name
Test status
Simulation time 739473919 ps
CPU time 33.61 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 01:04:56 PM PST 23
Peak memory 241988 kb
Host smart-1e54c076-2900-465e-a054-977ffc0e7858
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692721595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1692721595
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.3018692125
Short name T548
Test name
Test status
Simulation time 14025804008 ps
CPU time 2088.66 seconds
Started Dec 31 01:03:49 PM PST 23
Finished Dec 31 01:38:39 PM PST 23
Peak memory 380112 kb
Host smart-55d48351-c690-44d4-bb1e-1b44a58c7111
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018692125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.3018692125
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.2593717491
Short name T572
Test name
Test status
Simulation time 39045369316 ps
CPU time 1248.05 seconds
Started Dec 31 01:04:09 PM PST 23
Finished Dec 31 01:24:58 PM PST 23
Peak memory 202048 kb
Host smart-a5e85c8a-361c-4fc3-9e13-307624b4fc7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593717491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
2593717491
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.3545467767
Short name T268
Test name
Test status
Simulation time 1569298521 ps
CPU time 114.9 seconds
Started Dec 31 01:04:10 PM PST 23
Finished Dec 31 01:06:07 PM PST 23
Peak memory 346324 kb
Host smart-cd4a29f5-eb71-4ae9-a1c8-fd1e22f7535b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545467767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.3545467767
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.905484294
Short name T666
Test name
Test status
Simulation time 13600541733 ps
CPU time 82.33 seconds
Started Dec 31 01:04:17 PM PST 23
Finished Dec 31 01:05:41 PM PST 23
Peak memory 211144 kb
Host smart-c5923452-d604-4f18-8b81-4da36eff7c07
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905484294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_mem_partial_access.905484294
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.1865622201
Short name T789
Test name
Test status
Simulation time 6899645842 ps
CPU time 135.09 seconds
Started Dec 31 01:04:15 PM PST 23
Finished Dec 31 01:06:32 PM PST 23
Peak memory 202228 kb
Host smart-a3387655-9483-46a6-a69e-83380278ed94
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865622201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.1865622201
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.297962178
Short name T70
Test name
Test status
Simulation time 68907432336 ps
CPU time 772.61 seconds
Started Dec 31 01:04:00 PM PST 23
Finished Dec 31 01:16:53 PM PST 23
Peak memory 370804 kb
Host smart-df0078a1-74bd-4ab0-adec-9b9eef1956a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297962178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multipl
e_keys.297962178
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2936971784
Short name T936
Test name
Test status
Simulation time 2018623712 ps
CPU time 44.74 seconds
Started Dec 31 01:04:18 PM PST 23
Finished Dec 31 01:05:05 PM PST 23
Peak memory 202012 kb
Host smart-dc305a8d-200f-4bf9-adf7-c5a3fe29a848
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936971784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2936971784
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1207703133
Short name T952
Test name
Test status
Simulation time 10765090558 ps
CPU time 330.69 seconds
Started Dec 31 01:04:16 PM PST 23
Finished Dec 31 01:09:48 PM PST 23
Peak memory 201980 kb
Host smart-9bd5776a-9e4f-4934-951b-db00fe146280
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207703133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.1207703133
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.843487656
Short name T790
Test name
Test status
Simulation time 348467057 ps
CPU time 6.39 seconds
Started Dec 31 01:03:57 PM PST 23
Finished Dec 31 01:04:05 PM PST 23
Peak memory 202432 kb
Host smart-c0e3909f-3835-404f-bfbe-5aed245cc3ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843487656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.843487656
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3205216264
Short name T390
Test name
Test status
Simulation time 19843317099 ps
CPU time 1516.56 seconds
Started Dec 31 01:04:08 PM PST 23
Finished Dec 31 01:29:26 PM PST 23
Peak memory 378980 kb
Host smart-29854e2b-d9d6-4adc-a7f6-fd557e1909a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205216264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3205216264
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.3941481200
Short name T23
Test name
Test status
Simulation time 854152483 ps
CPU time 2.77 seconds
Started Dec 31 01:04:27 PM PST 23
Finished Dec 31 01:04:32 PM PST 23
Peak memory 220928 kb
Host smart-c131829b-5d8e-48dc-9d92-7a589856c194
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941481200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.3941481200
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.1799264288
Short name T585
Test name
Test status
Simulation time 4571896140 ps
CPU time 23.59 seconds
Started Dec 31 01:04:03 PM PST 23
Finished Dec 31 01:04:28 PM PST 23
Peak memory 202160 kb
Host smart-616a12a6-0421-44fd-bde1-41a22dc28ccb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799264288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1799264288
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.1606876688
Short name T558
Test name
Test status
Simulation time 105383674583 ps
CPU time 3782.07 seconds
Started Dec 31 01:04:05 PM PST 23
Finished Dec 31 02:07:09 PM PST 23
Peak memory 380136 kb
Host smart-a6553ebe-7573-4de2-8160-9d38c4067673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606876688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.1606876688
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.654964474
Short name T515
Test name
Test status
Simulation time 648047971 ps
CPU time 2202.85 seconds
Started Dec 31 01:03:53 PM PST 23
Finished Dec 31 01:40:37 PM PST 23
Peak memory 633088 kb
Host smart-48113d0d-72d3-4fb5-bd90-56876befbbf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=654964474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.654964474
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1008442944
Short name T586
Test name
Test status
Simulation time 39510535137 ps
CPU time 193.11 seconds
Started Dec 31 01:04:17 PM PST 23
Finished Dec 31 01:07:32 PM PST 23
Peak memory 202088 kb
Host smart-cb325eda-d194-4b59-9617-f6f55a66a004
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008442944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.1008442944
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3553167637
Short name T810
Test name
Test status
Simulation time 770494565 ps
CPU time 75.32 seconds
Started Dec 31 01:04:10 PM PST 23
Finished Dec 31 01:05:27 PM PST 23
Peak memory 316680 kb
Host smart-6d7380a2-5cd9-440f-a510-ef15893f0f2d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553167637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3553167637
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.763302532
Short name T17
Test name
Test status
Simulation time 14454598767 ps
CPU time 469.22 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:12:32 PM PST 23
Peak memory 373968 kb
Host smart-5389a6d6-29dd-4c94-a0e1-9838221b43bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763302532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 10.sram_ctrl_access_during_key_req.763302532
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.3403327665
Short name T490
Test name
Test status
Simulation time 46793756 ps
CPU time 0.62 seconds
Started Dec 31 01:04:29 PM PST 23
Finished Dec 31 01:04:32 PM PST 23
Peak memory 201312 kb
Host smart-aac0d70f-5e04-4f16-bd6f-500600e3a212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403327665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.3403327665
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.4266992198
Short name T371
Test name
Test status
Simulation time 121574467934 ps
CPU time 2021.52 seconds
Started Dec 31 01:04:19 PM PST 23
Finished Dec 31 01:38:03 PM PST 23
Peak memory 202072 kb
Host smart-b5f564dc-43b2-48b3-aeb9-d1f5c7152a6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266992198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.4266992198
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.913063762
Short name T129
Test name
Test status
Simulation time 36834123919 ps
CPU time 1113.53 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:22:59 PM PST 23
Peak memory 376884 kb
Host smart-4f6a82e2-9a23-41da-83cf-03d52fc0bf71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913063762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executabl
e.913063762
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.3636432786
Short name T287
Test name
Test status
Simulation time 1904567738 ps
CPU time 115.96 seconds
Started Dec 31 01:04:20 PM PST 23
Finished Dec 31 01:06:18 PM PST 23
Peak memory 364692 kb
Host smart-bb5ed705-6ace-49b9-b641-30e709f3b980
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636432786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.3636432786
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3178683416
Short name T530
Test name
Test status
Simulation time 9410471222 ps
CPU time 81.37 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:05:59 PM PST 23
Peak memory 218492 kb
Host smart-8c57bb53-c169-4041-8894-64d2e09baf6b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178683416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.3178683416
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.1338357036
Short name T841
Test name
Test status
Simulation time 19728870171 ps
CPU time 134.11 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 01:06:37 PM PST 23
Peak memory 202264 kb
Host smart-16749fe5-06a9-4ccf-9d4c-34585736c839
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338357036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.1338357036
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.3008947427
Short name T278
Test name
Test status
Simulation time 22158736878 ps
CPU time 1042.82 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:21:48 PM PST 23
Peak memory 380168 kb
Host smart-fa93af6c-9d24-4a02-badc-dae61df003b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008947427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.3008947427
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.3629458997
Short name T755
Test name
Test status
Simulation time 5276930718 ps
CPU time 172.16 seconds
Started Dec 31 01:04:22 PM PST 23
Finished Dec 31 01:07:16 PM PST 23
Peak memory 372832 kb
Host smart-f5a66a8b-3a65-4c8c-b646-71211de66e69
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629458997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.3629458997
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1429488806
Short name T394
Test name
Test status
Simulation time 20496216565 ps
CPU time 532.15 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:13:20 PM PST 23
Peak memory 202092 kb
Host smart-f5f23ecf-c256-4bed-8076-c41ad0500d59
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429488806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.1429488806
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.1821667050
Short name T908
Test name
Test status
Simulation time 3726570636 ps
CPU time 14.32 seconds
Started Dec 31 01:04:19 PM PST 23
Finished Dec 31 01:04:36 PM PST 23
Peak memory 202472 kb
Host smart-c4301f38-350e-4091-bd7c-051d14cf5487
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821667050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1821667050
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.2437692711
Short name T251
Test name
Test status
Simulation time 9434844244 ps
CPU time 1319.99 seconds
Started Dec 31 01:04:30 PM PST 23
Finished Dec 31 01:26:34 PM PST 23
Peak memory 380164 kb
Host smart-f7910b78-9d3b-4dc6-b6a7-b1e328aa398d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437692711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2437692711
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.962708767
Short name T698
Test name
Test status
Simulation time 1801276464 ps
CPU time 30.11 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 01:05:05 PM PST 23
Peak memory 202080 kb
Host smart-d15f408d-4c8f-45c2-aaa0-e2cb31ff6a33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962708767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.962708767
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.1804880124
Short name T373
Test name
Test status
Simulation time 103989089640 ps
CPU time 5877.31 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 02:42:25 PM PST 23
Peak memory 380124 kb
Host smart-e73bfbc7-6d11-45ee-ad6a-c7131d711ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804880124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.1804880124
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.465786670
Short name T868
Test name
Test status
Simulation time 1131063072 ps
CPU time 5195.48 seconds
Started Dec 31 01:04:30 PM PST 23
Finished Dec 31 02:31:10 PM PST 23
Peak memory 460576 kb
Host smart-9e3bda22-ff62-4ed3-a93e-a8847353652b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=465786670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.465786670
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3487077754
Short name T106
Test name
Test status
Simulation time 5151544765 ps
CPU time 383.64 seconds
Started Dec 31 01:04:20 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 202044 kb
Host smart-0e53fa1a-f52e-4756-8261-394a7a3942af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487077754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.3487077754
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4253659043
Short name T337
Test name
Test status
Simulation time 8484689086 ps
CPU time 30.52 seconds
Started Dec 31 01:04:38 PM PST 23
Finished Dec 31 01:05:13 PM PST 23
Peak memory 220372 kb
Host smart-bec27444-291d-45cc-9ad3-6662a3236342
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253659043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.4253659043
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2919067479
Short name T653
Test name
Test status
Simulation time 43039123979 ps
CPU time 1054.25 seconds
Started Dec 31 01:04:27 PM PST 23
Finished Dec 31 01:22:04 PM PST 23
Peak memory 380128 kb
Host smart-0c317811-e405-4e84-9c7d-fe6e1e149af3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919067479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.2919067479
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.519452394
Short name T695
Test name
Test status
Simulation time 27605318 ps
CPU time 0.65 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:04:28 PM PST 23
Peak memory 201892 kb
Host smart-4d75f660-5049-408c-bbe0-505830cb6cc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519452394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.519452394
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.1688602999
Short name T857
Test name
Test status
Simulation time 200896199585 ps
CPU time 1118.08 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 01:23:13 PM PST 23
Peak memory 202148 kb
Host smart-d7f8603a-99fd-4eb8-97ca-cd5d488bd50c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688602999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.1688602999
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.843659091
Short name T958
Test name
Test status
Simulation time 158736914570 ps
CPU time 1056.32 seconds
Started Dec 31 01:04:28 PM PST 23
Finished Dec 31 01:22:07 PM PST 23
Peak memory 378976 kb
Host smart-2fbdbf51-7acd-484e-917f-745b93cae8f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843659091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executabl
e.843659091
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.1039954596
Short name T456
Test name
Test status
Simulation time 12571066512 ps
CPU time 132.87 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 01:06:36 PM PST 23
Peak memory 354496 kb
Host smart-e6de60bd-15ce-49fd-a0b3-3c93ddf2e02d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039954596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.1039954596
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3878744346
Short name T68
Test name
Test status
Simulation time 4917392113 ps
CPU time 76.59 seconds
Started Dec 31 01:04:28 PM PST 23
Finished Dec 31 01:05:47 PM PST 23
Peak memory 218472 kb
Host smart-3df9f6a2-78f3-4165-887d-85a577029f0d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878744346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.3878744346
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.3940221246
Short name T699
Test name
Test status
Simulation time 16422398569 ps
CPU time 256.23 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:08:42 PM PST 23
Peak memory 202156 kb
Host smart-b62dd419-5e78-4fe5-bbc4-cbb78e1e24aa
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940221246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.3940221246
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.4140640127
Short name T309
Test name
Test status
Simulation time 19868308666 ps
CPU time 1224.33 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:24:52 PM PST 23
Peak memory 376952 kb
Host smart-93036143-4783-48af-bd30-c5a2647eaf08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140640127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.4140640127
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.1067173630
Short name T814
Test name
Test status
Simulation time 3361926735 ps
CPU time 16.99 seconds
Started Dec 31 01:04:32 PM PST 23
Finished Dec 31 01:04:52 PM PST 23
Peak memory 202072 kb
Host smart-4c42f1fc-68a2-44c4-8d8c-0b94758352f6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067173630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.1067173630
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.934756139
Short name T391
Test name
Test status
Simulation time 10304286550 ps
CPU time 219.24 seconds
Started Dec 31 01:04:24 PM PST 23
Finished Dec 31 01:08:05 PM PST 23
Peak memory 210276 kb
Host smart-6bfc77e5-b950-46fc-ad8b-244d61a8e14f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934756139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.sram_ctrl_partial_access_b2b.934756139
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.2895892515
Short name T424
Test name
Test status
Simulation time 351591234 ps
CPU time 6.8 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:04:34 PM PST 23
Peak memory 202428 kb
Host smart-c9a326e2-3477-42ff-b889-d37c99d81932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895892515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2895892515
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.3223554572
Short name T851
Test name
Test status
Simulation time 22807529879 ps
CPU time 579.24 seconds
Started Dec 31 01:04:30 PM PST 23
Finished Dec 31 01:14:13 PM PST 23
Peak memory 372952 kb
Host smart-f060a337-2b2a-4cee-ace4-8a0f0d216ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223554572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3223554572
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.1133640007
Short name T833
Test name
Test status
Simulation time 6902986382 ps
CPU time 32.02 seconds
Started Dec 31 01:04:40 PM PST 23
Finished Dec 31 01:05:17 PM PST 23
Peak memory 210360 kb
Host smart-91778ef3-fc61-4ce7-9eca-a6e569e06f25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133640007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1133640007
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3088861192
Short name T425
Test name
Test status
Simulation time 4474401061 ps
CPU time 2792.26 seconds
Started Dec 31 01:04:20 PM PST 23
Finished Dec 31 01:50:54 PM PST 23
Peak memory 519376 kb
Host smart-477e265c-cc61-4410-90cd-56779cf2b149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3088861192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3088861192
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2122676441
Short name T363
Test name
Test status
Simulation time 3721229818 ps
CPU time 241.79 seconds
Started Dec 31 01:04:28 PM PST 23
Finished Dec 31 01:08:33 PM PST 23
Peak memory 202184 kb
Host smart-27f966ee-f27f-4616-a8cd-3ab00daa3667
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122676441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.2122676441
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.570463468
Short name T338
Test name
Test status
Simulation time 774120138 ps
CPU time 142.55 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:06:50 PM PST 23
Peak memory 349824 kb
Host smart-413ee07c-81b5-4d4a-8924-ee20409a9a34
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570463468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.570463468
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.912210043
Short name T677
Test name
Test status
Simulation time 6257141879 ps
CPU time 745.51 seconds
Started Dec 31 01:04:35 PM PST 23
Finished Dec 31 01:17:03 PM PST 23
Peak memory 374972 kb
Host smart-e1aeb60f-b006-4b45-885f-9c2af0a385c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912210043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.sram_ctrl_access_during_key_req.912210043
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.2368431177
Short name T581
Test name
Test status
Simulation time 15011823 ps
CPU time 0.66 seconds
Started Dec 31 01:04:17 PM PST 23
Finished Dec 31 01:04:19 PM PST 23
Peak memory 201880 kb
Host smart-32eaedb6-a220-44cb-b7e5-58e148d8c341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368431177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.2368431177
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.402609615
Short name T875
Test name
Test status
Simulation time 71433917387 ps
CPU time 1395.32 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:27:53 PM PST 23
Peak memory 202156 kb
Host smart-2397a69a-291e-441e-a376-5581d5b8b06c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402609615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.
402609615
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.3991296232
Short name T926
Test name
Test status
Simulation time 8988380335 ps
CPU time 86.34 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:05:52 PM PST 23
Peak memory 213864 kb
Host smart-f39eb3e2-dc61-4274-aa8b-166ec66ec001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991296232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.3991296232
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.205546547
Short name T574
Test name
Test status
Simulation time 1495466184 ps
CPU time 102.8 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:06:11 PM PST 23
Peak memory 328868 kb
Host smart-4cfea726-5212-443c-a932-68025a98553d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205546547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.sram_ctrl_max_throughput.205546547
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.289813627
Short name T923
Test name
Test status
Simulation time 4455348352 ps
CPU time 145.92 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:06:51 PM PST 23
Peak memory 211216 kb
Host smart-3d7e89db-f522-43dc-a483-6b90312e94b5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289813627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.sram_ctrl_mem_partial_access.289813627
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.2028521294
Short name T720
Test name
Test status
Simulation time 94106355598 ps
CPU time 313.97 seconds
Started Dec 31 01:04:44 PM PST 23
Finished Dec 31 01:10:02 PM PST 23
Peak memory 202028 kb
Host smart-c210d057-c5c1-45c5-b62f-5588bcf6a6a6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028521294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.2028521294
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.2601413027
Short name T133
Test name
Test status
Simulation time 9618445716 ps
CPU time 279.03 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:09:06 PM PST 23
Peak memory 348324 kb
Host smart-e00d0cc5-824f-4e49-a46d-195d0692cddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601413027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.2601413027
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.1468604071
Short name T690
Test name
Test status
Simulation time 3737178279 ps
CPU time 18.27 seconds
Started Dec 31 01:04:29 PM PST 23
Finished Dec 31 01:04:51 PM PST 23
Peak memory 202144 kb
Host smart-50bdc808-eeb5-4309-8768-a03f40c685f8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468604071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.1468604071
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3479176637
Short name T819
Test name
Test status
Simulation time 6683029977 ps
CPU time 447.54 seconds
Started Dec 31 01:04:39 PM PST 23
Finished Dec 31 01:12:12 PM PST 23
Peak memory 202168 kb
Host smart-a7fb1050-fd19-427b-a94c-a4767bd5dd24
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479176637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.3479176637
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.879703148
Short name T587
Test name
Test status
Simulation time 682095024 ps
CPU time 13.27 seconds
Started Dec 31 01:04:16 PM PST 23
Finished Dec 31 01:04:31 PM PST 23
Peak memory 202480 kb
Host smart-1f99c3a6-b80c-4e69-ba52-1ff071bff9c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879703148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.879703148
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.2555843922
Short name T354
Test name
Test status
Simulation time 15626635519 ps
CPU time 1003.93 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:21:11 PM PST 23
Peak memory 379176 kb
Host smart-a30e5b95-001b-4b00-9e1c-a85a40945509
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555843922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2555843922
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.1947088718
Short name T709
Test name
Test status
Simulation time 387097591 ps
CPU time 25.24 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:05:03 PM PST 23
Peak memory 255784 kb
Host smart-963b3463-8ea7-4816-a6f7-b9cdf345d020
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947088718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1947088718
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4272143423
Short name T450
Test name
Test status
Simulation time 235261616 ps
CPU time 2912.7 seconds
Started Dec 31 01:04:30 PM PST 23
Finished Dec 31 01:53:07 PM PST 23
Peak memory 431620 kb
Host smart-870b129a-ae1d-4101-b2cc-5e1b5bd18004
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4272143423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.4272143423
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1474515780
Short name T257
Test name
Test status
Simulation time 3410934698 ps
CPU time 244.96 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:08:33 PM PST 23
Peak memory 210296 kb
Host smart-1f04c629-7076-42d6-b67d-1907c7a1e8f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474515780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.1474515780
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1334053753
Short name T606
Test name
Test status
Simulation time 1343588953 ps
CPU time 27.15 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:05:09 PM PST 23
Peak memory 210320 kb
Host smart-8d93dab8-4f38-4570-bb1a-f7e50214ddd4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334053753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1334053753
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.531018322
Short name T343
Test name
Test status
Simulation time 14150028358 ps
CPU time 677.6 seconds
Started Dec 31 01:04:38 PM PST 23
Finished Dec 31 01:16:01 PM PST 23
Peak memory 377016 kb
Host smart-d0239335-1e67-4910-8f59-be7394678ce7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531018322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.sram_ctrl_access_during_key_req.531018322
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.453959174
Short name T930
Test name
Test status
Simulation time 41661438 ps
CPU time 0.66 seconds
Started Dec 31 01:04:38 PM PST 23
Finished Dec 31 01:04:45 PM PST 23
Peak memory 201812 kb
Host smart-ecfaec08-d1c5-42fc-b926-fb1d9c7d3dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453959174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.453959174
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.1703021864
Short name T399
Test name
Test status
Simulation time 23815100844 ps
CPU time 1561.18 seconds
Started Dec 31 01:04:33 PM PST 23
Finished Dec 31 01:30:38 PM PST 23
Peak memory 202096 kb
Host smart-18296194-239e-4be0-82e8-0134c7cbe20a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703021864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.1703021864
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.2395919152
Short name T650
Test name
Test status
Simulation time 7443752388 ps
CPU time 85.24 seconds
Started Dec 31 01:04:40 PM PST 23
Finished Dec 31 01:06:11 PM PST 23
Peak memory 202120 kb
Host smart-7b620886-7c98-4b5c-83b7-4a87245e673c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395919152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.2395919152
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.4147088670
Short name T645
Test name
Test status
Simulation time 2603305379 ps
CPU time 72.79 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:05:41 PM PST 23
Peak memory 307436 kb
Host smart-6d4989ec-21bb-412a-8844-255b683814aa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147088670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.4147088670
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.298947928
Short name T636
Test name
Test status
Simulation time 1600059392 ps
CPU time 130.07 seconds
Started Dec 31 01:04:13 PM PST 23
Finished Dec 31 01:06:24 PM PST 23
Peak memory 211044 kb
Host smart-46164eed-c279-4b3c-9ba9-703d287a3cb1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298947928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.sram_ctrl_mem_partial_access.298947928
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.495069178
Short name T670
Test name
Test status
Simulation time 4113221028 ps
CPU time 130.8 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 01:06:45 PM PST 23
Peak memory 202120 kb
Host smart-ca459242-1292-4289-bad8-b0bf69002cd5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495069178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl
_mem_walk.495069178
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.2940209503
Short name T717
Test name
Test status
Simulation time 171506040218 ps
CPU time 1046.8 seconds
Started Dec 31 01:04:36 PM PST 23
Finished Dec 31 01:22:06 PM PST 23
Peak memory 380032 kb
Host smart-956a1d94-f674-47e6-9d7c-63110b9eb910
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940209503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.2940209503
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.3331255475
Short name T496
Test name
Test status
Simulation time 7570068903 ps
CPU time 41.69 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:05:09 PM PST 23
Peak memory 202132 kb
Host smart-6548634d-9c34-4baf-9cf6-9a68b766b1ed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331255475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.3331255475
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1647941095
Short name T111
Test name
Test status
Simulation time 127886800411 ps
CPU time 505.7 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:13:08 PM PST 23
Peak memory 202108 kb
Host smart-389d30c0-e504-4a46-9585-218aad4a0439
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647941095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.1647941095
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.1836186019
Short name T504
Test name
Test status
Simulation time 350121134 ps
CPU time 13.81 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:04:42 PM PST 23
Peak memory 202468 kb
Host smart-1ac9ef01-274d-4db9-8804-4941cc78bec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836186019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1836186019
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.3867640882
Short name T651
Test name
Test status
Simulation time 5171328299 ps
CPU time 404.94 seconds
Started Dec 31 01:04:35 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 372828 kb
Host smart-391bd4c0-8c46-4837-bffa-196e07ae0b13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867640882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3867640882
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.385402294
Short name T477
Test name
Test status
Simulation time 815430696 ps
CPU time 33.16 seconds
Started Dec 31 01:04:24 PM PST 23
Finished Dec 31 01:04:59 PM PST 23
Peak memory 201992 kb
Host smart-6e6e5076-8045-41e6-aadc-4300c9d6f13c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385402294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.385402294
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1195030907
Short name T632
Test name
Test status
Simulation time 4861075773 ps
CPU time 3174.11 seconds
Started Dec 31 01:04:52 PM PST 23
Finished Dec 31 01:57:48 PM PST 23
Peak memory 653156 kb
Host smart-20bee427-b4af-4651-8248-a3c23bd18134
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1195030907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1195030907
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.515511919
Short name T762
Test name
Test status
Simulation time 2247424830 ps
CPU time 196.36 seconds
Started Dec 31 01:04:43 PM PST 23
Finished Dec 31 01:08:03 PM PST 23
Peak memory 202148 kb
Host smart-a469b116-5fc4-47a0-b837-d42411cb10ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515511919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.sram_ctrl_stress_pipeline.515511919
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.419057275
Short name T303
Test name
Test status
Simulation time 3201124965 ps
CPU time 95.52 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:06:01 PM PST 23
Peak memory 326896 kb
Host smart-1342da86-b8b3-450c-851c-83e1a923af13
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419057275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_throughput_w_partial_write.419057275
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2938234892
Short name T383
Test name
Test status
Simulation time 12140220579 ps
CPU time 1079.95 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 01:22:23 PM PST 23
Peak memory 379096 kb
Host smart-1dd2def6-2852-405e-a546-6fc6bd1481f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938234892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.2938234892
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.148593827
Short name T484
Test name
Test status
Simulation time 87895607 ps
CPU time 0.62 seconds
Started Dec 31 01:04:38 PM PST 23
Finished Dec 31 01:04:44 PM PST 23
Peak memory 201896 kb
Host smart-e132f117-6446-4d05-baba-79a8f27fcd0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148593827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.148593827
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.2131873546
Short name T927
Test name
Test status
Simulation time 203278571838 ps
CPU time 1247.83 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 01:25:11 PM PST 23
Peak memory 202216 kb
Host smart-3679f0a8-9679-43db-9b3a-1332f41c2893
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131873546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.2131873546
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.3920341383
Short name T802
Test name
Test status
Simulation time 17314786238 ps
CPU time 59.22 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:05:37 PM PST 23
Peak memory 210352 kb
Host smart-8d0a3940-5833-4ee2-928c-d12179ab7c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920341383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.3920341383
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.2286465073
Short name T725
Test name
Test status
Simulation time 1559306192 ps
CPU time 179.34 seconds
Started Dec 31 01:04:36 PM PST 23
Finished Dec 31 01:07:39 PM PST 23
Peak memory 363124 kb
Host smart-3c6ec526-0a9d-4e52-8802-43bebaa75988
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286465073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.2286465073
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.917000498
Short name T69
Test name
Test status
Simulation time 6676189674 ps
CPU time 149.4 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 01:06:52 PM PST 23
Peak memory 218404 kb
Host smart-6ee7138d-f6b7-4eb3-920f-46ae7edd2332
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917000498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.sram_ctrl_mem_partial_access.917000498
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.1877493735
Short name T370
Test name
Test status
Simulation time 32907419549 ps
CPU time 123.39 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:06:30 PM PST 23
Peak memory 202132 kb
Host smart-571511f9-7c78-4c28-acf2-894413ba7d58
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877493735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.1877493735
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.3497508145
Short name T855
Test name
Test status
Simulation time 15208660073 ps
CPU time 584.67 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:14:12 PM PST 23
Peak memory 370904 kb
Host smart-882a881b-9608-4504-bd8e-a06500bc6598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497508145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.3497508145
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.2265934626
Short name T227
Test name
Test status
Simulation time 2796022192 ps
CPU time 24.6 seconds
Started Dec 31 01:04:33 PM PST 23
Finished Dec 31 01:05:01 PM PST 23
Peak memory 247984 kb
Host smart-df860c2e-a232-415c-9471-e8ed0864e477
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265934626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.2265934626
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3179542296
Short name T500
Test name
Test status
Simulation time 45635471592 ps
CPU time 259.85 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:08:47 PM PST 23
Peak memory 202172 kb
Host smart-979b3490-6de8-4fc8-aea4-767f08e35c4a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179542296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.3179542296
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.466463539
Short name T379
Test name
Test status
Simulation time 361421083 ps
CPU time 5.38 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:04:55 PM PST 23
Peak memory 202412 kb
Host smart-403526ea-259c-44a6-9021-0743c7d86324
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466463539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.466463539
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.4115412946
Short name T950
Test name
Test status
Simulation time 1742115914 ps
CPU time 92.67 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 01:06:07 PM PST 23
Peak memory 334932 kb
Host smart-5d4249b9-f230-4720-bf15-dc7e24efba6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115412946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.4115412946
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.1801975257
Short name T461
Test name
Test status
Simulation time 1891521903 ps
CPU time 9.3 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:04:37 PM PST 23
Peak memory 202080 kb
Host smart-fccb0bb7-480d-4ddf-8d18-624995fd7d40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801975257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1801975257
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3570082278
Short name T35
Test name
Test status
Simulation time 5544634786 ps
CPU time 3132.54 seconds
Started Dec 31 01:04:43 PM PST 23
Finished Dec 31 01:57:00 PM PST 23
Peak memory 536360 kb
Host smart-60bf6ae5-e363-446b-9701-8bcf613ca498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3570082278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3570082278
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3053784112
Short name T466
Test name
Test status
Simulation time 6072667965 ps
CPU time 419.13 seconds
Started Dec 31 01:04:40 PM PST 23
Finished Dec 31 01:11:45 PM PST 23
Peak memory 202172 kb
Host smart-123c414f-ecaf-4c96-8987-e1dc78006cb6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053784112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.3053784112
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4212848615
Short name T315
Test name
Test status
Simulation time 1377589361 ps
CPU time 31.75 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:05:14 PM PST 23
Peak memory 234856 kb
Host smart-a343feef-6727-4fbf-8029-c572963cea14
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212848615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.4212848615
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3418955854
Short name T382
Test name
Test status
Simulation time 7858539376 ps
CPU time 1389.91 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:27:52 PM PST 23
Peak memory 379124 kb
Host smart-3ffe30bd-2f78-4eba-9eff-fad13e4d76ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418955854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.3418955854
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.2054919032
Short name T674
Test name
Test status
Simulation time 131679785 ps
CPU time 0.61 seconds
Started Dec 31 01:04:35 PM PST 23
Finished Dec 31 01:04:38 PM PST 23
Peak memory 201424 kb
Host smart-9e842847-66bf-4681-a38b-8b280d5a4a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054919032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.2054919032
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.3579014040
Short name T233
Test name
Test status
Simulation time 112712670962 ps
CPU time 2567.44 seconds
Started Dec 31 01:04:42 PM PST 23
Finished Dec 31 01:47:34 PM PST 23
Peak memory 202076 kb
Host smart-86b9cf89-05bd-4245-a900-94ff36cce514
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579014040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.3579014040
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.3191675895
Short name T320
Test name
Test status
Simulation time 4606094563 ps
CPU time 24.9 seconds
Started Dec 31 01:04:47 PM PST 23
Finished Dec 31 01:05:14 PM PST 23
Peak memory 210428 kb
Host smart-cf5f3964-48bf-4c0f-888a-ed54c6ddf1b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191675895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.3191675895
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.1000318559
Short name T230
Test name
Test status
Simulation time 1471135532 ps
CPU time 42.1 seconds
Started Dec 31 01:04:43 PM PST 23
Finished Dec 31 01:05:29 PM PST 23
Peak memory 260848 kb
Host smart-68043145-f8c1-4b5b-b811-6ae0af0ed230
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000318559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.1000318559
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.4015748770
Short name T702
Test name
Test status
Simulation time 5956365347 ps
CPU time 137.45 seconds
Started Dec 31 01:04:22 PM PST 23
Finished Dec 31 01:06:42 PM PST 23
Peak memory 214540 kb
Host smart-e106e80b-bb7c-44b7-abc9-aba281e5644b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015748770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.4015748770
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.2158925593
Short name T922
Test name
Test status
Simulation time 3947672534 ps
CPU time 126.71 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 01:06:30 PM PST 23
Peak memory 202260 kb
Host smart-c9e06009-5ef5-4d6d-81bb-6e6e25b59c20
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158925593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.2158925593
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.701946842
Short name T773
Test name
Test status
Simulation time 15972419442 ps
CPU time 1479.82 seconds
Started Dec 31 01:04:29 PM PST 23
Finished Dec 31 01:29:12 PM PST 23
Peak memory 380024 kb
Host smart-bc8e1b82-cb4e-4a1b-963f-f41d350d1694
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701946842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip
le_keys.701946842
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.4248353347
Short name T473
Test name
Test status
Simulation time 4186689465 ps
CPU time 64.1 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:05:42 PM PST 23
Peak memory 296132 kb
Host smart-41fa1e85-4373-4b19-a2d5-048b0f51b904
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248353347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.4248353347
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2135056229
Short name T873
Test name
Test status
Simulation time 19922710246 ps
CPU time 317.67 seconds
Started Dec 31 01:04:22 PM PST 23
Finished Dec 31 01:09:41 PM PST 23
Peak memory 202104 kb
Host smart-1eb43f67-b1fa-4616-b0c3-672a9e2f15a3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135056229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.2135056229
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.59428818
Short name T943
Test name
Test status
Simulation time 1244690452 ps
CPU time 6.73 seconds
Started Dec 31 01:04:30 PM PST 23
Finished Dec 31 01:04:40 PM PST 23
Peak memory 202384 kb
Host smart-736ea051-a99e-4f0b-bda3-693c9fb873b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59428818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.59428818
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.1652510124
Short name T583
Test name
Test status
Simulation time 9211242617 ps
CPU time 798.41 seconds
Started Dec 31 01:04:36 PM PST 23
Finished Dec 31 01:17:58 PM PST 23
Peak memory 380100 kb
Host smart-8643b964-af96-43f7-8c20-705a7551c4e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652510124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1652510124
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.1700930767
Short name T788
Test name
Test status
Simulation time 948562437 ps
CPU time 16.63 seconds
Started Dec 31 01:04:33 PM PST 23
Finished Dec 31 01:04:53 PM PST 23
Peak memory 202056 kb
Host smart-1e238edc-fa45-4d48-94f3-187c5b51701c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700930767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1700930767
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.561884112
Short name T887
Test name
Test status
Simulation time 354397750654 ps
CPU time 3476.65 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 02:02:31 PM PST 23
Peak memory 379060 kb
Host smart-78e8e52b-bdb2-4a87-b280-3236aa92b05d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561884112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_stress_all.561884112
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3688480437
Short name T680
Test name
Test status
Simulation time 1863328760 ps
CPU time 2845.75 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:52:04 PM PST 23
Peak memory 699224 kb
Host smart-52babe21-ace7-476b-b35e-c8b8e167f11e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3688480437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3688480437
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.653648578
Short name T263
Test name
Test status
Simulation time 23571419858 ps
CPU time 356.82 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:10:38 PM PST 23
Peak memory 202180 kb
Host smart-cfaec351-e208-4fea-b21b-03d8c7576cf2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653648578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_stress_pipeline.653648578
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1897070652
Short name T276
Test name
Test status
Simulation time 3007134411 ps
CPU time 150.59 seconds
Started Dec 31 01:04:38 PM PST 23
Finished Dec 31 01:07:14 PM PST 23
Peak memory 366700 kb
Host smart-130fbea9-0690-44cb-ada7-6a92fa9cf989
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897070652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.1897070652
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2662937369
Short name T447
Test name
Test status
Simulation time 20782864822 ps
CPU time 747.08 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:17:05 PM PST 23
Peak memory 378820 kb
Host smart-5318ee69-af3d-454f-a3f5-ef861f165842
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662937369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.2662937369
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.2096903503
Short name T421
Test name
Test status
Simulation time 13627085 ps
CPU time 0.63 seconds
Started Dec 31 01:04:27 PM PST 23
Finished Dec 31 01:04:30 PM PST 23
Peak memory 201856 kb
Host smart-fb06d274-6eda-433b-ac14-48a6445085c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096903503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.2096903503
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.3007765490
Short name T284
Test name
Test status
Simulation time 316618612852 ps
CPU time 1298.22 seconds
Started Dec 31 01:04:36 PM PST 23
Finished Dec 31 01:26:18 PM PST 23
Peak memory 202068 kb
Host smart-611aa967-0a17-4dd7-9be7-f7e7815b15c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007765490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.3007765490
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.410110614
Short name T948
Test name
Test status
Simulation time 747983017 ps
CPU time 26.78 seconds
Started Dec 31 01:04:41 PM PST 23
Finished Dec 31 01:05:12 PM PST 23
Peak memory 210272 kb
Host smart-128f32ec-f0eb-44b6-850f-a67689f19fd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410110614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_esc
alation.410110614
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.4150137823
Short name T476
Test name
Test status
Simulation time 790059137 ps
CPU time 114.38 seconds
Started Dec 31 01:04:40 PM PST 23
Finished Dec 31 01:06:40 PM PST 23
Peak memory 353420 kb
Host smart-45bc103f-f14a-430e-8aec-755017db0757
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150137823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.4150137823
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.321194888
Short name T600
Test name
Test status
Simulation time 3971796442 ps
CPU time 81.9 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 01:05:56 PM PST 23
Peak memory 211000 kb
Host smart-c45bd702-ee3e-4836-849d-6c19a4b78bc0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321194888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.sram_ctrl_mem_partial_access.321194888
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.4161009375
Short name T842
Test name
Test status
Simulation time 4106674018 ps
CPU time 237.35 seconds
Started Dec 31 01:04:36 PM PST 23
Finished Dec 31 01:08:37 PM PST 23
Peak memory 202116 kb
Host smart-c9675a12-4159-452a-be7e-b8603771dd12
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161009375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.4161009375
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.1872141658
Short name T894
Test name
Test status
Simulation time 13134578439 ps
CPU time 610.2 seconds
Started Dec 31 01:04:28 PM PST 23
Finished Dec 31 01:14:40 PM PST 23
Peak memory 326872 kb
Host smart-7d60a209-e1d0-4db6-99dc-e6a4701fc8b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872141658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.1872141658
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.4167595816
Short name T905
Test name
Test status
Simulation time 3212344369 ps
CPU time 30.47 seconds
Started Dec 31 01:04:33 PM PST 23
Finished Dec 31 01:05:07 PM PST 23
Peak memory 273076 kb
Host smart-34fe4204-d277-4564-b362-18c287072049
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167595816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.4167595816
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3103577507
Short name T2
Test name
Test status
Simulation time 17387990103 ps
CPU time 270.1 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 01:09:04 PM PST 23
Peak memory 202188 kb
Host smart-41182bea-6b51-4050-a9a3-3af063c4bf19
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103577507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.3103577507
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.92254757
Short name T529
Test name
Test status
Simulation time 1293358398 ps
CPU time 13.67 seconds
Started Dec 31 01:04:47 PM PST 23
Finished Dec 31 01:05:03 PM PST 23
Peak memory 202396 kb
Host smart-ae91b95f-3271-4e2d-9873-0dbd30e61db2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92254757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.92254757
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.1750265326
Short name T547
Test name
Test status
Simulation time 13984734841 ps
CPU time 1251.3 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:25:34 PM PST 23
Peak memory 377992 kb
Host smart-1e535b9d-bfb8-4046-a96e-ec3522359fc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750265326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1750265326
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.2819614201
Short name T11
Test name
Test status
Simulation time 1187472856 ps
CPU time 33.04 seconds
Started Dec 31 01:04:44 PM PST 23
Finished Dec 31 01:05:20 PM PST 23
Peak memory 202080 kb
Host smart-e8e8e6d0-2fde-466b-9018-161408708a3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819614201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2819614201
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2415183545
Short name T333
Test name
Test status
Simulation time 38787457598 ps
CPU time 391.08 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:11:13 PM PST 23
Peak memory 202036 kb
Host smart-91c0be3c-4044-4b1c-acee-2e60a3a279c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415183545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.2415183545
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.961852319
Short name T10
Test name
Test status
Simulation time 2603893852 ps
CPU time 84.12 seconds
Started Dec 31 01:04:39 PM PST 23
Finished Dec 31 01:06:08 PM PST 23
Peak memory 331984 kb
Host smart-b8b82a10-2c14-403f-8828-39b0adfb3769
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961852319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_throughput_w_partial_write.961852319
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2790583234
Short name T741
Test name
Test status
Simulation time 65318695243 ps
CPU time 1122.21 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:23:25 PM PST 23
Peak memory 380132 kb
Host smart-f902ef8b-05c7-4901-9e67-e5733fbf63c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790583234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.2790583234
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.778691912
Short name T697
Test name
Test status
Simulation time 20108856 ps
CPU time 0.66 seconds
Started Dec 31 01:04:41 PM PST 23
Finished Dec 31 01:04:46 PM PST 23
Peak memory 201884 kb
Host smart-9bea9b41-73b5-4f8f-90dd-de17085a82d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778691912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.778691912
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.796843239
Short name T831
Test name
Test status
Simulation time 518911125774 ps
CPU time 1517.18 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:29:59 PM PST 23
Peak memory 202188 kb
Host smart-b46f87b3-13f0-43e0-a783-8febb3fe7cb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796843239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.
796843239
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.2792804561
Short name T910
Test name
Test status
Simulation time 25286147141 ps
CPU time 1885.25 seconds
Started Dec 31 01:04:27 PM PST 23
Finished Dec 31 01:35:55 PM PST 23
Peak memory 366800 kb
Host smart-ab66cda5-aed3-4f87-b13f-86fe6b286253
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792804561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.2792804561
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.1366542909
Short name T481
Test name
Test status
Simulation time 32666524607 ps
CPU time 77.06 seconds
Started Dec 31 01:04:40 PM PST 23
Finished Dec 31 01:06:02 PM PST 23
Peak memory 210392 kb
Host smart-7e1b676e-9200-4b00-8ad8-222b759b7887
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366542909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.1366542909
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.2506770028
Short name T304
Test name
Test status
Simulation time 3099043475 ps
CPU time 33.4 seconds
Started Dec 31 01:04:54 PM PST 23
Finished Dec 31 01:05:29 PM PST 23
Peak memory 225660 kb
Host smart-f4501389-9f5f-4645-ac1f-f186fbbe7f41
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506770028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.2506770028
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3437595391
Short name T647
Test name
Test status
Simulation time 4766134416 ps
CPU time 142.5 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:06:59 PM PST 23
Peak memory 218488 kb
Host smart-c6154528-d84b-46d9-9ed6-aac20e76974d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437595391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.3437595391
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.671352237
Short name T959
Test name
Test status
Simulation time 2061040186 ps
CPU time 120.88 seconds
Started Dec 31 01:04:39 PM PST 23
Finished Dec 31 01:06:45 PM PST 23
Peak memory 202040 kb
Host smart-c579cd06-3710-48fa-bf4a-a37f16161f08
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671352237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl
_mem_walk.671352237
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.3106162155
Short name T953
Test name
Test status
Simulation time 58849168022 ps
CPU time 1295.01 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:26:00 PM PST 23
Peak memory 380100 kb
Host smart-fb82e05c-f6fe-48c2-a076-d263ffbadf6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106162155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.3106162155
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.2479542943
Short name T705
Test name
Test status
Simulation time 2330630548 ps
CPU time 28.9 seconds
Started Dec 31 01:04:32 PM PST 23
Finished Dec 31 01:05:04 PM PST 23
Peak memory 202056 kb
Host smart-7e3991ab-0a1c-474a-90bf-4b9d3ecd3b2f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479542943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.2479542943
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4156046991
Short name T686
Test name
Test status
Simulation time 37888406521 ps
CPU time 426.57 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:11:32 PM PST 23
Peak memory 202108 kb
Host smart-74ab3def-6e30-4071-b040-68c2f35483de
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156046991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.4156046991
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.2957469120
Short name T619
Test name
Test status
Simulation time 1414016877 ps
CPU time 13.89 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:04:51 PM PST 23
Peak memory 202444 kb
Host smart-3776508c-b3b2-4e5a-ba65-b68a668717bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957469120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2957469120
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.2567893989
Short name T978
Test name
Test status
Simulation time 9414311937 ps
CPU time 699.89 seconds
Started Dec 31 01:04:32 PM PST 23
Finished Dec 31 01:16:16 PM PST 23
Peak memory 378996 kb
Host smart-612f8d7e-69c8-4182-a6c7-b36fca943a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567893989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2567893989
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.1243636463
Short name T956
Test name
Test status
Simulation time 746695152 ps
CPU time 15.51 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:04:52 PM PST 23
Peak memory 202072 kb
Host smart-c11c44f1-01ed-46e4-8c39-ff17f39e2e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243636463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1243636463
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.3484830138
Short name T828
Test name
Test status
Simulation time 37795095543 ps
CPU time 2356.66 seconds
Started Dec 31 01:04:22 PM PST 23
Finished Dec 31 01:43:41 PM PST 23
Peak memory 377960 kb
Host smart-89d9ecad-5e92-45af-ad5d-e0720ef57629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484830138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.sram_ctrl_stress_all.3484830138
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.168760242
Short name T951
Test name
Test status
Simulation time 13633936320 ps
CPU time 1838.86 seconds
Started Dec 31 01:04:37 PM PST 23
Finished Dec 31 01:35:22 PM PST 23
Peak memory 432516 kb
Host smart-c8caca50-4ffb-4243-8450-6a09de3645e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=168760242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.168760242
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2807495941
Short name T874
Test name
Test status
Simulation time 9957370515 ps
CPU time 374.04 seconds
Started Dec 31 01:04:36 PM PST 23
Finished Dec 31 01:10:54 PM PST 23
Peak memory 202172 kb
Host smart-948ce9e4-8f44-459c-bb8e-93ec63903100
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807495941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.2807495941
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1659747964
Short name T821
Test name
Test status
Simulation time 12865017403 ps
CPU time 141.16 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 01:06:55 PM PST 23
Peak memory 355584 kb
Host smart-eb6d5ab1-ee50-4d95-903b-b9b011f6a55e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659747964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1659747964
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.277392574
Short name T16
Test name
Test status
Simulation time 6246692451 ps
CPU time 1201.64 seconds
Started Dec 31 01:04:51 PM PST 23
Finished Dec 31 01:24:54 PM PST 23
Peak memory 378196 kb
Host smart-9a18b08c-ccd9-49e4-8044-8070ae62a147
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277392574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.sram_ctrl_access_during_key_req.277392574
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.1483857535
Short name T541
Test name
Test status
Simulation time 13708388 ps
CPU time 0.63 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:04:56 PM PST 23
Peak memory 201448 kb
Host smart-7c976f89-9ba3-4c0f-bc7b-8c35601601bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483857535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.1483857535
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.3477433208
Short name T603
Test name
Test status
Simulation time 27981604997 ps
CPU time 1783.15 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:34:38 PM PST 23
Peak memory 202132 kb
Host smart-ed6c24d9-cb23-4b01-b51f-6dc51292458d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477433208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.3477433208
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.568863656
Short name T589
Test name
Test status
Simulation time 1764882124 ps
CPU time 21.43 seconds
Started Dec 31 01:04:42 PM PST 23
Finished Dec 31 01:05:07 PM PST 23
Peak memory 210316 kb
Host smart-86244227-1590-42fb-b702-7df1da71b23d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568863656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc
alation.568863656
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.1309787876
Short name T350
Test name
Test status
Simulation time 807438777 ps
CPU time 155.77 seconds
Started Dec 31 01:04:50 PM PST 23
Finished Dec 31 01:07:26 PM PST 23
Peak memory 362608 kb
Host smart-bc4d1225-7fff-41ea-b9c5-94cbe88bf015
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309787876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.1309787876
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1451391923
Short name T895
Test name
Test status
Simulation time 1640659404 ps
CPU time 144.19 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:07:14 PM PST 23
Peak memory 214080 kb
Host smart-b49f8da3-9490-4fdb-8144-b9b37c9e2563
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451391923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.1451391923
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.1639565559
Short name T339
Test name
Test status
Simulation time 9341560674 ps
CPU time 145.56 seconds
Started Dec 31 01:04:36 PM PST 23
Finished Dec 31 01:07:06 PM PST 23
Peak memory 202120 kb
Host smart-bc282b46-908f-4c79-8135-9aa840770183
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639565559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.1639565559
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.236369110
Short name T237
Test name
Test status
Simulation time 110297988556 ps
CPU time 1023.24 seconds
Started Dec 31 01:04:59 PM PST 23
Finished Dec 31 01:22:03 PM PST 23
Peak memory 377860 kb
Host smart-24ca7bcb-03be-46cb-a3a3-758bc274b830
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236369110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip
le_keys.236369110
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.963776621
Short name T135
Test name
Test status
Simulation time 1906048051 ps
CPU time 8.36 seconds
Started Dec 31 01:04:42 PM PST 23
Finished Dec 31 01:04:54 PM PST 23
Peak memory 202040 kb
Host smart-b13dee92-a133-418c-9acf-a0ef76762b62
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963776621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.s
ram_ctrl_partial_access.963776621
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1846623128
Short name T4
Test name
Test status
Simulation time 52508073961 ps
CPU time 313.76 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:10:04 PM PST 23
Peak memory 202140 kb
Host smart-4eda577c-504e-4647-8e28-7fdf58f19444
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846623128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.1846623128
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.875998916
Short name T804
Test name
Test status
Simulation time 385128401 ps
CPU time 5.47 seconds
Started Dec 31 01:04:38 PM PST 23
Finished Dec 31 01:04:48 PM PST 23
Peak memory 202448 kb
Host smart-383c6fe0-320a-4496-ad0e-afe715e8e8cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875998916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.875998916
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.3913304365
Short name T266
Test name
Test status
Simulation time 32059647736 ps
CPU time 1159.41 seconds
Started Dec 31 01:04:59 PM PST 23
Finished Dec 31 01:24:20 PM PST 23
Peak memory 379360 kb
Host smart-13801b6d-96f1-4ee5-81e4-61949d74975a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913304365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3913304365
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.634781574
Short name T222
Test name
Test status
Simulation time 893950092 ps
CPU time 7.53 seconds
Started Dec 31 01:04:42 PM PST 23
Finished Dec 31 01:04:54 PM PST 23
Peak memory 202008 kb
Host smart-58012525-2a25-4ef3-8956-506dd9528d12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634781574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.634781574
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.3842059303
Short name T846
Test name
Test status
Simulation time 43323541802 ps
CPU time 2563.93 seconds
Started Dec 31 01:04:38 PM PST 23
Finished Dec 31 01:47:28 PM PST 23
Peak memory 378080 kb
Host smart-6c6d0a14-b329-40ea-bd62-984616f4e5f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842059303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.3842059303
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2051202305
Short name T215
Test name
Test status
Simulation time 1801362191 ps
CPU time 4369.25 seconds
Started Dec 31 01:04:50 PM PST 23
Finished Dec 31 02:17:41 PM PST 23
Peak memory 434548 kb
Host smart-1b2b1fb8-9171-46b6-a2ef-b8fd13a30ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2051202305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2051202305
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.4071922649
Short name T429
Test name
Test status
Simulation time 17767800082 ps
CPU time 270.91 seconds
Started Dec 31 01:04:58 PM PST 23
Finished Dec 31 01:09:30 PM PST 23
Peak memory 202168 kb
Host smart-93903e1c-7822-4ef1-992c-45f4816e5e13
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071922649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.4071922649
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2675847624
Short name T820
Test name
Test status
Simulation time 3075297309 ps
CPU time 154.52 seconds
Started Dec 31 01:04:54 PM PST 23
Finished Dec 31 01:07:31 PM PST 23
Peak memory 346336 kb
Host smart-db9c9bb5-9a81-447e-a75c-04f1298df99e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675847624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.2675847624
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.4076253261
Short name T907
Test name
Test status
Simulation time 6025540943 ps
CPU time 896.29 seconds
Started Dec 31 01:04:58 PM PST 23
Finished Dec 31 01:19:55 PM PST 23
Peak memory 380088 kb
Host smart-3c1beca6-8957-4872-b25a-8cf504e7215a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076253261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.4076253261
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.2447753076
Short name T617
Test name
Test status
Simulation time 20977367 ps
CPU time 0.63 seconds
Started Dec 31 01:04:43 PM PST 23
Finished Dec 31 01:04:47 PM PST 23
Peak memory 201776 kb
Host smart-465695ae-f521-42d7-b937-f65e42776352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447753076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.2447753076
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.108285201
Short name T346
Test name
Test status
Simulation time 106209383870 ps
CPU time 1844.52 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:35:40 PM PST 23
Peak memory 202148 kb
Host smart-026372f9-78fb-40ae-bf76-149c9d370773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108285201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.
108285201
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.1108163772
Short name T944
Test name
Test status
Simulation time 14796063790 ps
CPU time 40.87 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:05:30 PM PST 23
Peak memory 210368 kb
Host smart-f15360c0-e8a1-4db0-9196-3fd50f789917
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108163772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.1108163772
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.2527225859
Short name T656
Test name
Test status
Simulation time 1575098045 ps
CPU time 164.8 seconds
Started Dec 31 01:04:47 PM PST 23
Finished Dec 31 01:07:34 PM PST 23
Peak memory 370904 kb
Host smart-117860f1-6090-4d38-b244-a0875dc4f14c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527225859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.2527225859
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2262636952
Short name T38
Test name
Test status
Simulation time 2801130790 ps
CPU time 79.15 seconds
Started Dec 31 01:04:54 PM PST 23
Finished Dec 31 01:06:15 PM PST 23
Peak memory 210500 kb
Host smart-da1d8cff-a060-468e-aa63-5ca04d883130
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262636952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.2262636952
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.2702957749
Short name T250
Test name
Test status
Simulation time 20675948120 ps
CPU time 306.09 seconds
Started Dec 31 01:04:46 PM PST 23
Finished Dec 31 01:09:55 PM PST 23
Peak memory 202140 kb
Host smart-a325124e-a25f-4084-8e72-919677a475cf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702957749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.2702957749
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.1733345997
Short name T355
Test name
Test status
Simulation time 16154045959 ps
CPU time 663.05 seconds
Started Dec 31 01:04:43 PM PST 23
Finished Dec 31 01:15:50 PM PST 23
Peak memory 380052 kb
Host smart-473ea4bc-ce9d-4300-8bbd-9a28346c92c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733345997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.1733345997
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.862915909
Short name T384
Test name
Test status
Simulation time 791009486 ps
CPU time 13.92 seconds
Started Dec 31 01:04:58 PM PST 23
Finished Dec 31 01:05:13 PM PST 23
Peak memory 202100 kb
Host smart-429ef290-cb8a-4e4a-94e9-2a8f6d85da11
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862915909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s
ram_ctrl_partial_access.862915909
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.154441281
Short name T716
Test name
Test status
Simulation time 33017504491 ps
CPU time 348.87 seconds
Started Dec 31 01:04:54 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 202156 kb
Host smart-a63bac81-854b-499a-8f67-6432a4801741
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154441281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.sram_ctrl_partial_access_b2b.154441281
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.57689411
Short name T593
Test name
Test status
Simulation time 1406224914 ps
CPU time 14.22 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:05:10 PM PST 23
Peak memory 202392 kb
Host smart-dd4ace3c-e364-4ae0-97cf-81499a21d95d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57689411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.57689411
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.4198723071
Short name T298
Test name
Test status
Simulation time 17825258049 ps
CPU time 653.72 seconds
Started Dec 31 01:04:51 PM PST 23
Finished Dec 31 01:15:46 PM PST 23
Peak memory 353480 kb
Host smart-8e6b0b7c-760c-492e-9caa-32ee188362da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198723071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.4198723071
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.772761558
Short name T497
Test name
Test status
Simulation time 715352952 ps
CPU time 12.03 seconds
Started Dec 31 01:04:42 PM PST 23
Finished Dec 31 01:04:58 PM PST 23
Peak memory 202064 kb
Host smart-efb5ed70-9c5c-469e-94de-7f8470bb3580
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772761558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.772761558
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3344757235
Short name T975
Test name
Test status
Simulation time 4158168836 ps
CPU time 5259.13 seconds
Started Dec 31 01:04:50 PM PST 23
Finished Dec 31 02:32:31 PM PST 23
Peak memory 667340 kb
Host smart-0f07beb3-fb83-4ded-a1d1-730a42577c3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3344757235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3344757235
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3101549507
Short name T744
Test name
Test status
Simulation time 3254451825 ps
CPU time 275.81 seconds
Started Dec 31 01:04:43 PM PST 23
Finished Dec 31 01:09:23 PM PST 23
Peak memory 202184 kb
Host smart-96ef0a6d-bb37-437d-922f-f496e7356e38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101549507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.3101549507
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1688871910
Short name T659
Test name
Test status
Simulation time 2694580424 ps
CPU time 29.01 seconds
Started Dec 31 01:04:58 PM PST 23
Finished Dec 31 01:05:28 PM PST 23
Peak memory 217664 kb
Host smart-ce5ee8ff-834e-4617-af9c-6a1a9d664115
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688871910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1688871910
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1648353812
Short name T912
Test name
Test status
Simulation time 22020219226 ps
CPU time 1510.35 seconds
Started Dec 31 01:04:24 PM PST 23
Finished Dec 31 01:29:37 PM PST 23
Peak memory 377092 kb
Host smart-5698628e-b610-4491-9e59-3434f4dc2644
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648353812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.1648353812
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.809028151
Short name T377
Test name
Test status
Simulation time 26116373 ps
CPU time 0.67 seconds
Started Dec 31 01:04:01 PM PST 23
Finished Dec 31 01:04:03 PM PST 23
Peak memory 201864 kb
Host smart-a79d2558-c225-4771-bfa6-069b902ba8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809028151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.809028151
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.1420765910
Short name T258
Test name
Test status
Simulation time 12387508886 ps
CPU time 821.05 seconds
Started Dec 31 01:04:33 PM PST 23
Finished Dec 31 01:18:18 PM PST 23
Peak memory 202120 kb
Host smart-93427adf-2fe3-4b44-b071-7cf333bf1b5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420765910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
1420765910
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.1939473767
Short name T127
Test name
Test status
Simulation time 24666361820 ps
CPU time 634.85 seconds
Started Dec 31 01:04:30 PM PST 23
Finished Dec 31 01:15:08 PM PST 23
Peak memory 374936 kb
Host smart-76692470-6b8c-4014-baa9-a7142d6e7674
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939473767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.1939473767
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.2743508494
Short name T778
Test name
Test status
Simulation time 138514052833 ps
CPU time 81.57 seconds
Started Dec 31 01:04:32 PM PST 23
Finished Dec 31 01:05:57 PM PST 23
Peak memory 214184 kb
Host smart-e2597f5a-2f0c-46b4-94ae-3188088c1182
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743508494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.2743508494
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.2303067328
Short name T584
Test name
Test status
Simulation time 1494014401 ps
CPU time 82.96 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:05:50 PM PST 23
Peak memory 312028 kb
Host smart-8467e6e6-775f-4a14-8fe3-e41ab6e5cfa9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303067328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.2303067328
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2925145522
Short name T683
Test name
Test status
Simulation time 1973787886 ps
CPU time 72.29 seconds
Started Dec 31 01:04:33 PM PST 23
Finished Dec 31 01:05:49 PM PST 23
Peak memory 211120 kb
Host smart-14d24246-e199-487b-b03c-4b454611f751
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925145522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.2925145522
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.2878538069
Short name T482
Test name
Test status
Simulation time 124875599161 ps
CPU time 304.79 seconds
Started Dec 31 01:04:29 PM PST 23
Finished Dec 31 01:09:37 PM PST 23
Peak memory 202364 kb
Host smart-a1ddb08a-9f22-4b11-99de-d17305b803f0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878538069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.2878538069
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.128965879
Short name T286
Test name
Test status
Simulation time 18017123644 ps
CPU time 961.57 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:20:29 PM PST 23
Peak memory 379016 kb
Host smart-a5934be8-9f6a-4409-91e3-ded4342a686f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128965879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multipl
e_keys.128965879
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.121017432
Short name T131
Test name
Test status
Simulation time 9657529229 ps
CPU time 27.65 seconds
Started Dec 31 01:04:27 PM PST 23
Finished Dec 31 01:05:03 PM PST 23
Peak memory 202100 kb
Host smart-03f6f32a-158e-42e1-a482-46edc7d2b63f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121017432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sr
am_ctrl_partial_access.121017432
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1842673625
Short name T487
Test name
Test status
Simulation time 138388204296 ps
CPU time 180.71 seconds
Started Dec 31 01:04:30 PM PST 23
Finished Dec 31 01:07:34 PM PST 23
Peak memory 202136 kb
Host smart-a45cce95-46d8-4a26-9657-10001883c8e6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842673625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.1842673625
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.1284554199
Short name T531
Test name
Test status
Simulation time 1268186601 ps
CPU time 6.17 seconds
Started Dec 31 01:04:29 PM PST 23
Finished Dec 31 01:04:38 PM PST 23
Peak memory 202352 kb
Host smart-3c8dee53-b0f6-4ff7-adef-5f6b5e816eae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284554199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1284554199
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.2957333510
Short name T301
Test name
Test status
Simulation time 58142610142 ps
CPU time 835.78 seconds
Started Dec 31 01:04:28 PM PST 23
Finished Dec 31 01:18:26 PM PST 23
Peak memory 376096 kb
Host smart-41541b93-6cec-4558-8b2c-7c94278f2d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957333510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2957333510
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.518891795
Short name T22
Test name
Test status
Simulation time 453668124 ps
CPU time 1.9 seconds
Started Dec 31 01:03:54 PM PST 23
Finished Dec 31 01:03:58 PM PST 23
Peak memory 221036 kb
Host smart-b1a02bfc-1c9a-4da6-a1aa-ab2e039ff1fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518891795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_sec_cm.518891795
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.1291568786
Short name T601
Test name
Test status
Simulation time 6098406345 ps
CPU time 111.31 seconds
Started Dec 31 01:04:28 PM PST 23
Finished Dec 31 01:06:22 PM PST 23
Peak memory 345228 kb
Host smart-ade6ca59-4dc5-4dd6-9670-461083c7a4c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291568786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1291568786
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1162066148
Short name T367
Test name
Test status
Simulation time 11224739391 ps
CPU time 3965.64 seconds
Started Dec 31 01:03:55 PM PST 23
Finished Dec 31 02:10:03 PM PST 23
Peak memory 555880 kb
Host smart-8845c982-a616-4f5e-b580-bb74eb9f89df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1162066148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1162066148
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1787848456
Short name T366
Test name
Test status
Simulation time 57182059949 ps
CPU time 349.63 seconds
Started Dec 31 01:04:15 PM PST 23
Finished Dec 31 01:10:06 PM PST 23
Peak memory 202080 kb
Host smart-f0ffb172-1305-43d1-8340-8915ea32d312
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787848456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.1787848456
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.911838724
Short name T877
Test name
Test status
Simulation time 3254128400 ps
CPU time 160.31 seconds
Started Dec 31 01:04:33 PM PST 23
Finished Dec 31 01:07:17 PM PST 23
Peak memory 366528 kb
Host smart-51c7e029-177e-45a3-81ed-f5ceca4ffb00
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911838724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.911838724
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.444345011
Short name T513
Test name
Test status
Simulation time 122173801091 ps
CPU time 1512.16 seconds
Started Dec 31 01:04:56 PM PST 23
Finished Dec 31 01:30:09 PM PST 23
Peak memory 379100 kb
Host smart-21cb6f81-e217-43a4-83cf-740f321d261a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444345011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 20.sram_ctrl_access_during_key_req.444345011
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.422165128
Short name T308
Test name
Test status
Simulation time 20254497 ps
CPU time 0.64 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:04:50 PM PST 23
Peak memory 201796 kb
Host smart-8937b721-a8cd-4fce-9e97-41af53347b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422165128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.422165128
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.1315834364
Short name T467
Test name
Test status
Simulation time 17387841382 ps
CPU time 1207.11 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:24:57 PM PST 23
Peak memory 202224 kb
Host smart-ea5d1639-6f21-44d4-a3cc-31ecee24ef9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315834364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.1315834364
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.3624574819
Short name T392
Test name
Test status
Simulation time 19559035340 ps
CPU time 709.58 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:16:39 PM PST 23
Peak memory 379156 kb
Host smart-044fb3f4-8e84-4306-b45f-c10401fd6a08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624574819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.3624574819
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.1294204499
Short name T913
Test name
Test status
Simulation time 94155406262 ps
CPU time 144.5 seconds
Started Dec 31 01:04:58 PM PST 23
Finished Dec 31 01:07:23 PM PST 23
Peak memory 210368 kb
Host smart-11a10ff7-ec9e-4e5b-bd92-f62b40134015
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294204499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.1294204499
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.546806696
Short name T562
Test name
Test status
Simulation time 3025831363 ps
CPU time 135.18 seconds
Started Dec 31 01:04:43 PM PST 23
Finished Dec 31 01:07:02 PM PST 23
Peak memory 352496 kb
Host smart-761f23cf-91af-49b7-a19f-d59321624cfc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546806696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.sram_ctrl_max_throughput.546806696
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.4099979452
Short name T428
Test name
Test status
Simulation time 2510232515 ps
CPU time 83.43 seconds
Started Dec 31 01:04:46 PM PST 23
Finished Dec 31 01:06:12 PM PST 23
Peak memory 210724 kb
Host smart-7c0bd567-33f2-4c11-aa6a-1eadbb6b72ed
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099979452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.4099979452
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.739160195
Short name T389
Test name
Test status
Simulation time 21078919387 ps
CPU time 317.97 seconds
Started Dec 31 01:04:41 PM PST 23
Finished Dec 31 01:10:04 PM PST 23
Peak memory 202168 kb
Host smart-8477ecfd-1b4d-4f34-9c4f-9be80d2b4887
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739160195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl
_mem_walk.739160195
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.3136249612
Short name T642
Test name
Test status
Simulation time 5359505931 ps
CPU time 152.21 seconds
Started Dec 31 01:04:44 PM PST 23
Finished Dec 31 01:07:20 PM PST 23
Peak memory 375944 kb
Host smart-d4c736eb-6fa5-4331-9c14-f429654d3496
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136249612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.3136249612
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1685912429
Short name T644
Test name
Test status
Simulation time 28783390600 ps
CPU time 448.17 seconds
Started Dec 31 01:04:50 PM PST 23
Finished Dec 31 01:12:20 PM PST 23
Peak memory 202180 kb
Host smart-9fffef45-5cb1-4300-9bdf-78da7f950e10
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685912429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.1685912429
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.4112397412
Short name T539
Test name
Test status
Simulation time 1348430744 ps
CPU time 6.33 seconds
Started Dec 31 01:04:50 PM PST 23
Finished Dec 31 01:04:57 PM PST 23
Peak memory 202332 kb
Host smart-a0cfc59d-0fff-4d7a-935e-e80b06121153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112397412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.4112397412
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.3606592222
Short name T781
Test name
Test status
Simulation time 39438986217 ps
CPU time 537.33 seconds
Started Dec 31 01:04:51 PM PST 23
Finished Dec 31 01:13:50 PM PST 23
Peak memory 358716 kb
Host smart-f6643890-e488-4428-915b-ccf12ef255a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606592222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3606592222
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.1092858295
Short name T890
Test name
Test status
Simulation time 3336691303 ps
CPU time 63.07 seconds
Started Dec 31 01:04:52 PM PST 23
Finished Dec 31 01:05:57 PM PST 23
Peak memory 319844 kb
Host smart-bb3b5b15-03c0-4306-a34c-2ef32dad2e99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092858295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1092858295
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3321023334
Short name T931
Test name
Test status
Simulation time 3245525482 ps
CPU time 1843.42 seconds
Started Dec 31 01:04:45 PM PST 23
Finished Dec 31 01:35:31 PM PST 23
Peak memory 420308 kb
Host smart-8e5ad10d-0c10-466c-b10b-d4d5deb81528
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3321023334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3321023334
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1461818789
Short name T405
Test name
Test status
Simulation time 11476719030 ps
CPU time 362.69 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:10:58 PM PST 23
Peak memory 202160 kb
Host smart-d30d4d0a-269c-451e-b059-5cbe7a056e39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461818789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.1461818789
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1943081127
Short name T660
Test name
Test status
Simulation time 726333729 ps
CPU time 30.47 seconds
Started Dec 31 01:04:51 PM PST 23
Finished Dec 31 01:05:23 PM PST 23
Peak memory 225384 kb
Host smart-7df0ed1b-3315-40b3-836d-fafc63918bc5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943081127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.1943081127
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3629603006
Short name T335
Test name
Test status
Simulation time 4963841592 ps
CPU time 298.15 seconds
Started Dec 31 01:04:47 PM PST 23
Finished Dec 31 01:09:47 PM PST 23
Peak memory 309440 kb
Host smart-8cb73235-8568-40c2-9e8e-f2b7d2b7c7f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629603006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.3629603006
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.4212583212
Short name T669
Test name
Test status
Simulation time 34754370 ps
CPU time 0.61 seconds
Started Dec 31 01:04:58 PM PST 23
Finished Dec 31 01:05:00 PM PST 23
Peak memory 201892 kb
Host smart-c4af1745-12cc-456d-9e0c-7b3dd3fcae18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212583212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.4212583212
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.3876593511
Short name T775
Test name
Test status
Simulation time 48552325364 ps
CPU time 556.28 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:14:12 PM PST 23
Peak memory 202120 kb
Host smart-2c8cf501-6eac-4f15-b24a-0c802e9c278d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876593511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.3876593511
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.882471632
Short name T794
Test name
Test status
Simulation time 780312874 ps
CPU time 58.96 seconds
Started Dec 31 01:04:54 PM PST 23
Finished Dec 31 01:05:55 PM PST 23
Peak memory 289956 kb
Host smart-8db53488-2bfe-4026-8772-606916ba0dae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882471632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.sram_ctrl_max_throughput.882471632
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.462547267
Short name T715
Test name
Test status
Simulation time 1586265735 ps
CPU time 134.54 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:07:09 PM PST 23
Peak memory 211260 kb
Host smart-69c8f4f7-f782-46c3-b7cb-274370226ca5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462547267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.sram_ctrl_mem_partial_access.462547267
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.2874380653
Short name T375
Test name
Test status
Simulation time 20295774296 ps
CPU time 137.49 seconds
Started Dec 31 01:05:12 PM PST 23
Finished Dec 31 01:07:30 PM PST 23
Peak memory 202220 kb
Host smart-b8ed4671-9af5-4e4a-b57d-8408f75cfe6a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874380653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.2874380653
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.3099661077
Short name T858
Test name
Test status
Simulation time 2506377885 ps
CPU time 72.88 seconds
Started Dec 31 01:04:52 PM PST 23
Finished Dec 31 01:06:07 PM PST 23
Peak memory 290112 kb
Host smart-5cb2dfc1-f8be-46df-9683-97189b849488
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099661077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.3099661077
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.1652890199
Short name T847
Test name
Test status
Simulation time 2030190025 ps
CPU time 30.27 seconds
Started Dec 31 01:04:47 PM PST 23
Finished Dec 31 01:05:19 PM PST 23
Peak memory 202016 kb
Host smart-53d3bf73-d77a-4eee-be0f-3d1dffbbfdc3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652890199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.1652890199
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.821309773
Short name T521
Test name
Test status
Simulation time 86670112984 ps
CPU time 543.14 seconds
Started Dec 31 01:04:51 PM PST 23
Finished Dec 31 01:13:55 PM PST 23
Peak memory 202168 kb
Host smart-3ee484bd-d8a0-490c-bcfb-2bf5da9f0571
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821309773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.sram_ctrl_partial_access_b2b.821309773
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.2536475031
Short name T906
Test name
Test status
Simulation time 57232774073 ps
CPU time 1090.63 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:23:01 PM PST 23
Peak memory 373992 kb
Host smart-d2cf5dec-267e-4858-9656-e5a6f2f65dc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536475031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2536475031
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.1053697684
Short name T728
Test name
Test status
Simulation time 1295562979 ps
CPU time 21.54 seconds
Started Dec 31 01:04:51 PM PST 23
Finished Dec 31 01:05:14 PM PST 23
Peak memory 202056 kb
Host smart-43a3f58e-0f0b-43a7-b757-12494b84cc77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053697684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1053697684
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3492310379
Short name T516
Test name
Test status
Simulation time 22428200755 ps
CPU time 4960.76 seconds
Started Dec 31 01:04:50 PM PST 23
Finished Dec 31 02:27:32 PM PST 23
Peak memory 698752 kb
Host smart-b65eb78e-ed8e-4b63-88dc-f34bd468cd54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3492310379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.3492310379
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2814274434
Short name T771
Test name
Test status
Simulation time 7812663218 ps
CPU time 279.01 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:09:35 PM PST 23
Peak memory 202160 kb
Host smart-98055005-32c9-4036-927b-2e812263f9a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814274434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.2814274434
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3596999552
Short name T604
Test name
Test status
Simulation time 1618862274 ps
CPU time 134.91 seconds
Started Dec 31 01:05:01 PM PST 23
Finished Dec 31 01:07:17 PM PST 23
Peak memory 357500 kb
Host smart-dda32870-43be-44f3-990a-ef0fc6ff10a5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596999552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3596999552
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1109512429
Short name T80
Test name
Test status
Simulation time 6715250110 ps
CPU time 592.14 seconds
Started Dec 31 01:04:45 PM PST 23
Finished Dec 31 01:14:40 PM PST 23
Peak memory 378980 kb
Host smart-356d9e0d-9279-4164-9e2b-bfb2f94c4f59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109512429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.1109512429
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.215790581
Short name T43
Test name
Test status
Simulation time 24347747 ps
CPU time 0.66 seconds
Started Dec 31 01:04:52 PM PST 23
Finished Dec 31 01:04:54 PM PST 23
Peak memory 201440 kb
Host smart-2903bdd9-f85c-4691-8c4d-6d7ecd6df251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215790581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.215790581
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.2726749456
Short name T342
Test name
Test status
Simulation time 116039601008 ps
CPU time 680.38 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:16:10 PM PST 23
Peak memory 202156 kb
Host smart-9fcafc03-33b8-4d8c-b367-9738301abb0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726749456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.2726749456
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.1869312863
Short name T352
Test name
Test status
Simulation time 15603539951 ps
CPU time 89.89 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:06:24 PM PST 23
Peak memory 213824 kb
Host smart-4ba060e6-264d-45f6-b7b9-15b54568d4d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869312863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.1869312863
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.4124180784
Short name T745
Test name
Test status
Simulation time 2857692251 ps
CPU time 53.05 seconds
Started Dec 31 01:05:00 PM PST 23
Finished Dec 31 01:05:54 PM PST 23
Peak memory 283908 kb
Host smart-1be7b321-c55f-42b6-8ab0-0287b14a8788
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124180784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.4124180784
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3682435805
Short name T398
Test name
Test status
Simulation time 30544765210 ps
CPU time 159.84 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:07:34 PM PST 23
Peak memory 213668 kb
Host smart-d4452947-513a-4a3c-96d6-6d85772bf7e1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682435805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.3682435805
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.3727570037
Short name T742
Test name
Test status
Simulation time 89932459657 ps
CPU time 310.76 seconds
Started Dec 31 01:04:49 PM PST 23
Finished Dec 31 01:10:01 PM PST 23
Peak memory 202148 kb
Host smart-5ae63e98-af83-4b38-973d-924009be6f6f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727570037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.3727570037
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.109389419
Short name T648
Test name
Test status
Simulation time 41899316014 ps
CPU time 1678.38 seconds
Started Dec 31 01:04:52 PM PST 23
Finished Dec 31 01:32:52 PM PST 23
Peak memory 380084 kb
Host smart-5db1c980-db4b-4581-9702-6cfb81505a7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109389419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multip
le_keys.109389419
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.3399442578
Short name T459
Test name
Test status
Simulation time 837558405 ps
CPU time 63.03 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:05:58 PM PST 23
Peak memory 305020 kb
Host smart-95654050-bc4c-4ae2-a7bc-84481751b324
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399442578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.3399442578
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2049169506
Short name T441
Test name
Test status
Simulation time 28294529102 ps
CPU time 469.97 seconds
Started Dec 31 01:04:50 PM PST 23
Finished Dec 31 01:12:41 PM PST 23
Peak memory 202144 kb
Host smart-a43a769e-4199-4532-ba62-53a8dddcb6dd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049169506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.2049169506
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.2793670600
Short name T752
Test name
Test status
Simulation time 366098721 ps
CPU time 6.84 seconds
Started Dec 31 01:04:47 PM PST 23
Finished Dec 31 01:04:56 PM PST 23
Peak memory 202384 kb
Host smart-7166131e-e625-40cd-b77f-0dd50c000bc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793670600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2793670600
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.3455495496
Short name T892
Test name
Test status
Simulation time 76272798535 ps
CPU time 1386.68 seconds
Started Dec 31 01:04:46 PM PST 23
Finished Dec 31 01:27:55 PM PST 23
Peak memory 380052 kb
Host smart-75abb890-a698-4ec4-8f35-bba784e29022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455495496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3455495496
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.456284617
Short name T505
Test name
Test status
Simulation time 4429558807 ps
CPU time 20.51 seconds
Started Dec 31 01:04:55 PM PST 23
Finished Dec 31 01:05:17 PM PST 23
Peak memory 202080 kb
Host smart-3e97be10-5572-48d9-943d-ae1592a5c58a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456284617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.456284617
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.3500340993
Short name T897
Test name
Test status
Simulation time 871849528465 ps
CPU time 6721.52 seconds
Started Dec 31 01:04:47 PM PST 23
Finished Dec 31 02:56:51 PM PST 23
Peak memory 210332 kb
Host smart-e37b2697-5758-4114-a1cf-131345a33b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500340993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.3500340993
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.226034646
Short name T655
Test name
Test status
Simulation time 10681537227 ps
CPU time 237.52 seconds
Started Dec 31 01:04:47 PM PST 23
Finished Dec 31 01:08:47 PM PST 23
Peak memory 202184 kb
Host smart-c36fedab-2fe0-4d9b-9a61-7c4c96a39e26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226034646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_stress_pipeline.226034646
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3006103750
Short name T220
Test name
Test status
Simulation time 783270043 ps
CPU time 139.6 seconds
Started Dec 31 01:04:59 PM PST 23
Finished Dec 31 01:07:20 PM PST 23
Peak memory 361804 kb
Host smart-df6c68d4-87fb-4828-b7d5-0f35e0431ee8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006103750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3006103750
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.52349846
Short name T573
Test name
Test status
Simulation time 65055634677 ps
CPU time 1793.86 seconds
Started Dec 31 01:04:49 PM PST 23
Finished Dec 31 01:34:44 PM PST 23
Peak memory 381100 kb
Host smart-351db510-8fe3-4487-b5c8-47546d2f1964
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52349846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.sram_ctrl_access_during_key_req.52349846
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.3560949821
Short name T232
Test name
Test status
Simulation time 43137157 ps
CPU time 0.64 seconds
Started Dec 31 01:04:57 PM PST 23
Finished Dec 31 01:04:59 PM PST 23
Peak memory 201388 kb
Host smart-ade456fb-f717-425d-9848-2a220ac95551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560949821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.3560949821
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.2716785070
Short name T132
Test name
Test status
Simulation time 61471059931 ps
CPU time 1988.29 seconds
Started Dec 31 01:04:56 PM PST 23
Finished Dec 31 01:38:06 PM PST 23
Peak memory 202160 kb
Host smart-5074d1c3-373b-4c3a-9181-1befc973f775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716785070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.2716785070
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.1310307811
Short name T718
Test name
Test status
Simulation time 6757887445 ps
CPU time 647.73 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:15:43 PM PST 23
Peak memory 379088 kb
Host smart-96978a0b-37d9-4333-a028-91841b1003f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310307811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.1310307811
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.3545914004
Short name T356
Test name
Test status
Simulation time 124982240491 ps
CPU time 136.82 seconds
Started Dec 31 01:04:57 PM PST 23
Finished Dec 31 01:07:15 PM PST 23
Peak memory 214004 kb
Host smart-706609b5-383b-4dee-a9cd-6ed815647543
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545914004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.3545914004
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.1324848539
Short name T563
Test name
Test status
Simulation time 1485775722 ps
CPU time 89.16 seconds
Started Dec 31 01:04:59 PM PST 23
Finished Dec 31 01:06:30 PM PST 23
Peak memory 329116 kb
Host smart-8e82c4e6-9b8e-4e7d-8f4f-dc077e288362
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324848539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.1324848539
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.127972534
Short name T751
Test name
Test status
Simulation time 18966512737 ps
CPU time 156.95 seconds
Started Dec 31 01:04:52 PM PST 23
Finished Dec 31 01:07:30 PM PST 23
Peak memory 211136 kb
Host smart-241495bb-4c8b-4c93-b569-188a10209d36
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127972534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.sram_ctrl_mem_partial_access.127972534
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.380369691
Short name T946
Test name
Test status
Simulation time 26263021010 ps
CPU time 249.69 seconds
Started Dec 31 01:04:55 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 202340 kb
Host smart-f509b14f-28e4-46f5-be61-9d80305227d0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380369691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl
_mem_walk.380369691
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.2731993829
Short name T723
Test name
Test status
Simulation time 32465111665 ps
CPU time 876.08 seconds
Started Dec 31 01:04:43 PM PST 23
Finished Dec 31 01:19:23 PM PST 23
Peak memory 376088 kb
Host smart-ab9eec2e-e586-4d7f-a0c3-06937ec0298d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731993829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.2731993829
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.2708601841
Short name T453
Test name
Test status
Simulation time 5123149913 ps
CPU time 42.36 seconds
Started Dec 31 01:04:49 PM PST 23
Finished Dec 31 01:05:32 PM PST 23
Peak memory 202068 kb
Host smart-06f11ecc-2187-40c4-934a-9f9612de0b0a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708601841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.2708601841
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2425021225
Short name T663
Test name
Test status
Simulation time 9228597430 ps
CPU time 448.19 seconds
Started Dec 31 01:05:00 PM PST 23
Finished Dec 31 01:12:29 PM PST 23
Peak memory 202092 kb
Host smart-4380fd27-5c39-4303-bbb9-b91dd8ec9832
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425021225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.2425021225
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2741897903
Short name T610
Test name
Test status
Simulation time 681991443 ps
CPU time 13.48 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:05:03 PM PST 23
Peak memory 202456 kb
Host smart-0802f993-b60f-4b33-896a-54b965c4451e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741897903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2741897903
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.3822088223
Short name T454
Test name
Test status
Simulation time 19906457320 ps
CPU time 1549.73 seconds
Started Dec 31 01:04:49 PM PST 23
Finished Dec 31 01:30:40 PM PST 23
Peak memory 380032 kb
Host smart-39fdedfc-8943-4fa8-b7c2-37f47a8a6aa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822088223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3822088223
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.2392343287
Short name T792
Test name
Test status
Simulation time 1768800498 ps
CPU time 154.09 seconds
Started Dec 31 01:04:51 PM PST 23
Finished Dec 31 01:07:26 PM PST 23
Peak memory 366600 kb
Host smart-3b19bac6-d3d8-4af7-a11b-4392abab2f94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392343287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2392343287
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.352940876
Short name T311
Test name
Test status
Simulation time 2230648930 ps
CPU time 2007.17 seconds
Started Dec 31 01:04:47 PM PST 23
Finished Dec 31 01:38:16 PM PST 23
Peak memory 402840 kb
Host smart-d90aa6b5-9b79-4aed-8a82-d04c662f3127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=352940876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.352940876
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2497122425
Short name T756
Test name
Test status
Simulation time 19986042302 ps
CPU time 398.81 seconds
Started Dec 31 01:04:56 PM PST 23
Finished Dec 31 01:11:36 PM PST 23
Peak memory 202164 kb
Host smart-a56f4170-a4d4-4cb7-8c80-309a123ace68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497122425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.2497122425
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1081356584
Short name T525
Test name
Test status
Simulation time 1397602512 ps
CPU time 34.16 seconds
Started Dec 31 01:04:54 PM PST 23
Finished Dec 31 01:05:31 PM PST 23
Peak memory 234872 kb
Host smart-458c48c9-9ce7-490f-b0ec-bdb1e970854b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081356584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.1081356584
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2913966122
Short name T288
Test name
Test status
Simulation time 21518977624 ps
CPU time 1246.05 seconds
Started Dec 31 01:04:52 PM PST 23
Finished Dec 31 01:25:39 PM PST 23
Peak memory 377968 kb
Host smart-9c8b7269-bd03-4ba7-a804-fd34c563803e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913966122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.2913966122
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.107376225
Short name T618
Test name
Test status
Simulation time 17672517 ps
CPU time 0.65 seconds
Started Dec 31 01:04:52 PM PST 23
Finished Dec 31 01:04:54 PM PST 23
Peak memory 201844 kb
Host smart-21973b97-f5df-4ab1-93bf-e2393843b992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107376225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.107376225
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.110874697
Short name T270
Test name
Test status
Simulation time 52955744178 ps
CPU time 1092.89 seconds
Started Dec 31 01:04:56 PM PST 23
Finished Dec 31 01:23:10 PM PST 23
Peak memory 202160 kb
Host smart-d8a7bea3-d18c-46ce-843d-767c3bc9fc3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110874697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.
110874697
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.621439699
Short name T621
Test name
Test status
Simulation time 44252619088 ps
CPU time 138.05 seconds
Started Dec 31 01:04:58 PM PST 23
Finished Dec 31 01:07:17 PM PST 23
Peak memory 210308 kb
Host smart-6c11867c-fa3b-4ab1-a4d1-04de1fcae244
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621439699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esc
alation.621439699
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.2305151345
Short name T435
Test name
Test status
Simulation time 1397366399 ps
CPU time 30.28 seconds
Started Dec 31 01:04:55 PM PST 23
Finished Dec 31 01:05:27 PM PST 23
Peak memory 234844 kb
Host smart-641d74d2-2ba5-4953-aa64-a1eb9553c152
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305151345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.2305151345
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2957576149
Short name T823
Test name
Test status
Simulation time 3779130556 ps
CPU time 71.36 seconds
Started Dec 31 01:04:55 PM PST 23
Finished Dec 31 01:06:08 PM PST 23
Peak memory 211148 kb
Host smart-3c751a38-6bf7-4889-af0d-1400d71abd95
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957576149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.2957576149
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.1680551080
Short name T687
Test name
Test status
Simulation time 17913046037 ps
CPU time 266.81 seconds
Started Dec 31 01:05:01 PM PST 23
Finished Dec 31 01:09:29 PM PST 23
Peak memory 202128 kb
Host smart-82a74197-4ee7-4086-a045-80c99fce2c4a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680551080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.1680551080
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.4183449857
Short name T588
Test name
Test status
Simulation time 29278830075 ps
CPU time 991.46 seconds
Started Dec 31 01:04:56 PM PST 23
Finished Dec 31 01:21:29 PM PST 23
Peak memory 374856 kb
Host smart-b5266d98-525c-417b-8a7d-012a9d9fd676
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183449857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.4183449857
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.889770963
Short name T865
Test name
Test status
Simulation time 1473575081 ps
CPU time 13.54 seconds
Started Dec 31 01:04:58 PM PST 23
Finished Dec 31 01:05:13 PM PST 23
Peak memory 201992 kb
Host smart-a9fb1c2c-a48c-4c5b-bf72-c0ac5c321a41
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889770963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s
ram_ctrl_partial_access.889770963
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3593370996
Short name T671
Test name
Test status
Simulation time 20379280056 ps
CPU time 439.13 seconds
Started Dec 31 01:04:54 PM PST 23
Finished Dec 31 01:12:15 PM PST 23
Peak memory 202156 kb
Host smart-6fa76d42-e202-44e3-aa6d-9dc01e32dab1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593370996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.3593370996
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.495030774
Short name T681
Test name
Test status
Simulation time 1403653700 ps
CPU time 5.8 seconds
Started Dec 31 01:04:54 PM PST 23
Finished Dec 31 01:05:02 PM PST 23
Peak memory 202388 kb
Host smart-138dbeb2-5ddb-47b4-89d7-e1067aec792f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495030774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.495030774
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.3115576737
Short name T444
Test name
Test status
Simulation time 16651387387 ps
CPU time 404.92 seconds
Started Dec 31 01:04:52 PM PST 23
Finished Dec 31 01:11:38 PM PST 23
Peak memory 376928 kb
Host smart-38caf283-05bb-4a30-b50e-1d5ed549e819
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115576737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3115576737
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.4216941143
Short name T827
Test name
Test status
Simulation time 456104073 ps
CPU time 10.52 seconds
Started Dec 31 01:04:54 PM PST 23
Finished Dec 31 01:05:07 PM PST 23
Peak memory 219920 kb
Host smart-a5914c4f-f479-4ed8-9af9-2d5e179b1dab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216941143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.4216941143
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.3350964859
Short name T7
Test name
Test status
Simulation time 1179091278734 ps
CPU time 5078.93 seconds
Started Dec 31 01:04:47 PM PST 23
Finished Dec 31 02:29:29 PM PST 23
Peak memory 383180 kb
Host smart-48733c78-03bc-4380-876e-f9193843b41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350964859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.3350964859
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.245339946
Short name T783
Test name
Test status
Simulation time 1199579528 ps
CPU time 2041.59 seconds
Started Dec 31 01:04:53 PM PST 23
Finished Dec 31 01:38:56 PM PST 23
Peak memory 431800 kb
Host smart-646a6463-431e-4f59-a97f-7ff92e1311aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=245339946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.245339946
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2655369233
Short name T359
Test name
Test status
Simulation time 7492483510 ps
CPU time 251.16 seconds
Started Dec 31 01:05:14 PM PST 23
Finished Dec 31 01:09:26 PM PST 23
Peak memory 202116 kb
Host smart-f7618239-8811-4568-a3dc-c62f34587bbe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655369233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.2655369233
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.4271565423
Short name T859
Test name
Test status
Simulation time 2977474010 ps
CPU time 82.81 seconds
Started Dec 31 01:04:52 PM PST 23
Finished Dec 31 01:06:16 PM PST 23
Peak memory 316648 kb
Host smart-a228a279-f7ab-4c01-8d4c-02b9c41db7bf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271565423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.4271565423
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1412177269
Short name T501
Test name
Test status
Simulation time 14770680315 ps
CPU time 635.09 seconds
Started Dec 31 01:05:05 PM PST 23
Finished Dec 31 01:15:42 PM PST 23
Peak memory 372996 kb
Host smart-5ed0d106-212d-491f-a26c-8e711a26b486
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412177269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.1412177269
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.463210605
Short name T427
Test name
Test status
Simulation time 13366601 ps
CPU time 0.64 seconds
Started Dec 31 01:05:25 PM PST 23
Finished Dec 31 01:05:26 PM PST 23
Peak memory 201432 kb
Host smart-1011b1b5-ca36-4092-97b5-ef39f7bd0381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463210605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.463210605
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.1630761648
Short name T247
Test name
Test status
Simulation time 47077973094 ps
CPU time 743.99 seconds
Started Dec 31 01:05:04 PM PST 23
Finished Dec 31 01:17:29 PM PST 23
Peak memory 202208 kb
Host smart-8d7c82fa-c8a6-48ef-bebc-a032ce86f34b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630761648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.1630761648
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.4286044717
Short name T746
Test name
Test status
Simulation time 13944619102 ps
CPU time 152.66 seconds
Started Dec 31 01:05:29 PM PST 23
Finished Dec 31 01:08:03 PM PST 23
Peak memory 202204 kb
Host smart-fae7e08c-d08a-4186-a193-2566ce49721e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286044717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.4286044717
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.215286322
Short name T509
Test name
Test status
Simulation time 738536955 ps
CPU time 84.34 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:06:32 PM PST 23
Peak memory 321816 kb
Host smart-a2af9532-73c0-4a95-becb-b933cf2a2979
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215286322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.sram_ctrl_max_throughput.215286322
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1012932154
Short name T734
Test name
Test status
Simulation time 22619464008 ps
CPU time 149.22 seconds
Started Dec 31 01:05:25 PM PST 23
Finished Dec 31 01:07:55 PM PST 23
Peak memory 211040 kb
Host smart-e61dbfa3-45d2-4fa7-9758-1344a753c0ef
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012932154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.1012932154
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.2802835109
Short name T137
Test name
Test status
Simulation time 3943690547 ps
CPU time 242.21 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 202056 kb
Host smart-58156ee1-c432-4704-bbf9-7aca4f8bfc80
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802835109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.2802835109
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.297726748
Short name T140
Test name
Test status
Simulation time 14748482439 ps
CPU time 1024.57 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:22:12 PM PST 23
Peak memory 379076 kb
Host smart-84813b2f-95a7-4830-8f94-9647ecce9a30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297726748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multip
le_keys.297726748
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.3324929091
Short name T386
Test name
Test status
Simulation time 780482700 ps
CPU time 11.82 seconds
Started Dec 31 01:05:10 PM PST 23
Finished Dec 31 01:05:23 PM PST 23
Peak memory 202060 kb
Host smart-2d7bac8f-b92e-42f8-bc9a-9444c9cc6882
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324929091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.3324929091
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3486041028
Short name T439
Test name
Test status
Simulation time 45112248247 ps
CPU time 258.72 seconds
Started Dec 31 01:05:09 PM PST 23
Finished Dec 31 01:09:30 PM PST 23
Peak memory 202100 kb
Host smart-7cba5a56-b3ae-49d6-97dd-85198d886807
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486041028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.3486041028
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.1632326401
Short name T793
Test name
Test status
Simulation time 719900901 ps
CPU time 13.94 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:05:22 PM PST 23
Peak memory 202444 kb
Host smart-879de6e9-603a-4aea-b4d6-96a277a8318a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632326401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1632326401
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.403336501
Short name T434
Test name
Test status
Simulation time 6729345714 ps
CPU time 981.64 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:21:30 PM PST 23
Peak memory 376040 kb
Host smart-8505a40c-c0a2-4277-b40c-e12130725fa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403336501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.403336501
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.1086899563
Short name T282
Test name
Test status
Simulation time 3367727936 ps
CPU time 36.44 seconds
Started Dec 31 01:04:59 PM PST 23
Finished Dec 31 01:05:36 PM PST 23
Peak memory 202088 kb
Host smart-a50a4aa1-429e-4059-8e8c-55c2711c467a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086899563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1086899563
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3970481792
Short name T557
Test name
Test status
Simulation time 3007628488 ps
CPU time 3317.41 seconds
Started Dec 31 01:05:30 PM PST 23
Finished Dec 31 02:00:49 PM PST 23
Peak memory 422432 kb
Host smart-90df52f5-0065-4767-bebe-887535e6da63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3970481792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3970481792
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.93781670
Short name T915
Test name
Test status
Simulation time 5031428113 ps
CPU time 323.14 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:10:56 PM PST 23
Peak memory 202112 kb
Host smart-12ccf577-3ef4-4a32-b63e-e0f777b7727f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93781670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_stress_pipeline.93781670
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1160673942
Short name T611
Test name
Test status
Simulation time 3284583785 ps
CPU time 51.08 seconds
Started Dec 31 01:05:29 PM PST 23
Finished Dec 31 01:06:21 PM PST 23
Peak memory 278304 kb
Host smart-83840cdf-1c27-4306-a8c7-341e304c8649
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160673942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1160673942
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.4270480009
Short name T967
Test name
Test status
Simulation time 6115268020 ps
CPU time 726.26 seconds
Started Dec 31 01:05:28 PM PST 23
Finished Dec 31 01:17:35 PM PST 23
Peak memory 355464 kb
Host smart-0296e740-48d7-4219-9797-3755dbbbcc0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270480009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.4270480009
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.3938784278
Short name T262
Test name
Test status
Simulation time 40033917 ps
CPU time 0.63 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:05:09 PM PST 23
Peak memory 201860 kb
Host smart-29a4541e-de9a-4302-8457-2dd8e5922bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938784278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.3938784278
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.3015993934
Short name T732
Test name
Test status
Simulation time 96643938879 ps
CPU time 1613.21 seconds
Started Dec 31 01:05:04 PM PST 23
Finished Dec 31 01:31:59 PM PST 23
Peak memory 202080 kb
Host smart-839da063-8c36-4903-b4f3-87797a01ca76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015993934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.3015993934
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.3405011723
Short name T381
Test name
Test status
Simulation time 10546980430 ps
CPU time 553.29 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:14:46 PM PST 23
Peak memory 371852 kb
Host smart-bc2b0896-2117-4e8e-9a62-6974f19d8736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405011723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.3405011723
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.3810369272
Short name T863
Test name
Test status
Simulation time 66257961332 ps
CPU time 201.56 seconds
Started Dec 31 01:05:04 PM PST 23
Finished Dec 31 01:08:27 PM PST 23
Peak memory 210328 kb
Host smart-660dfe83-5abc-46c4-b8b6-277d4c1ce493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810369272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.3810369272
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.2836661654
Short name T357
Test name
Test status
Simulation time 1980055106 ps
CPU time 28.13 seconds
Started Dec 31 01:05:04 PM PST 23
Finished Dec 31 01:05:34 PM PST 23
Peak memory 217188 kb
Host smart-708bc2be-b452-4e1a-a80d-2bed6fc5b7b2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836661654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.2836661654
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1765527886
Short name T966
Test name
Test status
Simulation time 3959615382 ps
CPU time 78.44 seconds
Started Dec 31 01:05:27 PM PST 23
Finished Dec 31 01:06:46 PM PST 23
Peak memory 211080 kb
Host smart-32b76c30-9db1-4e46-aa69-7aa8ca267e42
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765527886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.1765527886
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.167193726
Short name T474
Test name
Test status
Simulation time 7602298000 ps
CPU time 118.83 seconds
Started Dec 31 01:05:08 PM PST 23
Finished Dec 31 01:07:08 PM PST 23
Peak memory 202176 kb
Host smart-8f17f098-5d1e-41ea-8b00-3d506664db6b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167193726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl
_mem_walk.167193726
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.3902248649
Short name T353
Test name
Test status
Simulation time 20451492092 ps
CPU time 1843.56 seconds
Started Dec 31 01:05:29 PM PST 23
Finished Dec 31 01:36:14 PM PST 23
Peak memory 381120 kb
Host smart-7ef667e7-a02d-4e42-9ae1-07ccf950cb15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902248649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.3902248649
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.2713011030
Short name T694
Test name
Test status
Simulation time 954823107 ps
CPU time 170.64 seconds
Started Dec 31 01:05:05 PM PST 23
Finished Dec 31 01:07:57 PM PST 23
Peak memory 374892 kb
Host smart-5fdf1426-8ef9-4059-8977-f06749c70afc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713011030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.2713011030
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2230547537
Short name T812
Test name
Test status
Simulation time 27798735295 ps
CPU time 380.73 seconds
Started Dec 31 01:05:08 PM PST 23
Finished Dec 31 01:11:30 PM PST 23
Peak memory 202148 kb
Host smart-283a70ec-33a4-4e1d-9446-59231338304e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230547537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.2230547537
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.1620071438
Short name T759
Test name
Test status
Simulation time 1352567557 ps
CPU time 13.73 seconds
Started Dec 31 01:05:05 PM PST 23
Finished Dec 31 01:05:21 PM PST 23
Peak memory 202220 kb
Host smart-322840e2-d085-4103-92b2-a8ac0aafcc73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620071438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1620071438
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.3350349993
Short name T764
Test name
Test status
Simulation time 31344899083 ps
CPU time 203.23 seconds
Started Dec 31 01:05:09 PM PST 23
Finished Dec 31 01:08:34 PM PST 23
Peak memory 369904 kb
Host smart-ec4477fe-0b4a-44aa-9e92-790717e8b9af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350349993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3350349993
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.40827714
Short name T800
Test name
Test status
Simulation time 698072353 ps
CPU time 35.6 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:06:08 PM PST 23
Peak memory 239136 kb
Host smart-2d15183e-689d-48ee-8c04-be3533ae2f3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40827714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.40827714
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.2876793490
Short name T879
Test name
Test status
Simulation time 321780712278 ps
CPU time 3016.65 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:55:24 PM PST 23
Peak memory 380020 kb
Host smart-83275765-059c-4fe3-9581-57f74dca52ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876793490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.2876793490
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2568386962
Short name T514
Test name
Test status
Simulation time 2879427261 ps
CPU time 4834.26 seconds
Started Dec 31 01:05:29 PM PST 23
Finished Dec 31 02:26:04 PM PST 23
Peak memory 712728 kb
Host smart-338d30a4-26d1-4219-a542-9cb52377c13d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2568386962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.2568386962
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.2658568810
Short name T836
Test name
Test status
Simulation time 4860275007 ps
CPU time 399.19 seconds
Started Dec 31 01:05:05 PM PST 23
Finished Dec 31 01:11:45 PM PST 23
Peak memory 201964 kb
Host smart-02a22c7d-ef29-4959-8666-f545fd8d1f52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658568810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.2658568810
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.462908943
Short name T730
Test name
Test status
Simulation time 767905579 ps
CPU time 99.78 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:06:48 PM PST 23
Peak memory 329916 kb
Host smart-0bb045fa-41c5-4b5d-a3b8-4cede3294a03
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462908943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.462908943
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3428166002
Short name T443
Test name
Test status
Simulation time 7990203999 ps
CPU time 203.26 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:08:32 PM PST 23
Peak memory 331912 kb
Host smart-c52b6aa3-f4e6-4d30-8309-1684c0db0fb3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428166002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.3428166002
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.3845306343
Short name T949
Test name
Test status
Simulation time 35199752 ps
CPU time 0.63 seconds
Started Dec 31 01:05:27 PM PST 23
Finished Dec 31 01:05:28 PM PST 23
Peak memory 201816 kb
Host smart-8d1963c0-4da1-4b57-a1b8-14cf38b0d2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845306343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.3845306343
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.4043366222
Short name T779
Test name
Test status
Simulation time 345406846004 ps
CPU time 2272.12 seconds
Started Dec 31 01:05:28 PM PST 23
Finished Dec 31 01:43:21 PM PST 23
Peak memory 202036 kb
Host smart-f0701104-bc59-4696-bb49-8f6e15bb99d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043366222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.4043366222
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.1797170336
Short name T799
Test name
Test status
Simulation time 13177850753 ps
CPU time 710.09 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:17:36 PM PST 23
Peak memory 362744 kb
Host smart-54852928-5496-4ed6-808f-1d5ff50cfd00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797170336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.1797170336
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.3359198427
Short name T6
Test name
Test status
Simulation time 44775805282 ps
CPU time 271.82 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:10:05 PM PST 23
Peak memory 202284 kb
Host smart-f9f50744-cd41-4eb1-82bd-3536db161f54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359198427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.3359198427
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.3827506917
Short name T664
Test name
Test status
Simulation time 797904825 ps
CPU time 44.24 seconds
Started Dec 31 01:05:33 PM PST 23
Finished Dec 31 01:06:19 PM PST 23
Peak memory 267544 kb
Host smart-20d327c1-b4a9-40c8-8233-5337ad410c0a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827506917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.3827506917
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.490534951
Short name T9
Test name
Test status
Simulation time 5148158953 ps
CPU time 153.99 seconds
Started Dec 31 01:05:29 PM PST 23
Finished Dec 31 01:08:03 PM PST 23
Peak memory 211200 kb
Host smart-6f085c81-3275-4479-8f17-fef7eab0f1c6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490534951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.sram_ctrl_mem_partial_access.490534951
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.1250506080
Short name T668
Test name
Test status
Simulation time 49191827833 ps
CPU time 285.45 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:09:54 PM PST 23
Peak memory 202112 kb
Host smart-1240f256-6410-436b-a90c-69a11de33a13
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250506080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.1250506080
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.2182262859
Short name T290
Test name
Test status
Simulation time 77431201454 ps
CPU time 932.05 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:21:04 PM PST 23
Peak memory 369812 kb
Host smart-1f077a27-976f-4d87-8cfd-13a8faa06350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182262859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.2182262859
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.1647858543
Short name T403
Test name
Test status
Simulation time 455285612 ps
CPU time 56.71 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:06:06 PM PST 23
Peak memory 293700 kb
Host smart-8685d376-f64d-42b2-b869-659ab0a5662d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647858543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.1647858543
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.80573566
Short name T30
Test name
Test status
Simulation time 694724399 ps
CPU time 5.68 seconds
Started Dec 31 01:05:03 PM PST 23
Finished Dec 31 01:05:10 PM PST 23
Peak memory 202428 kb
Host smart-307b9444-da90-4ae9-948c-bff0dae75ce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80573566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.80573566
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.1001666218
Short name T318
Test name
Test status
Simulation time 25017677205 ps
CPU time 1021.23 seconds
Started Dec 31 01:05:38 PM PST 23
Finished Dec 31 01:22:40 PM PST 23
Peak memory 372912 kb
Host smart-f7c131c6-2fde-4ead-9d5b-b755b2b70d50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001666218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1001666218
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.3820405723
Short name T494
Test name
Test status
Simulation time 405536238 ps
CPU time 14.6 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:05:22 PM PST 23
Peak memory 202064 kb
Host smart-d21e0e06-9983-49ef-9c92-18fb424e8ac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820405723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3820405723
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.1731277902
Short name T960
Test name
Test status
Simulation time 17502779536 ps
CPU time 1967.42 seconds
Started Dec 31 01:05:30 PM PST 23
Finished Dec 31 01:38:19 PM PST 23
Peak memory 381128 kb
Host smart-5dda44d9-7c37-4f3a-9e0d-e95850022bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731277902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.1731277902
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4177224918
Short name T231
Test name
Test status
Simulation time 1388225501 ps
CPU time 4008.23 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 02:12:21 PM PST 23
Peak memory 725968 kb
Host smart-93206499-2278-4d91-b7b2-30b0ce937772
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4177224918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.4177224918
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.4000281805
Short name T940
Test name
Test status
Simulation time 3499530115 ps
CPU time 144.37 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:07:33 PM PST 23
Peak memory 202084 kb
Host smart-0888f25d-184a-43ca-b08d-526604171228
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000281805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.4000281805
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2874650838
Short name T785
Test name
Test status
Simulation time 5654497623 ps
CPU time 29.23 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:06:03 PM PST 23
Peak memory 218504 kb
Host smart-71d1bec9-e1ef-4d43-8db9-005a088e6798
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874650838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.2874650838
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1713657898
Short name T240
Test name
Test status
Simulation time 22334485384 ps
CPU time 762.83 seconds
Started Dec 31 01:05:05 PM PST 23
Finished Dec 31 01:17:50 PM PST 23
Peak memory 372940 kb
Host smart-a6d67b5a-323d-41f0-8396-8e7382e46225
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713657898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.1713657898
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.1647623587
Short name T512
Test name
Test status
Simulation time 42305205 ps
CPU time 0.64 seconds
Started Dec 31 01:05:30 PM PST 23
Finished Dec 31 01:05:32 PM PST 23
Peak memory 201392 kb
Host smart-18102a35-7b7e-494c-ac93-5864cd9015aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647623587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.1647623587
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.4060467941
Short name T534
Test name
Test status
Simulation time 158131446999 ps
CPU time 2447.48 seconds
Started Dec 31 01:05:08 PM PST 23
Finished Dec 31 01:45:57 PM PST 23
Peak memory 202024 kb
Host smart-125e6f44-5cc7-4058-8bd4-eaf1f760929a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060467941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.4060467941
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.733400138
Short name T538
Test name
Test status
Simulation time 5695630804 ps
CPU time 298.08 seconds
Started Dec 31 01:05:04 PM PST 23
Finished Dec 31 01:10:03 PM PST 23
Peak memory 344196 kb
Host smart-6ae7bbcf-9eb0-418e-a1e9-727428bf380e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733400138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executabl
e.733400138
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.3945862077
Short name T519
Test name
Test status
Simulation time 776060714 ps
CPU time 128.45 seconds
Started Dec 31 01:05:11 PM PST 23
Finished Dec 31 01:07:20 PM PST 23
Peak memory 351416 kb
Host smart-4cc44a45-1eb0-4b50-a377-aa2c64e4c1bd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945862077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.3945862077
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.623859983
Short name T314
Test name
Test status
Simulation time 5045615218 ps
CPU time 159.57 seconds
Started Dec 31 01:05:12 PM PST 23
Finished Dec 31 01:07:52 PM PST 23
Peak memory 211136 kb
Host smart-11c04896-1cd0-47a3-ace9-9255d1e2e7d1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623859983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_mem_partial_access.623859983
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.3031553319
Short name T559
Test name
Test status
Simulation time 7889391251 ps
CPU time 126.17 seconds
Started Dec 31 01:05:11 PM PST 23
Finished Dec 31 01:07:18 PM PST 23
Peak memory 202100 kb
Host smart-1f64b94a-947c-44b3-8976-959ef5898655
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031553319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.3031553319
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.4171377026
Short name T274
Test name
Test status
Simulation time 93494673038 ps
CPU time 975.19 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:21:24 PM PST 23
Peak memory 381156 kb
Host smart-0625afb7-e753-42cb-a47f-a961308d1d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171377026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.4171377026
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.3883598921
Short name T914
Test name
Test status
Simulation time 1545871480 ps
CPU time 26.82 seconds
Started Dec 31 01:05:09 PM PST 23
Finished Dec 31 01:05:38 PM PST 23
Peak memory 202056 kb
Host smart-726200fc-4fc7-4959-932f-b9e936917ca3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883598921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.3883598921
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3060319359
Short name T869
Test name
Test status
Simulation time 9596559742 ps
CPU time 197.07 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:08:50 PM PST 23
Peak memory 210284 kb
Host smart-18a7ab41-ff2d-4169-9ce1-e1840da54ece
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060319359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.3060319359
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.3170490346
Short name T550
Test name
Test status
Simulation time 361111221 ps
CPU time 6.47 seconds
Started Dec 31 01:05:10 PM PST 23
Finished Dec 31 01:05:18 PM PST 23
Peak memory 202380 kb
Host smart-c1efd24e-09e8-4c83-8ea7-2a8523877bd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170490346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3170490346
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.2023337552
Short name T795
Test name
Test status
Simulation time 12944816898 ps
CPU time 733.47 seconds
Started Dec 31 01:05:27 PM PST 23
Finished Dec 31 01:17:41 PM PST 23
Peak memory 379120 kb
Host smart-5cd0f275-a65e-4b6d-8ee6-974c0c663cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023337552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2023337552
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.1972124904
Short name T901
Test name
Test status
Simulation time 754884239 ps
CPU time 27.78 seconds
Started Dec 31 01:05:30 PM PST 23
Finished Dec 31 01:05:59 PM PST 23
Peak memory 202008 kb
Host smart-16ed36b4-c4f0-4ee8-9acb-5f90bf72700b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972124904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1972124904
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.3720156750
Short name T968
Test name
Test status
Simulation time 597027709678 ps
CPU time 3071.82 seconds
Started Dec 31 01:05:05 PM PST 23
Finished Dec 31 01:56:19 PM PST 23
Peak memory 377916 kb
Host smart-c54e22c1-a63f-4623-83e4-2b0e62585a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720156750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.3720156750
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1901554199
Short name T679
Test name
Test status
Simulation time 1907261424 ps
CPU time 1743.28 seconds
Started Dec 31 01:05:01 PM PST 23
Finished Dec 31 01:34:06 PM PST 23
Peak memory 629024 kb
Host smart-9417cf5d-ee23-4b70-b893-72cb1af55768
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1901554199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1901554199
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3093714297
Short name T110
Test name
Test status
Simulation time 3108002682 ps
CPU time 239.14 seconds
Started Dec 31 01:05:03 PM PST 23
Finished Dec 31 01:09:03 PM PST 23
Peak memory 202372 kb
Host smart-31b217c4-9ce6-42c5-b9b6-cb20d7c1aa02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093714297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.3093714297
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.82294278
Short name T933
Test name
Test status
Simulation time 4917630696 ps
CPU time 63.7 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:06:12 PM PST 23
Peak memory 303316 kb
Host smart-fdc5c09c-de39-41f5-b61f-e1331d81c590
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82294278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.sram_ctrl_throughput_w_partial_write.82294278
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2301359695
Short name T856
Test name
Test status
Simulation time 5085708331 ps
CPU time 621.35 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:15:30 PM PST 23
Peak memory 378100 kb
Host smart-5c80eda7-8f61-4a0f-8420-e13957898ddf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301359695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.2301359695
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.1898653993
Short name T689
Test name
Test status
Simulation time 25444069 ps
CPU time 0.67 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:05:09 PM PST 23
Peak memory 201708 kb
Host smart-f2933141-2577-49b4-a373-4f726372c6be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898653993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.1898653993
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.3593361024
Short name T325
Test name
Test status
Simulation time 48123463802 ps
CPU time 1047.25 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:22:37 PM PST 23
Peak memory 202188 kb
Host smart-ac16113d-9276-4cd0-9c3a-37b3f7cce5f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593361024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.3593361024
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.2535022422
Short name T843
Test name
Test status
Simulation time 2332767141 ps
CPU time 32.26 seconds
Started Dec 31 01:05:03 PM PST 23
Finished Dec 31 01:05:37 PM PST 23
Peak memory 202104 kb
Host smart-1340b3dc-d01e-4718-bc55-937265b30839
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535022422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.2535022422
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.965737893
Short name T748
Test name
Test status
Simulation time 717424124 ps
CPU time 63.04 seconds
Started Dec 31 01:05:08 PM PST 23
Finished Dec 31 01:06:13 PM PST 23
Peak memory 283936 kb
Host smart-a7fe0edd-2146-4b4c-9146-fc4c24baeb57
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965737893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.sram_ctrl_max_throughput.965737893
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.2300050253
Short name T419
Test name
Test status
Simulation time 10368914723 ps
CPU time 158.82 seconds
Started Dec 31 01:05:09 PM PST 23
Finished Dec 31 01:07:50 PM PST 23
Peak memory 214356 kb
Host smart-dd83981a-7b82-4353-ac6c-264e76deb9cc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300050253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.2300050253
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.807504136
Short name T616
Test name
Test status
Simulation time 4114909854 ps
CPU time 135.23 seconds
Started Dec 31 01:05:30 PM PST 23
Finished Dec 31 01:07:47 PM PST 23
Peak memory 202144 kb
Host smart-414066b4-16fd-472f-8868-ddc63e92c319
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807504136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl
_mem_walk.807504136
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.1158079523
Short name T813
Test name
Test status
Simulation time 14799399232 ps
CPU time 1310.95 seconds
Started Dec 31 01:05:03 PM PST 23
Finished Dec 31 01:26:56 PM PST 23
Peak memory 379092 kb
Host smart-d0eb6d91-751a-49a4-9670-6d6649c20107
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158079523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.1158079523
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.3925323501
Short name T136
Test name
Test status
Simulation time 2999539550 ps
CPU time 22.79 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:05:56 PM PST 23
Peak memory 244032 kb
Host smart-c708e3b9-df21-4d24-9036-3c96f64e87f2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925323501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.3925323501
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3231616476
Short name T884
Test name
Test status
Simulation time 25777296282 ps
CPU time 277.25 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:09:46 PM PST 23
Peak memory 202128 kb
Host smart-a74d01a3-c412-4543-abc8-e88f841950ae
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231616476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.3231616476
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.640729002
Short name T628
Test name
Test status
Simulation time 1407716224 ps
CPU time 6.6 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:05:14 PM PST 23
Peak memory 202384 kb
Host smart-e4e1cb63-1abc-4bf6-b04d-e48209a2d8b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640729002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.640729002
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.967841612
Short name T976
Test name
Test status
Simulation time 5001990854 ps
CPU time 327.1 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 372944 kb
Host smart-f5d7d70a-cf21-4c23-bba7-5a9c5307caa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967841612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.967841612
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.3193496181
Short name T229
Test name
Test status
Simulation time 8516554535 ps
CPU time 111.68 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:06:59 PM PST 23
Peak memory 375932 kb
Host smart-925e16c6-fec7-4b70-ab59-c9b1358e2d98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193496181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3193496181
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1070193829
Short name T374
Test name
Test status
Simulation time 439838440 ps
CPU time 4610.66 seconds
Started Dec 31 01:05:09 PM PST 23
Finished Dec 31 02:22:02 PM PST 23
Peak memory 434908 kb
Host smart-7c2170e0-122e-4638-ae4f-b1df59ab807a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1070193829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1070193829
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1472638472
Short name T917
Test name
Test status
Simulation time 10234424840 ps
CPU time 389.01 seconds
Started Dec 31 01:05:15 PM PST 23
Finished Dec 31 01:11:45 PM PST 23
Peak memory 202124 kb
Host smart-3af0b5b1-2885-486f-8b41-eb17f52f86b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472638472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.1472638472
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.376301187
Short name T816
Test name
Test status
Simulation time 767589248 ps
CPU time 74.6 seconds
Started Dec 31 01:05:06 PM PST 23
Finished Dec 31 01:06:22 PM PST 23
Peak memory 311492 kb
Host smart-334afd10-6768-4185-81d6-70b8da221bc0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376301187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_throughput_w_partial_write.376301187
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.255222714
Short name T460
Test name
Test status
Simulation time 33800072034 ps
CPU time 1330.11 seconds
Started Dec 31 01:03:57 PM PST 23
Finished Dec 31 01:26:09 PM PST 23
Peak memory 380152 kb
Host smart-ec5729b8-eff4-4357-9175-a1776520eb7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255222714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_access_during_key_req.255222714
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.221509225
Short name T965
Test name
Test status
Simulation time 27812464 ps
CPU time 0.64 seconds
Started Dec 31 01:04:17 PM PST 23
Finished Dec 31 01:04:19 PM PST 23
Peak memory 201336 kb
Host smart-c70f4215-2b6f-488c-9f7a-420c478fbe58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221509225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.221509225
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.384017241
Short name T830
Test name
Test status
Simulation time 564342250595 ps
CPU time 2143.59 seconds
Started Dec 31 01:03:39 PM PST 23
Finished Dec 31 01:39:27 PM PST 23
Peak memory 202188 kb
Host smart-6b6e4a81-5a50-4a2f-a704-99b5dc3ad3a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384017241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.384017241
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.1993383835
Short name T736
Test name
Test status
Simulation time 47467862966 ps
CPU time 165.85 seconds
Started Dec 31 01:04:00 PM PST 23
Finished Dec 31 01:06:47 PM PST 23
Peak memory 210436 kb
Host smart-012bba9d-65af-477b-a17d-a17c9dd9d886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993383835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.1993383835
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.1713603818
Short name T312
Test name
Test status
Simulation time 794960804 ps
CPU time 83.65 seconds
Started Dec 31 01:04:04 PM PST 23
Finished Dec 31 01:05:29 PM PST 23
Peak memory 322884 kb
Host smart-570e2818-a011-470a-864d-5f6acb094802
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713603818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.1713603818
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.197826165
Short name T82
Test name
Test status
Simulation time 2584997159 ps
CPU time 72.84 seconds
Started Dec 31 01:03:55 PM PST 23
Finished Dec 31 01:05:10 PM PST 23
Peak memory 211024 kb
Host smart-1a822b58-e7cf-416c-b505-8c6821be8fb7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197826165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
sram_ctrl_mem_partial_access.197826165
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.3398923337
Short name T329
Test name
Test status
Simulation time 13778233327 ps
CPU time 281.78 seconds
Started Dec 31 01:04:14 PM PST 23
Finished Dec 31 01:08:57 PM PST 23
Peak memory 202284 kb
Host smart-3ae061dc-db90-488f-bcec-eb23ff1b6bb0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398923337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.3398923337
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.2044512570
Short name T684
Test name
Test status
Simulation time 13988821553 ps
CPU time 321.37 seconds
Started Dec 31 01:03:52 PM PST 23
Finished Dec 31 01:09:14 PM PST 23
Peak memory 368812 kb
Host smart-85d7b186-70e2-4510-8726-3e2a0d50ef34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044512570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.2044512570
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.2537365167
Short name T271
Test name
Test status
Simulation time 741030127 ps
CPU time 30.16 seconds
Started Dec 31 01:03:50 PM PST 23
Finished Dec 31 01:04:21 PM PST 23
Peak memory 226472 kb
Host smart-344d3d72-69ce-464f-b2d3-e5c7d8a33258
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537365167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.2537365167
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3600766336
Short name T472
Test name
Test status
Simulation time 4623552155 ps
CPU time 278.06 seconds
Started Dec 31 01:04:12 PM PST 23
Finished Dec 31 01:08:51 PM PST 23
Peak memory 202088 kb
Host smart-f90ada1a-dd09-4e3d-907e-298e72eed1e9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600766336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.3600766336
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.305839289
Short name T31
Test name
Test status
Simulation time 2595512598 ps
CPU time 6.38 seconds
Started Dec 31 01:04:09 PM PST 23
Finished Dec 31 01:04:17 PM PST 23
Peak memory 202476 kb
Host smart-8ce2cccc-d677-4158-9844-b87ef9d58219
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305839289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.305839289
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.823406606
Short name T578
Test name
Test status
Simulation time 679323788 ps
CPU time 32.46 seconds
Started Dec 31 01:03:53 PM PST 23
Finished Dec 31 01:04:26 PM PST 23
Peak memory 210260 kb
Host smart-584681e7-0e5b-4bb6-85e2-da9073da1cbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823406606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.823406606
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.2624728443
Short name T34
Test name
Test status
Simulation time 151961498 ps
CPU time 2 seconds
Started Dec 31 01:03:56 PM PST 23
Finished Dec 31 01:04:00 PM PST 23
Peak memory 231936 kb
Host smart-f493e0a5-ae46-4780-ae6d-3d2a62b7a93f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624728443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.2624728443
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.4220007099
Short name T719
Test name
Test status
Simulation time 2504057177 ps
CPU time 22.5 seconds
Started Dec 31 01:03:48 PM PST 23
Finished Dec 31 01:04:12 PM PST 23
Peak memory 202112 kb
Host smart-20b58735-5213-47c6-921a-9797e92ace1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220007099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.4220007099
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3451018368
Short name T939
Test name
Test status
Simulation time 1095067334 ps
CPU time 1989.17 seconds
Started Dec 31 01:04:07 PM PST 23
Finished Dec 31 01:37:17 PM PST 23
Peak memory 416684 kb
Host smart-3ec575ca-2aef-4ac1-8352-6a019f942dff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3451018368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3451018368
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1731656714
Short name T763
Test name
Test status
Simulation time 6803962003 ps
CPU time 267.83 seconds
Started Dec 31 01:04:07 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 202144 kb
Host smart-32cc9ca9-dfeb-4711-a779-a8e5ceac0b52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731656714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.1731656714
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3104218118
Short name T640
Test name
Test status
Simulation time 1040008824 ps
CPU time 54.84 seconds
Started Dec 31 01:03:41 PM PST 23
Finished Dec 31 01:04:40 PM PST 23
Peak memory 286004 kb
Host smart-97dc6008-18f2-411d-bfb7-248d63af3352
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104218118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.3104218118
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.4257183516
Short name T522
Test name
Test status
Simulation time 18478094094 ps
CPU time 1383.67 seconds
Started Dec 31 01:05:25 PM PST 23
Finished Dec 31 01:28:30 PM PST 23
Peak memory 380080 kb
Host smart-f43818eb-f80b-461f-b40e-d64108856893
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257183516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.4257183516
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.1707058110
Short name T635
Test name
Test status
Simulation time 12362779 ps
CPU time 0.62 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:05:34 PM PST 23
Peak memory 201444 kb
Host smart-15df6a68-9adb-4131-80d5-0b89686e77fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707058110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.1707058110
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.3402728776
Short name T667
Test name
Test status
Simulation time 66760316051 ps
CPU time 1308.51 seconds
Started Dec 31 01:05:03 PM PST 23
Finished Dec 31 01:26:53 PM PST 23
Peak memory 202128 kb
Host smart-dba2cf6c-92e0-4304-aee2-41bd0ba7146b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402728776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.3402728776
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.526128540
Short name T475
Test name
Test status
Simulation time 54882305143 ps
CPU time 228.07 seconds
Started Dec 31 01:05:02 PM PST 23
Finished Dec 31 01:08:52 PM PST 23
Peak memory 214264 kb
Host smart-53d04f9c-8791-4c8d-b300-d16f8bb36b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526128540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_esc
alation.526128540
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.3432559180
Short name T265
Test name
Test status
Simulation time 3035542533 ps
CPU time 145.63 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:07:35 PM PST 23
Peak memory 358604 kb
Host smart-d067a61a-a5e8-46d6-aa1c-4678239d400d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432559180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.3432559180
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2424076251
Short name T523
Test name
Test status
Simulation time 3175333487 ps
CPU time 131.8 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:07:44 PM PST 23
Peak memory 211228 kb
Host smart-5360455d-b43a-4415-82a5-ad8c60901307
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424076251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.2424076251
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.1810583323
Short name T969
Test name
Test status
Simulation time 21753199588 ps
CPU time 310.23 seconds
Started Dec 31 01:05:03 PM PST 23
Finished Dec 31 01:10:15 PM PST 23
Peak memory 202136 kb
Host smart-740d65c5-998a-4471-808c-41ad64ff2d14
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810583323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.1810583323
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.2271842047
Short name T498
Test name
Test status
Simulation time 45486308024 ps
CPU time 2034.18 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:39:26 PM PST 23
Peak memory 380072 kb
Host smart-64f5020e-3e45-46e5-9dde-de47d95d89d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271842047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.2271842047
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.1154807876
Short name T445
Test name
Test status
Simulation time 3669112341 ps
CPU time 22.76 seconds
Started Dec 31 01:05:03 PM PST 23
Finished Dec 31 01:05:27 PM PST 23
Peak memory 244008 kb
Host smart-8d3e79ac-2734-420e-8194-628d71cb7f25
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154807876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.1154807876
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2910372063
Short name T380
Test name
Test status
Simulation time 64669623389 ps
CPU time 388.97 seconds
Started Dec 31 01:05:08 PM PST 23
Finished Dec 31 01:11:39 PM PST 23
Peak memory 202192 kb
Host smart-24278180-1ed1-44da-aede-616d49e915a4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910372063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.2910372063
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.469643537
Short name T972
Test name
Test status
Simulation time 361538722 ps
CPU time 13.26 seconds
Started Dec 31 01:05:29 PM PST 23
Finished Dec 31 01:05:44 PM PST 23
Peak memory 202428 kb
Host smart-17793fca-19d3-41b7-9b0f-c091b837c30c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469643537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.469643537
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.4111841495
Short name T433
Test name
Test status
Simulation time 15456906035 ps
CPU time 1186.22 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:25:19 PM PST 23
Peak memory 379048 kb
Host smart-4018a9df-90ac-45dd-9739-1c6025bbcd9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111841495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.4111841495
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.2746479351
Short name T483
Test name
Test status
Simulation time 2249235190 ps
CPU time 115.76 seconds
Started Dec 31 01:05:29 PM PST 23
Finished Dec 31 01:07:26 PM PST 23
Peak memory 357512 kb
Host smart-5f7578a5-0f03-4124-aea7-d8b273e0d691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746479351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2746479351
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.3278356254
Short name T580
Test name
Test status
Simulation time 191783048013 ps
CPU time 2410.27 seconds
Started Dec 31 01:05:05 PM PST 23
Finished Dec 31 01:45:17 PM PST 23
Peak memory 378996 kb
Host smart-8a1cdf98-3f9b-41ee-982f-a8144a8e7fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278356254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.sram_ctrl_stress_all.3278356254
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3910540943
Short name T235
Test name
Test status
Simulation time 2645473590 ps
CPU time 4053.55 seconds
Started Dec 31 01:05:05 PM PST 23
Finished Dec 31 02:12:41 PM PST 23
Peak memory 715272 kb
Host smart-aaf64860-476b-4a73-b439-a1b2042512c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3910540943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3910540943
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2074512022
Short name T42
Test name
Test status
Simulation time 22317301305 ps
CPU time 465.35 seconds
Started Dec 31 01:05:09 PM PST 23
Finished Dec 31 01:12:56 PM PST 23
Peak memory 202160 kb
Host smart-05f7f1ba-3197-411c-a3db-f33cc928e32c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074512022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.2074512022
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.769727990
Short name T488
Test name
Test status
Simulation time 1575120997 ps
CPU time 84.62 seconds
Started Dec 31 01:05:05 PM PST 23
Finished Dec 31 01:06:31 PM PST 23
Peak memory 322752 kb
Host smart-e9303eb8-25d7-47db-b596-bdf003e323d8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769727990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_throughput_w_partial_write.769727990
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.855507925
Short name T468
Test name
Test status
Simulation time 65974556455 ps
CPU time 1184.34 seconds
Started Dec 31 01:05:33 PM PST 23
Finished Dec 31 01:25:19 PM PST 23
Peak memory 379536 kb
Host smart-a6bf3f88-0330-486a-958b-3f099f4a8ee2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855507925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.sram_ctrl_access_during_key_req.855507925
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.2523105420
Short name T608
Test name
Test status
Simulation time 45447975 ps
CPU time 0.65 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:05:34 PM PST 23
Peak memory 201428 kb
Host smart-e9d00b19-7bd4-46a4-82b5-5aa3fa19e93a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523105420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.2523105420
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.3227841981
Short name T299
Test name
Test status
Simulation time 16417328870 ps
CPU time 1090.06 seconds
Started Dec 31 01:05:09 PM PST 23
Finished Dec 31 01:23:21 PM PST 23
Peak memory 202064 kb
Host smart-4c9dad73-2ec9-4976-819b-e452aa59db04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227841981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.3227841981
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.3882025146
Short name T595
Test name
Test status
Simulation time 11498868048 ps
CPU time 673.04 seconds
Started Dec 31 01:05:07 PM PST 23
Finished Dec 31 01:16:22 PM PST 23
Peak memory 360600 kb
Host smart-4f0f1dea-05c3-4da6-888e-ca3b0e07198b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882025146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.3882025146
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.2546177096
Short name T409
Test name
Test status
Simulation time 39761246969 ps
CPU time 120.04 seconds
Started Dec 31 01:05:30 PM PST 23
Finished Dec 31 01:07:32 PM PST 23
Peak memory 213912 kb
Host smart-157f123e-9126-4979-8b5b-2d253c4469bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546177096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.2546177096
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.1398963447
Short name T533
Test name
Test status
Simulation time 778231302 ps
CPU time 163.7 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:08:18 PM PST 23
Peak memory 367672 kb
Host smart-b9fc0d4a-65d3-4a58-85e6-eb8656bfefe1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398963447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.1398963447
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1173578586
Short name T430
Test name
Test status
Simulation time 4407728080 ps
CPU time 153.11 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:08:06 PM PST 23
Peak memory 218496 kb
Host smart-9f8999bf-7ad1-488c-a99d-7b9311df3986
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173578586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.1173578586
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.2105427602
Short name T898
Test name
Test status
Simulation time 82655893541 ps
CPU time 334.36 seconds
Started Dec 31 01:05:08 PM PST 23
Finished Dec 31 01:10:44 PM PST 23
Peak memory 202112 kb
Host smart-7a111811-0cf4-46f2-9c62-3f7012c5081e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105427602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.2105427602
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.384810884
Short name T385
Test name
Test status
Simulation time 7025530567 ps
CPU time 539.27 seconds
Started Dec 31 01:05:09 PM PST 23
Finished Dec 31 01:14:10 PM PST 23
Peak memory 366668 kb
Host smart-11f20626-3185-4928-ba2b-c34c49808d02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384810884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip
le_keys.384810884
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.11901568
Short name T442
Test name
Test status
Simulation time 10064150200 ps
CPU time 20.08 seconds
Started Dec 31 01:05:10 PM PST 23
Finished Dec 31 01:05:31 PM PST 23
Peak memory 202104 kb
Host smart-3611d391-ea4d-4d2a-9571-685d7e20deff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11901568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sr
am_ctrl_partial_access.11901568
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2924116031
Short name T253
Test name
Test status
Simulation time 19094222738 ps
CPU time 404.55 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:12:18 PM PST 23
Peak memory 202052 kb
Host smart-28ed7e31-7c12-4e19-97a5-a046476b2c33
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924116031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.2924116031
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.3091572022
Short name T867
Test name
Test status
Simulation time 347020244 ps
CPU time 5.48 seconds
Started Dec 31 01:05:09 PM PST 23
Finished Dec 31 01:05:16 PM PST 23
Peak memory 202364 kb
Host smart-169cc566-00e2-4c61-ad67-6ba7c8ef7aee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091572022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3091572022
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.1808739714
Short name T256
Test name
Test status
Simulation time 17784951368 ps
CPU time 546.08 seconds
Started Dec 31 01:05:08 PM PST 23
Finished Dec 31 01:14:16 PM PST 23
Peak memory 369904 kb
Host smart-5154ac34-b1cd-4615-beb8-a5834ee3bb12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808739714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.1808739714
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.3060458061
Short name T932
Test name
Test status
Simulation time 817819836 ps
CPU time 36.96 seconds
Started Dec 31 01:05:04 PM PST 23
Finished Dec 31 01:05:43 PM PST 23
Peak memory 202104 kb
Host smart-7b445d7b-0cd5-4808-a4b0-5cb3b64abd8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060458061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3060458061
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.156660631
Short name T316
Test name
Test status
Simulation time 2458195687 ps
CPU time 2126.34 seconds
Started Dec 31 01:05:08 PM PST 23
Finished Dec 31 01:40:36 PM PST 23
Peak memory 518260 kb
Host smart-f8c5e3dc-3ae4-4eb7-8846-82a772b8de60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=156660631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.156660631
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1112814366
Short name T317
Test name
Test status
Simulation time 11510387061 ps
CPU time 401.96 seconds
Started Dec 31 01:05:30 PM PST 23
Finished Dec 31 01:12:13 PM PST 23
Peak memory 202100 kb
Host smart-a7c17686-cabb-4c3f-a72d-070709fff73b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112814366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.1112814366
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.200725699
Short name T8
Test name
Test status
Simulation time 1468821606 ps
CPU time 43.32 seconds
Started Dec 31 01:05:13 PM PST 23
Finished Dec 31 01:05:57 PM PST 23
Peak memory 258044 kb
Host smart-0add9de0-95a3-4507-81a7-f405bf6a1e3e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200725699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.200725699
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3828303930
Short name T724
Test name
Test status
Simulation time 5006145426 ps
CPU time 536.57 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:14:39 PM PST 23
Peak memory 362012 kb
Host smart-79a22abe-eab9-4061-add0-eed073ed0dcb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828303930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.3828303930
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.285217299
Short name T39
Test name
Test status
Simulation time 100363106 ps
CPU time 0.65 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:05:43 PM PST 23
Peak memory 201872 kb
Host smart-9c2665ee-0a39-41ab-9725-196db7db819d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285217299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.285217299
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.50310491
Short name T935
Test name
Test status
Simulation time 217732204421 ps
CPU time 882.19 seconds
Started Dec 31 01:05:30 PM PST 23
Finished Dec 31 01:20:14 PM PST 23
Peak memory 202124 kb
Host smart-1b27e0da-22c7-4a8f-bbd2-ce3cd97a28c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50310491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.50310491
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.289196547
Short name T378
Test name
Test status
Simulation time 3656213885 ps
CPU time 46.01 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:06:19 PM PST 23
Peak memory 210324 kb
Host smart-e8af117d-9039-4f1f-8073-efc7727615e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289196547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_esc
alation.289196547
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.1441150375
Short name T364
Test name
Test status
Simulation time 1176015737 ps
CPU time 117.05 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:07:30 PM PST 23
Peak memory 340128 kb
Host smart-62f98264-9b9b-4fc1-8106-9ae7a9e6e736
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441150375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.1441150375
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3600699664
Short name T415
Test name
Test status
Simulation time 1621367269 ps
CPU time 133.93 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:07:57 PM PST 23
Peak memory 211052 kb
Host smart-ab445c6f-7116-453e-bd59-e2dfa0af70dc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600699664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.3600699664
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.356183264
Short name T852
Test name
Test status
Simulation time 28095171154 ps
CPU time 309.35 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:10:43 PM PST 23
Peak memory 202152 kb
Host smart-96b39c82-df2a-4199-a364-fc9a246d881b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356183264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl
_mem_walk.356183264
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.1600024873
Short name T924
Test name
Test status
Simulation time 37748549477 ps
CPU time 1297.15 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:27:10 PM PST 23
Peak memory 380036 kb
Host smart-e8b0de53-5467-410f-ada8-6fd2f1c126e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600024873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.1600024873
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.2656149272
Short name T219
Test name
Test status
Simulation time 1605869809 ps
CPU time 26.84 seconds
Started Dec 31 01:05:33 PM PST 23
Finished Dec 31 01:06:01 PM PST 23
Peak memory 202080 kb
Host smart-32c6a565-2d65-408e-86f7-903ad88e0570
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656149272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.2656149272
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1934619835
Short name T860
Test name
Test status
Simulation time 62632946561 ps
CPU time 404.67 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:12:18 PM PST 23
Peak memory 202172 kb
Host smart-5f66553e-4ebf-4b2f-b3aa-180f749ebad9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934619835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.1934619835
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.2235538519
Short name T599
Test name
Test status
Simulation time 356860147 ps
CPU time 13.87 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:05:59 PM PST 23
Peak memory 202376 kb
Host smart-eb1060c7-0db2-4165-ab35-22f26db0e8f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235538519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2235538519
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.508542335
Short name T920
Test name
Test status
Simulation time 17072351330 ps
CPU time 751.37 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:18:14 PM PST 23
Peak memory 367004 kb
Host smart-eef29b3e-0452-4f6e-ba8b-0f443af629fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508542335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.508542335
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.987121202
Short name T845
Test name
Test status
Simulation time 5415286074 ps
CPU time 21.91 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:05:56 PM PST 23
Peak memory 202104 kb
Host smart-edaa5427-0499-46d4-a6cd-25824f68f16e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987121202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.987121202
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.2845123873
Short name T537
Test name
Test status
Simulation time 71815728901 ps
CPU time 3206.12 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:59:11 PM PST 23
Peak memory 378944 kb
Host smart-c064b315-f67b-469d-b975-852c882e454a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845123873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.sram_ctrl_stress_all.2845123873
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2265506046
Short name T597
Test name
Test status
Simulation time 828103917 ps
CPU time 1710.09 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:34:04 PM PST 23
Peak memory 652928 kb
Host smart-ab200ce2-2963-430d-b2bf-686dfd9fd156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2265506046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.2265506046
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3268088603
Short name T536
Test name
Test status
Simulation time 6449462470 ps
CPU time 282.2 seconds
Started Dec 31 01:05:09 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 202108 kb
Host smart-f1e5a73f-eaff-410c-b85a-0d4b3e9c96e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268088603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.3268088603
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.892614590
Short name T437
Test name
Test status
Simulation time 785047101 ps
CPU time 181.03 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:08:34 PM PST 23
Peak memory 365752 kb
Host smart-55c00dea-f9b6-406a-bf13-097970feb8f1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892614590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_throughput_w_partial_write.892614590
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.5756475
Short name T332
Test name
Test status
Simulation time 37761276037 ps
CPU time 1311.2 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:27:38 PM PST 23
Peak memory 376968 kb
Host smart-cdbcd7d1-73a7-4964-a9ab-50aabf469b54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5756475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.sram_ctrl_access_during_key_req.5756475
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.4144911199
Short name T701
Test name
Test status
Simulation time 18339120 ps
CPU time 0.62 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:05:43 PM PST 23
Peak memory 201872 kb
Host smart-baf5a606-a5dc-491f-9fac-686ae749173c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144911199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.4144911199
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.3227649222
Short name T224
Test name
Test status
Simulation time 96294046227 ps
CPU time 1070.28 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:23:24 PM PST 23
Peak memory 202072 kb
Host smart-5bc7a8eb-4f55-4c99-a33d-6d73c538c1cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227649222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.3227649222
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.2157998417
Short name T448
Test name
Test status
Simulation time 3022915680 ps
CPU time 60.64 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:06:45 PM PST 23
Peak memory 303320 kb
Host smart-1b92fa2f-c1e3-4996-9624-40d60d37867c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157998417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.2157998417
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3545918587
Short name T273
Test name
Test status
Simulation time 23780753107 ps
CPU time 78.88 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:07:02 PM PST 23
Peak memory 218424 kb
Host smart-670bdfcd-c5af-4416-a810-e436756ad1cd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545918587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.3545918587
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.2742481631
Short name T979
Test name
Test status
Simulation time 8043824040 ps
CPU time 237.27 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:09:42 PM PST 23
Peak memory 202096 kb
Host smart-b2e87a25-490f-4124-8cbc-9a56f35dc98d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742481631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.2742481631
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.1752820122
Short name T226
Test name
Test status
Simulation time 59280345750 ps
CPU time 861.34 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:20:03 PM PST 23
Peak memory 375960 kb
Host smart-7eecf88b-c2c0-4208-a941-6ccef6b2726d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752820122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.1752820122
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.3864352726
Short name T423
Test name
Test status
Simulation time 16043304144 ps
CPU time 163.92 seconds
Started Dec 31 01:05:33 PM PST 23
Finished Dec 31 01:08:18 PM PST 23
Peak memory 365716 kb
Host smart-fe7c87c9-4ffd-4408-ab73-6d8fa60bdf8e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864352726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.3864352726
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4088718193
Short name T446
Test name
Test status
Simulation time 23901480412 ps
CPU time 345.7 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:11:29 PM PST 23
Peak memory 202096 kb
Host smart-4328f9d3-d680-4ebc-8fb2-b5a745b95fab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088718193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.4088718193
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.449823531
Short name T726
Test name
Test status
Simulation time 1344031649 ps
CPU time 13.43 seconds
Started Dec 31 01:05:39 PM PST 23
Finished Dec 31 01:05:53 PM PST 23
Peak memory 202412 kb
Host smart-8388803c-e0a0-4c72-9620-8ddc2968dcb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449823531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.449823531
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.1468301971
Short name T941
Test name
Test status
Simulation time 14824747070 ps
CPU time 952.34 seconds
Started Dec 31 01:05:32 PM PST 23
Finished Dec 31 01:21:26 PM PST 23
Peak memory 375584 kb
Host smart-0753664b-7950-4fda-8fed-2bac0f242e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468301971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1468301971
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.3287539563
Short name T296
Test name
Test status
Simulation time 3871934747 ps
CPU time 18.36 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:06:05 PM PST 23
Peak memory 202012 kb
Host smart-1e3f87dc-b15e-49f1-8f05-87a259d3a8be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287539563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3287539563
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1593576680
Short name T903
Test name
Test status
Simulation time 3596361821 ps
CPU time 6076.63 seconds
Started Dec 31 01:05:47 PM PST 23
Finished Dec 31 02:47:05 PM PST 23
Peak memory 688324 kb
Host smart-d36c4708-cdd6-485a-8ed4-4ed1a031ec7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1593576680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1593576680
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3079003299
Short name T327
Test name
Test status
Simulation time 7463323004 ps
CPU time 263.27 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:10:07 PM PST 23
Peak memory 202080 kb
Host smart-875f9375-8de6-4d1d-a8c8-7da6f6e1f91f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079003299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.3079003299
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.923235334
Short name T134
Test name
Test status
Simulation time 727049873 ps
CPU time 35.79 seconds
Started Dec 31 01:05:39 PM PST 23
Finished Dec 31 01:06:16 PM PST 23
Peak memory 252272 kb
Host smart-c7aaf653-ed40-41bc-b478-9370dc157021
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923235334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_throughput_w_partial_write.923235334
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3540927880
Short name T780
Test name
Test status
Simulation time 30514953564 ps
CPU time 1019.45 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:22:40 PM PST 23
Peak memory 380004 kb
Host smart-8e18f274-c1e0-4f92-8d05-d8401a528d31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540927880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.3540927880
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.1216387038
Short name T19
Test name
Test status
Simulation time 30160005 ps
CPU time 0.63 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:05:33 PM PST 23
Peak memory 201408 kb
Host smart-640fb521-3670-4698-a642-d53e7ea4d9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216387038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.1216387038
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.3558505692
Short name T40
Test name
Test status
Simulation time 46171862275 ps
CPU time 1580.17 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:32:06 PM PST 23
Peak memory 202216 kb
Host smart-4347421c-54d3-4fd5-85c9-67736b38c93b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558505692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.3558505692
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.3315560133
Short name T464
Test name
Test status
Simulation time 20899721295 ps
CPU time 70.93 seconds
Started Dec 31 01:05:47 PM PST 23
Finished Dec 31 01:06:59 PM PST 23
Peak memory 210372 kb
Host smart-09a2853a-f214-41dd-93b1-6c3d04d08aa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315560133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.3315560133
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.2450588319
Short name T918
Test name
Test status
Simulation time 2488929559 ps
CPU time 66.35 seconds
Started Dec 31 01:05:45 PM PST 23
Finished Dec 31 01:06:54 PM PST 23
Peak memory 295124 kb
Host smart-9bf03ef7-0a15-4511-886f-e89c3d97f571
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450588319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.2450588319
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.811775967
Short name T395
Test name
Test status
Simulation time 4986192786 ps
CPU time 148.53 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:08:14 PM PST 23
Peak memory 210784 kb
Host smart-420dbc16-1800-4ad4-8b1b-2b4bf1020643
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811775967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_mem_partial_access.811775967
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.2629864615
Short name T639
Test name
Test status
Simulation time 20671259728 ps
CPU time 311.33 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:10:54 PM PST 23
Peak memory 202396 kb
Host smart-51d14740-8a4c-4ed9-92c3-997b4c4b3b97
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629864615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.2629864615
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.3999331031
Short name T518
Test name
Test status
Simulation time 35132144675 ps
CPU time 893.42 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:20:38 PM PST 23
Peak memory 373160 kb
Host smart-4f28047d-30e5-4c47-be44-991f1646fc56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999331031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.3999331031
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.2906422830
Short name T676
Test name
Test status
Simulation time 5237393732 ps
CPU time 174.71 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:08:41 PM PST 23
Peak memory 366716 kb
Host smart-0e6d104d-0ec0-44b6-8c32-122cadf69104
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906422830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.2906422830
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3156435081
Short name T970
Test name
Test status
Simulation time 5552982562 ps
CPU time 333.44 seconds
Started Dec 31 01:05:33 PM PST 23
Finished Dec 31 01:11:08 PM PST 23
Peak memory 202212 kb
Host smart-99accef1-05c2-499d-86a7-627af23ad382
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156435081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.3156435081
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.1723735345
Short name T971
Test name
Test status
Simulation time 349665301 ps
CPU time 6.35 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:05:39 PM PST 23
Peak memory 202420 kb
Host smart-67d83f31-5372-49e7-8f34-8439973996eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723735345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1723735345
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.2864799389
Short name T942
Test name
Test status
Simulation time 523873296 ps
CPU time 33.55 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:06:17 PM PST 23
Peak memory 247284 kb
Host smart-b49c1558-c108-4f45-8a1d-015a441928f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864799389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2864799389
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.2285987898
Short name T511
Test name
Test status
Simulation time 7266962280 ps
CPU time 43.87 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:06:27 PM PST 23
Peak memory 202088 kb
Host smart-224c7c64-1a35-41b1-808d-54b94c996beb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285987898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2285987898
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.4240220375
Short name T806
Test name
Test status
Simulation time 65108840533 ps
CPU time 3280.04 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 02:00:24 PM PST 23
Peak memory 380008 kb
Host smart-4afac38e-763b-4e0d-ad37-30697fba63b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240220375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.4240220375
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1101542828
Short name T261
Test name
Test status
Simulation time 6493746335 ps
CPU time 4811.3 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 02:25:58 PM PST 23
Peak memory 698108 kb
Host smart-50a60654-36c1-4cee-9f26-28e23990e713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1101542828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1101542828
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2670680826
Short name T457
Test name
Test status
Simulation time 10590728405 ps
CPU time 386.81 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:12:13 PM PST 23
Peak memory 202156 kb
Host smart-300cfa95-330a-483a-a963-8c6a1ef9521d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670680826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.2670680826
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3292759344
Short name T292
Test name
Test status
Simulation time 1398632728 ps
CPU time 30.84 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:06:13 PM PST 23
Peak memory 226220 kb
Host smart-906eba07-b161-4cdb-af96-9ee0930604e9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292759344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3292759344
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3851096213
Short name T552
Test name
Test status
Simulation time 41055895293 ps
CPU time 1308.95 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:27:35 PM PST 23
Peak memory 377088 kb
Host smart-47104986-52d6-48d6-8d32-afaa816aa4f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851096213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.3851096213
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.1017778775
Short name T306
Test name
Test status
Simulation time 12656901 ps
CPU time 0.62 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:05:47 PM PST 23
Peak memory 201428 kb
Host smart-56ac715e-9b79-4d21-a09c-b5b2ec53c89d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017778775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.1017778775
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.2078688253
Short name T661
Test name
Test status
Simulation time 141129077242 ps
CPU time 1176.61 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:25:20 PM PST 23
Peak memory 202216 kb
Host smart-08e1a2ac-5858-491c-a2dc-557f22e3c532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078688253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.2078688253
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.4204581356
Short name T255
Test name
Test status
Simulation time 33671898373 ps
CPU time 1862.82 seconds
Started Dec 31 01:05:39 PM PST 23
Finished Dec 31 01:36:43 PM PST 23
Peak memory 378980 kb
Host smart-1e15b258-0bb0-456f-830c-478d1696b4c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204581356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.4204581356
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.2949890749
Short name T768
Test name
Test status
Simulation time 4067902422 ps
CPU time 41.94 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:06:28 PM PST 23
Peak memory 210400 kb
Host smart-76a82d85-6986-4e9b-8a31-f1abf23f2e7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949890749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.2949890749
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.3247735610
Short name T665
Test name
Test status
Simulation time 1529028421 ps
CPU time 137.53 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:08:02 PM PST 23
Peak memory 365788 kb
Host smart-e3d81a15-c1c0-421f-b6f7-540208d25115
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247735610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.3247735610
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1693633543
Short name T849
Test name
Test status
Simulation time 7367243182 ps
CPU time 142.97 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:08:06 PM PST 23
Peak memory 214540 kb
Host smart-8d7abf06-b8b0-4061-8cda-b57de81347eb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693633543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.1693633543
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.879791104
Short name T241
Test name
Test status
Simulation time 28111170666 ps
CPU time 283.7 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:10:28 PM PST 23
Peak memory 202204 kb
Host smart-5ad2e74d-7bbf-4dc9-bdf6-5e09232da858
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879791104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl
_mem_walk.879791104
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.1535472880
Short name T404
Test name
Test status
Simulation time 5919208676 ps
CPU time 941.24 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:21:24 PM PST 23
Peak memory 380096 kb
Host smart-1c75257f-34ab-49e4-ba35-ba460b75e3e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535472880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.1535472880
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.1320271390
Short name T556
Test name
Test status
Simulation time 866682106 ps
CPU time 20.55 seconds
Started Dec 31 01:05:31 PM PST 23
Finished Dec 31 01:05:53 PM PST 23
Peak memory 233268 kb
Host smart-ff87050b-0624-455b-a724-5f337c34466b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320271390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.1320271390
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3074700497
Short name T713
Test name
Test status
Simulation time 6416895403 ps
CPU time 414.1 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:12:39 PM PST 23
Peak memory 202140 kb
Host smart-c67b15f9-5478-450f-a624-2c03b52fcca4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074700497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.3074700497
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.2663850238
Short name T465
Test name
Test status
Simulation time 350213927 ps
CPU time 13.32 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:06:00 PM PST 23
Peak memory 202416 kb
Host smart-06b99f19-7484-4bf3-ac71-5849d365f0b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663850238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2663850238
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.3293730094
Short name T835
Test name
Test status
Simulation time 13727273686 ps
CPU time 674.42 seconds
Started Dec 31 01:05:39 PM PST 23
Finished Dec 31 01:16:54 PM PST 23
Peak memory 372840 kb
Host smart-16e577aa-6abe-4952-bb4a-53f49913425b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293730094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.3293730094
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.225228614
Short name T691
Test name
Test status
Simulation time 1446125683 ps
CPU time 29.87 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:06:14 PM PST 23
Peak memory 202056 kb
Host smart-c6517443-4e03-4e63-971f-0fab94192de6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225228614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.225228614
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.1827176893
Short name T620
Test name
Test status
Simulation time 52962409707 ps
CPU time 3837.88 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 02:09:41 PM PST 23
Peak memory 380104 kb
Host smart-af7d8ded-f331-420e-9676-9ebca91813fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827176893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.1827176893
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2517177214
Short name T449
Test name
Test status
Simulation time 4886897981 ps
CPU time 4688.55 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 02:23:56 PM PST 23
Peak memory 519428 kb
Host smart-2a661055-df59-4bf1-aefd-faa3b9b66fcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2517177214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.2517177214
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2749337298
Short name T872
Test name
Test status
Simulation time 6841064091 ps
CPU time 269.13 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:10:14 PM PST 23
Peak memory 202140 kb
Host smart-c17ed2f6-138d-4fd3-9cf5-a53c48fe413c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749337298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.2749337298
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.471442819
Short name T554
Test name
Test status
Simulation time 790054874 ps
CPU time 185.21 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:08:50 PM PST 23
Peak memory 374940 kb
Host smart-fc6c548b-c648-46a6-95a5-49393cdef303
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471442819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_throughput_w_partial_write.471442819
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.228113272
Short name T345
Test name
Test status
Simulation time 4744628150 ps
CPU time 777.16 seconds
Started Dec 31 01:05:48 PM PST 23
Finished Dec 31 01:18:46 PM PST 23
Peak memory 363708 kb
Host smart-49a4b94b-20f6-46f6-a527-5a2ef1377bad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228113272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.sram_ctrl_access_during_key_req.228113272
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.337780505
Short name T20
Test name
Test status
Simulation time 35887996 ps
CPU time 0.65 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:05:45 PM PST 23
Peak memory 201420 kb
Host smart-9042b654-f32a-429c-8861-497f51824bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337780505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.337780505
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.2079434635
Short name T285
Test name
Test status
Simulation time 66942280091 ps
CPU time 1135.19 seconds
Started Dec 31 01:05:45 PM PST 23
Finished Dec 31 01:24:43 PM PST 23
Peak memory 202152 kb
Host smart-c3f6576b-50ee-4d6e-9725-3bfbf30905f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079434635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.2079434635
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.2459264684
Short name T462
Test name
Test status
Simulation time 21760534646 ps
CPU time 66.52 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:06:53 PM PST 23
Peak memory 210372 kb
Host smart-e31fddb8-a4c6-4289-bf2c-28c0ae66bf52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459264684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.2459264684
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.3418971482
Short name T625
Test name
Test status
Simulation time 3189513523 ps
CPU time 145.25 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:08:08 PM PST 23
Peak memory 365684 kb
Host smart-42c32bf1-fa73-476e-af1a-ec4e397b3f47
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418971482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.3418971482
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2732114896
Short name T964
Test name
Test status
Simulation time 13026760466 ps
CPU time 74.12 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:07:00 PM PST 23
Peak memory 211696 kb
Host smart-ee58e250-e339-4344-9687-45f5ec1b63e5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732114896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.2732114896
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.1838776846
Short name T854
Test name
Test status
Simulation time 86070594720 ps
CPU time 319.83 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:11:05 PM PST 23
Peak memory 202228 kb
Host smart-d7ef2d9a-eb16-4ff5-861c-93058095c212
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838776846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.1838776846
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.1069191521
Short name T613
Test name
Test status
Simulation time 22330766458 ps
CPU time 1243.4 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:26:31 PM PST 23
Peak memory 380064 kb
Host smart-30863493-b68f-459f-94ed-b86e18d86985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069191521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.1069191521
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.2879902511
Short name T899
Test name
Test status
Simulation time 3779026728 ps
CPU time 28.48 seconds
Started Dec 31 01:05:45 PM PST 23
Finished Dec 31 01:06:16 PM PST 23
Peak memory 257696 kb
Host smart-9de280a3-7787-4812-ae72-4908e4d0fe8b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879902511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.2879902511
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3881915805
Short name T657
Test name
Test status
Simulation time 20931430906 ps
CPU time 329.03 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:11:14 PM PST 23
Peak memory 202164 kb
Host smart-2d99abda-885b-4094-aff4-6fe23f2e9183
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881915805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.3881915805
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.692760963
Short name T440
Test name
Test status
Simulation time 1344272657 ps
CPU time 5.98 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:05:52 PM PST 23
Peak memory 202460 kb
Host smart-59ea94b3-d3c4-40d6-ad0b-97b32e2b1d64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692760963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.692760963
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.1003453326
Short name T916
Test name
Test status
Simulation time 19836741358 ps
CPU time 1316.95 seconds
Started Dec 31 01:05:49 PM PST 23
Finished Dec 31 01:27:47 PM PST 23
Peak memory 381072 kb
Host smart-6fffef01-0756-4ba3-9ac4-a9a1bb8ab6c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003453326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1003453326
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.656948911
Short name T239
Test name
Test status
Simulation time 899626081 ps
CPU time 105.68 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:07:29 PM PST 23
Peak memory 348496 kb
Host smart-407d4078-633f-4b8a-9c1f-ba3ae4f4c422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656948911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.656948911
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.2304950716
Short name T508
Test name
Test status
Simulation time 1129892386167 ps
CPU time 6382.02 seconds
Started Dec 31 01:05:47 PM PST 23
Finished Dec 31 02:52:11 PM PST 23
Peak memory 383752 kb
Host smart-85d397c3-673f-4754-bbd6-b70a53ccf30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304950716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.2304950716
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2053316295
Short name T708
Test name
Test status
Simulation time 2524715375 ps
CPU time 3190.43 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:58:56 PM PST 23
Peak memory 698368 kb
Host smart-e34b788d-3cb2-4e3c-bc48-fa4973839752
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2053316295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2053316295
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.702429421
Short name T532
Test name
Test status
Simulation time 20113695425 ps
CPU time 409.75 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:12:37 PM PST 23
Peak memory 202036 kb
Host smart-4b9315d2-c0e2-470c-9adc-cabb3c32b013
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702429421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_stress_pipeline.702429421
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.563439882
Short name T272
Test name
Test status
Simulation time 5577367087 ps
CPU time 28.93 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:06:16 PM PST 23
Peak memory 210280 kb
Host smart-45e30961-2d07-4367-8e83-b02264da1b7d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563439882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.563439882
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1548416802
Short name T234
Test name
Test status
Simulation time 11177889579 ps
CPU time 1744.04 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:34:51 PM PST 23
Peak memory 380124 kb
Host smart-71c6605f-1393-4d47-90c2-d647ee0a8d30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548416802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.1548416802
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.698622887
Short name T929
Test name
Test status
Simulation time 48498377 ps
CPU time 0.67 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:05:46 PM PST 23
Peak memory 201780 kb
Host smart-e148ca13-0a1c-4305-90b5-be86a2e07d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698622887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.698622887
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.3570397998
Short name T228
Test name
Test status
Simulation time 43290159984 ps
CPU time 765.52 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:18:31 PM PST 23
Peak memory 202060 kb
Host smart-d88d30fc-47ff-45eb-a6ba-9734e7b42f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570397998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.3570397998
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.4143902268
Short name T517
Test name
Test status
Simulation time 14425048759 ps
CPU time 73.93 seconds
Started Dec 31 01:05:46 PM PST 23
Finished Dec 31 01:07:02 PM PST 23
Peak memory 213780 kb
Host smart-f5ac24e1-1fe7-499e-ae5b-2a4b26d578ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143902268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.4143902268
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.2956668169
Short name T56
Test name
Test status
Simulation time 3153789591 ps
CPU time 121.27 seconds
Started Dec 31 01:05:49 PM PST 23
Finished Dec 31 01:07:50 PM PST 23
Peak memory 353404 kb
Host smart-13928d43-3057-4d35-acf9-2c4c1f16ddd8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956668169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.2956668169
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.711605425
Short name T85
Test name
Test status
Simulation time 995239628 ps
CPU time 72.28 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:06:54 PM PST 23
Peak memory 218388 kb
Host smart-e691604d-49af-4d27-a8bc-5a8f26d42306
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711605425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.sram_ctrl_mem_partial_access.711605425
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.3030518479
Short name T880
Test name
Test status
Simulation time 8211251765 ps
CPU time 255.06 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:09:58 PM PST 23
Peak memory 202208 kb
Host smart-37336f86-3418-4dc5-ab54-0dc3fce477f0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030518479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.3030518479
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.3445021797
Short name T803
Test name
Test status
Simulation time 14924011053 ps
CPU time 1217.16 seconds
Started Dec 31 01:05:48 PM PST 23
Finished Dec 31 01:26:06 PM PST 23
Peak memory 381056 kb
Host smart-eb016cfd-28bf-456f-94ec-f4679c681c84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445021797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.3445021797
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.1970568654
Short name T503
Test name
Test status
Simulation time 1633589174 ps
CPU time 18.27 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:06:05 PM PST 23
Peak memory 229656 kb
Host smart-ebfce8f5-834c-4006-9ced-22c1660d872d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970568654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.1970568654
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2530321074
Short name T615
Test name
Test status
Simulation time 7714017917 ps
CPU time 455.5 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:13:22 PM PST 23
Peak memory 202176 kb
Host smart-3990ca6a-fb19-4e8b-9400-2fd1938353ac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530321074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.2530321074
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.1446754657
Short name T602
Test name
Test status
Simulation time 685026234 ps
CPU time 5.47 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:05:49 PM PST 23
Peak memory 202332 kb
Host smart-28812d46-6f2d-4d3f-8ada-8a700cc9c2a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446754657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1446754657
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.1405007457
Short name T328
Test name
Test status
Simulation time 6409323313 ps
CPU time 906.92 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:20:53 PM PST 23
Peak memory 371940 kb
Host smart-0c1b40ec-f8b0-44a9-9143-8e307804c2ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405007457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1405007457
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.1929444666
Short name T412
Test name
Test status
Simulation time 946431340 ps
CPU time 37.02 seconds
Started Dec 31 01:05:46 PM PST 23
Finished Dec 31 01:06:25 PM PST 23
Peak memory 202040 kb
Host smart-8708fb28-1636-4023-8679-4db3e11e5806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929444666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1929444666
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.173411830
Short name T921
Test name
Test status
Simulation time 75458837155 ps
CPU time 4545.64 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 02:21:29 PM PST 23
Peak memory 368788 kb
Host smart-1bf0e075-23a0-4935-af74-c470317a771e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173411830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_stress_all.173411830
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3165649599
Short name T662
Test name
Test status
Simulation time 613698683 ps
CPU time 4054.17 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 02:13:18 PM PST 23
Peak memory 538232 kb
Host smart-6d74088a-1ab0-44df-b41a-4dc254fcc188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3165649599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3165649599
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.4059286352
Short name T637
Test name
Test status
Simulation time 3624409581 ps
CPU time 290.09 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:10:36 PM PST 23
Peak memory 202172 kb
Host smart-92972b38-8ec4-4cc2-99c7-d8850852004d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059286352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.4059286352
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.100665017
Short name T321
Test name
Test status
Simulation time 703363649 ps
CPU time 34.41 seconds
Started Dec 31 01:05:46 PM PST 23
Finished Dec 31 01:06:22 PM PST 23
Peak memory 242812 kb
Host smart-5d8dad75-31b5-4f0f-b7b1-7764613cd8ed
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100665017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_throughput_w_partial_write.100665017
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.555121473
Short name T850
Test name
Test status
Simulation time 41294396578 ps
CPU time 1222.7 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:26:07 PM PST 23
Peak memory 372432 kb
Host smart-848e8f40-6704-4c01-9cc5-ac8f14b1b94c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555121473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 38.sram_ctrl_access_during_key_req.555121473
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.1015848929
Short name T961
Test name
Test status
Simulation time 20849086 ps
CPU time 0.63 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:05:46 PM PST 23
Peak memory 201868 kb
Host smart-bf08b296-3eee-4ff0-875f-a7594b423a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015848929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.1015848929
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.2109459875
Short name T411
Test name
Test status
Simulation time 148055088056 ps
CPU time 1661.97 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:33:26 PM PST 23
Peak memory 202132 kb
Host smart-3416b984-638c-4977-8032-4daddd6c098d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109459875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.2109459875
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.2451398412
Short name T336
Test name
Test status
Simulation time 48581935001 ps
CPU time 744.14 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:18:07 PM PST 23
Peak memory 379080 kb
Host smart-d78f15af-d7ee-4020-b7b4-70b72063a348
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451398412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.2451398412
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.3329120489
Short name T570
Test name
Test status
Simulation time 41777604183 ps
CPU time 113.34 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:07:35 PM PST 23
Peak memory 210388 kb
Host smart-1b9476a6-a903-44ed-bb45-e9134e36ffd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329120489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.3329120489
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.2444584936
Short name T622
Test name
Test status
Simulation time 9735341387 ps
CPU time 31.94 seconds
Started Dec 31 01:05:38 PM PST 23
Finished Dec 31 01:06:10 PM PST 23
Peak memory 225484 kb
Host smart-153c1a5a-df63-4769-8269-2748b4b5e77a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444584936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.2444584936
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3254947094
Short name T707
Test name
Test status
Simulation time 6261293307 ps
CPU time 144.11 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:08:09 PM PST 23
Peak memory 211160 kb
Host smart-f53790e6-dbf6-4792-9b6c-ab52d249b7a9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254947094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.3254947094
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.2321029919
Short name T646
Test name
Test status
Simulation time 28106848969 ps
CPU time 303.32 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:10:49 PM PST 23
Peak memory 202340 kb
Host smart-bc2ddb8e-66c3-44b9-a959-ff68a9e8aa9e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321029919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.2321029919
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.4285717435
Short name T313
Test name
Test status
Simulation time 3545611873 ps
CPU time 315.41 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 352496 kb
Host smart-922ac330-7c05-4bac-917e-69ea12b361c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285717435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.4285717435
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.824466833
Short name T302
Test name
Test status
Simulation time 3111659161 ps
CPU time 14.94 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:06:01 PM PST 23
Peak memory 202172 kb
Host smart-7b89282a-a793-469c-aaa5-d151c300f3b9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824466833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s
ram_ctrl_partial_access.824466833
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.806011229
Short name T242
Test name
Test status
Simulation time 14388477391 ps
CPU time 310.2 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:10:54 PM PST 23
Peak memory 202116 kb
Host smart-126366ed-3063-4538-b17d-38063b20fd5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806011229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.sram_ctrl_partial_access_b2b.806011229
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.2955557239
Short name T700
Test name
Test status
Simulation time 1460388616 ps
CPU time 6.71 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:05:51 PM PST 23
Peak memory 202456 kb
Host smart-d08b5bb3-be07-4156-8fd4-d24dc2b3b75b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955557239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2955557239
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.1912181753
Short name T41
Test name
Test status
Simulation time 3467365988 ps
CPU time 1100.03 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:24:05 PM PST 23
Peak memory 376000 kb
Host smart-6412976e-3e88-40ce-a0ae-54558d87c9a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912181753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1912181753
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.2799694839
Short name T658
Test name
Test status
Simulation time 935519252 ps
CPU time 140.68 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:08:03 PM PST 23
Peak memory 355408 kb
Host smart-ab045ac3-d8a2-484d-81a4-0f1985e033eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799694839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2799694839
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1209783119
Short name T542
Test name
Test status
Simulation time 1417996270 ps
CPU time 2205.28 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:42:31 PM PST 23
Peak memory 403124 kb
Host smart-bfbf86d2-c8f0-4da9-9ab6-acd1dbd892f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1209783119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1209783119
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2939491386
Short name T782
Test name
Test status
Simulation time 2899748194 ps
CPU time 230.74 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:09:33 PM PST 23
Peak memory 202160 kb
Host smart-a94af61e-cd08-4a00-b0fc-11c5db3a187a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939491386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.2939491386
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1577218502
Short name T817
Test name
Test status
Simulation time 11465027187 ps
CPU time 36.14 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:06:22 PM PST 23
Peak memory 234800 kb
Host smart-0a38a592-b7e9-44fe-92f5-6c76cff522da
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577218502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.1577218502
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3495545431
Short name T527
Test name
Test status
Simulation time 10085883342 ps
CPU time 743.64 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:18:10 PM PST 23
Peak memory 377044 kb
Host smart-44278594-dc0d-4bec-b68f-5e3e5a8a5dba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495545431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.3495545431
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.122923526
Short name T480
Test name
Test status
Simulation time 13070385 ps
CPU time 0.62 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:05:46 PM PST 23
Peak memory 201872 kb
Host smart-d59ad98d-1ea9-426f-b7c8-e33544489b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122923526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.122923526
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.2401116505
Short name T138
Test name
Test status
Simulation time 163081670373 ps
CPU time 1760.43 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:35:05 PM PST 23
Peak memory 202140 kb
Host smart-5992f3fb-e963-46bc-bd82-92fa3d6d2f57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401116505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.2401116505
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.2038752890
Short name T347
Test name
Test status
Simulation time 105417978320 ps
CPU time 1648.39 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:33:11 PM PST 23
Peak memory 375852 kb
Host smart-85c59e77-d0aa-4a07-9427-3f3c7625c220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038752890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.2038752890
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.407833130
Short name T649
Test name
Test status
Simulation time 13973790791 ps
CPU time 151.8 seconds
Started Dec 31 01:05:45 PM PST 23
Finished Dec 31 01:08:19 PM PST 23
Peak memory 210404 kb
Host smart-b200f37f-cad4-453d-9733-6430b2d38cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407833130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_esc
alation.407833130
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.907433490
Short name T252
Test name
Test status
Simulation time 770317766 ps
CPU time 163.13 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:08:30 PM PST 23
Peak memory 373460 kb
Host smart-acd3f783-1a00-452e-8449-431f3a7d570c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907433490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.sram_ctrl_max_throughput.907433490
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.4149336201
Short name T862
Test name
Test status
Simulation time 1637085584 ps
CPU time 126.97 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:07:52 PM PST 23
Peak memory 218448 kb
Host smart-a44ba2b5-ccc7-4ddc-8693-64a330d96bde
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149336201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.4149336201
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.2387966465
Short name T643
Test name
Test status
Simulation time 8232470766 ps
CPU time 127.14 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:07:54 PM PST 23
Peak memory 202276 kb
Host smart-3025607b-d22d-4c0c-b9b5-d4a86b5d1095
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387966465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.2387966465
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.1323000499
Short name T797
Test name
Test status
Simulation time 6617437062 ps
CPU time 656.55 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:16:40 PM PST 23
Peak memory 370908 kb
Host smart-5156f11f-58fb-492e-810d-08bcf2876bbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323000499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.1323000499
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.544637990
Short name T368
Test name
Test status
Simulation time 773185141 ps
CPU time 29.25 seconds
Started Dec 31 01:05:45 PM PST 23
Finished Dec 31 01:06:17 PM PST 23
Peak memory 202144 kb
Host smart-db8246ef-854b-451b-ac21-4bf47ae0db5f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544637990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s
ram_ctrl_partial_access.544637990
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.69083796
Short name T796
Test name
Test status
Simulation time 22941502188 ps
CPU time 516.05 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:14:23 PM PST 23
Peak memory 202172 kb
Host smart-4b5ced1d-b69a-4567-a7b9-1ba84805d4d0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69083796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_partial_access_b2b.69083796
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.1816032472
Short name T652
Test name
Test status
Simulation time 4818299241 ps
CPU time 6.42 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:05:54 PM PST 23
Peak memory 202464 kb
Host smart-1edf0fd7-7d76-4953-a157-fb2c56adebc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816032472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1816032472
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.2424027733
Short name T704
Test name
Test status
Simulation time 23390500568 ps
CPU time 1122.55 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:24:29 PM PST 23
Peak memory 377028 kb
Host smart-d8b421d2-0d08-41e4-91b1-624c1fcb64d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424027733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2424027733
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.3840049788
Short name T340
Test name
Test status
Simulation time 5037316374 ps
CPU time 12.76 seconds
Started Dec 31 01:05:41 PM PST 23
Finished Dec 31 01:05:56 PM PST 23
Peak memory 202120 kb
Host smart-4b58c22e-189a-41b5-aed0-0e8ab9a1f8bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840049788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3840049788
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1290980409
Short name T28
Test name
Test status
Simulation time 2510791201 ps
CPU time 3902.07 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 02:10:50 PM PST 23
Peak memory 732076 kb
Host smart-f80fc09e-c952-455a-a4e7-c28a6585c023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1290980409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1290980409
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.3128695338
Short name T882
Test name
Test status
Simulation time 23338683250 ps
CPU time 444.07 seconds
Started Dec 31 01:05:42 PM PST 23
Finished Dec 31 01:13:09 PM PST 23
Peak memory 202172 kb
Host smart-e0fece5f-5acb-4d4c-8663-9e94128bca55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128695338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.3128695338
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1734046344
Short name T904
Test name
Test status
Simulation time 738287497 ps
CPU time 39.68 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:06:26 PM PST 23
Peak memory 256140 kb
Host smart-c904befe-7eee-4f78-8b00-03d8b6cc062d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734046344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1734046344
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.427054960
Short name T928
Test name
Test status
Simulation time 10104864709 ps
CPU time 1645.26 seconds
Started Dec 31 01:04:09 PM PST 23
Finished Dec 31 01:31:35 PM PST 23
Peak memory 380100 kb
Host smart-38d56b92-3bec-43d4-88a1-5eb611c63986
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427054960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.sram_ctrl_access_during_key_req.427054960
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.1511612671
Short name T609
Test name
Test status
Simulation time 41512150 ps
CPU time 0.61 seconds
Started Dec 31 01:04:00 PM PST 23
Finished Dec 31 01:04:01 PM PST 23
Peak memory 201360 kb
Host smart-3d0373e6-29c3-4df7-9058-1dea8dd0ed97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511612671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.1511612671
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.67506215
Short name T275
Test name
Test status
Simulation time 276021918208 ps
CPU time 1754.58 seconds
Started Dec 31 01:04:07 PM PST 23
Finished Dec 31 01:33:23 PM PST 23
Peak memory 201968 kb
Host smart-75510c55-631e-4f70-a4c0-ee96ab2cb0f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67506215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.67506215
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.515633550
Short name T305
Test name
Test status
Simulation time 8896060008 ps
CPU time 91.24 seconds
Started Dec 31 01:04:04 PM PST 23
Finished Dec 31 01:05:37 PM PST 23
Peak memory 210336 kb
Host smart-79940e59-4fd8-4581-bc40-674402c9b407
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515633550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca
lation.515633550
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.2688720997
Short name T818
Test name
Test status
Simulation time 758238639 ps
CPU time 96.71 seconds
Started Dec 31 01:04:17 PM PST 23
Finished Dec 31 01:05:55 PM PST 23
Peak memory 333036 kb
Host smart-49294722-bf02-44e5-936e-c5eaf7fc7b4f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688720997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.2688720997
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3060744791
Short name T431
Test name
Test status
Simulation time 1612015285 ps
CPU time 136.34 seconds
Started Dec 31 01:03:53 PM PST 23
Finished Dec 31 01:06:11 PM PST 23
Peak memory 211088 kb
Host smart-1f30acf1-e3c0-4323-8c9a-2186b2f7992b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060744791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.3060744791
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.3632536734
Short name T630
Test name
Test status
Simulation time 15755744780 ps
CPU time 241.12 seconds
Started Dec 31 01:03:55 PM PST 23
Finished Dec 31 01:07:58 PM PST 23
Peak memory 202136 kb
Host smart-18846f38-ec9d-4ced-b400-7dd30b6d10b8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632536734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.3632536734
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.839265826
Short name T418
Test name
Test status
Simulation time 131133633554 ps
CPU time 1784.15 seconds
Started Dec 31 01:03:49 PM PST 23
Finished Dec 31 01:33:35 PM PST 23
Peak memory 378988 kb
Host smart-710006ae-b81b-4c0e-afa7-2fa284a422c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839265826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl
e_keys.839265826
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.331135829
Short name T710
Test name
Test status
Simulation time 4235739236 ps
CPU time 42.9 seconds
Started Dec 31 01:03:39 PM PST 23
Finished Dec 31 01:04:25 PM PST 23
Peak memory 202092 kb
Host smart-7b68cab3-cc2d-440d-84f5-03c3f2b9110e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331135829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr
am_ctrl_partial_access.331135829
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2731652989
Short name T844
Test name
Test status
Simulation time 44592055847 ps
CPU time 282.38 seconds
Started Dec 31 01:04:02 PM PST 23
Finished Dec 31 01:08:46 PM PST 23
Peak memory 202116 kb
Host smart-de95d1a5-c42e-4059-a92b-a3f1e78886a4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731652989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.2731652989
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.1883811464
Short name T280
Test name
Test status
Simulation time 343084122 ps
CPU time 6.49 seconds
Started Dec 31 01:04:01 PM PST 23
Finished Dec 31 01:04:09 PM PST 23
Peak memory 202408 kb
Host smart-04abcf03-c992-410a-bfee-142b4620abf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883811464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1883811464
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.1836636357
Short name T267
Test name
Test status
Simulation time 11657981572 ps
CPU time 1181.68 seconds
Started Dec 31 01:04:03 PM PST 23
Finished Dec 31 01:23:46 PM PST 23
Peak memory 379984 kb
Host smart-f7d509cc-4e56-4990-bf7e-a7726d02e54c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836636357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1836636357
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.1797404151
Short name T33
Test name
Test status
Simulation time 5224016937 ps
CPU time 3.23 seconds
Started Dec 31 01:04:09 PM PST 23
Finished Dec 31 01:04:13 PM PST 23
Peak memory 221608 kb
Host smart-122929ef-0600-4e4d-9907-ccf1b8f8090f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797404151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.1797404151
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.1936590388
Short name T388
Test name
Test status
Simulation time 1589886205 ps
CPU time 20.27 seconds
Started Dec 31 01:03:54 PM PST 23
Finished Dec 31 01:04:16 PM PST 23
Peak memory 202096 kb
Host smart-3aec8939-9880-42da-baab-fa35c52dc8fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936590388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1936590388
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.2913308319
Short name T758
Test name
Test status
Simulation time 396466327358 ps
CPU time 5340.73 seconds
Started Dec 31 01:04:17 PM PST 23
Finished Dec 31 02:33:20 PM PST 23
Peak memory 380020 kb
Host smart-5fc342e5-352d-487a-9038-32608c13ff88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913308319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.2913308319
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2296947248
Short name T848
Test name
Test status
Simulation time 3211645377 ps
CPU time 4452.01 seconds
Started Dec 31 01:04:18 PM PST 23
Finished Dec 31 02:18:33 PM PST 23
Peak memory 555640 kb
Host smart-1d9fc005-2e83-4595-ab14-255f69334f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2296947248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2296947248
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.211397883
Short name T592
Test name
Test status
Simulation time 73802597050 ps
CPU time 495.21 seconds
Started Dec 31 01:03:58 PM PST 23
Finished Dec 31 01:12:15 PM PST 23
Peak memory 202160 kb
Host smart-3679ee47-f4c7-41d9-ac3e-0d3fd5a1635f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211397883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_stress_pipeline.211397883
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.936089178
Short name T767
Test name
Test status
Simulation time 5560132534 ps
CPU time 28.28 seconds
Started Dec 31 01:04:02 PM PST 23
Finished Dec 31 01:04:32 PM PST 23
Peak memory 210424 kb
Host smart-c3f41bf7-7572-4a54-866a-c202c3b8c9ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936089178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_throughput_w_partial_write.936089178
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2736403842
Short name T612
Test name
Test status
Simulation time 8338595386 ps
CPU time 952.14 seconds
Started Dec 31 01:06:19 PM PST 23
Finished Dec 31 01:22:14 PM PST 23
Peak memory 378004 kb
Host smart-803cab0f-962d-45b8-9ecf-bc8a5b6603e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736403842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.2736403842
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.2312384652
Short name T564
Test name
Test status
Simulation time 15641810 ps
CPU time 0.63 seconds
Started Dec 31 01:06:04 PM PST 23
Finished Dec 31 01:06:15 PM PST 23
Peak memory 201736 kb
Host smart-2216f1d5-4175-4639-a2c5-00ecaab47dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312384652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.2312384652
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.440179957
Short name T866
Test name
Test status
Simulation time 161892151400 ps
CPU time 2593.74 seconds
Started Dec 31 01:05:40 PM PST 23
Finished Dec 31 01:48:57 PM PST 23
Peak memory 202128 kb
Host smart-50e7093c-57e7-483f-bc27-35996eb6f4ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440179957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.
440179957
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.2182824219
Short name T44
Test name
Test status
Simulation time 12365353622 ps
CPU time 398.26 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:13:07 PM PST 23
Peak memory 378108 kb
Host smart-b0171e73-b620-4015-bf5e-dcebf19c39d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182824219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.2182824219
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.694626363
Short name T963
Test name
Test status
Simulation time 799068791 ps
CPU time 124.03 seconds
Started Dec 31 01:05:45 PM PST 23
Finished Dec 31 01:07:52 PM PST 23
Peak memory 365632 kb
Host smart-854f4783-444d-4481-bbb3-68feab52a9e0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694626363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.sram_ctrl_max_throughput.694626363
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.1690232479
Short name T824
Test name
Test status
Simulation time 6253421480 ps
CPU time 138.07 seconds
Started Dec 31 01:06:16 PM PST 23
Finished Dec 31 01:08:37 PM PST 23
Peak memory 211132 kb
Host smart-cda121d1-a70a-43d5-8783-6da2020e750a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690232479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.1690232479
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.1223882983
Short name T413
Test name
Test status
Simulation time 2046184805 ps
CPU time 124.23 seconds
Started Dec 31 01:05:46 PM PST 23
Finished Dec 31 01:07:52 PM PST 23
Peak memory 202080 kb
Host smart-10cc7cc4-03a3-400f-a671-bb09e3d44306
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223882983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.1223882983
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.124472746
Short name T420
Test name
Test status
Simulation time 38473920671 ps
CPU time 1453.53 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:30:00 PM PST 23
Peak memory 373032 kb
Host smart-39da9100-aab9-4ad6-9223-d169e5deecf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124472746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multip
le_keys.124472746
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.2851157127
Short name T714
Test name
Test status
Simulation time 7239720625 ps
CPU time 28.05 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:06:14 PM PST 23
Peak memory 202080 kb
Host smart-d87b7cbb-962d-45af-86fd-5157a2dd9cc0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851157127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.2851157127
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2622172656
Short name T499
Test name
Test status
Simulation time 95910160445 ps
CPU time 541.07 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:14:47 PM PST 23
Peak memory 202100 kb
Host smart-32c8a42d-797c-4bcf-be16-dd1167103114
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622172656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.2622172656
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.1981976741
Short name T682
Test name
Test status
Simulation time 1165237934 ps
CPU time 5.82 seconds
Started Dec 31 01:06:24 PM PST 23
Finished Dec 31 01:06:30 PM PST 23
Peak memory 202368 kb
Host smart-10eb7f72-cdb2-441f-adc4-31e6dda00f01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981976741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1981976741
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3981265627
Short name T372
Test name
Test status
Simulation time 3826295010 ps
CPU time 274.99 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:11:03 PM PST 23
Peak memory 370804 kb
Host smart-9fe10cf8-f75f-4f1b-a3c0-6ebd27a16790
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981265627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3981265627
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.4220321210
Short name T396
Test name
Test status
Simulation time 764157698 ps
CPU time 15.42 seconds
Started Dec 31 01:05:43 PM PST 23
Finished Dec 31 01:06:01 PM PST 23
Peak memory 202068 kb
Host smart-000a58b3-e6e2-4b51-bd5e-f76d603f24c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220321210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.4220321210
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.2604111742
Short name T549
Test name
Test status
Simulation time 209146998104 ps
CPU time 2081.72 seconds
Started Dec 31 01:06:04 PM PST 23
Finished Dec 31 01:40:56 PM PST 23
Peak memory 379096 kb
Host smart-48adf144-5c51-41e5-b93b-134ad561f381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604111742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.sram_ctrl_stress_all.2604111742
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2954702336
Short name T238
Test name
Test status
Simulation time 17569831375 ps
CPU time 1417.92 seconds
Started Dec 31 01:06:03 PM PST 23
Finished Dec 31 01:29:52 PM PST 23
Peak memory 729076 kb
Host smart-6166fa65-a6a2-4875-9d68-51ed28c43213
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2954702336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2954702336
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1982096063
Short name T510
Test name
Test status
Simulation time 6096778195 ps
CPU time 410.57 seconds
Started Dec 31 01:05:44 PM PST 23
Finished Dec 31 01:12:37 PM PST 23
Peak memory 202144 kb
Host smart-a15e6ad5-d102-4fa7-9f1a-28b8bad437cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982096063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.1982096063
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.880102866
Short name T277
Test name
Test status
Simulation time 890342662 ps
CPU time 135.36 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:08:44 PM PST 23
Peak memory 355440 kb
Host smart-4c11c59c-69c5-415b-9097-f08b264f36cb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880102866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_throughput_w_partial_write.880102866
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.485864652
Short name T426
Test name
Test status
Simulation time 30014878399 ps
CPU time 686.67 seconds
Started Dec 31 01:06:05 PM PST 23
Finished Dec 31 01:17:41 PM PST 23
Peak memory 375016 kb
Host smart-742b75c8-a31a-4b2a-95d4-36a5d4a78c5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485864652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.sram_ctrl_access_during_key_req.485864652
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.3938253445
Short name T909
Test name
Test status
Simulation time 21916709 ps
CPU time 0.63 seconds
Started Dec 31 01:06:18 PM PST 23
Finished Dec 31 01:06:23 PM PST 23
Peak memory 201364 kb
Host smart-624e26ed-fe51-44c9-88f2-a9725388106e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938253445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.3938253445
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.730281498
Short name T791
Test name
Test status
Simulation time 349091148021 ps
CPU time 1572.43 seconds
Started Dec 31 01:06:26 PM PST 23
Finished Dec 31 01:32:40 PM PST 23
Peak memory 202148 kb
Host smart-16797c56-d6ea-4831-a38d-86a794cec2b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730281498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.
730281498
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.735436767
Short name T125
Test name
Test status
Simulation time 18173158468 ps
CPU time 920.75 seconds
Started Dec 31 01:06:18 PM PST 23
Finished Dec 31 01:21:42 PM PST 23
Peak memory 378012 kb
Host smart-0869ce60-0070-49a3-a3a6-d0b8da1a6da8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735436767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executabl
e.735436767
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.15697656
Short name T26
Test name
Test status
Simulation time 7935588229 ps
CPU time 67.81 seconds
Started Dec 31 01:06:18 PM PST 23
Finished Dec 31 01:07:29 PM PST 23
Peak memory 202120 kb
Host smart-14149d61-1c4a-48a3-aead-6aacf11afe0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15697656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_esca
lation.15697656
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.4092877537
Short name T469
Test name
Test status
Simulation time 769600716 ps
CPU time 58.8 seconds
Started Dec 31 01:06:23 PM PST 23
Finished Dec 31 01:07:23 PM PST 23
Peak memory 291628 kb
Host smart-5bc3c856-cef0-4618-8dcd-d401fe162757
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092877537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.4092877537
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.4088504497
Short name T809
Test name
Test status
Simulation time 3167887639 ps
CPU time 129.27 seconds
Started Dec 31 01:06:16 PM PST 23
Finished Dec 31 01:08:28 PM PST 23
Peak memory 211672 kb
Host smart-c1a38043-3d78-4f27-856f-7fef49d7935c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088504497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.4088504497
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.2932718476
Short name T294
Test name
Test status
Simulation time 98393765044 ps
CPU time 289.65 seconds
Started Dec 31 01:06:20 PM PST 23
Finished Dec 31 01:11:12 PM PST 23
Peak memory 202248 kb
Host smart-e062a11e-7215-4a8c-87ae-e86d6a61a6db
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932718476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.2932718476
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.3017886594
Short name T297
Test name
Test status
Simulation time 50982992772 ps
CPU time 586.65 seconds
Started Dec 31 01:06:28 PM PST 23
Finished Dec 31 01:16:16 PM PST 23
Peak memory 376036 kb
Host smart-460ddedf-8f53-46d8-a051-d78b05f8c8bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017886594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.3017886594
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.3160206342
Short name T607
Test name
Test status
Simulation time 7042016127 ps
CPU time 36.45 seconds
Started Dec 31 01:06:16 PM PST 23
Finished Dec 31 01:06:57 PM PST 23
Peak memory 202148 kb
Host smart-b524fa8d-5311-4c05-b885-995ede852a99
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160206342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.3160206342
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2464960611
Short name T900
Test name
Test status
Simulation time 4896248865 ps
CPU time 318.61 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 01:11:45 PM PST 23
Peak memory 202124 kb
Host smart-631ba64e-8a9e-473b-8ce3-901266aae18f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464960611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.2464960611
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.958560723
Short name T685
Test name
Test status
Simulation time 357076080 ps
CPU time 13.5 seconds
Started Dec 31 01:06:24 PM PST 23
Finished Dec 31 01:06:38 PM PST 23
Peak memory 202196 kb
Host smart-df31711c-8353-43b9-8abc-ed2bb97ba882
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958560723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.958560723
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.2986502320
Short name T945
Test name
Test status
Simulation time 6400776775 ps
CPU time 188.96 seconds
Started Dec 31 01:06:17 PM PST 23
Finished Dec 31 01:09:30 PM PST 23
Peak memory 306956 kb
Host smart-386949f1-fa88-45c2-aec8-819063af5746
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986502320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2986502320
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.4134884680
Short name T295
Test name
Test status
Simulation time 744509046 ps
CPU time 26.99 seconds
Started Dec 31 01:05:47 PM PST 23
Finished Dec 31 01:06:15 PM PST 23
Peak memory 202076 kb
Host smart-2d914636-28b4-4172-ba35-fa377574cb1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134884680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.4134884680
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1137780619
Short name T221
Test name
Test status
Simulation time 16705011195 ps
CPU time 3433.84 seconds
Started Dec 31 01:06:15 PM PST 23
Finished Dec 31 02:03:33 PM PST 23
Peak memory 698384 kb
Host smart-74a48f5f-5e75-4a2a-8d0d-900dfbb14e01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1137780619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1137780619
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3465502229
Short name T67
Test name
Test status
Simulation time 16651741545 ps
CPU time 226.2 seconds
Started Dec 31 01:06:02 PM PST 23
Finished Dec 31 01:10:00 PM PST 23
Peak memory 202148 kb
Host smart-0e4c0214-f975-4cc5-8991-55ed38607e0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465502229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3465502229
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1029167873
Short name T217
Test name
Test status
Simulation time 2970117268 ps
CPU time 73.98 seconds
Started Dec 31 01:06:18 PM PST 23
Finished Dec 31 01:07:35 PM PST 23
Peak memory 304476 kb
Host smart-29434eef-2b1c-47ac-8e38-55092588ace1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029167873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1029167873
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1040813519
Short name T569
Test name
Test status
Simulation time 110353051952 ps
CPU time 1001.43 seconds
Started Dec 31 01:06:21 PM PST 23
Finished Dec 31 01:23:04 PM PST 23
Peak memory 380044 kb
Host smart-b4a22051-9d35-4e1f-99e1-9bec61d16e18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040813519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.1040813519
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.2094561755
Short name T458
Test name
Test status
Simulation time 34643840 ps
CPU time 0.64 seconds
Started Dec 31 01:06:17 PM PST 23
Finished Dec 31 01:06:21 PM PST 23
Peak memory 201884 kb
Host smart-00811598-1858-4940-bf6e-7b649f0fe458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094561755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.2094561755
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.1527224968
Short name T293
Test name
Test status
Simulation time 150831039150 ps
CPU time 2429.07 seconds
Started Dec 31 01:06:24 PM PST 23
Finished Dec 31 01:46:54 PM PST 23
Peak memory 202092 kb
Host smart-3af87ea2-8a08-4918-8548-702c71f17be6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527224968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.1527224968
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.3458807082
Short name T798
Test name
Test status
Simulation time 14999743061 ps
CPU time 136.52 seconds
Started Dec 31 01:06:31 PM PST 23
Finished Dec 31 01:08:49 PM PST 23
Peak memory 210368 kb
Host smart-a62adabf-44c3-4575-9835-c7a3a5cefb5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458807082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.3458807082
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.1544680158
Short name T871
Test name
Test status
Simulation time 2961178272 ps
CPU time 85.24 seconds
Started Dec 31 01:06:16 PM PST 23
Finished Dec 31 01:07:44 PM PST 23
Peak memory 329888 kb
Host smart-c3cc24f2-1292-4cfc-abc4-3bc913466e6e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544680158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.1544680158
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.106988317
Short name T834
Test name
Test status
Simulation time 2354572555 ps
CPU time 76.58 seconds
Started Dec 31 01:06:19 PM PST 23
Finished Dec 31 01:07:39 PM PST 23
Peak memory 211060 kb
Host smart-6764ef17-f198-4459-8eb0-8b457e61f42e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106988317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.sram_ctrl_mem_partial_access.106988317
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.1382673979
Short name T414
Test name
Test status
Simulation time 37269722009 ps
CPU time 310.64 seconds
Started Dec 31 01:06:24 PM PST 23
Finished Dec 31 01:11:35 PM PST 23
Peak memory 202212 kb
Host smart-172dab22-1b7c-4d72-9d50-654cbcff8527
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382673979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.1382673979
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.1439858432
Short name T361
Test name
Test status
Simulation time 71627455865 ps
CPU time 1231.89 seconds
Started Dec 31 01:06:26 PM PST 23
Finished Dec 31 01:26:59 PM PST 23
Peak memory 381084 kb
Host smart-b3cb58ac-2a95-4ccf-b429-092765391a1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439858432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.1439858432
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.2495983039
Short name T614
Test name
Test status
Simulation time 952700274 ps
CPU time 16.3 seconds
Started Dec 31 01:06:19 PM PST 23
Finished Dec 31 01:06:39 PM PST 23
Peak memory 202068 kb
Host smart-f7d6fdc3-521b-4d1a-8247-f8cc1b1f6290
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495983039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.2495983039
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2739493938
Short name T471
Test name
Test status
Simulation time 6985934968 ps
CPU time 443.71 seconds
Started Dec 31 01:06:28 PM PST 23
Finished Dec 31 01:13:53 PM PST 23
Peak memory 201812 kb
Host smart-5cf6818d-f509-434f-b83f-d1dfd4200e87
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739493938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.2739493938
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.3740878348
Short name T567
Test name
Test status
Simulation time 742507560 ps
CPU time 5.35 seconds
Started Dec 31 01:06:18 PM PST 23
Finished Dec 31 01:06:27 PM PST 23
Peak memory 202404 kb
Host smart-7a89be31-9a90-4916-bf3a-2a1a7f680b2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740878348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3740878348
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.769383461
Short name T633
Test name
Test status
Simulation time 11497590776 ps
CPU time 1123.07 seconds
Started Dec 31 01:06:20 PM PST 23
Finished Dec 31 01:25:06 PM PST 23
Peak memory 373028 kb
Host smart-0f5dbb41-9874-402a-a53c-2b869c0e78fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769383461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.769383461
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.2765140576
Short name T654
Test name
Test status
Simulation time 1381022448 ps
CPU time 26.95 seconds
Started Dec 31 01:06:17 PM PST 23
Finished Dec 31 01:06:48 PM PST 23
Peak memory 202100 kb
Host smart-c06dc2cd-a768-4a1f-91a0-0035b6823681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765140576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2765140576
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.1993875935
Short name T400
Test name
Test status
Simulation time 28557268630 ps
CPU time 1637.19 seconds
Started Dec 31 01:06:05 PM PST 23
Finished Dec 31 01:33:31 PM PST 23
Peak memory 377092 kb
Host smart-a7c49639-5496-4957-a215-0e7bb2553379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993875935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.sram_ctrl_stress_all.1993875935
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2646492233
Short name T641
Test name
Test status
Simulation time 3417484864 ps
CPU time 5383.17 seconds
Started Dec 31 01:06:24 PM PST 23
Finished Dec 31 02:36:08 PM PST 23
Peak memory 697768 kb
Host smart-8f52ad95-72d3-4759-8fc2-664c56a9b252
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2646492233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.2646492233
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.717539411
Short name T107
Test name
Test status
Simulation time 5107370057 ps
CPU time 355.46 seconds
Started Dec 31 01:06:19 PM PST 23
Finished Dec 31 01:12:18 PM PST 23
Peak memory 202172 kb
Host smart-2f6bcf31-78cb-47e6-b067-2d033acc69e8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717539411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.sram_ctrl_stress_pipeline.717539411
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1978392795
Short name T362
Test name
Test status
Simulation time 1605397449 ps
CPU time 157.79 seconds
Started Dec 31 01:06:04 PM PST 23
Finished Dec 31 01:08:52 PM PST 23
Peak memory 374820 kb
Host smart-68a9fd8d-969e-434e-a20f-91578479a0f1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978392795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.1978392795
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2803936362
Short name T886
Test name
Test status
Simulation time 10721002893 ps
CPU time 1228.57 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 01:26:54 PM PST 23
Peak memory 380092 kb
Host smart-c5cf9bc4-e2ad-4646-bf23-d7495228dc3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803936362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.2803936362
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.3609863076
Short name T37
Test name
Test status
Simulation time 12237216 ps
CPU time 0.62 seconds
Started Dec 31 01:06:17 PM PST 23
Finished Dec 31 01:06:21 PM PST 23
Peak memory 201360 kb
Host smart-b52c4fb3-76e4-4221-93f6-f6ac6df4d8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609863076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.3609863076
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.3185751174
Short name T743
Test name
Test status
Simulation time 34336874396 ps
CPU time 2006.54 seconds
Started Dec 31 01:06:03 PM PST 23
Finished Dec 31 01:39:41 PM PST 23
Peak memory 202140 kb
Host smart-06bbf33b-8761-47a8-a06b-85f3a087dd52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185751174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.3185751174
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.3856307305
Short name T727
Test name
Test status
Simulation time 14142246409 ps
CPU time 81.46 seconds
Started Dec 31 01:06:20 PM PST 23
Finished Dec 31 01:07:44 PM PST 23
Peak memory 210364 kb
Host smart-8ed05e88-433d-4e4a-a2de-717771144886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856307305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.3856307305
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.675359954
Short name T524
Test name
Test status
Simulation time 1784344604 ps
CPU time 106.98 seconds
Started Dec 31 01:06:19 PM PST 23
Finished Dec 31 01:08:10 PM PST 23
Peak memory 341196 kb
Host smart-ece370b3-fda4-47cb-8847-11e1a3858d72
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675359954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.sram_ctrl_max_throughput.675359954
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2037044482
Short name T878
Test name
Test status
Simulation time 7048854041 ps
CPU time 136.61 seconds
Started Dec 31 01:06:05 PM PST 23
Finished Dec 31 01:08:31 PM PST 23
Peak memory 211076 kb
Host smart-3e3c2c3f-ddf4-4c5c-a686-d3b7759bfffd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037044482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.2037044482
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.774188634
Short name T463
Test name
Test status
Simulation time 15767188369 ps
CPU time 252.82 seconds
Started Dec 31 01:06:16 PM PST 23
Finished Dec 31 01:10:32 PM PST 23
Peak memory 202224 kb
Host smart-e432e38e-70ec-4d3c-8dcc-9eaa42c8d114
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774188634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl
_mem_walk.774188634
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.4209148328
Short name T786
Test name
Test status
Simulation time 38313714171 ps
CPU time 1071.33 seconds
Started Dec 31 01:06:31 PM PST 23
Finished Dec 31 01:24:23 PM PST 23
Peak memory 367900 kb
Host smart-0ff872f4-2bf3-4e85-83f0-113123817847
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209148328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.4209148328
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.4125273109
Short name T575
Test name
Test status
Simulation time 1723670205 ps
CPU time 36.58 seconds
Started Dec 31 01:06:01 PM PST 23
Finished Dec 31 01:06:43 PM PST 23
Peak memory 202096 kb
Host smart-a1fc0088-0d9d-4fd6-a48a-90e588a0460a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125273109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.4125273109
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.83011887
Short name T108
Test name
Test status
Simulation time 6753227000 ps
CPU time 424.61 seconds
Started Dec 31 01:06:20 PM PST 23
Finished Dec 31 01:13:27 PM PST 23
Peak memory 202104 kb
Host smart-de56f3b0-d48d-487f-a482-b5ecf73b5d59
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83011887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_partial_access_b2b.83011887
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.3381639531
Short name T326
Test name
Test status
Simulation time 1346324890 ps
CPU time 5.88 seconds
Started Dec 31 01:06:20 PM PST 23
Finished Dec 31 01:06:29 PM PST 23
Peak memory 202352 kb
Host smart-92f307d9-8655-4e7a-9c63-851d315fe203
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381639531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3381639531
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.100298380
Short name T323
Test name
Test status
Simulation time 18183741580 ps
CPU time 644.08 seconds
Started Dec 31 01:06:19 PM PST 23
Finished Dec 31 01:17:07 PM PST 23
Peak memory 352628 kb
Host smart-a4ed8653-4944-419f-b8f6-db14f19cb1cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100298380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.100298380
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.4004797889
Short name T672
Test name
Test status
Simulation time 2144898204 ps
CPU time 17.03 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 01:06:43 PM PST 23
Peak memory 202020 kb
Host smart-dc79c228-1910-4c87-937b-7fbfbaa46e75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004797889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.4004797889
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2954327544
Short name T754
Test name
Test status
Simulation time 1069646839 ps
CPU time 1390.24 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:29:39 PM PST 23
Peak memory 414020 kb
Host smart-460238a0-ea69-4919-a5dc-8d60bbfa75ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2954327544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.2954327544
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.999821077
Short name T974
Test name
Test status
Simulation time 4417530189 ps
CPU time 297.3 seconds
Started Dec 31 01:06:18 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 202092 kb
Host smart-cebff7f3-5900-43fe-91f3-1f1c86c4cff3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999821077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.sram_ctrl_stress_pipeline.999821077
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3092248122
Short name T36
Test name
Test status
Simulation time 2785262346 ps
CPU time 35.26 seconds
Started Dec 31 01:06:24 PM PST 23
Finished Dec 31 01:07:00 PM PST 23
Peak memory 241812 kb
Host smart-71bed076-af96-4ecb-9392-76bf3c9226a8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092248122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.3092248122
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3009496244
Short name T401
Test name
Test status
Simulation time 11353847306 ps
CPU time 1506.84 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:31:36 PM PST 23
Peak memory 379068 kb
Host smart-4eee4f03-ca38-4afd-b2a2-9f914bab7c5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009496244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.3009496244
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.3914578354
Short name T18
Test name
Test status
Simulation time 59894745 ps
CPU time 0.64 seconds
Started Dec 31 01:06:26 PM PST 23
Finished Dec 31 01:06:29 PM PST 23
Peak memory 201828 kb
Host smart-f7270bdd-63fd-425e-be5d-df9c02af7dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914578354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.3914578354
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.1140392611
Short name T387
Test name
Test status
Simulation time 150891707055 ps
CPU time 2466.92 seconds
Started Dec 31 01:06:04 PM PST 23
Finished Dec 31 01:47:21 PM PST 23
Peak memory 202116 kb
Host smart-70a90ed5-13ce-4141-bdb8-e1b8ab3f52bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140392611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.1140392611
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.3022186266
Short name T507
Test name
Test status
Simulation time 43415453949 ps
CPU time 101.27 seconds
Started Dec 31 01:06:03 PM PST 23
Finished Dec 31 01:07:55 PM PST 23
Peak memory 202096 kb
Host smart-2a95c166-b0b5-4c11-962e-691d5eadfa57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022186266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.3022186266
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.3239593177
Short name T876
Test name
Test status
Simulation time 721486047 ps
CPU time 31.98 seconds
Started Dec 31 01:06:18 PM PST 23
Finished Dec 31 01:06:53 PM PST 23
Peak memory 234724 kb
Host smart-80eca699-e506-4546-9acd-10e05cce6c33
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239593177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.3239593177
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1479878060
Short name T492
Test name
Test status
Simulation time 2366072092 ps
CPU time 71.57 seconds
Started Dec 31 01:06:26 PM PST 23
Finished Dec 31 01:07:39 PM PST 23
Peak memory 211220 kb
Host smart-7b6123a0-01f0-4745-8768-e43c834ad328
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479878060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.1479878060
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.3839305392
Short name T675
Test name
Test status
Simulation time 38363876289 ps
CPU time 150.85 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:09:21 PM PST 23
Peak memory 202100 kb
Host smart-89e4a92f-ce9d-4902-b611-52ff0c7797d9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839305392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.3839305392
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.2952992496
Short name T493
Test name
Test status
Simulation time 79835811958 ps
CPU time 1117.65 seconds
Started Dec 31 01:06:04 PM PST 23
Finished Dec 31 01:24:52 PM PST 23
Peak memory 380088 kb
Host smart-49a81b39-ef72-41c2-b7d2-d3ddb9047034
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952992496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.2952992496
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.3464993423
Short name T896
Test name
Test status
Simulation time 1129293258 ps
CPU time 70.64 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:08:01 PM PST 23
Peak memory 322688 kb
Host smart-296cb646-8391-4a0f-afd3-b0c6a5736d1a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464993423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.3464993423
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.436274894
Short name T962
Test name
Test status
Simulation time 65493545046 ps
CPU time 353.42 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:12:22 PM PST 23
Peak memory 202132 kb
Host smart-be184358-eece-43b4-8b7e-f122a7db38e3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436274894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.sram_ctrl_partial_access_b2b.436274894
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.2114290843
Short name T376
Test name
Test status
Simulation time 1348972900 ps
CPU time 7.18 seconds
Started Dec 31 01:06:28 PM PST 23
Finished Dec 31 01:06:36 PM PST 23
Peak memory 202092 kb
Host smart-52d51f56-f914-46ba-81be-ef29a9a8bb6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114290843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2114290843
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.1211927366
Short name T861
Test name
Test status
Simulation time 1583273558 ps
CPU time 172.03 seconds
Started Dec 31 01:06:26 PM PST 23
Finished Dec 31 01:09:20 PM PST 23
Peak memory 368832 kb
Host smart-6f5a56d7-353c-4858-bf31-a7e99ccf70ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211927366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1211927366
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.2189088882
Short name T495
Test name
Test status
Simulation time 456088444 ps
CPU time 143.12 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:08:51 PM PST 23
Peak memory 374892 kb
Host smart-77613567-1836-496a-aba4-cb85887b04d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189088882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2189088882
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.587689187
Short name T330
Test name
Test status
Simulation time 2159284977 ps
CPU time 2037.19 seconds
Started Dec 31 01:06:26 PM PST 23
Finished Dec 31 01:40:25 PM PST 23
Peak memory 483776 kb
Host smart-dc98106c-2c51-4fbf-ba1f-b64ae459631e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=587689187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.587689187
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.717617750
Short name T735
Test name
Test status
Simulation time 7428037937 ps
CPU time 277.28 seconds
Started Dec 31 01:06:21 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 202076 kb
Host smart-b61c7008-9fac-4571-a138-4c32718e1bb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717617750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.sram_ctrl_stress_pipeline.717617750
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1055603694
Short name T934
Test name
Test status
Simulation time 3830590452 ps
CPU time 63.09 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 01:07:29 PM PST 23
Peak memory 288128 kb
Host smart-933653c6-9a03-4946-bcd4-fe465fc4b7af
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055603694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1055603694
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2195346469
Short name T478
Test name
Test status
Simulation time 9011077277 ps
CPU time 559.95 seconds
Started Dec 31 01:06:22 PM PST 23
Finished Dec 31 01:15:44 PM PST 23
Peak memory 358984 kb
Host smart-396dcc2f-a8a9-45b7-b9ff-41a17e5df908
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195346469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.2195346469
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.2913716949
Short name T410
Test name
Test status
Simulation time 46964111 ps
CPU time 0.66 seconds
Started Dec 31 01:06:21 PM PST 23
Finished Dec 31 01:06:24 PM PST 23
Peak memory 201340 kb
Host smart-a212dcac-fdfb-41e6-b6c5-f15d2f2d5155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913716949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.2913716949
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.3570823034
Short name T840
Test name
Test status
Simulation time 231565510828 ps
CPU time 739.76 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:18:48 PM PST 23
Peak memory 202140 kb
Host smart-fa39948c-f1a6-4c1c-a735-81bbd866775f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570823034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.3570823034
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.1608166710
Short name T737
Test name
Test status
Simulation time 36660766557 ps
CPU time 612.06 seconds
Started Dec 31 01:06:19 PM PST 23
Finished Dec 31 01:16:34 PM PST 23
Peak memory 371820 kb
Host smart-6dd82cce-3d3b-4cd8-a558-5758cc1f9e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608166710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.1608166710
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.332945281
Short name T124
Test name
Test status
Simulation time 9129971426 ps
CPU time 107.64 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 01:08:14 PM PST 23
Peak memory 213564 kb
Host smart-6c389ade-dc50-42ab-bf4f-0db578656b78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332945281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esc
alation.332945281
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.4070665167
Short name T891
Test name
Test status
Simulation time 1530209910 ps
CPU time 163.66 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:09:34 PM PST 23
Peak memory 365664 kb
Host smart-9e44cee4-3377-447e-87e2-ca0afd74a404
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070665167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.4070665167
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3190836017
Short name T451
Test name
Test status
Simulation time 5050151150 ps
CPU time 147.76 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:09:18 PM PST 23
Peak memory 213452 kb
Host smart-08574a85-50b4-4e06-8390-156cf01c2199
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190836017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.3190836017
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.549714651
Short name T455
Test name
Test status
Simulation time 7898555315 ps
CPU time 125.32 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:08:55 PM PST 23
Peak memory 202236 kb
Host smart-cb9f7027-e66b-4652-a0f2-e8dcb3c7d3a5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549714651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl
_mem_walk.549714651
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.3637651719
Short name T566
Test name
Test status
Simulation time 110516290630 ps
CPU time 619.99 seconds
Started Dec 31 01:06:18 PM PST 23
Finished Dec 31 01:16:42 PM PST 23
Peak memory 341248 kb
Host smart-ba64ca95-e978-4ac5-8600-069ebd0815ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637651719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.3637651719
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.2954491529
Short name T528
Test name
Test status
Simulation time 2872002955 ps
CPU time 37.08 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 01:07:03 PM PST 23
Peak memory 244608 kb
Host smart-ce6c043c-6812-4f31-a999-97ae357a1b17
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954491529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.2954491529
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3378415371
Short name T553
Test name
Test status
Simulation time 12261017533 ps
CPU time 322.5 seconds
Started Dec 31 01:06:23 PM PST 23
Finished Dec 31 01:11:47 PM PST 23
Peak memory 202180 kb
Host smart-31b34562-805b-4d16-a2b8-0501b438fe30
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378415371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.3378415371
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.2821000459
Short name T452
Test name
Test status
Simulation time 969520072 ps
CPU time 5.85 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 01:06:32 PM PST 23
Peak memory 202376 kb
Host smart-5ce0baa3-b865-4e40-aeab-ee160be5e614
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821000459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2821000459
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.2248426700
Short name T938
Test name
Test status
Simulation time 1689128060 ps
CPU time 630.34 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 01:16:57 PM PST 23
Peak memory 379160 kb
Host smart-6c7cf27a-da58-4251-a5e1-25e5d9a4c24c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248426700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2248426700
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.925201667
Short name T753
Test name
Test status
Simulation time 1320713724 ps
CPU time 23.26 seconds
Started Dec 31 01:06:22 PM PST 23
Finished Dec 31 01:06:47 PM PST 23
Peak memory 202068 kb
Host smart-81a569c1-76a1-4126-acfb-0a5ad3c8cc97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925201667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.925201667
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.45465246
Short name T678
Test name
Test status
Simulation time 602280831010 ps
CPU time 4597.56 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 02:23:06 PM PST 23
Peak memory 381152 kb
Host smart-bd7f48b3-837a-4fcc-b3a3-f34f40b0b425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45465246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.sram_ctrl_stress_all.45465246
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3497362208
Short name T774
Test name
Test status
Simulation time 1314470011 ps
CPU time 2619.75 seconds
Started Dec 31 01:06:45 PM PST 23
Finished Dec 31 01:50:31 PM PST 23
Peak memory 437052 kb
Host smart-f0de46c0-655a-4338-8ed4-63cfc4b17f04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3497362208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3497362208
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1283397789
Short name T393
Test name
Test status
Simulation time 39387573975 ps
CPU time 333.5 seconds
Started Dec 31 01:06:20 PM PST 23
Finished Dec 31 01:11:56 PM PST 23
Peak memory 202036 kb
Host smart-0c23716a-6c4e-4a01-bd3a-d2dc8a5f19a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283397789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.1283397789
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3395989382
Short name T747
Test name
Test status
Simulation time 743904431 ps
CPU time 65.65 seconds
Started Dec 31 01:06:26 PM PST 23
Finished Dec 31 01:07:33 PM PST 23
Peak memory 294236 kb
Host smart-987b8b0c-ef66-4d8e-802e-53b8289f73ff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395989382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.3395989382
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.1389187344
Short name T543
Test name
Test status
Simulation time 21149564 ps
CPU time 0.64 seconds
Started Dec 31 01:06:45 PM PST 23
Finished Dec 31 01:06:52 PM PST 23
Peak memory 201408 kb
Host smart-783f503c-9a9b-4f70-86a8-d40506ac866e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389187344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.1389187344
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.2035934843
Short name T126
Test name
Test status
Simulation time 49524662474 ps
CPU time 377.53 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:12:46 PM PST 23
Peak memory 353652 kb
Host smart-0f97f596-0b51-46b5-9201-d991bdaca637
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035934843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.2035934843
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.1838619157
Short name T115
Test name
Test status
Simulation time 11375525218 ps
CPU time 120.35 seconds
Started Dec 31 01:06:41 PM PST 23
Finished Dec 31 01:08:48 PM PST 23
Peak memory 210384 kb
Host smart-42824e1b-d204-4811-9e94-951b9038fd63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838619157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.1838619157
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.581560304
Short name T749
Test name
Test status
Simulation time 4930085507 ps
CPU time 95.06 seconds
Started Dec 31 01:06:17 PM PST 23
Finished Dec 31 01:07:56 PM PST 23
Peak memory 331024 kb
Host smart-8998a1cc-956f-4fca-b286-a3350fb80a82
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581560304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.sram_ctrl_max_throughput.581560304
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.4082324526
Short name T838
Test name
Test status
Simulation time 18252954571 ps
CPU time 153.28 seconds
Started Dec 31 01:06:41 PM PST 23
Finished Dec 31 01:09:23 PM PST 23
Peak memory 214736 kb
Host smart-bc7439c8-5b24-4fee-a4e5-0e20546ee007
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082324526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.4082324526
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.2183199816
Short name T365
Test name
Test status
Simulation time 28657925582 ps
CPU time 297.9 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:11:48 PM PST 23
Peak memory 202292 kb
Host smart-5baba329-51ce-4a07-81ff-acb7353965f3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183199816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.2183199816
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.332849608
Short name T535
Test name
Test status
Simulation time 52922012243 ps
CPU time 1006.64 seconds
Started Dec 31 01:06:26 PM PST 23
Finished Dec 31 01:23:15 PM PST 23
Peak memory 379888 kb
Host smart-c8d219ff-45f5-4c3a-9a2d-ec7f89e0e6e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332849608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip
le_keys.332849608
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.3562672147
Short name T568
Test name
Test status
Simulation time 4087765365 ps
CPU time 30.57 seconds
Started Dec 31 01:06:18 PM PST 23
Finished Dec 31 01:06:52 PM PST 23
Peak memory 202072 kb
Host smart-b072d937-2a0f-42fd-b5bc-27595986add7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562672147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.3562672147
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.336249857
Short name T594
Test name
Test status
Simulation time 8822253841 ps
CPU time 568.32 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 01:15:54 PM PST 23
Peak memory 202160 kb
Host smart-76812d31-e02a-41ca-bfe7-d9d415c3ff51
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336249857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.sram_ctrl_partial_access_b2b.336249857
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.3236246646
Short name T283
Test name
Test status
Simulation time 366506690 ps
CPU time 13.44 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:07:04 PM PST 23
Peak memory 202360 kb
Host smart-464e9bf3-321a-4dff-84f6-27ad3038b6f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236246646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3236246646
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.3406060038
Short name T825
Test name
Test status
Simulation time 587111369 ps
CPU time 10.24 seconds
Started Dec 31 01:06:45 PM PST 23
Finished Dec 31 01:07:01 PM PST 23
Peak memory 202028 kb
Host smart-ab2b7519-3d30-4f6f-a3e6-c1ac30034ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406060038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3406060038
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3988417956
Short name T223
Test name
Test status
Simulation time 1127975053 ps
CPU time 3236.9 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 02:00:23 PM PST 23
Peak memory 632724 kb
Host smart-44fc9cbe-0257-472b-b0d6-678eed7ce848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3988417956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3988417956
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2454841726
Short name T596
Test name
Test status
Simulation time 8860184108 ps
CPU time 322.98 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:12:13 PM PST 23
Peak memory 202168 kb
Host smart-184f2ade-ed6f-4412-ab6d-8eb1f1a6ec4a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454841726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.2454841726
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3657400548
Short name T319
Test name
Test status
Simulation time 1591122199 ps
CPU time 96.61 seconds
Started Dec 31 01:06:25 PM PST 23
Finished Dec 31 01:08:03 PM PST 23
Peak memory 344104 kb
Host smart-b51afbbc-9211-4f17-aa0d-2319b1193f1d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657400548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3657400548
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.676710852
Short name T479
Test name
Test status
Simulation time 47977375013 ps
CPU time 1305.19 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:28:35 PM PST 23
Peak memory 377024 kb
Host smart-8df1ede0-db86-4021-ae58-a0eaaff027c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676710852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.sram_ctrl_access_during_key_req.676710852
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.3894157669
Short name T289
Test name
Test status
Simulation time 25063668 ps
CPU time 0.65 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:06:51 PM PST 23
Peak memory 201912 kb
Host smart-8fcbf97e-a411-477f-af29-f7292096e1e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894157669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.3894157669
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.3483911329
Short name T757
Test name
Test status
Simulation time 335287939329 ps
CPU time 1661.85 seconds
Started Dec 31 01:06:48 PM PST 23
Finished Dec 31 01:34:38 PM PST 23
Peak memory 202140 kb
Host smart-55dc7a36-6601-4744-a0cf-b7c4e96eaa7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483911329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.3483911329
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.4006833649
Short name T130
Test name
Test status
Simulation time 116466407851 ps
CPU time 1677.96 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:34:48 PM PST 23
Peak memory 380076 kb
Host smart-34e465b9-3dc2-4e7e-9fce-70f7bc6902e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006833649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.4006833649
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.3771282279
Short name T973
Test name
Test status
Simulation time 25425179160 ps
CPU time 119.96 seconds
Started Dec 31 01:06:45 PM PST 23
Finished Dec 31 01:08:51 PM PST 23
Peak memory 210312 kb
Host smart-eed22d4f-939d-4719-a9ee-f68fc4e91b1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771282279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.3771282279
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.1815335609
Short name T731
Test name
Test status
Simulation time 1995547510 ps
CPU time 107.77 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:08:38 PM PST 23
Peak memory 328764 kb
Host smart-58471c88-6433-4256-8c6c-19b8ce45b1b1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815335609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.1815335609
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2785378907
Short name T902
Test name
Test status
Simulation time 1931298380 ps
CPU time 73.15 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:08:03 PM PST 23
Peak memory 210496 kb
Host smart-2402fff9-ad14-41cd-8138-d2dde0ef9cb0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785378907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.2785378907
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.959234267
Short name T634
Test name
Test status
Simulation time 4333654638 ps
CPU time 262.13 seconds
Started Dec 31 01:06:45 PM PST 23
Finished Dec 31 01:11:13 PM PST 23
Peak memory 202124 kb
Host smart-b428dfc2-e25f-41c8-83a6-ff47166b5c5e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959234267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl
_mem_walk.959234267
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.1101862132
Short name T870
Test name
Test status
Simulation time 26309756813 ps
CPU time 235.31 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 269896 kb
Host smart-315309f2-91ff-44f1-8596-dd54710661c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101862132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.1101862132
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.2998660946
Short name T310
Test name
Test status
Simulation time 938132267 ps
CPU time 23.02 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:07:13 PM PST 23
Peak memory 248044 kb
Host smart-50b3abc5-7db9-40a1-846b-66386d73cbf2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998660946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.2998660946
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1130993828
Short name T729
Test name
Test status
Simulation time 122930962591 ps
CPU time 374.93 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:13:05 PM PST 23
Peak memory 202084 kb
Host smart-e1a3ba2c-1977-4090-9575-7466a441505f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130993828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.1130993828
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.1168228752
Short name T32
Test name
Test status
Simulation time 345742108 ps
CPU time 6.32 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:06:56 PM PST 23
Peak memory 202340 kb
Host smart-5b808d43-1710-43d0-9065-090cce1afb87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168228752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1168228752
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.4022753151
Short name T577
Test name
Test status
Simulation time 14390134707 ps
CPU time 1389.71 seconds
Started Dec 31 01:06:45 PM PST 23
Finished Dec 31 01:30:01 PM PST 23
Peak memory 369104 kb
Host smart-7b7c0ab1-b4f7-4bbd-b70e-2101f6b518ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022753151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.4022753151
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.3234634123
Short name T811
Test name
Test status
Simulation time 744365748 ps
CPU time 59.55 seconds
Started Dec 31 01:06:23 PM PST 23
Finished Dec 31 01:07:24 PM PST 23
Peak memory 307324 kb
Host smart-2a9ed752-5636-466a-a72f-28c4847e71cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234634123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3234634123
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2782809888
Short name T402
Test name
Test status
Simulation time 1550195992 ps
CPU time 3016.25 seconds
Started Dec 31 01:06:28 PM PST 23
Finished Dec 31 01:56:46 PM PST 23
Peak memory 789744 kb
Host smart-048d3fa8-4da8-42f8-93d5-bd7b58d3831d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2782809888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2782809888
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1374779581
Short name T259
Test name
Test status
Simulation time 4339058705 ps
CPU time 312.67 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:12:03 PM PST 23
Peak memory 202200 kb
Host smart-cc256fc9-9536-46fe-9ce6-be400176819a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374779581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.1374779581
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3607022907
Short name T243
Test name
Test status
Simulation time 3556024023 ps
CPU time 105.66 seconds
Started Dec 31 01:06:45 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 364352 kb
Host smart-29557398-0868-4b18-bbaf-5da664e03300
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607022907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.3607022907
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.657260832
Short name T739
Test name
Test status
Simulation time 815565665 ps
CPU time 109.29 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:08:39 PM PST 23
Peak memory 337032 kb
Host smart-74b53ea6-a9e8-4f07-944e-8a72e60b82a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657260832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 48.sram_ctrl_access_during_key_req.657260832
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.3095525380
Short name T721
Test name
Test status
Simulation time 93968117 ps
CPU time 0.64 seconds
Started Dec 31 01:06:46 PM PST 23
Finished Dec 31 01:06:52 PM PST 23
Peak memory 201864 kb
Host smart-2d7d5bf3-ca16-4a14-a853-37ab32b59d9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095525380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.3095525380
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.65674261
Short name T769
Test name
Test status
Simulation time 14926807724 ps
CPU time 972.84 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:23:03 PM PST 23
Peak memory 202128 kb
Host smart-3fc63e25-32df-4eab-a53e-8d20c19b4821
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65674261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.65674261
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.3026860455
Short name T805
Test name
Test status
Simulation time 12441569414 ps
CPU time 228.12 seconds
Started Dec 31 01:06:46 PM PST 23
Finished Dec 31 01:10:42 PM PST 23
Peak memory 210244 kb
Host smart-00368ef4-91fc-4cb9-820e-7aee77e45bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026860455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.3026860455
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.4277632440
Short name T761
Test name
Test status
Simulation time 1530053086 ps
CPU time 143.77 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:09:14 PM PST 23
Peak memory 365656 kb
Host smart-cf8b784d-0b43-4b28-9161-f390b88eac23
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277632440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.4277632440
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2291229271
Short name T590
Test name
Test status
Simulation time 8921968491 ps
CPU time 160.69 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:09:31 PM PST 23
Peak memory 218508 kb
Host smart-15f090cf-917e-42f0-b35a-f4f878cdbc2d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291229271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.2291229271
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.3713918954
Short name T502
Test name
Test status
Simulation time 30311168031 ps
CPU time 258.82 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:11:09 PM PST 23
Peak memory 202136 kb
Host smart-9b5527c4-f7d6-433d-83ad-984cf3e5b211
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713918954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.3713918954
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.3071560478
Short name T638
Test name
Test status
Simulation time 9674830561 ps
CPU time 287.15 seconds
Started Dec 31 01:06:50 PM PST 23
Finished Dec 31 01:11:44 PM PST 23
Peak memory 354568 kb
Host smart-4c43c4f1-bb6d-4589-8d62-a8a2954b8ec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071560478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.3071560478
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.2594445303
Short name T291
Test name
Test status
Simulation time 4212886178 ps
CPU time 77.29 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:07:45 PM PST 23
Peak memory 315636 kb
Host smart-6121f70f-ae1d-4961-a4bf-1c95db797bef
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594445303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.2594445303
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2152457775
Short name T565
Test name
Test status
Simulation time 4736300272 ps
CPU time 293.74 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:11:44 PM PST 23
Peak memory 202160 kb
Host smart-b6d1aec3-2134-42c8-a631-85836642d69a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152457775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.2152457775
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.1698453089
Short name T631
Test name
Test status
Simulation time 394688980 ps
CPU time 6.71 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:06:57 PM PST 23
Peak memory 202456 kb
Host smart-2a853403-6d16-4a3a-9713-3796368b114d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698453089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1698453089
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.2830182696
Short name T955
Test name
Test status
Simulation time 6858168453 ps
CPU time 1062.14 seconds
Started Dec 31 01:06:26 PM PST 23
Finished Dec 31 01:24:10 PM PST 23
Peak memory 379088 kb
Host smart-31bbdbc0-11f7-4f02-a77f-53819fe707e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830182696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2830182696
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.1466954227
Short name T853
Test name
Test status
Simulation time 425894169 ps
CPU time 66.71 seconds
Started Dec 31 01:06:27 PM PST 23
Finished Dec 31 01:07:35 PM PST 23
Peak memory 308508 kb
Host smart-05794c38-7f44-497e-b901-636add34ac0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466954227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1466954227
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.1726070615
Short name T826
Test name
Test status
Simulation time 136707048623 ps
CPU time 4546.65 seconds
Started Dec 31 01:06:45 PM PST 23
Finished Dec 31 02:22:38 PM PST 23
Peak memory 382196 kb
Host smart-f329bb24-5d12-4de2-93e5-b4df8168a1e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726070615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.1726070615
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1065907365
Short name T348
Test name
Test status
Simulation time 2114237172 ps
CPU time 4734.37 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 02:25:45 PM PST 23
Peak memory 529228 kb
Host smart-e2b013d1-3645-4588-80f2-59656f7e98d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1065907365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1065907365
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3134075673
Short name T889
Test name
Test status
Simulation time 2313676972 ps
CPU time 182.88 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 202120 kb
Host smart-7ae28154-0764-436f-a871-9ebb26ed6c65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134075673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.3134075673
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1074582904
Short name T506
Test name
Test status
Simulation time 1580312611 ps
CPU time 87.27 seconds
Started Dec 31 01:06:41 PM PST 23
Finished Dec 31 01:08:17 PM PST 23
Peak memory 324868 kb
Host smart-22f592c7-2d0b-42d7-9c9d-6d8c350ed703
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074582904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1074582904
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1376858347
Short name T81
Test name
Test status
Simulation time 8143128339 ps
CPU time 734.34 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:19:05 PM PST 23
Peak memory 380064 kb
Host smart-8247dced-98f6-4612-913f-48e74ad499b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376858347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.1376858347
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.1719809700
Short name T369
Test name
Test status
Simulation time 13760857 ps
CPU time 0.62 seconds
Started Dec 31 01:06:48 PM PST 23
Finished Dec 31 01:06:57 PM PST 23
Peak memory 201368 kb
Host smart-a34275e1-46cb-4b5e-a62a-9cef5149958e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719809700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.1719809700
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.1518977771
Short name T576
Test name
Test status
Simulation time 250015021526 ps
CPU time 1407.99 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:30:18 PM PST 23
Peak memory 202200 kb
Host smart-24a448d0-3ea9-4d10-a8d0-368205287c95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518977771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.1518977771
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.1956263053
Short name T740
Test name
Test status
Simulation time 19226996061 ps
CPU time 105.04 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:08:35 PM PST 23
Peak memory 202108 kb
Host smart-15d968dc-2df0-4215-bc44-882b528b32a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956263053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.1956263053
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.1124014047
Short name T711
Test name
Test status
Simulation time 746931547 ps
CPU time 85.66 seconds
Started Dec 31 01:06:41 PM PST 23
Finished Dec 31 01:08:14 PM PST 23
Peak memory 325864 kb
Host smart-c6dce5a6-c414-4c24-9cde-be55ed827836
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124014047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.1124014047
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.17526198
Short name T837
Test name
Test status
Simulation time 18986845350 ps
CPU time 151.39 seconds
Started Dec 31 01:06:46 PM PST 23
Finished Dec 31 01:09:23 PM PST 23
Peak memory 218472 kb
Host smart-308b4af9-e05a-46b5-8f27-b5d375649462
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17526198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_mem_partial_access.17526198
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.2678014047
Short name T281
Test name
Test status
Simulation time 3945807864 ps
CPU time 250.31 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 202020 kb
Host smart-9b8abba0-7b41-4550-bdb1-210168ad5635
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678014047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.2678014047
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.1397608342
Short name T561
Test name
Test status
Simulation time 12913610519 ps
CPU time 909.93 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:22:00 PM PST 23
Peak memory 379096 kb
Host smart-4b2376be-beea-4062-ab62-849d58d329e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397608342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.1397608342
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.1608513945
Short name T545
Test name
Test status
Simulation time 1588595382 ps
CPU time 27.37 seconds
Started Dec 31 01:06:41 PM PST 23
Finished Dec 31 01:07:17 PM PST 23
Peak memory 202016 kb
Host smart-697afbe8-ac9a-4c4a-952b-90fae62775c6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608513945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.1608513945
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1130539009
Short name T598
Test name
Test status
Simulation time 112217786426 ps
CPU time 452.13 seconds
Started Dec 31 01:06:43 PM PST 23
Finished Dec 31 01:14:22 PM PST 23
Peak memory 202128 kb
Host smart-ffe54648-e257-4f67-bdae-827eb9dcc0aa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130539009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.1130539009
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.802005859
Short name T772
Test name
Test status
Simulation time 1458833157 ps
CPU time 13.19 seconds
Started Dec 31 01:06:46 PM PST 23
Finished Dec 31 01:07:06 PM PST 23
Peak memory 202384 kb
Host smart-1a6f3054-499c-499a-94ff-8f81e2bf3612
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802005859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.802005859
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.3618026463
Short name T128
Test name
Test status
Simulation time 8641795940 ps
CPU time 981.88 seconds
Started Dec 31 01:06:45 PM PST 23
Finished Dec 31 01:23:13 PM PST 23
Peak memory 372892 kb
Host smart-a30aa98c-4036-47b4-9389-ffb46459f18d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618026463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3618026463
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.3321311697
Short name T623
Test name
Test status
Simulation time 3511049589 ps
CPU time 22.6 seconds
Started Dec 31 01:06:42 PM PST 23
Finished Dec 31 01:07:13 PM PST 23
Peak memory 234876 kb
Host smart-0b8248d4-497a-43e1-8665-ecc4fdba8365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321311697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3321311697
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.105687938
Short name T808
Test name
Test status
Simulation time 1029907390921 ps
CPU time 5325.66 seconds
Started Dec 31 01:06:46 PM PST 23
Finished Dec 31 02:35:39 PM PST 23
Peak memory 377092 kb
Host smart-437ccee6-82e5-48a5-a1c2-4c0bb8cd6bfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105687938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_stress_all.105687938
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4200582765
Short name T692
Test name
Test status
Simulation time 1001956830 ps
CPU time 2679.21 seconds
Started Dec 31 01:06:41 PM PST 23
Finished Dec 31 01:51:29 PM PST 23
Peak memory 601912 kb
Host smart-3eba834d-fa74-4a4e-b3c2-8bd7822740c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4200582765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.4200582765
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.970458381
Short name T627
Test name
Test status
Simulation time 4617808680 ps
CPU time 334.85 seconds
Started Dec 31 01:06:41 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 202072 kb
Host smart-1346bc25-83f1-432b-9eb6-c63947d07bf1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970458381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_stress_pipeline.970458381
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2668364483
Short name T629
Test name
Test status
Simulation time 3067201790 ps
CPU time 137.49 seconds
Started Dec 31 01:06:44 PM PST 23
Finished Dec 31 01:09:08 PM PST 23
Peak memory 350492 kb
Host smart-7be41b24-21f6-4843-9cc2-801873ccf55b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668364483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2668364483
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1393362631
Short name T225
Test name
Test status
Simulation time 73248839113 ps
CPU time 976.89 seconds
Started Dec 31 01:03:54 PM PST 23
Finished Dec 31 01:20:12 PM PST 23
Peak memory 379064 kb
Host smart-cf6b3b5d-9892-4e2c-8495-956b2fcc0894
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393362631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.1393362631
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.2553671348
Short name T486
Test name
Test status
Simulation time 15517729 ps
CPU time 0.65 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:04:28 PM PST 23
Peak memory 201832 kb
Host smart-43611803-1115-4945-b009-77bd4ce3e52a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553671348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.2553671348
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.1481760605
Short name T883
Test name
Test status
Simulation time 136606883451 ps
CPU time 2107.66 seconds
Started Dec 31 01:04:03 PM PST 23
Finished Dec 31 01:39:12 PM PST 23
Peak memory 202100 kb
Host smart-e8d7d966-ee38-45f3-980c-b4789dbc71d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481760605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
1481760605
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.2788242536
Short name T776
Test name
Test status
Simulation time 92315044070 ps
CPU time 1612.06 seconds
Started Dec 31 01:04:07 PM PST 23
Finished Dec 31 01:31:00 PM PST 23
Peak memory 379024 kb
Host smart-94524f48-4f7e-42fe-a132-1d58fe4a7bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788242536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.2788242536
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.2149471632
Short name T341
Test name
Test status
Simulation time 11027202968 ps
CPU time 255.04 seconds
Started Dec 31 01:03:53 PM PST 23
Finished Dec 31 01:08:09 PM PST 23
Peak memory 210396 kb
Host smart-fa22b5a8-af51-4756-9ec8-7b06adc02dad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149471632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.2149471632
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.2794112739
Short name T696
Test name
Test status
Simulation time 687814590 ps
CPU time 27.73 seconds
Started Dec 31 01:04:03 PM PST 23
Finished Dec 31 01:04:32 PM PST 23
Peak memory 217480 kb
Host smart-c47b8607-d41d-4258-9a7a-6d3e1344fdc8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794112739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.2794112739
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1619455617
Short name T706
Test name
Test status
Simulation time 3259732180 ps
CPU time 134.04 seconds
Started Dec 31 01:04:10 PM PST 23
Finished Dec 31 01:06:25 PM PST 23
Peak memory 211124 kb
Host smart-866a7940-78fb-4651-9d2b-aef90d84fb3b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619455617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.1619455617
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.1111300921
Short name T765
Test name
Test status
Simulation time 7094415054 ps
CPU time 151.64 seconds
Started Dec 31 01:04:34 PM PST 23
Finished Dec 31 01:07:09 PM PST 23
Peak memory 202248 kb
Host smart-d4697239-25af-4383-af90-156fc0ec3eb7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111300921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.1111300921
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.3199873402
Short name T693
Test name
Test status
Simulation time 6583064592 ps
CPU time 154.57 seconds
Started Dec 31 01:03:58 PM PST 23
Finished Dec 31 01:06:34 PM PST 23
Peak memory 345796 kb
Host smart-89817086-b6df-417e-b8eb-face6e3fdf7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199873402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.3199873402
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.312647026
Short name T407
Test name
Test status
Simulation time 4910344584 ps
CPU time 45.16 seconds
Started Dec 31 01:03:59 PM PST 23
Finished Dec 31 01:04:45 PM PST 23
Peak memory 202064 kb
Host smart-c92f2f6f-9cb1-451a-bd4f-e22c6ffeb8be
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312647026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sr
am_ctrl_partial_access.312647026
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.666424208
Short name T249
Test name
Test status
Simulation time 5665135432 ps
CPU time 341.61 seconds
Started Dec 31 01:04:10 PM PST 23
Finished Dec 31 01:09:54 PM PST 23
Peak memory 202176 kb
Host smart-e4e7a07d-0d83-446f-a88f-39c738c22dee
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666424208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.sram_ctrl_partial_access_b2b.666424208
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.422430371
Short name T351
Test name
Test status
Simulation time 347149351 ps
CPU time 13.26 seconds
Started Dec 31 01:04:24 PM PST 23
Finished Dec 31 01:04:39 PM PST 23
Peak memory 202424 kb
Host smart-042157c9-b5e0-423b-ba48-f5b5e1ddd298
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422430371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.422430371
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.2718476161
Short name T123
Test name
Test status
Simulation time 7880025183 ps
CPU time 431.16 seconds
Started Dec 31 01:04:35 PM PST 23
Finished Dec 31 01:11:50 PM PST 23
Peak memory 370860 kb
Host smart-7187320d-c8a8-498c-a7d8-7598ea671cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718476161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2718476161
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.268527830
Short name T624
Test name
Test status
Simulation time 4274535847 ps
CPU time 24.21 seconds
Started Dec 31 01:04:11 PM PST 23
Finished Dec 31 01:04:37 PM PST 23
Peak memory 202116 kb
Host smart-65e78ae1-2fa8-4c93-9911-cbe4210ffa8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268527830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.268527830
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2974352093
Short name T12
Test name
Test status
Simulation time 873549738 ps
CPU time 2269.4 seconds
Started Dec 31 01:04:06 PM PST 23
Finished Dec 31 01:41:56 PM PST 23
Peak memory 696260 kb
Host smart-573d00c1-b578-4903-9c9e-b3200bad732a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2974352093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2974352093
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1876884515
Short name T977
Test name
Test status
Simulation time 17459868301 ps
CPU time 363.99 seconds
Started Dec 31 01:03:57 PM PST 23
Finished Dec 31 01:10:02 PM PST 23
Peak memory 202080 kb
Host smart-44edb692-6659-43d4-a36e-5e73ad7a13cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876884515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.1876884515
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1961728026
Short name T750
Test name
Test status
Simulation time 787771404 ps
CPU time 53.28 seconds
Started Dec 31 01:04:10 PM PST 23
Finished Dec 31 01:05:05 PM PST 23
Peak memory 290088 kb
Host smart-e0a5c4a8-4c28-41d6-837a-16c16d78ce84
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961728026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1961728026
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1873411854
Short name T712
Test name
Test status
Simulation time 4343205673 ps
CPU time 473.69 seconds
Started Dec 31 01:03:48 PM PST 23
Finished Dec 31 01:11:43 PM PST 23
Peak memory 374516 kb
Host smart-51794143-4414-47fb-8977-f4950929a1c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873411854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.1873411854
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.2533292515
Short name T245
Test name
Test status
Simulation time 27351963 ps
CPU time 0.63 seconds
Started Dec 31 01:04:08 PM PST 23
Finished Dec 31 01:04:10 PM PST 23
Peak memory 201460 kb
Host smart-fcd9ac36-b844-4840-b1fe-04e9b769f64f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533292515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.2533292515
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.845075631
Short name T582
Test name
Test status
Simulation time 73034061561 ps
CPU time 1103.34 seconds
Started Dec 31 01:04:10 PM PST 23
Finished Dec 31 01:22:36 PM PST 23
Peak memory 202100 kb
Host smart-78e69d9e-02f5-4c2d-9544-5194d09f809c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845075631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.845075631
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.786688705
Short name T864
Test name
Test status
Simulation time 11037789898 ps
CPU time 191.55 seconds
Started Dec 31 01:04:20 PM PST 23
Finished Dec 31 01:07:33 PM PST 23
Peak memory 346844 kb
Host smart-71de1c0e-0da0-4ea4-93b8-ce75c6070c48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786688705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable
.786688705
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.2628324127
Short name T279
Test name
Test status
Simulation time 2066222920 ps
CPU time 165.99 seconds
Started Dec 31 01:03:52 PM PST 23
Finished Dec 31 01:06:39 PM PST 23
Peak memory 366724 kb
Host smart-d17fa3af-56fc-411e-9d7b-0b9e9f64c891
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628324127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.2628324127
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2341098068
Short name T254
Test name
Test status
Simulation time 1553317229 ps
CPU time 138.99 seconds
Started Dec 31 01:04:03 PM PST 23
Finished Dec 31 01:06:23 PM PST 23
Peak memory 210516 kb
Host smart-b0c784b1-e3b1-4748-b8e6-b9b7ff0e9607
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341098068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.2341098068
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.617945254
Short name T770
Test name
Test status
Simulation time 9552109326 ps
CPU time 143.43 seconds
Started Dec 31 01:04:14 PM PST 23
Finished Dec 31 01:06:38 PM PST 23
Peak memory 202148 kb
Host smart-88f515cc-ae74-4e42-8d5b-6112a5b5fa53
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617945254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_
mem_walk.617945254
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.3564903229
Short name T555
Test name
Test status
Simulation time 23828118235 ps
CPU time 1103.25 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 01:22:46 PM PST 23
Peak memory 381056 kb
Host smart-eddee764-0a9a-48c3-9f76-b462d1292fca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564903229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.3564903229
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.289825977
Short name T544
Test name
Test status
Simulation time 4153629376 ps
CPU time 26.06 seconds
Started Dec 31 01:04:19 PM PST 23
Finished Dec 31 01:04:47 PM PST 23
Peak memory 202048 kb
Host smart-70888c68-caa7-432b-9e56-f22af0e638c6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289825977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr
am_ctrl_partial_access.289825977
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.667264996
Short name T236
Test name
Test status
Simulation time 31052727697 ps
CPU time 492.29 seconds
Started Dec 31 01:04:18 PM PST 23
Finished Dec 31 01:12:33 PM PST 23
Peak memory 202152 kb
Host smart-e4fa2c7f-adb3-4a7b-b60e-6319eb50c3b4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667264996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.sram_ctrl_partial_access_b2b.667264996
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.1049029085
Short name T246
Test name
Test status
Simulation time 2412016930 ps
CPU time 6.5 seconds
Started Dec 31 01:04:22 PM PST 23
Finished Dec 31 01:04:31 PM PST 23
Peak memory 202460 kb
Host smart-b0b8e21b-e416-409e-b902-5f532e513075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049029085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1049029085
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.361690253
Short name T57
Test name
Test status
Simulation time 2533868019 ps
CPU time 743.28 seconds
Started Dec 31 01:04:02 PM PST 23
Finished Dec 31 01:16:26 PM PST 23
Peak memory 379988 kb
Host smart-cf16d6e9-879d-454b-94d1-8116225bb665
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361690253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.361690253
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.1319606504
Short name T947
Test name
Test status
Simulation time 5911659002 ps
CPU time 12.24 seconds
Started Dec 31 01:04:19 PM PST 23
Finished Dec 31 01:04:33 PM PST 23
Peak memory 205336 kb
Host smart-fbfd1f41-93be-42bb-ae3d-a6215f1e98b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319606504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1319606504
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1021658953
Short name T25
Test name
Test status
Simulation time 11528367592 ps
CPU time 5413.01 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 02:34:37 PM PST 23
Peak memory 688316 kb
Host smart-1d49d5dc-d11c-4edc-9275-2d5fa50a3b66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1021658953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1021658953
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.293985442
Short name T560
Test name
Test status
Simulation time 9124624919 ps
CPU time 306.21 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 01:09:28 PM PST 23
Peak memory 210332 kb
Host smart-d39b789c-dc56-4427-bade-43aeb8d41528
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293985442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
sram_ctrl_stress_pipeline.293985442
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2763906108
Short name T406
Test name
Test status
Simulation time 2645500140 ps
CPU time 43.52 seconds
Started Dec 31 01:03:57 PM PST 23
Finished Dec 31 01:04:42 PM PST 23
Peak memory 269660 kb
Host smart-b5199643-a42f-45a2-b660-286c4d2c7715
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763906108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.2763906108
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.107983790
Short name T807
Test name
Test status
Simulation time 47133406242 ps
CPU time 1825.12 seconds
Started Dec 31 01:04:17 PM PST 23
Finished Dec 31 01:34:44 PM PST 23
Peak memory 376948 kb
Host smart-1fe91c37-ecc4-4862-af67-924fbf7ec4cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107983790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_access_during_key_req.107983790
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.130967565
Short name T334
Test name
Test status
Simulation time 31590035 ps
CPU time 0.64 seconds
Started Dec 31 01:04:38 PM PST 23
Finished Dec 31 01:04:44 PM PST 23
Peak memory 201900 kb
Host smart-a06fbb7f-d406-455f-8f44-7da0d1d6e3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130967565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.130967565
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.356126619
Short name T438
Test name
Test status
Simulation time 194187045956 ps
CPU time 1721.94 seconds
Started Dec 31 01:04:22 PM PST 23
Finished Dec 31 01:33:06 PM PST 23
Peak memory 202112 kb
Host smart-45998f2e-b1cd-4a57-9a97-9b760cc67f51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356126619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.356126619
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.1255380294
Short name T777
Test name
Test status
Simulation time 26540260577 ps
CPU time 670.26 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:15:37 PM PST 23
Peak memory 360616 kb
Host smart-8600a321-426e-42a2-a723-08d0531e677f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255380294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl
e.1255380294
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.637722214
Short name T360
Test name
Test status
Simulation time 8512215267 ps
CPU time 34.97 seconds
Started Dec 31 01:04:05 PM PST 23
Finished Dec 31 01:04:42 PM PST 23
Peak memory 234940 kb
Host smart-54d8fb16-6ee1-423d-97a8-8133e5013a00
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637722214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.sram_ctrl_max_throughput.637722214
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.326504344
Short name T546
Test name
Test status
Simulation time 1578188364 ps
CPU time 135.37 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:06:43 PM PST 23
Peak memory 218492 kb
Host smart-171fcb2e-8ebd-4103-9404-3ee76a366a2f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326504344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
sram_ctrl_mem_partial_access.326504344
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.2929198931
Short name T397
Test name
Test status
Simulation time 4107582302 ps
CPU time 255.76 seconds
Started Dec 31 01:04:01 PM PST 23
Finished Dec 31 01:08:18 PM PST 23
Peak memory 202168 kb
Host smart-8c384a15-a825-470c-886e-b2d3234077b2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929198931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.2929198931
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.1830320382
Short name T417
Test name
Test status
Simulation time 43053314197 ps
CPU time 920.31 seconds
Started Dec 31 01:04:05 PM PST 23
Finished Dec 31 01:19:27 PM PST 23
Peak memory 381196 kb
Host smart-f316e5f6-b01a-4efc-8579-d82097980ed8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830320382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.1830320382
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.846628446
Short name T829
Test name
Test status
Simulation time 754574460 ps
CPU time 14.32 seconds
Started Dec 31 01:04:07 PM PST 23
Finished Dec 31 01:04:22 PM PST 23
Peak memory 211232 kb
Host smart-edfca577-c45a-48ff-a139-294c1d60ca22
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846628446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sr
am_ctrl_partial_access.846628446
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4253336084
Short name T540
Test name
Test status
Simulation time 7128205429 ps
CPU time 469.6 seconds
Started Dec 31 01:04:18 PM PST 23
Finished Dec 31 01:12:10 PM PST 23
Peak memory 202144 kb
Host smart-6555d287-9c8d-4974-b549-5a20b0a2975d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253336084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.4253336084
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3639410523
Short name T520
Test name
Test status
Simulation time 671113717 ps
CPU time 6.37 seconds
Started Dec 31 01:04:24 PM PST 23
Finished Dec 31 01:04:33 PM PST 23
Peak memory 202432 kb
Host smart-f5203970-aff2-4b68-8808-cd344809e136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639410523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3639410523
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.541430996
Short name T264
Test name
Test status
Simulation time 4554813714 ps
CPU time 1560.39 seconds
Started Dec 31 01:04:25 PM PST 23
Finished Dec 31 01:30:28 PM PST 23
Peak memory 378068 kb
Host smart-740ffdfe-c016-407c-9d12-7a57650a4890
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541430996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.541430996
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.2302033654
Short name T422
Test name
Test status
Simulation time 2105381436 ps
CPU time 23.14 seconds
Started Dec 31 01:03:53 PM PST 23
Finished Dec 31 01:04:18 PM PST 23
Peak memory 202000 kb
Host smart-9eb828d3-16df-43cd-be18-fda4762e2e3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302033654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2302033654
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.794092359
Short name T722
Test name
Test status
Simulation time 2107603375 ps
CPU time 1824.35 seconds
Started Dec 31 01:04:14 PM PST 23
Finished Dec 31 01:34:40 PM PST 23
Peak memory 608812 kb
Host smart-dffccacc-3d91-4464-9be8-f7eb01a41483
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=794092359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.794092359
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3954011560
Short name T349
Test name
Test status
Simulation time 18350883957 ps
CPU time 255.87 seconds
Started Dec 31 01:04:18 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 202144 kb
Host smart-4aaa7628-8eac-43e9-a568-d148e16de7eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954011560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.3954011560
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.200836116
Short name T331
Test name
Test status
Simulation time 1469354992 ps
CPU time 67.76 seconds
Started Dec 31 01:04:03 PM PST 23
Finished Dec 31 01:05:12 PM PST 23
Peak memory 297016 kb
Host smart-7ccb52a0-f24f-4045-be97-b9692febad9c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200836116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_throughput_w_partial_write.200836116
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3948475680
Short name T957
Test name
Test status
Simulation time 12916352414 ps
CPU time 432.7 seconds
Started Dec 31 01:04:18 PM PST 23
Finished Dec 31 01:11:33 PM PST 23
Peak memory 372144 kb
Host smart-36b869fe-edef-475d-b90e-ae484329fcce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948475680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.3948475680
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.584988029
Short name T626
Test name
Test status
Simulation time 22695425 ps
CPU time 0.64 seconds
Started Dec 31 01:04:38 PM PST 23
Finished Dec 31 01:04:45 PM PST 23
Peak memory 201416 kb
Host smart-ee6de54d-ede8-40a8-8409-97d99e5b74d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584988029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.584988029
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.1721802412
Short name T248
Test name
Test status
Simulation time 72108287083 ps
CPU time 1152.07 seconds
Started Dec 31 01:04:46 PM PST 23
Finished Dec 31 01:24:01 PM PST 23
Peak memory 202196 kb
Host smart-236ae306-4bb9-49ed-bbf5-4aeda8e2ee1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721802412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
1721802412
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.2018051106
Short name T911
Test name
Test status
Simulation time 258856619990 ps
CPU time 1381.6 seconds
Started Dec 31 01:03:59 PM PST 23
Finished Dec 31 01:27:02 PM PST 23
Peak memory 375928 kb
Host smart-c457f833-8de4-48aa-bf5c-dffed8793e23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018051106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.2018051106
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.2398765856
Short name T703
Test name
Test status
Simulation time 21368353348 ps
CPU time 93.52 seconds
Started Dec 31 01:04:33 PM PST 23
Finished Dec 31 01:06:10 PM PST 23
Peak memory 210376 kb
Host smart-b170e6c9-44c9-4850-928a-0176a54769ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398765856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.2398765856
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.1731219241
Short name T139
Test name
Test status
Simulation time 3160679100 ps
CPU time 173.5 seconds
Started Dec 31 01:04:20 PM PST 23
Finished Dec 31 01:07:15 PM PST 23
Peak memory 359700 kb
Host smart-8c676dfe-a695-4511-a369-53ef3350dd5f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731219241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.1731219241
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2745627705
Short name T881
Test name
Test status
Simulation time 5109953882 ps
CPU time 82.26 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:05:47 PM PST 23
Peak memory 211060 kb
Host smart-09f98cc9-33f8-4611-a460-adc92a85b84f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745627705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.2745627705
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.650307696
Short name T491
Test name
Test status
Simulation time 38349607221 ps
CPU time 159.52 seconds
Started Dec 31 01:04:48 PM PST 23
Finished Dec 31 01:07:29 PM PST 23
Peak memory 202116 kb
Host smart-faf1d5af-9a8f-43ab-823e-cb9f4521d2d8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650307696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_
mem_walk.650307696
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.2729890453
Short name T801
Test name
Test status
Simulation time 1766303141 ps
CPU time 132.78 seconds
Started Dec 31 01:04:17 PM PST 23
Finished Dec 31 01:06:31 PM PST 23
Peak memory 285008 kb
Host smart-2025574e-1ac1-46db-ab61-4bdc57e25255
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729890453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.2729890453
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.3199656068
Short name T954
Test name
Test status
Simulation time 2373893963 ps
CPU time 28.76 seconds
Started Dec 31 01:04:16 PM PST 23
Finished Dec 31 01:04:46 PM PST 23
Peak memory 202164 kb
Host smart-5ca74bd7-84ae-4063-b5cc-24c7c552f935
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199656068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.3199656068
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2280279979
Short name T15
Test name
Test status
Simulation time 33293434089 ps
CPU time 377.93 seconds
Started Dec 31 01:04:29 PM PST 23
Finished Dec 31 01:10:50 PM PST 23
Peak memory 202032 kb
Host smart-55700a3d-5b70-4d52-8e6f-a3ff24531e11
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280279979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.2280279979
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.3337501864
Short name T551
Test name
Test status
Simulation time 357862237 ps
CPU time 6.61 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:04:32 PM PST 23
Peak memory 202416 kb
Host smart-422f44a4-22fa-4aa8-a2bc-86404382dae0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337501864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3337501864
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.246486005
Short name T815
Test name
Test status
Simulation time 5969485860 ps
CPU time 918.83 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 01:19:53 PM PST 23
Peak memory 379116 kb
Host smart-c3fb0ba0-9356-4232-b31a-05fc6f6d6d52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246486005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.246486005
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.446653590
Short name T571
Test name
Test status
Simulation time 830757250 ps
CPU time 81.55 seconds
Started Dec 31 01:04:15 PM PST 23
Finished Dec 31 01:05:38 PM PST 23
Peak memory 329868 kb
Host smart-063d407a-71ab-40f0-b37a-596456c6e307
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446653590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.446653590
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3378544877
Short name T489
Test name
Test status
Simulation time 2414779672 ps
CPU time 4058.81 seconds
Started Dec 31 01:04:19 PM PST 23
Finished Dec 31 02:12:00 PM PST 23
Peak memory 729000 kb
Host smart-10522132-410f-4530-8972-1ec337e7e108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3378544877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3378544877
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2288089216
Short name T260
Test name
Test status
Simulation time 11420658594 ps
CPU time 326.28 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:09:55 PM PST 23
Peak memory 202124 kb
Host smart-780a4404-96b7-4249-a4b4-6d7db5875c92
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288089216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.2288089216
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1290901941
Short name T436
Test name
Test status
Simulation time 3277578445 ps
CPU time 50.84 seconds
Started Dec 31 01:04:15 PM PST 23
Finished Dec 31 01:05:07 PM PST 23
Peak memory 284052 kb
Host smart-21201739-289b-4f97-a2ce-2fdcf15f25fc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290901941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.1290901941
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3721805531
Short name T416
Test name
Test status
Simulation time 4270741410 ps
CPU time 218.52 seconds
Started Dec 31 01:04:16 PM PST 23
Finished Dec 31 01:07:56 PM PST 23
Peak memory 363696 kb
Host smart-e3e04b75-21dd-40b5-a105-6734671a32e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721805531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.3721805531
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.3660053631
Short name T832
Test name
Test status
Simulation time 12810506 ps
CPU time 0.67 seconds
Started Dec 31 01:04:20 PM PST 23
Finished Dec 31 01:04:22 PM PST 23
Peak memory 201440 kb
Host smart-54b75781-9b27-40a1-a6cd-8e127a958570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660053631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.3660053631
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.1639553351
Short name T760
Test name
Test status
Simulation time 45120682787 ps
CPU time 763.71 seconds
Started Dec 31 01:04:28 PM PST 23
Finished Dec 31 01:17:14 PM PST 23
Peak memory 202072 kb
Host smart-163c99a7-976a-4dad-b822-42a71c24f036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639553351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
1639553351
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.540058604
Short name T919
Test name
Test status
Simulation time 3527836903 ps
CPU time 181.5 seconds
Started Dec 31 01:04:29 PM PST 23
Finished Dec 31 01:07:33 PM PST 23
Peak memory 373860 kb
Host smart-3e104f5e-fa5b-4078-ab2b-c1d672b75d17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540058604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable
.540058604
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.4258382516
Short name T822
Test name
Test status
Simulation time 29939237001 ps
CPU time 130.57 seconds
Started Dec 31 01:04:24 PM PST 23
Finished Dec 31 01:06:37 PM PST 23
Peak memory 210404 kb
Host smart-b3d5306e-7ae0-456d-87de-5a453a0f70d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258382516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.4258382516
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.3608723139
Short name T579
Test name
Test status
Simulation time 735962938 ps
CPU time 37.21 seconds
Started Dec 31 01:04:30 PM PST 23
Finished Dec 31 01:05:11 PM PST 23
Peak memory 251160 kb
Host smart-6861122f-a630-4d22-a132-85e962ab3af3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608723139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.3608723139
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2742852309
Short name T324
Test name
Test status
Simulation time 9345921007 ps
CPU time 78.98 seconds
Started Dec 31 01:04:22 PM PST 23
Finished Dec 31 01:05:43 PM PST 23
Peak memory 218484 kb
Host smart-3b924ec2-4480-4afe-80c4-7ea96aed7b5a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742852309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.2742852309
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.546717755
Short name T784
Test name
Test status
Simulation time 2061239969 ps
CPU time 120.48 seconds
Started Dec 31 01:04:29 PM PST 23
Finished Dec 31 01:06:33 PM PST 23
Peak memory 202060 kb
Host smart-aa157c54-4ec9-42b5-8970-0d2d10cdbcd1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546717755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_
mem_walk.546717755
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.3806894956
Short name T733
Test name
Test status
Simulation time 14577245749 ps
CPU time 84.43 seconds
Started Dec 31 01:04:44 PM PST 23
Finished Dec 31 01:06:12 PM PST 23
Peak memory 256748 kb
Host smart-817f2522-b061-4e34-8349-d4e63bda45b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806894956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.3806894956
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.2802199588
Short name T885
Test name
Test status
Simulation time 7988709352 ps
CPU time 16.74 seconds
Started Dec 31 01:04:23 PM PST 23
Finished Dec 31 01:04:42 PM PST 23
Peak memory 205956 kb
Host smart-d4d13ca3-bd7e-4914-87e8-949c5bdc1e1c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802199588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.2802199588
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3611584689
Short name T688
Test name
Test status
Simulation time 39949054443 ps
CPU time 569.22 seconds
Started Dec 31 01:04:39 PM PST 23
Finished Dec 31 01:14:14 PM PST 23
Peak memory 202136 kb
Host smart-5ab95fdf-23a1-4a7e-8570-183350d9cabc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611584689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.3611584689
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.3811572250
Short name T766
Test name
Test status
Simulation time 361113328 ps
CPU time 13.68 seconds
Started Dec 31 01:04:26 PM PST 23
Finished Dec 31 01:04:42 PM PST 23
Peak memory 202332 kb
Host smart-1fd2ca7d-2499-4a49-bc51-61e108d372c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811572250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3811572250
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.3353182291
Short name T888
Test name
Test status
Simulation time 7856615133 ps
CPU time 61.5 seconds
Started Dec 31 01:04:32 PM PST 23
Finished Dec 31 01:05:37 PM PST 23
Peak memory 202140 kb
Host smart-dc8adfa2-00a0-4e04-945d-7bce9ca56b2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353182291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3353182291
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.256372877
Short name T1
Test name
Test status
Simulation time 900345296 ps
CPU time 131.26 seconds
Started Dec 31 01:04:38 PM PST 23
Finished Dec 31 01:06:55 PM PST 23
Peak memory 351364 kb
Host smart-802f10d4-4182-4f1f-b4e4-9a9d4b59ee09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256372877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.256372877
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1574597954
Short name T787
Test name
Test status
Simulation time 1099152857 ps
CPU time 3897.06 seconds
Started Dec 31 01:04:31 PM PST 23
Finished Dec 31 02:09:32 PM PST 23
Peak memory 416760 kb
Host smart-6d1f0dd1-7733-4eb3-af47-5757b9a93ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1574597954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1574597954
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2676136373
Short name T322
Test name
Test status
Simulation time 4475549561 ps
CPU time 269.17 seconds
Started Dec 31 01:04:44 PM PST 23
Finished Dec 31 01:09:16 PM PST 23
Peak memory 202124 kb
Host smart-87eb7281-e346-4388-b079-8aa4f513f204
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676136373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.2676136373
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.283253743
Short name T218
Test name
Test status
Simulation time 817918710 ps
CPU time 170.92 seconds
Started Dec 31 01:04:21 PM PST 23
Finished Dec 31 01:07:14 PM PST 23
Peak memory 364592 kb
Host smart-68d495da-6fc4-4f44-b077-18c68da94f67
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283253743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_throughput_w_partial_write.283253743
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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