| T301 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2980256443 |
|
|
Mar 05 01:27:06 PM PST 24 |
Mar 05 01:27:07 PM PST 24 |
16572883 ps |
| T302 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2901857670 |
|
|
Mar 05 01:25:59 PM PST 24 |
Mar 05 01:26:03 PM PST 24 |
5594897495 ps |
| T303 |
/workspace/coverage/default/40.sram_ctrl_regwen.4193836348 |
|
|
Mar 05 01:26:44 PM PST 24 |
Mar 05 01:50:36 PM PST 24 |
45762679391 ps |
| T304 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4072874571 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:30:29 PM PST 24 |
49742455789 ps |
| T305 |
/workspace/coverage/default/17.sram_ctrl_smoke.3592763116 |
|
|
Mar 05 01:24:58 PM PST 24 |
Mar 05 01:25:16 PM PST 24 |
1443171800 ps |
| T306 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.4192434654 |
|
|
Mar 05 01:26:29 PM PST 24 |
Mar 05 01:26:45 PM PST 24 |
1589876782 ps |
| T307 |
/workspace/coverage/default/7.sram_ctrl_bijection.2032134235 |
|
|
Mar 05 01:24:51 PM PST 24 |
Mar 05 01:47:16 PM PST 24 |
394910389582 ps |
| T308 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.3504642641 |
|
|
Mar 05 01:26:44 PM PST 24 |
Mar 05 01:29:08 PM PST 24 |
3511259554 ps |
| T309 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.108121078 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 01:26:01 PM PST 24 |
2071158923 ps |
| T310 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2269743514 |
|
|
Mar 05 01:24:32 PM PST 24 |
Mar 05 01:24:35 PM PST 24 |
361955413 ps |
| T311 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.3296068091 |
|
|
Mar 05 01:25:16 PM PST 24 |
Mar 05 01:25:45 PM PST 24 |
764900590 ps |
| T312 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3472800616 |
|
|
Mar 05 01:24:39 PM PST 24 |
Mar 05 01:24:47 PM PST 24 |
791434834 ps |
| T313 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.2902352610 |
|
|
Mar 05 01:26:09 PM PST 24 |
Mar 05 01:26:12 PM PST 24 |
2236249332 ps |
| T314 |
/workspace/coverage/default/40.sram_ctrl_bijection.2434691794 |
|
|
Mar 05 01:26:34 PM PST 24 |
Mar 05 01:55:27 PM PST 24 |
28052129887 ps |
| T315 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2089900847 |
|
|
Mar 05 01:27:16 PM PST 24 |
Mar 05 01:37:13 PM PST 24 |
3125668206 ps |
| T316 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2490978003 |
|
|
Mar 05 01:24:41 PM PST 24 |
Mar 05 01:27:01 PM PST 24 |
763435327 ps |
| T317 |
/workspace/coverage/default/41.sram_ctrl_smoke.3436522325 |
|
|
Mar 05 01:26:44 PM PST 24 |
Mar 05 01:27:00 PM PST 24 |
1222880599 ps |
| T318 |
/workspace/coverage/default/11.sram_ctrl_regwen.2827599894 |
|
|
Mar 05 01:24:55 PM PST 24 |
Mar 05 01:43:35 PM PST 24 |
55460878118 ps |
| T319 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1454460711 |
|
|
Mar 05 01:27:14 PM PST 24 |
Mar 05 01:35:28 PM PST 24 |
25679770304 ps |
| T320 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2610507619 |
|
|
Mar 05 01:26:18 PM PST 24 |
Mar 05 01:26:19 PM PST 24 |
27087939 ps |
| T321 |
/workspace/coverage/default/26.sram_ctrl_bijection.861400279 |
|
|
Mar 05 01:25:28 PM PST 24 |
Mar 05 01:41:31 PM PST 24 |
41656594109 ps |
| T322 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1550529081 |
|
|
Mar 05 01:24:40 PM PST 24 |
Mar 05 01:28:00 PM PST 24 |
12452703776 ps |
| T323 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.131081691 |
|
|
Mar 05 01:26:26 PM PST 24 |
Mar 05 01:27:35 PM PST 24 |
947651248 ps |
| T324 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.116346938 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 01:28:38 PM PST 24 |
15759141729 ps |
| T325 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3032162635 |
|
|
Mar 05 01:25:40 PM PST 24 |
Mar 05 01:25:44 PM PST 24 |
2104304140 ps |
| T326 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2785278111 |
|
|
Mar 05 01:26:47 PM PST 24 |
Mar 05 01:29:29 PM PST 24 |
9067734667 ps |
| T327 |
/workspace/coverage/default/47.sram_ctrl_regwen.2586380437 |
|
|
Mar 05 01:27:39 PM PST 24 |
Mar 05 01:33:05 PM PST 24 |
4517306590 ps |
| T328 |
/workspace/coverage/default/19.sram_ctrl_regwen.3413523263 |
|
|
Mar 05 01:25:09 PM PST 24 |
Mar 05 01:34:45 PM PST 24 |
11386067934 ps |
| T329 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.3765673346 |
|
|
Mar 05 01:24:55 PM PST 24 |
Mar 05 01:27:20 PM PST 24 |
8966870234 ps |
| T330 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.1151777343 |
|
|
Mar 05 01:26:42 PM PST 24 |
Mar 05 01:28:21 PM PST 24 |
2991774511 ps |
| T331 |
/workspace/coverage/default/3.sram_ctrl_smoke.3402852660 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:24:40 PM PST 24 |
485246598 ps |
| T332 |
/workspace/coverage/default/41.sram_ctrl_bijection.885636530 |
|
|
Mar 05 01:26:44 PM PST 24 |
Mar 05 01:45:27 PM PST 24 |
63072688852 ps |
| T333 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3067167283 |
|
|
Mar 05 01:25:32 PM PST 24 |
Mar 05 01:29:32 PM PST 24 |
4534698653 ps |
| T334 |
/workspace/coverage/default/9.sram_ctrl_stress_all.4121525407 |
|
|
Mar 05 01:24:46 PM PST 24 |
Mar 05 03:16:38 PM PST 24 |
1811513360771 ps |
| T335 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3913839724 |
|
|
Mar 05 01:26:44 PM PST 24 |
Mar 05 01:27:28 PM PST 24 |
3083265983 ps |
| T336 |
/workspace/coverage/default/9.sram_ctrl_regwen.740429072 |
|
|
Mar 05 01:24:47 PM PST 24 |
Mar 05 01:28:11 PM PST 24 |
6739617062 ps |
| T337 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1184321869 |
|
|
Mar 05 01:27:07 PM PST 24 |
Mar 05 01:27:22 PM PST 24 |
2761196475 ps |
| T338 |
/workspace/coverage/default/34.sram_ctrl_alert_test.2348182167 |
|
|
Mar 05 01:26:05 PM PST 24 |
Mar 05 01:26:06 PM PST 24 |
39248792 ps |
| T339 |
/workspace/coverage/default/32.sram_ctrl_executable.3693469450 |
|
|
Mar 05 01:26:00 PM PST 24 |
Mar 05 01:46:02 PM PST 24 |
22089223114 ps |
| T340 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2402125661 |
|
|
Mar 05 01:25:48 PM PST 24 |
Mar 05 01:28:33 PM PST 24 |
2326739208 ps |
| T341 |
/workspace/coverage/default/17.sram_ctrl_alert_test.235595167 |
|
|
Mar 05 01:25:07 PM PST 24 |
Mar 05 01:25:08 PM PST 24 |
15043118 ps |
| T342 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2485885754 |
|
|
Mar 05 01:24:54 PM PST 24 |
Mar 05 01:25:22 PM PST 24 |
6449712845 ps |
| T343 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.2529624295 |
|
|
Mar 05 01:25:11 PM PST 24 |
Mar 05 01:25:31 PM PST 24 |
1411778529 ps |
| T344 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.906599874 |
|
|
Mar 05 01:26:08 PM PST 24 |
Mar 05 01:27:50 PM PST 24 |
6746100060 ps |
| T345 |
/workspace/coverage/default/49.sram_ctrl_partial_access.58295778 |
|
|
Mar 05 01:27:46 PM PST 24 |
Mar 05 01:28:16 PM PST 24 |
20996555195 ps |
| T346 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1505300397 |
|
|
Mar 05 01:25:45 PM PST 24 |
Mar 05 01:26:46 PM PST 24 |
1930477009 ps |
| T347 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2976378082 |
|
|
Mar 05 01:24:39 PM PST 24 |
Mar 05 01:24:47 PM PST 24 |
1393474499 ps |
| T348 |
/workspace/coverage/default/29.sram_ctrl_partial_access.3117546039 |
|
|
Mar 05 01:25:28 PM PST 24 |
Mar 05 01:25:37 PM PST 24 |
1416098941 ps |
| T349 |
/workspace/coverage/default/6.sram_ctrl_alert_test.4173345198 |
|
|
Mar 05 01:24:35 PM PST 24 |
Mar 05 01:24:35 PM PST 24 |
42620560 ps |
| T350 |
/workspace/coverage/default/9.sram_ctrl_smoke.2064474156 |
|
|
Mar 05 01:24:45 PM PST 24 |
Mar 05 01:24:49 PM PST 24 |
370787132 ps |
| T351 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3814643781 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 01:25:42 PM PST 24 |
10160862350 ps |
| T352 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2193680787 |
|
|
Mar 05 01:24:22 PM PST 24 |
Mar 05 01:25:35 PM PST 24 |
4783511372 ps |
| T353 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2004083179 |
|
|
Mar 05 01:27:39 PM PST 24 |
Mar 05 01:27:59 PM PST 24 |
3058329393 ps |
| T354 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.223302336 |
|
|
Mar 05 01:24:30 PM PST 24 |
Mar 05 01:29:40 PM PST 24 |
18451598973 ps |
| T355 |
/workspace/coverage/default/42.sram_ctrl_smoke.2959115587 |
|
|
Mar 05 01:26:54 PM PST 24 |
Mar 05 01:27:41 PM PST 24 |
5690639194 ps |
| T356 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1018921353 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:31:52 PM PST 24 |
21633237735 ps |
| T357 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1513539536 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 01:29:56 PM PST 24 |
59393037858 ps |
| T358 |
/workspace/coverage/default/19.sram_ctrl_bijection.58985411 |
|
|
Mar 05 01:25:17 PM PST 24 |
Mar 05 01:50:04 PM PST 24 |
258363410637 ps |
| T359 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.505907317 |
|
|
Mar 05 01:24:42 PM PST 24 |
Mar 05 01:25:47 PM PST 24 |
824441485 ps |
| T360 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2661507597 |
|
|
Mar 05 01:25:03 PM PST 24 |
Mar 05 03:01:37 PM PST 24 |
917270810698 ps |
| T361 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2464405208 |
|
|
Mar 05 01:24:37 PM PST 24 |
Mar 05 01:25:19 PM PST 24 |
3523760437 ps |
| T362 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.338022587 |
|
|
Mar 05 01:24:32 PM PST 24 |
Mar 05 01:26:59 PM PST 24 |
9783042812 ps |
| T363 |
/workspace/coverage/default/22.sram_ctrl_executable.2315035601 |
|
|
Mar 05 01:25:21 PM PST 24 |
Mar 05 01:43:21 PM PST 24 |
172654620778 ps |
| T364 |
/workspace/coverage/default/1.sram_ctrl_executable.1975672470 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 01:28:30 PM PST 24 |
2899016605 ps |
| T365 |
/workspace/coverage/default/47.sram_ctrl_partial_access.191584527 |
|
|
Mar 05 01:27:31 PM PST 24 |
Mar 05 01:27:47 PM PST 24 |
9931972422 ps |
| T366 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.615114517 |
|
|
Mar 05 01:26:44 PM PST 24 |
Mar 05 01:31:54 PM PST 24 |
36495787595 ps |
| T367 |
/workspace/coverage/default/15.sram_ctrl_alert_test.3171769784 |
|
|
Mar 05 01:25:05 PM PST 24 |
Mar 05 01:25:07 PM PST 24 |
21273158 ps |
| T368 |
/workspace/coverage/default/17.sram_ctrl_partial_access.3394121401 |
|
|
Mar 05 01:24:54 PM PST 24 |
Mar 05 01:25:20 PM PST 24 |
4175554753 ps |
| T369 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.654055571 |
|
|
Mar 05 01:27:21 PM PST 24 |
Mar 05 01:27:29 PM PST 24 |
2813941212 ps |
| T370 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3987967342 |
|
|
Mar 05 01:25:30 PM PST 24 |
Mar 05 01:26:28 PM PST 24 |
764844334 ps |
| T371 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.4088918538 |
|
|
Mar 05 01:25:07 PM PST 24 |
Mar 05 01:25:22 PM PST 24 |
3624522314 ps |
| T372 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1090723388 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:25:05 PM PST 24 |
369334982 ps |
| T373 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.885064467 |
|
|
Mar 05 01:25:29 PM PST 24 |
Mar 05 01:26:08 PM PST 24 |
729187681 ps |
| T374 |
/workspace/coverage/default/47.sram_ctrl_alert_test.3935697468 |
|
|
Mar 05 01:27:39 PM PST 24 |
Mar 05 01:27:40 PM PST 24 |
19513754 ps |
| T375 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2197378088 |
|
|
Mar 05 01:27:39 PM PST 24 |
Mar 05 01:50:54 PM PST 24 |
15113847809 ps |
| T376 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2370999551 |
|
|
Mar 05 01:27:24 PM PST 24 |
Mar 05 01:27:25 PM PST 24 |
91330278 ps |
| T377 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.510189487 |
|
|
Mar 05 01:25:12 PM PST 24 |
Mar 05 01:27:42 PM PST 24 |
19009853510 ps |
| T378 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3213254840 |
|
|
Mar 05 01:26:31 PM PST 24 |
Mar 05 01:39:33 PM PST 24 |
13226098407 ps |
| T379 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.4160408152 |
|
|
Mar 05 01:25:57 PM PST 24 |
Mar 05 01:28:01 PM PST 24 |
2690884933 ps |
| T380 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1827305163 |
|
|
Mar 05 01:25:07 PM PST 24 |
Mar 05 01:25:31 PM PST 24 |
5556812390 ps |
| T381 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.385703463 |
|
|
Mar 05 01:25:00 PM PST 24 |
Mar 05 01:25:04 PM PST 24 |
683660940 ps |
| T382 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1128931510 |
|
|
Mar 05 01:26:07 PM PST 24 |
Mar 05 01:27:56 PM PST 24 |
1499850615 ps |
| T383 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.3843019882 |
|
|
Mar 05 01:24:49 PM PST 24 |
Mar 05 01:25:15 PM PST 24 |
780219103 ps |
| T384 |
/workspace/coverage/default/30.sram_ctrl_smoke.376405633 |
|
|
Mar 05 01:25:39 PM PST 24 |
Mar 05 01:25:49 PM PST 24 |
872462217 ps |
| T385 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.802143312 |
|
|
Mar 05 01:25:47 PM PST 24 |
Mar 05 01:25:50 PM PST 24 |
724025242 ps |
| T386 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3163432202 |
|
|
Mar 05 01:24:41 PM PST 24 |
Mar 05 01:33:13 PM PST 24 |
23134890882 ps |
| T387 |
/workspace/coverage/default/46.sram_ctrl_bijection.1100786082 |
|
|
Mar 05 01:27:24 PM PST 24 |
Mar 05 01:59:34 PM PST 24 |
609365819928 ps |
| T388 |
/workspace/coverage/default/18.sram_ctrl_smoke.1720837138 |
|
|
Mar 05 01:25:04 PM PST 24 |
Mar 05 01:25:17 PM PST 24 |
7519744568 ps |
| T389 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.371286198 |
|
|
Mar 05 01:27:45 PM PST 24 |
Mar 05 01:47:50 PM PST 24 |
24715786071 ps |
| T390 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.529780656 |
|
|
Mar 05 01:24:37 PM PST 24 |
Mar 05 01:27:35 PM PST 24 |
3069840598 ps |
| T391 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1928041886 |
|
|
Mar 05 01:25:35 PM PST 24 |
Mar 05 01:25:44 PM PST 24 |
1737127534 ps |
| T392 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1541995369 |
|
|
Mar 05 01:24:34 PM PST 24 |
Mar 05 01:28:00 PM PST 24 |
6714655254 ps |
| T393 |
/workspace/coverage/default/4.sram_ctrl_executable.2897689080 |
|
|
Mar 05 01:24:29 PM PST 24 |
Mar 05 01:39:14 PM PST 24 |
151604785435 ps |
| T394 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.3147366648 |
|
|
Mar 05 01:26:27 PM PST 24 |
Mar 05 01:28:49 PM PST 24 |
27499157887 ps |
| T79 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1343974866 |
|
|
Mar 05 01:27:39 PM PST 24 |
Mar 05 01:28:42 PM PST 24 |
975614173 ps |
| T395 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.4073564976 |
|
|
Mar 05 01:27:09 PM PST 24 |
Mar 05 01:29:15 PM PST 24 |
12340256114 ps |
| T396 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.3497250488 |
|
|
Mar 05 01:26:57 PM PST 24 |
Mar 05 01:31:53 PM PST 24 |
57380358481 ps |
| T397 |
/workspace/coverage/default/32.sram_ctrl_partial_access.1878385907 |
|
|
Mar 05 01:25:57 PM PST 24 |
Mar 05 01:26:12 PM PST 24 |
3527051981 ps |
| T398 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3142455123 |
|
|
Mar 05 01:24:49 PM PST 24 |
Mar 05 01:29:10 PM PST 24 |
19412546955 ps |
| T399 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.39855257 |
|
|
Mar 05 01:25:31 PM PST 24 |
Mar 05 01:28:43 PM PST 24 |
3142569480 ps |
| T400 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1110496601 |
|
|
Mar 05 01:25:16 PM PST 24 |
Mar 05 01:25:23 PM PST 24 |
812187005 ps |
| T401 |
/workspace/coverage/default/2.sram_ctrl_stress_all.599098393 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 02:13:15 PM PST 24 |
43340058076 ps |
| T402 |
/workspace/coverage/default/44.sram_ctrl_bijection.1614539290 |
|
|
Mar 05 01:27:19 PM PST 24 |
Mar 05 01:44:14 PM PST 24 |
64287837992 ps |
| T403 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.3927467585 |
|
|
Mar 05 01:26:27 PM PST 24 |
Mar 05 01:26:32 PM PST 24 |
998721894 ps |
| T404 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.751072500 |
|
|
Mar 05 01:25:24 PM PST 24 |
Mar 05 01:25:28 PM PST 24 |
1400357513 ps |
| T405 |
/workspace/coverage/default/19.sram_ctrl_partial_access.1070301635 |
|
|
Mar 05 01:25:06 PM PST 24 |
Mar 05 01:25:13 PM PST 24 |
1318697297 ps |
| T406 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.92778198 |
|
|
Mar 05 01:27:18 PM PST 24 |
Mar 05 01:27:34 PM PST 24 |
2328910481 ps |
| T407 |
/workspace/coverage/default/24.sram_ctrl_regwen.1344632406 |
|
|
Mar 05 01:25:21 PM PST 24 |
Mar 05 01:25:50 PM PST 24 |
6329025963 ps |
| T408 |
/workspace/coverage/default/33.sram_ctrl_smoke.4085760298 |
|
|
Mar 05 01:26:03 PM PST 24 |
Mar 05 01:26:24 PM PST 24 |
5601469681 ps |
| T409 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3165374444 |
|
|
Mar 05 01:27:17 PM PST 24 |
Mar 05 01:29:16 PM PST 24 |
6248904766 ps |
| T410 |
/workspace/coverage/default/45.sram_ctrl_partial_access.1580354208 |
|
|
Mar 05 01:27:17 PM PST 24 |
Mar 05 01:27:34 PM PST 24 |
2194015191 ps |
| T411 |
/workspace/coverage/default/8.sram_ctrl_regwen.1688509875 |
|
|
Mar 05 01:24:36 PM PST 24 |
Mar 05 01:31:49 PM PST 24 |
11042460006 ps |
| T412 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1054055814 |
|
|
Mar 05 01:24:37 PM PST 24 |
Mar 05 01:24:41 PM PST 24 |
711591936 ps |
| T413 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.560986378 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:25:48 PM PST 24 |
2622346029 ps |
| T414 |
/workspace/coverage/default/10.sram_ctrl_regwen.1995744621 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:35:44 PM PST 24 |
3378170665 ps |
| T415 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.2521084253 |
|
|
Mar 05 01:25:12 PM PST 24 |
Mar 05 01:27:32 PM PST 24 |
6900700874 ps |
| T416 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3226615834 |
|
|
Mar 05 01:24:35 PM PST 24 |
Mar 05 01:25:01 PM PST 24 |
2934901034 ps |
| T417 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2582706645 |
|
|
Mar 05 01:24:40 PM PST 24 |
Mar 05 01:39:15 PM PST 24 |
82818294771 ps |
| T418 |
/workspace/coverage/default/28.sram_ctrl_stress_all.357455499 |
|
|
Mar 05 01:25:32 PM PST 24 |
Mar 05 02:48:13 PM PST 24 |
29273593595 ps |
| T419 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1589895018 |
|
|
Mar 05 01:27:30 PM PST 24 |
Mar 05 01:34:28 PM PST 24 |
19168091818 ps |
| T420 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.1685702353 |
|
|
Mar 05 01:24:30 PM PST 24 |
Mar 05 01:24:47 PM PST 24 |
720000657 ps |
| T421 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.801795325 |
|
|
Mar 05 01:26:51 PM PST 24 |
Mar 05 01:27:27 PM PST 24 |
4655799452 ps |
| T422 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.783905608 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:25:32 PM PST 24 |
3714193337 ps |
| T423 |
/workspace/coverage/default/11.sram_ctrl_stress_all.2650807285 |
|
|
Mar 05 01:24:34 PM PST 24 |
Mar 05 02:59:14 PM PST 24 |
285579771762 ps |
| T424 |
/workspace/coverage/default/18.sram_ctrl_alert_test.3184264862 |
|
|
Mar 05 01:25:09 PM PST 24 |
Mar 05 01:25:10 PM PST 24 |
10720176 ps |
| T425 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.245605415 |
|
|
Mar 05 01:27:24 PM PST 24 |
Mar 05 01:28:38 PM PST 24 |
2334570395 ps |
| T426 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.845055244 |
|
|
Mar 05 01:25:00 PM PST 24 |
Mar 05 01:31:20 PM PST 24 |
35959088658 ps |
| T427 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3665828266 |
|
|
Mar 05 01:27:22 PM PST 24 |
Mar 05 01:27:56 PM PST 24 |
2575299383 ps |
| T428 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.492870156 |
|
|
Mar 05 01:25:04 PM PST 24 |
Mar 05 01:37:11 PM PST 24 |
122826521553 ps |
| T429 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1689720041 |
|
|
Mar 05 01:24:44 PM PST 24 |
Mar 05 01:24:44 PM PST 24 |
11877427 ps |
| T100 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4198436843 |
|
|
Mar 05 01:25:15 PM PST 24 |
Mar 05 01:26:06 PM PST 24 |
1865234355 ps |
| T430 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1352209844 |
|
|
Mar 05 01:26:20 PM PST 24 |
Mar 05 01:26:21 PM PST 24 |
14498106 ps |
| T431 |
/workspace/coverage/default/37.sram_ctrl_regwen.1606278814 |
|
|
Mar 05 01:26:27 PM PST 24 |
Mar 05 01:42:56 PM PST 24 |
111004039639 ps |
| T432 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1663980856 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:45:40 PM PST 24 |
45182881166 ps |
| T433 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.3697655657 |
|
|
Mar 05 01:25:57 PM PST 24 |
Mar 05 01:28:17 PM PST 24 |
19127114715 ps |
| T25 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3634789262 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:24:32 PM PST 24 |
1856038637 ps |
| T434 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.60072124 |
|
|
Mar 05 01:26:18 PM PST 24 |
Mar 05 01:30:30 PM PST 24 |
16615560040 ps |
| T435 |
/workspace/coverage/default/29.sram_ctrl_stress_all.1265747015 |
|
|
Mar 05 01:25:38 PM PST 24 |
Mar 05 01:52:19 PM PST 24 |
44254414370 ps |
| T436 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3556478303 |
|
|
Mar 05 01:24:43 PM PST 24 |
Mar 05 01:26:47 PM PST 24 |
14385986888 ps |
| T437 |
/workspace/coverage/default/17.sram_ctrl_bijection.1751334081 |
|
|
Mar 05 01:25:03 PM PST 24 |
Mar 05 01:54:27 PM PST 24 |
79217714731 ps |
| T438 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2982556780 |
|
|
Mar 05 01:27:23 PM PST 24 |
Mar 05 01:31:48 PM PST 24 |
15644701631 ps |
| T439 |
/workspace/coverage/default/0.sram_ctrl_partial_access.1442614172 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:26:35 PM PST 24 |
4315082811 ps |
| T440 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4225118466 |
|
|
Mar 05 01:26:59 PM PST 24 |
Mar 05 01:27:10 PM PST 24 |
1071390786 ps |
| T441 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3526301795 |
|
|
Mar 05 01:25:20 PM PST 24 |
Mar 05 01:25:42 PM PST 24 |
1298094598 ps |
| T442 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3459928469 |
|
|
Mar 05 01:24:31 PM PST 24 |
Mar 05 01:25:34 PM PST 24 |
5765110432 ps |
| T443 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3368357082 |
|
|
Mar 05 01:24:29 PM PST 24 |
Mar 05 01:30:34 PM PST 24 |
46582888988 ps |
| T444 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3481966596 |
|
|
Mar 05 01:24:41 PM PST 24 |
Mar 05 01:33:49 PM PST 24 |
38378032926 ps |
| T445 |
/workspace/coverage/default/34.sram_ctrl_smoke.1939678328 |
|
|
Mar 05 01:25:59 PM PST 24 |
Mar 05 01:26:18 PM PST 24 |
1420586726 ps |
| T446 |
/workspace/coverage/default/42.sram_ctrl_regwen.208398404 |
|
|
Mar 05 01:27:00 PM PST 24 |
Mar 05 01:39:58 PM PST 24 |
3110880516 ps |
| T447 |
/workspace/coverage/default/26.sram_ctrl_regwen.3301412113 |
|
|
Mar 05 01:25:22 PM PST 24 |
Mar 05 01:40:51 PM PST 24 |
23562416217 ps |
| T448 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1412054118 |
|
|
Mar 05 01:24:49 PM PST 24 |
Mar 05 01:26:53 PM PST 24 |
6925039540 ps |
| T449 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.3636702333 |
|
|
Mar 05 01:25:17 PM PST 24 |
Mar 05 01:30:29 PM PST 24 |
21522144884 ps |
| T450 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.2462340752 |
|
|
Mar 05 01:25:08 PM PST 24 |
Mar 05 01:25:11 PM PST 24 |
345848196 ps |
| T451 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2521257131 |
|
|
Mar 05 01:24:56 PM PST 24 |
Mar 05 01:31:25 PM PST 24 |
12888538041 ps |
| T452 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3570472778 |
|
|
Mar 05 01:27:14 PM PST 24 |
Mar 05 01:28:59 PM PST 24 |
1484883980 ps |
| T453 |
/workspace/coverage/default/21.sram_ctrl_stress_all.4206809340 |
|
|
Mar 05 01:25:09 PM PST 24 |
Mar 05 02:46:06 PM PST 24 |
1301078099763 ps |
| T454 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.4262499387 |
|
|
Mar 05 01:24:21 PM PST 24 |
Mar 05 01:27:02 PM PST 24 |
60815006308 ps |
| T455 |
/workspace/coverage/default/43.sram_ctrl_bijection.53792838 |
|
|
Mar 05 01:26:58 PM PST 24 |
Mar 05 02:06:27 PM PST 24 |
207451632201 ps |
| T456 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3528854446 |
|
|
Mar 05 01:25:19 PM PST 24 |
Mar 05 01:28:43 PM PST 24 |
3110089464 ps |
| T457 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.4127241381 |
|
|
Mar 05 01:26:18 PM PST 24 |
Mar 05 01:27:46 PM PST 24 |
15176109091 ps |
| T458 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2770598312 |
|
|
Mar 05 01:26:35 PM PST 24 |
Mar 05 01:31:29 PM PST 24 |
57350816842 ps |
| T459 |
/workspace/coverage/default/48.sram_ctrl_smoke.545431133 |
|
|
Mar 05 01:27:41 PM PST 24 |
Mar 05 01:27:46 PM PST 24 |
1694642129 ps |
| T460 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3121308131 |
|
|
Mar 05 01:25:58 PM PST 24 |
Mar 05 01:28:22 PM PST 24 |
4355295298 ps |
| T461 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3303695085 |
|
|
Mar 05 01:26:14 PM PST 24 |
Mar 05 01:30:48 PM PST 24 |
4402866751 ps |
| T462 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.2433004188 |
|
|
Mar 05 01:25:09 PM PST 24 |
Mar 05 01:29:23 PM PST 24 |
4535683122 ps |
| T463 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2979775418 |
|
|
Mar 05 01:25:37 PM PST 24 |
Mar 05 01:30:47 PM PST 24 |
42144090806 ps |
| T464 |
/workspace/coverage/default/1.sram_ctrl_partial_access.643476442 |
|
|
Mar 05 01:24:11 PM PST 24 |
Mar 05 01:24:28 PM PST 24 |
607674983 ps |
| T465 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2296452475 |
|
|
Mar 05 01:24:44 PM PST 24 |
Mar 05 01:25:48 PM PST 24 |
5585155955 ps |
| T466 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.407184680 |
|
|
Mar 05 01:26:58 PM PST 24 |
Mar 05 01:27:02 PM PST 24 |
1779893032 ps |
| T467 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3368203516 |
|
|
Mar 05 01:25:10 PM PST 24 |
Mar 05 01:30:30 PM PST 24 |
41271685205 ps |
| T468 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.477851674 |
|
|
Mar 05 01:27:29 PM PST 24 |
Mar 05 01:27:33 PM PST 24 |
1356515788 ps |
| T469 |
/workspace/coverage/default/4.sram_ctrl_partial_access.3675891055 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 01:24:45 PM PST 24 |
3934050214 ps |
| T470 |
/workspace/coverage/default/44.sram_ctrl_smoke.2571223377 |
|
|
Mar 05 01:27:08 PM PST 24 |
Mar 05 01:27:27 PM PST 24 |
1304631555 ps |
| T101 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2992503730 |
|
|
Mar 05 01:24:32 PM PST 24 |
Mar 05 01:25:06 PM PST 24 |
2520056350 ps |
| T471 |
/workspace/coverage/default/27.sram_ctrl_partial_access.1850007937 |
|
|
Mar 05 01:25:24 PM PST 24 |
Mar 05 01:25:40 PM PST 24 |
585969187 ps |
| T472 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4271525540 |
|
|
Mar 05 01:26:27 PM PST 24 |
Mar 05 01:32:37 PM PST 24 |
72667020890 ps |
| T473 |
/workspace/coverage/default/35.sram_ctrl_smoke.3504881330 |
|
|
Mar 05 01:26:10 PM PST 24 |
Mar 05 01:26:15 PM PST 24 |
410923354 ps |
| T474 |
/workspace/coverage/default/4.sram_ctrl_regwen.3244089278 |
|
|
Mar 05 01:24:34 PM PST 24 |
Mar 05 01:40:12 PM PST 24 |
13195930928 ps |
| T475 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.4084488832 |
|
|
Mar 05 01:25:28 PM PST 24 |
Mar 05 01:25:31 PM PST 24 |
347045118 ps |
| T476 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1445251684 |
|
|
Mar 05 01:26:38 PM PST 24 |
Mar 05 01:32:49 PM PST 24 |
4452159131 ps |
| T477 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3814728442 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:31:42 PM PST 24 |
23580822531 ps |
| T478 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.889277759 |
|
|
Mar 05 01:27:22 PM PST 24 |
Mar 05 01:27:25 PM PST 24 |
349676237 ps |
| T479 |
/workspace/coverage/default/38.sram_ctrl_alert_test.2672237523 |
|
|
Mar 05 01:26:27 PM PST 24 |
Mar 05 01:26:29 PM PST 24 |
11747669 ps |
| T102 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.46945603 |
|
|
Mar 05 01:27:39 PM PST 24 |
Mar 05 01:30:38 PM PST 24 |
1617693214 ps |
| T480 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.1744137581 |
|
|
Mar 05 01:24:53 PM PST 24 |
Mar 05 01:28:30 PM PST 24 |
3824741177 ps |
| T481 |
/workspace/coverage/default/6.sram_ctrl_bijection.1647960995 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:33:22 PM PST 24 |
9906702436 ps |
| T482 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.2687414841 |
|
|
Mar 05 01:24:41 PM PST 24 |
Mar 05 01:30:31 PM PST 24 |
121442246099 ps |
| T483 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3316661483 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:25:48 PM PST 24 |
1929069349 ps |
| T484 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3060455167 |
|
|
Mar 05 01:25:12 PM PST 24 |
Mar 05 01:30:43 PM PST 24 |
80980405031 ps |
| T103 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1102456610 |
|
|
Mar 05 01:25:58 PM PST 24 |
Mar 05 01:26:34 PM PST 24 |
9089554913 ps |
| T485 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1573398531 |
|
|
Mar 05 01:27:24 PM PST 24 |
Mar 05 02:32:16 PM PST 24 |
129486121172 ps |
| T104 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3480968096 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 01:26:04 PM PST 24 |
11197012024 ps |
| T486 |
/workspace/coverage/default/5.sram_ctrl_regwen.3758910912 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:50:29 PM PST 24 |
16634575061 ps |
| T487 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.1997038088 |
|
|
Mar 05 01:25:12 PM PST 24 |
Mar 05 01:29:49 PM PST 24 |
40494853245 ps |
| T488 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1997090753 |
|
|
Mar 05 01:26:20 PM PST 24 |
Mar 05 01:28:21 PM PST 24 |
2172805699 ps |
| T489 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.304864835 |
|
|
Mar 05 01:27:15 PM PST 24 |
Mar 05 01:33:40 PM PST 24 |
14191017029 ps |
| T490 |
/workspace/coverage/default/23.sram_ctrl_stress_all.1267965103 |
|
|
Mar 05 01:25:12 PM PST 24 |
Mar 05 02:32:49 PM PST 24 |
239776111994 ps |
| T491 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.323775235 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:26:52 PM PST 24 |
1592666641 ps |
| T492 |
/workspace/coverage/default/19.sram_ctrl_smoke.1722312484 |
|
|
Mar 05 01:25:05 PM PST 24 |
Mar 05 01:25:26 PM PST 24 |
3242008948 ps |
| T493 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3823230101 |
|
|
Mar 05 01:25:21 PM PST 24 |
Mar 05 01:30:12 PM PST 24 |
29322415294 ps |
| T494 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.859337021 |
|
|
Mar 05 01:25:59 PM PST 24 |
Mar 05 01:26:50 PM PST 24 |
2925820156 ps |
| T495 |
/workspace/coverage/default/34.sram_ctrl_bijection.1701381044 |
|
|
Mar 05 01:26:10 PM PST 24 |
Mar 05 01:59:56 PM PST 24 |
112224924465 ps |
| T496 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2647171417 |
|
|
Mar 05 01:24:55 PM PST 24 |
Mar 05 01:27:33 PM PST 24 |
13782289536 ps |
| T497 |
/workspace/coverage/default/11.sram_ctrl_bijection.3166588497 |
|
|
Mar 05 01:24:39 PM PST 24 |
Mar 05 02:03:55 PM PST 24 |
635920217770 ps |
| T498 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.4182144643 |
|
|
Mar 05 01:24:36 PM PST 24 |
Mar 05 01:28:35 PM PST 24 |
3659210833 ps |
| T499 |
/workspace/coverage/default/23.sram_ctrl_alert_test.2815714563 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:25:14 PM PST 24 |
21890741 ps |
| T500 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.3536375198 |
|
|
Mar 05 01:25:00 PM PST 24 |
Mar 05 01:29:12 PM PST 24 |
14976714887 ps |
| T501 |
/workspace/coverage/default/33.sram_ctrl_stress_all.2123026321 |
|
|
Mar 05 01:25:59 PM PST 24 |
Mar 05 04:02:25 PM PST 24 |
2251968019059 ps |
| T502 |
/workspace/coverage/default/38.sram_ctrl_smoke.1955150545 |
|
|
Mar 05 01:26:27 PM PST 24 |
Mar 05 01:26:40 PM PST 24 |
1023135891 ps |
| T503 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1992660057 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:27:50 PM PST 24 |
6535048012 ps |
| T504 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3936563601 |
|
|
Mar 05 01:24:34 PM PST 24 |
Mar 05 01:30:46 PM PST 24 |
23460429411 ps |
| T505 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.240523001 |
|
|
Mar 05 01:27:45 PM PST 24 |
Mar 05 01:27:48 PM PST 24 |
368338556 ps |
| T506 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1770902741 |
|
|
Mar 05 01:24:22 PM PST 24 |
Mar 05 01:26:00 PM PST 24 |
3221623041 ps |
| T507 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3216354293 |
|
|
Mar 05 01:26:46 PM PST 24 |
Mar 05 01:28:02 PM PST 24 |
4899762841 ps |
| T508 |
/workspace/coverage/default/44.sram_ctrl_executable.3022918200 |
|
|
Mar 05 01:27:17 PM PST 24 |
Mar 05 01:44:06 PM PST 24 |
37451947776 ps |
| T509 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2800128646 |
|
|
Mar 05 01:26:49 PM PST 24 |
Mar 05 01:28:14 PM PST 24 |
2983363098 ps |
| T510 |
/workspace/coverage/default/46.sram_ctrl_executable.3578410955 |
|
|
Mar 05 01:27:31 PM PST 24 |
Mar 05 01:37:39 PM PST 24 |
73629687715 ps |
| T105 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2668430507 |
|
|
Mar 05 01:27:47 PM PST 24 |
Mar 05 01:27:57 PM PST 24 |
280312040 ps |
| T26 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1886073822 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 01:24:26 PM PST 24 |
891919983 ps |
| T511 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3457241063 |
|
|
Mar 05 01:27:46 PM PST 24 |
Mar 05 01:28:57 PM PST 24 |
4778198078 ps |
| T512 |
/workspace/coverage/default/44.sram_ctrl_stress_all.1961943896 |
|
|
Mar 05 01:27:18 PM PST 24 |
Mar 05 02:51:39 PM PST 24 |
195755595290 ps |
| T513 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2179855135 |
|
|
Mar 05 01:27:23 PM PST 24 |
Mar 05 01:39:06 PM PST 24 |
32130241003 ps |
| T514 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.4234794006 |
|
|
Mar 05 01:25:25 PM PST 24 |
Mar 05 01:25:40 PM PST 24 |
2957196137 ps |
| T515 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.163907630 |
|
|
Mar 05 01:27:30 PM PST 24 |
Mar 05 01:33:28 PM PST 24 |
5215263559 ps |
| T516 |
/workspace/coverage/default/37.sram_ctrl_alert_test.3245449541 |
|
|
Mar 05 01:26:31 PM PST 24 |
Mar 05 01:26:31 PM PST 24 |
16968689 ps |
| T517 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.145139518 |
|
|
Mar 05 01:24:17 PM PST 24 |
Mar 05 01:26:57 PM PST 24 |
1624667885 ps |
| T518 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2697798119 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:24:27 PM PST 24 |
16712260 ps |
| T519 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.905061219 |
|
|
Mar 05 01:25:27 PM PST 24 |
Mar 05 01:26:55 PM PST 24 |
9247180099 ps |
| T520 |
/workspace/coverage/default/27.sram_ctrl_executable.3982096503 |
|
|
Mar 05 01:25:27 PM PST 24 |
Mar 05 01:46:30 PM PST 24 |
40726050158 ps |
| T521 |
/workspace/coverage/default/5.sram_ctrl_smoke.2680208056 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:25:12 PM PST 24 |
699634436 ps |
| T522 |
/workspace/coverage/default/36.sram_ctrl_regwen.3026342778 |
|
|
Mar 05 01:26:19 PM PST 24 |
Mar 05 01:42:24 PM PST 24 |
10460619143 ps |
| T523 |
/workspace/coverage/default/44.sram_ctrl_alert_test.1942518001 |
|
|
Mar 05 01:27:17 PM PST 24 |
Mar 05 01:27:18 PM PST 24 |
10284129 ps |
| T524 |
/workspace/coverage/default/49.sram_ctrl_regwen.3727711018 |
|
|
Mar 05 01:27:53 PM PST 24 |
Mar 05 01:28:44 PM PST 24 |
590041480 ps |
| T525 |
/workspace/coverage/default/2.sram_ctrl_alert_test.4246914408 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 01:24:25 PM PST 24 |
14066616 ps |
| T526 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.4010800591 |
|
|
Mar 05 01:26:07 PM PST 24 |
Mar 05 01:34:35 PM PST 24 |
14286179718 ps |
| T527 |
/workspace/coverage/default/16.sram_ctrl_stress_all.370570502 |
|
|
Mar 05 01:25:07 PM PST 24 |
Mar 05 02:32:40 PM PST 24 |
341276880809 ps |
| T528 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2212306336 |
|
|
Mar 05 01:27:14 PM PST 24 |
Mar 05 01:33:15 PM PST 24 |
11801701472 ps |
| T529 |
/workspace/coverage/default/2.sram_ctrl_smoke.3835030508 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 01:24:50 PM PST 24 |
4321889226 ps |
| T530 |
/workspace/coverage/default/18.sram_ctrl_bijection.3820566458 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:57:12 PM PST 24 |
92151529989 ps |
| T531 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3536911158 |
|
|
Mar 05 01:25:37 PM PST 24 |
Mar 05 01:30:10 PM PST 24 |
26930816002 ps |
| T532 |
/workspace/coverage/default/9.sram_ctrl_executable.3243906894 |
|
|
Mar 05 01:24:22 PM PST 24 |
Mar 05 01:39:45 PM PST 24 |
6543106814 ps |
| T533 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2893248850 |
|
|
Mar 05 01:25:30 PM PST 24 |
Mar 05 01:33:46 PM PST 24 |
8656061659 ps |
| T534 |
/workspace/coverage/default/5.sram_ctrl_executable.1160769448 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:39:09 PM PST 24 |
13288659079 ps |
| T535 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.536326295 |
|
|
Mar 05 01:24:44 PM PST 24 |
Mar 05 01:24:48 PM PST 24 |
1411653404 ps |
| T536 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.2551348343 |
|
|
Mar 05 01:25:19 PM PST 24 |
Mar 05 01:30:30 PM PST 24 |
18676857781 ps |
| T537 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3476649784 |
|
|
Mar 05 01:27:46 PM PST 24 |
Mar 05 02:41:02 PM PST 24 |
47511103347 ps |
| T538 |
/workspace/coverage/default/10.sram_ctrl_partial_access.3257830958 |
|
|
Mar 05 01:24:42 PM PST 24 |
Mar 05 01:25:08 PM PST 24 |
9047989364 ps |
| T539 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1623749444 |
|
|
Mar 05 01:24:45 PM PST 24 |
Mar 05 01:29:52 PM PST 24 |
8312148521 ps |
| T540 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.30977370 |
|
|
Mar 05 01:27:22 PM PST 24 |
Mar 05 01:29:58 PM PST 24 |
8950771291 ps |
| T541 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.748962874 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 01:25:09 PM PST 24 |
1511049384 ps |