| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.43 | 100.00 | 98.04 | 100.00 | 100.00 | 99.72 | 99.70 | 98.52 |
| T790 | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2119610045 | Mar 05 01:24:28 PM PST 24 | Mar 05 01:24:36 PM PST 24 | 7461632319 ps | ||
| T791 | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1662296074 | Mar 05 01:27:06 PM PST 24 | Mar 05 01:28:04 PM PST 24 | 1533862048 ps | ||
| T792 | /workspace/coverage/default/35.sram_ctrl_max_throughput.523918801 | Mar 05 01:26:10 PM PST 24 | Mar 05 01:26:19 PM PST 24 | 5665272041 ps | ||
| T793 | /workspace/coverage/default/17.sram_ctrl_regwen.1555725078 | Mar 05 01:25:00 PM PST 24 | Mar 05 01:34:03 PM PST 24 | 1522910529 ps | ||
| T794 | /workspace/coverage/default/24.sram_ctrl_multiple_keys.3411712915 | Mar 05 01:25:19 PM PST 24 | Mar 05 01:42:31 PM PST 24 | 24729508504 ps | ||
| T795 | /workspace/coverage/default/3.sram_ctrl_bijection.922187185 | Mar 05 01:24:24 PM PST 24 | Mar 05 01:50:45 PM PST 24 | 23979281993 ps | ||
| T796 | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.36071661 | Mar 05 01:24:43 PM PST 24 | Mar 05 01:25:48 PM PST 24 | 7916930578 ps | ||
| T797 | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2247901984 | Mar 05 01:26:27 PM PST 24 | Mar 05 01:26:34 PM PST 24 | 736883407 ps | ||
| T798 | /workspace/coverage/default/43.sram_ctrl_ram_cfg.96480254 | Mar 05 01:27:06 PM PST 24 | Mar 05 01:27:11 PM PST 24 | 4200308725 ps | ||
| T799 | /workspace/coverage/default/8.sram_ctrl_mem_walk.210237184 | Mar 05 01:24:31 PM PST 24 | Mar 05 01:28:35 PM PST 24 | 4107603120 ps | ||
| T800 | /workspace/coverage/default/45.sram_ctrl_smoke.4035874376 | Mar 05 01:27:15 PM PST 24 | Mar 05 01:28:03 PM PST 24 | 5681714529 ps | ||
| T801 | /workspace/coverage/default/26.sram_ctrl_alert_test.1582918305 | Mar 05 01:25:32 PM PST 24 | Mar 05 01:25:34 PM PST 24 | 42298331 ps | ||
| T802 | /workspace/coverage/default/36.sram_ctrl_partial_access.4263630216 | Mar 05 01:26:18 PM PST 24 | Mar 05 01:26:26 PM PST 24 | 2924743685 ps | ||
| T803 | /workspace/coverage/default/14.sram_ctrl_multiple_keys.1332672562 | Mar 05 01:24:51 PM PST 24 | Mar 05 01:40:18 PM PST 24 | 19158980825 ps | ||
| T804 | /workspace/coverage/default/9.sram_ctrl_ram_cfg.2824358195 | Mar 05 01:24:37 PM PST 24 | Mar 05 01:24:41 PM PST 24 | 2413028447 ps | ||
| T805 | /workspace/coverage/default/38.sram_ctrl_executable.4092120608 | Mar 05 01:26:25 PM PST 24 | Mar 05 01:32:02 PM PST 24 | 5807154355 ps | ||
| T806 | /workspace/coverage/default/42.sram_ctrl_partial_access.3041567979 | Mar 05 01:26:54 PM PST 24 | Mar 05 01:29:26 PM PST 24 | 10748178309 ps | ||
| T807 | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1135653261 | Mar 05 01:24:44 PM PST 24 | Mar 05 01:25:57 PM PST 24 | 1541081808 ps | ||
| T808 | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1857912242 | Mar 05 01:24:41 PM PST 24 | Mar 05 01:26:15 PM PST 24 | 1585635079 ps | ||
| T809 | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3612590782 | Mar 05 01:24:32 PM PST 24 | Mar 05 01:28:29 PM PST 24 | 4105461905 ps | ||
| T810 | /workspace/coverage/default/8.sram_ctrl_bijection.3533680088 | Mar 05 01:24:27 PM PST 24 | Mar 05 02:06:33 PM PST 24 | 115103591403 ps | ||
| T811 | /workspace/coverage/default/31.sram_ctrl_mem_walk.2387372944 | Mar 05 01:25:53 PM PST 24 | Mar 05 01:29:57 PM PST 24 | 15769466962 ps | ||
| T812 | /workspace/coverage/default/29.sram_ctrl_max_throughput.925771988 | Mar 05 01:25:28 PM PST 24 | Mar 05 01:26:37 PM PST 24 | 1624243083 ps | ||
| T813 | /workspace/coverage/default/38.sram_ctrl_partial_access.3942855602 | Mar 05 01:26:27 PM PST 24 | Mar 05 01:26:55 PM PST 24 | 5994103732 ps | ||
| T814 | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.905720190 | Mar 05 01:25:24 PM PST 24 | Mar 05 01:25:37 PM PST 24 | 747932551 ps | ||
| T815 | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.748418240 | Mar 05 01:24:28 PM PST 24 | Mar 05 01:27:09 PM PST 24 | 4420981098 ps | ||
| T816 | /workspace/coverage/default/26.sram_ctrl_multiple_keys.1402760885 | Mar 05 01:25:36 PM PST 24 | Mar 05 01:41:55 PM PST 24 | 7915563241 ps | ||
| T817 | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1025031086 | Mar 05 01:25:00 PM PST 24 | Mar 05 01:26:19 PM PST 24 | 9411998919 ps | ||
| T818 | /workspace/coverage/default/22.sram_ctrl_lc_escalation.4175833298 | Mar 05 01:25:11 PM PST 24 | Mar 05 01:30:29 PM PST 24 | 23590529092 ps | ||
| T819 | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3106234972 | Mar 05 01:24:59 PM PST 24 | Mar 05 01:26:04 PM PST 24 | 996525327 ps | ||
| T820 | /workspace/coverage/default/8.sram_ctrl_lc_escalation.299856649 | Mar 05 01:24:34 PM PST 24 | Mar 05 01:25:20 PM PST 24 | 4618717978 ps | ||
| T821 | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1274901958 | Mar 05 01:25:16 PM PST 24 | Mar 05 01:29:29 PM PST 24 | 8515909824 ps | ||
| T822 | /workspace/coverage/default/31.sram_ctrl_max_throughput.4154501804 | Mar 05 01:25:47 PM PST 24 | Mar 05 01:27:26 PM PST 24 | 1727568955 ps | ||
| T823 | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3039819810 | Mar 05 01:26:17 PM PST 24 | Mar 05 01:28:03 PM PST 24 | 2547090070 ps | ||
| T824 | /workspace/coverage/default/48.sram_ctrl_partial_access.42168715 | Mar 05 01:27:39 PM PST 24 | Mar 05 01:28:09 PM PST 24 | 1026070594 ps | ||
| T825 | /workspace/coverage/default/4.sram_ctrl_alert_test.3051015229 | Mar 05 01:24:24 PM PST 24 | Mar 05 01:24:25 PM PST 24 | 44206389 ps | ||
| T826 | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3465844288 | Mar 05 01:26:32 PM PST 24 | Mar 05 01:28:23 PM PST 24 | 824307380 ps | ||
| T827 | /workspace/coverage/default/30.sram_ctrl_multiple_keys.499787948 | Mar 05 01:25:37 PM PST 24 | Mar 05 01:49:40 PM PST 24 | 136528080421 ps | ||
| T34 | /workspace/coverage/default/3.sram_ctrl_sec_cm.3041284943 | Mar 05 01:24:28 PM PST 24 | Mar 05 01:24:31 PM PST 24 | 299971110 ps | ||
| T828 | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1472237127 | Mar 05 01:24:44 PM PST 24 | Mar 05 01:28:14 PM PST 24 | 12805686106 ps | ||
| T829 | /workspace/coverage/default/39.sram_ctrl_smoke.3445910972 | Mar 05 01:26:27 PM PST 24 | Mar 05 01:26:48 PM PST 24 | 877171055 ps | ||
| T830 | /workspace/coverage/default/33.sram_ctrl_alert_test.198542423 | Mar 05 01:25:59 PM PST 24 | Mar 05 01:26:00 PM PST 24 | 13456055 ps | ||
| T831 | /workspace/coverage/default/12.sram_ctrl_alert_test.2843642895 | Mar 05 01:24:47 PM PST 24 | Mar 05 01:24:48 PM PST 24 | 43678265 ps | ||
| T832 | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4196210059 | Mar 05 01:26:08 PM PST 24 | Mar 05 01:29:10 PM PST 24 | 3231969803 ps | ||
| T833 | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2525330564 | Mar 05 01:25:09 PM PST 24 | Mar 05 01:28:03 PM PST 24 | 13544214013 ps | ||
| T834 | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3529582706 | Mar 05 01:25:15 PM PST 24 | Mar 05 01:26:02 PM PST 24 | 6657258653 ps | ||
| T835 | /workspace/coverage/default/21.sram_ctrl_executable.571414244 | Mar 05 01:25:11 PM PST 24 | Mar 05 01:30:14 PM PST 24 | 2383887386 ps | ||
| T836 | /workspace/coverage/default/25.sram_ctrl_ram_cfg.3266772611 | Mar 05 01:25:23 PM PST 24 | Mar 05 01:25:26 PM PST 24 | 705240052 ps | ||
| T837 | /workspace/coverage/default/13.sram_ctrl_alert_test.3490946944 | Mar 05 01:25:01 PM PST 24 | Mar 05 01:25:03 PM PST 24 | 18570142 ps | ||
| T838 | /workspace/coverage/default/25.sram_ctrl_executable.652838171 | Mar 05 01:25:29 PM PST 24 | Mar 05 01:39:49 PM PST 24 | 88890259376 ps | ||
| T839 | /workspace/coverage/default/5.sram_ctrl_partial_access.938928179 | Mar 05 01:24:30 PM PST 24 | Mar 05 01:27:03 PM PST 24 | 2677973998 ps | ||
| T840 | /workspace/coverage/default/26.sram_ctrl_executable.320670432 | Mar 05 01:25:32 PM PST 24 | Mar 05 01:36:27 PM PST 24 | 60435061103 ps | ||
| T841 | /workspace/coverage/default/25.sram_ctrl_partial_access.3589037262 | Mar 05 01:25:11 PM PST 24 | Mar 05 01:26:01 PM PST 24 | 3090693710 ps | ||
| T842 | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1438113585 | Mar 05 01:25:11 PM PST 24 | Mar 05 01:27:14 PM PST 24 | 1548255153 ps | ||
| T843 | /workspace/coverage/default/10.sram_ctrl_max_throughput.3063034735 | Mar 05 01:24:50 PM PST 24 | Mar 05 01:24:59 PM PST 24 | 685501283 ps | ||
| T844 | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1726628006 | Mar 05 01:24:46 PM PST 24 | Mar 05 01:26:53 PM PST 24 | 2505097100 ps | ||
| T845 | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3435042862 | Mar 05 01:25:36 PM PST 24 | Mar 05 01:37:04 PM PST 24 | 64945561606 ps | ||
| T846 | /workspace/coverage/default/8.sram_ctrl_multiple_keys.2803231196 | Mar 05 01:24:34 PM PST 24 | Mar 05 01:29:36 PM PST 24 | 35106471341 ps | ||
| T847 | /workspace/coverage/default/7.sram_ctrl_partial_access.4148936233 | Mar 05 01:24:41 PM PST 24 | Mar 05 01:25:09 PM PST 24 | 2751779211 ps | ||
| T848 | /workspace/coverage/default/30.sram_ctrl_partial_access.1477968641 | Mar 05 01:25:37 PM PST 24 | Mar 05 01:25:51 PM PST 24 | 6152624202 ps | ||
| T849 | /workspace/coverage/default/37.sram_ctrl_executable.18209550 | Mar 05 01:26:29 PM PST 24 | Mar 05 01:30:39 PM PST 24 | 3229682167 ps | ||
| T850 | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3191814786 | Mar 05 01:26:25 PM PST 24 | Mar 05 01:33:32 PM PST 24 | 73528085340 ps | ||
| T851 | /workspace/coverage/default/31.sram_ctrl_partial_access.2788075854 | Mar 05 01:25:46 PM PST 24 | Mar 05 01:25:56 PM PST 24 | 2672431416 ps | ||
| T852 | /workspace/coverage/default/22.sram_ctrl_multiple_keys.2434292697 | Mar 05 01:25:19 PM PST 24 | Mar 05 01:34:38 PM PST 24 | 13655278743 ps | ||
| T853 | /workspace/coverage/default/12.sram_ctrl_partial_access.3285498866 | Mar 05 01:24:51 PM PST 24 | Mar 05 01:26:15 PM PST 24 | 3173848437 ps | ||
| T854 | /workspace/coverage/default/5.sram_ctrl_stress_all.1168505953 | Mar 05 01:24:31 PM PST 24 | Mar 05 03:39:21 PM PST 24 | 235225127557 ps | ||
| T855 | /workspace/coverage/default/48.sram_ctrl_regwen.3532302745 | Mar 05 01:27:49 PM PST 24 | Mar 05 01:37:56 PM PST 24 | 65720148636 ps | ||
| T55 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.970848269 | Mar 05 12:48:40 PM PST 24 | Mar 05 12:48:41 PM PST 24 | 13943979 ps | ||
| T95 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4014988121 | Mar 05 12:48:58 PM PST 24 | Mar 05 12:49:00 PM PST 24 | 129353005 ps | ||
| T56 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3457124959 | Mar 05 12:48:36 PM PST 24 | Mar 05 12:48:39 PM PST 24 | 174870611 ps | ||
| T96 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2408323364 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:20 PM PST 24 | 258768434 ps | ||
| T97 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4093359337 | Mar 05 12:49:23 PM PST 24 | Mar 05 12:49:24 PM PST 24 | 331761909 ps | ||
| T856 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3833065567 | Mar 05 12:49:22 PM PST 24 | Mar 05 12:49:25 PM PST 24 | 1430496019 ps | ||
| T57 | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4215155316 | Mar 05 12:48:29 PM PST 24 | Mar 05 12:48:30 PM PST 24 | 134727562 ps | ||
| T110 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3802260711 | Mar 05 12:48:36 PM PST 24 | Mar 05 12:48:39 PM PST 24 | 918204591 ps | ||
| T857 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4261747107 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:21 PM PST 24 | 341620372 ps | ||
| T114 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1030282671 | Mar 05 12:48:40 PM PST 24 | Mar 05 12:48:42 PM PST 24 | 372791257 ps | ||
| T58 | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4194852117 | Mar 05 12:48:28 PM PST 24 | Mar 05 12:48:29 PM PST 24 | 47113071 ps | ||
| T858 | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2108961896 | Mar 05 12:48:57 PM PST 24 | Mar 05 12:49:03 PM PST 24 | 354109325 ps | ||
| T859 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1749852794 | Mar 05 12:49:19 PM PST 24 | Mar 05 12:49:23 PM PST 24 | 1411043347 ps | ||
| T860 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1326243672 | Mar 05 12:48:34 PM PST 24 | Mar 05 12:48:38 PM PST 24 | 1422447519 ps | ||
| T861 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2070448497 | Mar 05 12:49:20 PM PST 24 | Mar 05 12:49:22 PM PST 24 | 69235127 ps | ||
| T59 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2861749546 | Mar 05 12:48:29 PM PST 24 | Mar 05 12:48:30 PM PST 24 | 23241858 ps | ||
| T60 | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3499569707 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:44 PM PST 24 | 3787214116 ps | ||
| T92 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3097610019 | Mar 05 12:48:35 PM PST 24 | Mar 05 12:48:37 PM PST 24 | 19573100 ps | ||
| T61 | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.359865402 | Mar 05 12:49:19 PM PST 24 | Mar 05 12:49:20 PM PST 24 | 13841652 ps | ||
| T62 | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1789284158 | Mar 05 12:48:57 PM PST 24 | Mar 05 12:49:28 PM PST 24 | 16078064638 ps | ||
| T111 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.525959522 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:20 PM PST 24 | 445232728 ps | ||
| T93 | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2383979221 | Mar 05 12:49:19 PM PST 24 | Mar 05 12:49:45 PM PST 24 | 3707986747 ps | ||
| T63 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1438667375 | Mar 05 12:48:59 PM PST 24 | Mar 05 12:49:00 PM PST 24 | 11585339 ps | ||
| T862 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.464186167 | Mar 05 12:49:21 PM PST 24 | Mar 05 12:49:22 PM PST 24 | 20664995 ps | ||
| T115 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.537112038 | Mar 05 12:49:23 PM PST 24 | Mar 05 12:49:24 PM PST 24 | 215247366 ps | ||
| T863 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.506238289 | Mar 05 12:48:41 PM PST 24 | Mar 05 12:48:45 PM PST 24 | 375039732 ps | ||
| T864 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4180732292 | Mar 05 12:49:17 PM PST 24 | Mar 05 12:49:21 PM PST 24 | 354166061 ps | ||
| T865 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.621027528 | Mar 05 12:49:17 PM PST 24 | Mar 05 12:49:18 PM PST 24 | 17872963 ps | ||
| T866 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3064682067 | Mar 05 12:48:35 PM PST 24 | Mar 05 12:48:39 PM PST 24 | 397959109 ps | ||
| T64 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3530398075 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:19 PM PST 24 | 19883881 ps | ||
| T867 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3815535588 | Mar 05 12:48:29 PM PST 24 | Mar 05 12:48:31 PM PST 24 | 192873683 ps | ||
| T67 | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.995078237 | Mar 05 12:48:37 PM PST 24 | Mar 05 12:49:01 PM PST 24 | 14804463417 ps | ||
| T84 | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3143901884 | Mar 05 12:48:57 PM PST 24 | Mar 05 12:48:58 PM PST 24 | 58889132 ps | ||
| T868 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.743190185 | Mar 05 12:49:21 PM PST 24 | Mar 05 12:49:24 PM PST 24 | 30853955 ps | ||
| T869 | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.311865981 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:18 PM PST 24 | 82045549 ps | ||
| T870 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.420724239 | Mar 05 12:48:45 PM PST 24 | Mar 05 12:48:46 PM PST 24 | 49622737 ps | ||
| T117 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2544521563 | Mar 05 12:48:28 PM PST 24 | Mar 05 12:48:30 PM PST 24 | 174424397 ps | ||
| T68 | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1254471649 | Mar 05 12:49:23 PM PST 24 | Mar 05 12:49:49 PM PST 24 | 3868355185 ps | ||
| T871 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4197413269 | Mar 05 12:48:19 PM PST 24 | Mar 05 12:48:22 PM PST 24 | 80658238 ps | ||
| T872 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1706468904 | Mar 05 12:48:26 PM PST 24 | Mar 05 12:48:27 PM PST 24 | 15489028 ps | ||
| T873 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2716460414 | Mar 05 12:48:58 PM PST 24 | Mar 05 12:48:59 PM PST 24 | 20964005 ps | ||
| T69 | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1117956405 | Mar 05 12:48:57 PM PST 24 | Mar 05 12:49:21 PM PST 24 | 7802488200 ps | ||
| T874 | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2225804946 | Mar 05 12:49:19 PM PST 24 | Mar 05 12:49:20 PM PST 24 | 91160205 ps | ||
| T70 | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1294980727 | Mar 05 12:48:59 PM PST 24 | Mar 05 12:49:25 PM PST 24 | 3894579036 ps | ||
| T71 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2146547121 | Mar 05 12:48:30 PM PST 24 | Mar 05 12:48:31 PM PST 24 | 63891620 ps | ||
| T875 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2854539698 | Mar 05 12:48:58 PM PST 24 | Mar 05 12:49:03 PM PST 24 | 256263006 ps | ||
| T876 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1317187109 | Mar 05 12:49:19 PM PST 24 | Mar 05 12:49:20 PM PST 24 | 18064965 ps | ||
| T118 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1654882565 | Mar 05 12:49:19 PM PST 24 | Mar 05 12:49:20 PM PST 24 | 298376300 ps | ||
| T72 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1710855156 | Mar 05 12:49:19 PM PST 24 | Mar 05 12:49:20 PM PST 24 | 26433177 ps | ||
| T877 | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3211333902 | Mar 05 12:49:19 PM PST 24 | Mar 05 12:49:20 PM PST 24 | 48290880 ps | ||
| T878 | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2031897092 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:18 PM PST 24 | 16434679 ps | ||
| T879 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.853698615 | Mar 05 12:48:38 PM PST 24 | Mar 05 12:48:40 PM PST 24 | 51968684 ps | ||
| T880 | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2502350950 | Mar 05 12:49:25 PM PST 24 | Mar 05 12:49:26 PM PST 24 | 88204885 ps | ||
| T80 | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2794042114 | Mar 05 12:49:20 PM PST 24 | Mar 05 12:50:09 PM PST 24 | 28157555698 ps | ||
| T881 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1145000885 | Mar 05 12:48:34 PM PST 24 | Mar 05 12:48:37 PM PST 24 | 82608232 ps | ||
| T882 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.724390202 | Mar 05 12:48:57 PM PST 24 | Mar 05 12:49:03 PM PST 24 | 741306792 ps | ||
| T883 | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3328131889 | Mar 05 12:48:40 PM PST 24 | Mar 05 12:48:41 PM PST 24 | 23161937 ps | ||
| T884 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1821451309 | Mar 05 12:48:39 PM PST 24 | Mar 05 12:48:43 PM PST 24 | 1391153944 ps | ||
| T885 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.801641459 | Mar 05 12:49:20 PM PST 24 | Mar 05 12:49:24 PM PST 24 | 387236942 ps | ||
| T121 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2930894139 | Mar 05 12:49:00 PM PST 24 | Mar 05 12:49:03 PM PST 24 | 432717822 ps | ||
| T886 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.962548735 | Mar 05 12:48:37 PM PST 24 | Mar 05 12:48:38 PM PST 24 | 24113210 ps | ||
| T887 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3059855898 | Mar 05 12:49:21 PM PST 24 | Mar 05 12:49:24 PM PST 24 | 1191638535 ps | ||
| T112 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1712425875 | Mar 05 12:49:21 PM PST 24 | Mar 05 12:49:23 PM PST 24 | 474370846 ps | ||
| T888 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.726839337 | Mar 05 12:48:36 PM PST 24 | Mar 05 12:48:40 PM PST 24 | 148603844 ps | ||
| T889 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3726707093 | Mar 05 12:49:00 PM PST 24 | Mar 05 12:49:01 PM PST 24 | 104349408 ps | ||
| T113 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1069445535 | Mar 05 12:49:20 PM PST 24 | Mar 05 12:49:22 PM PST 24 | 92799934 ps | ||
| T890 | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1595748439 | Mar 05 12:49:20 PM PST 24 | Mar 05 12:49:21 PM PST 24 | 24236434 ps | ||
| T891 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2763447245 | Mar 05 12:49:21 PM PST 24 | Mar 05 12:49:23 PM PST 24 | 272616344 ps | ||
| T892 | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.878498712 | Mar 05 12:49:17 PM PST 24 | Mar 05 12:49:17 PM PST 24 | 19293789 ps | ||
| T893 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2285414685 | Mar 05 12:48:29 PM PST 24 | Mar 05 12:48:30 PM PST 24 | 26025215 ps | ||
| T894 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3964972248 | Mar 05 12:48:47 PM PST 24 | Mar 05 12:48:50 PM PST 24 | 157707213 ps | ||
| T895 | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.51360092 | Mar 05 12:48:35 PM PST 24 | Mar 05 12:49:00 PM PST 24 | 3836717456 ps | ||
| T896 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4116476065 | Mar 05 12:49:20 PM PST 24 | Mar 05 12:49:22 PM PST 24 | 329118116 ps | ||
| T897 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3074082613 | Mar 05 12:49:24 PM PST 24 | Mar 05 12:49:30 PM PST 24 | 724847883 ps | ||
| T81 | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1410258769 | Mar 05 12:48:21 PM PST 24 | Mar 05 12:49:07 PM PST 24 | 14698682873 ps | ||
| T898 | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1752807446 | Mar 05 12:48:40 PM PST 24 | Mar 05 12:48:41 PM PST 24 | 18981860 ps | ||
| T899 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3234956586 | Mar 05 12:48:29 PM PST 24 | Mar 05 12:48:30 PM PST 24 | 15103567 ps | ||
| T900 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2705865276 | Mar 05 12:48:35 PM PST 24 | Mar 05 12:48:39 PM PST 24 | 1442282829 ps | ||
| T901 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2323796348 | Mar 05 12:49:21 PM PST 24 | Mar 05 12:49:26 PM PST 24 | 1236147467 ps | ||
| T902 | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3758078136 | Mar 05 12:49:20 PM PST 24 | Mar 05 12:50:07 PM PST 24 | 7213229926 ps | ||
| T903 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2771924580 | Mar 05 12:48:38 PM PST 24 | Mar 05 12:48:39 PM PST 24 | 30592067 ps | ||
| T904 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.240777324 | Mar 05 12:48:58 PM PST 24 | Mar 05 12:49:00 PM PST 24 | 273007149 ps | ||
| T905 | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3252541558 | Mar 05 12:49:23 PM PST 24 | Mar 05 12:49:51 PM PST 24 | 3777344573 ps | ||
| T906 | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.434393923 | Mar 05 12:48:51 PM PST 24 | Mar 05 12:48:52 PM PST 24 | 50990394 ps | ||
| T907 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3220587750 | Mar 05 12:48:40 PM PST 24 | Mar 05 12:48:44 PM PST 24 | 2198948547 ps | ||
| T908 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4174305426 | Mar 05 12:48:59 PM PST 24 | Mar 05 12:49:03 PM PST 24 | 378437706 ps | ||
| T82 | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2367596305 | Mar 05 12:48:57 PM PST 24 | Mar 05 12:49:51 PM PST 24 | 35512201180 ps | ||
| T83 | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2789798416 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:43 PM PST 24 | 4334751725 ps | ||
| T909 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.630572627 | Mar 05 12:48:36 PM PST 24 | Mar 05 12:48:37 PM PST 24 | 29651794 ps | ||
| T910 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2743605451 | Mar 05 12:49:17 PM PST 24 | Mar 05 12:49:21 PM PST 24 | 160790657 ps | ||
| T911 | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3048001972 | Mar 05 12:49:30 PM PST 24 | Mar 05 12:49:32 PM PST 24 | 15967554 ps | ||
| T912 | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4234739332 | Mar 05 12:48:37 PM PST 24 | Mar 05 12:48:38 PM PST 24 | 20116509 ps | ||
| T913 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1105057909 | Mar 05 12:49:23 PM PST 24 | Mar 05 12:49:28 PM PST 24 | 706693367 ps | ||
| T914 | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1650990928 | Mar 05 12:48:26 PM PST 24 | Mar 05 12:49:14 PM PST 24 | 7899900208 ps | ||
| T915 | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1521634017 | Mar 05 12:48:45 PM PST 24 | Mar 05 12:49:14 PM PST 24 | 16779348189 ps | ||
| T916 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.706822727 | Mar 05 12:49:19 PM PST 24 | Mar 05 12:49:23 PM PST 24 | 162698486 ps | ||
| T917 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.871135736 | Mar 05 12:49:19 PM PST 24 | Mar 05 12:49:22 PM PST 24 | 84466181 ps | ||
| T918 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1954353751 | Mar 05 12:48:34 PM PST 24 | Mar 05 12:48:39 PM PST 24 | 489380107 ps | ||
| T919 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4088292125 | Mar 05 12:49:20 PM PST 24 | Mar 05 12:49:23 PM PST 24 | 708630837 ps | ||
| T920 | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.568985476 | Mar 05 12:49:22 PM PST 24 | Mar 05 12:50:18 PM PST 24 | 88001310952 ps | ||
| T921 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4232357408 | Mar 05 12:48:58 PM PST 24 | Mar 05 12:49:02 PM PST 24 | 387243386 ps | ||
| T922 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2479550182 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:19 PM PST 24 | 52494491 ps | ||
| T923 | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.630334779 | Mar 05 12:49:08 PM PST 24 | Mar 05 12:49:09 PM PST 24 | 30397325 ps | ||
| T924 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.768048625 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:20 PM PST 24 | 674948534 ps | ||
| T925 | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1510341074 | Mar 05 12:49:21 PM PST 24 | Mar 05 12:50:20 PM PST 24 | 41377078886 ps | ||
| T926 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.994660582 | Mar 05 12:49:16 PM PST 24 | Mar 05 12:49:17 PM PST 24 | 39882190 ps | ||
| T927 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2181612682 | Mar 05 12:48:29 PM PST 24 | Mar 05 12:48:31 PM PST 24 | 124651591 ps | ||
| T928 | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1600713183 | Mar 05 12:48:58 PM PST 24 | Mar 05 12:48:59 PM PST 24 | 31512630 ps | ||
| T929 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.418673512 | Mar 05 12:48:58 PM PST 24 | Mar 05 12:48:59 PM PST 24 | 15488718 ps | ||
| T930 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.919576716 | Mar 05 12:49:22 PM PST 24 | Mar 05 12:49:25 PM PST 24 | 205029775 ps | ||
| T931 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1203018403 | Mar 05 12:48:36 PM PST 24 | Mar 05 12:48:37 PM PST 24 | 76350506 ps | ||
| T932 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2360968554 | Mar 05 12:48:40 PM PST 24 | Mar 05 12:48:41 PM PST 24 | 28239184 ps | ||
| T933 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1094996198 | Mar 05 12:48:30 PM PST 24 | Mar 05 12:48:33 PM PST 24 | 352249905 ps | ||
| T934 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1131290398 | Mar 05 12:49:20 PM PST 24 | Mar 05 12:49:21 PM PST 24 | 11925136 ps | ||
| T935 | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.51696065 | Mar 05 12:49:23 PM PST 24 | Mar 05 12:50:14 PM PST 24 | 8935479996 ps | ||
| T936 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1733470697 | Mar 05 12:48:58 PM PST 24 | Mar 05 12:49:00 PM PST 24 | 33710446 ps | ||
| T937 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2570037695 | Mar 05 12:48:27 PM PST 24 | Mar 05 12:48:28 PM PST 24 | 16737261 ps | ||
| T938 | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2670345961 | Mar 05 12:49:23 PM PST 24 | Mar 05 12:49:28 PM PST 24 | 1466711802 ps | ||
| T939 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3546916526 | Mar 05 12:49:04 PM PST 24 | Mar 05 12:49:08 PM PST 24 | 63101305 ps | ||
| T940 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2839285917 | Mar 05 12:48:35 PM PST 24 | Mar 05 12:48:36 PM PST 24 | 25516841 ps | ||
| T941 | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1503019801 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:19 PM PST 24 | 25855900 ps | ||
| T942 | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.217596133 | Mar 05 12:48:37 PM PST 24 | Mar 05 12:49:27 PM PST 24 | 10628274720 ps | ||
| T943 | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2242000591 | Mar 05 12:49:23 PM PST 24 | Mar 05 12:49:24 PM PST 24 | 43806014 ps | ||
| T116 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.12370666 | Mar 05 12:48:37 PM PST 24 | Mar 05 12:48:40 PM PST 24 | 635440194 ps | ||
| T944 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2607165691 | Mar 05 12:48:38 PM PST 24 | Mar 05 12:48:39 PM PST 24 | 22441665 ps | ||
| T120 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2523043151 | Mar 05 12:49:21 PM PST 24 | Mar 05 12:49:22 PM PST 24 | 311094166 ps | ||
| T945 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2768683535 | Mar 05 12:48:57 PM PST 24 | Mar 05 12:49:01 PM PST 24 | 71314477 ps | ||
| T946 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1999537615 | Mar 05 12:49:24 PM PST 24 | Mar 05 12:49:29 PM PST 24 | 1288458446 ps | ||
| T947 | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.131243936 | Mar 05 12:49:18 PM PST 24 | Mar 05 12:49:19 PM PST 24 | 19834367 ps | ||
| T948 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1534276594 | Mar 05 12:48:35 PM PST 24 | Mar 05 12:48:38 PM PST 24 | 175424382 ps | ||
| T949 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2910887144 | Mar 05 12:49:23 PM PST 24 | Mar 05 12:49:24 PM PST 24 | 12632712 ps | ||
| T950 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1162935931 | Mar 05 12:49:20 PM PST 24 | Mar 05 12:49:23 PM PST 24 | 47054205 ps | ||
| T951 | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1798579622 | Mar 05 12:49:00 PM PST 24 | Mar 05 12:49:01 PM PST 24 | 32123239 ps | ||
| T952 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1609486459 | Mar 05 12:49:23 PM PST 24 | Mar 05 12:49:26 PM PST 24 | 70537446 ps | ||
| T119 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3510286352 | Mar 05 12:48:58 PM PST 24 | Mar 05 12:49:00 PM PST 24 | 253185575 ps |
| Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.1322135052 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 87922638865 ps |
| CPU time | 5306.2 seconds |
| Started | Mar 05 01:24:36 PM PST 24 |
| Finished | Mar 05 02:53:03 PM PST 24 |
| Peak memory | 386840 kb |
| Host | smart-238f835b-64de-45ed-b23a-3c7b387d4f96 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322135052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.1322135052 |
| Directory | /workspace/6.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.482245513 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1991275085 ps |
| CPU time | 24.28 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:25:38 PM PST 24 |
| Peak memory | 211032 kb |
| Host | smart-62178b26-205c-403b-becd-1d1c942f0195 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=482245513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.482245513 |
| Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2575963321 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 19109640635 ps |
| CPU time | 440.15 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:32:33 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-d4964546-df0a-4063-8cf7-de329bfdea57 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575963321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.2575963321 |
| Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.3634789262 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1856038637 ps |
| CPU time | 3.27 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:24:32 PM PST 24 |
| Peak memory | 221588 kb |
| Host | smart-e92b54f3-8d30-4941-956b-fda347e2ec05 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634789262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3634789262 |
| Directory | /workspace/1.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3802260711 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 918204591 ps |
| CPU time | 2.27 seconds |
| Started | Mar 05 12:48:36 PM PST 24 |
| Finished | Mar 05 12:48:39 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-8d7f130a-6c4d-4ba4-8423-473921973f00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802260711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.3802260711 |
| Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_executable.1251732219 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 20729362669 ps |
| CPU time | 464.32 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:32:55 PM PST 24 |
| Peak memory | 377612 kb |
| Host | smart-b28a48ea-2b06-4f0c-ab5a-01b30e88b44e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251732219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.1251732219 |
| Directory | /workspace/23.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.1529611393 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 21297414 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:25:03 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-03f6bba1-ced9-4480-b354-775f92b8aa4b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529611393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1529611393 |
| Directory | /workspace/10.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1438667375 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 11585339 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 12:48:59 PM PST 24 |
| Finished | Mar 05 12:49:00 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-f9b595e4-37d7-43e4-8324-e69f090dde79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438667375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.1438667375 |
| Directory | /workspace/9.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.2009134845 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 361637236835 ps |
| CPU time | 7809.44 seconds |
| Started | Mar 05 01:24:57 PM PST 24 |
| Finished | Mar 05 03:35:08 PM PST 24 |
| Peak memory | 388944 kb |
| Host | smart-b078912f-2878-4f11-9358-f837b0e3d72d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009134845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.2009134845 |
| Directory | /workspace/12.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3933772800 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 41410255845 ps |
| CPU time | 158.49 seconds |
| Started | Mar 05 01:25:26 PM PST 24 |
| Finished | Mar 05 01:28:05 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-c7119269-ce63-45cf-ba10-87fab692bee5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933772800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.3933772800 |
| Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.136449097 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1354861089 ps |
| CPU time | 3.24 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:25:06 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-e47765d1-183e-4780-a152-a53d636f2b80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136449097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.136449097 |
| Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3510286352 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 253185575 ps |
| CPU time | 1.35 seconds |
| Started | Mar 05 12:48:58 PM PST 24 |
| Finished | Mar 05 12:49:00 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-c88dab99-3cef-4b32-8d60-a5f92a6399e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510286352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.3510286352 |
| Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3480968096 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 11197012024 ps |
| CPU time | 99.19 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:26:04 PM PST 24 |
| Peak memory | 316992 kb |
| Host | smart-5707a74f-59ea-4912-9f2b-fa540737d549 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3480968096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.3480968096 |
| Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_regwen.3482621699 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6618022876 ps |
| CPU time | 948.68 seconds |
| Started | Mar 05 01:25:16 PM PST 24 |
| Finished | Mar 05 01:41:05 PM PST 24 |
| Peak memory | 376696 kb |
| Host | smart-ae1d6530-eea2-4af5-9460-3bfc39737747 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482621699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3482621699 |
| Directory | /workspace/23.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1534276594 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 175424382 ps |
| CPU time | 2.33 seconds |
| Started | Mar 05 12:48:35 PM PST 24 |
| Finished | Mar 05 12:48:38 PM PST 24 |
| Peak memory | 202084 kb |
| Host | smart-4af2512d-8b04-4533-81c8-d8b5fa858ec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534276594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.1534276594 |
| Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2544521563 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 174424397 ps |
| CPU time | 2.02 seconds |
| Started | Mar 05 12:48:28 PM PST 24 |
| Finished | Mar 05 12:48:30 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-57997783-2e26-4b49-bef7-a95adfc15da9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544521563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.2544521563 |
| Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1712425875 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 474370846 ps |
| CPU time | 2.26 seconds |
| Started | Mar 05 12:49:21 PM PST 24 |
| Finished | Mar 05 12:49:23 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-46b3e3ec-41b1-48c9-8f43-3bd849747380 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712425875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.1712425875 |
| Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.12370666 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 635440194 ps |
| CPU time | 2.28 seconds |
| Started | Mar 05 12:48:37 PM PST 24 |
| Finished | Mar 05 12:48:40 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-be798f53-e540-4ed7-9219-ec2f275be176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12370666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.sram_ctrl_tl_intg_err.12370666 |
| Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1410258769 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 14698682873 ps |
| CPU time | 46.05 seconds |
| Started | Mar 05 12:48:21 PM PST 24 |
| Finished | Mar 05 12:49:07 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-08e5c4ac-2e70-49d6-b88e-5ea6a6e2ed4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410258769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1410258769 |
| Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1706468904 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 15489028 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 12:48:26 PM PST 24 |
| Finished | Mar 05 12:48:27 PM PST 24 |
| Peak memory | 202056 kb |
| Host | smart-b20f328a-5fc7-4657-9456-d4621ba6830d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706468904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.1706468904 |
| Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3815535588 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 192873683 ps |
| CPU time | 1.87 seconds |
| Started | Mar 05 12:48:29 PM PST 24 |
| Finished | Mar 05 12:48:31 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-bd6d6b9b-6f24-4353-85bd-c3aee556cb34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815535588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.3815535588 |
| Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2570037695 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 16737261 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 12:48:27 PM PST 24 |
| Finished | Mar 05 12:48:28 PM PST 24 |
| Peak memory | 202060 kb |
| Host | smart-c2c9d365-aa3e-4b59-a231-35e3c90e319c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570037695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.2570037695 |
| Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1326243672 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1422447519 ps |
| CPU time | 3.66 seconds |
| Started | Mar 05 12:48:34 PM PST 24 |
| Finished | Mar 05 12:48:38 PM PST 24 |
| Peak memory | 210412 kb |
| Host | smart-72a63edd-cc6d-4524-8e11-60ed44ecfbc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326243672 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1326243672 |
| Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2861749546 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 23241858 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 12:48:29 PM PST 24 |
| Finished | Mar 05 12:48:30 PM PST 24 |
| Peak memory | 202048 kb |
| Host | smart-0269b222-659c-4eb3-95fc-edc7f3b179ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861749546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.2861749546 |
| Directory | /workspace/0.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4215155316 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 134727562 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 12:48:29 PM PST 24 |
| Finished | Mar 05 12:48:30 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-30f17644-cef3-42e2-800a-5e51afc3b16c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215155316 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.4215155316 |
| Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4197413269 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 80658238 ps |
| CPU time | 2.41 seconds |
| Started | Mar 05 12:48:19 PM PST 24 |
| Finished | Mar 05 12:48:22 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-cfb5b834-0471-45f3-9c1c-a397855e6cd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197413269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.4197413269 |
| Directory | /workspace/0.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2146547121 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 63891620 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 12:48:30 PM PST 24 |
| Finished | Mar 05 12:48:31 PM PST 24 |
| Peak memory | 202060 kb |
| Host | smart-babc749f-36aa-419b-8c08-75b740fa72e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146547121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.2146547121 |
| Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2181612682 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 124651591 ps |
| CPU time | 1.37 seconds |
| Started | Mar 05 12:48:29 PM PST 24 |
| Finished | Mar 05 12:48:31 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-0e94cced-9383-41bf-8909-6b6c8a2f4498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181612682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.2181612682 |
| Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2285414685 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 26025215 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 12:48:29 PM PST 24 |
| Finished | Mar 05 12:48:30 PM PST 24 |
| Peak memory | 202040 kb |
| Host | smart-64d36f69-49f3-4c52-8b4a-48d7e495050b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285414685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2285414685 |
| Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1094996198 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 352249905 ps |
| CPU time | 2.85 seconds |
| Started | Mar 05 12:48:30 PM PST 24 |
| Finished | Mar 05 12:48:33 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-6f4aa8d0-5dd0-41f4-915b-e0810f6ae567 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094996198 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1094996198 |
| Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3234956586 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 15103567 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 12:48:29 PM PST 24 |
| Finished | Mar 05 12:48:30 PM PST 24 |
| Peak memory | 202076 kb |
| Host | smart-21ce24bf-6537-466f-8267-62a3dd9a9b84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234956586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.3234956586 |
| Directory | /workspace/1.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.51360092 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 3836717456 ps |
| CPU time | 24.83 seconds |
| Started | Mar 05 12:48:35 PM PST 24 |
| Finished | Mar 05 12:49:00 PM PST 24 |
| Peak memory | 202156 kb |
| Host | smart-53db0ccf-292b-4560-969c-9dcd31890afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51360092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base _test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.51360092 |
| Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4194852117 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 47113071 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 12:48:28 PM PST 24 |
| Finished | Mar 05 12:48:29 PM PST 24 |
| Peak memory | 201940 kb |
| Host | smart-3001141b-adf2-4a78-8f3c-20eeac0eb411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194852117 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.4194852117 |
| Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1954353751 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 489380107 ps |
| CPU time | 4.31 seconds |
| Started | Mar 05 12:48:34 PM PST 24 |
| Finished | Mar 05 12:48:39 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-535b706a-4345-45e9-87d7-2d1ffa84fddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954353751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.1954353751 |
| Directory | /workspace/1.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1105057909 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 706693367 ps |
| CPU time | 5.22 seconds |
| Started | Mar 05 12:49:23 PM PST 24 |
| Finished | Mar 05 12:49:28 PM PST 24 |
| Peak memory | 210560 kb |
| Host | smart-b1fd8949-e498-44ef-bca0-7e357e93cf0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105057909 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1105057909 |
| Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1710855156 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26433177 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 12:49:19 PM PST 24 |
| Finished | Mar 05 12:49:20 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-babae105-8bdb-493a-9167-4aa2753da655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710855156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.1710855156 |
| Directory | /workspace/10.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2794042114 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 28157555698 ps |
| CPU time | 49.45 seconds |
| Started | Mar 05 12:49:20 PM PST 24 |
| Finished | Mar 05 12:50:09 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-790cd0b8-55fb-4b5b-b810-1912b6504363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794042114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2794042114 |
| Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2225804946 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 91160205 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 12:49:19 PM PST 24 |
| Finished | Mar 05 12:49:20 PM PST 24 |
| Peak memory | 202112 kb |
| Host | smart-88227f7f-90bc-4516-b2f2-ff309d971286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225804946 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2225804946 |
| Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.706822727 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 162698486 ps |
| CPU time | 3.66 seconds |
| Started | Mar 05 12:49:19 PM PST 24 |
| Finished | Mar 05 12:49:23 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-d861e397-1eaf-4a82-925c-848f22269d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706822727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.706822727 |
| Directory | /workspace/10.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1654882565 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 298376300 ps |
| CPU time | 1.36 seconds |
| Started | Mar 05 12:49:19 PM PST 24 |
| Finished | Mar 05 12:49:20 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-abecae85-76ea-41ae-96d1-f51fc06d408e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654882565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.1654882565 |
| Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2670345961 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 1466711802 ps |
| CPU time | 4.85 seconds |
| Started | Mar 05 12:49:23 PM PST 24 |
| Finished | Mar 05 12:49:28 PM PST 24 |
| Peak memory | 210536 kb |
| Host | smart-2e9cbe5a-15db-4110-9fd1-2d38a7d9c154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670345961 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2670345961 |
| Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.131243936 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 19834367 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:19 PM PST 24 |
| Peak memory | 202020 kb |
| Host | smart-9b7adabb-a03e-4069-a88a-563560e73a24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131243936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.sram_ctrl_csr_rw.131243936 |
| Directory | /workspace/11.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3499569707 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3787214116 ps |
| CPU time | 26.22 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:44 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-8b4dbcc5-1ede-4117-959b-9c3fc3af4283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499569707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.3499569707 |
| Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1595748439 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 24236434 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 12:49:20 PM PST 24 |
| Finished | Mar 05 12:49:21 PM PST 24 |
| Peak memory | 202076 kb |
| Host | smart-25c61244-b239-4d87-bd5f-dc398acfd853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595748439 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1595748439 |
| Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2743605451 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 160790657 ps |
| CPU time | 3.81 seconds |
| Started | Mar 05 12:49:17 PM PST 24 |
| Finished | Mar 05 12:49:21 PM PST 24 |
| Peak memory | 202132 kb |
| Host | smart-6b5f534a-f37b-4b9e-a45a-2310ebce75c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743605451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.2743605451 |
| Directory | /workspace/11.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1069445535 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 92799934 ps |
| CPU time | 1.46 seconds |
| Started | Mar 05 12:49:20 PM PST 24 |
| Finished | Mar 05 12:49:22 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-61e52d56-051f-4e9f-b438-672ff7e666e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069445535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.1069445535 |
| Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1749852794 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1411043347 ps |
| CPU time | 3.91 seconds |
| Started | Mar 05 12:49:19 PM PST 24 |
| Finished | Mar 05 12:49:23 PM PST 24 |
| Peak memory | 210612 kb |
| Host | smart-b65b3f07-fb60-4b16-892e-36faa064e8a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749852794 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1749852794 |
| Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2910887144 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 12632712 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 12:49:23 PM PST 24 |
| Finished | Mar 05 12:49:24 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-6922d772-93c7-4bdb-88c6-1a390606eddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910887144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.2910887144 |
| Directory | /workspace/12.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2383979221 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3707986747 ps |
| CPU time | 25.66 seconds |
| Started | Mar 05 12:49:19 PM PST 24 |
| Finished | Mar 05 12:49:45 PM PST 24 |
| Peak memory | 202180 kb |
| Host | smart-1588f332-9d6e-48ad-a6d4-49f055077b79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383979221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2383979221 |
| Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.311865981 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 82045549 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:18 PM PST 24 |
| Peak memory | 202048 kb |
| Host | smart-2c725b90-be57-423b-9a8e-7a5555a33ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311865981 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.311865981 |
| Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1609486459 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 70537446 ps |
| CPU time | 2.48 seconds |
| Started | Mar 05 12:49:23 PM PST 24 |
| Finished | Mar 05 12:49:26 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-db1f99a0-e04c-4422-a6df-38f43ae9bf8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609486459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.1609486459 |
| Directory | /workspace/12.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2408323364 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 258768434 ps |
| CPU time | 1.41 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:20 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-2f6d878c-c063-41ef-ae92-8a74bdf6d94f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408323364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.2408323364 |
| Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4088292125 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 708630837 ps |
| CPU time | 3.6 seconds |
| Started | Mar 05 12:49:20 PM PST 24 |
| Finished | Mar 05 12:49:23 PM PST 24 |
| Peak memory | 211528 kb |
| Host | smart-523431cd-0bdc-429c-b351-ae2be467a42d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088292125 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.4088292125 |
| Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1131290398 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 11925136 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 12:49:20 PM PST 24 |
| Finished | Mar 05 12:49:21 PM PST 24 |
| Peak memory | 202048 kb |
| Host | smart-75718c41-399f-4d5b-a49c-8e44acaaf03b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131290398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.1131290398 |
| Directory | /workspace/13.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3252541558 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 3777344573 ps |
| CPU time | 27.28 seconds |
| Started | Mar 05 12:49:23 PM PST 24 |
| Finished | Mar 05 12:49:51 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-6bc13b00-f698-4f64-b6e9-1a29c880d517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252541558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.3252541558 |
| Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.878498712 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 19293789 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 12:49:17 PM PST 24 |
| Finished | Mar 05 12:49:17 PM PST 24 |
| Peak memory | 202032 kb |
| Host | smart-b23e6f5e-c76e-4d1d-81c2-8460adeeb819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878498712 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.878498712 |
| Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.743190185 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 30853955 ps |
| CPU time | 2.52 seconds |
| Started | Mar 05 12:49:21 PM PST 24 |
| Finished | Mar 05 12:49:24 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-679adc50-0008-44be-a0f8-73edfc14208c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743190185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.743190185 |
| Directory | /workspace/13.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.525959522 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 445232728 ps |
| CPU time | 2.11 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:20 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-cd897d5d-979b-450b-a9f0-c090ebb717c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525959522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.sram_ctrl_tl_intg_err.525959522 |
| Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2323796348 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 1236147467 ps |
| CPU time | 4.48 seconds |
| Started | Mar 05 12:49:21 PM PST 24 |
| Finished | Mar 05 12:49:26 PM PST 24 |
| Peak memory | 210512 kb |
| Host | smart-3bc31739-1742-494f-99d5-c05b2c7fa7a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323796348 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2323796348 |
| Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.994660582 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 39882190 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 12:49:16 PM PST 24 |
| Finished | Mar 05 12:49:17 PM PST 24 |
| Peak memory | 201964 kb |
| Host | smart-67902347-cf1c-43b6-977b-e4bf5e87ee8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994660582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 14.sram_ctrl_csr_rw.994660582 |
| Directory | /workspace/14.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3758078136 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 7213229926 ps |
| CPU time | 46.73 seconds |
| Started | Mar 05 12:49:20 PM PST 24 |
| Finished | Mar 05 12:50:07 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-887fe31d-94f9-4b25-b548-a310c3509100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758078136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3758078136 |
| Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1503019801 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 25855900 ps |
| CPU time | 0.81 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:19 PM PST 24 |
| Peak memory | 202128 kb |
| Host | smart-69f76a84-eef5-4487-8810-1b5b6007f6ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503019801 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1503019801 |
| Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1162935931 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 47054205 ps |
| CPU time | 2.05 seconds |
| Started | Mar 05 12:49:20 PM PST 24 |
| Finished | Mar 05 12:49:23 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-96a8a6c6-28dd-4201-888f-bd996259a65b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162935931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.1162935931 |
| Directory | /workspace/14.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4180732292 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 354166061 ps |
| CPU time | 3.26 seconds |
| Started | Mar 05 12:49:17 PM PST 24 |
| Finished | Mar 05 12:49:21 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-175ca4f6-537c-4d1b-9290-8b10aa3907e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180732292 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.4180732292 |
| Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.464186167 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 20664995 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 12:49:21 PM PST 24 |
| Finished | Mar 05 12:49:22 PM PST 24 |
| Peak memory | 202040 kb |
| Host | smart-59b36202-a116-40f7-ad66-07d37cad493c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464186167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_csr_rw.464186167 |
| Directory | /workspace/15.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.568985476 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 88001310952 ps |
| CPU time | 56.34 seconds |
| Started | Mar 05 12:49:22 PM PST 24 |
| Finished | Mar 05 12:50:18 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-a7657166-c3ec-443b-96a9-4b327b6ff63b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568985476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.568985476 |
| Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3211333902 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 48290880 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 12:49:19 PM PST 24 |
| Finished | Mar 05 12:49:20 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-9114a645-78d7-4721-a793-1fb66f91b9dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211333902 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.3211333902 |
| Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2763447245 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 272616344 ps |
| CPU time | 2.42 seconds |
| Started | Mar 05 12:49:21 PM PST 24 |
| Finished | Mar 05 12:49:23 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-19064528-b458-4abb-8a9f-f9e92da53178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763447245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.2763447245 |
| Directory | /workspace/15.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2523043151 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 311094166 ps |
| CPU time | 1.34 seconds |
| Started | Mar 05 12:49:21 PM PST 24 |
| Finished | Mar 05 12:49:22 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-c93503a7-1c90-4e08-9a8b-61f486b32788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523043151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.2523043151 |
| Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3059855898 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 1191638535 ps |
| CPU time | 3.33 seconds |
| Started | Mar 05 12:49:21 PM PST 24 |
| Finished | Mar 05 12:49:24 PM PST 24 |
| Peak memory | 210332 kb |
| Host | smart-f95efd4b-954e-4da0-bfc3-dc2f141a2b89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059855898 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3059855898 |
| Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2479550182 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 52494491 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:19 PM PST 24 |
| Peak memory | 202100 kb |
| Host | smart-ed9405a6-4eca-4932-966e-7ff83e6310cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479550182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.2479550182 |
| Directory | /workspace/16.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1254471649 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3868355185 ps |
| CPU time | 25.46 seconds |
| Started | Mar 05 12:49:23 PM PST 24 |
| Finished | Mar 05 12:49:49 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-e22eeb01-ad7b-4b84-8b9a-18d67894cbeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254471649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1254471649 |
| Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2031897092 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 16434679 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:18 PM PST 24 |
| Peak memory | 202040 kb |
| Host | smart-fe326b2e-c861-4806-8284-63d7fba3a888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031897092 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2031897092 |
| Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4261747107 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 341620372 ps |
| CPU time | 3.55 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:21 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-6c25ba64-8124-48fe-b55f-08218e03b07b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261747107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.4261747107 |
| Directory | /workspace/16.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.768048625 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 674948534 ps |
| CPU time | 2.38 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:20 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-c6bd6156-f128-4ada-b01f-8fc95303c26f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768048625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.sram_ctrl_tl_intg_err.768048625 |
| Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3833065567 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1430496019 ps |
| CPU time | 3.37 seconds |
| Started | Mar 05 12:49:22 PM PST 24 |
| Finished | Mar 05 12:49:25 PM PST 24 |
| Peak memory | 210208 kb |
| Host | smart-162f0cd7-f825-46fd-8516-a6764728eca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833065567 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3833065567 |
| Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.621027528 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 17872963 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 12:49:17 PM PST 24 |
| Finished | Mar 05 12:49:18 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-23756492-8586-4530-927c-06573791a804 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621027528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.621027528 |
| Directory | /workspace/17.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.51696065 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 8935479996 ps |
| CPU time | 51.4 seconds |
| Started | Mar 05 12:49:23 PM PST 24 |
| Finished | Mar 05 12:50:14 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-2fe31af9-0e33-4c56-b2fd-dcdd17369726 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51696065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base _test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.51696065 |
| Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3048001972 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 15967554 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 12:49:30 PM PST 24 |
| Finished | Mar 05 12:49:32 PM PST 24 |
| Peak memory | 202032 kb |
| Host | smart-a3f9eada-f620-4360-8774-d668443b59e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048001972 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3048001972 |
| Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.871135736 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 84466181 ps |
| CPU time | 2.9 seconds |
| Started | Mar 05 12:49:19 PM PST 24 |
| Finished | Mar 05 12:49:22 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-b7da98b3-98a7-4d80-8d66-9657e6f7d795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871135736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.871135736 |
| Directory | /workspace/17.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4116476065 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 329118116 ps |
| CPU time | 1.49 seconds |
| Started | Mar 05 12:49:20 PM PST 24 |
| Finished | Mar 05 12:49:22 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-ab936965-a67a-4d34-be6b-e7a166d831cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116476065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.4116476065 |
| Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3074082613 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 724847883 ps |
| CPU time | 5.26 seconds |
| Started | Mar 05 12:49:24 PM PST 24 |
| Finished | Mar 05 12:49:30 PM PST 24 |
| Peak memory | 211484 kb |
| Host | smart-b4713b54-8401-4726-8e3d-dec050128753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074082613 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3074082613 |
| Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1317187109 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 18064965 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 12:49:19 PM PST 24 |
| Finished | Mar 05 12:49:20 PM PST 24 |
| Peak memory | 201960 kb |
| Host | smart-c1980540-c391-404d-bb49-ac01eca10b02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317187109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.1317187109 |
| Directory | /workspace/18.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2789798416 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4334751725 ps |
| CPU time | 24.74 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:43 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-74345958-ae35-45bb-a482-89687efc9bbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789798416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.2789798416 |
| Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2242000591 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 43806014 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 12:49:23 PM PST 24 |
| Finished | Mar 05 12:49:24 PM PST 24 |
| Peak memory | 202028 kb |
| Host | smart-6a0436f7-ce90-4775-9ac1-afccc055d721 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242000591 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.2242000591 |
| Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.919576716 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 205029775 ps |
| CPU time | 3.43 seconds |
| Started | Mar 05 12:49:22 PM PST 24 |
| Finished | Mar 05 12:49:25 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-06470096-e735-4df1-9588-b4f7c9355ef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919576716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.919576716 |
| Directory | /workspace/18.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.537112038 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 215247366 ps |
| CPU time | 1.71 seconds |
| Started | Mar 05 12:49:23 PM PST 24 |
| Finished | Mar 05 12:49:24 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-84bc4b81-671d-47ec-96f4-2d30fd3df502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537112038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.sram_ctrl_tl_intg_err.537112038 |
| Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1999537615 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 1288458446 ps |
| CPU time | 4.58 seconds |
| Started | Mar 05 12:49:24 PM PST 24 |
| Finished | Mar 05 12:49:29 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-ddfef5de-8584-4ba3-9e40-7fde18d98410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999537615 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1999537615 |
| Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3530398075 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 19883881 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 12:49:18 PM PST 24 |
| Finished | Mar 05 12:49:19 PM PST 24 |
| Peak memory | 202040 kb |
| Host | smart-5a764f07-f646-4d90-bd12-294a497c58d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530398075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.3530398075 |
| Directory | /workspace/19.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1510341074 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 41377078886 ps |
| CPU time | 58.6 seconds |
| Started | Mar 05 12:49:21 PM PST 24 |
| Finished | Mar 05 12:50:20 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-b56ae873-d230-4511-a39d-de58139f623c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510341074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1510341074 |
| Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2502350950 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 88204885 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 12:49:25 PM PST 24 |
| Finished | Mar 05 12:49:26 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-6e927801-660f-4f52-8754-7b53a5cbc07f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502350950 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2502350950 |
| Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2070448497 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 69235127 ps |
| CPU time | 2.42 seconds |
| Started | Mar 05 12:49:20 PM PST 24 |
| Finished | Mar 05 12:49:22 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-a58ec8bc-0063-4672-9a4d-a1f32e38b526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070448497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.2070448497 |
| Directory | /workspace/19.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4093359337 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 331761909 ps |
| CPU time | 1.62 seconds |
| Started | Mar 05 12:49:23 PM PST 24 |
| Finished | Mar 05 12:49:24 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-29136538-a935-43e8-9475-a8f87beb8f3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093359337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.4093359337 |
| Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.420724239 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 49622737 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 12:48:45 PM PST 24 |
| Finished | Mar 05 12:48:46 PM PST 24 |
| Peak memory | 201992 kb |
| Host | smart-437be5c4-4c56-4a7e-8b19-a5bd12b09b35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420724239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_aliasing.420724239 |
| Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.853698615 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 51968684 ps |
| CPU time | 1.26 seconds |
| Started | Mar 05 12:48:38 PM PST 24 |
| Finished | Mar 05 12:48:40 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-39be0eea-21e2-43d6-b944-ad447329bd78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853698615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.853698615 |
| Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3097610019 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 19573100 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 12:48:35 PM PST 24 |
| Finished | Mar 05 12:48:37 PM PST 24 |
| Peak memory | 202004 kb |
| Host | smart-c7933509-983b-41a1-a413-a4d11196a0ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097610019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.3097610019 |
| Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.506238289 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 375039732 ps |
| CPU time | 3.06 seconds |
| Started | Mar 05 12:48:41 PM PST 24 |
| Finished | Mar 05 12:48:45 PM PST 24 |
| Peak memory | 202112 kb |
| Host | smart-c80264ed-97c1-4bbc-b976-32b5e151b08f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506238289 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.506238289 |
| Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.970848269 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 13943979 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 12:48:40 PM PST 24 |
| Finished | Mar 05 12:48:41 PM PST 24 |
| Peak memory | 202068 kb |
| Host | smart-87464e96-9b98-4dac-8495-e5def6ffa235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970848269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_csr_rw.970848269 |
| Directory | /workspace/2.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1650990928 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 7899900208 ps |
| CPU time | 47.34 seconds |
| Started | Mar 05 12:48:26 PM PST 24 |
| Finished | Mar 05 12:49:14 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-7353a845-2752-4a3a-aa40-3008eccceaa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650990928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1650990928 |
| Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3328131889 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 23161937 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 12:48:40 PM PST 24 |
| Finished | Mar 05 12:48:41 PM PST 24 |
| Peak memory | 202036 kb |
| Host | smart-0aa4c8b0-c043-4ed5-9a18-fab2993cc146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328131889 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3328131889 |
| Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1145000885 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 82608232 ps |
| CPU time | 2.77 seconds |
| Started | Mar 05 12:48:34 PM PST 24 |
| Finished | Mar 05 12:48:37 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-5a7a4fb5-7fb4-42d9-8195-e78e7ccfda81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145000885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.1145000885 |
| Directory | /workspace/2.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.630572627 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 29651794 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 12:48:36 PM PST 24 |
| Finished | Mar 05 12:48:37 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-91cc51d8-d244-424a-9251-6066d8dc1519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630572627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.630572627 |
| Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3457124959 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 174870611 ps |
| CPU time | 2.2 seconds |
| Started | Mar 05 12:48:36 PM PST 24 |
| Finished | Mar 05 12:48:39 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-636abab9-9566-4300-b283-3cb6d6149ef4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457124959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.3457124959 |
| Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2839285917 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 25516841 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 12:48:35 PM PST 24 |
| Finished | Mar 05 12:48:36 PM PST 24 |
| Peak memory | 202096 kb |
| Host | smart-198c4e9b-8ec6-444f-8a1b-189daa9e2569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839285917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.2839285917 |
| Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2705865276 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1442282829 ps |
| CPU time | 3.26 seconds |
| Started | Mar 05 12:48:35 PM PST 24 |
| Finished | Mar 05 12:48:39 PM PST 24 |
| Peak memory | 210320 kb |
| Host | smart-1400a281-b583-4be4-b302-82a4df9581e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705865276 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2705865276 |
| Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2360968554 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 28239184 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 12:48:40 PM PST 24 |
| Finished | Mar 05 12:48:41 PM PST 24 |
| Peak memory | 202020 kb |
| Host | smart-aa8d61f4-0ddb-4161-8324-a8d5dcae749f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360968554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.2360968554 |
| Directory | /workspace/3.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.995078237 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 14804463417 ps |
| CPU time | 24.26 seconds |
| Started | Mar 05 12:48:37 PM PST 24 |
| Finished | Mar 05 12:49:01 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-bd7c0de5-d33b-4e5f-932f-d6d266b6a70f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995078237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.995078237 |
| Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4234739332 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 20116509 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 12:48:37 PM PST 24 |
| Finished | Mar 05 12:48:38 PM PST 24 |
| Peak memory | 202064 kb |
| Host | smart-0d276e2c-7b97-45b8-9df5-3cc968620286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234739332 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.4234739332 |
| Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.726839337 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 148603844 ps |
| CPU time | 2.93 seconds |
| Started | Mar 05 12:48:36 PM PST 24 |
| Finished | Mar 05 12:48:40 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-6368c3f7-05a8-47e1-bc1e-6432fc008a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726839337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.726839337 |
| Directory | /workspace/3.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2607165691 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 22441665 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 12:48:38 PM PST 24 |
| Finished | Mar 05 12:48:39 PM PST 24 |
| Peak memory | 201928 kb |
| Host | smart-b3aa7262-7c6e-42af-a884-347ff417cfcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607165691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.2607165691 |
| Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2771924580 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 30592067 ps |
| CPU time | 1.28 seconds |
| Started | Mar 05 12:48:38 PM PST 24 |
| Finished | Mar 05 12:48:39 PM PST 24 |
| Peak memory | 202128 kb |
| Host | smart-e316188a-5d8f-4809-b1c2-1bdbe9962f55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771924580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.2771924580 |
| Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.962548735 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 24113210 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 12:48:37 PM PST 24 |
| Finished | Mar 05 12:48:38 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-cacfe756-0cc9-4665-881a-819a455a6b68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962548735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_reset.962548735 |
| Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1821451309 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 1391153944 ps |
| CPU time | 3.63 seconds |
| Started | Mar 05 12:48:39 PM PST 24 |
| Finished | Mar 05 12:48:43 PM PST 24 |
| Peak memory | 210328 kb |
| Host | smart-6506f2c7-2dea-4a92-b0f9-f5842bc4db3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821451309 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1821451309 |
| Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1203018403 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 76350506 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 12:48:36 PM PST 24 |
| Finished | Mar 05 12:48:37 PM PST 24 |
| Peak memory | 202132 kb |
| Host | smart-05a42b61-69d2-4b2a-9c71-395b0456d5ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203018403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.1203018403 |
| Directory | /workspace/4.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.217596133 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 10628274720 ps |
| CPU time | 49.71 seconds |
| Started | Mar 05 12:48:37 PM PST 24 |
| Finished | Mar 05 12:49:27 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-4abcc594-d2ae-4af4-bb28-97b893fdb533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217596133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.217596133 |
| Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1752807446 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 18981860 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 12:48:40 PM PST 24 |
| Finished | Mar 05 12:48:41 PM PST 24 |
| Peak memory | 202044 kb |
| Host | smart-6c4ce15b-659c-40b0-9304-65a534acc3f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752807446 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1752807446 |
| Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3064682067 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 397959109 ps |
| CPU time | 3 seconds |
| Started | Mar 05 12:48:35 PM PST 24 |
| Finished | Mar 05 12:48:39 PM PST 24 |
| Peak memory | 210444 kb |
| Host | smart-2e486dc5-b442-471d-9415-454cc20f77d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064682067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.3064682067 |
| Directory | /workspace/4.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1030282671 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 372791257 ps |
| CPU time | 2.22 seconds |
| Started | Mar 05 12:48:40 PM PST 24 |
| Finished | Mar 05 12:48:42 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-000c3a51-3209-4606-ada1-4a391699a4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030282671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.1030282671 |
| Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4232357408 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 387243386 ps |
| CPU time | 3.56 seconds |
| Started | Mar 05 12:48:58 PM PST 24 |
| Finished | Mar 05 12:49:02 PM PST 24 |
| Peak memory | 210636 kb |
| Host | smart-a2d9f88e-d8d7-42b6-88f6-7dc0c01dbadb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232357408 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.4232357408 |
| Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.418673512 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 15488718 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 12:48:58 PM PST 24 |
| Finished | Mar 05 12:48:59 PM PST 24 |
| Peak memory | 202044 kb |
| Host | smart-0931fc2c-1977-4a36-ad49-387cd8420a39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418673512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_csr_rw.418673512 |
| Directory | /workspace/5.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1521634017 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 16779348189 ps |
| CPU time | 28.63 seconds |
| Started | Mar 05 12:48:45 PM PST 24 |
| Finished | Mar 05 12:49:14 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-06ea6307-a917-4b8c-8550-fb4cebc2ca4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521634017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.1521634017 |
| Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1798579622 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 32123239 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 12:49:00 PM PST 24 |
| Finished | Mar 05 12:49:01 PM PST 24 |
| Peak memory | 202056 kb |
| Host | smart-12e98d12-135a-48f5-a68d-4985c95f9322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798579622 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1798579622 |
| Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3220587750 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2198948547 ps |
| CPU time | 4.41 seconds |
| Started | Mar 05 12:48:40 PM PST 24 |
| Finished | Mar 05 12:48:44 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-4ee3f7a9-9399-4b47-b6a4-8d7db2ec783b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220587750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.3220587750 |
| Directory | /workspace/5.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4014988121 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 129353005 ps |
| CPU time | 1.36 seconds |
| Started | Mar 05 12:48:58 PM PST 24 |
| Finished | Mar 05 12:49:00 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-61e5327b-eeb5-4b20-a8d5-3b07a69ff5bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014988121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.4014988121 |
| Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2108961896 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 354109325 ps |
| CPU time | 4.4 seconds |
| Started | Mar 05 12:48:57 PM PST 24 |
| Finished | Mar 05 12:49:03 PM PST 24 |
| Peak memory | 211584 kb |
| Host | smart-0f76f0df-4b57-4e16-9e71-466c50e88b2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108961896 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2108961896 |
| Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.434393923 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 50990394 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 12:48:51 PM PST 24 |
| Finished | Mar 05 12:48:52 PM PST 24 |
| Peak memory | 201904 kb |
| Host | smart-133a7461-63ce-44cd-b19f-e60ad6483123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434393923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 6.sram_ctrl_csr_rw.434393923 |
| Directory | /workspace/6.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1294980727 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3894579036 ps |
| CPU time | 25.1 seconds |
| Started | Mar 05 12:48:59 PM PST 24 |
| Finished | Mar 05 12:49:25 PM PST 24 |
| Peak memory | 202092 kb |
| Host | smart-6de794cc-653b-4d57-bea1-722b902f7a4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294980727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.1294980727 |
| Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1600713183 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 31512630 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 12:48:58 PM PST 24 |
| Finished | Mar 05 12:48:59 PM PST 24 |
| Peak memory | 202012 kb |
| Host | smart-73205f26-99b1-4826-828e-d0bbc7b54132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600713183 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1600713183 |
| Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3964972248 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 157707213 ps |
| CPU time | 2.27 seconds |
| Started | Mar 05 12:48:47 PM PST 24 |
| Finished | Mar 05 12:48:50 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-63faf7f6-5791-4f7c-84d3-c547ad6b1c48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964972248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.3964972248 |
| Directory | /workspace/6.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.240777324 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 273007149 ps |
| CPU time | 1.41 seconds |
| Started | Mar 05 12:48:58 PM PST 24 |
| Finished | Mar 05 12:49:00 PM PST 24 |
| Peak memory | 202084 kb |
| Host | smart-d06cd354-d962-406d-93aa-3c4f790e9642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240777324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 6.sram_ctrl_tl_intg_err.240777324 |
| Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.724390202 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 741306792 ps |
| CPU time | 5.09 seconds |
| Started | Mar 05 12:48:57 PM PST 24 |
| Finished | Mar 05 12:49:03 PM PST 24 |
| Peak memory | 211600 kb |
| Host | smart-1fd35f21-718f-4c89-b1bf-0e427bf90600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724390202 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.724390202 |
| Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1733470697 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 33710446 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 12:48:58 PM PST 24 |
| Finished | Mar 05 12:49:00 PM PST 24 |
| Peak memory | 202048 kb |
| Host | smart-974b86c8-b615-4f97-afee-489c0a7164fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733470697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.1733470697 |
| Directory | /workspace/7.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1117956405 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 7802488200 ps |
| CPU time | 23.86 seconds |
| Started | Mar 05 12:48:57 PM PST 24 |
| Finished | Mar 05 12:49:21 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-7f2f81be-3b85-42df-9730-cbc0a8ff012a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117956405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.1117956405 |
| Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3143901884 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 58889132 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 12:48:57 PM PST 24 |
| Finished | Mar 05 12:48:58 PM PST 24 |
| Peak memory | 201972 kb |
| Host | smart-d53ece1d-9fd7-4292-a42c-4ebe325aa2a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143901884 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3143901884 |
| Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2768683535 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 71314477 ps |
| CPU time | 3.79 seconds |
| Started | Mar 05 12:48:57 PM PST 24 |
| Finished | Mar 05 12:49:01 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-8fdf9a6a-ac40-4b6b-ab6d-8d44f8b8c259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768683535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.2768683535 |
| Directory | /workspace/7.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2930894139 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 432717822 ps |
| CPU time | 2.76 seconds |
| Started | Mar 05 12:49:00 PM PST 24 |
| Finished | Mar 05 12:49:03 PM PST 24 |
| Peak memory | 202160 kb |
| Host | smart-79873efe-dc8e-4a58-a651-8c4de460239b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930894139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.2930894139 |
| Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4174305426 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 378437706 ps |
| CPU time | 3.66 seconds |
| Started | Mar 05 12:48:59 PM PST 24 |
| Finished | Mar 05 12:49:03 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-143d306e-a43a-4e5d-9a37-9052d3260262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174305426 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.4174305426 |
| Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2716460414 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 20964005 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 12:48:58 PM PST 24 |
| Finished | Mar 05 12:48:59 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-c1fce008-ace4-4528-a964-941e78aa459b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716460414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.2716460414 |
| Directory | /workspace/8.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2367596305 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 35512201180 ps |
| CPU time | 52.86 seconds |
| Started | Mar 05 12:48:57 PM PST 24 |
| Finished | Mar 05 12:49:51 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-b19153d6-c8b8-41b1-8e72-c9f92814a447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367596305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.2367596305 |
| Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.630334779 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 30397325 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 12:49:08 PM PST 24 |
| Finished | Mar 05 12:49:09 PM PST 24 |
| Peak memory | 201964 kb |
| Host | smart-cad291b1-df40-40b4-98bd-46dbd389cfdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630334779 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.630334779 |
| Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2854539698 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 256263006 ps |
| CPU time | 4.24 seconds |
| Started | Mar 05 12:48:58 PM PST 24 |
| Finished | Mar 05 12:49:03 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-b9bb6b8a-70cc-4cef-9ebb-421283d000a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854539698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.2854539698 |
| Directory | /workspace/8.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.801641459 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 387236942 ps |
| CPU time | 3.82 seconds |
| Started | Mar 05 12:49:20 PM PST 24 |
| Finished | Mar 05 12:49:24 PM PST 24 |
| Peak memory | 211804 kb |
| Host | smart-fa65f840-b305-4cb7-ad0e-60f1d6794308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801641459 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.801641459 |
| Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1789284158 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 16078064638 ps |
| CPU time | 30.65 seconds |
| Started | Mar 05 12:48:57 PM PST 24 |
| Finished | Mar 05 12:49:28 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-59e1dee8-00d2-45f9-9430-0f342f67bcf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789284158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1789284158 |
| Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.359865402 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 13841652 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 12:49:19 PM PST 24 |
| Finished | Mar 05 12:49:20 PM PST 24 |
| Peak memory | 201960 kb |
| Host | smart-89a5e3b8-4e92-4bdd-8f30-f19aaafa23f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359865402 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.359865402 |
| Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3546916526 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 63101305 ps |
| CPU time | 3.1 seconds |
| Started | Mar 05 12:49:04 PM PST 24 |
| Finished | Mar 05 12:49:08 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-78eeca26-adbe-492f-960c-302aa2198750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546916526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.3546916526 |
| Directory | /workspace/9.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3726707093 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 104349408 ps |
| CPU time | 1.39 seconds |
| Started | Mar 05 12:49:00 PM PST 24 |
| Finished | Mar 05 12:49:01 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-e3f32e81-a01f-4820-b6ac-a97260d7f2c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726707093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.3726707093 |
| Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.3623852675 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 26597615 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 01:24:27 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-48d92d4b-2281-431f-8713-3a6d46e6041a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623852675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3623852675 |
| Directory | /workspace/0.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_bijection.2988148293 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 113101235536 ps |
| CPU time | 1640.88 seconds |
| Started | Mar 05 01:24:19 PM PST 24 |
| Finished | Mar 05 01:51:40 PM PST 24 |
| Peak memory | 202856 kb |
| Host | smart-1f0ca4de-3588-4909-a8d7-a4e5abaee291 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988148293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 2988148293 |
| Directory | /workspace/0.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_executable.2623836770 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 4675026476 ps |
| CPU time | 225.22 seconds |
| Started | Mar 05 01:24:29 PM PST 24 |
| Finished | Mar 05 01:28:15 PM PST 24 |
| Peak memory | 365268 kb |
| Host | smart-ab87f6d3-bb84-449f-98ed-7063fa62f9f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623836770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.2623836770 |
| Directory | /workspace/0.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.108121078 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2071158923 ps |
| CPU time | 96.25 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 01:26:01 PM PST 24 |
| Peak memory | 338700 kb |
| Host | smart-58a8e03d-db88-4ec0-8f88-04afc234271f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108121078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.sram_ctrl_max_throughput.108121078 |
| Directory | /workspace/0.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3814643781 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 10160862350 ps |
| CPU time | 77.98 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:25:42 PM PST 24 |
| Peak memory | 210976 kb |
| Host | smart-41b6da6f-fc9f-4e4e-b0a3-cc5e0b0151d8 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814643781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.3814643781 |
| Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.4262499387 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 60815006308 ps |
| CPU time | 160.5 seconds |
| Started | Mar 05 01:24:21 PM PST 24 |
| Finished | Mar 05 01:27:02 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-15c32075-78a3-450c-9ed6-0f70eb15dbb1 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262499387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.4262499387 |
| Directory | /workspace/0.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.2486685656 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 62176054684 ps |
| CPU time | 1042.74 seconds |
| Started | Mar 05 01:24:15 PM PST 24 |
| Finished | Mar 05 01:41:38 PM PST 24 |
| Peak memory | 378668 kb |
| Host | smart-99fc9798-11d3-41fa-81b8-327357ca2e05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486685656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.2486685656 |
| Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.1442614172 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4315082811 ps |
| CPU time | 127.84 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:26:35 PM PST 24 |
| Peak memory | 362164 kb |
| Host | smart-99bc8b9e-99a9-4232-8882-17088954efb6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442614172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.1442614172 |
| Directory | /workspace/0.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2222901800 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 6589260421 ps |
| CPU time | 307.53 seconds |
| Started | Mar 05 01:24:12 PM PST 24 |
| Finished | Mar 05 01:29:20 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-1554e64e-cdab-477d-90b0-724028f3d243 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222901800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.2222901800 |
| Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.1323575632 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1409634560 ps |
| CPU time | 3.22 seconds |
| Started | Mar 05 01:24:23 PM PST 24 |
| Finished | Mar 05 01:24:26 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-8bd6b59f-0de7-4c6a-ab2d-50dbb8803abc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323575632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1323575632 |
| Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_regwen.3911934791 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3854983670 ps |
| CPU time | 187.5 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:27:31 PM PST 24 |
| Peak memory | 373684 kb |
| Host | smart-384dbb1c-5f5a-4ae7-8064-7e40a39b447b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911934791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3911934791 |
| Directory | /workspace/0.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.3801244234 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 122802071 ps |
| CPU time | 1.89 seconds |
| Started | Mar 05 01:24:15 PM PST 24 |
| Finished | Mar 05 01:24:17 PM PST 24 |
| Peak memory | 221692 kb |
| Host | smart-a5bbefee-3ce0-41f8-b639-417669dd5e46 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801244234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3801244234 |
| Directory | /workspace/0.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_smoke.577593859 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1189597884 ps |
| CPU time | 91.68 seconds |
| Started | Mar 05 01:24:31 PM PST 24 |
| Finished | Mar 05 01:26:03 PM PST 24 |
| Peak memory | 339712 kb |
| Host | smart-77c39ab9-abb9-4f24-b882-5df3aed11719 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577593859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.577593859 |
| Directory | /workspace/0.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.2661507597 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 917270810698 ps |
| CPU time | 5792.66 seconds |
| Started | Mar 05 01:25:03 PM PST 24 |
| Finished | Mar 05 03:01:37 PM PST 24 |
| Peak memory | 380732 kb |
| Host | smart-e54009de-406a-462e-9fa4-ec62e064bc1f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661507597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.2661507597 |
| Directory | /workspace/0.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3433033122 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5738890569 ps |
| CPU time | 149.35 seconds |
| Started | Mar 05 01:24:21 PM PST 24 |
| Finished | Mar 05 01:26:50 PM PST 24 |
| Peak memory | 202824 kb |
| Host | smart-55f177d1-baea-474c-b212-8466597fb635 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433033122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.3433033122 |
| Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1770902741 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 3221623041 ps |
| CPU time | 98.54 seconds |
| Started | Mar 05 01:24:22 PM PST 24 |
| Finished | Mar 05 01:26:00 PM PST 24 |
| Peak memory | 360244 kb |
| Host | smart-e8cba647-8bb2-49ad-9911-19809b7a2bc4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770902741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1770902741 |
| Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.2571482783 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 37178862 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:24:28 PM PST 24 |
| Peak memory | 202112 kb |
| Host | smart-2a5ff31a-c444-4568-8e9b-8ff5e2f1a32a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571482783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2571482783 |
| Directory | /workspace/1.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_bijection.1168174380 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 127232988714 ps |
| CPU time | 2291.6 seconds |
| Started | Mar 05 01:24:15 PM PST 24 |
| Finished | Mar 05 02:02:27 PM PST 24 |
| Peak memory | 202872 kb |
| Host | smart-fb26fb98-98a7-47c6-a87d-f04567b22a80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168174380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 1168174380 |
| Directory | /workspace/1.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_executable.1975672470 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 2899016605 ps |
| CPU time | 245.44 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:28:30 PM PST 24 |
| Peak memory | 370476 kb |
| Host | smart-48ffc8bc-defd-4916-9434-8df09ab3aba1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975672470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.1975672470 |
| Directory | /workspace/1.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.1501549356 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 3585919534 ps |
| CPU time | 14.42 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:24:41 PM PST 24 |
| Peak memory | 211016 kb |
| Host | smart-3c5b1d38-dc04-42bc-93bc-022d235e92d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501549356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.1501549356 |
| Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.323775235 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1592666641 ps |
| CPU time | 144.52 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:26:52 PM PST 24 |
| Peak memory | 369340 kb |
| Host | smart-7fb28831-878e-4a99-97fd-a8363450f042 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323775235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.sram_ctrl_max_throughput.323775235 |
| Directory | /workspace/1.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2193680787 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4783511372 ps |
| CPU time | 72.98 seconds |
| Started | Mar 05 01:24:22 PM PST 24 |
| Finished | Mar 05 01:25:35 PM PST 24 |
| Peak memory | 211012 kb |
| Host | smart-27d0e8ac-9ab3-4161-8694-8756547f53b5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193680787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.2193680787 |
| Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.1152283517 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 20854662185 ps |
| CPU time | 309.79 seconds |
| Started | Mar 05 01:24:12 PM PST 24 |
| Finished | Mar 05 01:29:22 PM PST 24 |
| Peak memory | 202840 kb |
| Host | smart-d6ba26da-613a-4b43-8a51-94c7cbe3c93a |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152283517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.1152283517 |
| Directory | /workspace/1.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.2896880058 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 17530939305 ps |
| CPU time | 875.23 seconds |
| Started | Mar 05 01:24:23 PM PST 24 |
| Finished | Mar 05 01:38:59 PM PST 24 |
| Peak memory | 377616 kb |
| Host | smart-c3490a1d-5512-4f5c-854f-186f5f902543 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896880058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.2896880058 |
| Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.643476442 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 607674983 ps |
| CPU time | 16.98 seconds |
| Started | Mar 05 01:24:11 PM PST 24 |
| Finished | Mar 05 01:24:28 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-1043a1b0-3e13-460d-ad11-ac7f74936fc1 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643476442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sr am_ctrl_partial_access.643476442 |
| Directory | /workspace/1.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2439397558 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 48127647759 ps |
| CPU time | 530.45 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:33:14 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-63823dcb-7e85-400b-a42d-4c0357baa409 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439397558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.2439397558 |
| Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.665887058 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1612047526 ps |
| CPU time | 3.17 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 01:24:29 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-86bc8f7d-da26-465f-8ac8-a91f741e73f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665887058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.665887058 |
| Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_regwen.2900539962 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2552382350 ps |
| CPU time | 17.11 seconds |
| Started | Mar 05 01:24:19 PM PST 24 |
| Finished | Mar 05 01:24:36 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-1691c96a-d286-4ffd-9de6-4c0dfc5c0d4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900539962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2900539962 |
| Directory | /workspace/1.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_smoke.2092095079 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 3252489930 ps |
| CPU time | 8.49 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:24:33 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-0488f24f-6812-4507-81c0-b2e283b83ad3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092095079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2092095079 |
| Directory | /workspace/1.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.145139518 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1624667885 ps |
| CPU time | 159.61 seconds |
| Started | Mar 05 01:24:17 PM PST 24 |
| Finished | Mar 05 01:26:57 PM PST 24 |
| Peak memory | 354084 kb |
| Host | smart-a223944b-33f6-4949-96eb-1bbd179a1ead |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=145139518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.145139518 |
| Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1513539536 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 59393037858 ps |
| CPU time | 330.58 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 01:29:56 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-ff3e1a4e-1442-45ed-b583-5a271656d55e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513539536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.1513539536 |
| Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1090289940 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1490662438 ps |
| CPU time | 45.5 seconds |
| Started | Mar 05 01:24:23 PM PST 24 |
| Finished | Mar 05 01:25:09 PM PST 24 |
| Peak memory | 309600 kb |
| Host | smart-0554a980-5caf-4df8-b1de-1171a6d5ec9f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090289940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.1090289940 |
| Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_bijection.1437029094 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 234640956800 ps |
| CPU time | 1969.05 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:57:30 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-61ffaef6-5d3f-4382-856e-ce59fa54efd4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437029094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .1437029094 |
| Directory | /workspace/10.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_executable.765400056 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 14462726457 ps |
| CPU time | 816.53 seconds |
| Started | Mar 05 01:24:32 PM PST 24 |
| Finished | Mar 05 01:38:08 PM PST 24 |
| Peak memory | 378708 kb |
| Host | smart-134fd735-b5d7-451d-9e05-c55a0fc47ae8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765400056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executabl e.765400056 |
| Directory | /workspace/10.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.2464405208 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3523760437 ps |
| CPU time | 41.43 seconds |
| Started | Mar 05 01:24:37 PM PST 24 |
| Finished | Mar 05 01:25:19 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-ddd138f2-be6a-41ff-ba25-41987b863ac7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464405208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.2464405208 |
| Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.3063034735 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 685501283 ps |
| CPU time | 8.28 seconds |
| Started | Mar 05 01:24:50 PM PST 24 |
| Finished | Mar 05 01:24:59 PM PST 24 |
| Peak memory | 220032 kb |
| Host | smart-dece1152-989e-4d19-9153-a95e2017b4db |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063034735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.3063034735 |
| Directory | /workspace/10.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3064644194 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4510931848 ps |
| CPU time | 150.06 seconds |
| Started | Mar 05 01:24:32 PM PST 24 |
| Finished | Mar 05 01:27:02 PM PST 24 |
| Peak memory | 210980 kb |
| Host | smart-cfc7362a-34df-4796-9f4c-b78569786f1c |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064644194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.3064644194 |
| Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.2687414841 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 121442246099 ps |
| CPU time | 350.31 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:30:31 PM PST 24 |
| Peak memory | 203020 kb |
| Host | smart-7be3ecce-be31-44c6-99f8-311f5ef825b1 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687414841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.2687414841 |
| Directory | /workspace/10.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.1623749444 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 8312148521 ps |
| CPU time | 306.73 seconds |
| Started | Mar 05 01:24:45 PM PST 24 |
| Finished | Mar 05 01:29:52 PM PST 24 |
| Peak memory | 360400 kb |
| Host | smart-b0f99138-7879-44d6-934b-eb96e67309d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623749444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.1623749444 |
| Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.3257830958 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 9047989364 ps |
| CPU time | 25.23 seconds |
| Started | Mar 05 01:24:42 PM PST 24 |
| Finished | Mar 05 01:25:08 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-942bc436-83f1-4630-97ee-9742281aa8d8 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257830958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.3257830958 |
| Directory | /workspace/10.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3163432202 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 23134890882 ps |
| CPU time | 511.62 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:33:13 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-260b7ae4-a96a-45d6-9e9b-d3f0151bb17e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163432202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.3163432202 |
| Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.1054055814 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 711591936 ps |
| CPU time | 3.31 seconds |
| Started | Mar 05 01:24:37 PM PST 24 |
| Finished | Mar 05 01:24:41 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-e3cfa1a1-2e0f-446a-a33c-7565fd626acb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054055814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1054055814 |
| Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_regwen.1995744621 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3378170665 ps |
| CPU time | 676.65 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:35:44 PM PST 24 |
| Peak memory | 373016 kb |
| Host | smart-e08ba716-47eb-4157-ad49-454fe9284afb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995744621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1995744621 |
| Directory | /workspace/10.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_smoke.3948056342 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 799240667 ps |
| CPU time | 14.82 seconds |
| Started | Mar 05 01:24:35 PM PST 24 |
| Finished | Mar 05 01:24:50 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-b5978807-eb77-4288-befd-8f49dc7d1db6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948056342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3948056342 |
| Directory | /workspace/10.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.651376769 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 41995062957 ps |
| CPU time | 2875.46 seconds |
| Started | Mar 05 01:24:45 PM PST 24 |
| Finished | Mar 05 02:12:41 PM PST 24 |
| Peak memory | 373444 kb |
| Host | smart-42a26998-1d89-4471-9643-e35a40f25b4e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651376769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_stress_all.651376769 |
| Directory | /workspace/10.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.893617356 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1732545385 ps |
| CPU time | 138.42 seconds |
| Started | Mar 05 01:24:38 PM PST 24 |
| Finished | Mar 05 01:26:57 PM PST 24 |
| Peak memory | 346772 kb |
| Host | smart-4d29db75-3a30-47c8-b2fa-03d343abc04c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=893617356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.893617356 |
| Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.529780656 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 3069840598 ps |
| CPU time | 177.42 seconds |
| Started | Mar 05 01:24:37 PM PST 24 |
| Finished | Mar 05 01:27:35 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-c6cdd592-ca79-48fd-8063-c6eedb7dd82b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529780656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_stress_pipeline.529780656 |
| Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3932014159 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1863305331 ps |
| CPU time | 35.19 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:25:21 PM PST 24 |
| Peak memory | 284432 kb |
| Host | smart-534cc091-c7e6-4f94-8e6a-0050451a1cfa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932014159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.3932014159 |
| Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.3366116642 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 22791435 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:24:33 PM PST 24 |
| Finished | Mar 05 01:24:33 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-99cc8bc4-392c-44e0-b714-fab45372deed |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366116642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3366116642 |
| Directory | /workspace/11.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_bijection.3166588497 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 635920217770 ps |
| CPU time | 2356 seconds |
| Started | Mar 05 01:24:39 PM PST 24 |
| Finished | Mar 05 02:03:55 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-34ce6390-dd41-409b-9c4f-9bb6131d5351 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166588497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .3166588497 |
| Directory | /workspace/11.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_executable.2934654507 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 66872964900 ps |
| CPU time | 1131.62 seconds |
| Started | Mar 05 01:24:45 PM PST 24 |
| Finished | Mar 05 01:43:37 PM PST 24 |
| Peak memory | 377432 kb |
| Host | smart-404fa9fa-180b-4120-88dc-b082bf01187f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934654507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.2934654507 |
| Directory | /workspace/11.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.1550529081 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 12452703776 ps |
| CPU time | 199.38 seconds |
| Started | Mar 05 01:24:40 PM PST 24 |
| Finished | Mar 05 01:28:00 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-e8a318a7-5b52-455b-8752-ed0f34c590ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550529081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1550529081 |
| Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.559530147 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 767974204 ps |
| CPU time | 54.34 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:25:36 PM PST 24 |
| Peak memory | 306648 kb |
| Host | smart-0bacd80d-b5d4-4275-a5c2-4f0f1d70a7b4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559530147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.sram_ctrl_max_throughput.559530147 |
| Directory | /workspace/11.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.338022587 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 9783042812 ps |
| CPU time | 146.4 seconds |
| Started | Mar 05 01:24:32 PM PST 24 |
| Finished | Mar 05 01:26:59 PM PST 24 |
| Peak memory | 211012 kb |
| Host | smart-92027d4a-7df4-48dc-b64b-87d42accf571 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338022587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .sram_ctrl_mem_partial_access.338022587 |
| Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.2052256143 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 108672495487 ps |
| CPU time | 305.5 seconds |
| Started | Mar 05 01:24:44 PM PST 24 |
| Finished | Mar 05 01:29:50 PM PST 24 |
| Peak memory | 203020 kb |
| Host | smart-9639036d-8c6d-43f3-836a-bdfd0161ecc9 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052256143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.2052256143 |
| Directory | /workspace/11.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.1663980856 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 45182881166 ps |
| CPU time | 1271.81 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:45:40 PM PST 24 |
| Peak memory | 371980 kb |
| Host | smart-e80b4c93-fd06-424d-be05-0599fce87de6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663980856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.1663980856 |
| Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.3006710078 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 516569788 ps |
| CPU time | 11.96 seconds |
| Started | Mar 05 01:24:59 PM PST 24 |
| Finished | Mar 05 01:25:12 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-13631a6a-ad09-4786-9f45-1a581d85aab3 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006710078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.3006710078 |
| Directory | /workspace/11.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3121813244 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 51736584749 ps |
| CPU time | 270.49 seconds |
| Started | Mar 05 01:24:44 PM PST 24 |
| Finished | Mar 05 01:29:15 PM PST 24 |
| Peak memory | 202808 kb |
| Host | smart-87f9dd82-5b54-4646-80af-a402fa151009 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121813244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.3121813244 |
| Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.2269743514 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 361955413 ps |
| CPU time | 3.23 seconds |
| Started | Mar 05 01:24:32 PM PST 24 |
| Finished | Mar 05 01:24:35 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-74b7774f-3f39-495e-9932-bd38ea2fd3f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269743514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2269743514 |
| Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_regwen.2827599894 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 55460878118 ps |
| CPU time | 1119.28 seconds |
| Started | Mar 05 01:24:55 PM PST 24 |
| Finished | Mar 05 01:43:35 PM PST 24 |
| Peak memory | 378476 kb |
| Host | smart-dd9d69bf-70d6-4838-91d9-f15ae12a4df2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827599894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2827599894 |
| Directory | /workspace/11.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_smoke.3274384413 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 962961882 ps |
| CPU time | 6.86 seconds |
| Started | Mar 05 01:24:54 PM PST 24 |
| Finished | Mar 05 01:25:01 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-78949270-d894-4b0e-9299-a0d49ccd713a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274384413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3274384413 |
| Directory | /workspace/11.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.2650807285 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 285579771762 ps |
| CPU time | 5679.4 seconds |
| Started | Mar 05 01:24:34 PM PST 24 |
| Finished | Mar 05 02:59:14 PM PST 24 |
| Peak memory | 378420 kb |
| Host | smart-e532b820-9f12-4abb-9e7f-a048c0105857 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650807285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.2650807285 |
| Directory | /workspace/11.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1472237127 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 12805686106 ps |
| CPU time | 210.31 seconds |
| Started | Mar 05 01:24:44 PM PST 24 |
| Finished | Mar 05 01:28:14 PM PST 24 |
| Peak memory | 326976 kb |
| Host | smart-b313a043-d405-476a-b291-7ed624c675d2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1472237127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1472237127 |
| Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3142455123 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 19412546955 ps |
| CPU time | 260.77 seconds |
| Started | Mar 05 01:24:49 PM PST 24 |
| Finished | Mar 05 01:29:10 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-e36e123d-27b0-409b-9f49-f95579a9ebdb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142455123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.3142455123 |
| Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1857912242 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1585635079 ps |
| CPU time | 93.45 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:26:15 PM PST 24 |
| Peak memory | 335620 kb |
| Host | smart-c6b4ff40-fb97-4a66-9140-e164c6cf17f5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857912242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.1857912242 |
| Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.2843642895 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 43678265 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 01:24:47 PM PST 24 |
| Finished | Mar 05 01:24:48 PM PST 24 |
| Peak memory | 202064 kb |
| Host | smart-8921e556-fbe0-4dd9-946c-3aa17c30f92c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843642895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.2843642895 |
| Directory | /workspace/12.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_bijection.1720465282 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 979519604710 ps |
| CPU time | 1811.46 seconds |
| Started | Mar 05 01:24:45 PM PST 24 |
| Finished | Mar 05 01:54:57 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-50240261-729e-4b85-9df4-30e98858ba56 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720465282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .1720465282 |
| Directory | /workspace/12.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_executable.3419423155 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 33201486180 ps |
| CPU time | 825.6 seconds |
| Started | Mar 05 01:24:55 PM PST 24 |
| Finished | Mar 05 01:38:41 PM PST 24 |
| Peak memory | 371604 kb |
| Host | smart-51f4d15e-e07d-40dd-91e8-ae69690204d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419423155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.3419423155 |
| Directory | /workspace/12.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.3789986854 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 5618146599 ps |
| CPU time | 87.1 seconds |
| Started | Mar 05 01:24:49 PM PST 24 |
| Finished | Mar 05 01:26:16 PM PST 24 |
| Peak memory | 210868 kb |
| Host | smart-b0cf31b4-2d8c-4f7b-b606-383c36140e66 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789986854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.3789986854 |
| Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.1412054118 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 6925039540 ps |
| CPU time | 124.33 seconds |
| Started | Mar 05 01:24:49 PM PST 24 |
| Finished | Mar 05 01:26:53 PM PST 24 |
| Peak memory | 366232 kb |
| Host | smart-698e80e0-c2a0-45af-946e-a6e1a530e7a7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412054118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.1412054118 |
| Directory | /workspace/12.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1125807734 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 7835234968 ps |
| CPU time | 74.65 seconds |
| Started | Mar 05 01:24:55 PM PST 24 |
| Finished | Mar 05 01:26:10 PM PST 24 |
| Peak memory | 211032 kb |
| Host | smart-3cc8f0f8-9d42-4c8f-ae8d-04a653180072 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125807734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.1125807734 |
| Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.3695231009 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 14064796309 ps |
| CPU time | 293.32 seconds |
| Started | Mar 05 01:24:54 PM PST 24 |
| Finished | Mar 05 01:29:48 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-92af9c79-bf2f-4162-9f6a-7a107acd15fb |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695231009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.3695231009 |
| Directory | /workspace/12.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.3481966596 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 38378032926 ps |
| CPU time | 548.62 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:33:49 PM PST 24 |
| Peak memory | 372560 kb |
| Host | smart-81425467-09ad-4847-8eff-f6a37b21051c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481966596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.3481966596 |
| Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.3285498866 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 3173848437 ps |
| CPU time | 84.37 seconds |
| Started | Mar 05 01:24:51 PM PST 24 |
| Finished | Mar 05 01:26:15 PM PST 24 |
| Peak memory | 349972 kb |
| Host | smart-e1febaac-afde-4583-9760-8589c17dcf4a |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285498866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.3285498866 |
| Directory | /workspace/12.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1391263690 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 22914043329 ps |
| CPU time | 296.87 seconds |
| Started | Mar 05 01:24:49 PM PST 24 |
| Finished | Mar 05 01:29:46 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-30664ff7-9d3c-4efe-b274-7bdcd79e4c1f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391263690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.1391263690 |
| Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.1469537854 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1607704504 ps |
| CPU time | 3.05 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:24:45 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-772b6f3d-14bf-4787-9b2b-0291098a6b78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469537854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1469537854 |
| Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_regwen.2286633312 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3483277278 ps |
| CPU time | 987.25 seconds |
| Started | Mar 05 01:24:59 PM PST 24 |
| Finished | Mar 05 01:41:26 PM PST 24 |
| Peak memory | 379704 kb |
| Host | smart-ebdf4580-4a44-4edb-98ce-849bf6be90fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286633312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2286633312 |
| Directory | /workspace/12.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_smoke.1928950959 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 995306225 ps |
| CPU time | 110.64 seconds |
| Started | Mar 05 01:24:36 PM PST 24 |
| Finished | Mar 05 01:26:27 PM PST 24 |
| Peak memory | 351784 kb |
| Host | smart-4a226913-e2ab-448e-a18e-adcb0b5a9707 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928950959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1928950959 |
| Directory | /workspace/12.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2114607062 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 1778300624 ps |
| CPU time | 39.12 seconds |
| Started | Mar 05 01:24:58 PM PST 24 |
| Finished | Mar 05 01:25:38 PM PST 24 |
| Peak memory | 213524 kb |
| Host | smart-d8b91192-87ed-4037-85dd-6c5c50023f45 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2114607062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2114607062 |
| Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1541995369 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 6714655254 ps |
| CPU time | 205.71 seconds |
| Started | Mar 05 01:24:34 PM PST 24 |
| Finished | Mar 05 01:28:00 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-0620d740-2b25-41a5-8af0-f2be3d8c4789 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541995369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.1541995369 |
| Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4225445031 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 704868331 ps |
| CPU time | 6.1 seconds |
| Started | Mar 05 01:24:36 PM PST 24 |
| Finished | Mar 05 01:24:42 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-9da62107-b890-4e6e-abc7-8d4abd9272d0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225445031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.4225445031 |
| Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.3490946944 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 18570142 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:25:03 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-58f52304-940a-41a9-9038-9c2838997ef4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490946944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3490946944 |
| Directory | /workspace/13.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_bijection.2382140551 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 87521523357 ps |
| CPU time | 1936.03 seconds |
| Started | Mar 05 01:24:45 PM PST 24 |
| Finished | Mar 05 01:57:01 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-d5ca17ac-46fc-41f9-9dd5-2e7ab5f7f8d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382140551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .2382140551 |
| Directory | /workspace/13.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_executable.2752705354 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 8160405230 ps |
| CPU time | 1317.36 seconds |
| Started | Mar 05 01:24:51 PM PST 24 |
| Finished | Mar 05 01:46:49 PM PST 24 |
| Peak memory | 371416 kb |
| Host | smart-a2e0c24d-c9cf-4c2f-b89d-86cc90d33735 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752705354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.2752705354 |
| Directory | /workspace/13.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.2647171417 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 13782289536 ps |
| CPU time | 157.55 seconds |
| Started | Mar 05 01:24:55 PM PST 24 |
| Finished | Mar 05 01:27:33 PM PST 24 |
| Peak memory | 210968 kb |
| Host | smart-0efdfad3-616e-4ada-aa1d-2aab1508bb69 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647171417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.2647171417 |
| Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.3843019882 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 780219103 ps |
| CPU time | 25.43 seconds |
| Started | Mar 05 01:24:49 PM PST 24 |
| Finished | Mar 05 01:25:15 PM PST 24 |
| Peak memory | 276564 kb |
| Host | smart-081a444a-a6f9-45c2-ae33-d7aa9f68c3e7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843019882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.3843019882 |
| Directory | /workspace/13.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.4142313126 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 20374212472 ps |
| CPU time | 137.73 seconds |
| Started | Mar 05 01:24:54 PM PST 24 |
| Finished | Mar 05 01:27:12 PM PST 24 |
| Peak memory | 210956 kb |
| Host | smart-3adc59a1-b9fb-4fba-ae17-2df61f7fb741 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142313126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.4142313126 |
| Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.3765673346 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 8966870234 ps |
| CPU time | 144.93 seconds |
| Started | Mar 05 01:24:55 PM PST 24 |
| Finished | Mar 05 01:27:20 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-b964493e-bd49-4296-8f46-0bbeed96a4c0 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765673346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.3765673346 |
| Directory | /workspace/13.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.1822741231 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13723144430 ps |
| CPU time | 695.3 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:36:37 PM PST 24 |
| Peak memory | 373600 kb |
| Host | smart-3cb09b02-2c36-4042-b6af-4175e70d33b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822741231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.1822741231 |
| Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.2485885754 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 6449712845 ps |
| CPU time | 27.92 seconds |
| Started | Mar 05 01:24:54 PM PST 24 |
| Finished | Mar 05 01:25:22 PM PST 24 |
| Peak memory | 262856 kb |
| Host | smart-84c35fee-dfee-4c97-a26a-9e8d8499dcaa |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485885754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.2485885754 |
| Directory | /workspace/13.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.809696867 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 26454717401 ps |
| CPU time | 395.19 seconds |
| Started | Mar 05 01:25:03 PM PST 24 |
| Finished | Mar 05 01:31:39 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-e7b40ee1-7d0b-4ea8-a2ac-a6bf8273fe0f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809696867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.sram_ctrl_partial_access_b2b.809696867 |
| Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_smoke.3985334645 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3985451553 ps |
| CPU time | 33.6 seconds |
| Started | Mar 05 01:24:47 PM PST 24 |
| Finished | Mar 05 01:25:20 PM PST 24 |
| Peak memory | 280484 kb |
| Host | smart-de37d4be-48f0-4b7a-9ce6-eac919f2ca16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985334645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3985334645 |
| Directory | /workspace/13.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.943093668 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 202372622202 ps |
| CPU time | 2977.51 seconds |
| Started | Mar 05 01:24:38 PM PST 24 |
| Finished | Mar 05 02:14:16 PM PST 24 |
| Peak memory | 386908 kb |
| Host | smart-d6fe71ba-d1db-47d9-bde3-be13e71d50f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943093668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_stress_all.943093668 |
| Directory | /workspace/13.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3189168907 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 2251814897 ps |
| CPU time | 166.49 seconds |
| Started | Mar 05 01:24:43 PM PST 24 |
| Finished | Mar 05 01:27:30 PM PST 24 |
| Peak memory | 370608 kb |
| Host | smart-34a1754c-71c9-4213-a754-7bee115b478f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3189168907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3189168907 |
| Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.857809158 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4756669097 ps |
| CPU time | 204.13 seconds |
| Started | Mar 05 01:24:44 PM PST 24 |
| Finished | Mar 05 01:28:09 PM PST 24 |
| Peak memory | 202824 kb |
| Host | smart-97ccd87d-91da-4319-b386-fe3ba544db2b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857809158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13 .sram_ctrl_stress_pipeline.857809158 |
| Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.316588057 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 2814325674 ps |
| CPU time | 7.51 seconds |
| Started | Mar 05 01:24:49 PM PST 24 |
| Finished | Mar 05 01:24:56 PM PST 24 |
| Peak memory | 219072 kb |
| Host | smart-e97d1588-65d8-4933-9b6c-ceafafca0a40 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316588057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_throughput_w_partial_write.316588057 |
| Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.4063769063 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 43130304 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 01:25:05 PM PST 24 |
| Finished | Mar 05 01:25:06 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-7f3a080b-d009-4fcf-b245-ee77f42a7ce1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063769063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.4063769063 |
| Directory | /workspace/14.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_bijection.3976726548 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 460878568919 ps |
| CPU time | 1499.28 seconds |
| Started | Mar 05 01:24:58 PM PST 24 |
| Finished | Mar 05 01:49:57 PM PST 24 |
| Peak memory | 203020 kb |
| Host | smart-e978a649-b8ea-41ff-bed8-8f661a1f6192 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976726548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .3976726548 |
| Directory | /workspace/14.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_executable.852711929 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 7102945413 ps |
| CPU time | 584.83 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:34:56 PM PST 24 |
| Peak memory | 367260 kb |
| Host | smart-d381e00a-b86f-473d-bc89-c470e015aa27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852711929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executabl e.852711929 |
| Directory | /workspace/14.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.3536375198 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 14976714887 ps |
| CPU time | 252.02 seconds |
| Started | Mar 05 01:25:00 PM PST 24 |
| Finished | Mar 05 01:29:12 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-1922b410-a38f-4fd3-b36a-796280a4f1a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536375198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.3536375198 |
| Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.2296452475 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 5585155955 ps |
| CPU time | 64.28 seconds |
| Started | Mar 05 01:24:44 PM PST 24 |
| Finished | Mar 05 01:25:48 PM PST 24 |
| Peak memory | 305968 kb |
| Host | smart-16865b42-40f2-4a7d-b992-1661e79fcab6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296452475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.2296452475 |
| Directory | /workspace/14.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3702852480 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 2441366882 ps |
| CPU time | 75.96 seconds |
| Started | Mar 05 01:25:03 PM PST 24 |
| Finished | Mar 05 01:26:20 PM PST 24 |
| Peak memory | 211020 kb |
| Host | smart-9c0e922f-d47e-4f1d-9e0d-3a7879ae8802 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702852480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.3702852480 |
| Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.968809275 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 55062998479 ps |
| CPU time | 284.72 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:29:47 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-ae947ea6-de52-4f46-b820-9d35f7e413be |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968809275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _mem_walk.968809275 |
| Directory | /workspace/14.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.1332672562 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 19158980825 ps |
| CPU time | 926.84 seconds |
| Started | Mar 05 01:24:51 PM PST 24 |
| Finished | Mar 05 01:40:18 PM PST 24 |
| Peak memory | 377652 kb |
| Host | smart-d7d3b1bd-f0ce-4cfe-9f35-82cade8acae0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332672562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.1332672562 |
| Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.407531720 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1391192458 ps |
| CPU time | 19.54 seconds |
| Started | Mar 05 01:24:52 PM PST 24 |
| Finished | Mar 05 01:25:11 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-f4b9d2ea-e2d7-4c8f-90be-dabbadb77060 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407531720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s ram_ctrl_partial_access.407531720 |
| Directory | /workspace/14.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2521257131 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 12888538041 ps |
| CPU time | 388.61 seconds |
| Started | Mar 05 01:24:56 PM PST 24 |
| Finished | Mar 05 01:31:25 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-537271e4-f745-4a56-b09d-32c9e0fdf628 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521257131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.2521257131 |
| Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.385703463 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 683660940 ps |
| CPU time | 3.29 seconds |
| Started | Mar 05 01:25:00 PM PST 24 |
| Finished | Mar 05 01:25:04 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-6296f525-aac7-47c0-9ad5-c599b1faa946 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385703463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.385703463 |
| Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_regwen.3546596206 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5484945131 ps |
| CPU time | 145.85 seconds |
| Started | Mar 05 01:25:07 PM PST 24 |
| Finished | Mar 05 01:27:33 PM PST 24 |
| Peak memory | 345840 kb |
| Host | smart-e84443a9-0747-4dc9-b1ca-5712604ef317 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546596206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3546596206 |
| Directory | /workspace/14.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_smoke.3824667194 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3556474734 ps |
| CPU time | 20.32 seconds |
| Started | Mar 05 01:24:46 PM PST 24 |
| Finished | Mar 05 01:25:07 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-dcde6dfb-98de-4125-a185-e908bd2dcc7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824667194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3824667194 |
| Directory | /workspace/14.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3319711739 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1292297616 ps |
| CPU time | 98.55 seconds |
| Started | Mar 05 01:25:00 PM PST 24 |
| Finished | Mar 05 01:26:40 PM PST 24 |
| Peak memory | 315248 kb |
| Host | smart-f6d11fb0-7824-4bc3-a47e-025e7b7f161c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3319711739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3319711739 |
| Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.189636687 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 5162210057 ps |
| CPU time | 161.89 seconds |
| Started | Mar 05 01:24:47 PM PST 24 |
| Finished | Mar 05 01:27:29 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-65b3ac3e-1425-425d-9411-27cd503ce571 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189636687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14 .sram_ctrl_stress_pipeline.189636687 |
| Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1135653261 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1541081808 ps |
| CPU time | 72.08 seconds |
| Started | Mar 05 01:24:44 PM PST 24 |
| Finished | Mar 05 01:25:57 PM PST 24 |
| Peak memory | 328748 kb |
| Host | smart-dcd2167c-2514-442b-8d0a-89b8d05ec36d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135653261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1135653261 |
| Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.3171769784 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 21273158 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:25:05 PM PST 24 |
| Finished | Mar 05 01:25:07 PM PST 24 |
| Peak memory | 202072 kb |
| Host | smart-b70ad42d-d00f-4b74-a973-c7f553790baf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171769784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.3171769784 |
| Directory | /workspace/15.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_bijection.2261784413 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 15394655638 ps |
| CPU time | 1000.67 seconds |
| Started | Mar 05 01:24:59 PM PST 24 |
| Finished | Mar 05 01:41:40 PM PST 24 |
| Peak memory | 203016 kb |
| Host | smart-d69076aa-55fd-4132-80ee-d8ec8d5ca4ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261784413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .2261784413 |
| Directory | /workspace/15.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.1824571211 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 45004337644 ps |
| CPU time | 343.3 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:30:55 PM PST 24 |
| Peak memory | 210864 kb |
| Host | smart-d9acf78c-ed78-427a-bd50-a3531f37c0c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824571211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.1824571211 |
| Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.3447225696 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 764580709 ps |
| CPU time | 139.37 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:27:21 PM PST 24 |
| Peak memory | 365328 kb |
| Host | smart-362b47b3-7c57-4130-b83e-05773810b151 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447225696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.3447225696 |
| Directory | /workspace/15.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1025031086 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 9411998919 ps |
| CPU time | 76.77 seconds |
| Started | Mar 05 01:25:00 PM PST 24 |
| Finished | Mar 05 01:26:19 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-eca6833a-430f-4f12-a719-ac30aeac31e5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025031086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.1025031086 |
| Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.4019671768 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 18766660772 ps |
| CPU time | 228.97 seconds |
| Started | Mar 05 01:25:05 PM PST 24 |
| Finished | Mar 05 01:28:54 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-bc279ac7-1521-4aae-a1f1-a7542e2ce373 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019671768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.4019671768 |
| Directory | /workspace/15.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.4230615517 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 130841083603 ps |
| CPU time | 1617.41 seconds |
| Started | Mar 05 01:25:02 PM PST 24 |
| Finished | Mar 05 01:52:00 PM PST 24 |
| Peak memory | 378672 kb |
| Host | smart-a0d081f5-5168-42d2-b052-a5e2f9471182 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230615517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.4230615517 |
| Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.1787777585 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 909337973 ps |
| CPU time | 13.7 seconds |
| Started | Mar 05 01:25:08 PM PST 24 |
| Finished | Mar 05 01:25:22 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-b1642c0f-c525-4214-a154-5c77d7e0da9a |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787777585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.1787777585 |
| Directory | /workspace/15.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.3378070783 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1301694509 ps |
| CPU time | 3.18 seconds |
| Started | Mar 05 01:25:05 PM PST 24 |
| Finished | Mar 05 01:25:09 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-0279dd5c-d330-442a-a3bc-436ed2fac9be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378070783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3378070783 |
| Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_regwen.823523588 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3151034504 ps |
| CPU time | 1157.94 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:44:20 PM PST 24 |
| Peak memory | 376556 kb |
| Host | smart-36425616-2e6d-4f59-8f6b-8629bc5e553e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823523588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.823523588 |
| Directory | /workspace/15.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_smoke.2812067138 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1081104249 ps |
| CPU time | 43.26 seconds |
| Started | Mar 05 01:25:05 PM PST 24 |
| Finished | Mar 05 01:25:49 PM PST 24 |
| Peak memory | 299800 kb |
| Host | smart-1cebe397-50c3-4bd6-92cb-f126653c8bec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812067138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2812067138 |
| Directory | /workspace/15.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.96339213 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 66997068511 ps |
| CPU time | 5858.69 seconds |
| Started | Mar 05 01:25:02 PM PST 24 |
| Finished | Mar 05 03:02:42 PM PST 24 |
| Peak memory | 387888 kb |
| Host | smart-89f57f45-944f-4b30-82fe-061e2740f913 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96339213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.sram_ctrl_stress_all.96339213 |
| Directory | /workspace/15.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.723065715 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 2744043840 ps |
| CPU time | 36.04 seconds |
| Started | Mar 05 01:25:06 PM PST 24 |
| Finished | Mar 05 01:25:42 PM PST 24 |
| Peak memory | 211060 kb |
| Host | smart-c55f97a7-bfda-4467-90c8-04a04adecdaf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=723065715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.723065715 |
| Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1180082625 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 9403735314 ps |
| CPU time | 156.73 seconds |
| Started | Mar 05 01:25:04 PM PST 24 |
| Finished | Mar 05 01:27:42 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-b2b0743d-6c05-49db-8f9b-44f539ba8b3e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180082625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.1180082625 |
| Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2494498874 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 5174046127 ps |
| CPU time | 7.92 seconds |
| Started | Mar 05 01:25:04 PM PST 24 |
| Finished | Mar 05 01:25:13 PM PST 24 |
| Peak memory | 212132 kb |
| Host | smart-d7cf9409-0705-42e2-8b5e-de8816561c38 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494498874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2494498874 |
| Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.3297815394 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 20861277 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:25:03 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-93d0863f-4c5f-4e8e-81aa-c0ee3b15237f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297815394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3297815394 |
| Directory | /workspace/16.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_bijection.3731432070 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 66950218997 ps |
| CPU time | 1129.2 seconds |
| Started | Mar 05 01:25:08 PM PST 24 |
| Finished | Mar 05 01:43:58 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-8cc3f17f-38ef-42ec-80e2-6f6e820e8618 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731432070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .3731432070 |
| Directory | /workspace/16.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_executable.1389150705 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 7800947483 ps |
| CPU time | 966.09 seconds |
| Started | Mar 05 01:25:00 PM PST 24 |
| Finished | Mar 05 01:41:07 PM PST 24 |
| Peak memory | 375500 kb |
| Host | smart-7065ae81-6ec8-466d-9bc1-25ecf1a20291 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389150705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.1389150705 |
| Directory | /workspace/16.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.845055244 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 35959088658 ps |
| CPU time | 378.93 seconds |
| Started | Mar 05 01:25:00 PM PST 24 |
| Finished | Mar 05 01:31:20 PM PST 24 |
| Peak memory | 210972 kb |
| Host | smart-4bd567b6-f0bb-4063-8ab8-f24319cbf546 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845055244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_esc alation.845055244 |
| Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.4125519266 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1520936769 ps |
| CPU time | 73.49 seconds |
| Started | Mar 05 01:24:58 PM PST 24 |
| Finished | Mar 05 01:26:11 PM PST 24 |
| Peak memory | 340720 kb |
| Host | smart-183eaf95-344f-4b32-b21f-32d07b58637b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125519266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.4125519266 |
| Directory | /workspace/16.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1023702304 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 20329240683 ps |
| CPU time | 153.32 seconds |
| Started | Mar 05 01:24:59 PM PST 24 |
| Finished | Mar 05 01:27:33 PM PST 24 |
| Peak memory | 210984 kb |
| Host | smart-f0ffef35-06d2-447f-999f-00e01d5caa3c |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023702304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.1023702304 |
| Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.2555678102 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 8040425228 ps |
| CPU time | 254.91 seconds |
| Started | Mar 05 01:25:00 PM PST 24 |
| Finished | Mar 05 01:29:17 PM PST 24 |
| Peak memory | 202872 kb |
| Host | smart-ea6e7dfe-b85f-4fc2-aa5e-0a07b0013982 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555678102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.2555678102 |
| Directory | /workspace/16.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.1421570849 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 11738239492 ps |
| CPU time | 563.02 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:34:25 PM PST 24 |
| Peak memory | 341792 kb |
| Host | smart-1bd678c2-1b73-4466-8195-7a24803ff388 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421570849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.1421570849 |
| Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.3035290360 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 553748073 ps |
| CPU time | 125.04 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:27:07 PM PST 24 |
| Peak memory | 351980 kb |
| Host | smart-48a31726-600b-4db1-aa07-eaacb2faeeb8 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035290360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.3035290360 |
| Directory | /workspace/16.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2084225606 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 36878782473 ps |
| CPU time | 389.36 seconds |
| Started | Mar 05 01:24:59 PM PST 24 |
| Finished | Mar 05 01:31:29 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-0b32c64b-724e-4143-ac41-3c3a6f980be3 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084225606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.2084225606 |
| Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.2462340752 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 345848196 ps |
| CPU time | 2.96 seconds |
| Started | Mar 05 01:25:08 PM PST 24 |
| Finished | Mar 05 01:25:11 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-a3b675f0-757d-4c93-8c2c-15872445d487 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462340752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2462340752 |
| Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_regwen.84127582 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 31898922674 ps |
| CPU time | 1206.94 seconds |
| Started | Mar 05 01:24:58 PM PST 24 |
| Finished | Mar 05 01:45:05 PM PST 24 |
| Peak memory | 377816 kb |
| Host | smart-806d6615-dd22-46df-ae32-ea8a608d6ce8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84127582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.84127582 |
| Directory | /workspace/16.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_smoke.153220162 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2819118892 ps |
| CPU time | 53.63 seconds |
| Started | Mar 05 01:24:58 PM PST 24 |
| Finished | Mar 05 01:25:52 PM PST 24 |
| Peak memory | 302064 kb |
| Host | smart-155e9710-5050-4c7e-81a1-60bf9e823824 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153220162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.153220162 |
| Directory | /workspace/16.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.370570502 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 341276880809 ps |
| CPU time | 4052.87 seconds |
| Started | Mar 05 01:25:07 PM PST 24 |
| Finished | Mar 05 02:32:40 PM PST 24 |
| Peak memory | 374276 kb |
| Host | smart-7ac0c644-2943-417b-978c-5f73d1ad7099 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370570502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_stress_all.370570502 |
| Directory | /workspace/16.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2240336900 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 3387941870 ps |
| CPU time | 24.25 seconds |
| Started | Mar 05 01:25:02 PM PST 24 |
| Finished | Mar 05 01:25:27 PM PST 24 |
| Peak memory | 211056 kb |
| Host | smart-c587cd0c-6475-4f2e-a9fb-d4df0ff7fe68 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2240336900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.2240336900 |
| Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1744137581 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 3824741177 ps |
| CPU time | 216.6 seconds |
| Started | Mar 05 01:24:53 PM PST 24 |
| Finished | Mar 05 01:28:30 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-31a7033e-9be5-40ee-a21c-d9476c7a265a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744137581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.1744137581 |
| Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3080299786 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3127183258 ps |
| CPU time | 89.26 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:26:32 PM PST 24 |
| Peak memory | 325488 kb |
| Host | smart-88eaa3fc-06e9-4f6b-b791-8566a4e365cd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080299786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.3080299786 |
| Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.235595167 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 15043118 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:25:07 PM PST 24 |
| Finished | Mar 05 01:25:08 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-9c7189dd-5e80-4d13-8136-0ac7d0a17e42 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235595167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.235595167 |
| Directory | /workspace/17.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_bijection.1751334081 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 79217714731 ps |
| CPU time | 1762.82 seconds |
| Started | Mar 05 01:25:03 PM PST 24 |
| Finished | Mar 05 01:54:27 PM PST 24 |
| Peak memory | 202984 kb |
| Host | smart-75d9cd36-eccb-4aec-8311-15f30be42957 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751334081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .1751334081 |
| Directory | /workspace/17.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_executable.4208285915 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 17364816494 ps |
| CPU time | 723.21 seconds |
| Started | Mar 05 01:25:03 PM PST 24 |
| Finished | Mar 05 01:37:07 PM PST 24 |
| Peak memory | 376624 kb |
| Host | smart-7e7e659a-b997-457a-90e4-136f5cbaddde |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208285915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.4208285915 |
| Directory | /workspace/17.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.486700802 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 5764295935 ps |
| CPU time | 95.92 seconds |
| Started | Mar 05 01:25:05 PM PST 24 |
| Finished | Mar 05 01:26:42 PM PST 24 |
| Peak memory | 215552 kb |
| Host | smart-46224abb-8453-4f8e-834a-19e0835ab2cb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486700802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esc alation.486700802 |
| Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.643760824 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 718625422 ps |
| CPU time | 7.05 seconds |
| Started | Mar 05 01:24:52 PM PST 24 |
| Finished | Mar 05 01:25:00 PM PST 24 |
| Peak memory | 219052 kb |
| Host | smart-bb11db69-5f13-463a-9481-34d71b199747 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643760824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.sram_ctrl_max_throughput.643760824 |
| Directory | /workspace/17.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3106234972 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 996525327 ps |
| CPU time | 64.68 seconds |
| Started | Mar 05 01:24:59 PM PST 24 |
| Finished | Mar 05 01:26:04 PM PST 24 |
| Peak memory | 210956 kb |
| Host | smart-9e4127de-b1cb-4daf-96ee-54e60aeb8043 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106234972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.3106234972 |
| Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.3060455167 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 80980405031 ps |
| CPU time | 330.63 seconds |
| Started | Mar 05 01:25:12 PM PST 24 |
| Finished | Mar 05 01:30:43 PM PST 24 |
| Peak memory | 202904 kb |
| Host | smart-93067045-56d3-49d5-a19c-ba8311a7abf9 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060455167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.3060455167 |
| Directory | /workspace/17.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.492870156 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 122826521553 ps |
| CPU time | 726.37 seconds |
| Started | Mar 05 01:25:04 PM PST 24 |
| Finished | Mar 05 01:37:11 PM PST 24 |
| Peak memory | 371524 kb |
| Host | smart-6c0b11aa-513c-412f-9eae-c98eb0151651 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492870156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multip le_keys.492870156 |
| Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.3394121401 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4175554753 ps |
| CPU time | 25.51 seconds |
| Started | Mar 05 01:24:54 PM PST 24 |
| Finished | Mar 05 01:25:20 PM PST 24 |
| Peak memory | 268260 kb |
| Host | smart-d9cebbb1-b815-4ef0-b298-f397357ed272 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394121401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.3394121401 |
| Directory | /workspace/17.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2654718673 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 19475864946 ps |
| CPU time | 300.62 seconds |
| Started | Mar 05 01:25:00 PM PST 24 |
| Finished | Mar 05 01:30:02 PM PST 24 |
| Peak memory | 202832 kb |
| Host | smart-97ed8ca6-9f8c-47ca-a4a9-c6c6ad7458dd |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654718673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.2654718673 |
| Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.963983518 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 692116440 ps |
| CPU time | 3.02 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:25:14 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-4653ff14-e386-4477-afdb-1fe666b2cdd0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963983518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.963983518 |
| Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_regwen.1555725078 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1522910529 ps |
| CPU time | 541.16 seconds |
| Started | Mar 05 01:25:00 PM PST 24 |
| Finished | Mar 05 01:34:03 PM PST 24 |
| Peak memory | 365288 kb |
| Host | smart-a43e7b63-53d3-4d07-90b8-93af0673d2ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555725078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1555725078 |
| Directory | /workspace/17.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_smoke.3592763116 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1443171800 ps |
| CPU time | 18.04 seconds |
| Started | Mar 05 01:24:58 PM PST 24 |
| Finished | Mar 05 01:25:16 PM PST 24 |
| Peak memory | 262724 kb |
| Host | smart-5de1b65d-688c-4cb8-b1a9-faf02e032219 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592763116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3592763116 |
| Directory | /workspace/17.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.902759532 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 402153434935 ps |
| CPU time | 3628.96 seconds |
| Started | Mar 05 01:25:10 PM PST 24 |
| Finished | Mar 05 02:25:40 PM PST 24 |
| Peak memory | 387876 kb |
| Host | smart-b0b44f50-915c-4588-ba45-f117c02ddb1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902759532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_stress_all.902759532 |
| Directory | /workspace/17.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1097535053 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13740726806 ps |
| CPU time | 92.68 seconds |
| Started | Mar 05 01:25:06 PM PST 24 |
| Finished | Mar 05 01:26:39 PM PST 24 |
| Peak memory | 216580 kb |
| Host | smart-389ead3d-9c22-4f4e-8f0f-ac5cfe0dfe01 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1097535053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1097535053 |
| Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.415436203 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 2832312319 ps |
| CPU time | 147.8 seconds |
| Started | Mar 05 01:24:57 PM PST 24 |
| Finished | Mar 05 01:27:25 PM PST 24 |
| Peak memory | 202788 kb |
| Host | smart-5b568a9f-def8-433e-859a-d111b3e896e6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415436203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17 .sram_ctrl_stress_pipeline.415436203 |
| Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.823072835 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 757749978 ps |
| CPU time | 25.4 seconds |
| Started | Mar 05 01:25:03 PM PST 24 |
| Finished | Mar 05 01:25:29 PM PST 24 |
| Peak memory | 271240 kb |
| Host | smart-1a550749-7909-4416-974f-98d919670328 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823072835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_throughput_w_partial_write.823072835 |
| Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.3184264862 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 10720176 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:25:09 PM PST 24 |
| Finished | Mar 05 01:25:10 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-0f120f4a-c380-42f1-8bca-13fe4da29284 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184264862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3184264862 |
| Directory | /workspace/18.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_bijection.3820566458 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 92151529989 ps |
| CPU time | 1919.03 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:57:12 PM PST 24 |
| Peak memory | 202840 kb |
| Host | smart-f9fc1183-1f0b-497d-ad08-5363513307f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820566458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .3820566458 |
| Directory | /workspace/18.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_executable.3136189426 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 16691177111 ps |
| CPU time | 586.66 seconds |
| Started | Mar 05 01:25:07 PM PST 24 |
| Finished | Mar 05 01:34:54 PM PST 24 |
| Peak memory | 378564 kb |
| Host | smart-55e79b7c-8a1a-4868-adb3-8380c2618043 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136189426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.3136189426 |
| Directory | /workspace/18.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.3700684444 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 5264464627 ps |
| CPU time | 57.91 seconds |
| Started | Mar 05 01:25:16 PM PST 24 |
| Finished | Mar 05 01:26:15 PM PST 24 |
| Peak memory | 215032 kb |
| Host | smart-84ca6106-eb59-48dc-ba89-cff199fc7939 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700684444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.3700684444 |
| Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.3675936586 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1692393063 ps |
| CPU time | 26.33 seconds |
| Started | Mar 05 01:25:10 PM PST 24 |
| Finished | Mar 05 01:25:37 PM PST 24 |
| Peak memory | 278348 kb |
| Host | smart-7d29c195-9c9d-4266-b7b4-4ed0e20abae0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675936586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.3675936586 |
| Directory | /workspace/18.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2992720400 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3338267562 ps |
| CPU time | 118.5 seconds |
| Started | Mar 05 01:25:05 PM PST 24 |
| Finished | Mar 05 01:27:04 PM PST 24 |
| Peak memory | 210992 kb |
| Host | smart-34794ee3-d27a-4599-af2a-21ddd8ce93b5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992720400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.2992720400 |
| Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.3368203516 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 41271685205 ps |
| CPU time | 319.67 seconds |
| Started | Mar 05 01:25:10 PM PST 24 |
| Finished | Mar 05 01:30:30 PM PST 24 |
| Peak memory | 203200 kb |
| Host | smart-94ebcbd8-6129-4338-b0ba-0a810cfd3363 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368203516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.3368203516 |
| Directory | /workspace/18.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.1010667781 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 5592972292 ps |
| CPU time | 35.64 seconds |
| Started | Mar 05 01:25:15 PM PST 24 |
| Finished | Mar 05 01:25:51 PM PST 24 |
| Peak memory | 210008 kb |
| Host | smart-7575e0e1-c220-4f17-83e9-737f9be6cf64 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010667781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.1010667781 |
| Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.1827305163 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 5556812390 ps |
| CPU time | 22.94 seconds |
| Started | Mar 05 01:25:07 PM PST 24 |
| Finished | Mar 05 01:25:31 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-d7ee1057-0d19-4cb0-a14f-a56782afb887 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827305163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.1827305163 |
| Directory | /workspace/18.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.2850562867 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1534473696 ps |
| CPU time | 3.26 seconds |
| Started | Mar 05 01:25:06 PM PST 24 |
| Finished | Mar 05 01:25:10 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-1da3beb6-bb88-48bc-872e-ca9cd7fa36ff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850562867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2850562867 |
| Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_regwen.1709080616 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 11112578445 ps |
| CPU time | 616.69 seconds |
| Started | Mar 05 01:25:03 PM PST 24 |
| Finished | Mar 05 01:35:20 PM PST 24 |
| Peak memory | 371592 kb |
| Host | smart-793cb4c4-a1c1-48dd-a502-9f12ec2115a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709080616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1709080616 |
| Directory | /workspace/18.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_smoke.1720837138 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 7519744568 ps |
| CPU time | 13.25 seconds |
| Started | Mar 05 01:25:04 PM PST 24 |
| Finished | Mar 05 01:25:17 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-5cb2b71d-c7bb-4a88-a05e-0cf3b7baabdf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720837138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1720837138 |
| Directory | /workspace/18.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1326141849 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 4300268037 ps |
| CPU time | 135.09 seconds |
| Started | Mar 05 01:25:06 PM PST 24 |
| Finished | Mar 05 01:27:21 PM PST 24 |
| Peak memory | 378692 kb |
| Host | smart-07af47e3-d3e5-41a0-8b76-49fe37408c73 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1326141849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1326141849 |
| Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2525330564 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 13544214013 ps |
| CPU time | 174.49 seconds |
| Started | Mar 05 01:25:09 PM PST 24 |
| Finished | Mar 05 01:28:03 PM PST 24 |
| Peak memory | 202808 kb |
| Host | smart-2d60db33-8d0e-454a-899b-7ff7607c486e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525330564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.2525330564 |
| Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.185632147 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3229224868 ps |
| CPU time | 97.54 seconds |
| Started | Mar 05 01:25:09 PM PST 24 |
| Finished | Mar 05 01:26:47 PM PST 24 |
| Peak memory | 358996 kb |
| Host | smart-28181f55-3596-44c6-8e92-00368f9093f2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185632147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.185632147 |
| Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.2212096872 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 14249397 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:25:14 PM PST 24 |
| Peak memory | 202180 kb |
| Host | smart-3783699e-0364-485f-b150-d2628d51390b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212096872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.2212096872 |
| Directory | /workspace/19.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_bijection.58985411 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 258363410637 ps |
| CPU time | 1486.68 seconds |
| Started | Mar 05 01:25:17 PM PST 24 |
| Finished | Mar 05 01:50:04 PM PST 24 |
| Peak memory | 202856 kb |
| Host | smart-3a93219e-d8e2-4317-9e97-bbd1ebea39da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58985411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.58985411 |
| Directory | /workspace/19.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_executable.216045081 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 29995943049 ps |
| CPU time | 298.17 seconds |
| Started | Mar 05 01:25:12 PM PST 24 |
| Finished | Mar 05 01:30:11 PM PST 24 |
| Peak memory | 363292 kb |
| Host | smart-96d60c64-7e9e-442d-b330-b7e26e910763 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216045081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executabl e.216045081 |
| Directory | /workspace/19.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.820272475 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 49093686601 ps |
| CPU time | 662.77 seconds |
| Started | Mar 05 01:25:08 PM PST 24 |
| Finished | Mar 05 01:36:11 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-53bf0cd2-799a-4481-b916-4ac3941a8d37 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820272475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_esc alation.820272475 |
| Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.4088918538 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3624522314 ps |
| CPU time | 14.46 seconds |
| Started | Mar 05 01:25:07 PM PST 24 |
| Finished | Mar 05 01:25:22 PM PST 24 |
| Peak memory | 240316 kb |
| Host | smart-76a3a296-6b54-4110-a21d-1e3fdf6b3cc2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088918538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.4088918538 |
| Directory | /workspace/19.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.4170562367 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 19031745744 ps |
| CPU time | 151.52 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:27:45 PM PST 24 |
| Peak memory | 210952 kb |
| Host | smart-5a01fab7-e9cc-4e5c-94a9-5ce44ecffb4c |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170562367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.4170562367 |
| Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.2433004188 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 4535683122 ps |
| CPU time | 253.8 seconds |
| Started | Mar 05 01:25:09 PM PST 24 |
| Finished | Mar 05 01:29:23 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-89007af3-b94c-437f-8ce6-7b581b7000c0 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433004188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.2433004188 |
| Directory | /workspace/19.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.1630821821 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 72002976682 ps |
| CPU time | 1219.78 seconds |
| Started | Mar 05 01:24:59 PM PST 24 |
| Finished | Mar 05 01:45:19 PM PST 24 |
| Peak memory | 377672 kb |
| Host | smart-b04c8b93-397d-46ea-a44b-d635449f6ec9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630821821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.1630821821 |
| Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.1070301635 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1318697297 ps |
| CPU time | 6.37 seconds |
| Started | Mar 05 01:25:06 PM PST 24 |
| Finished | Mar 05 01:25:13 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-0144db28-7cd1-4124-aa6d-b73829268a09 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070301635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.1070301635 |
| Directory | /workspace/19.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3378357644 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 60792612545 ps |
| CPU time | 407.62 seconds |
| Started | Mar 05 01:25:02 PM PST 24 |
| Finished | Mar 05 01:31:50 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-e43baf8b-2890-4340-897b-ee266f095924 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378357644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.3378357644 |
| Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.3185385309 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1202652827 ps |
| CPU time | 3.29 seconds |
| Started | Mar 05 01:25:06 PM PST 24 |
| Finished | Mar 05 01:25:10 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-e5a04087-58d5-422d-a2d5-f99a9837bc0f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185385309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3185385309 |
| Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_regwen.3413523263 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 11386067934 ps |
| CPU time | 575.35 seconds |
| Started | Mar 05 01:25:09 PM PST 24 |
| Finished | Mar 05 01:34:45 PM PST 24 |
| Peak memory | 336828 kb |
| Host | smart-5f09513f-f547-44da-acb6-ea9ed0faff2a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413523263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3413523263 |
| Directory | /workspace/19.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_smoke.1722312484 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3242008948 ps |
| CPU time | 21.13 seconds |
| Started | Mar 05 01:25:05 PM PST 24 |
| Finished | Mar 05 01:25:26 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-14527f27-4d8c-4c44-a1e6-b617dc6d12ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722312484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.1722312484 |
| Directory | /workspace/19.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2710238154 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3047193983 ps |
| CPU time | 14.35 seconds |
| Started | Mar 05 01:25:03 PM PST 24 |
| Finished | Mar 05 01:25:18 PM PST 24 |
| Peak memory | 211124 kb |
| Host | smart-375870b5-a8df-48df-a575-fee48a7d2986 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2710238154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2710238154 |
| Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1920652104 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 5890856866 ps |
| CPU time | 169.77 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:28:03 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-44a19128-a1bc-4e94-9823-0cd9fa04b674 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920652104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.1920652104 |
| Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.353293065 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 771157624 ps |
| CPU time | 120.26 seconds |
| Started | Mar 05 01:24:59 PM PST 24 |
| Finished | Mar 05 01:27:00 PM PST 24 |
| Peak memory | 347176 kb |
| Host | smart-ce31fbe6-e5dd-4583-8874-32bb6d014af7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353293065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.353293065 |
| Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.4246914408 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 14066616 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:24:25 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-786d6c9d-c63b-444c-8035-038f5722addc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246914408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.4246914408 |
| Directory | /workspace/2.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_bijection.1942245764 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11328636169 ps |
| CPU time | 653.39 seconds |
| Started | Mar 05 01:24:18 PM PST 24 |
| Finished | Mar 05 01:35:12 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-fa21165c-0269-47c6-b25f-4c5b3ba7ac22 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942245764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 1942245764 |
| Directory | /workspace/2.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_executable.2070079575 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 117667789984 ps |
| CPU time | 1479.12 seconds |
| Started | Mar 05 01:24:43 PM PST 24 |
| Finished | Mar 05 01:49:23 PM PST 24 |
| Peak memory | 372552 kb |
| Host | smart-430d1f8e-418c-4a33-8516-69bba980e998 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070079575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.2070079575 |
| Directory | /workspace/2.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.2748128269 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 43121040803 ps |
| CPU time | 458.42 seconds |
| Started | Mar 05 01:24:23 PM PST 24 |
| Finished | Mar 05 01:32:02 PM PST 24 |
| Peak memory | 210972 kb |
| Host | smart-989d3bc8-c02c-4840-ba77-8551b340d2b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748128269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.2748128269 |
| Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.748962874 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1511049384 ps |
| CPU time | 43.52 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 01:25:09 PM PST 24 |
| Peak memory | 295956 kb |
| Host | smart-7b6fa189-c61a-43bb-b54b-90e9fa994698 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748962874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.sram_ctrl_max_throughput.748962874 |
| Directory | /workspace/2.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1472822440 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 72266578121 ps |
| CPU time | 154.23 seconds |
| Started | Mar 05 01:24:22 PM PST 24 |
| Finished | Mar 05 01:26:56 PM PST 24 |
| Peak memory | 210972 kb |
| Host | smart-3553b135-bd43-4a76-83c4-ed228cfdb3a2 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472822440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.1472822440 |
| Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.3478950929 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4072661938 ps |
| CPU time | 245.22 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:28:30 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-e8263f80-cc24-42e8-b4af-53e8384f8769 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478950929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.3478950929 |
| Directory | /workspace/2.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.3910149978 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 103480885423 ps |
| CPU time | 1059.24 seconds |
| Started | Mar 05 01:24:11 PM PST 24 |
| Finished | Mar 05 01:41:51 PM PST 24 |
| Peak memory | 378632 kb |
| Host | smart-7866f8cc-9707-4bd1-9cd4-a5176986ec21 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910149978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.3910149978 |
| Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.3494602836 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1508609977 ps |
| CPU time | 5.73 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:24:30 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-a2f754b8-ae4f-42be-abc6-a8f2330ddaff |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494602836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.3494602836 |
| Directory | /workspace/2.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1018921353 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 21633237735 ps |
| CPU time | 444.55 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:31:52 PM PST 24 |
| Peak memory | 202784 kb |
| Host | smart-88ecfd99-0696-4afa-aec6-0dcab9b23439 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018921353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.1018921353 |
| Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.950807958 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 432460069 ps |
| CPU time | 3.32 seconds |
| Started | Mar 05 01:24:21 PM PST 24 |
| Finished | Mar 05 01:24:24 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-a58dd772-4e9f-4f40-a77a-2b9dbed8a5a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950807958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.950807958 |
| Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_regwen.3769416114 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 55330360757 ps |
| CPU time | 838.85 seconds |
| Started | Mar 05 01:24:18 PM PST 24 |
| Finished | Mar 05 01:38:17 PM PST 24 |
| Peak memory | 374536 kb |
| Host | smart-ff139a50-2fa0-4333-84c6-bb7c5213ad77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769416114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3769416114 |
| Directory | /workspace/2.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.1886073822 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 891919983 ps |
| CPU time | 1.83 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 01:24:26 PM PST 24 |
| Peak memory | 221664 kb |
| Host | smart-6cc0ad41-8506-4ce2-ac74-097ce2ad819b |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886073822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.1886073822 |
| Directory | /workspace/2.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_smoke.3835030508 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 4321889226 ps |
| CPU time | 19.16 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 01:24:50 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-f23d3c90-ddcb-4633-a58e-cf564acc814b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835030508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3835030508 |
| Directory | /workspace/2.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.599098393 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 43340058076 ps |
| CPU time | 2930.31 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 02:13:15 PM PST 24 |
| Peak memory | 378664 kb |
| Host | smart-a1fe15ca-2b4e-44c6-b595-397aca68bce4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599098393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_stress_all.599098393 |
| Directory | /workspace/2.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3459928469 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 5765110432 ps |
| CPU time | 62.68 seconds |
| Started | Mar 05 01:24:31 PM PST 24 |
| Finished | Mar 05 01:25:34 PM PST 24 |
| Peak memory | 274520 kb |
| Host | smart-709f7857-2962-4155-8f44-cb606a2636e7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3459928469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3459928469 |
| Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2676348338 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 12611238122 ps |
| CPU time | 231.81 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 01:28:17 PM PST 24 |
| Peak memory | 202832 kb |
| Host | smart-52fd62e1-1652-43c8-8185-7493229e53a4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676348338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.2676348338 |
| Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1195582287 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3201820225 ps |
| CPU time | 85.52 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 01:25:52 PM PST 24 |
| Peak memory | 336220 kb |
| Host | smart-b951b216-c479-40df-843a-af6bd5bb0c61 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195582287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1195582287 |
| Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.2761415764 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 26163615 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:25:15 PM PST 24 |
| Finished | Mar 05 01:25:16 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-2a25cb18-acff-4730-b1aa-f4f0ca559104 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761415764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.2761415764 |
| Directory | /workspace/20.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_bijection.2975434735 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 838545540598 ps |
| CPU time | 1987.07 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:58:18 PM PST 24 |
| Peak memory | 202860 kb |
| Host | smart-9908a6b3-161c-4a95-a445-6408411d2836 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975434735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .2975434735 |
| Directory | /workspace/20.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_executable.2573661316 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 7470777132 ps |
| CPU time | 594.27 seconds |
| Started | Mar 05 01:25:10 PM PST 24 |
| Finished | Mar 05 01:35:05 PM PST 24 |
| Peak memory | 374492 kb |
| Host | smart-6d9a4a4b-70ed-461f-93c6-4b2722c72605 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573661316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.2573661316 |
| Directory | /workspace/20.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.2357085300 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 718536705 ps |
| CPU time | 39.9 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:25:54 PM PST 24 |
| Peak memory | 284476 kb |
| Host | smart-fc1cd7d2-2c06-46c5-ae69-c90064225384 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357085300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.2357085300 |
| Directory | /workspace/20.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2202376174 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 2673961001 ps |
| CPU time | 79.15 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:26:32 PM PST 24 |
| Peak memory | 210956 kb |
| Host | smart-6e4e596f-c909-4ff3-86b7-224afa905c77 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202376174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.2202376174 |
| Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.2521084253 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6900700874 ps |
| CPU time | 140.35 seconds |
| Started | Mar 05 01:25:12 PM PST 24 |
| Finished | Mar 05 01:27:32 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-f31cf43d-dbe4-4313-a8b8-c6a23c5ae7d3 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521084253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.2521084253 |
| Directory | /workspace/20.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.188573174 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 7013434484 ps |
| CPU time | 474.04 seconds |
| Started | Mar 05 01:25:04 PM PST 24 |
| Finished | Mar 05 01:32:59 PM PST 24 |
| Peak memory | 345104 kb |
| Host | smart-45439f93-2db6-4ff2-83e6-3bb09207c3c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188573174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip le_keys.188573174 |
| Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.4254319997 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 3991756989 ps |
| CPU time | 116.9 seconds |
| Started | Mar 05 01:25:10 PM PST 24 |
| Finished | Mar 05 01:27:07 PM PST 24 |
| Peak memory | 338648 kb |
| Host | smart-96542531-d1a6-48df-8b22-0ef3d1c013a2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254319997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.4254319997 |
| Directory | /workspace/20.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.1090723388 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 369334982 ps |
| CPU time | 2.91 seconds |
| Started | Mar 05 01:25:01 PM PST 24 |
| Finished | Mar 05 01:25:05 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-444f53e1-8465-4694-919f-d39e667b3737 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090723388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1090723388 |
| Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_regwen.169026701 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 8397227547 ps |
| CPU time | 637.21 seconds |
| Started | Mar 05 01:24:59 PM PST 24 |
| Finished | Mar 05 01:35:36 PM PST 24 |
| Peak memory | 367196 kb |
| Host | smart-0e59d5ed-2642-4024-9cdc-04f7cf290c13 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169026701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.169026701 |
| Directory | /workspace/20.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_smoke.2944790439 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 358511408 ps |
| CPU time | 3.61 seconds |
| Started | Mar 05 01:25:04 PM PST 24 |
| Finished | Mar 05 01:25:08 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-a3a5a95a-7b01-4a9f-bf3d-826570505acd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944790439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2944790439 |
| Directory | /workspace/20.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.3967709326 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 185661008520 ps |
| CPU time | 2999.79 seconds |
| Started | Mar 05 01:25:12 PM PST 24 |
| Finished | Mar 05 02:15:12 PM PST 24 |
| Peak memory | 370056 kb |
| Host | smart-49295ab7-27ad-45e4-bb2b-493ab9cc1923 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967709326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.3967709326 |
| Directory | /workspace/20.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1734680883 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 4367017094 ps |
| CPU time | 237.42 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:29:11 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-8215f7a8-3eb8-4b95-b228-6cc681b1cb87 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734680883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.1734680883 |
| Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.4136426546 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 768406735 ps |
| CPU time | 102.94 seconds |
| Started | Mar 05 01:25:12 PM PST 24 |
| Finished | Mar 05 01:26:56 PM PST 24 |
| Peak memory | 341672 kb |
| Host | smart-0a263b83-1804-4c7b-ab53-663b8eba26e7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136426546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.4136426546 |
| Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.3518939623 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14921664 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:25:12 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-a08fca96-4fe8-4d2a-8092-7c366f2b4723 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518939623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.3518939623 |
| Directory | /workspace/21.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_bijection.598983751 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 331607553698 ps |
| CPU time | 1979.46 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:58:14 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-cd485486-0ab2-49ae-b0a0-830b126bd30a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598983751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection. 598983751 |
| Directory | /workspace/21.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_executable.571414244 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2383887386 ps |
| CPU time | 302.81 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:30:14 PM PST 24 |
| Peak memory | 360688 kb |
| Host | smart-3950fe37-f819-4b67-94f9-6bfb90e3faed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571414244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executabl e.571414244 |
| Directory | /workspace/21.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.59268216 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 40477466323 ps |
| CPU time | 494.12 seconds |
| Started | Mar 05 01:25:17 PM PST 24 |
| Finished | Mar 05 01:33:32 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-fa96ce47-76ef-4b9c-96eb-9e6c34001407 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59268216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esca lation.59268216 |
| Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.47817300 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1697281609 ps |
| CPU time | 21.25 seconds |
| Started | Mar 05 01:25:09 PM PST 24 |
| Finished | Mar 05 01:25:31 PM PST 24 |
| Peak memory | 262120 kb |
| Host | smart-a2d6dc20-14c7-451e-b369-18e779adf7c3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47817300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 21.sram_ctrl_max_throughput.47817300 |
| Directory | /workspace/21.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.898082548 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 18194778584 ps |
| CPU time | 150.6 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:27:44 PM PST 24 |
| Peak memory | 210988 kb |
| Host | smart-fa38749b-4019-4dea-a8eb-5270f822a143 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898082548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_mem_partial_access.898082548 |
| Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.3823230101 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 29322415294 ps |
| CPU time | 290.97 seconds |
| Started | Mar 05 01:25:21 PM PST 24 |
| Finished | Mar 05 01:30:12 PM PST 24 |
| Peak memory | 202860 kb |
| Host | smart-1a56375a-ef4a-48d6-8803-da2db7616f22 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823230101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.3823230101 |
| Directory | /workspace/21.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.3884578056 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 34447478552 ps |
| CPU time | 1148.85 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:44:20 PM PST 24 |
| Peak memory | 378624 kb |
| Host | smart-dc0b83bc-c92c-4014-9a22-37870b3d6bbe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884578056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.3884578056 |
| Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.2387465719 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1703382085 ps |
| CPU time | 24.71 seconds |
| Started | Mar 05 01:25:12 PM PST 24 |
| Finished | Mar 05 01:25:37 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-9401d0f4-41c2-49d7-91cf-c79aa84b2eef |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387465719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.2387465719 |
| Directory | /workspace/21.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1103643616 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 358019715234 ps |
| CPU time | 504.43 seconds |
| Started | Mar 05 01:25:15 PM PST 24 |
| Finished | Mar 05 01:33:41 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-0265f6ec-8669-4143-8bdd-6df88b7325f5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103643616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.1103643616 |
| Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.1962605698 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 686431319 ps |
| CPU time | 2.96 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:25:26 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-72bd3488-962b-4c71-adac-5ff45e3c06d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962605698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1962605698 |
| Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_regwen.1740774737 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 33764040985 ps |
| CPU time | 644.58 seconds |
| Started | Mar 05 01:25:22 PM PST 24 |
| Finished | Mar 05 01:36:07 PM PST 24 |
| Peak memory | 377720 kb |
| Host | smart-f313e51f-3cbf-4d75-ad14-5b1aa94a5d6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740774737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1740774737 |
| Directory | /workspace/21.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_smoke.502211043 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1080200784 ps |
| CPU time | 52.53 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:26:07 PM PST 24 |
| Peak memory | 293824 kb |
| Host | smart-342c8d81-9c67-436d-aa7c-035bcc344eac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502211043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.502211043 |
| Directory | /workspace/21.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.4206809340 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1301078099763 ps |
| CPU time | 4855.89 seconds |
| Started | Mar 05 01:25:09 PM PST 24 |
| Finished | Mar 05 02:46:06 PM PST 24 |
| Peak memory | 375372 kb |
| Host | smart-92732af9-9f35-4d8d-a992-2cbc410ca468 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206809340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.4206809340 |
| Directory | /workspace/21.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.801718233 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 5166504172 ps |
| CPU time | 59.15 seconds |
| Started | Mar 05 01:25:10 PM PST 24 |
| Finished | Mar 05 01:26:09 PM PST 24 |
| Peak memory | 211096 kb |
| Host | smart-86068eb5-47f0-49fc-b5a4-a1f07a894924 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=801718233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.801718233 |
| Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3055221369 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 30088809911 ps |
| CPU time | 237.01 seconds |
| Started | Mar 05 01:25:18 PM PST 24 |
| Finished | Mar 05 01:29:15 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-bcca8b87-92ac-4b35-9f15-113d486bb85b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055221369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.3055221369 |
| Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1110496601 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 812187005 ps |
| CPU time | 6 seconds |
| Started | Mar 05 01:25:16 PM PST 24 |
| Finished | Mar 05 01:25:23 PM PST 24 |
| Peak memory | 210784 kb |
| Host | smart-e3a7be7f-ba98-4256-adf4-f835b120aa0d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110496601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.1110496601 |
| Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.2569348303 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 24978712 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:25:15 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-29444ed6-8355-433a-a211-8d31abc24755 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569348303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.2569348303 |
| Directory | /workspace/22.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_bijection.2304876169 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 27663212024 ps |
| CPU time | 1836.34 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:55:49 PM PST 24 |
| Peak memory | 202864 kb |
| Host | smart-3a7ee345-9db4-422d-96c7-52b53cee8866 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304876169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .2304876169 |
| Directory | /workspace/22.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_executable.2315035601 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 172654620778 ps |
| CPU time | 1079.37 seconds |
| Started | Mar 05 01:25:21 PM PST 24 |
| Finished | Mar 05 01:43:21 PM PST 24 |
| Peak memory | 367392 kb |
| Host | smart-8e9b1d4f-49e7-4f68-aa8a-607c8161c5a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315035601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.2315035601 |
| Directory | /workspace/22.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.4175833298 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 23590529092 ps |
| CPU time | 317.11 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:30:29 PM PST 24 |
| Peak memory | 210948 kb |
| Host | smart-dd202771-8f6c-46f3-a765-bafbba32f3db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175833298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.4175833298 |
| Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.3349059921 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 803032509 ps |
| CPU time | 119.52 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:27:13 PM PST 24 |
| Peak memory | 369356 kb |
| Host | smart-fd1911c1-6dfe-45c9-aa7b-73c237b4f4ca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349059921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.3349059921 |
| Directory | /workspace/22.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3944568640 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 72189731766 ps |
| CPU time | 159.71 seconds |
| Started | Mar 05 01:25:12 PM PST 24 |
| Finished | Mar 05 01:27:52 PM PST 24 |
| Peak memory | 210992 kb |
| Host | smart-05f38a78-0b36-4e6e-8be9-64ac489e3915 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944568640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.3944568640 |
| Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.3636702333 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 21522144884 ps |
| CPU time | 312.16 seconds |
| Started | Mar 05 01:25:17 PM PST 24 |
| Finished | Mar 05 01:30:29 PM PST 24 |
| Peak memory | 202996 kb |
| Host | smart-024c2e62-e4ec-4925-98bb-e2e1c8dadc59 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636702333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.3636702333 |
| Directory | /workspace/22.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.2434292697 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 13655278743 ps |
| CPU time | 557.79 seconds |
| Started | Mar 05 01:25:19 PM PST 24 |
| Finished | Mar 05 01:34:38 PM PST 24 |
| Peak memory | 357508 kb |
| Host | smart-20938188-2433-48e7-bbba-34478ce875be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434292697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.2434292697 |
| Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.3700819113 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 464376830 ps |
| CPU time | 55.12 seconds |
| Started | Mar 05 01:25:10 PM PST 24 |
| Finished | Mar 05 01:26:05 PM PST 24 |
| Peak memory | 294844 kb |
| Host | smart-d6d3ba81-e0b5-4d35-ba42-5896da81bf6b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700819113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.3700819113 |
| Directory | /workspace/22.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1274901958 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 8515909824 ps |
| CPU time | 251.79 seconds |
| Started | Mar 05 01:25:16 PM PST 24 |
| Finished | Mar 05 01:29:29 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-669a2731-7d72-4dd2-9b15-01fc3e39cd6b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274901958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.1274901958 |
| Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.3541821718 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1397715337 ps |
| CPU time | 3.7 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:25:17 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-749b6fab-6a7e-4faa-82be-23b685c652b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541821718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3541821718 |
| Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_regwen.2596182237 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 17374316194 ps |
| CPU time | 333.37 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:30:47 PM PST 24 |
| Peak memory | 372560 kb |
| Host | smart-63c3b631-0f04-43d3-b009-d1aea49e2a64 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596182237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2596182237 |
| Directory | /workspace/22.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_smoke.364258383 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 554024711 ps |
| CPU time | 7.34 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:25:21 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-043d5ce8-7ce7-4b62-ac38-7f44154fe224 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364258383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.364258383 |
| Directory | /workspace/22.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.1731379170 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 280414554885 ps |
| CPU time | 4729.9 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 02:44:04 PM PST 24 |
| Peak memory | 387844 kb |
| Host | smart-b30d0d95-2019-4ae2-8d2d-92a2fc9c9c80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731379170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.1731379170 |
| Directory | /workspace/22.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3279588338 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1512388118 ps |
| CPU time | 183.58 seconds |
| Started | Mar 05 01:25:15 PM PST 24 |
| Finished | Mar 05 01:28:18 PM PST 24 |
| Peak memory | 377624 kb |
| Host | smart-cb755813-2c6a-4240-89c7-a6e809b3eca1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3279588338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3279588338 |
| Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.3528854446 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3110089464 ps |
| CPU time | 204.52 seconds |
| Started | Mar 05 01:25:19 PM PST 24 |
| Finished | Mar 05 01:28:43 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-b748beb2-48b3-44e7-97ea-7902e256c5d4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528854446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.3528854446 |
| Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3526301795 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1298094598 ps |
| CPU time | 21.59 seconds |
| Started | Mar 05 01:25:20 PM PST 24 |
| Finished | Mar 05 01:25:42 PM PST 24 |
| Peak memory | 268148 kb |
| Host | smart-be403ff4-25aa-463f-ba35-d1c5f12383ee |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526301795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3526301795 |
| Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.2815714563 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 21890741 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:25:14 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-4ebbd2de-f352-4f27-a55a-9d522d1d13bd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815714563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.2815714563 |
| Directory | /workspace/23.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_bijection.2565541519 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 29248149054 ps |
| CPU time | 2001.72 seconds |
| Started | Mar 05 01:25:15 PM PST 24 |
| Finished | Mar 05 01:58:37 PM PST 24 |
| Peak memory | 202916 kb |
| Host | smart-61df99ab-dee9-49cd-99fa-af16a428a9d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565541519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .2565541519 |
| Directory | /workspace/23.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.2529624295 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1411778529 ps |
| CPU time | 19.42 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:25:31 PM PST 24 |
| Peak memory | 268140 kb |
| Host | smart-1edfd11e-bde6-4ea8-b0e1-8f6eda20422d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529624295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.2529624295 |
| Directory | /workspace/23.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.510189487 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 19009853510 ps |
| CPU time | 150.41 seconds |
| Started | Mar 05 01:25:12 PM PST 24 |
| Finished | Mar 05 01:27:42 PM PST 24 |
| Peak memory | 211024 kb |
| Host | smart-d95f788f-cee2-4b14-bb1f-3912f5cf4580 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510189487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23 .sram_ctrl_mem_partial_access.510189487 |
| Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.2947924069 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 36945068522 ps |
| CPU time | 151.21 seconds |
| Started | Mar 05 01:25:19 PM PST 24 |
| Finished | Mar 05 01:27:51 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-0359a42d-54b5-46fe-874c-354ec0ea4f96 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947924069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.2947924069 |
| Directory | /workspace/23.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.2286240058 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 5006159241 ps |
| CPU time | 802.93 seconds |
| Started | Mar 05 01:25:15 PM PST 24 |
| Finished | Mar 05 01:38:39 PM PST 24 |
| Peak memory | 375632 kb |
| Host | smart-618c6bd5-7373-40e8-bda6-cbaf2bb9b2aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286240058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.2286240058 |
| Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.2574930362 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3738701217 ps |
| CPU time | 26.25 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:25:40 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-485fd08e-fb92-43cf-a080-cdc117413168 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574930362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.2574930362 |
| Directory | /workspace/23.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1855882677 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4793003590 ps |
| CPU time | 244.03 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:29:18 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-f964a594-93ca-44f8-970d-6db3cc08fb21 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855882677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.1855882677 |
| Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.2097579827 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1405085326 ps |
| CPU time | 3.77 seconds |
| Started | Mar 05 01:25:17 PM PST 24 |
| Finished | Mar 05 01:25:21 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-ecb1c196-c83a-49a0-8d3f-ea85e7e6205e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097579827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2097579827 |
| Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_smoke.2098085562 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 902846403 ps |
| CPU time | 16.29 seconds |
| Started | Mar 05 01:25:19 PM PST 24 |
| Finished | Mar 05 01:25:36 PM PST 24 |
| Peak memory | 245652 kb |
| Host | smart-82a00372-abee-416a-bcb1-87181983ad77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098085562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2098085562 |
| Directory | /workspace/23.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.1267965103 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 239776111994 ps |
| CPU time | 4057.03 seconds |
| Started | Mar 05 01:25:12 PM PST 24 |
| Finished | Mar 05 02:32:49 PM PST 24 |
| Peak memory | 379728 kb |
| Host | smart-ba3fc9e0-f3fb-4912-afde-c79ab73cd392 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267965103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.1267965103 |
| Directory | /workspace/23.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3529582706 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 6657258653 ps |
| CPU time | 45.43 seconds |
| Started | Mar 05 01:25:15 PM PST 24 |
| Finished | Mar 05 01:26:02 PM PST 24 |
| Peak memory | 211092 kb |
| Host | smart-6497f1f7-62fb-459a-991f-cee042cd8bce |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3529582706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3529582706 |
| Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1043800147 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 31832447541 ps |
| CPU time | 136.36 seconds |
| Started | Mar 05 01:25:15 PM PST 24 |
| Finished | Mar 05 01:27:32 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-3dff7259-7793-4526-b1ce-44feb5078ba6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043800147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.1043800147 |
| Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.341746294 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2749256035 ps |
| CPU time | 10.54 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:25:24 PM PST 24 |
| Peak memory | 235276 kb |
| Host | smart-af5109ab-ec90-460b-9d8d-930d7c8a6a36 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341746294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.341746294 |
| Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.2779920120 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 27776077 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 01:25:17 PM PST 24 |
| Finished | Mar 05 01:25:18 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-e2a54eda-52d4-4468-bd10-179d7967324b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779920120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2779920120 |
| Directory | /workspace/24.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_executable.1168055658 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 254009749939 ps |
| CPU time | 1364.1 seconds |
| Started | Mar 05 01:25:17 PM PST 24 |
| Finished | Mar 05 01:48:01 PM PST 24 |
| Peak memory | 379648 kb |
| Host | smart-ed4de872-59d0-41b0-a898-e501212f5f4e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168055658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.1168055658 |
| Directory | /workspace/24.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.1587860733 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 50779817622 ps |
| CPU time | 601.35 seconds |
| Started | Mar 05 01:25:19 PM PST 24 |
| Finished | Mar 05 01:35:21 PM PST 24 |
| Peak memory | 210972 kb |
| Host | smart-ce04ea4f-d403-40ef-af4b-c60ae929eafb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587860733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.1587860733 |
| Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.1062721454 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4426597270 ps |
| CPU time | 31.39 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:25:45 PM PST 24 |
| Peak memory | 276472 kb |
| Host | smart-40f1b3a3-90c7-40d9-9e92-60f013de32c8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062721454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.1062721454 |
| Directory | /workspace/24.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1438113585 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 1548255153 ps |
| CPU time | 122.09 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:27:14 PM PST 24 |
| Peak memory | 210884 kb |
| Host | smart-781a2023-7893-4661-833e-b6116dc04ac2 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438113585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1438113585 |
| Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.1997038088 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 40494853245 ps |
| CPU time | 275.71 seconds |
| Started | Mar 05 01:25:12 PM PST 24 |
| Finished | Mar 05 01:29:49 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-597abb5e-a4d1-475e-a4a1-d07f75cee9a1 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997038088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.1997038088 |
| Directory | /workspace/24.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.3411712915 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 24729508504 ps |
| CPU time | 1030.98 seconds |
| Started | Mar 05 01:25:19 PM PST 24 |
| Finished | Mar 05 01:42:31 PM PST 24 |
| Peak memory | 375632 kb |
| Host | smart-b77777cb-0cb5-4764-a13f-83dc1b78d808 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411712915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.3411712915 |
| Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.2704788141 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1347235642 ps |
| CPU time | 21.29 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:25:45 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-3033dbeb-8d9d-4150-9e63-1c0c1739e75d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704788141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.2704788141 |
| Directory | /workspace/24.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2809025422 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 62946860728 ps |
| CPU time | 371.55 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:31:25 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-3c418de1-df06-4089-946e-7f83c58492e4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809025422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.2809025422 |
| Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.1423824572 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 4808718931 ps |
| CPU time | 4.47 seconds |
| Started | Mar 05 01:25:19 PM PST 24 |
| Finished | Mar 05 01:25:24 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-a01dae9f-9fc6-4137-ba51-21478830c1e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423824572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1423824572 |
| Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_regwen.1344632406 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 6329025963 ps |
| CPU time | 28.55 seconds |
| Started | Mar 05 01:25:21 PM PST 24 |
| Finished | Mar 05 01:25:50 PM PST 24 |
| Peak memory | 271348 kb |
| Host | smart-5b7555a7-a2fb-421f-8f3a-c480cad4f906 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344632406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1344632406 |
| Directory | /workspace/24.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_smoke.692894 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1576874419 ps |
| CPU time | 8.33 seconds |
| Started | Mar 05 01:25:20 PM PST 24 |
| Finished | Mar 05 01:25:29 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-2d663fc6-eac2-475a-bb60-4364c0686f7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.692894 |
| Directory | /workspace/24.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.861821838 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 37548657355 ps |
| CPU time | 1580.98 seconds |
| Started | Mar 05 01:25:20 PM PST 24 |
| Finished | Mar 05 01:51:41 PM PST 24 |
| Peak memory | 379760 kb |
| Host | smart-0247dd76-f430-4930-98d9-30199955795c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861821838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_stress_all.861821838 |
| Directory | /workspace/24.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4198436843 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1865234355 ps |
| CPU time | 51.02 seconds |
| Started | Mar 05 01:25:15 PM PST 24 |
| Finished | Mar 05 01:26:06 PM PST 24 |
| Peak memory | 249864 kb |
| Host | smart-e9e87240-f50e-457d-9774-9f4cb367214d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4198436843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.4198436843 |
| Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1565493325 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 4996962960 ps |
| CPU time | 249.35 seconds |
| Started | Mar 05 01:25:14 PM PST 24 |
| Finished | Mar 05 01:29:23 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-33849c19-b5e5-4901-a8ff-08947c6b9059 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565493325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.1565493325 |
| Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.783905608 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 3714193337 ps |
| CPU time | 18.82 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:25:32 PM PST 24 |
| Peak memory | 256400 kb |
| Host | smart-529621a8-9056-49d4-abd7-b641538e65c8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783905608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_throughput_w_partial_write.783905608 |
| Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.3657648405 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 30624071 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:25:36 PM PST 24 |
| Finished | Mar 05 01:25:37 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-04b20755-47d1-432d-a6f4-90f36d6f89e4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657648405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.3657648405 |
| Directory | /workspace/25.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_bijection.2773565278 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 78891636300 ps |
| CPU time | 1763.81 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:54:37 PM PST 24 |
| Peak memory | 202860 kb |
| Host | smart-f2bd0f01-28de-461f-96d0-24e7811de09b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773565278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .2773565278 |
| Directory | /workspace/25.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_executable.652838171 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 88890259376 ps |
| CPU time | 859.4 seconds |
| Started | Mar 05 01:25:29 PM PST 24 |
| Finished | Mar 05 01:39:49 PM PST 24 |
| Peak memory | 375792 kb |
| Host | smart-4ed789f9-9197-4adf-b5ee-d1a11ec97dba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652838171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executabl e.652838171 |
| Directory | /workspace/25.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.3296068091 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 764900590 ps |
| CPU time | 28.18 seconds |
| Started | Mar 05 01:25:16 PM PST 24 |
| Finished | Mar 05 01:25:45 PM PST 24 |
| Peak memory | 276984 kb |
| Host | smart-695b7eef-ad56-4568-881e-e98ccdfbda54 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296068091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.3296068091 |
| Directory | /workspace/25.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1995550002 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 6282652395 ps |
| CPU time | 59.44 seconds |
| Started | Mar 05 01:25:32 PM PST 24 |
| Finished | Mar 05 01:26:33 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-5ed1833b-0acf-4541-97b4-2424b00f793c |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995550002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.1995550002 |
| Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.2551348343 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 18676857781 ps |
| CPU time | 309.75 seconds |
| Started | Mar 05 01:25:19 PM PST 24 |
| Finished | Mar 05 01:30:30 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-3b628c6b-027c-41c7-b17d-e2267c04fc5d |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551348343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.2551348343 |
| Directory | /workspace/25.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.3246138346 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 23530899239 ps |
| CPU time | 1423.7 seconds |
| Started | Mar 05 01:25:21 PM PST 24 |
| Finished | Mar 05 01:49:06 PM PST 24 |
| Peak memory | 379728 kb |
| Host | smart-841a2781-bf26-4e02-99f5-853d17a7f0c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246138346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.3246138346 |
| Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.3589037262 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3090693710 ps |
| CPU time | 49.7 seconds |
| Started | Mar 05 01:25:11 PM PST 24 |
| Finished | Mar 05 01:26:01 PM PST 24 |
| Peak memory | 311032 kb |
| Host | smart-8f7279d5-50b6-4b5c-afc8-5b567ed42df4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589037262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.3589037262 |
| Directory | /workspace/25.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3942777411 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 30075489127 ps |
| CPU time | 338.99 seconds |
| Started | Mar 05 01:25:26 PM PST 24 |
| Finished | Mar 05 01:31:05 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-5bf33033-5838-409e-9fda-e2425a13fc91 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942777411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.3942777411 |
| Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.3266772611 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 705240052 ps |
| CPU time | 3.05 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:25:26 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-c303c852-3510-46bd-b9a7-79de46f54b0f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266772611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3266772611 |
| Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_regwen.364746176 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 10934669745 ps |
| CPU time | 369.34 seconds |
| Started | Mar 05 01:25:15 PM PST 24 |
| Finished | Mar 05 01:31:26 PM PST 24 |
| Peak memory | 367300 kb |
| Host | smart-9a9ff707-9af0-45df-b312-5a803b2cc110 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364746176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.364746176 |
| Directory | /workspace/25.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_smoke.3774639602 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 893418606 ps |
| CPU time | 84.91 seconds |
| Started | Mar 05 01:25:16 PM PST 24 |
| Finished | Mar 05 01:26:42 PM PST 24 |
| Peak memory | 331496 kb |
| Host | smart-a0a9c94d-f9c7-44e4-9dc3-08052613e01f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774639602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3774639602 |
| Directory | /workspace/25.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.3215395192 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 29662679587 ps |
| CPU time | 1638.69 seconds |
| Started | Mar 05 01:25:32 PM PST 24 |
| Finished | Mar 05 01:52:53 PM PST 24 |
| Peak memory | 380688 kb |
| Host | smart-c3a44517-8a58-498c-ab78-76a4d60d9f52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215395192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.3215395192 |
| Directory | /workspace/25.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2566651912 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 5028816512 ps |
| CPU time | 36.85 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:26:00 PM PST 24 |
| Peak memory | 211060 kb |
| Host | smart-e70da757-3d99-488d-b793-88d22d6c2254 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2566651912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2566651912 |
| Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3814728442 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 23580822531 ps |
| CPU time | 388.58 seconds |
| Started | Mar 05 01:25:13 PM PST 24 |
| Finished | Mar 05 01:31:42 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-cbd0e39e-a8b7-4d76-8339-aa70f2389b53 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814728442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.3814728442 |
| Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2086441256 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 7222647591 ps |
| CPU time | 26.15 seconds |
| Started | Mar 05 01:25:18 PM PST 24 |
| Finished | Mar 05 01:25:44 PM PST 24 |
| Peak memory | 284448 kb |
| Host | smart-75d9dc8b-c362-42bc-8ba0-d27b9a5ecc0e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086441256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.2086441256 |
| Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.1582918305 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 42298331 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:25:32 PM PST 24 |
| Finished | Mar 05 01:25:34 PM PST 24 |
| Peak memory | 201980 kb |
| Host | smart-96cb6c8b-225b-4667-9a76-993920274983 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582918305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.1582918305 |
| Directory | /workspace/26.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_bijection.861400279 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 41656594109 ps |
| CPU time | 962.75 seconds |
| Started | Mar 05 01:25:28 PM PST 24 |
| Finished | Mar 05 01:41:31 PM PST 24 |
| Peak memory | 202836 kb |
| Host | smart-89e6e19d-ee96-40e2-9bf1-1062f23f9ad8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861400279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 861400279 |
| Directory | /workspace/26.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_executable.320670432 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 60435061103 ps |
| CPU time | 653.26 seconds |
| Started | Mar 05 01:25:32 PM PST 24 |
| Finished | Mar 05 01:36:27 PM PST 24 |
| Peak memory | 375540 kb |
| Host | smart-4da61c80-5893-4d9b-826a-bfd89c32b7ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320670432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl e.320670432 |
| Directory | /workspace/26.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.2776924353 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 36407984043 ps |
| CPU time | 381.45 seconds |
| Started | Mar 05 01:25:24 PM PST 24 |
| Finished | Mar 05 01:31:45 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-a08f50e1-cd0c-4b68-825e-7e744f0b6f9f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776924353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.2776924353 |
| Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.108777454 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 725327804 ps |
| CPU time | 14.28 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:25:37 PM PST 24 |
| Peak memory | 243944 kb |
| Host | smart-e063dbea-a1fc-4e08-a4c2-d764447b80b6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108777454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.sram_ctrl_max_throughput.108777454 |
| Directory | /workspace/26.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1992660057 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 6535048012 ps |
| CPU time | 146.46 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:27:50 PM PST 24 |
| Peak memory | 210904 kb |
| Host | smart-9244de8a-3509-4f40-af0b-001a8e6700fb |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992660057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.1992660057 |
| Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.3067167283 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4534698653 ps |
| CPU time | 238.09 seconds |
| Started | Mar 05 01:25:32 PM PST 24 |
| Finished | Mar 05 01:29:32 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-f2efed0f-fff6-4ddc-8d76-c2a7f8130b78 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067167283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.3067167283 |
| Directory | /workspace/26.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.1402760885 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 7915563241 ps |
| CPU time | 978.43 seconds |
| Started | Mar 05 01:25:36 PM PST 24 |
| Finished | Mar 05 01:41:55 PM PST 24 |
| Peak memory | 378636 kb |
| Host | smart-2d7a6ba5-33d8-44e3-a190-35117a858a25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402760885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.1402760885 |
| Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.4258704379 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 2956643373 ps |
| CPU time | 70.09 seconds |
| Started | Mar 05 01:25:22 PM PST 24 |
| Finished | Mar 05 01:26:33 PM PST 24 |
| Peak memory | 325848 kb |
| Host | smart-45b22f79-6ce5-4042-bd0d-073dfa2a2694 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258704379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.4258704379 |
| Directory | /workspace/26.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3435042862 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 64945561606 ps |
| CPU time | 686.69 seconds |
| Started | Mar 05 01:25:36 PM PST 24 |
| Finished | Mar 05 01:37:04 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-0661a46e-6c9f-4de9-8287-7ac1fe46a886 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435042862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.3435042862 |
| Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.2156808216 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 869736576 ps |
| CPU time | 3.09 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:25:27 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-661ab365-b91e-4bc0-ac2e-f07b6d8c8be2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156808216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2156808216 |
| Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_regwen.3301412113 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 23562416217 ps |
| CPU time | 928.5 seconds |
| Started | Mar 05 01:25:22 PM PST 24 |
| Finished | Mar 05 01:40:51 PM PST 24 |
| Peak memory | 368300 kb |
| Host | smart-df0e9587-ba84-4dbd-8f6a-79c883f67530 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301412113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3301412113 |
| Directory | /workspace/26.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_smoke.334248139 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1839673857 ps |
| CPU time | 7.64 seconds |
| Started | Mar 05 01:25:32 PM PST 24 |
| Finished | Mar 05 01:25:41 PM PST 24 |
| Peak memory | 217516 kb |
| Host | smart-c4b43486-ad12-41d3-afe6-88b27275c20d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334248139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.334248139 |
| Directory | /workspace/26.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.4234794006 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2957196137 ps |
| CPU time | 14.69 seconds |
| Started | Mar 05 01:25:25 PM PST 24 |
| Finished | Mar 05 01:25:40 PM PST 24 |
| Peak memory | 211028 kb |
| Host | smart-121376c5-fd65-42aa-affa-4e18469113f0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4234794006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.4234794006 |
| Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.39855257 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3142569480 ps |
| CPU time | 190.8 seconds |
| Started | Mar 05 01:25:31 PM PST 24 |
| Finished | Mar 05 01:28:43 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-8c8148c3-3162-4818-b9c0-36836eddfb9e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39855257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_stress_pipeline.39855257 |
| Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.560986378 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2622346029 ps |
| CPU time | 25.02 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:25:48 PM PST 24 |
| Peak memory | 262092 kb |
| Host | smart-955b33d6-89a1-44d6-a835-b52c01737cba |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560986378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.560986378 |
| Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.4018782780 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 11823937 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 01:25:36 PM PST 24 |
| Finished | Mar 05 01:25:37 PM PST 24 |
| Peak memory | 202160 kb |
| Host | smart-712704ef-6b59-441e-a213-4cbce5c6d38a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018782780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.4018782780 |
| Directory | /workspace/27.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_executable.3982096503 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 40726050158 ps |
| CPU time | 1262.85 seconds |
| Started | Mar 05 01:25:27 PM PST 24 |
| Finished | Mar 05 01:46:30 PM PST 24 |
| Peak memory | 372492 kb |
| Host | smart-b7821e3f-1a27-4f06-b726-8f1ef80d455b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982096503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.3982096503 |
| Directory | /workspace/27.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.3893680851 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1540304753 ps |
| CPU time | 136.26 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:27:39 PM PST 24 |
| Peak memory | 370284 kb |
| Host | smart-feb92664-26a5-4919-8312-f443eddcc824 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893680851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.3893680851 |
| Directory | /workspace/27.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.764698991 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 298128174695 ps |
| CPU time | 399.37 seconds |
| Started | Mar 05 01:25:22 PM PST 24 |
| Finished | Mar 05 01:32:02 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-c91f01b4-d6d7-49c3-bffc-ae353b6b59d5 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764698991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl _mem_walk.764698991 |
| Directory | /workspace/27.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.2807121386 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 100762642347 ps |
| CPU time | 697.01 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:37:00 PM PST 24 |
| Peak memory | 379688 kb |
| Host | smart-b2814252-4b0c-4842-b62c-54addbdac06d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807121386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.2807121386 |
| Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.1850007937 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 585969187 ps |
| CPU time | 15.48 seconds |
| Started | Mar 05 01:25:24 PM PST 24 |
| Finished | Mar 05 01:25:40 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-93bd19b2-7452-4a78-bff1-f8e1158d4fb8 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850007937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.1850007937 |
| Directory | /workspace/27.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.709311043 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 55542902561 ps |
| CPU time | 314.96 seconds |
| Started | Mar 05 01:25:25 PM PST 24 |
| Finished | Mar 05 01:30:40 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-b353293c-ad87-4ba7-8a37-f8b9610b7dd0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709311043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 27.sram_ctrl_partial_access_b2b.709311043 |
| Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.751072500 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1400357513 ps |
| CPU time | 3.64 seconds |
| Started | Mar 05 01:25:24 PM PST 24 |
| Finished | Mar 05 01:25:28 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-46dd760e-fc7b-4664-9dbd-ab9b2e00f29c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751072500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.751072500 |
| Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_regwen.63413001 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 9217817248 ps |
| CPU time | 703.82 seconds |
| Started | Mar 05 01:25:24 PM PST 24 |
| Finished | Mar 05 01:37:08 PM PST 24 |
| Peak memory | 373548 kb |
| Host | smart-4b8fadb7-2a6c-451a-8be0-22f83d3f9701 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63413001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.63413001 |
| Directory | /workspace/27.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_smoke.1319993668 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2856349158 ps |
| CPU time | 23.23 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:25:47 PM PST 24 |
| Peak memory | 279420 kb |
| Host | smart-3ac913bb-bbff-4b0e-b32f-fb0d4475dd3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319993668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1319993668 |
| Directory | /workspace/27.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.833531639 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 37078969249 ps |
| CPU time | 1036.94 seconds |
| Started | Mar 05 01:25:36 PM PST 24 |
| Finished | Mar 05 01:42:53 PM PST 24 |
| Peak memory | 378416 kb |
| Host | smart-fe7be5c7-ca0c-4ad0-a8f6-d8f07df3d08d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833531639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_stress_all.833531639 |
| Directory | /workspace/27.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3316661483 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1929069349 ps |
| CPU time | 24.73 seconds |
| Started | Mar 05 01:25:23 PM PST 24 |
| Finished | Mar 05 01:25:48 PM PST 24 |
| Peak memory | 212228 kb |
| Host | smart-11bfbf65-0d48-405e-afbd-7814517dfd85 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3316661483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3316661483 |
| Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1066007060 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2587085156 ps |
| CPU time | 144.49 seconds |
| Started | Mar 05 01:25:25 PM PST 24 |
| Finished | Mar 05 01:27:50 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-d671b45a-f420-4c9d-8085-cd6e553fda8b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066007060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.1066007060 |
| Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.905720190 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 747932551 ps |
| CPU time | 12.92 seconds |
| Started | Mar 05 01:25:24 PM PST 24 |
| Finished | Mar 05 01:25:37 PM PST 24 |
| Peak memory | 240236 kb |
| Host | smart-c67dac58-f9cb-4b9a-8c80-6fe62aea0722 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905720190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_throughput_w_partial_write.905720190 |
| Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.3785840089 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 38918137 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 01:25:28 PM PST 24 |
| Finished | Mar 05 01:25:28 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-c0715579-556d-458a-bc5e-d48a8050aa05 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785840089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3785840089 |
| Directory | /workspace/28.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_bijection.4022104769 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 118909830092 ps |
| CPU time | 1631.7 seconds |
| Started | Mar 05 01:25:36 PM PST 24 |
| Finished | Mar 05 01:52:48 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-c5bd7ac9-d343-45f9-af58-ac8bf426e739 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022104769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .4022104769 |
| Directory | /workspace/28.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_executable.4046116861 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 19884464226 ps |
| CPU time | 555.54 seconds |
| Started | Mar 05 01:25:36 PM PST 24 |
| Finished | Mar 05 01:34:51 PM PST 24 |
| Peak memory | 377424 kb |
| Host | smart-850bd3e3-51f1-40f5-99a9-1bda8a6502e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046116861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.4046116861 |
| Directory | /workspace/28.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.905061219 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 9247180099 ps |
| CPU time | 88.07 seconds |
| Started | Mar 05 01:25:27 PM PST 24 |
| Finished | Mar 05 01:26:55 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-c8f8ba60-ffbb-490a-af43-dfa72450c4ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905061219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc alation.905061219 |
| Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.885064467 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 729187681 ps |
| CPU time | 38.45 seconds |
| Started | Mar 05 01:25:29 PM PST 24 |
| Finished | Mar 05 01:26:08 PM PST 24 |
| Peak memory | 292564 kb |
| Host | smart-6574d24d-5a2b-4dd4-a0d9-d4ecfe4f67f0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885064467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.sram_ctrl_max_throughput.885064467 |
| Directory | /workspace/28.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.1767497265 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2974122802 ps |
| CPU time | 65.66 seconds |
| Started | Mar 05 01:25:31 PM PST 24 |
| Finished | Mar 05 01:26:37 PM PST 24 |
| Peak memory | 210848 kb |
| Host | smart-083f405e-a276-4c3c-886f-b6e3e1938230 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767497265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.1767497265 |
| Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.3002540534 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 7898714756 ps |
| CPU time | 118.49 seconds |
| Started | Mar 05 01:25:32 PM PST 24 |
| Finished | Mar 05 01:27:32 PM PST 24 |
| Peak memory | 202808 kb |
| Host | smart-f1539faa-4d74-482f-b60a-e86eedd52d12 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002540534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.3002540534 |
| Directory | /workspace/28.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.1443753446 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 74743600938 ps |
| CPU time | 1283.42 seconds |
| Started | Mar 05 01:25:24 PM PST 24 |
| Finished | Mar 05 01:46:47 PM PST 24 |
| Peak memory | 379524 kb |
| Host | smart-cf7bbd03-5f4d-48fd-8b55-9f591abe7e3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443753446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.1443753446 |
| Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.1928041886 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1737127534 ps |
| CPU time | 8.31 seconds |
| Started | Mar 05 01:25:35 PM PST 24 |
| Finished | Mar 05 01:25:44 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-73450dd1-99db-45e4-bbb3-3d0b034bd8fd |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928041886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.1928041886 |
| Directory | /workspace/28.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2893248850 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 8656061659 ps |
| CPU time | 495 seconds |
| Started | Mar 05 01:25:30 PM PST 24 |
| Finished | Mar 05 01:33:46 PM PST 24 |
| Peak memory | 202828 kb |
| Host | smart-3fbee1af-ef84-485a-bbdf-a19ec0b84ff4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893248850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.2893248850 |
| Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.4084488832 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 347045118 ps |
| CPU time | 3.01 seconds |
| Started | Mar 05 01:25:28 PM PST 24 |
| Finished | Mar 05 01:25:31 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-f3a3bae4-7625-4bdc-b40c-f3c3b2f32c94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084488832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.4084488832 |
| Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_regwen.3811152971 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 7762618028 ps |
| CPU time | 639.58 seconds |
| Started | Mar 05 01:25:29 PM PST 24 |
| Finished | Mar 05 01:36:09 PM PST 24 |
| Peak memory | 379692 kb |
| Host | smart-15bfa8aa-8edc-49a7-a22b-1e20bcc2d6df |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811152971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3811152971 |
| Directory | /workspace/28.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_smoke.2295438150 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 15284799751 ps |
| CPU time | 166.49 seconds |
| Started | Mar 05 01:25:36 PM PST 24 |
| Finished | Mar 05 01:28:24 PM PST 24 |
| Peak memory | 367284 kb |
| Host | smart-2d819199-59ad-4abd-995b-d336d83b3119 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295438150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2295438150 |
| Directory | /workspace/28.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.357455499 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 29273593595 ps |
| CPU time | 4959.9 seconds |
| Started | Mar 05 01:25:32 PM PST 24 |
| Finished | Mar 05 02:48:13 PM PST 24 |
| Peak memory | 386832 kb |
| Host | smart-07667d41-ca7b-4bde-a365-f2ef9d3be7fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357455499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_stress_all.357455499 |
| Directory | /workspace/28.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1555784601 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 338916355 ps |
| CPU time | 9.36 seconds |
| Started | Mar 05 01:25:31 PM PST 24 |
| Finished | Mar 05 01:25:42 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-dc780618-0734-4d48-8e2c-6beea148d490 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1555784601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1555784601 |
| Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2605707592 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 19177899736 ps |
| CPU time | 302.31 seconds |
| Started | Mar 05 01:25:31 PM PST 24 |
| Finished | Mar 05 01:30:35 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-2266a352-c969-4fd3-9e12-7a2a0f926f72 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605707592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.2605707592 |
| Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1908921435 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 791755703 ps |
| CPU time | 77.26 seconds |
| Started | Mar 05 01:25:28 PM PST 24 |
| Finished | Mar 05 01:26:45 PM PST 24 |
| Peak memory | 350856 kb |
| Host | smart-9d43e4ec-6785-43db-a2b8-64b5866d2a8e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908921435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1908921435 |
| Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.406434301 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 111088385 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:25:39 PM PST 24 |
| Finished | Mar 05 01:25:40 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-424f9b66-8b5b-4d2f-8ce3-0de367b4e8c8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406434301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.406434301 |
| Directory | /workspace/29.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_bijection.2842396439 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 832882775387 ps |
| CPU time | 682 seconds |
| Started | Mar 05 01:25:32 PM PST 24 |
| Finished | Mar 05 01:36:56 PM PST 24 |
| Peak memory | 202808 kb |
| Host | smart-c23ca2f3-4a7a-4d2d-ab03-6dc83b19ba42 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842396439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .2842396439 |
| Directory | /workspace/29.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_executable.504778116 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 16199387565 ps |
| CPU time | 1288.24 seconds |
| Started | Mar 05 01:25:34 PM PST 24 |
| Finished | Mar 05 01:47:03 PM PST 24 |
| Peak memory | 374536 kb |
| Host | smart-33af1b22-7655-4782-b5b5-e18ffdd6efcf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504778116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executabl e.504778116 |
| Directory | /workspace/29.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.3061789943 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 10987067374 ps |
| CPU time | 173.79 seconds |
| Started | Mar 05 01:25:30 PM PST 24 |
| Finished | Mar 05 01:28:25 PM PST 24 |
| Peak memory | 210868 kb |
| Host | smart-9e7d1c6d-0cac-4c34-bdcf-bcd0ad1f50db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061789943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.3061789943 |
| Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.925771988 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1624243083 ps |
| CPU time | 68.06 seconds |
| Started | Mar 05 01:25:28 PM PST 24 |
| Finished | Mar 05 01:26:37 PM PST 24 |
| Peak memory | 336616 kb |
| Host | smart-389e0711-79ed-44d0-8466-caaa374a420c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925771988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.sram_ctrl_max_throughput.925771988 |
| Directory | /workspace/29.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3103019293 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 10628947241 ps |
| CPU time | 77.97 seconds |
| Started | Mar 05 01:25:40 PM PST 24 |
| Finished | Mar 05 01:26:58 PM PST 24 |
| Peak memory | 210908 kb |
| Host | smart-8e5f3ad1-34f8-45c1-8abb-70a3a12224f5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103019293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.3103019293 |
| Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.2979775418 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 42144090806 ps |
| CPU time | 310.03 seconds |
| Started | Mar 05 01:25:37 PM PST 24 |
| Finished | Mar 05 01:30:47 PM PST 24 |
| Peak memory | 202908 kb |
| Host | smart-b7e83ff2-ee79-495a-8256-d85114ebde9d |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979775418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.2979775418 |
| Directory | /workspace/29.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.194027357 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 12574440301 ps |
| CPU time | 635.24 seconds |
| Started | Mar 05 01:25:32 PM PST 24 |
| Finished | Mar 05 01:36:08 PM PST 24 |
| Peak memory | 363308 kb |
| Host | smart-ad7553e5-ef8f-493b-892c-620d0275c046 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194027357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multip le_keys.194027357 |
| Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.3117546039 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1416098941 ps |
| CPU time | 8.91 seconds |
| Started | Mar 05 01:25:28 PM PST 24 |
| Finished | Mar 05 01:25:37 PM PST 24 |
| Peak memory | 218332 kb |
| Host | smart-2104e7d5-3343-4646-96fa-6806e4c78fbe |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117546039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.3117546039 |
| Directory | /workspace/29.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3177832637 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 22261268041 ps |
| CPU time | 268.6 seconds |
| Started | Mar 05 01:25:35 PM PST 24 |
| Finished | Mar 05 01:30:04 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-1d78e239-3ef9-44c2-8ddd-68d0e7f92cea |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177832637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.3177832637 |
| Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.3032162635 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2104304140 ps |
| CPU time | 3.9 seconds |
| Started | Mar 05 01:25:40 PM PST 24 |
| Finished | Mar 05 01:25:44 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-8490d74b-8fd9-4a9a-baea-e2b3108b61dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032162635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3032162635 |
| Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_regwen.2273645976 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 43777121365 ps |
| CPU time | 833.66 seconds |
| Started | Mar 05 01:25:38 PM PST 24 |
| Finished | Mar 05 01:39:32 PM PST 24 |
| Peak memory | 380688 kb |
| Host | smart-b3e858a3-e144-45a0-b56f-80b3b934e39d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273645976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2273645976 |
| Directory | /workspace/29.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_smoke.956721508 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 1079661615 ps |
| CPU time | 6.85 seconds |
| Started | Mar 05 01:25:31 PM PST 24 |
| Finished | Mar 05 01:25:39 PM PST 24 |
| Peak memory | 221120 kb |
| Host | smart-69c11f73-93f7-4f6d-9a21-2fef293269f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956721508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.956721508 |
| Directory | /workspace/29.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.1265747015 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 44254414370 ps |
| CPU time | 1599.76 seconds |
| Started | Mar 05 01:25:38 PM PST 24 |
| Finished | Mar 05 01:52:19 PM PST 24 |
| Peak memory | 375576 kb |
| Host | smart-b88c0a46-3b2e-4eaf-a950-a5982c3475dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265747015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.1265747015 |
| Directory | /workspace/29.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.931256118 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3880218252 ps |
| CPU time | 211.58 seconds |
| Started | Mar 05 01:25:30 PM PST 24 |
| Finished | Mar 05 01:29:02 PM PST 24 |
| Peak memory | 202824 kb |
| Host | smart-6d77a526-19b3-47d0-a017-adc06e16a331 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931256118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29 .sram_ctrl_stress_pipeline.931256118 |
| Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3987967342 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 764844334 ps |
| CPU time | 57.5 seconds |
| Started | Mar 05 01:25:30 PM PST 24 |
| Finished | Mar 05 01:26:28 PM PST 24 |
| Peak memory | 330528 kb |
| Host | smart-5163c3f5-6dd3-4ff7-86c2-269a83035f81 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987967342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3987967342 |
| Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.2120228910 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 31737328 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 01:24:35 PM PST 24 |
| Finished | Mar 05 01:24:36 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-d6ae8492-051a-4735-9646-74cafbcc17fe |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120228910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2120228910 |
| Directory | /workspace/3.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_bijection.922187185 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 23979281993 ps |
| CPU time | 1580.59 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:50:45 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-457c1c66-ad59-4219-9216-45bd23c1080e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922187185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.922187185 |
| Directory | /workspace/3.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_executable.1905573619 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 91988333449 ps |
| CPU time | 1245.68 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:45:14 PM PST 24 |
| Peak memory | 372508 kb |
| Host | smart-62f94fab-3df2-4270-bc51-ae894a566e5b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905573619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.1905573619 |
| Directory | /workspace/3.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.3135207049 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 13412774959 ps |
| CPU time | 209.69 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 01:27:56 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-8a7a92db-e3a2-49f6-91b7-81efff1c3c8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135207049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.3135207049 |
| Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.3226615834 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2934901034 ps |
| CPU time | 25.97 seconds |
| Started | Mar 05 01:24:35 PM PST 24 |
| Finished | Mar 05 01:25:01 PM PST 24 |
| Peak memory | 268216 kb |
| Host | smart-cb5ead79-6d9f-46dd-975b-958717d8da1f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226615834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.3226615834 |
| Directory | /workspace/3.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.36071661 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 7916930578 ps |
| CPU time | 64.64 seconds |
| Started | Mar 05 01:24:43 PM PST 24 |
| Finished | Mar 05 01:25:48 PM PST 24 |
| Peak memory | 210948 kb |
| Host | smart-c2a743e4-6e95-4607-b6b3-ca86afd2bcc3 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36071661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_mem_partial_access.36071661 |
| Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.2559533952 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 21073813602 ps |
| CPU time | 306.75 seconds |
| Started | Mar 05 01:24:23 PM PST 24 |
| Finished | Mar 05 01:29:30 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-d11e4ada-116d-4346-9d9b-55bed62181c2 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559533952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.2559533952 |
| Directory | /workspace/3.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.3365074737 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 15586769748 ps |
| CPU time | 707.19 seconds |
| Started | Mar 05 01:24:33 PM PST 24 |
| Finished | Mar 05 01:36:20 PM PST 24 |
| Peak memory | 380640 kb |
| Host | smart-b0adc395-0d65-4936-9ec5-a3bd74c9fd4c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365074737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.3365074737 |
| Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.2208152755 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 1005972362 ps |
| CPU time | 10.47 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:24:37 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-4a363fde-b9cc-4a8c-aba4-082efd45c4df |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208152755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.2208152755 |
| Directory | /workspace/3.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2312327079 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 70660125207 ps |
| CPU time | 368.34 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 01:30:33 PM PST 24 |
| Peak memory | 202788 kb |
| Host | smart-6e7bbebd-a61d-4425-a672-88ce6e76da92 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312327079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.2312327079 |
| Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.1287640658 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 362381125 ps |
| CPU time | 3.04 seconds |
| Started | Mar 05 01:24:40 PM PST 24 |
| Finished | Mar 05 01:24:43 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-4a025fc7-df28-4ac8-9cc0-67e5f74a63d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287640658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1287640658 |
| Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_regwen.1387819317 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 42801185554 ps |
| CPU time | 415.93 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 01:31:21 PM PST 24 |
| Peak memory | 356104 kb |
| Host | smart-aca41566-3d34-4571-9e20-a3734eda55ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387819317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1387819317 |
| Directory | /workspace/3.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.3041284943 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 299971110 ps |
| CPU time | 2.03 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:24:31 PM PST 24 |
| Peak memory | 221724 kb |
| Host | smart-c2a489ff-94db-4020-bf07-0f89fc5334ec |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041284943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.3041284943 |
| Directory | /workspace/3.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_smoke.3402852660 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 485246598 ps |
| CPU time | 12.94 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:24:40 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-d890dd4f-8e74-4dfb-88d7-2c9f07c029c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402852660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3402852660 |
| Directory | /workspace/3.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.2877608164 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1511472939610 ps |
| CPU time | 5252.6 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 02:51:59 PM PST 24 |
| Peak memory | 388060 kb |
| Host | smart-4e6985fa-5b81-4bfe-9920-de9ae89120d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877608164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.2877608164 |
| Directory | /workspace/3.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3645608516 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 432461221 ps |
| CPU time | 14.06 seconds |
| Started | Mar 05 01:24:29 PM PST 24 |
| Finished | Mar 05 01:24:43 PM PST 24 |
| Peak memory | 211104 kb |
| Host | smart-dc20e464-c851-42a9-9fa5-64a4116283ae |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3645608516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3645608516 |
| Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.4182144643 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3659210833 ps |
| CPU time | 238.38 seconds |
| Started | Mar 05 01:24:36 PM PST 24 |
| Finished | Mar 05 01:28:35 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-8d736260-ffcb-4d18-871a-7be773825e31 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182144643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.4182144643 |
| Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1584956302 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1511716221 ps |
| CPU time | 33.49 seconds |
| Started | Mar 05 01:24:19 PM PST 24 |
| Finished | Mar 05 01:24:53 PM PST 24 |
| Peak memory | 287612 kb |
| Host | smart-35b6343c-db3c-4837-aa73-403a5b37c9ee |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584956302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1584956302 |
| Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.2163559993 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 29180002 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 01:25:49 PM PST 24 |
| Finished | Mar 05 01:25:49 PM PST 24 |
| Peak memory | 202116 kb |
| Host | smart-15e22fbb-7128-427d-bbdd-c3b065962fb0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163559993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.2163559993 |
| Directory | /workspace/30.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_bijection.1100014777 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 23609181564 ps |
| CPU time | 735.99 seconds |
| Started | Mar 05 01:25:38 PM PST 24 |
| Finished | Mar 05 01:37:54 PM PST 24 |
| Peak memory | 202832 kb |
| Host | smart-fa211b7b-5ea4-43e9-9833-26579d9fb648 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100014777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .1100014777 |
| Directory | /workspace/30.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_executable.431317721 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 35819628951 ps |
| CPU time | 893.7 seconds |
| Started | Mar 05 01:25:48 PM PST 24 |
| Finished | Mar 05 01:40:42 PM PST 24 |
| Peak memory | 378444 kb |
| Host | smart-06c21d89-12ac-485b-bf15-b8d011efaddc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431317721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executabl e.431317721 |
| Directory | /workspace/30.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.3536911158 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 26930816002 ps |
| CPU time | 272.67 seconds |
| Started | Mar 05 01:25:37 PM PST 24 |
| Finished | Mar 05 01:30:10 PM PST 24 |
| Peak memory | 210964 kb |
| Host | smart-c30d4d7c-4ef4-4295-bd06-b55a3acaba88 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536911158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.3536911158 |
| Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.2327277467 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2767247231 ps |
| CPU time | 6.29 seconds |
| Started | Mar 05 01:25:37 PM PST 24 |
| Finished | Mar 05 01:25:44 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-33e4c31a-1acb-42a5-afdb-e77daf197e78 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327277467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.2327277467 |
| Directory | /workspace/30.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.1505300397 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1930477009 ps |
| CPU time | 60.16 seconds |
| Started | Mar 05 01:25:45 PM PST 24 |
| Finished | Mar 05 01:26:46 PM PST 24 |
| Peak memory | 210872 kb |
| Host | smart-1e6682b5-7840-41fa-bd13-2492541d9553 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505300397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.1505300397 |
| Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.4246320126 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 29088568327 ps |
| CPU time | 291.63 seconds |
| Started | Mar 05 01:25:46 PM PST 24 |
| Finished | Mar 05 01:30:38 PM PST 24 |
| Peak memory | 202872 kb |
| Host | smart-c7fe58b6-8592-49f6-b2de-9018ec59c6d3 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246320126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.4246320126 |
| Directory | /workspace/30.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.499787948 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 136528080421 ps |
| CPU time | 1442.69 seconds |
| Started | Mar 05 01:25:37 PM PST 24 |
| Finished | Mar 05 01:49:40 PM PST 24 |
| Peak memory | 378692 kb |
| Host | smart-1be3ce9a-fa67-472d-b950-ccdd51bcb593 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499787948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multip le_keys.499787948 |
| Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.1477968641 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 6152624202 ps |
| CPU time | 13.62 seconds |
| Started | Mar 05 01:25:37 PM PST 24 |
| Finished | Mar 05 01:25:51 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-a98005ff-592a-4a49-8287-a9ee884df47a |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477968641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.1477968641 |
| Directory | /workspace/30.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3585601441 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 8444453244 ps |
| CPU time | 201.82 seconds |
| Started | Mar 05 01:25:40 PM PST 24 |
| Finished | Mar 05 01:29:02 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-fb3a8ec1-ee09-4865-9e8b-f6c5041993e4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585601441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3585601441 |
| Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.143296290 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1350394989 ps |
| CPU time | 3.18 seconds |
| Started | Mar 05 01:25:47 PM PST 24 |
| Finished | Mar 05 01:25:50 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-6e5de94a-9e41-49b3-90f1-336e8ebdb40e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143296290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.143296290 |
| Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_smoke.376405633 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 872462217 ps |
| CPU time | 10.18 seconds |
| Started | Mar 05 01:25:39 PM PST 24 |
| Finished | Mar 05 01:25:49 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-b1efe5c7-bd72-4331-b58b-e9763481b426 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376405633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.376405633 |
| Directory | /workspace/30.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2402125661 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2326739208 ps |
| CPU time | 164.76 seconds |
| Started | Mar 05 01:25:48 PM PST 24 |
| Finished | Mar 05 01:28:33 PM PST 24 |
| Peak memory | 374740 kb |
| Host | smart-81ac616e-63cd-4f17-bf12-a06ddf319dc8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2402125661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.2402125661 |
| Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1760491647 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 55165576535 ps |
| CPU time | 251.69 seconds |
| Started | Mar 05 01:25:38 PM PST 24 |
| Finished | Mar 05 01:29:50 PM PST 24 |
| Peak memory | 202808 kb |
| Host | smart-8573201b-24ee-4c8a-a09e-85a3ea690f90 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760491647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.1760491647 |
| Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2294609532 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3102481341 ps |
| CPU time | 61.85 seconds |
| Started | Mar 05 01:25:40 PM PST 24 |
| Finished | Mar 05 01:26:41 PM PST 24 |
| Peak memory | 309756 kb |
| Host | smart-e806400b-b21e-43f9-9723-fa53457a1853 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294609532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.2294609532 |
| Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.3933495679 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 54681909 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:25:48 PM PST 24 |
| Finished | Mar 05 01:25:49 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-62724058-7247-475e-9c50-b203aaf26136 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933495679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.3933495679 |
| Directory | /workspace/31.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_executable.906764133 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 63227635165 ps |
| CPU time | 638.79 seconds |
| Started | Mar 05 01:25:47 PM PST 24 |
| Finished | Mar 05 01:36:26 PM PST 24 |
| Peak memory | 371492 kb |
| Host | smart-3525f826-9d8a-4ec3-b2de-a08e0704b8ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906764133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executabl e.906764133 |
| Directory | /workspace/31.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.2064480602 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 48488961476 ps |
| CPU time | 501.75 seconds |
| Started | Mar 05 01:25:46 PM PST 24 |
| Finished | Mar 05 01:34:08 PM PST 24 |
| Peak memory | 210972 kb |
| Host | smart-fa2ec552-fd69-4e02-9ac2-109f8efbe42c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064480602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.2064480602 |
| Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.4154501804 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 1727568955 ps |
| CPU time | 99.42 seconds |
| Started | Mar 05 01:25:47 PM PST 24 |
| Finished | Mar 05 01:27:26 PM PST 24 |
| Peak memory | 356752 kb |
| Host | smart-2dbb2472-d812-4143-9cf9-fd9881b2e2ef |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154501804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.4154501804 |
| Directory | /workspace/31.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2319395727 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 9808695463 ps |
| CPU time | 76.23 seconds |
| Started | Mar 05 01:25:48 PM PST 24 |
| Finished | Mar 05 01:27:04 PM PST 24 |
| Peak memory | 211016 kb |
| Host | smart-73f2dfa6-f2be-4d21-a925-4e6fac6cb83b |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319395727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.2319395727 |
| Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.2387372944 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 15769466962 ps |
| CPU time | 244.06 seconds |
| Started | Mar 05 01:25:53 PM PST 24 |
| Finished | Mar 05 01:29:57 PM PST 24 |
| Peak memory | 202784 kb |
| Host | smart-f1f1e0a2-9885-4995-9a5f-50f322c5e6b0 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387372944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.2387372944 |
| Directory | /workspace/31.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.2788075854 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2672431416 ps |
| CPU time | 9.37 seconds |
| Started | Mar 05 01:25:46 PM PST 24 |
| Finished | Mar 05 01:25:56 PM PST 24 |
| Peak memory | 228220 kb |
| Host | smart-78d943f1-2676-4342-b42e-6e5b4820eb93 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788075854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.2788075854 |
| Directory | /workspace/31.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1269846898 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 45792479816 ps |
| CPU time | 466.75 seconds |
| Started | Mar 05 01:25:49 PM PST 24 |
| Finished | Mar 05 01:33:37 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-ed423c0c-4efa-4b81-b588-1c0fe9c8e1b1 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269846898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.1269846898 |
| Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.802143312 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 724025242 ps |
| CPU time | 3.21 seconds |
| Started | Mar 05 01:25:47 PM PST 24 |
| Finished | Mar 05 01:25:50 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-a0c2590d-52e0-4226-9c3c-4e40f40e37e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802143312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.802143312 |
| Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_regwen.4618279 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 75885954604 ps |
| CPU time | 1404.08 seconds |
| Started | Mar 05 01:25:46 PM PST 24 |
| Finished | Mar 05 01:49:11 PM PST 24 |
| Peak memory | 380352 kb |
| Host | smart-32b83a1c-ed74-4aff-a75c-a3d309c3db54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4618279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.4618279 |
| Directory | /workspace/31.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_smoke.508593442 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 877650592 ps |
| CPU time | 84.66 seconds |
| Started | Mar 05 01:25:47 PM PST 24 |
| Finished | Mar 05 01:27:12 PM PST 24 |
| Peak memory | 345736 kb |
| Host | smart-12e7d601-afd0-4520-8219-b200dc4bba75 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508593442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.508593442 |
| Directory | /workspace/31.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.1673073244 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 253061216200 ps |
| CPU time | 7026.19 seconds |
| Started | Mar 05 01:25:48 PM PST 24 |
| Finished | Mar 05 03:22:55 PM PST 24 |
| Peak memory | 376728 kb |
| Host | smart-2209052c-7860-475b-8952-0a2799fae5c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673073244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.1673073244 |
| Directory | /workspace/31.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3496585934 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3154754266 ps |
| CPU time | 21.07 seconds |
| Started | Mar 05 01:25:48 PM PST 24 |
| Finished | Mar 05 01:26:09 PM PST 24 |
| Peak memory | 211040 kb |
| Host | smart-7cd5a217-d955-461a-8d73-3725ca12a81d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3496585934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3496585934 |
| Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.4231547504 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 4144655017 ps |
| CPU time | 248.63 seconds |
| Started | Mar 05 01:25:47 PM PST 24 |
| Finished | Mar 05 01:29:56 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-f772503f-1458-4b0a-b656-a9303ab76b1f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231547504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.4231547504 |
| Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.432065407 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 744924501 ps |
| CPU time | 17.51 seconds |
| Started | Mar 05 01:25:48 PM PST 24 |
| Finished | Mar 05 01:26:05 PM PST 24 |
| Peak memory | 261848 kb |
| Host | smart-87c1b74c-f434-49b2-8acc-6e85c1acda9e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432065407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.432065407 |
| Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.596622827 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 13860453 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 01:25:58 PM PST 24 |
| Finished | Mar 05 01:25:59 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-58753041-2098-4693-848e-5de5ddb0a7a5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596622827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.596622827 |
| Directory | /workspace/32.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_bijection.160547121 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 126122456744 ps |
| CPU time | 1646.55 seconds |
| Started | Mar 05 01:25:57 PM PST 24 |
| Finished | Mar 05 01:53:24 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-4c3febeb-ccee-497e-a67d-f2b6afe5c41c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160547121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection. 160547121 |
| Directory | /workspace/32.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_executable.3693469450 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 22089223114 ps |
| CPU time | 1201.91 seconds |
| Started | Mar 05 01:26:00 PM PST 24 |
| Finished | Mar 05 01:46:02 PM PST 24 |
| Peak memory | 378580 kb |
| Host | smart-ec0766ec-a2c4-4502-9487-4b04ab74fccd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693469450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.3693469450 |
| Directory | /workspace/32.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.3717746396 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 13593314434 ps |
| CPU time | 165.59 seconds |
| Started | Mar 05 01:26:03 PM PST 24 |
| Finished | Mar 05 01:28:49 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-9508653f-c42d-4f94-b6cc-a92a41ac8f50 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717746396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.3717746396 |
| Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.4160408152 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2690884933 ps |
| CPU time | 123.68 seconds |
| Started | Mar 05 01:25:57 PM PST 24 |
| Finished | Mar 05 01:28:01 PM PST 24 |
| Peak memory | 350896 kb |
| Host | smart-85c4becf-c497-4586-8340-a4acde7d41b5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160408152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.4160408152 |
| Directory | /workspace/32.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1255780851 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2800607658 ps |
| CPU time | 78.67 seconds |
| Started | Mar 05 01:25:55 PM PST 24 |
| Finished | Mar 05 01:27:15 PM PST 24 |
| Peak memory | 211024 kb |
| Host | smart-f6342728-4c09-46e1-ac75-c1c54fccd3e4 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255780851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.1255780851 |
| Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.1326595223 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 86001580907 ps |
| CPU time | 322.4 seconds |
| Started | Mar 05 01:25:58 PM PST 24 |
| Finished | Mar 05 01:31:20 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-3e9404e1-0404-4f20-9026-2ef131e3256c |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326595223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.1326595223 |
| Directory | /workspace/32.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.3262392597 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 5606697484 ps |
| CPU time | 456.58 seconds |
| Started | Mar 05 01:26:00 PM PST 24 |
| Finished | Mar 05 01:33:37 PM PST 24 |
| Peak memory | 371532 kb |
| Host | smart-c456f0f3-8fb5-4496-bc94-5724947e5ace |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262392597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.3262392597 |
| Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.1878385907 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3527051981 ps |
| CPU time | 15.67 seconds |
| Started | Mar 05 01:25:57 PM PST 24 |
| Finished | Mar 05 01:26:12 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-2a047564-26f5-49cd-b4c2-eafd92649e75 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878385907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.1878385907 |
| Directory | /workspace/32.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4276028846 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 87193233506 ps |
| CPU time | 466.89 seconds |
| Started | Mar 05 01:26:00 PM PST 24 |
| Finished | Mar 05 01:33:47 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-b3f90c70-cb31-4dce-94b0-7618469b01c9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276028846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.4276028846 |
| Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.1498717643 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2805063263 ps |
| CPU time | 3.91 seconds |
| Started | Mar 05 01:26:03 PM PST 24 |
| Finished | Mar 05 01:26:07 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-2ff6b517-5578-4e1e-afca-a3f3ccc062fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498717643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1498717643 |
| Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_regwen.3385678660 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 106370739995 ps |
| CPU time | 1219.81 seconds |
| Started | Mar 05 01:26:00 PM PST 24 |
| Finished | Mar 05 01:46:20 PM PST 24 |
| Peak memory | 379516 kb |
| Host | smart-724bca53-3ce3-410b-848c-6a078ae4a197 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385678660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.3385678660 |
| Directory | /workspace/32.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_smoke.508757956 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2026221883 ps |
| CPU time | 19.07 seconds |
| Started | Mar 05 01:25:49 PM PST 24 |
| Finished | Mar 05 01:26:08 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-453fa0fc-70e6-41ef-ac3a-7113568d2728 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508757956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.508757956 |
| Directory | /workspace/32.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.328673569 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 170110067001 ps |
| CPU time | 7172.98 seconds |
| Started | Mar 05 01:25:59 PM PST 24 |
| Finished | Mar 05 03:25:33 PM PST 24 |
| Peak memory | 386396 kb |
| Host | smart-c5f477b4-1ebf-4251-8172-265174f3949a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328673569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_stress_all.328673569 |
| Directory | /workspace/32.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1102456610 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 9089554913 ps |
| CPU time | 36.26 seconds |
| Started | Mar 05 01:25:58 PM PST 24 |
| Finished | Mar 05 01:26:34 PM PST 24 |
| Peak memory | 211148 kb |
| Host | smart-a37f0c41-5dbf-497a-8a45-6db4f477e45c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1102456610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1102456610 |
| Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2861179452 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2964399382 ps |
| CPU time | 167.38 seconds |
| Started | Mar 05 01:25:58 PM PST 24 |
| Finished | Mar 05 01:28:45 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-6cbb2f56-b051-42a7-a4ac-d48baed7f7d0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861179452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.2861179452 |
| Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.859337021 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2925820156 ps |
| CPU time | 50.93 seconds |
| Started | Mar 05 01:25:59 PM PST 24 |
| Finished | Mar 05 01:26:50 PM PST 24 |
| Peak memory | 291932 kb |
| Host | smart-853bbdd7-34a3-4659-b007-4c4c83405d90 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859337021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_throughput_w_partial_write.859337021 |
| Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.198542423 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 13456055 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 01:25:59 PM PST 24 |
| Finished | Mar 05 01:26:00 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-5fea6256-23f2-488b-b5b0-d3ea4b7c2fff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198542423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.198542423 |
| Directory | /workspace/33.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_bijection.3623034608 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 19309019623 ps |
| CPU time | 1271.1 seconds |
| Started | Mar 05 01:26:00 PM PST 24 |
| Finished | Mar 05 01:47:12 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-0a410cf3-c544-42d0-92a6-a716947238fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623034608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .3623034608 |
| Directory | /workspace/33.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_executable.1947266129 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 44423046516 ps |
| CPU time | 674.43 seconds |
| Started | Mar 05 01:25:59 PM PST 24 |
| Finished | Mar 05 01:37:13 PM PST 24 |
| Peak memory | 373548 kb |
| Host | smart-08a78bc2-ef26-4971-a949-61a54887a7fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947266129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.1947266129 |
| Directory | /workspace/33.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.3203010569 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 16472523796 ps |
| CPU time | 197.42 seconds |
| Started | Mar 05 01:26:00 PM PST 24 |
| Finished | Mar 05 01:29:17 PM PST 24 |
| Peak memory | 210820 kb |
| Host | smart-f06595e3-bcf4-4796-b103-cd5f80b6edc1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203010569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.3203010569 |
| Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.2945041312 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2692944650 ps |
| CPU time | 7.74 seconds |
| Started | Mar 05 01:25:58 PM PST 24 |
| Finished | Mar 05 01:26:06 PM PST 24 |
| Peak memory | 216256 kb |
| Host | smart-0c3f44e3-b357-49c7-b1fb-22ec8bc86dc5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945041312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.2945041312 |
| Directory | /workspace/33.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3121308131 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 4355295298 ps |
| CPU time | 143.22 seconds |
| Started | Mar 05 01:25:58 PM PST 24 |
| Finished | Mar 05 01:28:22 PM PST 24 |
| Peak memory | 210936 kb |
| Host | smart-f9ae0fcf-7b45-4880-88a9-b66422262f29 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121308131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.3121308131 |
| Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.3697655657 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 19127114715 ps |
| CPU time | 139.58 seconds |
| Started | Mar 05 01:25:57 PM PST 24 |
| Finished | Mar 05 01:28:17 PM PST 24 |
| Peak memory | 202972 kb |
| Host | smart-1ad199d1-d75d-4d43-882a-b58abb731cf4 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697655657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.3697655657 |
| Directory | /workspace/33.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.2729648184 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 24224522475 ps |
| CPU time | 448.39 seconds |
| Started | Mar 05 01:25:58 PM PST 24 |
| Finished | Mar 05 01:33:27 PM PST 24 |
| Peak memory | 377240 kb |
| Host | smart-335b72d8-139f-4f22-8760-380e0e5bc02e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729648184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.2729648184 |
| Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.1742090822 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1898541933 ps |
| CPU time | 21.21 seconds |
| Started | Mar 05 01:25:59 PM PST 24 |
| Finished | Mar 05 01:26:20 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-7181976c-ed02-4d48-9fd5-991de4af3478 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742090822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.1742090822 |
| Directory | /workspace/33.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1791264984 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 39284573898 ps |
| CPU time | 458.74 seconds |
| Started | Mar 05 01:25:58 PM PST 24 |
| Finished | Mar 05 01:33:37 PM PST 24 |
| Peak memory | 202812 kb |
| Host | smart-792afcf5-9085-4f58-b5e8-f773f3265426 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791264984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.1791264984 |
| Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.2901857670 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 5594897495 ps |
| CPU time | 4.09 seconds |
| Started | Mar 05 01:25:59 PM PST 24 |
| Finished | Mar 05 01:26:03 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-bafbf08e-af39-4732-8df5-047ee9d916d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901857670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2901857670 |
| Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_regwen.3288944906 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 62680581989 ps |
| CPU time | 696.35 seconds |
| Started | Mar 05 01:25:57 PM PST 24 |
| Finished | Mar 05 01:37:33 PM PST 24 |
| Peak memory | 364344 kb |
| Host | smart-b4898ec9-7d09-4e26-be1b-33edce6f4aa6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288944906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3288944906 |
| Directory | /workspace/33.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_smoke.4085760298 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 5601469681 ps |
| CPU time | 20.65 seconds |
| Started | Mar 05 01:26:03 PM PST 24 |
| Finished | Mar 05 01:26:24 PM PST 24 |
| Peak memory | 202788 kb |
| Host | smart-eb88569d-41d8-41ab-b768-d7923fc7516d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085760298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.4085760298 |
| Directory | /workspace/33.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.2123026321 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2251968019059 ps |
| CPU time | 9384.47 seconds |
| Started | Mar 05 01:25:59 PM PST 24 |
| Finished | Mar 05 04:02:25 PM PST 24 |
| Peak memory | 380672 kb |
| Host | smart-a9170c79-ee65-4e1a-8241-46028c8b2f27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123026321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.2123026321 |
| Directory | /workspace/33.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2859496688 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 21912264253 ps |
| CPU time | 35.82 seconds |
| Started | Mar 05 01:25:58 PM PST 24 |
| Finished | Mar 05 01:26:34 PM PST 24 |
| Peak memory | 219244 kb |
| Host | smart-0847207f-05d0-4ccf-9be0-52c29c9d4f04 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2859496688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.2859496688 |
| Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2004495589 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 22747588385 ps |
| CPU time | 298.63 seconds |
| Started | Mar 05 01:25:56 PM PST 24 |
| Finished | Mar 05 01:30:55 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-3cb62952-6cd1-4eda-b078-19e63380dcdb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004495589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.2004495589 |
| Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3304264520 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 864682596 ps |
| CPU time | 151.92 seconds |
| Started | Mar 05 01:25:57 PM PST 24 |
| Finished | Mar 05 01:28:29 PM PST 24 |
| Peak memory | 369452 kb |
| Host | smart-ca6c336b-82db-4436-bd07-f06f1318c3cd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304264520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3304264520 |
| Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.2348182167 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 39248792 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:26:05 PM PST 24 |
| Finished | Mar 05 01:26:06 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-e6296073-34b7-4653-915c-7ccbabf6b2b1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348182167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2348182167 |
| Directory | /workspace/34.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_bijection.1701381044 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 112224924465 ps |
| CPU time | 2026.23 seconds |
| Started | Mar 05 01:26:10 PM PST 24 |
| Finished | Mar 05 01:59:56 PM PST 24 |
| Peak memory | 202976 kb |
| Host | smart-88ea8562-17da-4860-af26-5a564aac8edb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701381044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .1701381044 |
| Directory | /workspace/34.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.906599874 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 6746100060 ps |
| CPU time | 102.04 seconds |
| Started | Mar 05 01:26:08 PM PST 24 |
| Finished | Mar 05 01:27:50 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-923e585e-a721-4aea-bacf-1014ef9eccb4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906599874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esc alation.906599874 |
| Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.525243232 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 716577767 ps |
| CPU time | 10.91 seconds |
| Started | Mar 05 01:26:06 PM PST 24 |
| Finished | Mar 05 01:26:17 PM PST 24 |
| Peak memory | 235492 kb |
| Host | smart-d22f7333-f23f-4a23-a19d-130ead2de741 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525243232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.sram_ctrl_max_throughput.525243232 |
| Directory | /workspace/34.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2638068687 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1230035686 ps |
| CPU time | 61.54 seconds |
| Started | Mar 05 01:26:07 PM PST 24 |
| Finished | Mar 05 01:27:09 PM PST 24 |
| Peak memory | 210872 kb |
| Host | smart-76d6aa76-9a12-41d1-80ee-2cc9f02f6273 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638068687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.2638068687 |
| Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.2553381261 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 42976510861 ps |
| CPU time | 161.76 seconds |
| Started | Mar 05 01:26:06 PM PST 24 |
| Finished | Mar 05 01:28:48 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-c551f505-c199-410c-ae49-c0a7873f3068 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553381261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.2553381261 |
| Directory | /workspace/34.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.4010800591 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 14286179718 ps |
| CPU time | 507.83 seconds |
| Started | Mar 05 01:26:07 PM PST 24 |
| Finished | Mar 05 01:34:35 PM PST 24 |
| Peak memory | 379680 kb |
| Host | smart-628a822a-897a-4d2b-ba5a-47c1bdecaf4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010800591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.4010800591 |
| Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.2874057014 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 9809445216 ps |
| CPU time | 127.84 seconds |
| Started | Mar 05 01:26:07 PM PST 24 |
| Finished | Mar 05 01:28:15 PM PST 24 |
| Peak memory | 366528 kb |
| Host | smart-f9d1f3c3-5e50-4973-b633-35af664aea1d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874057014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.2874057014 |
| Directory | /workspace/34.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2167578966 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 15824340996 ps |
| CPU time | 314.87 seconds |
| Started | Mar 05 01:26:06 PM PST 24 |
| Finished | Mar 05 01:31:22 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-973b3552-31f0-441f-b969-4ae86ad3905c |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167578966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.2167578966 |
| Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.2902352610 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2236249332 ps |
| CPU time | 3.38 seconds |
| Started | Mar 05 01:26:09 PM PST 24 |
| Finished | Mar 05 01:26:12 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-84e29cb4-5fd1-4c84-bb9d-8724874757ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902352610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2902352610 |
| Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_regwen.1774369392 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3727171468 ps |
| CPU time | 626.85 seconds |
| Started | Mar 05 01:26:06 PM PST 24 |
| Finished | Mar 05 01:36:33 PM PST 24 |
| Peak memory | 357172 kb |
| Host | smart-37367949-614a-47ba-b472-d728eb456655 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774369392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1774369392 |
| Directory | /workspace/34.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_smoke.1939678328 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1420586726 ps |
| CPU time | 18.75 seconds |
| Started | Mar 05 01:25:59 PM PST 24 |
| Finished | Mar 05 01:26:18 PM PST 24 |
| Peak memory | 257092 kb |
| Host | smart-e6eba9ca-6e15-4b56-8552-7e3cce992575 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939678328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1939678328 |
| Directory | /workspace/34.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.652976197 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 604950406325 ps |
| CPU time | 8005.81 seconds |
| Started | Mar 05 01:26:07 PM PST 24 |
| Finished | Mar 05 03:39:34 PM PST 24 |
| Peak memory | 382552 kb |
| Host | smart-c0596a58-5609-4c74-a6a9-091dc7f6c36c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652976197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_stress_all.652976197 |
| Directory | /workspace/34.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2652563445 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2332558156 ps |
| CPU time | 33.61 seconds |
| Started | Mar 05 01:26:09 PM PST 24 |
| Finished | Mar 05 01:26:42 PM PST 24 |
| Peak memory | 212160 kb |
| Host | smart-454da986-e9e9-40c3-8b5c-06caff6c451f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2652563445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2652563445 |
| Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4196210059 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3231969803 ps |
| CPU time | 182.42 seconds |
| Started | Mar 05 01:26:08 PM PST 24 |
| Finished | Mar 05 01:29:10 PM PST 24 |
| Peak memory | 202844 kb |
| Host | smart-8c6ce316-f6d8-466a-879a-43f30484d394 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196210059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.4196210059 |
| Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1128931510 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1499850615 ps |
| CPU time | 108.79 seconds |
| Started | Mar 05 01:26:07 PM PST 24 |
| Finished | Mar 05 01:27:56 PM PST 24 |
| Peak memory | 344804 kb |
| Host | smart-7bc3fe97-6792-49bf-ba3f-e8bb59284758 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128931510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1128931510 |
| Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.2610507619 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 27087939 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:26:18 PM PST 24 |
| Finished | Mar 05 01:26:19 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-e43372ec-f3b8-4a71-8090-cfb3ec68d7fe |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610507619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2610507619 |
| Directory | /workspace/35.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_bijection.4013899477 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 69912100655 ps |
| CPU time | 1564.26 seconds |
| Started | Mar 05 01:26:10 PM PST 24 |
| Finished | Mar 05 01:52:15 PM PST 24 |
| Peak memory | 202956 kb |
| Host | smart-862e921d-acd7-4ed8-ba7b-5ce8ea8ca478 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013899477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .4013899477 |
| Directory | /workspace/35.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_executable.2342083411 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 62458246498 ps |
| CPU time | 975.38 seconds |
| Started | Mar 05 01:26:09 PM PST 24 |
| Finished | Mar 05 01:42:24 PM PST 24 |
| Peak memory | 376500 kb |
| Host | smart-120b5a00-ab36-4d30-9d03-0fec4ef3e878 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342083411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.2342083411 |
| Directory | /workspace/35.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.523918801 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 5665272041 ps |
| CPU time | 8.81 seconds |
| Started | Mar 05 01:26:10 PM PST 24 |
| Finished | Mar 05 01:26:19 PM PST 24 |
| Peak memory | 220728 kb |
| Host | smart-f42ce0a1-09b6-4f0b-a2b1-afdf7487689a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523918801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.sram_ctrl_max_throughput.523918801 |
| Directory | /workspace/35.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3253887160 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 3790251487 ps |
| CPU time | 65.53 seconds |
| Started | Mar 05 01:26:07 PM PST 24 |
| Finished | Mar 05 01:27:12 PM PST 24 |
| Peak memory | 210984 kb |
| Host | smart-0a5188e8-3270-49d7-bf0a-1e9c5feb6eac |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253887160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.3253887160 |
| Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.576453746 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 55096558034 ps |
| CPU time | 305.28 seconds |
| Started | Mar 05 01:26:09 PM PST 24 |
| Finished | Mar 05 01:31:14 PM PST 24 |
| Peak memory | 203300 kb |
| Host | smart-f7f31fdd-e7ae-4f25-a1fc-7400c4132e5e |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576453746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _mem_walk.576453746 |
| Directory | /workspace/35.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.3518085840 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 17747769848 ps |
| CPU time | 464.58 seconds |
| Started | Mar 05 01:26:14 PM PST 24 |
| Finished | Mar 05 01:33:58 PM PST 24 |
| Peak memory | 374476 kb |
| Host | smart-ea8bef9f-bd46-4a47-9923-77923269c151 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518085840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.3518085840 |
| Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.1073227697 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2027264010 ps |
| CPU time | 14.45 seconds |
| Started | Mar 05 01:26:06 PM PST 24 |
| Finished | Mar 05 01:26:21 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-77ce655a-f218-4887-b2f5-1f026946cdc4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073227697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.1073227697 |
| Directory | /workspace/35.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.96738382 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 8992344511 ps |
| CPU time | 222.98 seconds |
| Started | Mar 05 01:26:09 PM PST 24 |
| Finished | Mar 05 01:29:52 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-663051c8-63e1-4041-9ee8-c8bf462b25a9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96738382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_partial_access_b2b.96738382 |
| Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.2456831670 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 361187088 ps |
| CPU time | 3.05 seconds |
| Started | Mar 05 01:26:09 PM PST 24 |
| Finished | Mar 05 01:26:12 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-82821abb-5576-4c43-a7a9-920e83151d5f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456831670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2456831670 |
| Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_regwen.1960680711 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 65200898759 ps |
| CPU time | 980.64 seconds |
| Started | Mar 05 01:26:09 PM PST 24 |
| Finished | Mar 05 01:42:30 PM PST 24 |
| Peak memory | 377624 kb |
| Host | smart-bd052d29-9a0c-42c0-8881-7a012ef3e903 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960680711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1960680711 |
| Directory | /workspace/35.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_smoke.3504881330 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 410923354 ps |
| CPU time | 5.42 seconds |
| Started | Mar 05 01:26:10 PM PST 24 |
| Finished | Mar 05 01:26:15 PM PST 24 |
| Peak memory | 210704 kb |
| Host | smart-d2b14815-e3ee-4db8-bb86-03eb8f1e0079 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504881330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3504881330 |
| Directory | /workspace/35.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.1223285454 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 805286361320 ps |
| CPU time | 5192.73 seconds |
| Started | Mar 05 01:26:18 PM PST 24 |
| Finished | Mar 05 02:52:51 PM PST 24 |
| Peak memory | 378656 kb |
| Host | smart-f297f413-a570-4be4-8961-6f87df1823e8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223285454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.1223285454 |
| Directory | /workspace/35.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3039819810 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2547090070 ps |
| CPU time | 106.12 seconds |
| Started | Mar 05 01:26:17 PM PST 24 |
| Finished | Mar 05 01:28:03 PM PST 24 |
| Peak memory | 218164 kb |
| Host | smart-3a546ad3-d53c-4dd9-a25e-76ee28f77c4e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3039819810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3039819810 |
| Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3303695085 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 4402866751 ps |
| CPU time | 274.78 seconds |
| Started | Mar 05 01:26:14 PM PST 24 |
| Finished | Mar 05 01:30:48 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-bb614da2-143a-4712-9d17-8addd5de1260 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303695085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.3303695085 |
| Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2497330272 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 3697613992 ps |
| CPU time | 35.49 seconds |
| Started | Mar 05 01:26:14 PM PST 24 |
| Finished | Mar 05 01:26:49 PM PST 24 |
| Peak memory | 292436 kb |
| Host | smart-e61c3dd7-0132-48f4-a470-01f2493ddafe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497330272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.2497330272 |
| Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.1352209844 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 14498106 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:26:20 PM PST 24 |
| Finished | Mar 05 01:26:21 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-9319f0bc-8310-4a72-9751-18695e5f7f24 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352209844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1352209844 |
| Directory | /workspace/36.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_bijection.1221123771 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 718398633472 ps |
| CPU time | 2806.64 seconds |
| Started | Mar 05 01:26:18 PM PST 24 |
| Finished | Mar 05 02:13:05 PM PST 24 |
| Peak memory | 203028 kb |
| Host | smart-486f7a6e-3aee-4de4-ac64-66a57e56fd33 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221123771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .1221123771 |
| Directory | /workspace/36.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_executable.303198727 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 43714746859 ps |
| CPU time | 790.21 seconds |
| Started | Mar 05 01:26:18 PM PST 24 |
| Finished | Mar 05 01:39:29 PM PST 24 |
| Peak memory | 375592 kb |
| Host | smart-70d2c25e-7cd2-422e-8bb1-1dba156766d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303198727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executabl e.303198727 |
| Directory | /workspace/36.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.60072124 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 16615560040 ps |
| CPU time | 252.09 seconds |
| Started | Mar 05 01:26:18 PM PST 24 |
| Finished | Mar 05 01:30:30 PM PST 24 |
| Peak memory | 202808 kb |
| Host | smart-8a152fa9-77eb-4573-8d99-630f576c7ec1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60072124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_esca lation.60072124 |
| Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.3451936240 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 779178284 ps |
| CPU time | 112.57 seconds |
| Started | Mar 05 01:26:20 PM PST 24 |
| Finished | Mar 05 01:28:12 PM PST 24 |
| Peak memory | 366292 kb |
| Host | smart-522dfc2e-b463-4b95-a5aa-4fb7f77a8d87 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451936240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.3451936240 |
| Directory | /workspace/36.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2963088783 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1599684878 ps |
| CPU time | 123.62 seconds |
| Started | Mar 05 01:26:18 PM PST 24 |
| Finished | Mar 05 01:28:22 PM PST 24 |
| Peak memory | 210900 kb |
| Host | smart-b11aa94a-3018-47b1-a337-559514720a11 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963088783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.2963088783 |
| Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.1498053824 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 15763178063 ps |
| CPU time | 246.92 seconds |
| Started | Mar 05 01:26:22 PM PST 24 |
| Finished | Mar 05 01:30:29 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-de35c745-a6c0-4d6e-bb25-547a39086f85 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498053824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.1498053824 |
| Directory | /workspace/36.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.2867572667 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 86109810483 ps |
| CPU time | 1096.3 seconds |
| Started | Mar 05 01:26:17 PM PST 24 |
| Finished | Mar 05 01:44:34 PM PST 24 |
| Peak memory | 377540 kb |
| Host | smart-5593fe50-6690-4372-bf18-9e3c23d70005 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867572667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.2867572667 |
| Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.4263630216 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 2924743685 ps |
| CPU time | 8.43 seconds |
| Started | Mar 05 01:26:18 PM PST 24 |
| Finished | Mar 05 01:26:26 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-06d950d6-ffce-4791-b8ab-29def9965c26 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263630216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.4263630216 |
| Directory | /workspace/36.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2496742966 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 150945486652 ps |
| CPU time | 453.48 seconds |
| Started | Mar 05 01:26:20 PM PST 24 |
| Finished | Mar 05 01:33:54 PM PST 24 |
| Peak memory | 202844 kb |
| Host | smart-cc89f2fe-89b3-4e98-b215-ddd94ee86898 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496742966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.2496742966 |
| Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.1664518221 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 377961485 ps |
| CPU time | 3.05 seconds |
| Started | Mar 05 01:26:20 PM PST 24 |
| Finished | Mar 05 01:26:23 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-b372161b-0840-431b-a85f-6eaf251f4512 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664518221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1664518221 |
| Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_regwen.3026342778 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 10460619143 ps |
| CPU time | 964.62 seconds |
| Started | Mar 05 01:26:19 PM PST 24 |
| Finished | Mar 05 01:42:24 PM PST 24 |
| Peak memory | 380980 kb |
| Host | smart-787654cd-84b4-43ab-a317-fd1131f5648a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026342778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3026342778 |
| Directory | /workspace/36.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_smoke.2530343040 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 967534780 ps |
| CPU time | 5.49 seconds |
| Started | Mar 05 01:26:18 PM PST 24 |
| Finished | Mar 05 01:26:24 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-ac1da47e-c27f-4dd5-85fb-d48f72e88fa3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530343040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2530343040 |
| Directory | /workspace/36.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1997090753 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2172805699 ps |
| CPU time | 120.93 seconds |
| Started | Mar 05 01:26:20 PM PST 24 |
| Finished | Mar 05 01:28:21 PM PST 24 |
| Peak memory | 310680 kb |
| Host | smart-bfeb51e7-8e9d-4104-b247-4eff94546b15 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1997090753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1997090753 |
| Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.181281878 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 16353835905 ps |
| CPU time | 145.62 seconds |
| Started | Mar 05 01:26:19 PM PST 24 |
| Finished | Mar 05 01:28:45 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-3bc02c25-cfbf-414f-9906-da8bbc03a237 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181281878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36 .sram_ctrl_stress_pipeline.181281878 |
| Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.4127241381 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 15176109091 ps |
| CPU time | 88.03 seconds |
| Started | Mar 05 01:26:18 PM PST 24 |
| Finished | Mar 05 01:27:46 PM PST 24 |
| Peak memory | 334572 kb |
| Host | smart-4a8a8406-ac2c-4eb9-be95-4bb0064dac07 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127241381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.4127241381 |
| Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.3245449541 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 16968689 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:26:31 PM PST 24 |
| Finished | Mar 05 01:26:31 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-a63268b5-19e3-40b3-b31d-a4067f573adb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245449541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3245449541 |
| Directory | /workspace/37.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_bijection.1177345281 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 53185340699 ps |
| CPU time | 1744.44 seconds |
| Started | Mar 05 01:26:21 PM PST 24 |
| Finished | Mar 05 01:55:26 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-8ff5bd60-3e49-4949-bf43-abdbc21e9fc9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177345281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .1177345281 |
| Directory | /workspace/37.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_executable.18209550 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 3229682167 ps |
| CPU time | 248.52 seconds |
| Started | Mar 05 01:26:29 PM PST 24 |
| Finished | Mar 05 01:30:39 PM PST 24 |
| Peak memory | 351792 kb |
| Host | smart-97d90168-2804-4a3e-b22c-df0fd2fd4b35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18209550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable .18209550 |
| Directory | /workspace/37.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.387168163 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5025994108 ps |
| CPU time | 77.5 seconds |
| Started | Mar 05 01:26:26 PM PST 24 |
| Finished | Mar 05 01:27:45 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-f9e0d43e-7439-4e85-a926-df5a4cc964d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387168163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc alation.387168163 |
| Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.113623788 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 773595244 ps |
| CPU time | 26.31 seconds |
| Started | Mar 05 01:26:24 PM PST 24 |
| Finished | Mar 05 01:26:51 PM PST 24 |
| Peak memory | 284492 kb |
| Host | smart-fc6b6602-b360-4c4c-83b9-7a56d200e74e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113623788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.sram_ctrl_max_throughput.113623788 |
| Directory | /workspace/37.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1521053535 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4537438103 ps |
| CPU time | 77.29 seconds |
| Started | Mar 05 01:26:31 PM PST 24 |
| Finished | Mar 05 01:27:49 PM PST 24 |
| Peak memory | 211004 kb |
| Host | smart-70c4cdc3-6000-463d-b286-adbd5fe6f3b1 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521053535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.1521053535 |
| Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.3147366648 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 27499157887 ps |
| CPU time | 140.89 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:28:49 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-4f18ef15-22fc-4bd9-8f66-4014e64608bb |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147366648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.3147366648 |
| Directory | /workspace/37.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.1423659245 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 62914508449 ps |
| CPU time | 322.89 seconds |
| Started | Mar 05 01:26:20 PM PST 24 |
| Finished | Mar 05 01:31:43 PM PST 24 |
| Peak memory | 335444 kb |
| Host | smart-34aac853-791f-47a1-ba60-52eb78c22644 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423659245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.1423659245 |
| Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.2247443189 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1069391286 ps |
| CPU time | 15.57 seconds |
| Started | Mar 05 01:26:20 PM PST 24 |
| Finished | Mar 05 01:26:36 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-db818615-0b99-400b-b34b-135ac1cf9202 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247443189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.2247443189 |
| Directory | /workspace/37.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3191814786 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 73528085340 ps |
| CPU time | 426.85 seconds |
| Started | Mar 05 01:26:25 PM PST 24 |
| Finished | Mar 05 01:33:32 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-d892cf65-728d-470e-a0a8-d18d57a76f33 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191814786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.3191814786 |
| Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.3773075803 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 349106554 ps |
| CPU time | 3.13 seconds |
| Started | Mar 05 01:26:26 PM PST 24 |
| Finished | Mar 05 01:26:30 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-4ccdeaa9-a716-45e3-9b45-e7e2f412212d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773075803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3773075803 |
| Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_regwen.1606278814 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 111004039639 ps |
| CPU time | 987.51 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:42:56 PM PST 24 |
| Peak memory | 366436 kb |
| Host | smart-475794fc-1c2d-471e-945e-3f4b60ca57e7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606278814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1606278814 |
| Directory | /workspace/37.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_smoke.1828390862 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 869769727 ps |
| CPU time | 13.29 seconds |
| Started | Mar 05 01:26:23 PM PST 24 |
| Finished | Mar 05 01:26:36 PM PST 24 |
| Peak memory | 238904 kb |
| Host | smart-3a8e1f10-2a18-4d1c-8061-c96c14710767 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828390862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1828390862 |
| Directory | /workspace/37.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1832280524 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 584904468 ps |
| CPU time | 9.46 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:26:38 PM PST 24 |
| Peak memory | 210956 kb |
| Host | smart-75239a9c-d29f-42cf-b575-5d8c6a235da2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1832280524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1832280524 |
| Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2035572825 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 22345412246 ps |
| CPU time | 326.42 seconds |
| Started | Mar 05 01:26:18 PM PST 24 |
| Finished | Mar 05 01:31:45 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-724a870a-6f50-41de-b505-38daa5ca66a5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035572825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.2035572825 |
| Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2383825171 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 3053320001 ps |
| CPU time | 95.43 seconds |
| Started | Mar 05 01:26:28 PM PST 24 |
| Finished | Mar 05 01:28:05 PM PST 24 |
| Peak memory | 336308 kb |
| Host | smart-a0e665fc-2282-49d2-847e-f54dcd2eb154 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383825171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.2383825171 |
| Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.2672237523 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 11747669 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:26:29 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-50094559-aaa9-4bb8-8e1c-af76f6c2b2e5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672237523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.2672237523 |
| Directory | /workspace/38.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_bijection.4139523504 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 72612809173 ps |
| CPU time | 1334.78 seconds |
| Started | Mar 05 01:26:28 PM PST 24 |
| Finished | Mar 05 01:48:44 PM PST 24 |
| Peak memory | 202880 kb |
| Host | smart-0c07ef81-7a84-4315-9726-29e1c31c005b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139523504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .4139523504 |
| Directory | /workspace/38.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_executable.4092120608 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 5807154355 ps |
| CPU time | 336.11 seconds |
| Started | Mar 05 01:26:25 PM PST 24 |
| Finished | Mar 05 01:32:02 PM PST 24 |
| Peak memory | 352052 kb |
| Host | smart-71abd9e6-346c-46c6-b134-010c27865a4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092120608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.4092120608 |
| Directory | /workspace/38.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.3294080568 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 1280066849 ps |
| CPU time | 13.95 seconds |
| Started | Mar 05 01:26:26 PM PST 24 |
| Finished | Mar 05 01:26:42 PM PST 24 |
| Peak memory | 239856 kb |
| Host | smart-debfcb0c-f175-42af-b9b8-fda663ff857c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294080568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.3294080568 |
| Directory | /workspace/38.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.131081691 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 947651248 ps |
| CPU time | 67.53 seconds |
| Started | Mar 05 01:26:26 PM PST 24 |
| Finished | Mar 05 01:27:35 PM PST 24 |
| Peak memory | 210940 kb |
| Host | smart-e12b73e6-3f67-49bc-8619-86ed1796ff29 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131081691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_mem_partial_access.131081691 |
| Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.1354975326 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 43046394459 ps |
| CPU time | 151.56 seconds |
| Started | Mar 05 01:26:30 PM PST 24 |
| Finished | Mar 05 01:29:02 PM PST 24 |
| Peak memory | 202852 kb |
| Host | smart-a1f23585-83ee-4b4d-b373-980ed98bef5a |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354975326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.1354975326 |
| Directory | /workspace/38.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.698936253 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 16259708924 ps |
| CPU time | 484.75 seconds |
| Started | Mar 05 01:26:32 PM PST 24 |
| Finished | Mar 05 01:34:37 PM PST 24 |
| Peak memory | 370384 kb |
| Host | smart-aedcf42e-0d95-4f74-88be-b324aa3850a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698936253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip le_keys.698936253 |
| Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.3942855602 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 5994103732 ps |
| CPU time | 26.8 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:26:55 PM PST 24 |
| Peak memory | 264084 kb |
| Host | smart-b02264b7-327e-4a99-98f3-ca48cfd6fc01 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942855602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.3942855602 |
| Directory | /workspace/38.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4271525540 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 72667020890 ps |
| CPU time | 368.79 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:32:37 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-e1dfbac2-75c9-4ca3-91e6-ec3fa3e6bf85 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271525540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.4271525540 |
| Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.3927467585 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 998721894 ps |
| CPU time | 3.25 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:26:32 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-9f21e006-263f-4915-890c-20da0e55b5ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927467585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3927467585 |
| Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_regwen.102525988 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4551658821 ps |
| CPU time | 219.02 seconds |
| Started | Mar 05 01:26:28 PM PST 24 |
| Finished | Mar 05 01:30:09 PM PST 24 |
| Peak memory | 379632 kb |
| Host | smart-7a48974a-f86b-4190-9908-f2d0c053e0fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102525988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.102525988 |
| Directory | /workspace/38.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_smoke.1955150545 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1023135891 ps |
| CPU time | 11.46 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:26:40 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-e917e53d-ee05-4865-b94c-81ea9b4eee53 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955150545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1955150545 |
| Directory | /workspace/38.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.67666522 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 41058892868 ps |
| CPU time | 1736.76 seconds |
| Started | Mar 05 01:26:28 PM PST 24 |
| Finished | Mar 05 01:55:27 PM PST 24 |
| Peak memory | 379668 kb |
| Host | smart-fe42ccbc-c2cf-49c9-83cb-31b497481504 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67666522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.sram_ctrl_stress_all.67666522 |
| Directory | /workspace/38.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1223775611 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 590890984 ps |
| CPU time | 13.96 seconds |
| Started | Mar 05 01:26:29 PM PST 24 |
| Finished | Mar 05 01:26:44 PM PST 24 |
| Peak memory | 210992 kb |
| Host | smart-7e2dc8ce-54f3-4491-a250-a33072c6c07b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1223775611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1223775611 |
| Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3102206567 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 6906981403 ps |
| CPU time | 413.83 seconds |
| Started | Mar 05 01:26:30 PM PST 24 |
| Finished | Mar 05 01:33:24 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-8bf1e763-85ff-4f52-81d7-47644c1f84fa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102206567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.3102206567 |
| Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2247901984 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 736883407 ps |
| CPU time | 5.87 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:26:34 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-aa15bc0c-b05f-47ea-abf5-1ae70cf51a0c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247901984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2247901984 |
| Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.3773992099 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 12194727 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 01:26:38 PM PST 24 |
| Finished | Mar 05 01:26:39 PM PST 24 |
| Peak memory | 202144 kb |
| Host | smart-6c482d2a-3010-487a-88ff-615d7fb8a4b6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773992099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3773992099 |
| Directory | /workspace/39.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_bijection.3359302869 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 221416986079 ps |
| CPU time | 1002.66 seconds |
| Started | Mar 05 01:26:26 PM PST 24 |
| Finished | Mar 05 01:43:09 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-99f7d36c-c7ca-46d6-acb3-c626c3f6ca51 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359302869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .3359302869 |
| Directory | /workspace/39.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_executable.961620120 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 22206171278 ps |
| CPU time | 796.53 seconds |
| Started | Mar 05 01:26:38 PM PST 24 |
| Finished | Mar 05 01:39:54 PM PST 24 |
| Peak memory | 365388 kb |
| Host | smart-b5ebb8f6-dd46-4889-be7d-623f9000f4b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961620120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executabl e.961620120 |
| Directory | /workspace/39.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.4192434654 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1589876782 ps |
| CPU time | 14.84 seconds |
| Started | Mar 05 01:26:29 PM PST 24 |
| Finished | Mar 05 01:26:45 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-223e020a-9d21-474c-b3f6-e9f4c95b7361 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192434654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.4192434654 |
| Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.2374844874 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 693052960 ps |
| CPU time | 7.52 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:26:37 PM PST 24 |
| Peak memory | 218788 kb |
| Host | smart-b6ad2d39-3cf3-450f-be0d-e9abca5c71bc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374844874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.2374844874 |
| Directory | /workspace/39.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2429709495 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2359595894 ps |
| CPU time | 73.77 seconds |
| Started | Mar 05 01:26:38 PM PST 24 |
| Finished | Mar 05 01:27:52 PM PST 24 |
| Peak memory | 210700 kb |
| Host | smart-537db2e2-8c46-49e1-a7e0-d228ceab98d4 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429709495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.2429709495 |
| Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.2770598312 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 57350816842 ps |
| CPU time | 294.04 seconds |
| Started | Mar 05 01:26:35 PM PST 24 |
| Finished | Mar 05 01:31:29 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-cf09d490-3277-4746-87e5-b2e96260c35f |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770598312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.2770598312 |
| Directory | /workspace/39.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.3213254840 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 13226098407 ps |
| CPU time | 781.83 seconds |
| Started | Mar 05 01:26:31 PM PST 24 |
| Finished | Mar 05 01:39:33 PM PST 24 |
| Peak memory | 376600 kb |
| Host | smart-0be29f02-a0e1-47b6-8756-96abb565d82f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213254840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.3213254840 |
| Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.3375395751 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 386563967 ps |
| CPU time | 3.82 seconds |
| Started | Mar 05 01:26:30 PM PST 24 |
| Finished | Mar 05 01:26:35 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-2c2232ef-57d8-4f20-a542-5efe7c766b56 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375395751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.3375395751 |
| Directory | /workspace/39.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.1403641830 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 5612777867 ps |
| CPU time | 3.22 seconds |
| Started | Mar 05 01:26:35 PM PST 24 |
| Finished | Mar 05 01:26:39 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-b3f03a32-8778-4213-bcf1-0e71ba1450fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403641830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1403641830 |
| Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_regwen.4024071467 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 11742833592 ps |
| CPU time | 1201.5 seconds |
| Started | Mar 05 01:26:35 PM PST 24 |
| Finished | Mar 05 01:46:37 PM PST 24 |
| Peak memory | 369460 kb |
| Host | smart-98951562-5248-49b1-86f8-762b52a6d200 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024071467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.4024071467 |
| Directory | /workspace/39.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_smoke.3445910972 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 877171055 ps |
| CPU time | 19.69 seconds |
| Started | Mar 05 01:26:27 PM PST 24 |
| Finished | Mar 05 01:26:48 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-74d15bdc-bf5f-4931-abdf-05c3e36a2034 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445910972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3445910972 |
| Directory | /workspace/39.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.3115274863 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 89714130125 ps |
| CPU time | 2353.83 seconds |
| Started | Mar 05 01:26:36 PM PST 24 |
| Finished | Mar 05 02:05:50 PM PST 24 |
| Peak memory | 371644 kb |
| Host | smart-e7d58100-9bbf-4690-8089-783d84038000 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115274863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.3115274863 |
| Directory | /workspace/39.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2338495854 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1249699913 ps |
| CPU time | 71.79 seconds |
| Started | Mar 05 01:26:36 PM PST 24 |
| Finished | Mar 05 01:27:47 PM PST 24 |
| Peak memory | 301932 kb |
| Host | smart-c1782e70-d54a-49a7-9251-085f3ce4a2a0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2338495854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2338495854 |
| Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1414387990 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 34612849307 ps |
| CPU time | 379.71 seconds |
| Started | Mar 05 01:26:28 PM PST 24 |
| Finished | Mar 05 01:32:49 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-6fc9b64e-1140-43d0-ae35-dff307d91387 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414387990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1414387990 |
| Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3465844288 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 824307380 ps |
| CPU time | 110.47 seconds |
| Started | Mar 05 01:26:32 PM PST 24 |
| Finished | Mar 05 01:28:23 PM PST 24 |
| Peak memory | 363168 kb |
| Host | smart-0aa96a2e-1e57-4544-8bcd-b207fe5022c0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465844288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3465844288 |
| Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.3051015229 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 44206389 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:24:25 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-1497b5aa-a91f-41c1-8cb1-28c3db464209 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051015229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.3051015229 |
| Directory | /workspace/4.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_bijection.4193895903 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 115871152068 ps |
| CPU time | 766.59 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 01:37:12 PM PST 24 |
| Peak memory | 202832 kb |
| Host | smart-328227a4-1299-4caa-89f2-d29cb98014c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193895903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 4193895903 |
| Directory | /workspace/4.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_executable.2897689080 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 151604785435 ps |
| CPU time | 884.99 seconds |
| Started | Mar 05 01:24:29 PM PST 24 |
| Finished | Mar 05 01:39:14 PM PST 24 |
| Peak memory | 368516 kb |
| Host | smart-ce35a7fd-ec84-4524-bee8-67773846581b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897689080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.2897689080 |
| Directory | /workspace/4.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.2490978003 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 763435327 ps |
| CPU time | 139.41 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:27:01 PM PST 24 |
| Peak memory | 360024 kb |
| Host | smart-e837229e-b57a-49be-9652-82b6ff5ca29f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490978003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.2490978003 |
| Directory | /workspace/4.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.748418240 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4420981098 ps |
| CPU time | 160.65 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:27:09 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-1137b1ee-9260-4b86-9889-8fe64101f24f |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748418240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. sram_ctrl_mem_partial_access.748418240 |
| Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.2364152634 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3951607350 ps |
| CPU time | 120.54 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 01:26:24 PM PST 24 |
| Peak memory | 202840 kb |
| Host | smart-47df7b9f-9414-49b8-9a3f-c57be1b5b47d |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364152634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.2364152634 |
| Directory | /workspace/4.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.125659581 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 33882950394 ps |
| CPU time | 856.41 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:38:44 PM PST 24 |
| Peak memory | 371388 kb |
| Host | smart-cdecca48-7811-4701-8a54-ee1cd2af7e66 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125659581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl e_keys.125659581 |
| Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.3675891055 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3934050214 ps |
| CPU time | 19.77 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 01:24:45 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-a675ee3c-3645-4746-9615-ee4248912ab6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675891055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.3675891055 |
| Directory | /workspace/4.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3368357082 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 46582888988 ps |
| CPU time | 363.94 seconds |
| Started | Mar 05 01:24:29 PM PST 24 |
| Finished | Mar 05 01:30:34 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-8999ac90-b469-4182-86ec-3ab2d5584bd5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368357082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.3368357082 |
| Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.536326295 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1411653404 ps |
| CPU time | 3.71 seconds |
| Started | Mar 05 01:24:44 PM PST 24 |
| Finished | Mar 05 01:24:48 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-910e3f6f-95c4-4b96-bebe-7ed4151fe151 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536326295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.536326295 |
| Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_regwen.3244089278 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 13195930928 ps |
| CPU time | 936.97 seconds |
| Started | Mar 05 01:24:34 PM PST 24 |
| Finished | Mar 05 01:40:12 PM PST 24 |
| Peak memory | 378660 kb |
| Host | smart-2d7ff5bc-0fc5-49a3-9b9b-d5550cb4a6bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244089278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3244089278 |
| Directory | /workspace/4.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.3719809750 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 456941704 ps |
| CPU time | 3.25 seconds |
| Started | Mar 05 01:24:30 PM PST 24 |
| Finished | Mar 05 01:24:33 PM PST 24 |
| Peak memory | 221580 kb |
| Host | smart-fff30646-7203-4214-8779-1818777b232c |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719809750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.3719809750 |
| Directory | /workspace/4.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2320624428 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2614575180 ps |
| CPU time | 23.12 seconds |
| Started | Mar 05 01:24:37 PM PST 24 |
| Finished | Mar 05 01:25:00 PM PST 24 |
| Peak memory | 211008 kb |
| Host | smart-d7019a31-1511-4ec5-abf7-cfde5fa546fd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2320624428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2320624428 |
| Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3936563601 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 23460429411 ps |
| CPU time | 372.06 seconds |
| Started | Mar 05 01:24:34 PM PST 24 |
| Finished | Mar 05 01:30:46 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-326a50e0-d2cc-4143-b60d-51c6ddccff0d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936563601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.3936563601 |
| Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.4096906056 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1398900540 ps |
| CPU time | 53.32 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 01:25:19 PM PST 24 |
| Peak memory | 306900 kb |
| Host | smart-75eb722c-45d0-4bb4-a63e-2809ca17a4ee |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096906056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.4096906056 |
| Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.2983692323 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 20965419 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 01:26:44 PM PST 24 |
| Finished | Mar 05 01:26:45 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-dd092ef7-c24f-4485-83a9-00b88af0be99 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983692323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.2983692323 |
| Directory | /workspace/40.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_bijection.2434691794 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 28052129887 ps |
| CPU time | 1732.11 seconds |
| Started | Mar 05 01:26:34 PM PST 24 |
| Finished | Mar 05 01:55:27 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-63bc50b9-39d4-4cd3-961d-441cdf801c4b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434691794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .2434691794 |
| Directory | /workspace/40.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_executable.2951767482 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 37899057323 ps |
| CPU time | 932.2 seconds |
| Started | Mar 05 01:26:43 PM PST 24 |
| Finished | Mar 05 01:42:16 PM PST 24 |
| Peak memory | 377324 kb |
| Host | smart-4adf3c87-692c-498e-912e-ca5d8d418e47 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951767482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.2951767482 |
| Directory | /workspace/40.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.94092149 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 12350456562 ps |
| CPU time | 186.7 seconds |
| Started | Mar 05 01:26:45 PM PST 24 |
| Finished | Mar 05 01:29:53 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-5194b514-3b80-4eca-ab12-24ce69e8a2f2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94092149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esca lation.94092149 |
| Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.1151777343 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2991774511 ps |
| CPU time | 99.04 seconds |
| Started | Mar 05 01:26:42 PM PST 24 |
| Finished | Mar 05 01:28:21 PM PST 24 |
| Peak memory | 340816 kb |
| Host | smart-b686f89a-99f1-45fd-a0c9-a98754ae07dc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151777343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.1151777343 |
| Directory | /workspace/40.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3216354293 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 4899762841 ps |
| CPU time | 75.72 seconds |
| Started | Mar 05 01:26:46 PM PST 24 |
| Finished | Mar 05 01:28:02 PM PST 24 |
| Peak memory | 211028 kb |
| Host | smart-e75b9a56-e441-4abb-8376-a9bfec61cafd |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216354293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.3216354293 |
| Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.615114517 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 36495787595 ps |
| CPU time | 310.15 seconds |
| Started | Mar 05 01:26:44 PM PST 24 |
| Finished | Mar 05 01:31:54 PM PST 24 |
| Peak memory | 202884 kb |
| Host | smart-c62040bd-59fd-4f30-9a4f-13b3e283ab03 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615114517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl _mem_walk.615114517 |
| Directory | /workspace/40.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.1445251684 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 4452159131 ps |
| CPU time | 370.63 seconds |
| Started | Mar 05 01:26:38 PM PST 24 |
| Finished | Mar 05 01:32:49 PM PST 24 |
| Peak memory | 341656 kb |
| Host | smart-82f31afa-dfa1-4158-aaec-17a8e760a9e7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445251684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.1445251684 |
| Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.2441264882 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2256871453 ps |
| CPU time | 18.95 seconds |
| Started | Mar 05 01:26:35 PM PST 24 |
| Finished | Mar 05 01:26:54 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-b7a021f3-bb2d-4c5e-b20c-ddcdd0d4344b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441264882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.2441264882 |
| Directory | /workspace/40.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3537753223 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4534676106 ps |
| CPU time | 224.16 seconds |
| Started | Mar 05 01:26:43 PM PST 24 |
| Finished | Mar 05 01:30:28 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-55573442-581c-4f0d-a75b-38409ef8ce46 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537753223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.3537753223 |
| Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.2290167909 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1341593719 ps |
| CPU time | 3.13 seconds |
| Started | Mar 05 01:26:48 PM PST 24 |
| Finished | Mar 05 01:26:51 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-25472169-2384-4143-ab4d-4d94fed03fba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290167909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2290167909 |
| Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_regwen.4193836348 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 45762679391 ps |
| CPU time | 1431.98 seconds |
| Started | Mar 05 01:26:44 PM PST 24 |
| Finished | Mar 05 01:50:36 PM PST 24 |
| Peak memory | 381740 kb |
| Host | smart-ab795241-4c45-4417-bc04-bd0454783cc4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193836348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.4193836348 |
| Directory | /workspace/40.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_smoke.2845316768 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1696851161 ps |
| CPU time | 12.75 seconds |
| Started | Mar 05 01:26:32 PM PST 24 |
| Finished | Mar 05 01:26:45 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-03005488-b916-4fe0-9e80-e9a6b6426e7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845316768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2845316768 |
| Directory | /workspace/40.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.273759000 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 64230957669 ps |
| CPU time | 3583.63 seconds |
| Started | Mar 05 01:26:46 PM PST 24 |
| Finished | Mar 05 02:26:30 PM PST 24 |
| Peak memory | 380676 kb |
| Host | smart-42556ca3-6724-4bbb-bec3-07181302cc2d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273759000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_stress_all.273759000 |
| Directory | /workspace/40.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.697152367 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 7268574329 ps |
| CPU time | 44.33 seconds |
| Started | Mar 05 01:26:42 PM PST 24 |
| Finished | Mar 05 01:27:26 PM PST 24 |
| Peak memory | 212972 kb |
| Host | smart-2c3dbbd7-98e7-4a4c-99a5-a255c05bba65 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=697152367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.697152367 |
| Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3669886830 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 6780553224 ps |
| CPU time | 205.57 seconds |
| Started | Mar 05 01:26:39 PM PST 24 |
| Finished | Mar 05 01:30:04 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-f9c4c1af-b4e6-41dd-ac6e-9e0bdad17792 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669886830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.3669886830 |
| Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2679294321 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 2511384895 ps |
| CPU time | 7.36 seconds |
| Started | Mar 05 01:26:42 PM PST 24 |
| Finished | Mar 05 01:26:50 PM PST 24 |
| Peak memory | 219160 kb |
| Host | smart-a9961fe0-6c4d-43f7-8fe3-c2cbea381ca0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679294321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.2679294321 |
| Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.1373972088 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 39760551 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:26:50 PM PST 24 |
| Finished | Mar 05 01:26:51 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-6885e597-3490-44ea-9af9-a33798f55a33 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373972088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.1373972088 |
| Directory | /workspace/41.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_bijection.885636530 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 63072688852 ps |
| CPU time | 1122.32 seconds |
| Started | Mar 05 01:26:44 PM PST 24 |
| Finished | Mar 05 01:45:27 PM PST 24 |
| Peak memory | 203088 kb |
| Host | smart-139b8b7c-6b98-4595-9426-63227cbd241b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885636530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection. 885636530 |
| Directory | /workspace/41.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_executable.2823459975 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 8362796664 ps |
| CPU time | 1047.35 seconds |
| Started | Mar 05 01:26:55 PM PST 24 |
| Finished | Mar 05 01:44:23 PM PST 24 |
| Peak memory | 378464 kb |
| Host | smart-492b6bed-c754-4357-a638-bb4d35ce87d6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823459975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.2823459975 |
| Directory | /workspace/41.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.3144960093 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1439514940 ps |
| CPU time | 21.82 seconds |
| Started | Mar 05 01:26:43 PM PST 24 |
| Finished | Mar 05 01:27:05 PM PST 24 |
| Peak memory | 261200 kb |
| Host | smart-0abf4e98-7545-466a-ac5c-0196969f6ab0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144960093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.3144960093 |
| Directory | /workspace/41.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3246993476 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4707652858 ps |
| CPU time | 144.46 seconds |
| Started | Mar 05 01:26:50 PM PST 24 |
| Finished | Mar 05 01:29:15 PM PST 24 |
| Peak memory | 210952 kb |
| Host | smart-86623b60-d162-47c3-a023-bd2ca14ef731 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246993476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.3246993476 |
| Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.2369719209 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 21066273047 ps |
| CPU time | 154 seconds |
| Started | Mar 05 01:26:49 PM PST 24 |
| Finished | Mar 05 01:29:23 PM PST 24 |
| Peak memory | 202884 kb |
| Host | smart-54f7a60d-b983-4999-beb3-d204e7b3d276 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369719209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.2369719209 |
| Directory | /workspace/41.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.3504642641 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3511259554 ps |
| CPU time | 144.32 seconds |
| Started | Mar 05 01:26:44 PM PST 24 |
| Finished | Mar 05 01:29:08 PM PST 24 |
| Peak memory | 319276 kb |
| Host | smart-5779ec89-a16c-4f42-bb2f-42e48fb677d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504642641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.3504642641 |
| Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.1894144503 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5470604082 ps |
| CPU time | 19.09 seconds |
| Started | Mar 05 01:26:46 PM PST 24 |
| Finished | Mar 05 01:27:06 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-ef0ddfe7-e1ed-44d6-a721-dab48eac67a2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894144503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.1894144503 |
| Directory | /workspace/41.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.289276876 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 15627811898 ps |
| CPU time | 341.54 seconds |
| Started | Mar 05 01:26:43 PM PST 24 |
| Finished | Mar 05 01:32:25 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-34314fcf-60ba-495f-a019-c0ac71cc6c00 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289276876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.sram_ctrl_partial_access_b2b.289276876 |
| Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.890702969 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 734484764 ps |
| CPU time | 3.29 seconds |
| Started | Mar 05 01:26:59 PM PST 24 |
| Finished | Mar 05 01:27:04 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-0541c85e-27f7-440c-a251-8ddb17a91836 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890702969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.890702969 |
| Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_regwen.2171404789 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 14267140864 ps |
| CPU time | 459.24 seconds |
| Started | Mar 05 01:26:48 PM PST 24 |
| Finished | Mar 05 01:34:28 PM PST 24 |
| Peak memory | 373184 kb |
| Host | smart-78726395-4f44-454b-9546-b7f19916031c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171404789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2171404789 |
| Directory | /workspace/41.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_smoke.3436522325 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1222880599 ps |
| CPU time | 15.14 seconds |
| Started | Mar 05 01:26:44 PM PST 24 |
| Finished | Mar 05 01:27:00 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-b28bcbf7-0e1a-418e-becf-53a9e19aa589 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436522325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3436522325 |
| Directory | /workspace/41.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.1945514778 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 94294149755 ps |
| CPU time | 4934.91 seconds |
| Started | Mar 05 01:26:52 PM PST 24 |
| Finished | Mar 05 02:49:09 PM PST 24 |
| Peak memory | 380560 kb |
| Host | smart-875fe1e9-6176-41b6-a6f3-8dfc661ccea4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945514778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.1945514778 |
| Directory | /workspace/41.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.801795325 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4655799452 ps |
| CPU time | 35.11 seconds |
| Started | Mar 05 01:26:51 PM PST 24 |
| Finished | Mar 05 01:27:27 PM PST 24 |
| Peak memory | 211016 kb |
| Host | smart-43d288f1-2b55-444c-99ea-c2d68c20786c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=801795325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.801795325 |
| Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.1465412185 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 10093082271 ps |
| CPU time | 206.42 seconds |
| Started | Mar 05 01:26:44 PM PST 24 |
| Finished | Mar 05 01:30:10 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-8a0251ad-5fa7-4654-8567-1e8e0e28ba7e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465412185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.1465412185 |
| Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3913839724 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3083265983 ps |
| CPU time | 43.02 seconds |
| Started | Mar 05 01:26:44 PM PST 24 |
| Finished | Mar 05 01:27:28 PM PST 24 |
| Peak memory | 301948 kb |
| Host | smart-17fed37f-7565-49e9-ba44-08152dbd8152 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913839724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3913839724 |
| Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.591258839 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 13910669 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 01:26:58 PM PST 24 |
| Finished | Mar 05 01:27:00 PM PST 24 |
| Peak memory | 202180 kb |
| Host | smart-b4e198c7-f7f0-4784-998b-796f64d96571 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591258839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.591258839 |
| Directory | /workspace/42.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_bijection.4223185310 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 184405599636 ps |
| CPU time | 1066.55 seconds |
| Started | Mar 05 01:26:55 PM PST 24 |
| Finished | Mar 05 01:44:42 PM PST 24 |
| Peak memory | 202840 kb |
| Host | smart-4600fae6-ed61-4e45-ab92-2827b24e44b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223185310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .4223185310 |
| Directory | /workspace/42.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_executable.2905560152 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 25822307375 ps |
| CPU time | 1065.43 seconds |
| Started | Mar 05 01:26:58 PM PST 24 |
| Finished | Mar 05 01:44:44 PM PST 24 |
| Peak memory | 377612 kb |
| Host | smart-0df9ff8b-dea2-4037-9154-095c1add2c4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905560152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.2905560152 |
| Directory | /workspace/42.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.2785278111 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 9067734667 ps |
| CPU time | 161.49 seconds |
| Started | Mar 05 01:26:47 PM PST 24 |
| Finished | Mar 05 01:29:29 PM PST 24 |
| Peak memory | 210972 kb |
| Host | smart-e72d8ff6-7577-44eb-be9e-8926c40497c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785278111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.2785278111 |
| Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.1959736419 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2829815600 ps |
| CPU time | 26.68 seconds |
| Started | Mar 05 01:26:50 PM PST 24 |
| Finished | Mar 05 01:27:18 PM PST 24 |
| Peak memory | 273208 kb |
| Host | smart-5cc22cb1-ad1f-4423-b556-035207f21121 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959736419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.1959736419 |
| Directory | /workspace/42.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.955174317 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1602287753 ps |
| CPU time | 129.46 seconds |
| Started | Mar 05 01:27:00 PM PST 24 |
| Finished | Mar 05 01:29:10 PM PST 24 |
| Peak memory | 210848 kb |
| Host | smart-8ab43494-0a63-48fc-9ef8-92ad72e9c17e |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955174317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_mem_partial_access.955174317 |
| Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.3497250488 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 57380358481 ps |
| CPU time | 294.45 seconds |
| Started | Mar 05 01:26:57 PM PST 24 |
| Finished | Mar 05 01:31:53 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-c53a4fdf-9abc-461c-8251-36448937be27 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497250488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.3497250488 |
| Directory | /workspace/42.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.2943884039 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 51452952309 ps |
| CPU time | 888.98 seconds |
| Started | Mar 05 01:26:53 PM PST 24 |
| Finished | Mar 05 01:41:42 PM PST 24 |
| Peak memory | 380696 kb |
| Host | smart-71ea8129-d013-4281-890a-e77ffb06850f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943884039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.2943884039 |
| Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.3041567979 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 10748178309 ps |
| CPU time | 150.65 seconds |
| Started | Mar 05 01:26:54 PM PST 24 |
| Finished | Mar 05 01:29:26 PM PST 24 |
| Peak memory | 368148 kb |
| Host | smart-a227ae5b-950b-46a0-8c1c-f74a374733b7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041567979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.3041567979 |
| Directory | /workspace/42.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1660202583 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 128320280853 ps |
| CPU time | 479.22 seconds |
| Started | Mar 05 01:26:50 PM PST 24 |
| Finished | Mar 05 01:34:50 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-060c628d-c451-4fd9-aa7d-c76f430e9a4b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660202583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.1660202583 |
| Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.407184680 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1779893032 ps |
| CPU time | 3.03 seconds |
| Started | Mar 05 01:26:58 PM PST 24 |
| Finished | Mar 05 01:27:02 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-ced452e2-c41a-4207-9665-2774f845cbe4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407184680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.407184680 |
| Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_regwen.208398404 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3110880516 ps |
| CPU time | 776.92 seconds |
| Started | Mar 05 01:27:00 PM PST 24 |
| Finished | Mar 05 01:39:58 PM PST 24 |
| Peak memory | 375480 kb |
| Host | smart-d533ee85-8e54-4852-8bec-55db4a19cb9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208398404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.208398404 |
| Directory | /workspace/42.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_smoke.2959115587 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5690639194 ps |
| CPU time | 45.93 seconds |
| Started | Mar 05 01:26:54 PM PST 24 |
| Finished | Mar 05 01:27:41 PM PST 24 |
| Peak memory | 296756 kb |
| Host | smart-23de4170-d8dc-49c1-b02b-eb8d4519b40f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959115587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2959115587 |
| Directory | /workspace/42.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4225118466 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1071390786 ps |
| CPU time | 9.99 seconds |
| Started | Mar 05 01:26:59 PM PST 24 |
| Finished | Mar 05 01:27:10 PM PST 24 |
| Peak memory | 210944 kb |
| Host | smart-ccea37fe-4579-4f35-9f4b-204a26d45c09 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4225118466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.4225118466 |
| Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.176269585 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 6296551519 ps |
| CPU time | 340.33 seconds |
| Started | Mar 05 01:26:55 PM PST 24 |
| Finished | Mar 05 01:32:36 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-b99aea33-12df-4a78-ba44-ee74f00f3c42 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176269585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_stress_pipeline.176269585 |
| Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2800128646 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2983363098 ps |
| CPU time | 85.36 seconds |
| Started | Mar 05 01:26:49 PM PST 24 |
| Finished | Mar 05 01:28:14 PM PST 24 |
| Peak memory | 315388 kb |
| Host | smart-4e01537a-2711-4748-99f6-39e528008c96 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800128646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2800128646 |
| Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.2980256443 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 16572883 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:27:06 PM PST 24 |
| Finished | Mar 05 01:27:07 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-9c9c8717-b558-41b2-881f-63062cc27cd9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980256443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2980256443 |
| Directory | /workspace/43.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_bijection.53792838 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 207451632201 ps |
| CPU time | 2367.33 seconds |
| Started | Mar 05 01:26:58 PM PST 24 |
| Finished | Mar 05 02:06:27 PM PST 24 |
| Peak memory | 202880 kb |
| Host | smart-3187e19a-966c-488d-bc48-bae374cc983c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53792838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.53792838 |
| Directory | /workspace/43.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_executable.3316935396 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 76709525100 ps |
| CPU time | 536.81 seconds |
| Started | Mar 05 01:27:10 PM PST 24 |
| Finished | Mar 05 01:36:07 PM PST 24 |
| Peak memory | 371452 kb |
| Host | smart-c7ba9d56-94d6-4e0e-9eff-4ddbacbdf52a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316935396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.3316935396 |
| Directory | /workspace/43.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.746212228 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 5759680909 ps |
| CPU time | 86.16 seconds |
| Started | Mar 05 01:27:07 PM PST 24 |
| Finished | Mar 05 01:28:33 PM PST 24 |
| Peak memory | 210952 kb |
| Host | smart-e01b29cb-2e32-4473-a32b-0e3815a68ba6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746212228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_esc alation.746212228 |
| Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.1184321869 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2761196475 ps |
| CPU time | 14.95 seconds |
| Started | Mar 05 01:27:07 PM PST 24 |
| Finished | Mar 05 01:27:22 PM PST 24 |
| Peak memory | 243852 kb |
| Host | smart-9e56221b-67f3-4ba9-856a-4f3bfb885930 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184321869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.1184321869 |
| Directory | /workspace/43.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.1530809916 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4327509442 ps |
| CPU time | 63.65 seconds |
| Started | Mar 05 01:27:06 PM PST 24 |
| Finished | Mar 05 01:28:09 PM PST 24 |
| Peak memory | 211012 kb |
| Host | smart-7870f110-014d-4c50-a4cb-3f09be3e7336 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530809916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.1530809916 |
| Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.4073564976 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 12340256114 ps |
| CPU time | 125.63 seconds |
| Started | Mar 05 01:27:09 PM PST 24 |
| Finished | Mar 05 01:29:15 PM PST 24 |
| Peak memory | 202880 kb |
| Host | smart-b987c522-558c-4ba4-a7b6-398e7c892eb7 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073564976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.4073564976 |
| Directory | /workspace/43.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.1782811667 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 85342213126 ps |
| CPU time | 1504.69 seconds |
| Started | Mar 05 01:26:59 PM PST 24 |
| Finished | Mar 05 01:52:05 PM PST 24 |
| Peak memory | 378616 kb |
| Host | smart-e5c0cedf-33d8-487b-8f40-918b7757cd1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782811667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.1782811667 |
| Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.1105005503 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 895626610 ps |
| CPU time | 8.68 seconds |
| Started | Mar 05 01:26:58 PM PST 24 |
| Finished | Mar 05 01:27:07 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-f6f978af-bcce-4037-9305-f492f0199b95 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105005503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.1105005503 |
| Directory | /workspace/43.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4011213101 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 64597281478 ps |
| CPU time | 391.62 seconds |
| Started | Mar 05 01:26:59 PM PST 24 |
| Finished | Mar 05 01:33:32 PM PST 24 |
| Peak memory | 202808 kb |
| Host | smart-5629d22d-c145-456d-a221-ceebed6c3fbb |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011213101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.4011213101 |
| Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.96480254 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 4200308725 ps |
| CPU time | 4.51 seconds |
| Started | Mar 05 01:27:06 PM PST 24 |
| Finished | Mar 05 01:27:11 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-f5debd8a-0939-4eda-a2e7-53fa1bf13977 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96480254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.96480254 |
| Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_regwen.3934867026 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 24122642634 ps |
| CPU time | 1527.44 seconds |
| Started | Mar 05 01:27:07 PM PST 24 |
| Finished | Mar 05 01:52:34 PM PST 24 |
| Peak memory | 381740 kb |
| Host | smart-f5ac9727-8989-4583-8624-5399ded4ee20 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934867026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3934867026 |
| Directory | /workspace/43.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_smoke.1889872215 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1821395167 ps |
| CPU time | 20.11 seconds |
| Started | Mar 05 01:26:58 PM PST 24 |
| Finished | Mar 05 01:27:18 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-13245ce4-1c73-4ff8-820f-f0ae1aa6081f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889872215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1889872215 |
| Directory | /workspace/43.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.1792133900 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 355454974296 ps |
| CPU time | 4473.59 seconds |
| Started | Mar 05 01:27:09 PM PST 24 |
| Finished | Mar 05 02:41:43 PM PST 24 |
| Peak memory | 381712 kb |
| Host | smart-9657772e-fe4e-4415-a449-1b6d20ca3097 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792133900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.1792133900 |
| Directory | /workspace/43.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3933661368 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 5735345443 ps |
| CPU time | 76.56 seconds |
| Started | Mar 05 01:27:07 PM PST 24 |
| Finished | Mar 05 01:28:23 PM PST 24 |
| Peak memory | 219044 kb |
| Host | smart-459659ff-f1fe-4dbd-b3b8-e3027419a3d5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3933661368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3933661368 |
| Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.134206039 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 9338554260 ps |
| CPU time | 302.73 seconds |
| Started | Mar 05 01:26:59 PM PST 24 |
| Finished | Mar 05 01:32:03 PM PST 24 |
| Peak memory | 202812 kb |
| Host | smart-30cf03b2-428d-4ef2-916f-578902bd4366 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134206039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43 .sram_ctrl_stress_pipeline.134206039 |
| Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1662296074 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 1533862048 ps |
| CPU time | 57.86 seconds |
| Started | Mar 05 01:27:06 PM PST 24 |
| Finished | Mar 05 01:28:04 PM PST 24 |
| Peak memory | 326500 kb |
| Host | smart-c9560b82-281b-471c-83b3-24d39a275d3f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662296074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1662296074 |
| Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.1942518001 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 10284129 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:27:17 PM PST 24 |
| Finished | Mar 05 01:27:18 PM PST 24 |
| Peak memory | 202004 kb |
| Host | smart-1d6fdb61-4878-4dfd-89fd-ba170d68f8a9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942518001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1942518001 |
| Directory | /workspace/44.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_bijection.1614539290 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 64287837992 ps |
| CPU time | 1014.66 seconds |
| Started | Mar 05 01:27:19 PM PST 24 |
| Finished | Mar 05 01:44:14 PM PST 24 |
| Peak memory | 202824 kb |
| Host | smart-a6de4d0a-40d6-4368-9f40-ec958a42e180 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614539290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .1614539290 |
| Directory | /workspace/44.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_executable.3022918200 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 37451947776 ps |
| CPU time | 1009.4 seconds |
| Started | Mar 05 01:27:17 PM PST 24 |
| Finished | Mar 05 01:44:06 PM PST 24 |
| Peak memory | 375480 kb |
| Host | smart-993996a5-ad07-4d74-bcb0-bcbe75d9eb20 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022918200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.3022918200 |
| Directory | /workspace/44.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.2325519462 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 32756305220 ps |
| CPU time | 397.7 seconds |
| Started | Mar 05 01:27:17 PM PST 24 |
| Finished | Mar 05 01:33:55 PM PST 24 |
| Peak memory | 210964 kb |
| Host | smart-a12cf40c-72b2-470d-8acb-a620b9623ea5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325519462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.2325519462 |
| Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.733096911 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3178786712 ps |
| CPU time | 100.67 seconds |
| Started | Mar 05 01:27:14 PM PST 24 |
| Finished | Mar 05 01:28:55 PM PST 24 |
| Peak memory | 362188 kb |
| Host | smart-c978bdcb-85ed-4510-9e31-035e4cd31c15 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733096911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.sram_ctrl_max_throughput.733096911 |
| Directory | /workspace/44.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3165374444 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 6248904766 ps |
| CPU time | 118.84 seconds |
| Started | Mar 05 01:27:17 PM PST 24 |
| Finished | Mar 05 01:29:16 PM PST 24 |
| Peak memory | 210844 kb |
| Host | smart-183fb8da-cff2-46e4-8e32-33e492c374d0 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165374444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.3165374444 |
| Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.1075445539 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 6909519438 ps |
| CPU time | 144.1 seconds |
| Started | Mar 05 01:27:15 PM PST 24 |
| Finished | Mar 05 01:29:40 PM PST 24 |
| Peak memory | 202836 kb |
| Host | smart-d956afe8-c18e-4533-adc6-b9179d669a24 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075445539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1075445539 |
| Directory | /workspace/44.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.2212306336 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 11801701472 ps |
| CPU time | 360.64 seconds |
| Started | Mar 05 01:27:14 PM PST 24 |
| Finished | Mar 05 01:33:15 PM PST 24 |
| Peak memory | 353228 kb |
| Host | smart-797556b3-6f17-42f7-b6d9-13d5de2fb17e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212306336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.2212306336 |
| Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.1562744553 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 1657195634 ps |
| CPU time | 23.7 seconds |
| Started | Mar 05 01:27:14 PM PST 24 |
| Finished | Mar 05 01:27:37 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-1ce8f8e8-966e-4755-b2a1-fb70a63f0466 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562744553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.1562744553 |
| Directory | /workspace/44.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.304864835 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 14191017029 ps |
| CPU time | 385.45 seconds |
| Started | Mar 05 01:27:15 PM PST 24 |
| Finished | Mar 05 01:33:40 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-1e564e6d-f631-48b4-98ae-ab0b2b697b3f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304864835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.sram_ctrl_partial_access_b2b.304864835 |
| Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.2766999356 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 361959628 ps |
| CPU time | 3.25 seconds |
| Started | Mar 05 01:27:15 PM PST 24 |
| Finished | Mar 05 01:27:18 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-fd5bd63b-c21f-4371-bd93-863d3d83e030 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766999356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2766999356 |
| Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_regwen.1410250663 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 48775469631 ps |
| CPU time | 1169.55 seconds |
| Started | Mar 05 01:27:14 PM PST 24 |
| Finished | Mar 05 01:46:44 PM PST 24 |
| Peak memory | 376588 kb |
| Host | smart-c3374e07-745e-4f0f-8fa4-344fba7feae9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410250663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1410250663 |
| Directory | /workspace/44.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_smoke.2571223377 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1304631555 ps |
| CPU time | 18.85 seconds |
| Started | Mar 05 01:27:08 PM PST 24 |
| Finished | Mar 05 01:27:27 PM PST 24 |
| Peak memory | 253020 kb |
| Host | smart-7414be59-0704-4894-9df9-9472ba367375 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571223377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2571223377 |
| Directory | /workspace/44.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.1961943896 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 195755595290 ps |
| CPU time | 5060.11 seconds |
| Started | Mar 05 01:27:18 PM PST 24 |
| Finished | Mar 05 02:51:39 PM PST 24 |
| Peak memory | 379688 kb |
| Host | smart-02b708e8-8663-4cc4-b2a2-42b9a5cd8506 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961943896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.1961943896 |
| Directory | /workspace/44.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2089900847 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3125668206 ps |
| CPU time | 596.63 seconds |
| Started | Mar 05 01:27:16 PM PST 24 |
| Finished | Mar 05 01:37:13 PM PST 24 |
| Peak memory | 356260 kb |
| Host | smart-5aa48fa8-5528-4cfb-9d86-f77bc925b0dc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2089900847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2089900847 |
| Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3455005907 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 41785950400 ps |
| CPU time | 263.47 seconds |
| Started | Mar 05 01:27:17 PM PST 24 |
| Finished | Mar 05 01:31:40 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-f8dfcdde-9002-490a-8333-6807f0c6f3bf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455005907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.3455005907 |
| Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.92778198 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2328910481 ps |
| CPU time | 16.56 seconds |
| Started | Mar 05 01:27:18 PM PST 24 |
| Finished | Mar 05 01:27:34 PM PST 24 |
| Peak memory | 251868 kb |
| Host | smart-dbd5d7ad-5a2b-4bb4-9385-7eeb6b9a672e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92778198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.sram_ctrl_throughput_w_partial_write.92778198 |
| Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.2370999551 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 91330278 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:27:24 PM PST 24 |
| Finished | Mar 05 01:27:25 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-238561f6-d63d-47a0-bf9e-28a4f36ef123 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370999551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.2370999551 |
| Directory | /workspace/45.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_executable.3299129107 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 69856216819 ps |
| CPU time | 450.32 seconds |
| Started | Mar 05 01:27:22 PM PST 24 |
| Finished | Mar 05 01:34:52 PM PST 24 |
| Peak memory | 334200 kb |
| Host | smart-693cb26d-4cc9-444a-83d2-ea8b4e73536d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299129107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.3299129107 |
| Directory | /workspace/45.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.1883768048 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6687068456 ps |
| CPU time | 94.82 seconds |
| Started | Mar 05 01:27:16 PM PST 24 |
| Finished | Mar 05 01:28:51 PM PST 24 |
| Peak memory | 210956 kb |
| Host | smart-905b371e-7d31-4a18-83cb-9617eccb0b10 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883768048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.1883768048 |
| Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.2770107014 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 799142705 ps |
| CPU time | 136.69 seconds |
| Started | Mar 05 01:27:15 PM PST 24 |
| Finished | Mar 05 01:29:32 PM PST 24 |
| Peak memory | 365228 kb |
| Host | smart-7ac11051-7be6-490a-b002-a04f321867f1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770107014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.2770107014 |
| Directory | /workspace/45.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.245605415 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2334570395 ps |
| CPU time | 74.56 seconds |
| Started | Mar 05 01:27:24 PM PST 24 |
| Finished | Mar 05 01:28:38 PM PST 24 |
| Peak memory | 211016 kb |
| Host | smart-4c3d4a9f-10a4-45dd-a709-6bd8c2d27dfd |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245605415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45 .sram_ctrl_mem_partial_access.245605415 |
| Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.30977370 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 8950771291 ps |
| CPU time | 155.69 seconds |
| Started | Mar 05 01:27:22 PM PST 24 |
| Finished | Mar 05 01:29:58 PM PST 24 |
| Peak memory | 202972 kb |
| Host | smart-26e1af1d-7413-4827-b89e-60785ec7a154 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30977370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ mem_walk.30977370 |
| Directory | /workspace/45.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.88261140 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 27111733601 ps |
| CPU time | 552.69 seconds |
| Started | Mar 05 01:27:16 PM PST 24 |
| Finished | Mar 05 01:36:29 PM PST 24 |
| Peak memory | 371500 kb |
| Host | smart-e66ff0d5-7b80-4472-9b67-4f812d4d0658 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88261140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multipl e_keys.88261140 |
| Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.1580354208 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2194015191 ps |
| CPU time | 17.28 seconds |
| Started | Mar 05 01:27:17 PM PST 24 |
| Finished | Mar 05 01:27:34 PM PST 24 |
| Peak memory | 254512 kb |
| Host | smart-926b5060-9952-4c41-b0c4-5cd75d279ae3 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580354208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.1580354208 |
| Directory | /workspace/45.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1454460711 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 25679770304 ps |
| CPU time | 493.91 seconds |
| Started | Mar 05 01:27:14 PM PST 24 |
| Finished | Mar 05 01:35:28 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-3acd8926-2cf2-4bc4-84df-463c232debb2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454460711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.1454460711 |
| Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.889277759 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 349676237 ps |
| CPU time | 3.13 seconds |
| Started | Mar 05 01:27:22 PM PST 24 |
| Finished | Mar 05 01:27:25 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-e50c614f-9f89-494b-af34-afcd1ea58597 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889277759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.889277759 |
| Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_regwen.1483678654 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3718075508 ps |
| CPU time | 32.48 seconds |
| Started | Mar 05 01:27:23 PM PST 24 |
| Finished | Mar 05 01:27:56 PM PST 24 |
| Peak memory | 264596 kb |
| Host | smart-a2029d62-af69-46ab-a6e6-4275060b7999 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483678654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1483678654 |
| Directory | /workspace/45.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_smoke.4035874376 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 5681714529 ps |
| CPU time | 48.81 seconds |
| Started | Mar 05 01:27:15 PM PST 24 |
| Finished | Mar 05 01:28:03 PM PST 24 |
| Peak memory | 294908 kb |
| Host | smart-d5454396-5e86-4090-94e0-3ee828872a79 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035874376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.4035874376 |
| Directory | /workspace/45.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.1573398531 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 129486121172 ps |
| CPU time | 3891.55 seconds |
| Started | Mar 05 01:27:24 PM PST 24 |
| Finished | Mar 05 02:32:16 PM PST 24 |
| Peak memory | 379708 kb |
| Host | smart-755ac8ab-0ff4-44f5-8038-3b66a12dd2d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573398531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.1573398531 |
| Directory | /workspace/45.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.897963004 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 950305469 ps |
| CPU time | 21.14 seconds |
| Started | Mar 05 01:27:24 PM PST 24 |
| Finished | Mar 05 01:27:45 PM PST 24 |
| Peak memory | 211028 kb |
| Host | smart-e4c23c88-f7d6-4ac4-9d5b-2487bc032f2e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=897963004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.897963004 |
| Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.4292863065 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 40142536686 ps |
| CPU time | 316.9 seconds |
| Started | Mar 05 01:27:18 PM PST 24 |
| Finished | Mar 05 01:32:35 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-41c7c3ec-0d71-4f9f-b379-93e2bf700a3e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292863065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.4292863065 |
| Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3570472778 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1484883980 ps |
| CPU time | 105.02 seconds |
| Started | Mar 05 01:27:14 PM PST 24 |
| Finished | Mar 05 01:28:59 PM PST 24 |
| Peak memory | 332544 kb |
| Host | smart-7f05cba9-c61f-4e72-97c3-7acc1508ad9b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570472778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.3570472778 |
| Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.1846517769 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 36612660 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:27:33 PM PST 24 |
| Finished | Mar 05 01:27:34 PM PST 24 |
| Peak memory | 202160 kb |
| Host | smart-1555658f-7907-413e-a8f8-218907ce6519 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846517769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1846517769 |
| Directory | /workspace/46.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_bijection.1100786082 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 609365819928 ps |
| CPU time | 1929.53 seconds |
| Started | Mar 05 01:27:24 PM PST 24 |
| Finished | Mar 05 01:59:34 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-9023c784-beff-471f-9b45-21e04b7e8cce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100786082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .1100786082 |
| Directory | /workspace/46.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_executable.3578410955 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 73629687715 ps |
| CPU time | 607.94 seconds |
| Started | Mar 05 01:27:31 PM PST 24 |
| Finished | Mar 05 01:37:39 PM PST 24 |
| Peak memory | 372404 kb |
| Host | smart-86abd337-82b3-4c70-b73c-4d57220d6280 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578410955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.3578410955 |
| Directory | /workspace/46.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.1995098916 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 5743075642 ps |
| CPU time | 94.47 seconds |
| Started | Mar 05 01:27:33 PM PST 24 |
| Finished | Mar 05 01:29:08 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-3306f022-7fab-4a58-9433-7538acd45c7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995098916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.1995098916 |
| Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.4272729050 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 821740477 ps |
| CPU time | 6.75 seconds |
| Started | Mar 05 01:27:23 PM PST 24 |
| Finished | Mar 05 01:27:30 PM PST 24 |
| Peak memory | 213696 kb |
| Host | smart-9c9b32f6-e55c-4853-9ce6-fc528df395c6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272729050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.4272729050 |
| Directory | /workspace/46.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1853432922 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 17451952569 ps |
| CPU time | 141.96 seconds |
| Started | Mar 05 01:27:29 PM PST 24 |
| Finished | Mar 05 01:29:51 PM PST 24 |
| Peak memory | 210956 kb |
| Host | smart-848cafb2-4331-4a07-9a5e-cb7869d6085e |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853432922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.1853432922 |
| Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.2565670972 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2042268739 ps |
| CPU time | 121.98 seconds |
| Started | Mar 05 01:27:31 PM PST 24 |
| Finished | Mar 05 01:29:33 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-5620abfa-dfa8-4ec3-97bd-38829ee42d06 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565670972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.2565670972 |
| Directory | /workspace/46.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.2179855135 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 32130241003 ps |
| CPU time | 703.02 seconds |
| Started | Mar 05 01:27:23 PM PST 24 |
| Finished | Mar 05 01:39:06 PM PST 24 |
| Peak memory | 371484 kb |
| Host | smart-63b03730-7c22-48ba-9a28-445a629cb07f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179855135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.2179855135 |
| Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.3665828266 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 2575299383 ps |
| CPU time | 33.94 seconds |
| Started | Mar 05 01:27:22 PM PST 24 |
| Finished | Mar 05 01:27:56 PM PST 24 |
| Peak memory | 284512 kb |
| Host | smart-e528e94d-3e89-4f19-9880-63758a15853c |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665828266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.3665828266 |
| Directory | /workspace/46.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2558386462 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 12810197964 ps |
| CPU time | 282.19 seconds |
| Started | Mar 05 01:27:23 PM PST 24 |
| Finished | Mar 05 01:32:05 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-19bc36dc-b60f-4587-99ea-6c0a564b7b25 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558386462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.2558386462 |
| Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.477851674 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1356515788 ps |
| CPU time | 3.39 seconds |
| Started | Mar 05 01:27:29 PM PST 24 |
| Finished | Mar 05 01:27:33 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-d02a7099-0732-4407-ac5b-ed5ea8c67ba5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477851674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.477851674 |
| Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_regwen.1903367175 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 11445457645 ps |
| CPU time | 540.05 seconds |
| Started | Mar 05 01:27:30 PM PST 24 |
| Finished | Mar 05 01:36:31 PM PST 24 |
| Peak memory | 373528 kb |
| Host | smart-b8b69464-d1e9-4444-aeb9-25a5bb594f5d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903367175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1903367175 |
| Directory | /workspace/46.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_smoke.4175769443 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3751802557 ps |
| CPU time | 144.18 seconds |
| Started | Mar 05 01:27:23 PM PST 24 |
| Finished | Mar 05 01:29:48 PM PST 24 |
| Peak memory | 368340 kb |
| Host | smart-12274c82-daf1-4227-817f-6f57c005c058 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175769443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.4175769443 |
| Directory | /workspace/46.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.612736428 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 494855744 ps |
| CPU time | 8.94 seconds |
| Started | Mar 05 01:27:31 PM PST 24 |
| Finished | Mar 05 01:27:40 PM PST 24 |
| Peak memory | 212016 kb |
| Host | smart-c4622f92-4721-4c2c-88eb-283a6927b392 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=612736428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.612736428 |
| Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2982556780 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 15644701631 ps |
| CPU time | 264.93 seconds |
| Started | Mar 05 01:27:23 PM PST 24 |
| Finished | Mar 05 01:31:48 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-789e2a44-75cd-41d3-9029-4e8003e01661 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982556780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.2982556780 |
| Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.654055571 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2813941212 ps |
| CPU time | 8.04 seconds |
| Started | Mar 05 01:27:21 PM PST 24 |
| Finished | Mar 05 01:27:29 PM PST 24 |
| Peak memory | 217732 kb |
| Host | smart-8c3ef024-279d-4c10-b4a7-0a4dc521320c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654055571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_throughput_w_partial_write.654055571 |
| Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.3935697468 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 19513754 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:27:40 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-b6b7e935-d7ee-4845-8b6d-e2363351aa6e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935697468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3935697468 |
| Directory | /workspace/47.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_bijection.1725927411 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 99552964977 ps |
| CPU time | 1974.93 seconds |
| Started | Mar 05 01:27:33 PM PST 24 |
| Finished | Mar 05 02:00:28 PM PST 24 |
| Peak memory | 202848 kb |
| Host | smart-717ca688-9abf-49bc-abcc-e06dbd019dad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725927411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .1725927411 |
| Directory | /workspace/47.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_executable.812449930 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 59029961640 ps |
| CPU time | 394.69 seconds |
| Started | Mar 05 01:27:40 PM PST 24 |
| Finished | Mar 05 01:34:14 PM PST 24 |
| Peak memory | 353020 kb |
| Host | smart-714ce49c-b64e-45a2-b6be-84aac60bada6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812449930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executabl e.812449930 |
| Directory | /workspace/47.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.4140121476 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 800769556 ps |
| CPU time | 141.28 seconds |
| Started | Mar 05 01:27:31 PM PST 24 |
| Finished | Mar 05 01:29:53 PM PST 24 |
| Peak memory | 368764 kb |
| Host | smart-910305cc-db59-48ca-8fed-9944d0c6a9b2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140121476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.4140121476 |
| Directory | /workspace/47.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1343974866 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 975614173 ps |
| CPU time | 62.17 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:28:42 PM PST 24 |
| Peak memory | 210804 kb |
| Host | smart-d00f4907-36f6-4869-90f3-0a5664f6d005 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343974866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.1343974866 |
| Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.912112421 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 4028326181 ps |
| CPU time | 251.42 seconds |
| Started | Mar 05 01:27:38 PM PST 24 |
| Finished | Mar 05 01:31:50 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-099d1c26-11c8-4ecf-af93-955a112b2e30 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912112421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl _mem_walk.912112421 |
| Directory | /workspace/47.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.566089068 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 70960588349 ps |
| CPU time | 898.05 seconds |
| Started | Mar 05 01:27:31 PM PST 24 |
| Finished | Mar 05 01:42:29 PM PST 24 |
| Peak memory | 379608 kb |
| Host | smart-6fe913ac-9b99-4a5d-807b-e62191dd3937 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566089068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multip le_keys.566089068 |
| Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.191584527 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 9931972422 ps |
| CPU time | 15.3 seconds |
| Started | Mar 05 01:27:31 PM PST 24 |
| Finished | Mar 05 01:27:47 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-d9193476-e62a-4c36-ac6e-b1fd4722a57d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191584527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.s ram_ctrl_partial_access.191584527 |
| Directory | /workspace/47.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1589895018 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 19168091818 ps |
| CPU time | 417.18 seconds |
| Started | Mar 05 01:27:30 PM PST 24 |
| Finished | Mar 05 01:34:28 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-abea79be-2391-4978-8eff-8a39dabb5f4b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589895018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.1589895018 |
| Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.3934083357 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 360811438 ps |
| CPU time | 2.95 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:27:42 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-72519f3a-670a-4c5b-a376-80e3b1319e74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934083357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3934083357 |
| Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_regwen.2586380437 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4517306590 ps |
| CPU time | 325.46 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:33:05 PM PST 24 |
| Peak memory | 365368 kb |
| Host | smart-b234a0cc-b8f6-41ac-a4fa-cd1cae704c27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586380437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2586380437 |
| Directory | /workspace/47.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_smoke.1934933199 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 392860228 ps |
| CPU time | 3.82 seconds |
| Started | Mar 05 01:27:30 PM PST 24 |
| Finished | Mar 05 01:27:34 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-ca8ba48c-f463-401f-8160-8ab3090b32b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934933199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1934933199 |
| Directory | /workspace/47.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.331552389 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 820294200420 ps |
| CPU time | 8625.45 seconds |
| Started | Mar 05 01:27:43 PM PST 24 |
| Finished | Mar 05 03:51:29 PM PST 24 |
| Peak memory | 387860 kb |
| Host | smart-22f5d187-17c6-4670-b600-fe876b85a030 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331552389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_stress_all.331552389 |
| Directory | /workspace/47.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.46945603 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1617693214 ps |
| CPU time | 179.25 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:30:38 PM PST 24 |
| Peak memory | 375608 kb |
| Host | smart-c52e974c-f360-4e17-8c31-221eaef70b74 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=46945603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.46945603 |
| Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.163907630 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 5215263559 ps |
| CPU time | 357.71 seconds |
| Started | Mar 05 01:27:30 PM PST 24 |
| Finished | Mar 05 01:33:28 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-20da8471-32be-4add-87b8-d3a738236ec3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163907630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_stress_pipeline.163907630 |
| Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2519993022 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 5328583371 ps |
| CPU time | 12.45 seconds |
| Started | Mar 05 01:27:30 PM PST 24 |
| Finished | Mar 05 01:27:43 PM PST 24 |
| Peak memory | 239640 kb |
| Host | smart-b64cfd21-e959-4034-8672-88bdc0fe05a0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519993022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.2519993022 |
| Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.2330486660 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 18970568 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:27:47 PM PST 24 |
| Finished | Mar 05 01:27:48 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-b2ffd6fa-9e55-4e69-bbec-6e2c846bbded |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330486660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.2330486660 |
| Directory | /workspace/48.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_bijection.4009522511 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 106626444833 ps |
| CPU time | 2434.47 seconds |
| Started | Mar 05 01:27:41 PM PST 24 |
| Finished | Mar 05 02:08:15 PM PST 24 |
| Peak memory | 202856 kb |
| Host | smart-cc317309-2b86-496c-9647-8873140e4acd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009522511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .4009522511 |
| Directory | /workspace/48.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_executable.2185207394 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 27273150711 ps |
| CPU time | 1426.1 seconds |
| Started | Mar 05 01:27:47 PM PST 24 |
| Finished | Mar 05 01:51:33 PM PST 24 |
| Peak memory | 377604 kb |
| Host | smart-822cd7b9-1ebb-462d-a7ae-1ca31328b940 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185207394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.2185207394 |
| Directory | /workspace/48.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.1606783666 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 19398983174 ps |
| CPU time | 281.4 seconds |
| Started | Mar 05 01:27:45 PM PST 24 |
| Finished | Mar 05 01:32:27 PM PST 24 |
| Peak memory | 216040 kb |
| Host | smart-b5d9e1b1-0ef0-4a54-ade2-6a1a53150f5b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606783666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.1606783666 |
| Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.1861001265 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2511387795 ps |
| CPU time | 7.04 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:27:46 PM PST 24 |
| Peak memory | 216144 kb |
| Host | smart-65c8e579-c069-4969-8943-a068e2ec2d8f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861001265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.1861001265 |
| Directory | /workspace/48.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3457241063 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 4778198078 ps |
| CPU time | 71.8 seconds |
| Started | Mar 05 01:27:46 PM PST 24 |
| Finished | Mar 05 01:28:57 PM PST 24 |
| Peak memory | 211008 kb |
| Host | smart-688e8e27-32f5-419c-9f53-40e5f640f284 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457241063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.3457241063 |
| Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.652907761 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 105979280396 ps |
| CPU time | 303.26 seconds |
| Started | Mar 05 01:27:48 PM PST 24 |
| Finished | Mar 05 01:32:52 PM PST 24 |
| Peak memory | 202840 kb |
| Host | smart-155f8c10-197d-44eb-adec-e82da1260d67 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652907761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl _mem_walk.652907761 |
| Directory | /workspace/48.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.2197378088 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 15113847809 ps |
| CPU time | 1393.85 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:50:54 PM PST 24 |
| Peak memory | 377800 kb |
| Host | smart-34adfeb3-503e-4a2c-bd94-109d421362e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197378088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.2197378088 |
| Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.42168715 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 1026070594 ps |
| CPU time | 30.03 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:28:09 PM PST 24 |
| Peak memory | 274876 kb |
| Host | smart-db1b7ab7-00d2-4fa9-a8c8-6ccfb6fe9bbd |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42168715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sr am_ctrl_partial_access.42168715 |
| Directory | /workspace/48.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1315414377 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 14205654003 ps |
| CPU time | 193.59 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:30:52 PM PST 24 |
| Peak memory | 202784 kb |
| Host | smart-06a46c6e-b3a0-49ff-ac6b-54954f4de5d0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315414377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.1315414377 |
| Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.240523001 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 368338556 ps |
| CPU time | 2.99 seconds |
| Started | Mar 05 01:27:45 PM PST 24 |
| Finished | Mar 05 01:27:48 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-dd07a5a6-df93-4d36-8a3a-a3449cc81b2c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240523001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.240523001 |
| Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_regwen.3532302745 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 65720148636 ps |
| CPU time | 606.46 seconds |
| Started | Mar 05 01:27:49 PM PST 24 |
| Finished | Mar 05 01:37:56 PM PST 24 |
| Peak memory | 372404 kb |
| Host | smart-64460633-d717-4b06-adfa-4ca591ecfa7f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532302745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3532302745 |
| Directory | /workspace/48.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_smoke.545431133 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1694642129 ps |
| CPU time | 4.68 seconds |
| Started | Mar 05 01:27:41 PM PST 24 |
| Finished | Mar 05 01:27:46 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-08242f09-02e5-4cd0-aac8-4b1920960067 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545431133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.545431133 |
| Directory | /workspace/48.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.3476649784 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 47511103347 ps |
| CPU time | 4395.37 seconds |
| Started | Mar 05 01:27:46 PM PST 24 |
| Finished | Mar 05 02:41:02 PM PST 24 |
| Peak memory | 388864 kb |
| Host | smart-baef4ccd-f099-486f-b91b-9c5a4fc0d198 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476649784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.3476649784 |
| Directory | /workspace/48.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2668430507 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 280312040 ps |
| CPU time | 10.05 seconds |
| Started | Mar 05 01:27:47 PM PST 24 |
| Finished | Mar 05 01:27:57 PM PST 24 |
| Peak memory | 212068 kb |
| Host | smart-e33e9989-9918-4ec7-a5c2-0d96964879ee |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2668430507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2668430507 |
| Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1911455075 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 5298248553 ps |
| CPU time | 293.02 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:32:32 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-f5609558-0ff5-4513-957d-8411c3361b7e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911455075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.1911455075 |
| Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2004083179 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3058329393 ps |
| CPU time | 20.18 seconds |
| Started | Mar 05 01:27:39 PM PST 24 |
| Finished | Mar 05 01:27:59 PM PST 24 |
| Peak memory | 253916 kb |
| Host | smart-4ccf7682-0183-4a89-9b4e-e2c266f7b6e0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004083179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.2004083179 |
| Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.2057200870 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 62116121 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 01:27:53 PM PST 24 |
| Finished | Mar 05 01:27:53 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-4c04027e-6fdf-4666-bbc3-d503cb4791a8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057200870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2057200870 |
| Directory | /workspace/49.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_bijection.3728535950 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 29537543008 ps |
| CPU time | 2072.07 seconds |
| Started | Mar 05 01:27:45 PM PST 24 |
| Finished | Mar 05 02:02:17 PM PST 24 |
| Peak memory | 202868 kb |
| Host | smart-34e45d95-d86e-4921-9886-d43af7a9eaf9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728535950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .3728535950 |
| Directory | /workspace/49.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_executable.2331527496 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 21141758173 ps |
| CPU time | 608.47 seconds |
| Started | Mar 05 01:27:53 PM PST 24 |
| Finished | Mar 05 01:38:02 PM PST 24 |
| Peak memory | 372000 kb |
| Host | smart-9122c2fe-cfde-4e44-8d4f-6da0d871263a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331527496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.2331527496 |
| Directory | /workspace/49.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.1403569373 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5326517144 ps |
| CPU time | 74.25 seconds |
| Started | Mar 05 01:27:51 PM PST 24 |
| Finished | Mar 05 01:29:06 PM PST 24 |
| Peak memory | 210964 kb |
| Host | smart-cedfc050-4f72-451a-aaf9-1a0ef3857133 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403569373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.1403569373 |
| Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.2645505483 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 7753133598 ps |
| CPU time | 18.96 seconds |
| Started | Mar 05 01:27:52 PM PST 24 |
| Finished | Mar 05 01:28:11 PM PST 24 |
| Peak memory | 251800 kb |
| Host | smart-0a81ebda-3755-4a77-9067-8c89498305ec |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645505483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.2645505483 |
| Directory | /workspace/49.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.933901465 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2456131374 ps |
| CPU time | 72.58 seconds |
| Started | Mar 05 01:27:55 PM PST 24 |
| Finished | Mar 05 01:29:07 PM PST 24 |
| Peak memory | 210972 kb |
| Host | smart-adb83de4-47c4-43c8-bec1-624955f8edad |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933901465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sram_ctrl_mem_partial_access.933901465 |
| Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.1008001695 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 39729271951 ps |
| CPU time | 303.96 seconds |
| Started | Mar 05 01:27:55 PM PST 24 |
| Finished | Mar 05 01:32:59 PM PST 24 |
| Peak memory | 202892 kb |
| Host | smart-9f6dadf8-cf1a-4d05-99aa-db318d5e8fb1 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008001695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.1008001695 |
| Directory | /workspace/49.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.371286198 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 24715786071 ps |
| CPU time | 1204.34 seconds |
| Started | Mar 05 01:27:45 PM PST 24 |
| Finished | Mar 05 01:47:50 PM PST 24 |
| Peak memory | 380744 kb |
| Host | smart-d54bc6aa-3b48-4758-aea9-2820b34ba208 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371286198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip le_keys.371286198 |
| Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.58295778 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 20996555195 ps |
| CPU time | 29.22 seconds |
| Started | Mar 05 01:27:46 PM PST 24 |
| Finished | Mar 05 01:28:16 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-558a4d9b-9791-465f-a764-0d52892bc52c |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58295778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sr am_ctrl_partial_access.58295778 |
| Directory | /workspace/49.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3705184530 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 18572319055 ps |
| CPU time | 444.96 seconds |
| Started | Mar 05 01:27:49 PM PST 24 |
| Finished | Mar 05 01:35:14 PM PST 24 |
| Peak memory | 201900 kb |
| Host | smart-f7ecdbd7-f1c9-4f2b-b0ef-5975ea3e1df5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705184530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.3705184530 |
| Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.662442195 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 690303350 ps |
| CPU time | 3.19 seconds |
| Started | Mar 05 01:27:53 PM PST 24 |
| Finished | Mar 05 01:27:56 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-bb0727b0-53ce-41ae-ab7a-0d8e4bb897e7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662442195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.662442195 |
| Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_regwen.3727711018 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 590041480 ps |
| CPU time | 50 seconds |
| Started | Mar 05 01:27:53 PM PST 24 |
| Finished | Mar 05 01:28:44 PM PST 24 |
| Peak memory | 295688 kb |
| Host | smart-330ae9ed-be08-4867-91d0-12a9089d0732 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727711018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3727711018 |
| Directory | /workspace/49.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_smoke.3063831322 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 5439518787 ps |
| CPU time | 12.76 seconds |
| Started | Mar 05 01:27:47 PM PST 24 |
| Finished | Mar 05 01:28:00 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-fd9b5074-1afd-4f6a-8b7c-f866e5bacd23 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063831322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3063831322 |
| Directory | /workspace/49.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1179591931 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 571194548 ps |
| CPU time | 17.95 seconds |
| Started | Mar 05 01:27:53 PM PST 24 |
| Finished | Mar 05 01:28:11 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-6bbfff34-5e2a-4014-8f68-8c34a17f31c3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1179591931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1179591931 |
| Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1372385609 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 4314373065 ps |
| CPU time | 109.74 seconds |
| Started | Mar 05 01:27:47 PM PST 24 |
| Finished | Mar 05 01:29:37 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-f6370c21-ce7e-45d9-8762-fd2fcfb337b9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372385609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.1372385609 |
| Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4104003398 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2974424540 ps |
| CPU time | 49.14 seconds |
| Started | Mar 05 01:27:54 PM PST 24 |
| Finished | Mar 05 01:28:43 PM PST 24 |
| Peak memory | 310216 kb |
| Host | smart-01eebe0c-62a6-4238-9db1-e807cf5d02e5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104003398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.4104003398 |
| Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.4249290465 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 12236562 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 01:24:26 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-1a7bd150-cb91-4684-a25d-2e05e9dc2fb9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249290465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.4249290465 |
| Directory | /workspace/5.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_bijection.3929784153 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 97643431984 ps |
| CPU time | 2228.21 seconds |
| Started | Mar 05 01:24:45 PM PST 24 |
| Finished | Mar 05 02:01:54 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-f55006c9-4ded-48af-9d57-794cd4b0401f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929784153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 3929784153 |
| Directory | /workspace/5.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_executable.1160769448 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 13288659079 ps |
| CPU time | 881.49 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:39:09 PM PST 24 |
| Peak memory | 373436 kb |
| Host | smart-07563484-eba7-40d2-895c-b07ecb6f1c7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160769448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.1160769448 |
| Directory | /workspace/5.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.3525097002 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4267507541 ps |
| CPU time | 71.84 seconds |
| Started | Mar 05 01:24:33 PM PST 24 |
| Finished | Mar 05 01:25:44 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-26227af5-edae-4e38-b951-0c599e21d0ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525097002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.3525097002 |
| Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.124392801 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5885539344 ps |
| CPU time | 25.11 seconds |
| Started | Mar 05 01:24:35 PM PST 24 |
| Finished | Mar 05 01:25:00 PM PST 24 |
| Peak memory | 269152 kb |
| Host | smart-571d14b9-fd7d-4854-a329-ebccf572cba7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124392801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.sram_ctrl_max_throughput.124392801 |
| Directory | /workspace/5.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3877211504 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2724042117 ps |
| CPU time | 77.15 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:25:45 PM PST 24 |
| Peak memory | 210856 kb |
| Host | smart-37af28d0-aa3f-4c0e-8082-8a6c3de21714 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877211504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.3877211504 |
| Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.223302336 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 18451598973 ps |
| CPU time | 309.96 seconds |
| Started | Mar 05 01:24:30 PM PST 24 |
| Finished | Mar 05 01:29:40 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-528708ec-2820-4d22-9991-a839f1de6fc4 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223302336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ mem_walk.223302336 |
| Directory | /workspace/5.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.1461071457 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 6200618036 ps |
| CPU time | 397.18 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:31:18 PM PST 24 |
| Peak memory | 375220 kb |
| Host | smart-8c0f4832-b0b8-48b1-98fb-5acdba759ec6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461071457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.1461071457 |
| Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.938928179 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2677973998 ps |
| CPU time | 152.99 seconds |
| Started | Mar 05 01:24:30 PM PST 24 |
| Finished | Mar 05 01:27:03 PM PST 24 |
| Peak memory | 366316 kb |
| Host | smart-bbb4d655-3488-4f8e-a91b-65abbfc8f23b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938928179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sr am_ctrl_partial_access.938928179 |
| Directory | /workspace/5.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1173602479 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 77180063620 ps |
| CPU time | 452.02 seconds |
| Started | Mar 05 01:24:46 PM PST 24 |
| Finished | Mar 05 01:32:18 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-b134bb88-874a-4553-aa4f-a6a4dbbde30e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173602479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.1173602479 |
| Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.1999769401 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3411073295 ps |
| CPU time | 3.24 seconds |
| Started | Mar 05 01:24:36 PM PST 24 |
| Finished | Mar 05 01:24:40 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-ccd3d5aa-25d7-441a-9221-7f15c775f081 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999769401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1999769401 |
| Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_regwen.3758910912 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 16634575061 ps |
| CPU time | 1561.59 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:50:29 PM PST 24 |
| Peak memory | 371956 kb |
| Host | smart-bee99709-a750-4e3a-b910-9ee4483db686 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758910912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3758910912 |
| Directory | /workspace/5.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_smoke.2680208056 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 699634436 ps |
| CPU time | 43.85 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:25:12 PM PST 24 |
| Peak memory | 285676 kb |
| Host | smart-0b158748-312f-4110-9b96-bc0a620e64df |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680208056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2680208056 |
| Directory | /workspace/5.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.1168505953 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 235225127557 ps |
| CPU time | 8088.8 seconds |
| Started | Mar 05 01:24:31 PM PST 24 |
| Finished | Mar 05 03:39:21 PM PST 24 |
| Peak memory | 381748 kb |
| Host | smart-994fdaa4-ce10-4fb2-a390-5f01ca9621dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168505953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.1168505953 |
| Directory | /workspace/5.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3343914612 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 394966987 ps |
| CPU time | 8.09 seconds |
| Started | Mar 05 01:24:31 PM PST 24 |
| Finished | Mar 05 01:24:39 PM PST 24 |
| Peak memory | 211044 kb |
| Host | smart-6876d7ac-a3e0-49d3-b7c4-35cc890af459 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3343914612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3343914612 |
| Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1726628006 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2505097100 ps |
| CPU time | 126.91 seconds |
| Started | Mar 05 01:24:46 PM PST 24 |
| Finished | Mar 05 01:26:53 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-b412a23a-0e11-4409-82b4-a66b83269b16 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726628006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.1726628006 |
| Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1221316259 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 716745383 ps |
| CPU time | 22.34 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:24:50 PM PST 24 |
| Peak memory | 256796 kb |
| Host | smart-b32756e0-a383-4e23-8930-567285f551bc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221316259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1221316259 |
| Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.4173345198 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 42620560 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:24:35 PM PST 24 |
| Finished | Mar 05 01:24:35 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-807f7bb2-3f4f-4df7-8b99-e5dc6e5a3e54 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173345198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.4173345198 |
| Directory | /workspace/6.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_bijection.1647960995 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 9906702436 ps |
| CPU time | 535.02 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:33:22 PM PST 24 |
| Peak memory | 202904 kb |
| Host | smart-355975bc-1b0b-4938-9b21-2db78709f6b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647960995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 1647960995 |
| Directory | /workspace/6.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_executable.621588077 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3637195426 ps |
| CPU time | 22.02 seconds |
| Started | Mar 05 01:24:47 PM PST 24 |
| Finished | Mar 05 01:25:10 PM PST 24 |
| Peak memory | 229344 kb |
| Host | smart-271ac9d4-59f1-4e55-b981-b2a4e95e3269 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621588077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable .621588077 |
| Directory | /workspace/6.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.1685702353 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 720000657 ps |
| CPU time | 17.02 seconds |
| Started | Mar 05 01:24:30 PM PST 24 |
| Finished | Mar 05 01:24:47 PM PST 24 |
| Peak memory | 256788 kb |
| Host | smart-2a20519f-a9eb-495f-a300-8a486cb8071c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685702353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.1685702353 |
| Directory | /workspace/6.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.82212292 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 17352562937 ps |
| CPU time | 147.56 seconds |
| Started | Mar 05 01:24:36 PM PST 24 |
| Finished | Mar 05 01:27:09 PM PST 24 |
| Peak memory | 210992 kb |
| Host | smart-39dec843-978a-4d18-91f5-4180a4edb74f |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82212292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_mem_partial_access.82212292 |
| Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.116346938 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 15759141729 ps |
| CPU time | 252.02 seconds |
| Started | Mar 05 01:24:25 PM PST 24 |
| Finished | Mar 05 01:28:38 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-7e31d8b6-50f0-4bd1-b733-9cd5f9dd186f |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116346938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ mem_walk.116346938 |
| Directory | /workspace/6.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.2838660494 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 370763941 ps |
| CPU time | 7.37 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:24:35 PM PST 24 |
| Peak memory | 221440 kb |
| Host | smart-d18f987f-8899-4dae-902d-62c7e9552cf0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838660494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.2838660494 |
| Directory | /workspace/6.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3509192789 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 9860196061 ps |
| CPU time | 140.55 seconds |
| Started | Mar 05 01:24:50 PM PST 24 |
| Finished | Mar 05 01:27:11 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-5e3b6a89-7248-4861-a998-815e464acaab |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509192789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.3509192789 |
| Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.2801987115 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 443128032 ps |
| CPU time | 3.32 seconds |
| Started | Mar 05 01:24:40 PM PST 24 |
| Finished | Mar 05 01:24:43 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-78a9c9ef-bdce-4c47-b750-af89b3085d09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801987115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2801987115 |
| Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_regwen.1703867774 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 49814680198 ps |
| CPU time | 1184.56 seconds |
| Started | Mar 05 01:25:39 PM PST 24 |
| Finished | Mar 05 01:45:24 PM PST 24 |
| Peak memory | 373676 kb |
| Host | smart-aa8b2dea-5348-4fbe-a991-1818ec716ad1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703867774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1703867774 |
| Directory | /workspace/6.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_smoke.3702578740 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3921719507 ps |
| CPU time | 17.54 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:24:45 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-1675f7b7-fc00-4ffd-97ed-d29d6280d2ef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702578740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3702578740 |
| Directory | /workspace/6.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.20233697 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 357787123 ps |
| CPU time | 5.92 seconds |
| Started | Mar 05 01:24:42 PM PST 24 |
| Finished | Mar 05 01:24:48 PM PST 24 |
| Peak memory | 210976 kb |
| Host | smart-e831f4bd-e15e-44af-ab3b-684e9ec253cc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=20233697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.20233697 |
| Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3612590782 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 4105461905 ps |
| CPU time | 236.51 seconds |
| Started | Mar 05 01:24:32 PM PST 24 |
| Finished | Mar 05 01:28:29 PM PST 24 |
| Peak memory | 202808 kb |
| Host | smart-187f56e6-9c73-4883-a89b-0d127f550dd5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612590782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.3612590782 |
| Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.505907317 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 824441485 ps |
| CPU time | 65.09 seconds |
| Started | Mar 05 01:24:42 PM PST 24 |
| Finished | Mar 05 01:25:47 PM PST 24 |
| Peak memory | 302952 kb |
| Host | smart-c31de5d0-7707-4107-a04b-f5ed94339842 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505907317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.505907317 |
| Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.2697798119 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 16712260 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:24:27 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-6be2d1e4-562f-49f8-8699-c654c441c779 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697798119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.2697798119 |
| Directory | /workspace/7.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_bijection.2032134235 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 394910389582 ps |
| CPU time | 1344.87 seconds |
| Started | Mar 05 01:24:51 PM PST 24 |
| Finished | Mar 05 01:47:16 PM PST 24 |
| Peak memory | 202940 kb |
| Host | smart-e49354c2-95e5-46d4-ad0b-41f7c7c35c6b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032134235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 2032134235 |
| Directory | /workspace/7.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_executable.852405330 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 26298318271 ps |
| CPU time | 1486.13 seconds |
| Started | Mar 05 01:24:30 PM PST 24 |
| Finished | Mar 05 01:49:17 PM PST 24 |
| Peak memory | 379256 kb |
| Host | smart-aa68f5ab-0301-4c36-a22a-9813f3901efc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852405330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable .852405330 |
| Directory | /workspace/7.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.2552991242 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 24025052654 ps |
| CPU time | 305.05 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 01:29:31 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-a7343058-9c89-41f4-a9f2-7e965b4ef96b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552991242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.2552991242 |
| Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.2976378082 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1393474499 ps |
| CPU time | 7.83 seconds |
| Started | Mar 05 01:24:39 PM PST 24 |
| Finished | Mar 05 01:24:47 PM PST 24 |
| Peak memory | 220160 kb |
| Host | smart-41999611-8a08-4835-8b1c-cda9bd19eb71 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976378082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.2976378082 |
| Directory | /workspace/7.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.989069174 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2970877279 ps |
| CPU time | 75.06 seconds |
| Started | Mar 05 01:24:29 PM PST 24 |
| Finished | Mar 05 01:25:44 PM PST 24 |
| Peak memory | 211020 kb |
| Host | smart-6b5e283e-1d9c-4e7f-85e3-b0a2fb49f502 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989069174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7. sram_ctrl_mem_partial_access.989069174 |
| Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.2317987872 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 13769562395 ps |
| CPU time | 142.05 seconds |
| Started | Mar 05 01:24:37 PM PST 24 |
| Finished | Mar 05 01:27:00 PM PST 24 |
| Peak memory | 202992 kb |
| Host | smart-37e82e31-abc7-4f9e-816b-ce288bc87176 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317987872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2317987872 |
| Directory | /workspace/7.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.1806770651 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 24434733964 ps |
| CPU time | 939.76 seconds |
| Started | Mar 05 01:24:38 PM PST 24 |
| Finished | Mar 05 01:40:18 PM PST 24 |
| Peak memory | 380644 kb |
| Host | smart-dd5b08dc-9c2e-4291-a681-269cb2adde5d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806770651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.1806770651 |
| Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.4148936233 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2751779211 ps |
| CPU time | 27.31 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:25:09 PM PST 24 |
| Peak memory | 279232 kb |
| Host | smart-69c85667-dd4f-48c6-a144-6b3846885ab3 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148936233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.4148936233 |
| Directory | /workspace/7.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2266109534 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 19608837743 ps |
| CPU time | 463.14 seconds |
| Started | Mar 05 01:24:46 PM PST 24 |
| Finished | Mar 05 01:32:29 PM PST 24 |
| Peak memory | 202844 kb |
| Host | smart-4c48aff0-2892-4b74-bf9c-a458e138bce4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266109534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.2266109534 |
| Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.3123206674 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 693885892 ps |
| CPU time | 3.26 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:24:31 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-f7489f3b-5459-49d0-8acf-349164722e38 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123206674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3123206674 |
| Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_regwen.3214360924 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 8268555719 ps |
| CPU time | 371.61 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:30:39 PM PST 24 |
| Peak memory | 378600 kb |
| Host | smart-9280b843-06d9-47d5-8011-5abb67776d70 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214360924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3214360924 |
| Directory | /workspace/7.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_smoke.3644496611 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1939610570 ps |
| CPU time | 9.93 seconds |
| Started | Mar 05 01:24:35 PM PST 24 |
| Finished | Mar 05 01:24:50 PM PST 24 |
| Peak memory | 231368 kb |
| Host | smart-6359d0bd-aa81-40ac-b172-81b5b2a23799 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644496611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3644496611 |
| Directory | /workspace/7.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.1739596241 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1319510314337 ps |
| CPU time | 4776.04 seconds |
| Started | Mar 05 01:24:24 PM PST 24 |
| Finished | Mar 05 02:44:01 PM PST 24 |
| Peak memory | 381744 kb |
| Host | smart-a95a1ad8-2b36-48c2-8991-ed095c05ab39 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739596241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.1739596241 |
| Directory | /workspace/7.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2992503730 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2520056350 ps |
| CPU time | 33.57 seconds |
| Started | Mar 05 01:24:32 PM PST 24 |
| Finished | Mar 05 01:25:06 PM PST 24 |
| Peak memory | 211100 kb |
| Host | smart-d980adf1-60d6-45f9-abff-4d74da138363 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2992503730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2992503730 |
| Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3653029492 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4148889612 ps |
| CPU time | 250.15 seconds |
| Started | Mar 05 01:24:30 PM PST 24 |
| Finished | Mar 05 01:28:40 PM PST 24 |
| Peak memory | 202788 kb |
| Host | smart-b3115895-f99c-4161-9b7b-57c28733e90f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653029492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.3653029492 |
| Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2018451288 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 11178484103 ps |
| CPU time | 161.83 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:27:10 PM PST 24 |
| Peak memory | 368368 kb |
| Host | smart-74740fb1-dfd3-4296-ae5f-483064feb451 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018451288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2018451288 |
| Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.3874168870 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 11036795 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:24:28 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-54e16885-4a77-42a7-8550-ce82373016c8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874168870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.3874168870 |
| Directory | /workspace/8.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_bijection.3533680088 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 115103591403 ps |
| CPU time | 2525.6 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 02:06:33 PM PST 24 |
| Peak memory | 202844 kb |
| Host | smart-a0b1e842-bccc-44d8-bac8-aa1219c333d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533680088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 3533680088 |
| Directory | /workspace/8.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_executable.1445116844 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 19978191226 ps |
| CPU time | 506 seconds |
| Started | Mar 05 01:24:30 PM PST 24 |
| Finished | Mar 05 01:32:56 PM PST 24 |
| Peak memory | 377496 kb |
| Host | smart-bcb2f30c-ba2b-4108-82bb-e4fd8829ba91 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445116844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.1445116844 |
| Directory | /workspace/8.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.299856649 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 4618717978 ps |
| CPU time | 46.31 seconds |
| Started | Mar 05 01:24:34 PM PST 24 |
| Finished | Mar 05 01:25:20 PM PST 24 |
| Peak memory | 210868 kb |
| Host | smart-c31cfc0b-5475-4900-a8fb-98077a9f2285 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299856649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca lation.299856649 |
| Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.263126944 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3005655331 ps |
| CPU time | 98.38 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:26:05 PM PST 24 |
| Peak memory | 353924 kb |
| Host | smart-6847fa70-1473-4df5-afa1-87f017348968 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263126944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.sram_ctrl_max_throughput.263126944 |
| Directory | /workspace/8.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2435763867 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 22149272493 ps |
| CPU time | 121.48 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 01:26:27 PM PST 24 |
| Peak memory | 210928 kb |
| Host | smart-6c975c16-db21-42f9-b7e8-0f87c7d4b4d2 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435763867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.2435763867 |
| Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.210237184 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 4107603120 ps |
| CPU time | 243.53 seconds |
| Started | Mar 05 01:24:31 PM PST 24 |
| Finished | Mar 05 01:28:35 PM PST 24 |
| Peak memory | 203024 kb |
| Host | smart-d0f3d842-8d89-44be-9c21-dd94fdbd5c71 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210237184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ mem_walk.210237184 |
| Directory | /workspace/8.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.2803231196 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 35106471341 ps |
| CPU time | 302.29 seconds |
| Started | Mar 05 01:24:34 PM PST 24 |
| Finished | Mar 05 01:29:36 PM PST 24 |
| Peak memory | 334976 kb |
| Host | smart-d22a2f56-f3f5-4915-be62-e1dbe4ebe8cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803231196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.2803231196 |
| Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.615779399 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 494341957 ps |
| CPU time | 56.32 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:25:24 PM PST 24 |
| Peak memory | 322384 kb |
| Host | smart-86e9bc3f-f3c1-4d07-9d7a-8ce899c9615e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615779399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr am_ctrl_partial_access.615779399 |
| Directory | /workspace/8.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3096652408 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 13476837719 ps |
| CPU time | 311.25 seconds |
| Started | Mar 05 01:24:30 PM PST 24 |
| Finished | Mar 05 01:29:41 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-5888cf06-0843-4862-9373-50cd6794cdbb |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096652408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.3096652408 |
| Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.3125078387 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4186378999 ps |
| CPU time | 4.51 seconds |
| Started | Mar 05 01:24:26 PM PST 24 |
| Finished | Mar 05 01:24:30 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-eb311978-25ef-4ecc-8d45-00d49775b34d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125078387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3125078387 |
| Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_regwen.1688509875 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 11042460006 ps |
| CPU time | 433.09 seconds |
| Started | Mar 05 01:24:36 PM PST 24 |
| Finished | Mar 05 01:31:49 PM PST 24 |
| Peak memory | 370504 kb |
| Host | smart-2cd919b3-5770-433e-8947-4eeeeae2aad7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688509875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1688509875 |
| Directory | /workspace/8.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_smoke.3580220053 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 4345226864 ps |
| CPU time | 58.28 seconds |
| Started | Mar 05 01:24:29 PM PST 24 |
| Finished | Mar 05 01:25:28 PM PST 24 |
| Peak memory | 301916 kb |
| Host | smart-fd4e314a-7891-40fc-bfd9-1f6a0c17462f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580220053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3580220053 |
| Directory | /workspace/8.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.4200790568 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 89911002935 ps |
| CPU time | 3227.98 seconds |
| Started | Mar 05 01:24:40 PM PST 24 |
| Finished | Mar 05 02:18:29 PM PST 24 |
| Peak memory | 380596 kb |
| Host | smart-9c8617bb-4c28-42ea-8d7c-48fd7f1b5df8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200790568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.4200790568 |
| Directory | /workspace/8.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1290808042 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4633298598 ps |
| CPU time | 40.6 seconds |
| Started | Mar 05 01:24:40 PM PST 24 |
| Finished | Mar 05 01:25:21 PM PST 24 |
| Peak memory | 211100 kb |
| Host | smart-1109f51a-18b7-417c-8331-d6840471ca24 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1290808042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1290808042 |
| Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2678447366 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 8157185898 ps |
| CPU time | 286.24 seconds |
| Started | Mar 05 01:24:32 PM PST 24 |
| Finished | Mar 05 01:29:18 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-c0522a2c-7b24-44f1-9be0-254c9827dc6b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678447366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.2678447366 |
| Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2119610045 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 7461632319 ps |
| CPU time | 7.36 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:24:36 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-e5ede117-f44a-455b-b5b3-18d42e993baa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119610045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2119610045 |
| Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.1689720041 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 11877427 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 01:24:44 PM PST 24 |
| Finished | Mar 05 01:24:44 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-f409f89a-f0e5-4870-ac2b-d956e91add84 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689720041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1689720041 |
| Directory | /workspace/9.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_bijection.1066815409 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 46556872217 ps |
| CPU time | 549.76 seconds |
| Started | Mar 05 01:24:35 PM PST 24 |
| Finished | Mar 05 01:33:45 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-30acf9e5-b59e-42c3-8e28-ea064ccd935a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066815409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 1066815409 |
| Directory | /workspace/9.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_executable.3243906894 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 6543106814 ps |
| CPU time | 922.28 seconds |
| Started | Mar 05 01:24:22 PM PST 24 |
| Finished | Mar 05 01:39:45 PM PST 24 |
| Peak memory | 375552 kb |
| Host | smart-f9b2bbae-6f82-440b-9b55-fd98c0658ada |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243906894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.3243906894 |
| Directory | /workspace/9.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.3620929187 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 6317854561 ps |
| CPU time | 54.53 seconds |
| Started | Mar 05 01:24:35 PM PST 24 |
| Finished | Mar 05 01:25:30 PM PST 24 |
| Peak memory | 210972 kb |
| Host | smart-56af5cf2-f5c3-4346-9d6f-4831a3d85653 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620929187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.3620929187 |
| Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.1107180944 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 794826715 ps |
| CPU time | 99.7 seconds |
| Started | Mar 05 01:24:37 PM PST 24 |
| Finished | Mar 05 01:26:17 PM PST 24 |
| Peak memory | 358964 kb |
| Host | smart-4b8a4cf8-fe26-43cb-b28c-85891229dcc8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107180944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.1107180944 |
| Directory | /workspace/9.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3177169170 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2500344143 ps |
| CPU time | 70.34 seconds |
| Started | Mar 05 01:24:46 PM PST 24 |
| Finished | Mar 05 01:25:57 PM PST 24 |
| Peak memory | 210944 kb |
| Host | smart-f1f07fe0-4233-477e-b1d1-cd4b9b076fa8 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177169170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.3177169170 |
| Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.2247974786 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 28695075882 ps |
| CPU time | 272.46 seconds |
| Started | Mar 05 01:24:41 PM PST 24 |
| Finished | Mar 05 01:29:13 PM PST 24 |
| Peak memory | 202856 kb |
| Host | smart-bc436727-9e50-4fa8-b477-96cc42befae3 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247974786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.2247974786 |
| Directory | /workspace/9.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.2582706645 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 82818294771 ps |
| CPU time | 874.86 seconds |
| Started | Mar 05 01:24:40 PM PST 24 |
| Finished | Mar 05 01:39:15 PM PST 24 |
| Peak memory | 378628 kb |
| Host | smart-abe785d1-389f-43cc-82f3-a7b0791661ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582706645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.2582706645 |
| Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.3556478303 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 14385986888 ps |
| CPU time | 123.42 seconds |
| Started | Mar 05 01:24:43 PM PST 24 |
| Finished | Mar 05 01:26:47 PM PST 24 |
| Peak memory | 348928 kb |
| Host | smart-ea800efe-84be-4bb8-9c36-53034d001ccf |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556478303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.3556478303 |
| Directory | /workspace/9.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4072874571 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 49742455789 ps |
| CPU time | 356.05 seconds |
| Started | Mar 05 01:24:27 PM PST 24 |
| Finished | Mar 05 01:30:29 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-4e64854d-ac2d-41fe-9f1d-111fd5ace644 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072874571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.4072874571 |
| Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.2824358195 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2413028447 ps |
| CPU time | 3.7 seconds |
| Started | Mar 05 01:24:37 PM PST 24 |
| Finished | Mar 05 01:24:41 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-0c7cf1e7-243f-459b-b0a8-2965f88a9029 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824358195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2824358195 |
| Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_regwen.740429072 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 6739617062 ps |
| CPU time | 203.59 seconds |
| Started | Mar 05 01:24:47 PM PST 24 |
| Finished | Mar 05 01:28:11 PM PST 24 |
| Peak memory | 359212 kb |
| Host | smart-b1877a84-a1d0-4dc2-85c8-304111e1a4d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740429072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.740429072 |
| Directory | /workspace/9.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_smoke.2064474156 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 370787132 ps |
| CPU time | 3.75 seconds |
| Started | Mar 05 01:24:45 PM PST 24 |
| Finished | Mar 05 01:24:49 PM PST 24 |
| Peak memory | 202784 kb |
| Host | smart-9ead4969-069e-4ad5-a03f-0279845641f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064474156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2064474156 |
| Directory | /workspace/9.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.4121525407 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1811513360771 ps |
| CPU time | 6711.17 seconds |
| Started | Mar 05 01:24:46 PM PST 24 |
| Finished | Mar 05 03:16:38 PM PST 24 |
| Peak memory | 376648 kb |
| Host | smart-88839ded-064c-4cf0-a1cd-c8a252621d26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121525407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.4121525407 |
| Directory | /workspace/9.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3472800616 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 791434834 ps |
| CPU time | 7.37 seconds |
| Started | Mar 05 01:24:39 PM PST 24 |
| Finished | Mar 05 01:24:47 PM PST 24 |
| Peak memory | 212112 kb |
| Host | smart-dc766b8c-e480-428c-9c21-fd6e9fbea810 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3472800616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3472800616 |
| Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1493260586 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 11978903574 ps |
| CPU time | 180.37 seconds |
| Started | Mar 05 01:24:28 PM PST 24 |
| Finished | Mar 05 01:27:28 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-b85cf4ed-b294-4f18-87fc-965999188d88 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493260586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.1493260586 |
| Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2551961870 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 1454706752 ps |
| CPU time | 19.85 seconds |
| Started | Mar 05 01:24:35 PM PST 24 |
| Finished | Mar 05 01:24:55 PM PST 24 |
| Peak memory | 261756 kb |
| Host | smart-4195abb1-78eb-4299-88da-647dcc4757d8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551961870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2551961870 |
| Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
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