| T542 |
/workspace/coverage/default/35.sram_ctrl_executable.2342083411 |
|
|
Mar 05 01:26:09 PM PST 24 |
Mar 05 01:42:24 PM PST 24 |
62458246498 ps |
| T543 |
/workspace/coverage/default/22.sram_ctrl_partial_access.3700819113 |
|
|
Mar 05 01:25:10 PM PST 24 |
Mar 05 01:26:05 PM PST 24 |
464376830 ps |
| T544 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.968809275 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:29:47 PM PST 24 |
55062998479 ps |
| T545 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4276028846 |
|
|
Mar 05 01:26:00 PM PST 24 |
Mar 05 01:33:47 PM PST 24 |
87193233506 ps |
| T546 |
/workspace/coverage/default/33.sram_ctrl_executable.1947266129 |
|
|
Mar 05 01:25:59 PM PST 24 |
Mar 05 01:37:13 PM PST 24 |
44423046516 ps |
| T547 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2945041312 |
|
|
Mar 05 01:25:58 PM PST 24 |
Mar 05 01:26:06 PM PST 24 |
2692944650 ps |
| T548 |
/workspace/coverage/default/45.sram_ctrl_executable.3299129107 |
|
|
Mar 05 01:27:22 PM PST 24 |
Mar 05 01:34:52 PM PST 24 |
69856216819 ps |
| T549 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1403641830 |
|
|
Mar 05 01:26:35 PM PST 24 |
Mar 05 01:26:39 PM PST 24 |
5612777867 ps |
| T550 |
/workspace/coverage/default/8.sram_ctrl_stress_all.4200790568 |
|
|
Mar 05 01:24:40 PM PST 24 |
Mar 05 02:18:29 PM PST 24 |
89911002935 ps |
| T551 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2320624428 |
|
|
Mar 05 01:24:37 PM PST 24 |
Mar 05 01:25:00 PM PST 24 |
2614575180 ps |
| T552 |
/workspace/coverage/default/38.sram_ctrl_stress_all.67666522 |
|
|
Mar 05 01:26:28 PM PST 24 |
Mar 05 01:55:27 PM PST 24 |
41058892868 ps |
| T553 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2222901800 |
|
|
Mar 05 01:24:12 PM PST 24 |
Mar 05 01:29:20 PM PST 24 |
6589260421 ps |
| T554 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2330486660 |
|
|
Mar 05 01:27:47 PM PST 24 |
Mar 05 01:27:48 PM PST 24 |
18970568 ps |
| T555 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.2097579827 |
|
|
Mar 05 01:25:17 PM PST 24 |
Mar 05 01:25:21 PM PST 24 |
1405085326 ps |
| T556 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.933901465 |
|
|
Mar 05 01:27:55 PM PST 24 |
Mar 05 01:29:07 PM PST 24 |
2456131374 ps |
| T557 |
/workspace/coverage/default/16.sram_ctrl_smoke.153220162 |
|
|
Mar 05 01:24:58 PM PST 24 |
Mar 05 01:25:52 PM PST 24 |
2819118892 ps |
| T558 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.662442195 |
|
|
Mar 05 01:27:53 PM PST 24 |
Mar 05 01:27:56 PM PST 24 |
690303350 ps |
| T559 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.801718233 |
|
|
Mar 05 01:25:10 PM PST 24 |
Mar 05 01:26:09 PM PST 24 |
5166504172 ps |
| T560 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.723065715 |
|
|
Mar 05 01:25:06 PM PST 24 |
Mar 05 01:25:42 PM PST 24 |
2744043840 ps |
| T561 |
/workspace/coverage/default/17.sram_ctrl_executable.4208285915 |
|
|
Mar 05 01:25:03 PM PST 24 |
Mar 05 01:37:07 PM PST 24 |
17364816494 ps |
| T562 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.3262392597 |
|
|
Mar 05 01:26:00 PM PST 24 |
Mar 05 01:33:37 PM PST 24 |
5606697484 ps |
| T563 |
/workspace/coverage/default/39.sram_ctrl_partial_access.3375395751 |
|
|
Mar 05 01:26:30 PM PST 24 |
Mar 05 01:26:35 PM PST 24 |
386563967 ps |
| T564 |
/workspace/coverage/default/8.sram_ctrl_partial_access.615779399 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:25:24 PM PST 24 |
494341957 ps |
| T565 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1501549356 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:24:41 PM PST 24 |
3585919534 ps |
| T566 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.2286240058 |
|
|
Mar 05 01:25:15 PM PST 24 |
Mar 05 01:38:39 PM PST 24 |
5006159241 ps |
| T567 |
/workspace/coverage/default/49.sram_ctrl_alert_test.2057200870 |
|
|
Mar 05 01:27:53 PM PST 24 |
Mar 05 01:27:53 PM PST 24 |
62116121 ps |
| T568 |
/workspace/coverage/default/36.sram_ctrl_executable.303198727 |
|
|
Mar 05 01:26:18 PM PST 24 |
Mar 05 01:39:29 PM PST 24 |
43714746859 ps |
| T569 |
/workspace/coverage/default/31.sram_ctrl_alert_test.3933495679 |
|
|
Mar 05 01:25:48 PM PST 24 |
Mar 05 01:25:49 PM PST 24 |
54681909 ps |
| T570 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.566089068 |
|
|
Mar 05 01:27:31 PM PST 24 |
Mar 05 01:42:29 PM PST 24 |
70960588349 ps |
| T571 |
/workspace/coverage/default/0.sram_ctrl_smoke.577593859 |
|
|
Mar 05 01:24:31 PM PST 24 |
Mar 05 01:26:03 PM PST 24 |
1189597884 ps |
| T572 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.4125519266 |
|
|
Mar 05 01:24:58 PM PST 24 |
Mar 05 01:26:11 PM PST 24 |
1520936769 ps |
| T573 |
/workspace/coverage/default/20.sram_ctrl_regwen.169026701 |
|
|
Mar 05 01:24:59 PM PST 24 |
Mar 05 01:35:36 PM PST 24 |
8397227547 ps |
| T574 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.665887058 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 01:24:29 PM PST 24 |
1612047526 ps |
| T575 |
/workspace/coverage/default/29.sram_ctrl_executable.504778116 |
|
|
Mar 05 01:25:34 PM PST 24 |
Mar 05 01:47:03 PM PST 24 |
16199387565 ps |
| T576 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2850562867 |
|
|
Mar 05 01:25:06 PM PST 24 |
Mar 05 01:25:10 PM PST 24 |
1534473696 ps |
| T577 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2018451288 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:27:10 PM PST 24 |
11178484103 ps |
| T578 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3304264520 |
|
|
Mar 05 01:25:57 PM PST 24 |
Mar 05 01:28:29 PM PST 24 |
864682596 ps |
| T579 |
/workspace/coverage/default/32.sram_ctrl_bijection.160547121 |
|
|
Mar 05 01:25:57 PM PST 24 |
Mar 05 01:53:24 PM PST 24 |
126122456744 ps |
| T580 |
/workspace/coverage/default/39.sram_ctrl_stress_all.3115274863 |
|
|
Mar 05 01:26:36 PM PST 24 |
Mar 05 02:05:50 PM PST 24 |
89714130125 ps |
| T581 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.3185385309 |
|
|
Mar 05 01:25:06 PM PST 24 |
Mar 05 01:25:10 PM PST 24 |
1202652827 ps |
| T582 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2569348303 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:25:15 PM PST 24 |
24978712 ps |
| T583 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2439397558 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 01:33:14 PM PST 24 |
48127647759 ps |
| T584 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.912112421 |
|
|
Mar 05 01:27:38 PM PST 24 |
Mar 05 01:31:50 PM PST 24 |
4028326181 ps |
| T585 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3494602836 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 01:24:30 PM PST 24 |
1508609977 ps |
| T586 |
/workspace/coverage/default/43.sram_ctrl_smoke.1889872215 |
|
|
Mar 05 01:26:58 PM PST 24 |
Mar 05 01:27:18 PM PST 24 |
1821395167 ps |
| T587 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1782811667 |
|
|
Mar 05 01:26:59 PM PST 24 |
Mar 05 01:52:05 PM PST 24 |
85342213126 ps |
| T588 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3253887160 |
|
|
Mar 05 01:26:07 PM PST 24 |
Mar 05 01:27:12 PM PST 24 |
3790251487 ps |
| T589 |
/workspace/coverage/default/38.sram_ctrl_bijection.4139523504 |
|
|
Mar 05 01:26:28 PM PST 24 |
Mar 05 01:48:44 PM PST 24 |
72612809173 ps |
| T590 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3123206674 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:24:31 PM PST 24 |
693885892 ps |
| T591 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.194027357 |
|
|
Mar 05 01:25:32 PM PST 24 |
Mar 05 01:36:08 PM PST 24 |
12574440301 ps |
| T592 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2552991242 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 01:29:31 PM PST 24 |
24025052654 ps |
| T593 |
/workspace/coverage/default/0.sram_ctrl_bijection.2988148293 |
|
|
Mar 05 01:24:19 PM PST 24 |
Mar 05 01:51:40 PM PST 24 |
113101235536 ps |
| T594 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2208152755 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:24:37 PM PST 24 |
1005972362 ps |
| T595 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1152283517 |
|
|
Mar 05 01:24:12 PM PST 24 |
Mar 05 01:29:22 PM PST 24 |
20854662185 ps |
| T596 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.289276876 |
|
|
Mar 05 01:26:43 PM PST 24 |
Mar 05 01:32:25 PM PST 24 |
15627811898 ps |
| T597 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2809025422 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:31:25 PM PST 24 |
62946860728 ps |
| T598 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1660202583 |
|
|
Mar 05 01:26:50 PM PST 24 |
Mar 05 01:34:50 PM PST 24 |
128320280853 ps |
| T599 |
/workspace/coverage/default/23.sram_ctrl_bijection.2565541519 |
|
|
Mar 05 01:25:15 PM PST 24 |
Mar 05 01:58:37 PM PST 24 |
29248149054 ps |
| T600 |
/workspace/coverage/default/34.sram_ctrl_stress_all.652976197 |
|
|
Mar 05 01:26:07 PM PST 24 |
Mar 05 03:39:34 PM PST 24 |
604950406325 ps |
| T601 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.1010667781 |
|
|
Mar 05 01:25:15 PM PST 24 |
Mar 05 01:25:51 PM PST 24 |
5592972292 ps |
| T602 |
/workspace/coverage/default/15.sram_ctrl_regwen.823523588 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:44:20 PM PST 24 |
3151034504 ps |
| T603 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2319395727 |
|
|
Mar 05 01:25:48 PM PST 24 |
Mar 05 01:27:04 PM PST 24 |
9808695463 ps |
| T604 |
/workspace/coverage/default/2.sram_ctrl_regwen.3769416114 |
|
|
Mar 05 01:24:18 PM PST 24 |
Mar 05 01:38:17 PM PST 24 |
55330360757 ps |
| T605 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.2374844874 |
|
|
Mar 05 01:26:27 PM PST 24 |
Mar 05 01:26:37 PM PST 24 |
693052960 ps |
| T606 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1465412185 |
|
|
Mar 05 01:26:44 PM PST 24 |
Mar 05 01:30:10 PM PST 24 |
10093082271 ps |
| T607 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.2247974786 |
|
|
Mar 05 01:24:41 PM PST 24 |
Mar 05 01:29:13 PM PST 24 |
28695075882 ps |
| T608 |
/workspace/coverage/default/14.sram_ctrl_executable.852711929 |
|
|
Mar 05 01:25:11 PM PST 24 |
Mar 05 01:34:56 PM PST 24 |
7102945413 ps |
| T609 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.1043800147 |
|
|
Mar 05 01:25:15 PM PST 24 |
Mar 05 01:27:32 PM PST 24 |
31832447541 ps |
| T610 |
/workspace/coverage/default/13.sram_ctrl_smoke.3985334645 |
|
|
Mar 05 01:24:47 PM PST 24 |
Mar 05 01:25:20 PM PST 24 |
3985451553 ps |
| T611 |
/workspace/coverage/default/7.sram_ctrl_regwen.3214360924 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:30:39 PM PST 24 |
8268555719 ps |
| T612 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.4170562367 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:27:45 PM PST 24 |
19031745744 ps |
| T613 |
/workspace/coverage/default/32.sram_ctrl_smoke.508757956 |
|
|
Mar 05 01:25:49 PM PST 24 |
Mar 05 01:26:08 PM PST 24 |
2026221883 ps |
| T614 |
/workspace/coverage/default/47.sram_ctrl_smoke.1934933199 |
|
|
Mar 05 01:27:30 PM PST 24 |
Mar 05 01:27:34 PM PST 24 |
392860228 ps |
| T615 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3102206567 |
|
|
Mar 05 01:26:30 PM PST 24 |
Mar 05 01:33:24 PM PST 24 |
6906981403 ps |
| T616 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.576453746 |
|
|
Mar 05 01:26:09 PM PST 24 |
Mar 05 01:31:14 PM PST 24 |
55096558034 ps |
| T617 |
/workspace/coverage/default/32.sram_ctrl_stress_all.328673569 |
|
|
Mar 05 01:25:59 PM PST 24 |
Mar 05 03:25:33 PM PST 24 |
170110067001 ps |
| T618 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3061789943 |
|
|
Mar 05 01:25:30 PM PST 24 |
Mar 05 01:28:25 PM PST 24 |
10987067374 ps |
| T619 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2497330272 |
|
|
Mar 05 01:26:14 PM PST 24 |
Mar 05 01:26:49 PM PST 24 |
3697613992 ps |
| T620 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.3002540534 |
|
|
Mar 05 01:25:32 PM PST 24 |
Mar 05 01:27:32 PM PST 24 |
7898714756 ps |
| T621 |
/workspace/coverage/default/32.sram_ctrl_alert_test.596622827 |
|
|
Mar 05 01:25:58 PM PST 24 |
Mar 05 01:25:59 PM PST 24 |
13860453 ps |
| T622 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2266109534 |
|
|
Mar 05 01:24:46 PM PST 24 |
Mar 05 01:32:29 PM PST 24 |
19608837743 ps |
| T623 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2678447366 |
|
|
Mar 05 01:24:32 PM PST 24 |
Mar 05 01:29:18 PM PST 24 |
8157185898 ps |
| T624 |
/workspace/coverage/default/27.sram_ctrl_alert_test.4018782780 |
|
|
Mar 05 01:25:36 PM PST 24 |
Mar 05 01:25:37 PM PST 24 |
11823937 ps |
| T625 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1090289940 |
|
|
Mar 05 01:24:23 PM PST 24 |
Mar 05 01:25:09 PM PST 24 |
1490662438 ps |
| T626 |
/workspace/coverage/default/13.sram_ctrl_bijection.2382140551 |
|
|
Mar 05 01:24:45 PM PST 24 |
Mar 05 01:57:01 PM PST 24 |
87521523357 ps |
| T627 |
/workspace/coverage/default/16.sram_ctrl_executable.1389150705 |
|
|
Mar 05 01:25:00 PM PST 24 |
Mar 05 01:41:07 PM PST 24 |
7800947483 ps |
| T628 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.525243232 |
|
|
Mar 05 01:26:06 PM PST 24 |
Mar 05 01:26:17 PM PST 24 |
716577767 ps |
| T106 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.697152367 |
|
|
Mar 05 01:26:42 PM PST 24 |
Mar 05 01:27:26 PM PST 24 |
7268574329 ps |
| T629 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1806770651 |
|
|
Mar 05 01:24:38 PM PST 24 |
Mar 05 01:40:18 PM PST 24 |
24434733964 ps |
| T630 |
/workspace/coverage/default/31.sram_ctrl_regwen.4618279 |
|
|
Mar 05 01:25:46 PM PST 24 |
Mar 05 01:49:11 PM PST 24 |
75885954604 ps |
| T631 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2519993022 |
|
|
Mar 05 01:27:30 PM PST 24 |
Mar 05 01:27:43 PM PST 24 |
5328583371 ps |
| T632 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.3144960093 |
|
|
Mar 05 01:26:43 PM PST 24 |
Mar 05 01:27:05 PM PST 24 |
1439514940 ps |
| T633 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2202376174 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:26:32 PM PST 24 |
2673961001 ps |
| T634 |
/workspace/coverage/default/43.sram_ctrl_executable.3316935396 |
|
|
Mar 05 01:27:10 PM PST 24 |
Mar 05 01:36:07 PM PST 24 |
76709525100 ps |
| T635 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3675936586 |
|
|
Mar 05 01:25:10 PM PST 24 |
Mar 05 01:25:37 PM PST 24 |
1692393063 ps |
| T636 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1920652104 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:28:03 PM PST 24 |
5890856866 ps |
| T637 |
/workspace/coverage/default/12.sram_ctrl_smoke.1928950959 |
|
|
Mar 05 01:24:36 PM PST 24 |
Mar 05 01:26:27 PM PST 24 |
995306225 ps |
| T638 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.1734680883 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:29:11 PM PST 24 |
4367017094 ps |
| T639 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2240336900 |
|
|
Mar 05 01:25:02 PM PST 24 |
Mar 05 01:25:27 PM PST 24 |
3387941870 ps |
| T640 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3645608516 |
|
|
Mar 05 01:24:29 PM PST 24 |
Mar 05 01:24:43 PM PST 24 |
432461221 ps |
| T641 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3932014159 |
|
|
Mar 05 01:24:41 PM PST 24 |
Mar 05 01:25:21 PM PST 24 |
1863305331 ps |
| T642 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2064480602 |
|
|
Mar 05 01:25:46 PM PST 24 |
Mar 05 01:34:08 PM PST 24 |
48488961476 ps |
| T33 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.3801244234 |
|
|
Mar 05 01:24:15 PM PST 24 |
Mar 05 01:24:17 PM PST 24 |
122802071 ps |
| T643 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.809696867 |
|
|
Mar 05 01:25:03 PM PST 24 |
Mar 05 01:31:39 PM PST 24 |
26454717401 ps |
| T644 |
/workspace/coverage/default/29.sram_ctrl_regwen.2273645976 |
|
|
Mar 05 01:25:38 PM PST 24 |
Mar 05 01:39:32 PM PST 24 |
43777121365 ps |
| T645 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3297815394 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:25:03 PM PST 24 |
20861277 ps |
| T646 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3121813244 |
|
|
Mar 05 01:24:44 PM PST 24 |
Mar 05 01:29:15 PM PST 24 |
51736584749 ps |
| T647 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2327277467 |
|
|
Mar 05 01:25:37 PM PST 24 |
Mar 05 01:25:44 PM PST 24 |
2767247231 ps |
| T648 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.94092149 |
|
|
Mar 05 01:26:45 PM PST 24 |
Mar 05 01:29:53 PM PST 24 |
12350456562 ps |
| T649 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1606783666 |
|
|
Mar 05 01:27:45 PM PST 24 |
Mar 05 01:32:27 PM PST 24 |
19398983174 ps |
| T650 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1269846898 |
|
|
Mar 05 01:25:49 PM PST 24 |
Mar 05 01:33:37 PM PST 24 |
45792479816 ps |
| T651 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1469537854 |
|
|
Mar 05 01:24:41 PM PST 24 |
Mar 05 01:24:45 PM PST 24 |
1607704504 ps |
| T652 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1315414377 |
|
|
Mar 05 01:27:39 PM PST 24 |
Mar 05 01:30:52 PM PST 24 |
14205654003 ps |
| T653 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.1023702304 |
|
|
Mar 05 01:24:59 PM PST 24 |
Mar 05 01:27:33 PM PST 24 |
20329240683 ps |
| T654 |
/workspace/coverage/default/10.sram_ctrl_executable.765400056 |
|
|
Mar 05 01:24:32 PM PST 24 |
Mar 05 01:38:08 PM PST 24 |
14462726457 ps |
| T655 |
/workspace/coverage/default/40.sram_ctrl_partial_access.2441264882 |
|
|
Mar 05 01:26:35 PM PST 24 |
Mar 05 01:26:54 PM PST 24 |
2256871453 ps |
| T656 |
/workspace/coverage/default/13.sram_ctrl_stress_all.943093668 |
|
|
Mar 05 01:24:38 PM PST 24 |
Mar 05 02:14:16 PM PST 24 |
202372622202 ps |
| T657 |
/workspace/coverage/default/14.sram_ctrl_smoke.3824667194 |
|
|
Mar 05 01:24:46 PM PST 24 |
Mar 05 01:25:07 PM PST 24 |
3556474734 ps |
| T658 |
/workspace/coverage/default/29.sram_ctrl_alert_test.406434301 |
|
|
Mar 05 01:25:39 PM PST 24 |
Mar 05 01:25:40 PM PST 24 |
111088385 ps |
| T659 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2867572667 |
|
|
Mar 05 01:26:17 PM PST 24 |
Mar 05 01:44:34 PM PST 24 |
86109810483 ps |
| T660 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3700684444 |
|
|
Mar 05 01:25:16 PM PST 24 |
Mar 05 01:26:15 PM PST 24 |
5264464627 ps |
| T661 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3695231009 |
|
|
Mar 05 01:24:54 PM PST 24 |
Mar 05 01:29:48 PM PST 24 |
14064796309 ps |
| T662 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.4231547504 |
|
|
Mar 05 01:25:47 PM PST 24 |
Mar 05 01:29:56 PM PST 24 |
4144655017 ps |
| T663 |
/workspace/coverage/default/7.sram_ctrl_executable.852405330 |
|
|
Mar 05 01:24:30 PM PST 24 |
Mar 05 01:49:17 PM PST 24 |
26298318271 ps |
| T664 |
/workspace/coverage/default/18.sram_ctrl_executable.3136189426 |
|
|
Mar 05 01:25:07 PM PST 24 |
Mar 05 01:34:54 PM PST 24 |
16691177111 ps |
| T665 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3653029492 |
|
|
Mar 05 01:24:30 PM PST 24 |
Mar 05 01:28:40 PM PST 24 |
4148889612 ps |
| T666 |
/workspace/coverage/default/49.sram_ctrl_smoke.3063831322 |
|
|
Mar 05 01:27:47 PM PST 24 |
Mar 05 01:28:00 PM PST 24 |
5439518787 ps |
| T667 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3447225696 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:27:21 PM PST 24 |
764580709 ps |
| T668 |
/workspace/coverage/default/0.sram_ctrl_executable.2623836770 |
|
|
Mar 05 01:24:29 PM PST 24 |
Mar 05 01:28:15 PM PST 24 |
4675026476 ps |
| T669 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.1962605698 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:25:26 PM PST 24 |
686431319 ps |
| T670 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.4096906056 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 01:25:19 PM PST 24 |
1398900540 ps |
| T671 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2551961870 |
|
|
Mar 05 01:24:35 PM PST 24 |
Mar 05 01:24:55 PM PST 24 |
1454706752 ps |
| T672 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2086441256 |
|
|
Mar 05 01:25:18 PM PST 24 |
Mar 05 01:25:44 PM PST 24 |
7222647591 ps |
| T673 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2801987115 |
|
|
Mar 05 01:24:40 PM PST 24 |
Mar 05 01:24:43 PM PST 24 |
443128032 ps |
| T674 |
/workspace/coverage/default/41.sram_ctrl_regwen.2171404789 |
|
|
Mar 05 01:26:48 PM PST 24 |
Mar 05 01:34:28 PM PST 24 |
14267140864 ps |
| T675 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1908921435 |
|
|
Mar 05 01:25:28 PM PST 24 |
Mar 05 01:26:45 PM PST 24 |
791755703 ps |
| T676 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.3055221369 |
|
|
Mar 05 01:25:18 PM PST 24 |
Mar 05 01:29:15 PM PST 24 |
30088809911 ps |
| T677 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.3103019293 |
|
|
Mar 05 01:25:40 PM PST 24 |
Mar 05 01:26:58 PM PST 24 |
10628947241 ps |
| T678 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1911455075 |
|
|
Mar 05 01:27:39 PM PST 24 |
Mar 05 01:32:32 PM PST 24 |
5298248553 ps |
| T679 |
/workspace/coverage/default/8.sram_ctrl_smoke.3580220053 |
|
|
Mar 05 01:24:29 PM PST 24 |
Mar 05 01:25:28 PM PST 24 |
4345226864 ps |
| T680 |
/workspace/coverage/default/28.sram_ctrl_regwen.3811152971 |
|
|
Mar 05 01:25:29 PM PST 24 |
Mar 05 01:36:09 PM PST 24 |
7762618028 ps |
| T681 |
/workspace/coverage/default/48.sram_ctrl_executable.2185207394 |
|
|
Mar 05 01:27:47 PM PST 24 |
Mar 05 01:51:33 PM PST 24 |
27273150711 ps |
| T682 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.4019671768 |
|
|
Mar 05 01:25:05 PM PST 24 |
Mar 05 01:28:54 PM PST 24 |
18766660772 ps |
| T683 |
/workspace/coverage/default/45.sram_ctrl_regwen.1483678654 |
|
|
Mar 05 01:27:23 PM PST 24 |
Mar 05 01:27:56 PM PST 24 |
3718075508 ps |
| T684 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2654718673 |
|
|
Mar 05 01:25:00 PM PST 24 |
Mar 05 01:30:02 PM PST 24 |
19475864946 ps |
| T685 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2369719209 |
|
|
Mar 05 01:26:49 PM PST 24 |
Mar 05 01:29:23 PM PST 24 |
21066273047 ps |
| T686 |
/workspace/coverage/default/20.sram_ctrl_stress_all.3967709326 |
|
|
Mar 05 01:25:12 PM PST 24 |
Mar 05 02:15:12 PM PST 24 |
185661008520 ps |
| T687 |
/workspace/coverage/default/31.sram_ctrl_smoke.508593442 |
|
|
Mar 05 01:25:47 PM PST 24 |
Mar 05 01:27:12 PM PST 24 |
877650592 ps |
| T688 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3035290360 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:27:07 PM PST 24 |
553748073 ps |
| T689 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.4136426546 |
|
|
Mar 05 01:25:12 PM PST 24 |
Mar 05 01:26:56 PM PST 24 |
768406735 ps |
| T690 |
/workspace/coverage/default/6.sram_ctrl_regwen.1703867774 |
|
|
Mar 05 01:25:39 PM PST 24 |
Mar 05 01:45:24 PM PST 24 |
49814680198 ps |
| T691 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1103643616 |
|
|
Mar 05 01:25:15 PM PST 24 |
Mar 05 01:33:41 PM PST 24 |
358019715234 ps |
| T692 |
/workspace/coverage/default/15.sram_ctrl_bijection.2261784413 |
|
|
Mar 05 01:24:59 PM PST 24 |
Mar 05 01:41:40 PM PST 24 |
15394655638 ps |
| T693 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2114607062 |
|
|
Mar 05 01:24:58 PM PST 24 |
Mar 05 01:25:38 PM PST 24 |
1778300624 ps |
| T694 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.2156808216 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:25:27 PM PST 24 |
869736576 ps |
| T695 |
/workspace/coverage/default/24.sram_ctrl_executable.1168055658 |
|
|
Mar 05 01:25:17 PM PST 24 |
Mar 05 01:48:01 PM PST 24 |
254009749939 ps |
| T696 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.4140121476 |
|
|
Mar 05 01:27:31 PM PST 24 |
Mar 05 01:29:53 PM PST 24 |
800769556 ps |
| T697 |
/workspace/coverage/default/11.sram_ctrl_alert_test.3366116642 |
|
|
Mar 05 01:24:33 PM PST 24 |
Mar 05 01:24:33 PM PST 24 |
22791435 ps |
| T698 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.263126944 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:26:05 PM PST 24 |
3005655331 ps |
| T699 |
/workspace/coverage/default/40.sram_ctrl_smoke.2845316768 |
|
|
Mar 05 01:26:32 PM PST 24 |
Mar 05 01:26:45 PM PST 24 |
1696851161 ps |
| T700 |
/workspace/coverage/default/14.sram_ctrl_bijection.3976726548 |
|
|
Mar 05 01:24:58 PM PST 24 |
Mar 05 01:49:57 PM PST 24 |
460878568919 ps |
| T701 |
/workspace/coverage/default/19.sram_ctrl_executable.216045081 |
|
|
Mar 05 01:25:12 PM PST 24 |
Mar 05 01:30:11 PM PST 24 |
29995943049 ps |
| T702 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.2807121386 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:37:00 PM PST 24 |
100762642347 ps |
| T703 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3669886830 |
|
|
Mar 05 01:26:39 PM PST 24 |
Mar 05 01:30:04 PM PST 24 |
6780553224 ps |
| T704 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3702852480 |
|
|
Mar 05 01:25:03 PM PST 24 |
Mar 05 01:26:20 PM PST 24 |
2441366882 ps |
| T705 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2294609532 |
|
|
Mar 05 01:25:40 PM PST 24 |
Mar 05 01:26:41 PM PST 24 |
3102481341 ps |
| T706 |
/workspace/coverage/default/33.sram_ctrl_bijection.3623034608 |
|
|
Mar 05 01:26:00 PM PST 24 |
Mar 05 01:47:12 PM PST 24 |
19309019623 ps |
| T707 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2084225606 |
|
|
Mar 05 01:24:59 PM PST 24 |
Mar 05 01:31:29 PM PST 24 |
36878782473 ps |
| T708 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1423824572 |
|
|
Mar 05 01:25:19 PM PST 24 |
Mar 05 01:25:24 PM PST 24 |
4808718931 ps |
| T709 |
/workspace/coverage/default/25.sram_ctrl_bijection.2773565278 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:54:37 PM PST 24 |
78891636300 ps |
| T710 |
/workspace/coverage/default/21.sram_ctrl_bijection.598983751 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:58:14 PM PST 24 |
331607553698 ps |
| T711 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1373972088 |
|
|
Mar 05 01:26:50 PM PST 24 |
Mar 05 01:26:51 PM PST 24 |
39760551 ps |
| T712 |
/workspace/coverage/default/5.sram_ctrl_alert_test.4249290465 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 01:24:26 PM PST 24 |
12236562 ps |
| T713 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3349059921 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:27:13 PM PST 24 |
803032509 ps |
| T714 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.709311043 |
|
|
Mar 05 01:25:25 PM PST 24 |
Mar 05 01:30:40 PM PST 24 |
55542902561 ps |
| T715 |
/workspace/coverage/default/36.sram_ctrl_smoke.2530343040 |
|
|
Mar 05 01:26:18 PM PST 24 |
Mar 05 01:26:24 PM PST 24 |
967534780 ps |
| T716 |
/workspace/coverage/default/22.sram_ctrl_bijection.2304876169 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:55:49 PM PST 24 |
27663212024 ps |
| T717 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.2776924353 |
|
|
Mar 05 01:25:24 PM PST 24 |
Mar 05 01:31:45 PM PST 24 |
36407984043 ps |
| T718 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.113623788 |
|
|
Mar 05 01:26:24 PM PST 24 |
Mar 05 01:26:51 PM PST 24 |
773595244 ps |
| T719 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3623852675 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 01:24:27 PM PST 24 |
26597615 ps |
| T720 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3944568640 |
|
|
Mar 05 01:25:12 PM PST 24 |
Mar 05 01:27:52 PM PST 24 |
72189731766 ps |
| T721 |
/workspace/coverage/default/3.sram_ctrl_stress_all.2877608164 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 02:51:59 PM PST 24 |
1511472939610 ps |
| T722 |
/workspace/coverage/default/3.sram_ctrl_alert_test.2120228910 |
|
|
Mar 05 01:24:35 PM PST 24 |
Mar 05 01:24:36 PM PST 24 |
31737328 ps |
| T723 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.1630821821 |
|
|
Mar 05 01:24:59 PM PST 24 |
Mar 05 01:45:19 PM PST 24 |
72002976682 ps |
| T724 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.1107180944 |
|
|
Mar 05 01:24:37 PM PST 24 |
Mar 05 01:26:17 PM PST 24 |
794826715 ps |
| T725 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1391263690 |
|
|
Mar 05 01:24:49 PM PST 24 |
Mar 05 01:29:46 PM PST 24 |
22914043329 ps |
| T726 |
/workspace/coverage/default/26.sram_ctrl_smoke.334248139 |
|
|
Mar 05 01:25:32 PM PST 24 |
Mar 05 01:25:41 PM PST 24 |
1839673857 ps |
| T727 |
/workspace/coverage/default/12.sram_ctrl_executable.3419423155 |
|
|
Mar 05 01:24:55 PM PST 24 |
Mar 05 01:38:41 PM PST 24 |
33201486180 ps |
| T728 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1493260586 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:27:28 PM PST 24 |
11978903574 ps |
| T729 |
/workspace/coverage/default/6.sram_ctrl_partial_access.2838660494 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:24:35 PM PST 24 |
370763941 ps |
| T730 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.3365074737 |
|
|
Mar 05 01:24:33 PM PST 24 |
Mar 05 01:36:20 PM PST 24 |
15586769748 ps |
| T731 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1223285454 |
|
|
Mar 05 01:26:18 PM PST 24 |
Mar 05 02:52:51 PM PST 24 |
805286361320 ps |
| T732 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3884578056 |
|
|
Mar 05 01:25:11 PM PST 24 |
Mar 05 01:44:20 PM PST 24 |
34447478552 ps |
| T733 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.3518085840 |
|
|
Mar 05 01:26:14 PM PST 24 |
Mar 05 01:33:58 PM PST 24 |
17747769848 ps |
| T734 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.1287640658 |
|
|
Mar 05 01:24:40 PM PST 24 |
Mar 05 01:24:43 PM PST 24 |
362381125 ps |
| T735 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.2555678102 |
|
|
Mar 05 01:25:00 PM PST 24 |
Mar 05 01:29:17 PM PST 24 |
8040425228 ps |
| T736 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.341746294 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:25:24 PM PST 24 |
2749256035 ps |
| T737 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2859496688 |
|
|
Mar 05 01:25:58 PM PST 24 |
Mar 05 01:26:34 PM PST 24 |
21912264253 ps |
| T738 |
/workspace/coverage/default/29.sram_ctrl_smoke.956721508 |
|
|
Mar 05 01:25:31 PM PST 24 |
Mar 05 01:25:39 PM PST 24 |
1079661615 ps |
| T739 |
/workspace/coverage/default/22.sram_ctrl_regwen.2596182237 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:30:47 PM PST 24 |
17374316194 ps |
| T740 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4011213101 |
|
|
Mar 05 01:26:59 PM PST 24 |
Mar 05 01:33:32 PM PST 24 |
64597281478 ps |
| T741 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.2553381261 |
|
|
Mar 05 01:26:06 PM PST 24 |
Mar 05 01:28:48 PM PST 24 |
42976510861 ps |
| T742 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1664518221 |
|
|
Mar 05 01:26:20 PM PST 24 |
Mar 05 01:26:23 PM PST 24 |
377961485 ps |
| T743 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.1354975326 |
|
|
Mar 05 01:26:30 PM PST 24 |
Mar 05 01:29:02 PM PST 24 |
43046394459 ps |
| T744 |
/workspace/coverage/default/35.sram_ctrl_bijection.4013899477 |
|
|
Mar 05 01:26:10 PM PST 24 |
Mar 05 01:52:15 PM PST 24 |
69912100655 ps |
| T745 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.2052256143 |
|
|
Mar 05 01:24:44 PM PST 24 |
Mar 05 01:29:50 PM PST 24 |
108672495487 ps |
| T746 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.185632147 |
|
|
Mar 05 01:25:09 PM PST 24 |
Mar 05 01:26:47 PM PST 24 |
3229224868 ps |
| T747 |
/workspace/coverage/default/36.sram_ctrl_bijection.1221123771 |
|
|
Mar 05 01:26:18 PM PST 24 |
Mar 05 02:13:05 PM PST 24 |
718398633472 ps |
| T748 |
/workspace/coverage/default/46.sram_ctrl_smoke.4175769443 |
|
|
Mar 05 01:27:23 PM PST 24 |
Mar 05 01:29:48 PM PST 24 |
3751802557 ps |
| T749 |
/workspace/coverage/default/44.sram_ctrl_partial_access.1562744553 |
|
|
Mar 05 01:27:14 PM PST 24 |
Mar 05 01:27:37 PM PST 24 |
1657195634 ps |
| T750 |
/workspace/coverage/default/43.sram_ctrl_regwen.3934867026 |
|
|
Mar 05 01:27:07 PM PST 24 |
Mar 05 01:52:34 PM PST 24 |
24122642634 ps |
| T751 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.20233697 |
|
|
Mar 05 01:24:42 PM PST 24 |
Mar 05 01:24:48 PM PST 24 |
357787123 ps |
| T752 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3096652408 |
|
|
Mar 05 01:24:30 PM PST 24 |
Mar 05 01:29:41 PM PST 24 |
13476837719 ps |
| T753 |
/workspace/coverage/default/23.sram_ctrl_smoke.2098085562 |
|
|
Mar 05 01:25:19 PM PST 24 |
Mar 05 01:25:36 PM PST 24 |
902846403 ps |
| T754 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.387168163 |
|
|
Mar 05 01:26:26 PM PST 24 |
Mar 05 01:27:45 PM PST 24 |
5025994108 ps |
| T755 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.415436203 |
|
|
Mar 05 01:24:57 PM PST 24 |
Mar 05 01:27:25 PM PST 24 |
2832312319 ps |
| T756 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.4246320126 |
|
|
Mar 05 01:25:46 PM PST 24 |
Mar 05 01:30:38 PM PST 24 |
29088568327 ps |
| T757 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3378357644 |
|
|
Mar 05 01:25:02 PM PST 24 |
Mar 05 01:31:50 PM PST 24 |
60792612545 ps |
| T758 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3933661368 |
|
|
Mar 05 01:27:07 PM PST 24 |
Mar 05 01:28:23 PM PST 24 |
5735345443 ps |
| T759 |
/workspace/coverage/default/8.sram_ctrl_executable.1445116844 |
|
|
Mar 05 01:24:30 PM PST 24 |
Mar 05 01:32:56 PM PST 24 |
19978191226 ps |
| T760 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.1498053824 |
|
|
Mar 05 01:26:22 PM PST 24 |
Mar 05 01:30:29 PM PST 24 |
15763178063 ps |
| T761 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.857809158 |
|
|
Mar 05 01:24:44 PM PST 24 |
Mar 05 01:28:09 PM PST 24 |
4756669097 ps |
| T762 |
/workspace/coverage/default/6.sram_ctrl_smoke.3702578740 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:24:45 PM PST 24 |
3921719507 ps |
| T763 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3177832637 |
|
|
Mar 05 01:25:35 PM PST 24 |
Mar 05 01:30:04 PM PST 24 |
22261268041 ps |
| T764 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.2748128269 |
|
|
Mar 05 01:24:23 PM PST 24 |
Mar 05 01:32:02 PM PST 24 |
43121040803 ps |
| T765 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.3294080568 |
|
|
Mar 05 01:26:26 PM PST 24 |
Mar 05 01:26:42 PM PST 24 |
1280066849 ps |
| T766 |
/workspace/coverage/default/42.sram_ctrl_alert_test.591258839 |
|
|
Mar 05 01:26:58 PM PST 24 |
Mar 05 01:27:00 PM PST 24 |
13910669 ps |
| T767 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3877211504 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:25:45 PM PST 24 |
2724042117 ps |
| T768 |
/workspace/coverage/default/11.sram_ctrl_smoke.3274384413 |
|
|
Mar 05 01:24:54 PM PST 24 |
Mar 05 01:25:01 PM PST 24 |
962961882 ps |
| T769 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.96738382 |
|
|
Mar 05 01:26:09 PM PST 24 |
Mar 05 01:29:52 PM PST 24 |
8992344511 ps |
| T770 |
/workspace/coverage/default/44.sram_ctrl_regwen.1410250663 |
|
|
Mar 05 01:27:14 PM PST 24 |
Mar 05 01:46:44 PM PST 24 |
48775469631 ps |
| T771 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3451936240 |
|
|
Mar 05 01:26:20 PM PST 24 |
Mar 05 01:28:12 PM PST 24 |
779178284 ps |
| T772 |
/workspace/coverage/default/16.sram_ctrl_regwen.84127582 |
|
|
Mar 05 01:24:58 PM PST 24 |
Mar 05 01:45:05 PM PST 24 |
31898922674 ps |
| T773 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.890702969 |
|
|
Mar 05 01:26:59 PM PST 24 |
Mar 05 01:27:04 PM PST 24 |
734484764 ps |
| T774 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.486700802 |
|
|
Mar 05 01:25:05 PM PST 24 |
Mar 05 01:26:42 PM PST 24 |
5764295935 ps |
| T775 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2456831670 |
|
|
Mar 05 01:26:09 PM PST 24 |
Mar 05 01:26:12 PM PST 24 |
361187088 ps |
| T776 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3189168907 |
|
|
Mar 05 01:24:43 PM PST 24 |
Mar 05 01:27:30 PM PST 24 |
2251814897 ps |
| T777 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2761415764 |
|
|
Mar 05 01:25:15 PM PST 24 |
Mar 05 01:25:16 PM PST 24 |
26163615 ps |
| T778 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1792133900 |
|
|
Mar 05 01:27:09 PM PST 24 |
Mar 05 02:41:43 PM PST 24 |
355454974296 ps |
| T779 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.181281878 |
|
|
Mar 05 01:26:19 PM PST 24 |
Mar 05 01:28:45 PM PST 24 |
16353835905 ps |
| T780 |
/workspace/coverage/default/26.sram_ctrl_partial_access.4258704379 |
|
|
Mar 05 01:25:22 PM PST 24 |
Mar 05 01:26:33 PM PST 24 |
2956643373 ps |
| T781 |
/workspace/coverage/default/37.sram_ctrl_smoke.1828390862 |
|
|
Mar 05 01:26:23 PM PST 24 |
Mar 05 01:26:36 PM PST 24 |
869769727 ps |
| T782 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.746212228 |
|
|
Mar 05 01:27:07 PM PST 24 |
Mar 05 01:28:33 PM PST 24 |
5759680909 ps |
| T783 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.823072835 |
|
|
Mar 05 01:25:03 PM PST 24 |
Mar 05 01:25:29 PM PST 24 |
757749978 ps |
| T784 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1861001265 |
|
|
Mar 05 01:27:39 PM PST 24 |
Mar 05 01:27:46 PM PST 24 |
2511387795 ps |
| T785 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1221316259 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:24:50 PM PST 24 |
716745383 ps |
| T786 |
/workspace/coverage/default/1.sram_ctrl_alert_test.2571482783 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:24:28 PM PST 24 |
37178862 ps |
| T787 |
/workspace/coverage/default/17.sram_ctrl_stress_all.902759532 |
|
|
Mar 05 01:25:10 PM PST 24 |
Mar 05 02:25:40 PM PST 24 |
402153434935 ps |
| T788 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.316588057 |
|
|
Mar 05 01:24:49 PM PST 24 |
Mar 05 01:24:56 PM PST 24 |
2814325674 ps |
| T789 |
/workspace/coverage/default/41.sram_ctrl_stress_all.1945514778 |
|
|
Mar 05 01:26:52 PM PST 24 |
Mar 05 02:49:09 PM PST 24 |
94294149755 ps |