SRAM_CTRL/MAIN Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.756m 1.564ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.740s 20.930us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 23.906us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.130s 345.941us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.710s 28.001us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.420s 6.900ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 23.906us 20 20 100.00
sram_ctrl_csr_aliasing 0.710s 28.001us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.770m 187.845ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.646m 19.815ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 36.767m 117.501ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.497m 13.592ms 50 50 100.00
V2 bijection sram_ctrl_bijection 46.975m 220.843ms 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 38.555m 17.504ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 34.526m 185.952ms 42 50 84.00
V2 executable sram_ctrl_executable 33.727m 24.940ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.299m 5.672ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.102m 37.489ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.769m 3.181ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.737m 3.321ms 50 50 100.00
V2 regwen sram_ctrl_regwen 29.264m 23.505ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.360s 6.684ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.961h 1.016s 40 50 80.00
V2 alert_test sram_ctrl_alert_test 0.700s 21.560us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.870s 574.026us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.870s 574.026us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.740s 20.930us 5 5 100.00
sram_ctrl_csr_rw 0.720s 23.906us 20 20 100.00
sram_ctrl_csr_aliasing 0.710s 28.001us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 28.824us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.740s 20.930us 5 5 100.00
sram_ctrl_csr_rw 0.720s 23.906us 20 20 100.00
sram_ctrl_csr_aliasing 0.710s 28.001us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 28.824us 20 20 100.00
V2 TOTAL 720 740 97.30
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 57.820s 44.021ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.270s 285.385us 5 5 100.00
sram_ctrl_tl_intg_err 2.960s 481.762us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.270s 285.385us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.960s 481.762us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 29.264m 23.505ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 23.906us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 33.727m 24.940ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 33.727m 24.940ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 33.727m 24.940ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 34.526m 185.952ms 42 50 84.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 57.820s 44.021ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.756m 1.564ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.756m 1.564ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 33.727m 24.940ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.270s 285.385us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 34.526m 185.952ms 42 50 84.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.270s 285.385us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.270s 285.385us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.756m 1.564ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.270s 285.385us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.181m 6.059ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1020 1040 98.08

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.41 100.00 97.91 100.00 100.00 99.72 99.70 98.52

Failure Buckets

Past Results