Unified Coverage Report :: Module :: sram_ctrl_regs_reg_top

Module : sram_ctrl_regs_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58	100.00	98.31			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs	99.58	100.00	98.31			100.00	100.00

---

Module Instance : tb.dut.u_reg_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58	100.00	98.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.50	99.03	96.77	100.00		96.72	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.68	100.00	92.71	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl0_qe	100.00	100.00				100.00
u_ctrl_init	100.00	100.00	100.00			100.00
u_ctrl_regwen	100.00	100.00	100.00			100.00
u_ctrl_renew_scr_key	100.00	100.00	100.00			100.00
u_exec	100.00	100.00	100.00			100.00
u_exec_regwen	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_readback	100.00	100.00	100.00			100.00
u_readback_regwen	66.30	88.89	50.00			60.00
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_scr_key_rotated	100.00	100.00	100.00			100.00
u_status_bus_integ_error	100.00	100.00	100.00			100.00
u_status_escalated	100.00	100.00	100.00			100.00
u_status_init_done	100.00	100.00	100.00			100.00
u_status_init_error	100.00	100.00	100.00			100.00
u_status_readback_error	62.59	77.78	50.00			60.00
u_status_scr_key_seed_valid	100.00	100.00	100.00			100.00
u_status_scr_key_valid	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sram_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
TOTAL		75	75	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
ALWAYS	616	10	10	100.00
CONT_ASSIGN	628	1	1	100.00
ALWAYS	632	1	1	100.00
CONT_ASSIGN	645	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	651	1	1	100.00
CONT_ASSIGN	653	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	656	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	661	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	665	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
ALWAYS	674	10	10	100.00
ALWAYS	688	18	18	100.00
CONT_ASSIGN	744	0	0
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
159	1	1
173	1	1
398	1	1
468	1	1
495	1	1
523	1	1
585	1	1
616	1	1
617	1	1
618	1	1
619	1	1
620	1	1
621	1	1
622	1	1
623	1	1
624	1	1
625	1	1
628	1	1
632	1	1
645	1	1
647	1	1
648	1	1
650	1	1
651	1	1
653	1	1
654	1	1
656	1	1
657	1	1
659	1	1
661	1	1
662	1	1
664	1	1
665	1	1
667	1	1
668	1	1
670	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
681	1	1
682	1	1
683	1	1
688	1	1
689	1	1
691	1	1
695	1	1
696	1	1
697	1	1
698	1	1
699	1	1
700	1	1
701	1	1
705	1	1
709	1	1
713	1	1
717	1	1
718	1	1
722	1	1
726	1	1
730	1	1
744		unreachable
752	1	1
753	1	1

---

Cond Coverage for Module : sram_ctrl_regs_reg_top

	Total	Covered	Percent
Conditions	118	116	98.31
Logical	118	116	98.31
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T20,T21
1	0	Covered	T46,T47,T48

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T19,T20,T21
0	1	0	Covered	T46,T47,T48
1	0	0	Covered	T19,T20,T21

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T46,T47,T48
0	1	0	Covered	T26,T27,T28
1	0	0	Covered	T26,T27,T28

 LINE       398
 EXPRESSION (exec_we & exec_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T23,T24
1	1	Covered	T2,T4,T14

 LINE       468
 EXPRESSION (ctrl_we & ctrl_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T23,T24
1	1	Covered	T1,T2,T3

 LINE       585
 EXPRESSION (readback_we & readback_regwen_qs)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       617
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_ALERT_TEST_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T9,T23

 LINE       618
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T9,T23

 LINE       619
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T23,T49

 LINE       620
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       621
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T9,T14

 LINE       622
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       623
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_SCR_KEY_ROTATED_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T9,T23

 LINE       624
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_READBACK_REGWEN_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T23,T49

 LINE       625
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_READBACK_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       628
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       628
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T23,T24

 LINE       632
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T27,T28

 LINE       632
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	1	Covered	T23,T49,T50
0	0	0	0	0	0	0	1	0	Covered	T23,T50,T51
0	0	0	0	0	0	1	0	0	Covered	T5,T9,T23
0	0	0	0	0	1	0	0	0	Covered	T9,T14,T23
0	0	0	0	1	0	0	0	0	Covered	T5,T9,T23
0	0	0	1	0	0	0	0	0	Covered	T1,T9,T23
0	0	1	0	0	0	0	0	0	Covered	T23,T49,T50
0	1	0	0	0	0	0	0	0	Covered	T9,T23,T49
1	0	0	0	0	0	0	0	0	Covered	T5,T23,T49

 LINE       632
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T9,T23,T49
1	1	Covered	T5,T23,T49

 LINE       632
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T5,T23,T49
1	1	Covered	T9,T23,T49

 LINE       632
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T14,T23,T49
1	1	Covered	T23,T49,T50

 LINE       632
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T9,T23

 LINE       632
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T14,T23,T49
1	1	Covered	T5,T9,T23

 LINE       632
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T14,T23

 LINE       632
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T23,T49,T50
1	1	Covered	T5,T9,T23

 LINE       632
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T9,T23,T49
1	1	Covered	T23,T50,T51

 LINE       632
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T49,T50

 LINE       645
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T9,T23
1	1	0	Covered	T26,T27,T28
1	1	1	Covered	T16,T17,T18

 LINE       648
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T14,T23,T49
1	1	0	Covered	T26,T27,T28
1	1	1	Covered	T14,T23,T24

 LINE       651
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T26,T27,T28
1	1	1	Covered	T2,T4,T14

 LINE       654
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T9,T14
1	1	0	Covered	T26,T27,T28
1	1	1	Covered	T14,T23,T24

 LINE       657
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T26,T27,T28
1	1	1	Covered	T1,T2,T3

 LINE       662
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T9,T23
1	1	0	Covered	T26,T27,T28
1	1	1	Covered	T52,T53,T54

 LINE       665
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T9,T23,T49
1	1	0	Covered	T26,T27,T28
1	1	1	Not Covered

 LINE       668
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T26,T27,T28
1	1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : sram_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
Branches		15	15	100.00
TERNARY	628	2	2	100.00
IF	68	3	3	100.00
CASE	689	10	10	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	628	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T19,T20,T21
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	689	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T2,T3,T4
addr_hit[1]	Covered	T2,T3,T4
addr_hit[2]	Covered	T2,T3,T4
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T2,T3,T4
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T2,T3,T4
addr_hit[7]	Covered	T2,T3,T4
addr_hit[8]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : sram_ctrl_regs_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	739916831	204723	0	0
reAfterRv	739916831	204723	0	0
rePulse	739916831	14603	0	0
wePulse	739916831	190120	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	739916831	204723	0	0
T1	49813	3	0	0
T2	627958	137	0	0
T3	44517	3	0	0
T4	190938	332	0	0
T5	154371	11	0	0
T9	70491	10	0	0
T10	481813	95	0	0
T11	67633	2	0	0
T12	249357	375	0	0
T13	324714	654	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	739916831	204723	0	0
T1	49813	3	0	0
T2	627958	137	0	0
T3	44517	3	0	0
T4	190938	332	0	0
T5	154371	11	0	0
T9	70491	10	0	0
T10	481813	95	0	0
T11	67633	2	0	0
T12	249357	375	0	0
T13	324714	654	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	739916831	14603	0	0
T6	0	30	0	0
T7	0	14	0	0
T14	119210	16	0	0
T15	325810	0	0	0
T16	1633	0	0	0
T22	124918	0	0	0
T23	124771	21	0	0
T24	0	9	0	0
T43	104457	0	0	0
T44	624655	0	0	0
T45	70027	0	0	0
T49	494473	0	0	0
T50	0	24	0	0
T55	0	14	0	0
T56	0	2	0	0
T57	0	4	0	0
T58	0	3	0	0
T59	690632	0	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	739916831	190120	0	0
T1	49813	3	0	0
T2	627958	137	0	0
T3	44517	3	0	0
T4	190938	332	0	0
T5	154371	11	0	0
T9	70491	10	0	0
T10	481813	95	0	0
T11	67633	2	0	0
T12	249357	375	0	0
T13	324714	654	0	0