Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	90.82	100.00		100.00	85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	95.68	100.00	92.71	100.00		100.00	85.71

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.68	100.00	92.71	100.00		100.00	85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.52	99.43	95.61	100.00	100.00	96.55	99.56

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_instr_ctrl.u_prim_lc_sync_hw_debug_en	100.00	100.00				100.00	100.00
gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch	100.00	100.00				100.00	100.00
sram_ctrl_regs_csr_assert	100.00						100.00
tlul_assert_device_ram	100.00	100.00				100.00	100.00
tlul_assert_device_regs	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_prim_alert_sender_parity	100.00			100.00
u_prim_count	100.00			100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_prim_ram_1p_scr	98.49	100.00	92.45	100.00		100.00	100.00
u_prim_sync_reqack_data	100.00	100.00	100.00			100.00	100.00
u_reg_regs	98.50	99.03	96.77	100.00		96.72	100.00
u_tlul_adapter_sram	98.26	99.16	95.57	100.00	100.00	94.82	100.00
u_tlul_data_integ_enc	100.00	100.00
u_tlul_lc_gate	96.79	100.00	100.00		100.00	96.43	87.50

Line Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
TOTAL		53	53	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
ALWAYS	224	3	3	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	296	11	11	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	560	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
134	1	1
137	1	1
141	1	1
145	1	1
148	1	1
180	1	1
182	1	1
190	1	1
197	1	1
206	1	1
215	1	1
220	1	1
224	1	1
225	1	1
227	1	1
236	1	1
237	1	1
261	1	1
262	1	1
273	1	1
278	1	1
282	1	1
283	1	1
287	1	1
288	1	1
292	1	1
293	1	1
296	1	1
297	1	1
300	1	1
301	1	1
303	1	1
304	1	1
305	1	1
306	1	1
			MISSING_ELSE
311	1	1
312	1	1
313	1	1
			MISSING_ELSE
340	1	1
372	1	1
374	1	1
376	1	1
460	1	1
501	1	1
507	1	1
508	1	1
509	1	1
510	1	1
511	1	1
512	1	1
523	1	1
560	1	1

---

Cond Coverage for Module : sram_ctrl

	Total	Covered	Percent
Conditions	98	89	90.82
Logical	98	89	90.82
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T17,T18

 LINE       148
 EXPRESSION (((|bus_integ_error)) | init_error | readback_error)
             ----------1---------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T19,T20,T21
1	0	0	Covered	T19,T20,T21

 LINE       190
 EXPRESSION (reg2hw.status.escalated.q | reg2hw.status.init_error.q | reg2hw.status.bus_integ_error.q | reg2hw.status.readback_error.q)
             ------------1------------   -------------2------------   ---------------3---------------   ---------------4--------------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T19,T20,T21
0	1	0	0	Covered	T19,T20,T21
1	0	0	0	Covered	T6,T7,T8

 LINE       197
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | readback_error | local_esc_reg)
             ----1---   -----2----   ----------3---------   -------4------   ------5------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T6,T7,T8
0	0	0	1	0	Not Covered
0	0	1	0	0	Covered	T19,T20,T21
0	1	0	0	0	Covered	T19,T20,T21
1	0	0	0	0	Covered	T6,T7,T8

 LINE       215
 EXPRESSION (reg2hw.ctrl.init.q && reg2hw.ctrl.init.qe && ((!init_q)))
             ---------1--------    ---------2---------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       220
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION ((init_cnt == 15'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       237
 SUB-EXPRESSION (init_cnt == 15'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       261
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T2,T3

 LINE       262
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q && reg2hw.ctrl.renew_scr_key.qe && ((!key_req_pending_q)) && ((!init_q)))
             -------------1-------------    --------------2-------------    -----------3----------    -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T14,T23,T24
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       278
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       278
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       287
 EXPRESSION ((key_ack & ((~local_esc))) ? MuBi4True : MuBi4False)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       287
 SUB-EXPRESSION (key_ack & ((~local_esc)))
                 ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       292
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       501
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       507
 EXPRESSION (key_valid & ((~init_req)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       508
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       509
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T19,T20,T21

 LINE       510
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       511
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       512
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_compound_txn_in_progress) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_compound_txn_in_progress) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       523
 SUB-EXPRESSION (tl_gate_resp_pending & sram_compound_txn_in_progress)
                 ----------1---------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T25

---

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	60	60	100.00
Total Bits	1226	1226	100.00
Total Bits 0->1	613	613	100.00
Total Bits 1->0	613	613	100.00

Ports	60	60	100.00
Port Bits	1226	1226	100.00
Port Bits 0->1	613	613	100.00
Port Bits 1->0	613	613	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T6,T7,T8	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T6,T7,T8	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T4,T14	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T9	Yes	T1,T5,T9	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T5,T9	Yes	T1,T5,T9	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T5,T9	Yes	T5,T9,T14	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T4,*T5	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T14,T23,T24	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T14,*T23,*T24	Yes	T14,T23,T24	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T2,T4,T14	Yes	T2,T4,T14	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T2,T4,T14	Yes	T2,T4,T14	INPUT
sram_otp_key_o.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T2,T4,T9	Yes	T2,T4,T5	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T2,T4,T10	Yes	T2,T4,T10	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T2,T4,T10	Yes	T2,T4,T10	INPUT
sram_otp_key_i.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_i.rf_cfg.cfg[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_i.rf_cfg.cfg_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_i.ram_cfg.cfg[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_i.ram_cfg.cfg_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	220	3	3	100.00
TERNARY	278	3	3	100.00
TERNARY	287	2	2	100.00
TERNARY	510	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	512	2	2	100.00
TERNARY	523	3	3	100.00
IF	224	2	2	100.00
IF	296	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	220	(init_done) ? 
-2-:	220	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	278	(key_req) ? 
-2-:	278	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	287	((key_ack & (~local_esc))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	512	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	523	(key_req_pending_q) ? 
-2-:	523	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	296	if ((!rst_ni))
-2-:	304	if (key_ack)
-3-:	311	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T6,T7,T8
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : sram_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	12	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	12	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertOutKnown_A	729017898	728917481	0	0
FpvSecCmCntCheck_A	729017898	80	0	0
FpvSecCmFifoRptrCheck_A	729017898	80	0	0
FpvSecCmFifoWptrCheck_A	729017898	80	0	0
FpvSecCmLcGateFsmCheck_A	729017898	0	0	0
FpvSecCmRegWeOnehotCheck_A	729017898	80	0	0
FpvSecCmTlSramByteFsm_A	729017898	0	0	0
NonceWidthsLessThanSource_A	786	786	0	0
RamTlOutKnown_A	729017898	728917481	0	0
RamTlOutPayLoadKnown_A	729017898	196109444	0	0
RamTlOutPayLoadKnown_AKnownEnable	729017898	728917481	0	0
RegsTlOutKnown_A	729017898	728917481	0	0
SramOtpKeyKnown_A	729017898	728917481	0	0
TlulGntIsCorrect_A	729017898	159876561	0	0

AlertOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	728917481	0	0
T1	49813	49731	0	0
T2	627958	627881	0	0
T3	44517	44461	0	0
T4	190938	190931	0	0
T5	154371	154309	0	0
T9	70491	70407	0	0
T10	481813	481752	0	0
T11	67633	67580	0	0
T12	249357	249351	0	0
T13	324714	324707	0	0

FpvSecCmCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	80	0	0
T19	70297	20	0	0
T20	0	20	0	0
T21	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	72890	0	0	0
T35	1203	0	0	0
T36	71751	0	0	0
T37	780446	0	0	0
T38	34643	0	0	0
T39	33713	0	0	0
T40	221359	0	0	0
T41	344942	0	0	0
T42	33586	0	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	80	0	0
T19	70297	20	0	0
T20	0	20	0	0
T21	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	72890	0	0	0
T35	1203	0	0	0
T36	71751	0	0	0
T37	780446	0	0	0
T38	34643	0	0	0
T39	33713	0	0	0
T40	221359	0	0	0
T41	344942	0	0	0
T42	33586	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	80	0	0
T19	70297	20	0	0
T20	0	20	0	0
T21	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	72890	0	0	0
T35	1203	0	0	0
T36	71751	0	0	0
T37	780446	0	0	0
T38	34643	0	0	0
T39	33713	0	0	0
T40	221359	0	0	0
T41	344942	0	0	0
T42	33586	0	0	0

FpvSecCmLcGateFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	80	0	0
T19	70297	20	0	0
T20	0	20	0	0
T21	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	72890	0	0	0
T35	1203	0	0	0
T36	71751	0	0	0
T37	780446	0	0	0
T38	34643	0	0	0
T39	33713	0	0	0
T40	221359	0	0	0
T41	344942	0	0	0
T42	33586	0	0	0

FpvSecCmTlSramByteFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	0	0	0

NonceWidthsLessThanSource_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786	786	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

RamTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	728917481	0	0
T1	49813	49731	0	0
T2	627958	627881	0	0
T3	44517	44461	0	0
T4	190938	190931	0	0
T5	154371	154309	0	0
T9	70491	70407	0	0
T10	481813	481752	0	0
T11	67633	67580	0	0
T12	249357	249351	0	0
T13	324714	324707	0	0

RamTlOutPayLoadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	196109444	0	0
T1	49813	8314	0	0
T2	627958	120780	0	0
T3	44517	4021	0	0
T4	190938	199256	0	0
T5	154371	44871	0	0
T9	70491	1499	0	0
T10	481813	172735	0	0
T11	67633	541	0	0
T12	249357	295667	0	0
T13	324714	144179	0	0

RamTlOutPayLoadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	728917481	0	0
T1	49813	49731	0	0
T2	627958	627881	0	0
T3	44517	44461	0	0
T4	190938	190931	0	0
T5	154371	154309	0	0
T9	70491	70407	0	0
T10	481813	481752	0	0
T11	67633	67580	0	0
T12	249357	249351	0	0
T13	324714	324707	0	0

RegsTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	728917481	0	0
T1	49813	49731	0	0
T2	627958	627881	0	0
T3	44517	44461	0	0
T4	190938	190931	0	0
T5	154371	154309	0	0
T9	70491	70407	0	0
T10	481813	481752	0	0
T11	67633	67580	0	0
T12	249357	249351	0	0
T13	324714	324707	0	0

SramOtpKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	728917481	0	0
T1	49813	49731	0	0
T2	627958	627881	0	0
T3	44517	44461	0	0
T4	190938	190931	0	0
T5	154371	154309	0	0
T9	70491	70407	0	0
T10	481813	481752	0	0
T11	67633	67580	0	0
T12	249357	249351	0	0
T13	324714	324707	0	0

TlulGntIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	159876561	0	0
T1	49813	4207	0	0
T2	627958	75448	0	0
T3	44517	8222	0	0
T4	190938	149050	0	0
T5	154371	23092	0	0
T9	70491	3022	0	0
T10	481813	257991	0	0
T11	67633	541	0	0
T12	249357	417654	0	0
T13	324714	209715	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		53	53	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
ALWAYS	224	3	3	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	296	11	11	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	560	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
134	1	1
137	1	1
141	1	1
145	1	1
148	1	1
180	1	1
182	1	1
190	1	1
197	1	1
206	1	1
215	1	1
220	1	1
224	1	1
225	1	1
227	1	1
236	1	1
237	1	1
261	1	1
262	1	1
273	1	1
278	1	1
282	1	1
283	1	1
287	1	1
288	1	1
292	1	1
293	1	1
296	1	1
297	1	1
300	1	1
301	1	1
303	1	1
304	1	1
305	1	1
306	1	1
			MISSING_ELSE
311	1	1
312	1	1
313	1	1
			MISSING_ELSE
340	1	1
372	1	1
374	1	1
376	1	1
460	1	1
501	1	1
507	1	1
508	1	1
509	1	1
510	1	1
511	1	1
512	1	1
523	1	1
560	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	96	89	92.71
Logical	96	89	92.71
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T17,T18

 LINE       148
 EXPRESSION (((|bus_integ_error)) | init_error | readback_error)
             ----------1---------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T19,T20,T21
1	0	0	Covered	T19,T20,T21

 LINE       190
 EXPRESSION (reg2hw.status.escalated.q | reg2hw.status.init_error.q | reg2hw.status.bus_integ_error.q | reg2hw.status.readback_error.q)
             ------------1------------   -------------2------------   ---------------3---------------   ---------------4--------------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T19,T20,T21
0	1	0	0	Covered	T19,T20,T21
1	0	0	0	Covered	T6,T7,T8

 LINE       197
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | readback_error | local_esc_reg)
             ----1---   -----2----   ----------3---------   -------4------   ------5------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T6,T7,T8
0	0	0	1	0	Not Covered
0	0	1	0	0	Covered	T19,T20,T21
0	1	0	0	0	Covered	T19,T20,T21
1	0	0	0	0	Covered	T6,T7,T8

 LINE       215
 EXPRESSION (reg2hw.ctrl.init.q && reg2hw.ctrl.init.qe && ((!init_q)))
             ---------1--------    ---------2---------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       220
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION ((init_cnt == 15'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       237
 SUB-EXPRESSION (init_cnt == 15'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       261
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[LOWRISK] we don't issue a new init when there is a unfinished init
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T2,T3

 LINE       262
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q && reg2hw.ctrl.renew_scr_key.qe && ((!key_req_pending_q)) && ((!init_q)))
             -------------1-------------    --------------2-------------    -----------3----------    -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T14,T23,T24
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       278
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       278
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[UNSUPPORTED] ACK can't come without REQ
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       287
 EXPRESSION ((key_ack & ((~local_esc))) ? MuBi4True : MuBi4False)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       287
 SUB-EXPRESSION (key_ack & ((~local_esc)))
                 ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       292
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       501
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       507
 EXPRESSION (key_valid & ((~init_req)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       508
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       509
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T19,T20,T21

 LINE       510
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       511
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       512
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_compound_txn_in_progress) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_compound_txn_in_progress) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       523
 SUB-EXPRESSION (tl_gate_resp_pending & sram_compound_txn_in_progress)
                 ----------1---------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T25

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	60	60	100.00
Total Bits	1226	1226	100.00
Total Bits 0->1	613	613	100.00
Total Bits 1->0	613	613	100.00

Ports	60	60	100.00
Port Bits	1226	1226	100.00
Port Bits 0->1	613	613	100.00
Port Bits 1->0	613	613	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T6,T7,T8	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T6,T7,T8	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T4,T14	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T9	Yes	T1,T5,T9	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T5,T9	Yes	T1,T5,T9	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T5,T9	Yes	T5,T9,T14	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T4,*T5	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T14,T23,T24	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T14,*T23,*T24	Yes	T14,T23,T24	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T2,T4,T14	Yes	T2,T4,T14	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T2,T4,T14	Yes	T2,T4,T14	INPUT
sram_otp_key_o.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T2,T4,T9	Yes	T2,T4,T5	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T2,T4,T10	Yes	T2,T4,T10	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T2,T4,T10	Yes	T2,T4,T10	INPUT
sram_otp_key_i.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_i.rf_cfg.cfg[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_i.rf_cfg.cfg_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_i.ram_cfg.cfg[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_i.ram_cfg.cfg_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	220	3	3	100.00
TERNARY	278	3	3	100.00
TERNARY	287	2	2	100.00
TERNARY	510	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	512	2	2	100.00
TERNARY	523	3	3	100.00
IF	224	2	2	100.00
IF	296	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	220	(init_done) ? 
-2-:	220	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	278	(key_req) ? 
-2-:	278	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	287	((key_ack & (~local_esc))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	512	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	523	(key_req_pending_q) ? 
-2-:	523	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	296	if ((!rst_ni))
-2-:	304	if (key_ack)
-3-:	311	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T6,T7,T8
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	12	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	12	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertOutKnown_A	729017898	728917481	0	0
FpvSecCmCntCheck_A	729017898	80	0	0
FpvSecCmFifoRptrCheck_A	729017898	80	0	0
FpvSecCmFifoWptrCheck_A	729017898	80	0	0
FpvSecCmLcGateFsmCheck_A	729017898	0	0	0
FpvSecCmRegWeOnehotCheck_A	729017898	80	0	0
FpvSecCmTlSramByteFsm_A	729017898	0	0	0
NonceWidthsLessThanSource_A	786	786	0	0
RamTlOutKnown_A	729017898	728917481	0	0
RamTlOutPayLoadKnown_A	729017898	196109444	0	0
RamTlOutPayLoadKnown_AKnownEnable	729017898	728917481	0	0
RegsTlOutKnown_A	729017898	728917481	0	0
SramOtpKeyKnown_A	729017898	728917481	0	0
TlulGntIsCorrect_A	729017898	159876561	0	0

AlertOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	728917481	0	0
T1	49813	49731	0	0
T2	627958	627881	0	0
T3	44517	44461	0	0
T4	190938	190931	0	0
T5	154371	154309	0	0
T9	70491	70407	0	0
T10	481813	481752	0	0
T11	67633	67580	0	0
T12	249357	249351	0	0
T13	324714	324707	0	0

FpvSecCmCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	80	0	0
T19	70297	20	0	0
T20	0	20	0	0
T21	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	72890	0	0	0
T35	1203	0	0	0
T36	71751	0	0	0
T37	780446	0	0	0
T38	34643	0	0	0
T39	33713	0	0	0
T40	221359	0	0	0
T41	344942	0	0	0
T42	33586	0	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	80	0	0
T19	70297	20	0	0
T20	0	20	0	0
T21	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	72890	0	0	0
T35	1203	0	0	0
T36	71751	0	0	0
T37	780446	0	0	0
T38	34643	0	0	0
T39	33713	0	0	0
T40	221359	0	0	0
T41	344942	0	0	0
T42	33586	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	80	0	0
T19	70297	20	0	0
T20	0	20	0	0
T21	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	72890	0	0	0
T35	1203	0	0	0
T36	71751	0	0	0
T37	780446	0	0	0
T38	34643	0	0	0
T39	33713	0	0	0
T40	221359	0	0	0
T41	344942	0	0	0
T42	33586	0	0	0

FpvSecCmLcGateFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	80	0	0
T19	70297	20	0	0
T20	0	20	0	0
T21	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	72890	0	0	0
T35	1203	0	0	0
T36	71751	0	0	0
T37	780446	0	0	0
T38	34643	0	0	0
T39	33713	0	0	0
T40	221359	0	0	0
T41	344942	0	0	0
T42	33586	0	0	0

FpvSecCmTlSramByteFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	0	0	0

NonceWidthsLessThanSource_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786	786	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

RamTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	728917481	0	0
T1	49813	49731	0	0
T2	627958	627881	0	0
T3	44517	44461	0	0
T4	190938	190931	0	0
T5	154371	154309	0	0
T9	70491	70407	0	0
T10	481813	481752	0	0
T11	67633	67580	0	0
T12	249357	249351	0	0
T13	324714	324707	0	0

RamTlOutPayLoadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	196109444	0	0
T1	49813	8314	0	0
T2	627958	120780	0	0
T3	44517	4021	0	0
T4	190938	199256	0	0
T5	154371	44871	0	0
T9	70491	1499	0	0
T10	481813	172735	0	0
T11	67633	541	0	0
T12	249357	295667	0	0
T13	324714	144179	0	0

RamTlOutPayLoadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	728917481	0	0
T1	49813	49731	0	0
T2	627958	627881	0	0
T3	44517	44461	0	0
T4	190938	190931	0	0
T5	154371	154309	0	0
T9	70491	70407	0	0
T10	481813	481752	0	0
T11	67633	67580	0	0
T12	249357	249351	0	0
T13	324714	324707	0	0

RegsTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	728917481	0	0
T1	49813	49731	0	0
T2	627958	627881	0	0
T3	44517	44461	0	0
T4	190938	190931	0	0
T5	154371	154309	0	0
T9	70491	70407	0	0
T10	481813	481752	0	0
T11	67633	67580	0	0
T12	249357	249351	0	0
T13	324714	324707	0	0

SramOtpKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	728917481	0	0
T1	49813	49731	0	0
T2	627958	627881	0	0
T3	44517	44461	0	0
T4	190938	190931	0	0
T5	154371	154309	0	0
T9	70491	70407	0	0
T10	481813	481752	0	0
T11	67633	67580	0	0
T12	249357	249351	0	0
T13	324714	324707	0	0

TlulGntIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729017898	159876561	0	0
T1	49813	4207	0	0
T2	627958	75448	0	0
T3	44517	8222	0	0
T4	190938	149050	0	0
T5	154371	23092	0	0
T9	70491	3022	0	0
T10	481813	257991	0	0
T11	67633	541	0	0
T12	249357	417654	0	0
T13	324714	209715	0	0