Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.68	100.00	92.71	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	739916831	125379	0	0
ctrl_regwen_rd_A	739916831	2235	0	0
exec_rd_A	739916831	1963	0	0
exec_regwen_rd_A	739916831	2161	0	0
readback_rd_A	739916831	1267	0	0
readback_regwen_rd_A	739916831	1035	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	739916831	125379	0	0
T26	26365	1340	0	0
T27	0	3602	0	0
T28	0	3915	0	0
T60	0	1901	0	0
T61	0	5645	0	0
T62	0	769	0	0
T63	0	4521	0	0
T64	0	2619	0	0
T65	0	1521	0	0
T66	0	6128	0	0
T67	111665	0	0	0
T68	112787	0	0	0
T69	535011	0	0	0
T70	1007	0	0	0
T71	846144	0	0	0
T72	773605	0	0	0
T73	177127	0	0	0
T74	39613	0	0	0
T75	467483	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	739916831	2235	0	0
T27	76291	173	0	0
T28	47005	0	0	0
T64	0	191	0	0
T80	159070	0	0	0
T91	0	38	0	0
T105	138867	0	0	0
T125	0	132	0	0
T126	0	149	0	0
T127	0	177	0	0
T128	0	106	0	0
T129	0	199	0	0
T130	0	29	0	0
T131	0	4	0	0
T132	1360	0	0	0
T133	693116	0	0	0
T134	859463	0	0	0
T135	34988	0	0	0
T136	137593	0	0	0
T137	104120	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	739916831	1963	0	0
T27	76291	100	0	0
T28	47005	0	0	0
T64	0	154	0	0
T80	159070	0	0	0
T91	0	32	0	0
T105	138867	0	0	0
T125	0	146	0	0
T126	0	146	0	0
T127	0	154	0	0
T128	0	99	0	0
T129	0	137	0	0
T130	0	52	0	0
T131	0	3	0	0
T132	1360	0	0	0
T133	693116	0	0	0
T134	859463	0	0	0
T135	34988	0	0	0
T136	137593	0	0	0
T137	104120	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	739916831	2161	0	0
T27	76291	135	0	0
T28	47005	0	0	0
T64	0	239	0	0
T80	159070	0	0	0
T91	0	37	0	0
T105	138867	0	0	0
T125	0	120	0	0
T126	0	129	0	0
T127	0	152	0	0
T128	0	143	0	0
T129	0	131	0	0
T130	0	64	0	0
T131	0	17	0	0
T132	1360	0	0	0
T133	693116	0	0	0
T134	859463	0	0	0
T135	34988	0	0	0
T136	137593	0	0	0
T137	104120	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	739916831	1267	0	0
T27	76291	177	0	0
T28	47005	0	0	0
T64	0	196	0	0
T80	159070	0	0	0
T105	138867	0	0	0
T125	0	94	0	0
T126	0	117	0	0
T127	0	95	0	0
T128	0	115	0	0
T129	0	178	0	0
T130	0	38	0	0
T131	0	2	0	0
T132	1360	0	0	0
T133	693116	0	0	0
T134	859463	0	0	0
T135	34988	0	0	0
T136	137593	0	0	0
T137	104120	0	0	0
T138	0	42	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	739916831	1035	0	0
T27	76291	118	0	0
T28	47005	0	0	0
T64	0	145	0	0
T80	159070	0	0	0
T105	138867	0	0	0
T125	0	98	0	0
T126	0	145	0	0
T127	0	131	0	0
T128	0	102	0	0
T129	0	84	0	0
T130	0	42	0	0
T132	1360	0	0	0
T133	693116	0	0	0
T134	859463	0	0	0
T135	34988	0	0	0
T136	137593	0	0	0
T137	104120	0	0	0
T138	0	30	0	0
T139	0	25	0	0