| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 98.32 | 99.43 | 95.61 | 100.00 | 100.00 | 96.55 | 99.56 | 97.07 |
| T789 | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3244712666 | May 26 03:14:47 PM PDT 24 | May 26 03:20:24 PM PDT 24 | 51009173353 ps | ||
| T790 | /workspace/coverage/default/8.sram_ctrl_smoke.3098076476 | May 26 03:05:16 PM PDT 24 | May 26 03:06:44 PM PDT 24 | 8171017622 ps | ||
| T791 | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2227883143 | May 26 03:09:34 PM PDT 24 | May 26 03:12:07 PM PDT 24 | 12216823478 ps | ||
| T792 | /workspace/coverage/default/43.sram_ctrl_ram_cfg.99665739 | May 26 03:15:22 PM PDT 24 | May 26 03:15:26 PM PDT 24 | 1302216692 ps | ||
| T793 | /workspace/coverage/default/0.sram_ctrl_mem_walk.24347471 | May 26 03:02:51 PM PDT 24 | May 26 03:08:33 PM PDT 24 | 28234545816 ps | ||
| T794 | /workspace/coverage/default/7.sram_ctrl_lc_escalation.1166116775 | May 26 03:04:54 PM PDT 24 | May 26 03:05:32 PM PDT 24 | 5717617755 ps | ||
| T795 | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2556627624 | May 26 03:08:15 PM PDT 24 | May 26 03:10:30 PM PDT 24 | 1590112913 ps | ||
| T796 | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.4028466276 | May 26 03:15:24 PM PDT 24 | May 26 03:19:35 PM PDT 24 | 17360541751 ps | ||
| T797 | /workspace/coverage/default/8.sram_ctrl_multiple_keys.2217491122 | May 26 03:05:10 PM PDT 24 | May 26 03:14:39 PM PDT 24 | 7534128177 ps | ||
| T798 | /workspace/coverage/default/17.sram_ctrl_regwen.2441069516 | May 26 03:08:00 PM PDT 24 | May 26 03:22:58 PM PDT 24 | 156516697834 ps | ||
| T799 | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3651147983 | May 26 03:03:07 PM PDT 24 | May 26 03:06:14 PM PDT 24 | 19502849401 ps | ||
| T800 | /workspace/coverage/default/35.sram_ctrl_partial_access.3621718373 | May 26 03:12:48 PM PDT 24 | May 26 03:15:49 PM PDT 24 | 2822967635 ps | ||
| T801 | /workspace/coverage/default/17.sram_ctrl_max_throughput.2984160669 | May 26 03:07:54 PM PDT 24 | May 26 03:10:41 PM PDT 24 | 1096297400 ps | ||
| T130 | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1606466123 | May 26 03:13:50 PM PDT 24 | May 26 03:13:58 PM PDT 24 | 1348265312 ps | ||
| T802 | /workspace/coverage/default/49.sram_ctrl_smoke.3575955897 | May 26 03:16:58 PM PDT 24 | May 26 03:18:03 PM PDT 24 | 1792888626 ps | ||
| T803 | /workspace/coverage/default/1.sram_ctrl_partial_access.1616397618 | May 26 03:02:57 PM PDT 24 | May 26 03:03:20 PM PDT 24 | 981018704 ps | ||
| T804 | /workspace/coverage/default/10.sram_ctrl_max_throughput.2846173947 | May 26 03:05:53 PM PDT 24 | May 26 03:06:00 PM PDT 24 | 2776711845 ps | ||
| T805 | /workspace/coverage/default/26.sram_ctrl_alert_test.3151077698 | May 26 03:10:20 PM PDT 24 | May 26 03:10:22 PM PDT 24 | 57042811 ps | ||
| T806 | /workspace/coverage/default/2.sram_ctrl_alert_test.3131165493 | May 26 03:03:27 PM PDT 24 | May 26 03:03:29 PM PDT 24 | 35340609 ps | ||
| T807 | /workspace/coverage/default/28.sram_ctrl_max_throughput.3692785064 | May 26 03:10:49 PM PDT 24 | May 26 03:11:15 PM PDT 24 | 2797560698 ps | ||
| T808 | /workspace/coverage/default/35.sram_ctrl_lc_escalation.2946885638 | May 26 03:12:59 PM PDT 24 | May 26 03:14:06 PM PDT 24 | 79113445853 ps | ||
| T809 | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1788343543 | May 26 03:06:07 PM PDT 24 | May 26 03:07:36 PM PDT 24 | 2266383769 ps | ||
| T810 | /workspace/coverage/default/21.sram_ctrl_executable.631965180 | May 26 03:09:04 PM PDT 24 | May 26 03:34:37 PM PDT 24 | 96695853170 ps | ||
| T811 | /workspace/coverage/default/37.sram_ctrl_mem_walk.4072608965 | May 26 03:13:27 PM PDT 24 | May 26 03:17:41 PM PDT 24 | 3985635462 ps | ||
| T812 | /workspace/coverage/default/38.sram_ctrl_bijection.2550189509 | May 26 03:13:41 PM PDT 24 | May 26 03:44:09 PM PDT 24 | 138022804389 ps | ||
| T813 | /workspace/coverage/default/47.sram_ctrl_smoke.3380100993 | May 26 03:16:13 PM PDT 24 | May 26 03:18:24 PM PDT 24 | 954591651 ps | ||
| T814 | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2057754566 | May 26 03:12:25 PM PDT 24 | May 26 03:17:58 PM PDT 24 | 74644171643 ps | ||
| T815 | /workspace/coverage/default/40.sram_ctrl_mem_walk.2314976049 | May 26 03:14:25 PM PDT 24 | May 26 03:20:13 PM PDT 24 | 121788747758 ps | ||
| T816 | /workspace/coverage/default/6.sram_ctrl_ram_cfg.3154362552 | May 26 03:04:39 PM PDT 24 | May 26 03:04:43 PM PDT 24 | 1400596945 ps | ||
| T817 | /workspace/coverage/default/42.sram_ctrl_max_throughput.2315482947 | May 26 03:14:48 PM PDT 24 | May 26 03:17:15 PM PDT 24 | 7596845264 ps | ||
| T818 | /workspace/coverage/default/9.sram_ctrl_mem_walk.2981146832 | May 26 03:05:40 PM PDT 24 | May 26 03:11:43 PM PDT 24 | 94415482313 ps | ||
| T819 | /workspace/coverage/default/31.sram_ctrl_executable.4163018610 | May 26 03:11:40 PM PDT 24 | May 26 03:33:47 PM PDT 24 | 19942806481 ps | ||
| T820 | /workspace/coverage/default/29.sram_ctrl_ram_cfg.1269058917 | May 26 03:11:10 PM PDT 24 | May 26 03:11:13 PM PDT 24 | 353643810 ps | ||
| T821 | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.19468076 | May 26 03:09:17 PM PDT 24 | May 26 03:12:37 PM PDT 24 | 11447836516 ps | ||
| T822 | /workspace/coverage/default/36.sram_ctrl_executable.3988664306 | May 26 03:13:06 PM PDT 24 | May 26 03:22:43 PM PDT 24 | 10633229798 ps | ||
| T823 | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1173576789 | May 26 03:10:29 PM PDT 24 | May 26 03:11:43 PM PDT 24 | 931680786 ps | ||
| T824 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2822341012 | May 26 02:51:54 PM PDT 24 | May 26 02:51:58 PM PDT 24 | 243502638 ps | ||
| T52 | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1864451564 | May 26 02:52:14 PM PDT 24 | May 26 02:53:09 PM PDT 24 | 7059769940 ps | ||
| T53 | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.473496677 | May 26 02:52:03 PM PDT 24 | May 26 02:52:33 PM PDT 24 | 7378608408 ps | ||
| T825 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.956026633 | May 26 02:52:11 PM PDT 24 | May 26 02:52:16 PM PDT 24 | 1758064776 ps | ||
| T54 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2781968357 | May 26 02:51:57 PM PDT 24 | May 26 02:52:00 PM PDT 24 | 44157510 ps | ||
| T46 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1081834337 | May 26 02:52:07 PM PDT 24 | May 26 02:52:10 PM PDT 24 | 679506969 ps | ||
| T47 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2933507507 | May 26 02:52:13 PM PDT 24 | May 26 02:52:16 PM PDT 24 | 194799914 ps | ||
| T117 | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1341845121 | May 26 02:52:14 PM PDT 24 | May 26 02:52:18 PM PDT 24 | 16967455 ps | ||
| T91 | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2398988687 | May 26 02:51:58 PM PDT 24 | May 26 02:52:30 PM PDT 24 | 15414955379 ps | ||
| T131 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2560952969 | May 26 02:51:56 PM PDT 24 | May 26 02:52:02 PM PDT 24 | 413277006 ps | ||
| T48 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.769192216 | May 26 02:52:16 PM PDT 24 | May 26 02:52:24 PM PDT 24 | 1204479790 ps | ||
| T826 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1642922078 | May 26 02:51:58 PM PDT 24 | May 26 02:52:03 PM PDT 24 | 459771343 ps | ||
| T827 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.242009965 | May 26 02:52:17 PM PDT 24 | May 26 02:52:25 PM PDT 24 | 88863011 ps | ||
| T141 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.858737580 | May 26 02:52:10 PM PDT 24 | May 26 02:52:12 PM PDT 24 | 187094025 ps | ||
| T138 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2213425744 | May 26 02:52:22 PM PDT 24 | May 26 02:52:30 PM PDT 24 | 181173703 ps | ||
| T118 | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4172604190 | May 26 02:52:17 PM PDT 24 | May 26 02:52:23 PM PDT 24 | 57647863 ps | ||
| T828 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3736871843 | May 26 02:52:14 PM PDT 24 | May 26 02:52:19 PM PDT 24 | 80162545 ps | ||
| T829 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2853300214 | May 26 02:52:15 PM PDT 24 | May 26 02:52:22 PM PDT 24 | 70350323 ps | ||
| T139 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2511300919 | May 26 02:51:54 PM PDT 24 | May 26 02:52:00 PM PDT 24 | 132208238 ps | ||
| T830 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2070955633 | May 26 02:52:17 PM PDT 24 | May 26 02:52:24 PM PDT 24 | 52214751 ps | ||
| T831 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2279827357 | May 26 02:52:18 PM PDT 24 | May 26 02:52:26 PM PDT 24 | 344025862 ps | ||
| T92 | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1603169674 | May 26 02:52:22 PM PDT 24 | May 26 02:52:52 PM PDT 24 | 16143916333 ps | ||
| T832 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3873751108 | May 26 02:51:58 PM PDT 24 | May 26 02:52:01 PM PDT 24 | 20647861 ps | ||
| T93 | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.994346124 | May 26 02:52:03 PM PDT 24 | May 26 02:52:34 PM PDT 24 | 14221025443 ps | ||
| T833 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1742717477 | May 26 02:52:05 PM PDT 24 | May 26 02:52:06 PM PDT 24 | 30949892 ps | ||
| T119 | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2490816043 | May 26 02:52:15 PM PDT 24 | May 26 02:52:20 PM PDT 24 | 63702661 ps | ||
| T834 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4278300560 | May 26 02:52:21 PM PDT 24 | May 26 02:52:28 PM PDT 24 | 355154493 ps | ||
| T94 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1566691147 | May 26 02:51:56 PM PDT 24 | May 26 02:52:00 PM PDT 24 | 16930755 ps | ||
| T120 | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3262675661 | May 26 02:52:12 PM PDT 24 | May 26 02:52:14 PM PDT 24 | 44342328 ps | ||
| T835 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2486405397 | May 26 02:51:56 PM PDT 24 | May 26 02:52:01 PM PDT 24 | 66735642 ps | ||
| T836 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3887789569 | May 26 02:51:55 PM PDT 24 | May 26 02:51:58 PM PDT 24 | 18544013 ps | ||
| T145 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.363963142 | May 26 02:51:54 PM PDT 24 | May 26 02:51:58 PM PDT 24 | 249728496 ps | ||
| T837 | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3358569010 | May 26 02:52:16 PM PDT 24 | May 26 02:52:22 PM PDT 24 | 99690490 ps | ||
| T838 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4243697729 | May 26 02:51:53 PM PDT 24 | May 26 02:51:54 PM PDT 24 | 19829076 ps | ||
| T839 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3638144643 | May 26 02:51:55 PM PDT 24 | May 26 02:51:59 PM PDT 24 | 55493103 ps | ||
| T840 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.438623545 | May 26 02:52:17 PM PDT 24 | May 26 02:52:26 PM PDT 24 | 218324061 ps | ||
| T841 | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.770276789 | May 26 02:52:04 PM PDT 24 | May 26 02:52:05 PM PDT 24 | 13041794 ps | ||
| T95 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2570563227 | May 26 02:52:05 PM PDT 24 | May 26 02:52:07 PM PDT 24 | 45942924 ps | ||
| T842 | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1447550960 | May 26 02:52:04 PM PDT 24 | May 26 02:53:06 PM PDT 24 | 44397023203 ps | ||
| T843 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.755750143 | May 26 02:51:58 PM PDT 24 | May 26 02:52:04 PM PDT 24 | 1371212012 ps | ||
| T844 | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1844704083 | May 26 02:52:00 PM PDT 24 | May 26 02:52:03 PM PDT 24 | 196821419 ps | ||
| T845 | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1184882001 | May 26 02:52:15 PM PDT 24 | May 26 02:52:19 PM PDT 24 | 25588267 ps | ||
| T846 | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3282464963 | May 26 02:52:04 PM PDT 24 | May 26 02:52:06 PM PDT 24 | 36157916 ps | ||
| T847 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1959959447 | May 26 02:52:14 PM PDT 24 | May 26 02:52:19 PM PDT 24 | 333542809 ps | ||
| T848 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3348179062 | May 26 02:51:57 PM PDT 24 | May 26 02:52:00 PM PDT 24 | 22471430 ps | ||
| T849 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2948931264 | May 26 02:52:14 PM PDT 24 | May 26 02:52:17 PM PDT 24 | 46881599 ps | ||
| T850 | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.732447575 | May 26 02:52:13 PM PDT 24 | May 26 02:52:16 PM PDT 24 | 36240805 ps | ||
| T96 | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1670979400 | May 26 02:51:54 PM PDT 24 | May 26 02:52:50 PM PDT 24 | 32171926594 ps | ||
| T851 | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.697470891 | May 26 02:52:03 PM PDT 24 | May 26 02:52:08 PM PDT 24 | 351724914 ps | ||
| T97 | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3386613232 | May 26 02:52:01 PM PDT 24 | May 26 02:52:30 PM PDT 24 | 7692225721 ps | ||
| T852 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2960628577 | May 26 02:52:17 PM PDT 24 | May 26 02:52:27 PM PDT 24 | 752078988 ps | ||
| T853 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3867212501 | May 26 02:51:54 PM PDT 24 | May 26 02:51:58 PM PDT 24 | 486712106 ps | ||
| T854 | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2774679718 | May 26 02:51:55 PM PDT 24 | May 26 02:51:58 PM PDT 24 | 20997799 ps | ||
| T855 | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2253755751 | May 26 02:51:56 PM PDT 24 | May 26 02:52:32 PM PDT 24 | 14218332080 ps | ||
| T98 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1588424504 | May 26 02:52:06 PM PDT 24 | May 26 02:52:08 PM PDT 24 | 28890762 ps | ||
| T856 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2890256854 | May 26 02:51:59 PM PDT 24 | May 26 02:52:02 PM PDT 24 | 41956767 ps | ||
| T111 | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2674872300 | May 26 02:52:14 PM PDT 24 | May 26 02:52:50 PM PDT 24 | 14788296480 ps | ||
| T857 | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2970178444 | May 26 02:52:15 PM PDT 24 | May 26 02:52:20 PM PDT 24 | 55112714 ps | ||
| T149 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3575913398 | May 26 02:52:14 PM PDT 24 | May 26 02:52:19 PM PDT 24 | 308579087 ps | ||
| T858 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2347220869 | May 26 02:52:01 PM PDT 24 | May 26 02:52:07 PM PDT 24 | 361967765 ps | ||
| T859 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2336861132 | May 26 02:51:56 PM PDT 24 | May 26 02:52:02 PM PDT 24 | 4274172582 ps | ||
| T860 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2661797653 | May 26 02:52:07 PM PDT 24 | May 26 02:52:12 PM PDT 24 | 752920850 ps | ||
| T861 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3018005061 | May 26 02:52:12 PM PDT 24 | May 26 02:52:14 PM PDT 24 | 26386778 ps | ||
| T112 | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2251342883 | May 26 02:52:16 PM PDT 24 | May 26 02:52:48 PM PDT 24 | 10649304918 ps | ||
| T862 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1435858677 | May 26 02:52:01 PM PDT 24 | May 26 02:52:05 PM PDT 24 | 664365323 ps | ||
| T863 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2623753836 | May 26 02:51:55 PM PDT 24 | May 26 02:51:59 PM PDT 24 | 15826824 ps | ||
| T864 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3328394632 | May 26 02:52:15 PM PDT 24 | May 26 02:52:22 PM PDT 24 | 180518088 ps | ||
| T865 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3841478106 | May 26 02:51:55 PM PDT 24 | May 26 02:52:01 PM PDT 24 | 104758500 ps | ||
| T866 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1263519323 | May 26 02:52:11 PM PDT 24 | May 26 02:52:14 PM PDT 24 | 36578006 ps | ||
| T867 | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3456673795 | May 26 02:51:56 PM PDT 24 | May 26 02:52:00 PM PDT 24 | 40446345 ps | ||
| T148 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.874602620 | May 26 02:52:01 PM PDT 24 | May 26 02:52:04 PM PDT 24 | 302163039 ps | ||
| T868 | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.772247305 | May 26 02:52:14 PM PDT 24 | May 26 02:52:17 PM PDT 24 | 71886184 ps | ||
| T116 | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1208059307 | May 26 02:51:54 PM PDT 24 | May 26 02:52:26 PM PDT 24 | 3702734252 ps | ||
| T869 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3431109743 | May 26 02:52:22 PM PDT 24 | May 26 02:52:29 PM PDT 24 | 711662934 ps | ||
| T870 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3999931556 | May 26 02:52:01 PM PDT 24 | May 26 02:52:05 PM PDT 24 | 67640732 ps | ||
| T113 | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1629473890 | May 26 02:52:13 PM PDT 24 | May 26 02:53:22 PM PDT 24 | 63998942173 ps | ||
| T871 | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1588080908 | May 26 02:52:22 PM PDT 24 | May 26 02:52:26 PM PDT 24 | 14933580 ps | ||
| T114 | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.620841114 | May 26 02:51:56 PM PDT 24 | May 26 02:52:53 PM PDT 24 | 7493505030 ps | ||
| T872 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.785612570 | May 26 02:52:09 PM PDT 24 | May 26 02:52:11 PM PDT 24 | 27342569 ps | ||
| T873 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3281890699 | May 26 02:52:15 PM PDT 24 | May 26 02:52:19 PM PDT 24 | 22152298 ps | ||
| T874 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.162430271 | May 26 02:52:04 PM PDT 24 | May 26 02:52:08 PM PDT 24 | 310949269 ps | ||
| T875 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4288442181 | May 26 02:52:13 PM PDT 24 | May 26 02:52:15 PM PDT 24 | 16068397 ps | ||
| T876 | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4073323336 | May 26 02:52:00 PM PDT 24 | May 26 02:52:29 PM PDT 24 | 7584309197 ps | ||
| T150 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1286960380 | May 26 02:52:02 PM PDT 24 | May 26 02:52:05 PM PDT 24 | 109300102 ps | ||
| T115 | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2499951155 | May 26 02:52:04 PM PDT 24 | May 26 02:52:58 PM PDT 24 | 14495446832 ps | ||
| T143 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.305067039 | May 26 02:52:08 PM PDT 24 | May 26 02:52:10 PM PDT 24 | 1637626019 ps | ||
| T877 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3812871856 | May 26 02:52:10 PM PDT 24 | May 26 02:52:14 PM PDT 24 | 363554781 ps | ||
| T878 | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1373033944 | May 26 02:52:19 PM PDT 24 | May 26 02:52:52 PM PDT 24 | 15355858874 ps | ||
| T879 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.602466724 | May 26 02:52:15 PM PDT 24 | May 26 02:52:20 PM PDT 24 | 34049674 ps | ||
| T880 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1378904585 | May 26 02:52:11 PM PDT 24 | May 26 02:52:17 PM PDT 24 | 615728920 ps | ||
| T144 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.162823692 | May 26 02:52:18 PM PDT 24 | May 26 02:52:24 PM PDT 24 | 201558145 ps | ||
| T881 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1350908523 | May 26 02:52:15 PM PDT 24 | May 26 02:52:23 PM PDT 24 | 1421090781 ps | ||
| T882 | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1801543 | May 26 02:52:13 PM PDT 24 | May 26 02:52:15 PM PDT 24 | 54453856 ps | ||
| T883 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3721301127 | May 26 02:52:16 PM PDT 24 | May 26 02:52:23 PM PDT 24 | 196671047 ps | ||
| T146 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1479559057 | May 26 02:51:56 PM PDT 24 | May 26 02:52:00 PM PDT 24 | 327607169 ps | ||
| T884 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3065086156 | May 26 02:52:01 PM PDT 24 | May 26 02:52:07 PM PDT 24 | 364699113 ps | ||
| T142 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4193590692 | May 26 02:52:09 PM PDT 24 | May 26 02:52:11 PM PDT 24 | 380584486 ps | ||
| T885 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1064838108 | May 26 02:51:54 PM PDT 24 | May 26 02:51:57 PM PDT 24 | 65632645 ps | ||
| T886 | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1459997435 | May 26 02:52:01 PM PDT 24 | May 26 02:52:04 PM PDT 24 | 34091468 ps | ||
| T887 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.842902237 | May 26 02:51:55 PM PDT 24 | May 26 02:52:01 PM PDT 24 | 451394827 ps | ||
| T888 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2428591449 | May 26 02:51:56 PM PDT 24 | May 26 02:52:03 PM PDT 24 | 43568979 ps | ||
| T889 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3387644577 | May 26 02:51:58 PM PDT 24 | May 26 02:52:01 PM PDT 24 | 113096358 ps | ||
| T890 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3443065768 | May 26 02:51:56 PM PDT 24 | May 26 02:52:00 PM PDT 24 | 18985787 ps | ||
| T891 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1137325455 | May 26 02:52:04 PM PDT 24 | May 26 02:52:09 PM PDT 24 | 1451034278 ps | ||
| T892 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3567671859 | May 26 02:52:09 PM PDT 24 | May 26 02:52:14 PM PDT 24 | 1285168543 ps | ||
| T893 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2129674324 | May 26 02:51:59 PM PDT 24 | May 26 02:52:05 PM PDT 24 | 716593964 ps | ||
| T894 | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1261858716 | May 26 02:52:04 PM PDT 24 | May 26 02:52:37 PM PDT 24 | 7254715786 ps | ||
| T895 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3010617249 | May 26 02:51:59 PM PDT 24 | May 26 02:52:02 PM PDT 24 | 74365692 ps | ||
| T896 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.866943355 | May 26 02:51:59 PM PDT 24 | May 26 02:52:01 PM PDT 24 | 53471256 ps | ||
| T897 | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4103868302 | May 26 02:52:03 PM PDT 24 | May 26 02:52:05 PM PDT 24 | 13559385 ps | ||
| T898 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1544178283 | May 26 02:52:13 PM PDT 24 | May 26 02:52:15 PM PDT 24 | 16674647 ps | ||
| T899 | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1408982575 | May 26 02:51:56 PM PDT 24 | May 26 02:51:59 PM PDT 24 | 41629169 ps | ||
| T900 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2876276986 | May 26 02:52:13 PM PDT 24 | May 26 02:52:17 PM PDT 24 | 64874003 ps | ||
| T901 | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1794907982 | May 26 02:52:02 PM PDT 24 | May 26 02:52:04 PM PDT 24 | 71954880 ps | ||
| T902 | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2241574465 | May 26 02:52:14 PM PDT 24 | May 26 02:52:47 PM PDT 24 | 7570857914 ps | ||
| T903 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1830812269 | May 26 02:52:05 PM PDT 24 | May 26 02:52:06 PM PDT 24 | 11114298 ps | ||
| T904 | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1642749896 | May 26 02:52:16 PM PDT 24 | May 26 02:52:21 PM PDT 24 | 23553191 ps | ||
| T905 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4245688299 | May 26 02:51:54 PM PDT 24 | May 26 02:52:00 PM PDT 24 | 1153125969 ps | ||
| T906 | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3890349066 | May 26 02:51:53 PM PDT 24 | May 26 02:51:55 PM PDT 24 | 77702488 ps | ||
| T907 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.505844356 | May 26 02:52:13 PM PDT 24 | May 26 02:52:17 PM PDT 24 | 146649472 ps | ||
| T908 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1322024697 | May 26 02:52:03 PM PDT 24 | May 26 02:52:04 PM PDT 24 | 35936579 ps | ||
| T909 | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.41124784 | May 26 02:52:02 PM PDT 24 | May 26 02:52:07 PM PDT 24 | 357203703 ps | ||
| T910 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3912533421 | May 26 02:51:55 PM PDT 24 | May 26 02:51:58 PM PDT 24 | 113518201 ps | ||
| T911 | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4027945574 | May 26 02:52:08 PM PDT 24 | May 26 02:53:03 PM PDT 24 | 28175130443 ps | ||
| T147 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2612939324 | May 26 02:51:54 PM PDT 24 | May 26 02:51:57 PM PDT 24 | 194136756 ps | ||
| T912 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1216439590 | May 26 02:52:19 PM PDT 24 | May 26 02:52:28 PM PDT 24 | 387447185 ps | ||
| T913 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1261840016 | May 26 02:52:19 PM PDT 24 | May 26 02:52:24 PM PDT 24 | 19283448 ps | ||
| T914 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.602911657 | May 26 02:52:12 PM PDT 24 | May 26 02:52:16 PM PDT 24 | 56069084 ps | ||
| T915 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2592687830 | May 26 02:51:54 PM PDT 24 | May 26 02:51:57 PM PDT 24 | 18152333 ps | ||
| T916 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1053588357 | May 26 02:52:20 PM PDT 24 | May 26 02:52:29 PM PDT 24 | 4811801132 ps |
| Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.3823925397 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1608110692 ps |
| CPU time | 143.51 seconds |
| Started | May 26 03:16:06 PM PDT 24 |
| Finished | May 26 03:18:30 PM PDT 24 |
| Peak memory | 363884 kb |
| Host | smart-6cacbb6a-73dc-47af-92b3-bd8b95b6d8f6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823925397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.3823925397 |
| Directory | /workspace/46.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_bijection.1314127043 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 66267795541 ps |
| CPU time | 2156.1 seconds |
| Started | May 26 03:08:41 PM PDT 24 |
| Finished | May 26 03:44:38 PM PDT 24 |
| Peak memory | 211148 kb |
| Host | smart-d857650b-24ea-4434-ab90-876009e75fdd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314127043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .1314127043 |
| Directory | /workspace/20.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.3835916122 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 62053537260 ps |
| CPU time | 76.56 seconds |
| Started | May 26 03:07:32 PM PDT 24 |
| Finished | May 26 03:08:49 PM PDT 24 |
| Peak memory | 210744 kb |
| Host | smart-58292831-db88-44ac-b18f-66eaaeb05386 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835916122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.3835916122 |
| Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_regwen.392366330 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 51988574861 ps |
| CPU time | 939.2 seconds |
| Started | May 26 03:06:09 PM PDT 24 |
| Finished | May 26 03:21:50 PM PDT 24 |
| Peak memory | 374220 kb |
| Host | smart-1e69da05-cf69-4432-bcc4-5c6d34a520c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392366330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.392366330 |
| Directory | /workspace/11.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2716450899 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 803054392 ps |
| CPU time | 22.71 seconds |
| Started | May 26 03:08:35 PM PDT 24 |
| Finished | May 26 03:08:59 PM PDT 24 |
| Peak memory | 210716 kb |
| Host | smart-e5be3553-da0c-4ae7-aa4e-b716a4426fa3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2716450899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2716450899 |
| Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1081834337 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 679506969 ps |
| CPU time | 2.68 seconds |
| Started | May 26 02:52:07 PM PDT 24 |
| Finished | May 26 02:52:10 PM PDT 24 |
| Peak memory | 202860 kb |
| Host | smart-0b35409c-18fe-4003-9052-1a7808d5f565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081834337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.1081834337 |
| Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2878173378 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 57934990376 ps |
| CPU time | 320.57 seconds |
| Started | May 26 03:10:08 PM PDT 24 |
| Finished | May 26 03:15:30 PM PDT 24 |
| Peak memory | 210724 kb |
| Host | smart-64710b60-0f7b-4bcf-b3a9-2e0f4d45d2f7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878173378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.2878173378 |
| Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.3138858644 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 578781658 ps |
| CPU time | 2.01 seconds |
| Started | May 26 03:02:50 PM PDT 24 |
| Finished | May 26 03:02:53 PM PDT 24 |
| Peak memory | 222160 kb |
| Host | smart-b0970c82-6c6a-44a3-9f64-dc3874497493 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138858644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3138858644 |
| Directory | /workspace/0.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_regwen.2652642579 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 23324929191 ps |
| CPU time | 1444.78 seconds |
| Started | May 26 03:15:33 PM PDT 24 |
| Finished | May 26 03:39:38 PM PDT 24 |
| Peak memory | 380592 kb |
| Host | smart-569fa629-c9ed-4700-8541-851d1576f938 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652642579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2652642579 |
| Directory | /workspace/44.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_executable.1031332627 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 17312127933 ps |
| CPU time | 1689.21 seconds |
| Started | May 26 03:12:18 PM PDT 24 |
| Finished | May 26 03:40:28 PM PDT 24 |
| Peak memory | 376356 kb |
| Host | smart-58b40e3c-02d2-439e-9ea5-64f437d9e358 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031332627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.1031332627 |
| Directory | /workspace/33.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.2267043739 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 35157203 ps |
| CPU time | 0.66 seconds |
| Started | May 26 03:02:51 PM PDT 24 |
| Finished | May 26 03:02:52 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-1a299159-a1d9-4924-a1a0-2362a683874b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267043739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.2267043739 |
| Directory | /workspace/0.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2398988687 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 15414955379 ps |
| CPU time | 29.32 seconds |
| Started | May 26 02:51:58 PM PDT 24 |
| Finished | May 26 02:52:30 PM PDT 24 |
| Peak memory | 203040 kb |
| Host | smart-e3d3ce45-afe1-4d8e-a1d3-03c9f29efb8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398988687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.2398988687 |
| Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.644347276 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1035281240 ps |
| CPU time | 65.87 seconds |
| Started | May 26 03:02:51 PM PDT 24 |
| Finished | May 26 03:03:58 PM PDT 24 |
| Peak memory | 212464 kb |
| Host | smart-87de62aa-f4b9-4006-beb1-02173c01b22a |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644347276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_mem_partial_access.644347276 |
| Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.2487175374 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 344114861 ps |
| CPU time | 3.35 seconds |
| Started | May 26 03:03:06 PM PDT 24 |
| Finished | May 26 03:03:10 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-66d10d4f-d349-46c3-a233-f6513319eed3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487175374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2487175374 |
| Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4193590692 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 380584486 ps |
| CPU time | 1.65 seconds |
| Started | May 26 02:52:09 PM PDT 24 |
| Finished | May 26 02:52:11 PM PDT 24 |
| Peak memory | 211080 kb |
| Host | smart-380d4040-b39c-4691-ae00-3643deba3d4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193590692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.4193590692 |
| Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.3292202886 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 127753479660 ps |
| CPU time | 2849.64 seconds |
| Started | May 26 03:13:37 PM PDT 24 |
| Finished | May 26 04:01:08 PM PDT 24 |
| Peak memory | 213148 kb |
| Host | smart-34d4b7b0-3c8b-4799-a6a3-7b69bb493794 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292202886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.3292202886 |
| Directory | /workspace/37.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.305067039 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1637626019 ps |
| CPU time | 1.83 seconds |
| Started | May 26 02:52:08 PM PDT 24 |
| Finished | May 26 02:52:10 PM PDT 24 |
| Peak memory | 211060 kb |
| Host | smart-79e4cb6b-a693-4f22-ba03-23226a88ff39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305067039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.sram_ctrl_tl_intg_err.305067039 |
| Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1286960380 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 109300102 ps |
| CPU time | 1.56 seconds |
| Started | May 26 02:52:02 PM PDT 24 |
| Finished | May 26 02:52:05 PM PDT 24 |
| Peak memory | 202880 kb |
| Host | smart-8e281bd8-66e2-4eb3-8339-f0631ebe3c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286960380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.1286960380 |
| Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_regwen.1126458224 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 26370422957 ps |
| CPU time | 853.08 seconds |
| Started | May 26 03:03:04 PM PDT 24 |
| Finished | May 26 03:17:18 PM PDT 24 |
| Peak memory | 374292 kb |
| Host | smart-ec7f42f5-3190-4196-a92c-faa268ca8420 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126458224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.1126458224 |
| Directory | /workspace/1.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3887789569 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 18544013 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:51:55 PM PDT 24 |
| Finished | May 26 02:51:58 PM PDT 24 |
| Peak memory | 202588 kb |
| Host | smart-076862c9-f49d-450d-93ba-0df93dcf929d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887789569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.3887789569 |
| Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1642922078 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 459771343 ps |
| CPU time | 2.24 seconds |
| Started | May 26 02:51:58 PM PDT 24 |
| Finished | May 26 02:52:03 PM PDT 24 |
| Peak memory | 202400 kb |
| Host | smart-2014a635-cb98-4885-b4ae-4d5d23b246f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642922078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.1642922078 |
| Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3387644577 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 113096358 ps |
| CPU time | 0.72 seconds |
| Started | May 26 02:51:58 PM PDT 24 |
| Finished | May 26 02:52:01 PM PDT 24 |
| Peak memory | 202696 kb |
| Host | smart-6a6eb37a-09a3-4588-8b1b-e4e519ad340c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387644577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.3387644577 |
| Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2560952969 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 413277006 ps |
| CPU time | 3.53 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:52:02 PM PDT 24 |
| Peak memory | 210952 kb |
| Host | smart-575f92fc-5875-4a2b-867c-8191795ca3cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560952969 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2560952969 |
| Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1566691147 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 16930755 ps |
| CPU time | 0.64 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:52:00 PM PDT 24 |
| Peak memory | 202548 kb |
| Host | smart-e5194265-11b5-4e08-807d-7e0f3765f995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566691147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.1566691147 |
| Directory | /workspace/0.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2253755751 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 14218332080 ps |
| CPU time | 33.33 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:52:32 PM PDT 24 |
| Peak memory | 203064 kb |
| Host | smart-269f122d-3345-4564-8c71-7e6bb40528bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253755751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.2253755751 |
| Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2774679718 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 20997799 ps |
| CPU time | 0.7 seconds |
| Started | May 26 02:51:55 PM PDT 24 |
| Finished | May 26 02:51:58 PM PDT 24 |
| Peak memory | 202724 kb |
| Host | smart-c6762b25-23e3-49c3-9dc5-bdbfc72941b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774679718 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2774679718 |
| Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4245688299 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 1153125969 ps |
| CPU time | 4.47 seconds |
| Started | May 26 02:51:54 PM PDT 24 |
| Finished | May 26 02:52:00 PM PDT 24 |
| Peak memory | 211316 kb |
| Host | smart-b0e7fede-2c98-42de-8c19-1833b203e65e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245688299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.4245688299 |
| Directory | /workspace/0.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3867212501 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 486712106 ps |
| CPU time | 2.39 seconds |
| Started | May 26 02:51:54 PM PDT 24 |
| Finished | May 26 02:51:58 PM PDT 24 |
| Peak memory | 211088 kb |
| Host | smart-c277a140-939b-4272-aa8a-49f43567307c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867212501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.3867212501 |
| Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3638144643 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 55493103 ps |
| CPU time | 0.73 seconds |
| Started | May 26 02:51:55 PM PDT 24 |
| Finished | May 26 02:51:59 PM PDT 24 |
| Peak memory | 202648 kb |
| Host | smart-8a8e7e88-ac10-40af-9801-8f21726dfcf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638144643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.3638144643 |
| Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.842902237 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 451394827 ps |
| CPU time | 2.34 seconds |
| Started | May 26 02:51:55 PM PDT 24 |
| Finished | May 26 02:52:01 PM PDT 24 |
| Peak memory | 202904 kb |
| Host | smart-a8399c40-f487-4e4c-bff4-c80f3f8a5db3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842902237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.842902237 |
| Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2623753836 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 15826824 ps |
| CPU time | 0.66 seconds |
| Started | May 26 02:51:55 PM PDT 24 |
| Finished | May 26 02:51:59 PM PDT 24 |
| Peak memory | 202396 kb |
| Host | smart-46b49826-8ffd-4795-b258-7f06017bd700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623753836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2623753836 |
| Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.755750143 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1371212012 ps |
| CPU time | 3.49 seconds |
| Started | May 26 02:51:58 PM PDT 24 |
| Finished | May 26 02:52:04 PM PDT 24 |
| Peak memory | 210432 kb |
| Host | smart-5771945d-9b3a-41e5-bb79-cdf967c88bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755750143 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.755750143 |
| Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2890256854 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 41956767 ps |
| CPU time | 0.73 seconds |
| Started | May 26 02:51:59 PM PDT 24 |
| Finished | May 26 02:52:02 PM PDT 24 |
| Peak memory | 202640 kb |
| Host | smart-54727349-812c-4b76-975d-1c61bb1d3be0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890256854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.2890256854 |
| Directory | /workspace/1.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.620841114 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 7493505030 ps |
| CPU time | 54.31 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:52:53 PM PDT 24 |
| Peak memory | 203076 kb |
| Host | smart-0ca4ecf8-1c00-41c3-aa3f-2d7ded4e7236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620841114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.620841114 |
| Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1408982575 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 41629169 ps |
| CPU time | 0.78 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:51:59 PM PDT 24 |
| Peak memory | 202688 kb |
| Host | smart-3a6d629f-e871-4910-8190-219321fd8e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408982575 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.1408982575 |
| Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2822341012 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 243502638 ps |
| CPU time | 2.41 seconds |
| Started | May 26 02:51:54 PM PDT 24 |
| Finished | May 26 02:51:58 PM PDT 24 |
| Peak memory | 211124 kb |
| Host | smart-c9e94174-f7be-4973-b020-9f97ebf5a470 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822341012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.2822341012 |
| Directory | /workspace/1.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1479559057 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 327607169 ps |
| CPU time | 1.42 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:52:00 PM PDT 24 |
| Peak memory | 211088 kb |
| Host | smart-1b730c28-6846-4c81-859f-4a0e558eeb93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479559057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1479559057 |
| Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3065086156 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 364699113 ps |
| CPU time | 3.98 seconds |
| Started | May 26 02:52:01 PM PDT 24 |
| Finished | May 26 02:52:07 PM PDT 24 |
| Peak memory | 212304 kb |
| Host | smart-392c6c8b-47ee-4b2f-843f-6e765480bc92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065086156 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3065086156 |
| Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.785612570 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 27342569 ps |
| CPU time | 0.69 seconds |
| Started | May 26 02:52:09 PM PDT 24 |
| Finished | May 26 02:52:11 PM PDT 24 |
| Peak memory | 202704 kb |
| Host | smart-bf8cc515-6a32-4c5c-8320-221a0ca74d0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785612570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 10.sram_ctrl_csr_rw.785612570 |
| Directory | /workspace/10.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2241574465 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 7570857914 ps |
| CPU time | 31.24 seconds |
| Started | May 26 02:52:14 PM PDT 24 |
| Finished | May 26 02:52:47 PM PDT 24 |
| Peak memory | 203088 kb |
| Host | smart-bc6af276-ec32-406c-ab22-dbbecd9fb45e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241574465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2241574465 |
| Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3282464963 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 36157916 ps |
| CPU time | 0.82 seconds |
| Started | May 26 02:52:04 PM PDT 24 |
| Finished | May 26 02:52:06 PM PDT 24 |
| Peak memory | 202652 kb |
| Host | smart-c7ae8f83-d7a3-477c-9c30-a7c8760cdc63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282464963 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3282464963 |
| Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3999931556 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 67640732 ps |
| CPU time | 2.27 seconds |
| Started | May 26 02:52:01 PM PDT 24 |
| Finished | May 26 02:52:05 PM PDT 24 |
| Peak memory | 202968 kb |
| Host | smart-b751e3b2-829e-4b0d-971b-98cbdfa8777b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999931556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.3999931556 |
| Directory | /workspace/10.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.41124784 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 357203703 ps |
| CPU time | 3.84 seconds |
| Started | May 26 02:52:02 PM PDT 24 |
| Finished | May 26 02:52:07 PM PDT 24 |
| Peak memory | 211212 kb |
| Host | smart-6ea990b2-68dc-4790-b161-84cb5cee3baa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41124784 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.41124784 |
| Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4103868302 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 13559385 ps |
| CPU time | 0.7 seconds |
| Started | May 26 02:52:03 PM PDT 24 |
| Finished | May 26 02:52:05 PM PDT 24 |
| Peak memory | 202748 kb |
| Host | smart-dc3d3d90-2f91-4f44-93bb-c85a5cf8e6c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103868302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.4103868302 |
| Directory | /workspace/11.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4073323336 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 7584309197 ps |
| CPU time | 27.03 seconds |
| Started | May 26 02:52:00 PM PDT 24 |
| Finished | May 26 02:52:29 PM PDT 24 |
| Peak memory | 203060 kb |
| Host | smart-16ecc4c8-06be-4b4c-a480-1d46e6147cf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073323336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.4073323336 |
| Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4172604190 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 57647863 ps |
| CPU time | 0.78 seconds |
| Started | May 26 02:52:17 PM PDT 24 |
| Finished | May 26 02:52:23 PM PDT 24 |
| Peak memory | 202664 kb |
| Host | smart-7d433154-10e9-46e9-b63b-d70658572fc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172604190 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.4172604190 |
| Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.438623545 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 218324061 ps |
| CPU time | 3.84 seconds |
| Started | May 26 02:52:17 PM PDT 24 |
| Finished | May 26 02:52:26 PM PDT 24 |
| Peak memory | 211172 kb |
| Host | smart-a8b31d2a-eefa-48f3-a7c4-8d7355fdcfd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438623545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.438623545 |
| Directory | /workspace/11.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3567671859 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 1285168543 ps |
| CPU time | 3.73 seconds |
| Started | May 26 02:52:09 PM PDT 24 |
| Finished | May 26 02:52:14 PM PDT 24 |
| Peak memory | 211112 kb |
| Host | smart-cedc145e-958d-4d57-99c8-c207b685bdca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567671859 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3567671859 |
| Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2570563227 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 45942924 ps |
| CPU time | 0.65 seconds |
| Started | May 26 02:52:05 PM PDT 24 |
| Finished | May 26 02:52:07 PM PDT 24 |
| Peak memory | 202612 kb |
| Host | smart-e0be5d9b-ff18-4fe7-aa83-1c32b0520366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570563227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.2570563227 |
| Directory | /workspace/12.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1261858716 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 7254715786 ps |
| CPU time | 31.26 seconds |
| Started | May 26 02:52:04 PM PDT 24 |
| Finished | May 26 02:52:37 PM PDT 24 |
| Peak memory | 202996 kb |
| Host | smart-bb2ac579-17be-4514-8610-77b0106b76e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261858716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1261858716 |
| Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1801543 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 54453856 ps |
| CPU time | 0.69 seconds |
| Started | May 26 02:52:13 PM PDT 24 |
| Finished | May 26 02:52:15 PM PDT 24 |
| Peak memory | 202716 kb |
| Host | smart-9591fb63-01a1-46a4-a3ac-c3f58d24f370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801543 -assert nopostproc +UVM_TESTNAME=sram_ctrl _base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1801543 |
| Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.162430271 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 310949269 ps |
| CPU time | 2.78 seconds |
| Started | May 26 02:52:04 PM PDT 24 |
| Finished | May 26 02:52:08 PM PDT 24 |
| Peak memory | 211100 kb |
| Host | smart-535f0fe7-a55b-47e3-80cd-d999cfab445c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162430271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.162430271 |
| Directory | /workspace/12.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3575913398 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 308579087 ps |
| CPU time | 2.19 seconds |
| Started | May 26 02:52:14 PM PDT 24 |
| Finished | May 26 02:52:19 PM PDT 24 |
| Peak memory | 211092 kb |
| Host | smart-c095f8f9-a7c3-4f86-93cd-73ce3912e093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575913398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.3575913398 |
| Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1216439590 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 387447185 ps |
| CPU time | 3.85 seconds |
| Started | May 26 02:52:19 PM PDT 24 |
| Finished | May 26 02:52:28 PM PDT 24 |
| Peak memory | 211152 kb |
| Host | smart-8d7c7d75-90dd-4ebe-9def-9af743a7ac5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216439590 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1216439590 |
| Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1742717477 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 30949892 ps |
| CPU time | 0.63 seconds |
| Started | May 26 02:52:05 PM PDT 24 |
| Finished | May 26 02:52:06 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-cfc8231f-0b81-4987-bac6-86caa0bf2022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742717477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.1742717477 |
| Directory | /workspace/13.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.473496677 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 7378608408 ps |
| CPU time | 29.09 seconds |
| Started | May 26 02:52:03 PM PDT 24 |
| Finished | May 26 02:52:33 PM PDT 24 |
| Peak memory | 203056 kb |
| Host | smart-8804c596-dce1-470c-966f-0f33532ebaec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473496677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.473496677 |
| Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2490816043 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 63702661 ps |
| CPU time | 0.74 seconds |
| Started | May 26 02:52:15 PM PDT 24 |
| Finished | May 26 02:52:20 PM PDT 24 |
| Peak memory | 202688 kb |
| Host | smart-1e437287-9ef7-4e2c-9c64-14138f9d79c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490816043 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2490816043 |
| Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2876276986 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 64874003 ps |
| CPU time | 2.93 seconds |
| Started | May 26 02:52:13 PM PDT 24 |
| Finished | May 26 02:52:17 PM PDT 24 |
| Peak memory | 202968 kb |
| Host | smart-5eb08936-0cf7-4a4b-9485-663a63fde951 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876276986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.2876276986 |
| Directory | /workspace/13.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.769192216 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1204479790 ps |
| CPU time | 2.58 seconds |
| Started | May 26 02:52:16 PM PDT 24 |
| Finished | May 26 02:52:24 PM PDT 24 |
| Peak memory | 202888 kb |
| Host | smart-5f39e43e-251b-4581-a065-910e847c0aa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769192216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.sram_ctrl_tl_intg_err.769192216 |
| Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.956026633 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1758064776 ps |
| CPU time | 3.43 seconds |
| Started | May 26 02:52:11 PM PDT 24 |
| Finished | May 26 02:52:16 PM PDT 24 |
| Peak memory | 212008 kb |
| Host | smart-d85bfbb7-9486-46ea-8e0f-7d5d1acbeb89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956026633 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.956026633 |
| Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2948931264 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 46881599 ps |
| CPU time | 0.64 seconds |
| Started | May 26 02:52:14 PM PDT 24 |
| Finished | May 26 02:52:17 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-f8245161-091e-48d3-bbcf-996ec0faf8e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948931264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.2948931264 |
| Directory | /workspace/14.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1603169674 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 16143916333 ps |
| CPU time | 26.66 seconds |
| Started | May 26 02:52:22 PM PDT 24 |
| Finished | May 26 02:52:52 PM PDT 24 |
| Peak memory | 203056 kb |
| Host | smart-f6cd701e-c4cc-456a-a12b-1239942b3558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603169674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1603169674 |
| Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2970178444 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 55112714 ps |
| CPU time | 0.68 seconds |
| Started | May 26 02:52:15 PM PDT 24 |
| Finished | May 26 02:52:20 PM PDT 24 |
| Peak memory | 202712 kb |
| Host | smart-bf61a32b-9611-47bd-8b5e-c29521e8079d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970178444 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.2970178444 |
| Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1959959447 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 333542809 ps |
| CPU time | 2.21 seconds |
| Started | May 26 02:52:14 PM PDT 24 |
| Finished | May 26 02:52:19 PM PDT 24 |
| Peak memory | 202960 kb |
| Host | smart-01df4d22-5934-4bf8-909e-83da60026bf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959959447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.1959959447 |
| Directory | /workspace/14.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2933507507 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 194799914 ps |
| CPU time | 1.58 seconds |
| Started | May 26 02:52:13 PM PDT 24 |
| Finished | May 26 02:52:16 PM PDT 24 |
| Peak memory | 211084 kb |
| Host | smart-7f778d09-de7f-459e-98f2-668a9a362e1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933507507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.2933507507 |
| Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4278300560 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 355154493 ps |
| CPU time | 3.57 seconds |
| Started | May 26 02:52:21 PM PDT 24 |
| Finished | May 26 02:52:28 PM PDT 24 |
| Peak memory | 210964 kb |
| Host | smart-0334df09-ec4a-4a0c-ac7d-6ae40e61b569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278300560 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.4278300560 |
| Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4288442181 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 16068397 ps |
| CPU time | 0.68 seconds |
| Started | May 26 02:52:13 PM PDT 24 |
| Finished | May 26 02:52:15 PM PDT 24 |
| Peak memory | 202652 kb |
| Host | smart-8bfa8cce-5257-4da7-aa61-bb4e80d34209 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288442181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.4288442181 |
| Directory | /workspace/15.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2674872300 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 14788296480 ps |
| CPU time | 32.78 seconds |
| Started | May 26 02:52:14 PM PDT 24 |
| Finished | May 26 02:52:50 PM PDT 24 |
| Peak memory | 203108 kb |
| Host | smart-aa9f7a48-dcda-4e1f-ae25-9cea122e5857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674872300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.2674872300 |
| Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.772247305 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 71886184 ps |
| CPU time | 0.7 seconds |
| Started | May 26 02:52:14 PM PDT 24 |
| Finished | May 26 02:52:17 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-0aa72d1f-8455-4e83-a252-9e69b8f7cb8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772247305 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.772247305 |
| Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3721301127 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 196671047 ps |
| CPU time | 2 seconds |
| Started | May 26 02:52:16 PM PDT 24 |
| Finished | May 26 02:52:23 PM PDT 24 |
| Peak memory | 202984 kb |
| Host | smart-3ee22db5-85a7-4e84-97a1-aa8efef09d95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721301127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.3721301127 |
| Directory | /workspace/15.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2279827357 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 344025862 ps |
| CPU time | 3.1 seconds |
| Started | May 26 02:52:18 PM PDT 24 |
| Finished | May 26 02:52:26 PM PDT 24 |
| Peak memory | 211036 kb |
| Host | smart-28183c93-e3f8-4218-a1ef-8166c84bb22e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279827357 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2279827357 |
| Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1263519323 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 36578006 ps |
| CPU time | 0.66 seconds |
| Started | May 26 02:52:11 PM PDT 24 |
| Finished | May 26 02:52:14 PM PDT 24 |
| Peak memory | 202676 kb |
| Host | smart-e272e7f0-0782-4956-bfab-d5406d96f3e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263519323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.1263519323 |
| Directory | /workspace/16.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2251342883 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 10649304918 ps |
| CPU time | 27.01 seconds |
| Started | May 26 02:52:16 PM PDT 24 |
| Finished | May 26 02:52:48 PM PDT 24 |
| Peak memory | 203108 kb |
| Host | smart-53afa4af-a945-4ce9-9f45-b7301d2b8e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251342883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2251342883 |
| Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1184882001 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 25588267 ps |
| CPU time | 0.87 seconds |
| Started | May 26 02:52:15 PM PDT 24 |
| Finished | May 26 02:52:19 PM PDT 24 |
| Peak memory | 202680 kb |
| Host | smart-a68301af-9201-456d-85df-196bd5019366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184882001 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.1184882001 |
| Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2853300214 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 70350323 ps |
| CPU time | 2.38 seconds |
| Started | May 26 02:52:15 PM PDT 24 |
| Finished | May 26 02:52:22 PM PDT 24 |
| Peak memory | 211168 kb |
| Host | smart-6c9a55d3-b914-40a8-be07-44d05eda4b7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853300214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.2853300214 |
| Directory | /workspace/16.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1053588357 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 4811801132 ps |
| CPU time | 4.55 seconds |
| Started | May 26 02:52:20 PM PDT 24 |
| Finished | May 26 02:52:29 PM PDT 24 |
| Peak memory | 211048 kb |
| Host | smart-56abe35e-b8c5-468a-8814-39be20a59d52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053588357 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1053588357 |
| Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.602466724 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 34049674 ps |
| CPU time | 0.63 seconds |
| Started | May 26 02:52:15 PM PDT 24 |
| Finished | May 26 02:52:20 PM PDT 24 |
| Peak memory | 202704 kb |
| Host | smart-4b65ef06-b28d-4f83-81b7-41b33f95320a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602466724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.602466724 |
| Directory | /workspace/17.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1864451564 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 7059769940 ps |
| CPU time | 51.99 seconds |
| Started | May 26 02:52:14 PM PDT 24 |
| Finished | May 26 02:53:09 PM PDT 24 |
| Peak memory | 203108 kb |
| Host | smart-5bbe628e-6b44-476b-b3dc-f73112d29705 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864451564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.1864451564 |
| Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1588080908 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 14933580 ps |
| CPU time | 0.74 seconds |
| Started | May 26 02:52:22 PM PDT 24 |
| Finished | May 26 02:52:26 PM PDT 24 |
| Peak memory | 202680 kb |
| Host | smart-c5797f15-c8e4-487c-ab0a-f108bd95c6eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588080908 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1588080908 |
| Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.505844356 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 146649472 ps |
| CPU time | 2.48 seconds |
| Started | May 26 02:52:13 PM PDT 24 |
| Finished | May 26 02:52:17 PM PDT 24 |
| Peak memory | 211192 kb |
| Host | smart-0708bf74-3e1d-4327-87e3-eac6da5de5af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505844356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.505844356 |
| Directory | /workspace/17.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.162823692 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 201558145 ps |
| CPU time | 1.85 seconds |
| Started | May 26 02:52:18 PM PDT 24 |
| Finished | May 26 02:52:24 PM PDT 24 |
| Peak memory | 211096 kb |
| Host | smart-3a074025-6697-49fd-9b75-464feb27879c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162823692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.sram_ctrl_tl_intg_err.162823692 |
| Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1350908523 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1421090781 ps |
| CPU time | 3.75 seconds |
| Started | May 26 02:52:15 PM PDT 24 |
| Finished | May 26 02:52:23 PM PDT 24 |
| Peak memory | 211152 kb |
| Host | smart-00974245-c219-4450-a1b0-f5baeefbfd29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350908523 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1350908523 |
| Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3281890699 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 22152298 ps |
| CPU time | 0.67 seconds |
| Started | May 26 02:52:15 PM PDT 24 |
| Finished | May 26 02:52:19 PM PDT 24 |
| Peak memory | 202708 kb |
| Host | smart-9668ac92-df65-44d6-9170-15d824546d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281890699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.3281890699 |
| Directory | /workspace/18.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1629473890 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 63998942173 ps |
| CPU time | 67.08 seconds |
| Started | May 26 02:52:13 PM PDT 24 |
| Finished | May 26 02:53:22 PM PDT 24 |
| Peak memory | 203108 kb |
| Host | smart-f52e8442-43a7-4d41-be25-6e5d236b5878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629473890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1629473890 |
| Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.732447575 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 36240805 ps |
| CPU time | 0.69 seconds |
| Started | May 26 02:52:13 PM PDT 24 |
| Finished | May 26 02:52:16 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-39e7c5bf-fe1f-40c3-89d4-7b985701a441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732447575 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.732447575 |
| Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2213425744 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 181173703 ps |
| CPU time | 4.37 seconds |
| Started | May 26 02:52:22 PM PDT 24 |
| Finished | May 26 02:52:30 PM PDT 24 |
| Peak memory | 211168 kb |
| Host | smart-9eaa703d-30fb-4b35-93cb-66e0a9de7e21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213425744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.2213425744 |
| Directory | /workspace/18.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3431109743 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 711662934 ps |
| CPU time | 3.7 seconds |
| Started | May 26 02:52:22 PM PDT 24 |
| Finished | May 26 02:52:29 PM PDT 24 |
| Peak memory | 211932 kb |
| Host | smart-859fcf88-c7f0-45de-88e5-52f83dd2ab2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431109743 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3431109743 |
| Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1261840016 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 19283448 ps |
| CPU time | 0.71 seconds |
| Started | May 26 02:52:19 PM PDT 24 |
| Finished | May 26 02:52:24 PM PDT 24 |
| Peak memory | 202680 kb |
| Host | smart-915ee5cd-5702-493d-a7c2-bbb764fa18b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261840016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.1261840016 |
| Directory | /workspace/19.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1373033944 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 15355858874 ps |
| CPU time | 28.73 seconds |
| Started | May 26 02:52:19 PM PDT 24 |
| Finished | May 26 02:52:52 PM PDT 24 |
| Peak memory | 203212 kb |
| Host | smart-2c59a3d2-d195-4b23-a18e-982063ed2966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373033944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1373033944 |
| Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1341845121 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 16967455 ps |
| CPU time | 0.79 seconds |
| Started | May 26 02:52:14 PM PDT 24 |
| Finished | May 26 02:52:18 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-c9f6bf7b-b4b0-4410-82b0-82ae5d727baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341845121 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1341845121 |
| Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3328394632 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 180518088 ps |
| CPU time | 3.48 seconds |
| Started | May 26 02:52:15 PM PDT 24 |
| Finished | May 26 02:52:22 PM PDT 24 |
| Peak memory | 203040 kb |
| Host | smart-9fec3226-2596-4de0-b8e1-4687830d62c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328394632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.3328394632 |
| Directory | /workspace/19.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3348179062 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 22471430 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:51:57 PM PDT 24 |
| Finished | May 26 02:52:00 PM PDT 24 |
| Peak memory | 202700 kb |
| Host | smart-809a8915-1c41-45e1-a2b1-910ffdb4609c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348179062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.3348179062 |
| Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2486405397 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 66735642 ps |
| CPU time | 1.42 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:52:01 PM PDT 24 |
| Peak memory | 202888 kb |
| Host | smart-7c771e6c-4945-42a5-ab82-12b9fa2d1bfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486405397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.2486405397 |
| Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3443065768 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 18985787 ps |
| CPU time | 0.71 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:52:00 PM PDT 24 |
| Peak memory | 202716 kb |
| Host | smart-ed0fc8eb-0d52-41f8-b0c8-d417249e20b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443065768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.3443065768 |
| Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2336861132 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 4274172582 ps |
| CPU time | 3.58 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:52:02 PM PDT 24 |
| Peak memory | 211044 kb |
| Host | smart-e1f8fb5c-8ae2-48d1-ad0b-b0054be80556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336861132 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.2336861132 |
| Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3873751108 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 20647861 ps |
| CPU time | 0.65 seconds |
| Started | May 26 02:51:58 PM PDT 24 |
| Finished | May 26 02:52:01 PM PDT 24 |
| Peak memory | 202624 kb |
| Host | smart-43fbe088-4c53-4586-bbbc-bc23c3fe8393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873751108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.3873751108 |
| Directory | /workspace/2.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3456673795 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 40446345 ps |
| CPU time | 0.79 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:52:00 PM PDT 24 |
| Peak memory | 202692 kb |
| Host | smart-1b0d8a94-590f-424b-9da5-d10978efdebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456673795 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3456673795 |
| Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2428591449 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 43568979 ps |
| CPU time | 3.59 seconds |
| Started | May 26 02:51:56 PM PDT 24 |
| Finished | May 26 02:52:03 PM PDT 24 |
| Peak memory | 211140 kb |
| Host | smart-3bd76960-8acd-4988-ac3e-d7efe26f4fbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428591449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.2428591449 |
| Directory | /workspace/2.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2781968357 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 44157510 ps |
| CPU time | 0.71 seconds |
| Started | May 26 02:51:57 PM PDT 24 |
| Finished | May 26 02:52:00 PM PDT 24 |
| Peak memory | 202640 kb |
| Host | smart-db997c2f-4517-4ecb-8850-47ec00e7af32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781968357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.2781968357 |
| Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1064838108 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 65632645 ps |
| CPU time | 1.34 seconds |
| Started | May 26 02:51:54 PM PDT 24 |
| Finished | May 26 02:51:57 PM PDT 24 |
| Peak memory | 202880 kb |
| Host | smart-947dc717-1163-40dd-bc5e-a081182797a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064838108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.1064838108 |
| Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.866943355 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 53471256 ps |
| CPU time | 0.67 seconds |
| Started | May 26 02:51:59 PM PDT 24 |
| Finished | May 26 02:52:01 PM PDT 24 |
| Peak memory | 202612 kb |
| Host | smart-24632535-75f7-4a6f-beac-aee156dc3091 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866943355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_reset.866943355 |
| Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2129674324 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 716593964 ps |
| CPU time | 3.56 seconds |
| Started | May 26 02:51:59 PM PDT 24 |
| Finished | May 26 02:52:05 PM PDT 24 |
| Peak memory | 210912 kb |
| Host | smart-38aa9c64-19c2-4a04-8752-dcb4f951bc01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129674324 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2129674324 |
| Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2592687830 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 18152333 ps |
| CPU time | 0.68 seconds |
| Started | May 26 02:51:54 PM PDT 24 |
| Finished | May 26 02:51:57 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-4375ab37-25b8-4867-9e29-52da2206fced |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592687830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.2592687830 |
| Directory | /workspace/3.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1208059307 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3702734252 ps |
| CPU time | 30.5 seconds |
| Started | May 26 02:51:54 PM PDT 24 |
| Finished | May 26 02:52:26 PM PDT 24 |
| Peak memory | 203056 kb |
| Host | smart-464b3cf4-507f-4293-832c-df94dac60a71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208059307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1208059307 |
| Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3890349066 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 77702488 ps |
| CPU time | 0.83 seconds |
| Started | May 26 02:51:53 PM PDT 24 |
| Finished | May 26 02:51:55 PM PDT 24 |
| Peak memory | 202696 kb |
| Host | smart-909be5b3-7937-42ff-b5e7-530290828c58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890349066 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.3890349066 |
| Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2511300919 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 132208238 ps |
| CPU time | 3.99 seconds |
| Started | May 26 02:51:54 PM PDT 24 |
| Finished | May 26 02:52:00 PM PDT 24 |
| Peak memory | 211208 kb |
| Host | smart-e5eebeaa-ef59-4ca9-a151-64d9f0c43ee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511300919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.2511300919 |
| Directory | /workspace/3.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.363963142 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 249728496 ps |
| CPU time | 1.41 seconds |
| Started | May 26 02:51:54 PM PDT 24 |
| Finished | May 26 02:51:58 PM PDT 24 |
| Peak memory | 211156 kb |
| Host | smart-eb302a87-3212-4747-b585-9b1cbd66a839 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363963142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.sram_ctrl_tl_intg_err.363963142 |
| Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1588424504 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 28890762 ps |
| CPU time | 0.73 seconds |
| Started | May 26 02:52:06 PM PDT 24 |
| Finished | May 26 02:52:08 PM PDT 24 |
| Peak memory | 202640 kb |
| Host | smart-21e6fe41-97d6-45dc-853c-b848da1ba509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588424504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.1588424504 |
| Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3010617249 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 74365692 ps |
| CPU time | 1.35 seconds |
| Started | May 26 02:51:59 PM PDT 24 |
| Finished | May 26 02:52:02 PM PDT 24 |
| Peak memory | 202840 kb |
| Host | smart-7a41d4fe-8197-47b7-859e-0a87cee1a04e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010617249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.3010617249 |
| Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4243697729 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 19829076 ps |
| CPU time | 0.7 seconds |
| Started | May 26 02:51:53 PM PDT 24 |
| Finished | May 26 02:51:54 PM PDT 24 |
| Peak memory | 202696 kb |
| Host | smart-3503ef99-96a5-406b-96f3-fc422f3f6c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243697729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.4243697729 |
| Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1137325455 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 1451034278 ps |
| CPU time | 3.91 seconds |
| Started | May 26 02:52:04 PM PDT 24 |
| Finished | May 26 02:52:09 PM PDT 24 |
| Peak memory | 211156 kb |
| Host | smart-77f7945f-ea34-4137-86dc-bd3d2087e79a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137325455 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1137325455 |
| Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3912533421 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 113518201 ps |
| CPU time | 0.65 seconds |
| Started | May 26 02:51:55 PM PDT 24 |
| Finished | May 26 02:51:58 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-e29dd4da-6b56-46b6-ab53-f0f37f51a5ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912533421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.3912533421 |
| Directory | /workspace/4.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1670979400 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 32171926594 ps |
| CPU time | 55.61 seconds |
| Started | May 26 02:51:54 PM PDT 24 |
| Finished | May 26 02:52:50 PM PDT 24 |
| Peak memory | 203064 kb |
| Host | smart-223efcae-73b6-491f-806c-63e884e0e808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670979400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.1670979400 |
| Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3358569010 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 99690490 ps |
| CPU time | 0.82 seconds |
| Started | May 26 02:52:16 PM PDT 24 |
| Finished | May 26 02:52:22 PM PDT 24 |
| Peak memory | 202696 kb |
| Host | smart-d05b5a2f-374e-4c59-acbd-753688831996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358569010 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3358569010 |
| Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3841478106 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 104758500 ps |
| CPU time | 2.52 seconds |
| Started | May 26 02:51:55 PM PDT 24 |
| Finished | May 26 02:52:01 PM PDT 24 |
| Peak memory | 211212 kb |
| Host | smart-215e2ad6-0748-463c-adc6-b113519eb523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841478106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.3841478106 |
| Directory | /workspace/4.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2612939324 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 194136756 ps |
| CPU time | 1.57 seconds |
| Started | May 26 02:51:54 PM PDT 24 |
| Finished | May 26 02:51:57 PM PDT 24 |
| Peak memory | 202892 kb |
| Host | smart-1098479c-d44f-49a0-aa8f-9bd84fddf3a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612939324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.2612939324 |
| Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2960628577 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 752078988 ps |
| CPU time | 4.61 seconds |
| Started | May 26 02:52:17 PM PDT 24 |
| Finished | May 26 02:52:27 PM PDT 24 |
| Peak memory | 211184 kb |
| Host | smart-5f93fb5c-7e4b-4c61-b2bf-3dd35d0c0923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960628577 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2960628577 |
| Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3018005061 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 26386778 ps |
| CPU time | 0.69 seconds |
| Started | May 26 02:52:12 PM PDT 24 |
| Finished | May 26 02:52:14 PM PDT 24 |
| Peak memory | 202388 kb |
| Host | smart-11ceb8cf-88e7-4561-a5fc-3ee3800e2ae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018005061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.3018005061 |
| Directory | /workspace/5.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1447550960 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 44397023203 ps |
| CPU time | 60.48 seconds |
| Started | May 26 02:52:04 PM PDT 24 |
| Finished | May 26 02:53:06 PM PDT 24 |
| Peak memory | 203136 kb |
| Host | smart-2023a239-4fc7-4b15-a2db-af581af58e13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447550960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.1447550960 |
| Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1459997435 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 34091468 ps |
| CPU time | 0.75 seconds |
| Started | May 26 02:52:01 PM PDT 24 |
| Finished | May 26 02:52:04 PM PDT 24 |
| Peak memory | 202692 kb |
| Host | smart-6d00d729-e482-4377-b67b-f686ed8c1c8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459997435 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1459997435 |
| Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1435858677 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 664365323 ps |
| CPU time | 2.26 seconds |
| Started | May 26 02:52:01 PM PDT 24 |
| Finished | May 26 02:52:05 PM PDT 24 |
| Peak memory | 202984 kb |
| Host | smart-053327fe-497f-4419-86e6-85a217441b16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435858677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.1435858677 |
| Directory | /workspace/5.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.697470891 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 351724914 ps |
| CPU time | 3.56 seconds |
| Started | May 26 02:52:03 PM PDT 24 |
| Finished | May 26 02:52:08 PM PDT 24 |
| Peak memory | 210924 kb |
| Host | smart-6d498749-5b63-42f1-b656-0c9afd69fa94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697470891 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.697470891 |
| Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.770276789 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 13041794 ps |
| CPU time | 0.71 seconds |
| Started | May 26 02:52:04 PM PDT 24 |
| Finished | May 26 02:52:05 PM PDT 24 |
| Peak memory | 202628 kb |
| Host | smart-38950f52-c2dc-49a9-9b81-44008ec28990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770276789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 6.sram_ctrl_csr_rw.770276789 |
| Directory | /workspace/6.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.994346124 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 14221025443 ps |
| CPU time | 29.85 seconds |
| Started | May 26 02:52:03 PM PDT 24 |
| Finished | May 26 02:52:34 PM PDT 24 |
| Peak memory | 203028 kb |
| Host | smart-c3327612-ecad-4e99-a8d5-51b4b63c3a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994346124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.994346124 |
| Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1844704083 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 196821419 ps |
| CPU time | 0.75 seconds |
| Started | May 26 02:52:00 PM PDT 24 |
| Finished | May 26 02:52:03 PM PDT 24 |
| Peak memory | 202636 kb |
| Host | smart-ab28a72c-fc8f-4d22-a37d-18d9d08e3bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844704083 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1844704083 |
| Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2070955633 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 52214751 ps |
| CPU time | 2.11 seconds |
| Started | May 26 02:52:17 PM PDT 24 |
| Finished | May 26 02:52:24 PM PDT 24 |
| Peak memory | 211152 kb |
| Host | smart-11d15bcb-5079-495c-887d-c20187672b30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070955633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.2070955633 |
| Directory | /workspace/6.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2661797653 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 752920850 ps |
| CPU time | 4.8 seconds |
| Started | May 26 02:52:07 PM PDT 24 |
| Finished | May 26 02:52:12 PM PDT 24 |
| Peak memory | 211176 kb |
| Host | smart-94b7d974-4faf-48a5-87e7-1e9be12c4d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661797653 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2661797653 |
| Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1544178283 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 16674647 ps |
| CPU time | 0.66 seconds |
| Started | May 26 02:52:13 PM PDT 24 |
| Finished | May 26 02:52:15 PM PDT 24 |
| Peak memory | 202664 kb |
| Host | smart-56ebf4d5-7cd7-4672-b08d-50d5957c85f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544178283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.1544178283 |
| Directory | /workspace/7.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2499951155 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 14495446832 ps |
| CPU time | 52.76 seconds |
| Started | May 26 02:52:04 PM PDT 24 |
| Finished | May 26 02:52:58 PM PDT 24 |
| Peak memory | 203052 kb |
| Host | smart-6d481db4-00b1-470d-87a5-fd4e986d9239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499951155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2499951155 |
| Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3262675661 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 44342328 ps |
| CPU time | 0.76 seconds |
| Started | May 26 02:52:12 PM PDT 24 |
| Finished | May 26 02:52:14 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-57232afc-69b0-4a40-aeed-b10fba82c5df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262675661 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3262675661 |
| Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1378904585 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 615728920 ps |
| CPU time | 5.02 seconds |
| Started | May 26 02:52:11 PM PDT 24 |
| Finished | May 26 02:52:17 PM PDT 24 |
| Peak memory | 211224 kb |
| Host | smart-d521712b-9379-46d5-929a-204963b8179d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378904585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.1378904585 |
| Directory | /workspace/7.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.858737580 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 187094025 ps |
| CPU time | 1.66 seconds |
| Started | May 26 02:52:10 PM PDT 24 |
| Finished | May 26 02:52:12 PM PDT 24 |
| Peak memory | 202892 kb |
| Host | smart-7824d0e3-562f-4b51-8444-4069c47b328d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858737580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.sram_ctrl_tl_intg_err.858737580 |
| Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3812871856 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 363554781 ps |
| CPU time | 3.65 seconds |
| Started | May 26 02:52:10 PM PDT 24 |
| Finished | May 26 02:52:14 PM PDT 24 |
| Peak memory | 212796 kb |
| Host | smart-f4c15f6b-fd3c-46ad-a813-8a9ca39c3129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812871856 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3812871856 |
| Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1322024697 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 35936579 ps |
| CPU time | 0.67 seconds |
| Started | May 26 02:52:03 PM PDT 24 |
| Finished | May 26 02:52:04 PM PDT 24 |
| Peak memory | 202700 kb |
| Host | smart-c8ca74bd-7ba3-463e-b8a6-0cd71a5830c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322024697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.1322024697 |
| Directory | /workspace/8.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3386613232 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 7692225721 ps |
| CPU time | 26.61 seconds |
| Started | May 26 02:52:01 PM PDT 24 |
| Finished | May 26 02:52:30 PM PDT 24 |
| Peak memory | 203092 kb |
| Host | smart-1597625a-6921-4080-a0dc-73317d2eca14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386613232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3386613232 |
| Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1642749896 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 23553191 ps |
| CPU time | 0.76 seconds |
| Started | May 26 02:52:16 PM PDT 24 |
| Finished | May 26 02:52:21 PM PDT 24 |
| Peak memory | 202696 kb |
| Host | smart-46ababf5-5d22-4fdd-ba1e-aafe6786d2ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642749896 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1642749896 |
| Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.602911657 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 56069084 ps |
| CPU time | 2.59 seconds |
| Started | May 26 02:52:12 PM PDT 24 |
| Finished | May 26 02:52:16 PM PDT 24 |
| Peak memory | 211820 kb |
| Host | smart-f7184abc-8006-4e22-bff4-663c8871c561 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602911657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.602911657 |
| Directory | /workspace/8.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3736871843 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 80162545 ps |
| CPU time | 1.55 seconds |
| Started | May 26 02:52:14 PM PDT 24 |
| Finished | May 26 02:52:19 PM PDT 24 |
| Peak memory | 211116 kb |
| Host | smart-639b9858-8883-4ef1-8760-e5f256268bc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736871843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.3736871843 |
| Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2347220869 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 361967765 ps |
| CPU time | 3.95 seconds |
| Started | May 26 02:52:01 PM PDT 24 |
| Finished | May 26 02:52:07 PM PDT 24 |
| Peak memory | 211120 kb |
| Host | smart-8bd631ab-9dee-4796-b626-8c23de296367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347220869 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.2347220869 |
| Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1830812269 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 11114298 ps |
| CPU time | 0.63 seconds |
| Started | May 26 02:52:05 PM PDT 24 |
| Finished | May 26 02:52:06 PM PDT 24 |
| Peak memory | 202668 kb |
| Host | smart-65d0f8e8-b5c1-4338-9897-9e049705bc25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830812269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.1830812269 |
| Directory | /workspace/9.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4027945574 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 28175130443 ps |
| CPU time | 54.41 seconds |
| Started | May 26 02:52:08 PM PDT 24 |
| Finished | May 26 02:53:03 PM PDT 24 |
| Peak memory | 203036 kb |
| Host | smart-0850eff8-d408-4713-a0dd-e06eb1638c06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027945574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.4027945574 |
| Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1794907982 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 71954880 ps |
| CPU time | 0.83 seconds |
| Started | May 26 02:52:02 PM PDT 24 |
| Finished | May 26 02:52:04 PM PDT 24 |
| Peak memory | 202676 kb |
| Host | smart-35ea22a4-5bd2-4543-9fa0-6343a0deb3f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794907982 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1794907982 |
| Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.242009965 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 88863011 ps |
| CPU time | 3.16 seconds |
| Started | May 26 02:52:17 PM PDT 24 |
| Finished | May 26 02:52:25 PM PDT 24 |
| Peak memory | 219244 kb |
| Host | smart-ea057046-3666-4344-8e0a-978fd4016f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242009965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.242009965 |
| Directory | /workspace/9.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.874602620 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 302163039 ps |
| CPU time | 1.48 seconds |
| Started | May 26 02:52:01 PM PDT 24 |
| Finished | May 26 02:52:04 PM PDT 24 |
| Peak memory | 202896 kb |
| Host | smart-d322287a-2156-454a-bec4-fda79c451675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874602620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.sram_ctrl_tl_intg_err.874602620 |
| Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_bijection.1209196222 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 124976541483 ps |
| CPU time | 1382.88 seconds |
| Started | May 26 03:02:40 PM PDT 24 |
| Finished | May 26 03:25:43 PM PDT 24 |
| Peak memory | 210752 kb |
| Host | smart-a61c77a4-5542-41f2-b1a8-1d447607df11 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209196222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 1209196222 |
| Directory | /workspace/0.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_executable.3034234507 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 10210917794 ps |
| CPU time | 1275.39 seconds |
| Started | May 26 03:02:43 PM PDT 24 |
| Finished | May 26 03:24:00 PM PDT 24 |
| Peak memory | 378912 kb |
| Host | smart-22fb0979-214e-490f-8fea-00248335075a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034234507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.3034234507 |
| Directory | /workspace/0.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.597643134 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 47794884293 ps |
| CPU time | 70.7 seconds |
| Started | May 26 03:02:44 PM PDT 24 |
| Finished | May 26 03:03:55 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-f623ab72-a517-497b-a8a5-f1b5241b99ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597643134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca lation.597643134 |
| Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.1724720588 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2876958116 ps |
| CPU time | 47.26 seconds |
| Started | May 26 03:02:36 PM PDT 24 |
| Finished | May 26 03:03:24 PM PDT 24 |
| Peak memory | 290500 kb |
| Host | smart-c166eae7-fa97-4c77-9ad1-aedbe453c93d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724720588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.1724720588 |
| Directory | /workspace/0.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.24347471 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 28234545816 ps |
| CPU time | 341.76 seconds |
| Started | May 26 03:02:51 PM PDT 24 |
| Finished | May 26 03:08:33 PM PDT 24 |
| Peak memory | 210604 kb |
| Host | smart-81538d5d-c3c8-4402-af00-ace2bb4eedb2 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24347471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m em_walk.24347471 |
| Directory | /workspace/0.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.2436455819 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 36905303989 ps |
| CPU time | 1153.35 seconds |
| Started | May 26 03:02:37 PM PDT 24 |
| Finished | May 26 03:21:51 PM PDT 24 |
| Peak memory | 376424 kb |
| Host | smart-5a493bc4-3bc3-4dad-8c14-7c49f31e4ade |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436455819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.2436455819 |
| Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.78493040 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 6847321962 ps |
| CPU time | 183.85 seconds |
| Started | May 26 03:02:38 PM PDT 24 |
| Finished | May 26 03:05:42 PM PDT 24 |
| Peak memory | 368096 kb |
| Host | smart-d80ac58b-91de-43e5-b897-20fc21fc4ab0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78493040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sra m_ctrl_partial_access.78493040 |
| Directory | /workspace/0.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.823098305 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 8450429619 ps |
| CPU time | 441.96 seconds |
| Started | May 26 03:02:37 PM PDT 24 |
| Finished | May 26 03:10:00 PM PDT 24 |
| Peak memory | 202484 kb |
| Host | smart-a1ebe40d-98cf-4382-a09e-805a17dccc89 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823098305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.sram_ctrl_partial_access_b2b.823098305 |
| Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.3408386782 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1680433867 ps |
| CPU time | 3.83 seconds |
| Started | May 26 03:02:50 PM PDT 24 |
| Finished | May 26 03:02:55 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-fa59677b-5a6b-4f1d-9294-81742f61d3b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408386782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3408386782 |
| Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_regwen.3988944384 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1400513905 ps |
| CPU time | 205.03 seconds |
| Started | May 26 03:02:43 PM PDT 24 |
| Finished | May 26 03:06:09 PM PDT 24 |
| Peak memory | 332040 kb |
| Host | smart-d6860afa-eb8f-486c-b2dc-93cdfc9d421f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988944384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3988944384 |
| Directory | /workspace/0.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_smoke.1157803431 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 683753307 ps |
| CPU time | 8.81 seconds |
| Started | May 26 03:02:29 PM PDT 24 |
| Finished | May 26 03:02:38 PM PDT 24 |
| Peak memory | 216604 kb |
| Host | smart-e51ccb50-014d-4ba3-9d52-09253c956392 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157803431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1157803431 |
| Directory | /workspace/0.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1761860781 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 1992286890 ps |
| CPU time | 25.15 seconds |
| Started | May 26 03:02:51 PM PDT 24 |
| Finished | May 26 03:03:17 PM PDT 24 |
| Peak memory | 210796 kb |
| Host | smart-6df16140-b0db-47e4-826a-dc0b50ace306 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1761860781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1761860781 |
| Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4191815889 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 7168054106 ps |
| CPU time | 424.94 seconds |
| Started | May 26 03:02:37 PM PDT 24 |
| Finished | May 26 03:09:42 PM PDT 24 |
| Peak memory | 202464 kb |
| Host | smart-57186d12-a6e0-48a8-9c18-52224f7d70a7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191815889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.4191815889 |
| Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3134202182 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1423725976 ps |
| CPU time | 6.96 seconds |
| Started | May 26 03:02:45 PM PDT 24 |
| Finished | May 26 03:02:53 PM PDT 24 |
| Peak memory | 210624 kb |
| Host | smart-c59b57f6-0652-4f6f-9497-45aaf0a0c16a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134202182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3134202182 |
| Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.2987195816 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 22905210 ps |
| CPU time | 0.67 seconds |
| Started | May 26 03:03:08 PM PDT 24 |
| Finished | May 26 03:03:09 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-011dece3-2ee6-432d-8ca5-8ef5b99e3209 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987195816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2987195816 |
| Directory | /workspace/1.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_bijection.3896260364 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 51477285557 ps |
| CPU time | 1327.67 seconds |
| Started | May 26 03:02:58 PM PDT 24 |
| Finished | May 26 03:25:07 PM PDT 24 |
| Peak memory | 210656 kb |
| Host | smart-6df881af-9a1b-43ec-b2db-4279fa7443ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896260364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 3896260364 |
| Directory | /workspace/1.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_executable.1000553924 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 42570044414 ps |
| CPU time | 789.58 seconds |
| Started | May 26 03:03:05 PM PDT 24 |
| Finished | May 26 03:16:15 PM PDT 24 |
| Peak memory | 376308 kb |
| Host | smart-b6c33050-7936-4c55-bb57-85cf0a45f44d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000553924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.1000553924 |
| Directory | /workspace/1.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.1449754349 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 7086573686 ps |
| CPU time | 30.63 seconds |
| Started | May 26 03:02:58 PM PDT 24 |
| Finished | May 26 03:03:29 PM PDT 24 |
| Peak memory | 210712 kb |
| Host | smart-4219436b-6360-4098-b5ae-07d5bd447a29 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449754349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.1449754349 |
| Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.3620657328 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 742773529 ps |
| CPU time | 80.57 seconds |
| Started | May 26 03:03:00 PM PDT 24 |
| Finished | May 26 03:04:21 PM PDT 24 |
| Peak memory | 312832 kb |
| Host | smart-ae9250f1-0bc6-4558-a6d4-a2339e5e0a0a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620657328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.3620657328 |
| Directory | /workspace/1.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3651147983 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 19502849401 ps |
| CPU time | 185.03 seconds |
| Started | May 26 03:03:07 PM PDT 24 |
| Finished | May 26 03:06:14 PM PDT 24 |
| Peak memory | 215888 kb |
| Host | smart-e6015e3c-a795-41ce-b9b2-1ed459fe9d8d |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651147983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.3651147983 |
| Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.3533612845 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 8233264764 ps |
| CPU time | 126.5 seconds |
| Started | May 26 03:03:05 PM PDT 24 |
| Finished | May 26 03:05:12 PM PDT 24 |
| Peak memory | 210592 kb |
| Host | smart-05fa2a67-22d0-4180-bb09-b1d34d4539c6 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533612845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.3533612845 |
| Directory | /workspace/1.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.2036106238 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2320176119 ps |
| CPU time | 178.98 seconds |
| Started | May 26 03:03:01 PM PDT 24 |
| Finished | May 26 03:06:00 PM PDT 24 |
| Peak memory | 370160 kb |
| Host | smart-de5d0e23-2d45-49e1-a193-5ab6fa7e0378 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036106238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.2036106238 |
| Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.1616397618 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 981018704 ps |
| CPU time | 21.91 seconds |
| Started | May 26 03:02:57 PM PDT 24 |
| Finished | May 26 03:03:20 PM PDT 24 |
| Peak memory | 202404 kb |
| Host | smart-28490447-781f-4c7c-8e6a-086fa06327b5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616397618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.1616397618 |
| Directory | /workspace/1.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.486340657 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 15181114645 ps |
| CPU time | 340.71 seconds |
| Started | May 26 03:02:58 PM PDT 24 |
| Finished | May 26 03:08:40 PM PDT 24 |
| Peak memory | 202528 kb |
| Host | smart-7b4088b8-ad54-4d70-b320-a2d82106cf95 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486340657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.sram_ctrl_partial_access_b2b.486340657 |
| Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.149441828 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 858134159 ps |
| CPU time | 3.58 seconds |
| Started | May 26 03:03:06 PM PDT 24 |
| Finished | May 26 03:03:10 PM PDT 24 |
| Peak memory | 222000 kb |
| Host | smart-34462729-3ab5-4558-bc68-b404eabd27fa |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149441828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_sec_cm.149441828 |
| Directory | /workspace/1.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_smoke.1090564432 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1276681468 ps |
| CPU time | 136.89 seconds |
| Started | May 26 03:02:58 PM PDT 24 |
| Finished | May 26 03:05:16 PM PDT 24 |
| Peak memory | 358944 kb |
| Host | smart-7df53895-c0af-495d-b66e-00db2d15d7dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090564432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1090564432 |
| Directory | /workspace/1.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3917874876 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 15298660427 ps |
| CPU time | 230.83 seconds |
| Started | May 26 03:02:59 PM PDT 24 |
| Finished | May 26 03:06:51 PM PDT 24 |
| Peak memory | 202552 kb |
| Host | smart-440fb3cd-6f06-4298-a2f1-350b58e49a71 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917874876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.3917874876 |
| Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2629248772 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3218401164 ps |
| CPU time | 140.56 seconds |
| Started | May 26 03:03:01 PM PDT 24 |
| Finished | May 26 03:05:22 PM PDT 24 |
| Peak memory | 359880 kb |
| Host | smart-7d16a5c4-214a-4372-b237-25571a93cd41 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629248772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.2629248772 |
| Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.2166105534 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 18432326 ps |
| CPU time | 0.71 seconds |
| Started | May 26 03:06:02 PM PDT 24 |
| Finished | May 26 03:06:03 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-84c1a55a-5c26-4b12-b236-e7e4e6763f25 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166105534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.2166105534 |
| Directory | /workspace/10.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_bijection.4271017270 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 44613421181 ps |
| CPU time | 727.85 seconds |
| Started | May 26 03:05:46 PM PDT 24 |
| Finished | May 26 03:17:55 PM PDT 24 |
| Peak memory | 210816 kb |
| Host | smart-e24b869a-b340-4f4e-b249-7bd8c38c2cd1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271017270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .4271017270 |
| Directory | /workspace/10.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_executable.3848358773 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 7513294802 ps |
| CPU time | 428.64 seconds |
| Started | May 26 03:05:52 PM PDT 24 |
| Finished | May 26 03:13:02 PM PDT 24 |
| Peak memory | 321700 kb |
| Host | smart-ab4b95a7-6547-42d0-b4a3-9e2f29968cca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848358773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.3848358773 |
| Directory | /workspace/10.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.2546526618 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 220068269404 ps |
| CPU time | 149.98 seconds |
| Started | May 26 03:05:54 PM PDT 24 |
| Finished | May 26 03:08:25 PM PDT 24 |
| Peak memory | 202540 kb |
| Host | smart-a18a80a0-aa50-40e4-821e-3f9f7c307a63 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546526618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.2546526618 |
| Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.2846173947 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2776711845 ps |
| CPU time | 6.39 seconds |
| Started | May 26 03:05:53 PM PDT 24 |
| Finished | May 26 03:06:00 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-a4ec3e00-ca55-401b-a018-61c5a730694a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846173947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.2846173947 |
| Directory | /workspace/10.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2057696063 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5555716754 ps |
| CPU time | 78.46 seconds |
| Started | May 26 03:05:53 PM PDT 24 |
| Finished | May 26 03:07:12 PM PDT 24 |
| Peak memory | 213056 kb |
| Host | smart-39fffe77-e068-4079-9442-92dface76b4f |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057696063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.2057696063 |
| Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.2624707846 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 37395657669 ps |
| CPU time | 194.67 seconds |
| Started | May 26 03:05:53 PM PDT 24 |
| Finished | May 26 03:09:08 PM PDT 24 |
| Peak memory | 210572 kb |
| Host | smart-1b16bc25-aef9-4259-bc1a-69a365543bfc |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624707846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.2624707846 |
| Directory | /workspace/10.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.1561516535 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 62807676368 ps |
| CPU time | 1271.92 seconds |
| Started | May 26 03:05:49 PM PDT 24 |
| Finished | May 26 03:27:01 PM PDT 24 |
| Peak memory | 379360 kb |
| Host | smart-03e9884d-285c-49dd-babe-62f783c236dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561516535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.1561516535 |
| Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.3730074708 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2707428016 ps |
| CPU time | 7.38 seconds |
| Started | May 26 03:05:50 PM PDT 24 |
| Finished | May 26 03:05:58 PM PDT 24 |
| Peak memory | 202452 kb |
| Host | smart-be3be9c6-34be-4260-aa8a-ecee90c16fa5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730074708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.3730074708 |
| Directory | /workspace/10.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.876301968 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 44009474266 ps |
| CPU time | 284.31 seconds |
| Started | May 26 03:05:44 PM PDT 24 |
| Finished | May 26 03:10:30 PM PDT 24 |
| Peak memory | 202488 kb |
| Host | smart-7451b96d-6358-4353-9457-18ac939a41f6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876301968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.sram_ctrl_partial_access_b2b.876301968 |
| Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.3755128113 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2406475858 ps |
| CPU time | 3.65 seconds |
| Started | May 26 03:05:52 PM PDT 24 |
| Finished | May 26 03:05:57 PM PDT 24 |
| Peak memory | 202640 kb |
| Host | smart-aa85e293-1b58-4068-8c40-efe073de58fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755128113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3755128113 |
| Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_smoke.2015587571 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 7526280129 ps |
| CPU time | 170.09 seconds |
| Started | May 26 03:05:48 PM PDT 24 |
| Finished | May 26 03:08:38 PM PDT 24 |
| Peak memory | 367964 kb |
| Host | smart-ed458eb2-5f47-4967-a138-5aaeb246bd94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015587571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2015587571 |
| Directory | /workspace/10.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3161391775 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1092047320 ps |
| CPU time | 21.8 seconds |
| Started | May 26 03:06:02 PM PDT 24 |
| Finished | May 26 03:06:25 PM PDT 24 |
| Peak memory | 210808 kb |
| Host | smart-22deb74c-9162-475c-8423-a9eef7cfb888 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3161391775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3161391775 |
| Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.34067671 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 6922732309 ps |
| CPU time | 362.55 seconds |
| Started | May 26 03:05:49 PM PDT 24 |
| Finished | May 26 03:11:52 PM PDT 24 |
| Peak memory | 210620 kb |
| Host | smart-b71fab60-0f42-4743-91fc-c13462ed8db0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_stress_pipeline.34067671 |
| Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.954188458 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 793343736 ps |
| CPU time | 118.64 seconds |
| Started | May 26 03:05:55 PM PDT 24 |
| Finished | May 26 03:07:54 PM PDT 24 |
| Peak memory | 356824 kb |
| Host | smart-a06aee92-534f-4b78-b9b3-c8ccb0d5b78b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954188458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.954188458 |
| Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.672877815 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 62606113 ps |
| CPU time | 0.61 seconds |
| Started | May 26 03:06:16 PM PDT 24 |
| Finished | May 26 03:06:17 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-c483279b-15b2-4b6a-b8e7-80ccc18a8e7c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672877815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.672877815 |
| Directory | /workspace/11.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_bijection.3370305827 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 90645920321 ps |
| CPU time | 2275.92 seconds |
| Started | May 26 03:06:02 PM PDT 24 |
| Finished | May 26 03:43:59 PM PDT 24 |
| Peak memory | 210668 kb |
| Host | smart-8f05f3d1-ffc5-4fee-9861-0ece83c480ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370305827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .3370305827 |
| Directory | /workspace/11.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_executable.4172462933 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 78395184990 ps |
| CPU time | 1781.34 seconds |
| Started | May 26 03:06:09 PM PDT 24 |
| Finished | May 26 03:35:51 PM PDT 24 |
| Peak memory | 374592 kb |
| Host | smart-7592173f-dc0c-4511-b82b-b313e03aefbc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172462933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.4172462933 |
| Directory | /workspace/11.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.1951884214 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 25529837177 ps |
| CPU time | 84.5 seconds |
| Started | May 26 03:06:00 PM PDT 24 |
| Finished | May 26 03:07:25 PM PDT 24 |
| Peak memory | 202476 kb |
| Host | smart-35b6bf10-57ff-428e-a455-62664870a8c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951884214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1951884214 |
| Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.1880484494 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 784807643 ps |
| CPU time | 50.3 seconds |
| Started | May 26 03:06:01 PM PDT 24 |
| Finished | May 26 03:06:51 PM PDT 24 |
| Peak memory | 330152 kb |
| Host | smart-7067443a-acbc-45db-9f5a-bb17b65fb162 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880484494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.1880484494 |
| Directory | /workspace/11.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2339654550 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2454277790 ps |
| CPU time | 149.13 seconds |
| Started | May 26 03:06:09 PM PDT 24 |
| Finished | May 26 03:08:39 PM PDT 24 |
| Peak memory | 214468 kb |
| Host | smart-3372338c-ed39-407b-b7ed-4947afa16df4 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339654550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.2339654550 |
| Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.4184423224 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 21565714844 ps |
| CPU time | 350.63 seconds |
| Started | May 26 03:06:10 PM PDT 24 |
| Finished | May 26 03:12:02 PM PDT 24 |
| Peak memory | 210612 kb |
| Host | smart-8883af3b-9abe-412d-a111-c0431b2c7cfd |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184423224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.4184423224 |
| Directory | /workspace/11.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.3662343450 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 36508673839 ps |
| CPU time | 753.72 seconds |
| Started | May 26 03:06:02 PM PDT 24 |
| Finished | May 26 03:18:36 PM PDT 24 |
| Peak memory | 379368 kb |
| Host | smart-dc402505-6b50-48df-b259-9258929ec047 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662343450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.3662343450 |
| Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.3789865518 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 392646712 ps |
| CPU time | 4.06 seconds |
| Started | May 26 03:06:01 PM PDT 24 |
| Finished | May 26 03:06:05 PM PDT 24 |
| Peak memory | 202464 kb |
| Host | smart-53cc7579-f998-4852-8ff9-fddb08828086 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789865518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.3789865518 |
| Directory | /workspace/11.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4103607139 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 110817249315 ps |
| CPU time | 670.07 seconds |
| Started | May 26 03:06:01 PM PDT 24 |
| Finished | May 26 03:17:12 PM PDT 24 |
| Peak memory | 202488 kb |
| Host | smart-3f4aeee3-4e13-45bc-a2d3-1de7407ccc94 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103607139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.4103607139 |
| Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.2317203891 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 695599000 ps |
| CPU time | 3.42 seconds |
| Started | May 26 03:06:08 PM PDT 24 |
| Finished | May 26 03:06:13 PM PDT 24 |
| Peak memory | 202516 kb |
| Host | smart-18a6433f-9533-4810-97da-3d2e7f0a654d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317203891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2317203891 |
| Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_smoke.1144612942 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 797194960 ps |
| CPU time | 11.9 seconds |
| Started | May 26 03:06:02 PM PDT 24 |
| Finished | May 26 03:06:15 PM PDT 24 |
| Peak memory | 202432 kb |
| Host | smart-16300b80-a5fb-4c18-bd61-40d0c60602c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144612942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1144612942 |
| Directory | /workspace/11.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1788343543 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2266383769 ps |
| CPU time | 88.03 seconds |
| Started | May 26 03:06:07 PM PDT 24 |
| Finished | May 26 03:07:36 PM PDT 24 |
| Peak memory | 212956 kb |
| Host | smart-c1fb8ba8-ce7b-479a-a3b1-2c37bd54ec70 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1788343543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1788343543 |
| Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3619943108 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 4455469224 ps |
| CPU time | 300.45 seconds |
| Started | May 26 03:06:01 PM PDT 24 |
| Finished | May 26 03:11:02 PM PDT 24 |
| Peak memory | 202476 kb |
| Host | smart-5fc967f6-2124-41fa-95cd-ee60520c5324 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619943108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.3619943108 |
| Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3378544129 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2652113393 ps |
| CPU time | 32.93 seconds |
| Started | May 26 03:06:02 PM PDT 24 |
| Finished | May 26 03:06:36 PM PDT 24 |
| Peak memory | 274020 kb |
| Host | smart-01cb32a4-b4de-44f6-adaf-e59815ad01c0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378544129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3378544129 |
| Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.2689568995 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 16582208 ps |
| CPU time | 0.68 seconds |
| Started | May 26 03:06:34 PM PDT 24 |
| Finished | May 26 03:06:35 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-6a284274-1dd0-4bc5-beb0-6b9688732eb8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689568995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.2689568995 |
| Directory | /workspace/12.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_executable.1225837501 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 36273374236 ps |
| CPU time | 287.42 seconds |
| Started | May 26 03:06:26 PM PDT 24 |
| Finished | May 26 03:11:14 PM PDT 24 |
| Peak memory | 334548 kb |
| Host | smart-f6600794-398a-40d8-ac2d-da0d370ea5b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225837501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.1225837501 |
| Directory | /workspace/12.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.1711573771 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 21000415112 ps |
| CPU time | 54.03 seconds |
| Started | May 26 03:06:26 PM PDT 24 |
| Finished | May 26 03:07:21 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-c0e08f72-e5d6-4ee2-82ee-11fd8a1a744d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711573771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.1711573771 |
| Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.699584434 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3050701779 ps |
| CPU time | 19.61 seconds |
| Started | May 26 03:06:27 PM PDT 24 |
| Finished | May 26 03:06:48 PM PDT 24 |
| Peak memory | 257476 kb |
| Host | smart-f4ef46ad-b7e2-440d-a946-deaf2e4f077c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699584434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.sram_ctrl_max_throughput.699584434 |
| Directory | /workspace/12.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2296901951 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4878745289 ps |
| CPU time | 75.39 seconds |
| Started | May 26 03:06:35 PM PDT 24 |
| Finished | May 26 03:07:52 PM PDT 24 |
| Peak memory | 213372 kb |
| Host | smart-29f9962f-7e11-4b4c-a5e5-f7cdfff6e2d7 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296901951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.2296901951 |
| Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.3205050568 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 26563187166 ps |
| CPU time | 177.54 seconds |
| Started | May 26 03:06:37 PM PDT 24 |
| Finished | May 26 03:09:35 PM PDT 24 |
| Peak memory | 210688 kb |
| Host | smart-2e7d2f6c-ae5d-4522-9099-6d37fe35801d |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205050568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.3205050568 |
| Directory | /workspace/12.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.1551725076 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 56375545525 ps |
| CPU time | 916.74 seconds |
| Started | May 26 03:06:18 PM PDT 24 |
| Finished | May 26 03:21:35 PM PDT 24 |
| Peak memory | 382464 kb |
| Host | smart-0490a38e-5411-4cc6-b932-1e6e98d8c732 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551725076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.1551725076 |
| Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.2598724689 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 5440033972 ps |
| CPU time | 131.79 seconds |
| Started | May 26 03:06:27 PM PDT 24 |
| Finished | May 26 03:08:40 PM PDT 24 |
| Peak memory | 356008 kb |
| Host | smart-34a9b61c-9375-4d88-9e3d-e85116b5fc77 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598724689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.2598724689 |
| Directory | /workspace/12.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2705614693 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 9091989110 ps |
| CPU time | 404.52 seconds |
| Started | May 26 03:06:27 PM PDT 24 |
| Finished | May 26 03:13:13 PM PDT 24 |
| Peak memory | 210700 kb |
| Host | smart-e4ba87f0-8aac-4cb6-be63-2be316e72833 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705614693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.2705614693 |
| Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.4042081144 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1439540212 ps |
| CPU time | 3.61 seconds |
| Started | May 26 03:06:27 PM PDT 24 |
| Finished | May 26 03:06:31 PM PDT 24 |
| Peak memory | 202536 kb |
| Host | smart-93465c1e-cf4a-4b5f-b3c5-a9f2765d5942 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042081144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.4042081144 |
| Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_regwen.3406069407 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 57864055770 ps |
| CPU time | 916.1 seconds |
| Started | May 26 03:06:28 PM PDT 24 |
| Finished | May 26 03:21:45 PM PDT 24 |
| Peak memory | 376356 kb |
| Host | smart-960b9d07-b33c-44cf-986a-75b0199cbf01 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406069407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3406069407 |
| Directory | /workspace/12.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_smoke.2650340088 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 431741465 ps |
| CPU time | 9.36 seconds |
| Started | May 26 03:06:21 PM PDT 24 |
| Finished | May 26 03:06:31 PM PDT 24 |
| Peak memory | 210624 kb |
| Host | smart-e3268351-95ba-4003-8cac-659cf19f3fa8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650340088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2650340088 |
| Directory | /workspace/12.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.4150795092 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 5394768250 ps |
| CPU time | 398.93 seconds |
| Started | May 26 03:06:21 PM PDT 24 |
| Finished | May 26 03:13:01 PM PDT 24 |
| Peak memory | 202488 kb |
| Host | smart-80f0949e-3896-449e-ac82-97ffc76a9f38 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150795092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.4150795092 |
| Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.764030258 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1507891818 ps |
| CPU time | 64.04 seconds |
| Started | May 26 03:06:27 PM PDT 24 |
| Finished | May 26 03:07:32 PM PDT 24 |
| Peak memory | 300576 kb |
| Host | smart-9832dd33-0069-40d4-acaf-239344e1af0e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764030258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_throughput_w_partial_write.764030258 |
| Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.1549263399 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 41349733 ps |
| CPU time | 0.65 seconds |
| Started | May 26 03:06:47 PM PDT 24 |
| Finished | May 26 03:06:48 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-dada7695-2724-43ca-a7fc-7dbb9680a818 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549263399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1549263399 |
| Directory | /workspace/13.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_bijection.4037193893 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 294332928176 ps |
| CPU time | 2784.61 seconds |
| Started | May 26 03:06:38 PM PDT 24 |
| Finished | May 26 03:53:03 PM PDT 24 |
| Peak memory | 210636 kb |
| Host | smart-cb207b1b-fe62-4f07-82d0-72ffc6adb484 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037193893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .4037193893 |
| Directory | /workspace/13.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_executable.3327523227 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 6201451005 ps |
| CPU time | 169.54 seconds |
| Started | May 26 03:06:51 PM PDT 24 |
| Finished | May 26 03:09:41 PM PDT 24 |
| Peak memory | 321056 kb |
| Host | smart-8e850653-3dad-4c93-9807-996ab7714267 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327523227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.3327523227 |
| Directory | /workspace/13.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.977763936 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 7924381024 ps |
| CPU time | 54.82 seconds |
| Started | May 26 03:06:40 PM PDT 24 |
| Finished | May 26 03:07:36 PM PDT 24 |
| Peak memory | 210732 kb |
| Host | smart-d47bf7c0-cc16-4575-b9cb-a47c8eaae9f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977763936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_esc alation.977763936 |
| Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.2574825631 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2808540592 ps |
| CPU time | 6.01 seconds |
| Started | May 26 03:06:41 PM PDT 24 |
| Finished | May 26 03:06:47 PM PDT 24 |
| Peak memory | 210480 kb |
| Host | smart-3f4a3419-55a6-46e6-a678-cce2d9213535 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574825631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.2574825631 |
| Directory | /workspace/13.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1170673059 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 19716881706 ps |
| CPU time | 144.43 seconds |
| Started | May 26 03:06:51 PM PDT 24 |
| Finished | May 26 03:09:16 PM PDT 24 |
| Peak memory | 218620 kb |
| Host | smart-520b32b8-3cb5-4442-8585-9cc2c3c10252 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170673059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.1170673059 |
| Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.805791009 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 10954784844 ps |
| CPU time | 167.43 seconds |
| Started | May 26 03:06:50 PM PDT 24 |
| Finished | May 26 03:09:38 PM PDT 24 |
| Peak memory | 210588 kb |
| Host | smart-eba8de66-6eeb-4f22-b859-e61210b60411 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805791009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _mem_walk.805791009 |
| Directory | /workspace/13.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.558596735 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 80872819574 ps |
| CPU time | 1374.86 seconds |
| Started | May 26 03:06:34 PM PDT 24 |
| Finished | May 26 03:29:29 PM PDT 24 |
| Peak memory | 371604 kb |
| Host | smart-667b6cef-a388-4063-9681-4f768ad8b99e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558596735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip le_keys.558596735 |
| Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.3493549605 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 10371529026 ps |
| CPU time | 14.46 seconds |
| Started | May 26 03:06:37 PM PDT 24 |
| Finished | May 26 03:06:52 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-f2fd768f-6142-40d3-9b6f-717157371b22 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493549605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.3493549605 |
| Directory | /workspace/13.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2890324099 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 38273116211 ps |
| CPU time | 438.22 seconds |
| Started | May 26 03:06:36 PM PDT 24 |
| Finished | May 26 03:13:55 PM PDT 24 |
| Peak memory | 210660 kb |
| Host | smart-7c9bd182-c263-40e1-b9d9-966ce28079ee |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890324099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.2890324099 |
| Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.872259322 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1131599757 ps |
| CPU time | 3.28 seconds |
| Started | May 26 03:06:49 PM PDT 24 |
| Finished | May 26 03:06:53 PM PDT 24 |
| Peak memory | 202552 kb |
| Host | smart-2df35fcc-5a79-4330-a107-21b3cc1742c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872259322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.872259322 |
| Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_regwen.526681764 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 7210025931 ps |
| CPU time | 639.82 seconds |
| Started | May 26 03:06:50 PM PDT 24 |
| Finished | May 26 03:17:31 PM PDT 24 |
| Peak memory | 370284 kb |
| Host | smart-8897c363-7a51-4abe-b45b-849298a47386 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526681764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.526681764 |
| Directory | /workspace/13.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_smoke.105544256 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 4338412975 ps |
| CPU time | 131.16 seconds |
| Started | May 26 03:06:33 PM PDT 24 |
| Finished | May 26 03:08:45 PM PDT 24 |
| Peak memory | 369144 kb |
| Host | smart-c656f2cc-7c52-4260-8e01-2ba58314b5a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105544256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.105544256 |
| Directory | /workspace/13.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.4007629434 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 897216307 ps |
| CPU time | 15.56 seconds |
| Started | May 26 03:06:48 PM PDT 24 |
| Finished | May 26 03:07:04 PM PDT 24 |
| Peak memory | 210684 kb |
| Host | smart-e23cb635-38cb-45a8-8720-806d6d962641 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4007629434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.4007629434 |
| Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.23181138 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12747988904 ps |
| CPU time | 359.79 seconds |
| Started | May 26 03:06:36 PM PDT 24 |
| Finished | May 26 03:12:37 PM PDT 24 |
| Peak memory | 202500 kb |
| Host | smart-60c0a722-c08a-43c4-8a5b-e87e88c997cf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23181138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_stress_pipeline.23181138 |
| Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2438552250 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2799586739 ps |
| CPU time | 162.74 seconds |
| Started | May 26 03:06:41 PM PDT 24 |
| Finished | May 26 03:09:24 PM PDT 24 |
| Peak memory | 369272 kb |
| Host | smart-f965ec4d-f86c-476a-bd5d-f47a4946dddc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438552250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.2438552250 |
| Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.3975115249 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 86778898 ps |
| CPU time | 0.67 seconds |
| Started | May 26 03:07:11 PM PDT 24 |
| Finished | May 26 03:07:12 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-0e1f6f85-6197-4cad-99c1-93c0c6f49b41 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975115249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3975115249 |
| Directory | /workspace/14.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_bijection.2936422644 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 26100323107 ps |
| CPU time | 1715.88 seconds |
| Started | May 26 03:06:54 PM PDT 24 |
| Finished | May 26 03:35:31 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-344bc2b4-c499-42ec-a92b-77541e48d71f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936422644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .2936422644 |
| Directory | /workspace/14.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_executable.3998314022 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 90364445930 ps |
| CPU time | 1303.01 seconds |
| Started | May 26 03:07:02 PM PDT 24 |
| Finished | May 26 03:28:46 PM PDT 24 |
| Peak memory | 378396 kb |
| Host | smart-ce05c6cc-30a6-493d-9921-71fd0f68f427 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998314022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.3998314022 |
| Directory | /workspace/14.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.1248763805 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 13645443591 ps |
| CPU time | 89.71 seconds |
| Started | May 26 03:07:03 PM PDT 24 |
| Finished | May 26 03:08:34 PM PDT 24 |
| Peak memory | 214776 kb |
| Host | smart-b63dc0ad-b45b-438e-b61e-68d6522dd891 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248763805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.1248763805 |
| Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.1456731192 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2797887226 ps |
| CPU time | 6.83 seconds |
| Started | May 26 03:06:57 PM PDT 24 |
| Finished | May 26 03:07:05 PM PDT 24 |
| Peak memory | 210628 kb |
| Host | smart-7d64450c-1762-481c-8d7b-591e539da159 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456731192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.1456731192 |
| Directory | /workspace/14.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.4265098526 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1413863363 ps |
| CPU time | 75.79 seconds |
| Started | May 26 03:07:10 PM PDT 24 |
| Finished | May 26 03:08:27 PM PDT 24 |
| Peak memory | 212336 kb |
| Host | smart-f2ec4fa8-3529-4782-ba25-f99808169d4f |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265098526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.4265098526 |
| Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.2815304541 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 86379893659 ps |
| CPU time | 312.39 seconds |
| Started | May 26 03:07:12 PM PDT 24 |
| Finished | May 26 03:12:25 PM PDT 24 |
| Peak memory | 210880 kb |
| Host | smart-9b353b81-8fc0-4942-a7db-fb57b8c3865b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815304541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.2815304541 |
| Directory | /workspace/14.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.4003894966 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 10595714176 ps |
| CPU time | 514.12 seconds |
| Started | May 26 03:06:55 PM PDT 24 |
| Finished | May 26 03:15:30 PM PDT 24 |
| Peak memory | 379664 kb |
| Host | smart-7c54d466-8788-4d48-babc-2daa755e1c81 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003894966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.4003894966 |
| Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.1537504603 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 2365301912 ps |
| CPU time | 16.42 seconds |
| Started | May 26 03:06:57 PM PDT 24 |
| Finished | May 26 03:07:14 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-fe10ef4a-79b0-4455-b4cb-6ba436fde113 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537504603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.1537504603 |
| Directory | /workspace/14.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2375866343 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 46153395750 ps |
| CPU time | 577.23 seconds |
| Started | May 26 03:06:55 PM PDT 24 |
| Finished | May 26 03:16:33 PM PDT 24 |
| Peak memory | 202492 kb |
| Host | smart-398ace40-63c5-4318-8905-f66cbe0e2c83 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375866343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.2375866343 |
| Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.109517185 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 681432430 ps |
| CPU time | 3.33 seconds |
| Started | May 26 03:07:01 PM PDT 24 |
| Finished | May 26 03:07:05 PM PDT 24 |
| Peak memory | 202528 kb |
| Host | smart-6f257985-5917-4e6a-9648-26ae0f7f0b65 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109517185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.109517185 |
| Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_regwen.2622241141 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 22128879082 ps |
| CPU time | 1530.92 seconds |
| Started | May 26 03:07:03 PM PDT 24 |
| Finished | May 26 03:32:35 PM PDT 24 |
| Peak memory | 381444 kb |
| Host | smart-cba55da4-26ab-4ebc-96b3-9721ba298b46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622241141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2622241141 |
| Directory | /workspace/14.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_smoke.3713137228 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1355644127 ps |
| CPU time | 11.05 seconds |
| Started | May 26 03:06:57 PM PDT 24 |
| Finished | May 26 03:07:08 PM PDT 24 |
| Peak memory | 219280 kb |
| Host | smart-94942746-645a-4d44-b775-35567bac26c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713137228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3713137228 |
| Directory | /workspace/14.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3530133459 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 9849411722 ps |
| CPU time | 26.32 seconds |
| Started | May 26 03:07:11 PM PDT 24 |
| Finished | May 26 03:07:38 PM PDT 24 |
| Peak memory | 210796 kb |
| Host | smart-a01fc969-a97a-4059-bfe8-4b46a9bb7a5c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3530133459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3530133459 |
| Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2602138574 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 32277245146 ps |
| CPU time | 256.51 seconds |
| Started | May 26 03:06:56 PM PDT 24 |
| Finished | May 26 03:11:13 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-410cfa38-e06d-4fb2-9166-9064f1fb16c0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602138574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.2602138574 |
| Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1465073098 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1571240261 ps |
| CPU time | 121.81 seconds |
| Started | May 26 03:06:56 PM PDT 24 |
| Finished | May 26 03:08:58 PM PDT 24 |
| Peak memory | 367988 kb |
| Host | smart-829919eb-3a4a-496d-85dd-7a5486ab3a8c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465073098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1465073098 |
| Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.2366067434 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12425095 ps |
| CPU time | 0.65 seconds |
| Started | May 26 03:07:29 PM PDT 24 |
| Finished | May 26 03:07:30 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-13a6d398-5493-4655-bb59-ce80804ebe31 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366067434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.2366067434 |
| Directory | /workspace/15.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_bijection.2210594642 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 501711738960 ps |
| CPU time | 2925.59 seconds |
| Started | May 26 03:07:13 PM PDT 24 |
| Finished | May 26 03:55:59 PM PDT 24 |
| Peak memory | 210692 kb |
| Host | smart-786c7aeb-5117-4703-8e99-a25ab9123f12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210594642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .2210594642 |
| Directory | /workspace/15.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_executable.1709451742 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 42112792919 ps |
| CPU time | 452.95 seconds |
| Started | May 26 03:07:20 PM PDT 24 |
| Finished | May 26 03:14:54 PM PDT 24 |
| Peak memory | 355056 kb |
| Host | smart-6e37580a-e1b3-46cd-b618-d29ca1f22bca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709451742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.1709451742 |
| Directory | /workspace/15.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.2493131846 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 54067746130 ps |
| CPU time | 113.28 seconds |
| Started | May 26 03:07:18 PM PDT 24 |
| Finished | May 26 03:09:12 PM PDT 24 |
| Peak memory | 210716 kb |
| Host | smart-021ecc67-c05c-4842-8be8-e9bd98fe8605 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493131846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.2493131846 |
| Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.1270429853 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 12712893288 ps |
| CPU time | 126.49 seconds |
| Started | May 26 03:07:20 PM PDT 24 |
| Finished | May 26 03:09:28 PM PDT 24 |
| Peak memory | 370288 kb |
| Host | smart-fd6a3840-ab8e-4055-ae10-173f85a139c0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270429853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.1270429853 |
| Directory | /workspace/15.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2972656354 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 14780349459 ps |
| CPU time | 89.47 seconds |
| Started | May 26 03:07:27 PM PDT 24 |
| Finished | May 26 03:08:57 PM PDT 24 |
| Peak memory | 212756 kb |
| Host | smart-543c8eec-0bfb-411d-ad1b-d114737dd374 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972656354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.2972656354 |
| Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.997353540 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 28800807046 ps |
| CPU time | 161.19 seconds |
| Started | May 26 03:07:28 PM PDT 24 |
| Finished | May 26 03:10:10 PM PDT 24 |
| Peak memory | 210720 kb |
| Host | smart-53891577-cc50-4677-80b4-421057811c59 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997353540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _mem_walk.997353540 |
| Directory | /workspace/15.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.2797934553 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 8837498049 ps |
| CPU time | 1159.92 seconds |
| Started | May 26 03:07:12 PM PDT 24 |
| Finished | May 26 03:26:32 PM PDT 24 |
| Peak memory | 375336 kb |
| Host | smart-fc419c96-c2f0-4d2f-b8aa-cc7104d61d5f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797934553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.2797934553 |
| Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.3685735710 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1636955797 ps |
| CPU time | 4.54 seconds |
| Started | May 26 03:07:20 PM PDT 24 |
| Finished | May 26 03:07:26 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-1af7742a-c55b-438e-9ef1-68c84317f0a9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685735710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.3685735710 |
| Directory | /workspace/15.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1187552307 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 95447728542 ps |
| CPU time | 597.81 seconds |
| Started | May 26 03:07:20 PM PDT 24 |
| Finished | May 26 03:17:19 PM PDT 24 |
| Peak memory | 202468 kb |
| Host | smart-300d57b7-5352-4723-b6c2-c1f718b1e1be |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187552307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.1187552307 |
| Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.3427214932 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 365949667 ps |
| CPU time | 3.34 seconds |
| Started | May 26 03:07:19 PM PDT 24 |
| Finished | May 26 03:07:23 PM PDT 24 |
| Peak memory | 202576 kb |
| Host | smart-99294842-8479-4263-81e2-542f837783b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427214932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3427214932 |
| Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_regwen.967640592 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 13127250279 ps |
| CPU time | 1237.92 seconds |
| Started | May 26 03:07:18 PM PDT 24 |
| Finished | May 26 03:27:57 PM PDT 24 |
| Peak memory | 379408 kb |
| Host | smart-6edb512a-7f2b-4be6-bde5-3adc019fcc85 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967640592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.967640592 |
| Directory | /workspace/15.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_smoke.4041660906 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1888352483 ps |
| CPU time | 5.85 seconds |
| Started | May 26 03:07:12 PM PDT 24 |
| Finished | May 26 03:07:19 PM PDT 24 |
| Peak memory | 208932 kb |
| Host | smart-02ffb33a-94d3-40ef-9e32-3f85338900bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041660906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.4041660906 |
| Directory | /workspace/15.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.1151182988 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 163985287087 ps |
| CPU time | 5369.2 seconds |
| Started | May 26 03:07:26 PM PDT 24 |
| Finished | May 26 04:36:56 PM PDT 24 |
| Peak memory | 381488 kb |
| Host | smart-3699c5bf-a46d-4fa0-81d6-376204c10429 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151182988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.1151182988 |
| Directory | /workspace/15.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1830739216 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 642413143 ps |
| CPU time | 12.95 seconds |
| Started | May 26 03:07:26 PM PDT 24 |
| Finished | May 26 03:07:40 PM PDT 24 |
| Peak memory | 210716 kb |
| Host | smart-f4ab9a2d-93a8-4cce-af7d-f38fdf0d4f24 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1830739216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.1830739216 |
| Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3043616556 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 17483477023 ps |
| CPU time | 235.8 seconds |
| Started | May 26 03:07:11 PM PDT 24 |
| Finished | May 26 03:11:08 PM PDT 24 |
| Peak memory | 202444 kb |
| Host | smart-d43100fa-8a52-44b2-9cf3-583d58358a1a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043616556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.3043616556 |
| Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1145364603 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1401871589 ps |
| CPU time | 49.25 seconds |
| Started | May 26 03:07:19 PM PDT 24 |
| Finished | May 26 03:08:09 PM PDT 24 |
| Peak memory | 288328 kb |
| Host | smart-ea6de11d-8caa-46e7-a687-662c9a04d3de |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145364603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.1145364603 |
| Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.168714403 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 41780573 ps |
| CPU time | 0.64 seconds |
| Started | May 26 03:07:39 PM PDT 24 |
| Finished | May 26 03:07:40 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-06d373db-dce2-4d3a-a9b8-115a41ed8c4e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168714403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.168714403 |
| Directory | /workspace/16.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_bijection.3162695458 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 460979055085 ps |
| CPU time | 2228.72 seconds |
| Started | May 26 03:07:26 PM PDT 24 |
| Finished | May 26 03:44:35 PM PDT 24 |
| Peak memory | 210676 kb |
| Host | smart-6506f737-ecd5-4d3f-ba7f-78b6c71aaaad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162695458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .3162695458 |
| Directory | /workspace/16.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_executable.2758973358 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 96292042297 ps |
| CPU time | 1583.32 seconds |
| Started | May 26 03:07:33 PM PDT 24 |
| Finished | May 26 03:33:57 PM PDT 24 |
| Peak memory | 381464 kb |
| Host | smart-870904d2-46b4-44f5-80d4-68890f2e44ef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758973358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.2758973358 |
| Directory | /workspace/16.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.1516380256 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 3194602166 ps |
| CPU time | 149.69 seconds |
| Started | May 26 03:07:26 PM PDT 24 |
| Finished | May 26 03:09:57 PM PDT 24 |
| Peak memory | 370152 kb |
| Host | smart-b596823a-5a09-4b03-afa6-bb21176b17ea |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516380256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.1516380256 |
| Directory | /workspace/16.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.605709218 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 5578943061 ps |
| CPU time | 95.78 seconds |
| Started | May 26 03:07:40 PM PDT 24 |
| Finished | May 26 03:09:16 PM PDT 24 |
| Peak memory | 213032 kb |
| Host | smart-3f890097-5b2e-446e-89fc-7e74e857dc85 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605709218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_mem_partial_access.605709218 |
| Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.3322211870 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 7290048593 ps |
| CPU time | 151.19 seconds |
| Started | May 26 03:07:39 PM PDT 24 |
| Finished | May 26 03:10:11 PM PDT 24 |
| Peak memory | 211092 kb |
| Host | smart-93b7df60-7201-4b8c-b8f2-620c3d949aab |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322211870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.3322211870 |
| Directory | /workspace/16.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.3316919543 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 53649138236 ps |
| CPU time | 849.75 seconds |
| Started | May 26 03:07:26 PM PDT 24 |
| Finished | May 26 03:21:36 PM PDT 24 |
| Peak memory | 361128 kb |
| Host | smart-41521d65-bc15-46fe-9b83-916cbf228cb4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316919543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.3316919543 |
| Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.1033186063 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1636869021 ps |
| CPU time | 4.62 seconds |
| Started | May 26 03:07:27 PM PDT 24 |
| Finished | May 26 03:07:33 PM PDT 24 |
| Peak memory | 210636 kb |
| Host | smart-f66fddee-1e1b-42b1-8e8c-3553992490a7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033186063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.1033186063 |
| Directory | /workspace/16.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.4220545365 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 18536985330 ps |
| CPU time | 476.19 seconds |
| Started | May 26 03:07:26 PM PDT 24 |
| Finished | May 26 03:15:23 PM PDT 24 |
| Peak memory | 210632 kb |
| Host | smart-c3bd84b7-b2f2-4a13-9b13-7bba000edec6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220545365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.4220545365 |
| Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.669250335 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2402539683 ps |
| CPU time | 3.54 seconds |
| Started | May 26 03:07:41 PM PDT 24 |
| Finished | May 26 03:07:45 PM PDT 24 |
| Peak memory | 202628 kb |
| Host | smart-40ba62e7-38ba-4d01-8a47-24a15c9d554f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669250335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.669250335 |
| Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_regwen.2920392359 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 10113878454 ps |
| CPU time | 987 seconds |
| Started | May 26 03:07:39 PM PDT 24 |
| Finished | May 26 03:24:06 PM PDT 24 |
| Peak memory | 379080 kb |
| Host | smart-6a12f389-fdd5-4f13-97b1-f58e6d06b51e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920392359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2920392359 |
| Directory | /workspace/16.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_smoke.1787068091 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1077262019 ps |
| CPU time | 8.26 seconds |
| Started | May 26 03:07:27 PM PDT 24 |
| Finished | May 26 03:07:36 PM PDT 24 |
| Peak memory | 227928 kb |
| Host | smart-0bb7400d-dd69-4547-abcf-96fc7a7b747e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787068091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1787068091 |
| Directory | /workspace/16.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3196915852 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1014462180 ps |
| CPU time | 7.99 seconds |
| Started | May 26 03:07:40 PM PDT 24 |
| Finished | May 26 03:07:49 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-8ceaea8b-9382-4829-a016-3d7e90ab84b6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3196915852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3196915852 |
| Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.439469890 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 9185518282 ps |
| CPU time | 193.24 seconds |
| Started | May 26 03:07:27 PM PDT 24 |
| Finished | May 26 03:10:41 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-d324ff78-e67f-4e5e-964c-001e9059343f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439469890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_stress_pipeline.439469890 |
| Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1800813520 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2562228313 ps |
| CPU time | 61.45 seconds |
| Started | May 26 03:07:33 PM PDT 24 |
| Finished | May 26 03:08:35 PM PDT 24 |
| Peak memory | 314900 kb |
| Host | smart-ce9776e8-b4bf-40d2-ad49-bc03fb6f8f02 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800813520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.1800813520 |
| Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.2325622326 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 20996374 ps |
| CPU time | 0.63 seconds |
| Started | May 26 03:07:59 PM PDT 24 |
| Finished | May 26 03:08:01 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-6a01d49c-044f-418d-b2f8-6e75c877f793 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325622326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.2325622326 |
| Directory | /workspace/17.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_bijection.3604209170 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 165637277689 ps |
| CPU time | 2062.9 seconds |
| Started | May 26 03:07:47 PM PDT 24 |
| Finished | May 26 03:42:11 PM PDT 24 |
| Peak memory | 210684 kb |
| Host | smart-47eaa933-f137-4684-a46f-ee09250cc3ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604209170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .3604209170 |
| Directory | /workspace/17.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_executable.2262781916 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 28301996535 ps |
| CPU time | 738.33 seconds |
| Started | May 26 03:08:02 PM PDT 24 |
| Finished | May 26 03:20:21 PM PDT 24 |
| Peak memory | 370252 kb |
| Host | smart-ef600750-4f98-498f-971b-f742967af8fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262781916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.2262781916 |
| Directory | /workspace/17.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.303818726 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 16819010899 ps |
| CPU time | 96.88 seconds |
| Started | May 26 03:07:52 PM PDT 24 |
| Finished | May 26 03:09:30 PM PDT 24 |
| Peak memory | 210716 kb |
| Host | smart-901674be-4ec5-4d84-99eb-123817516a78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303818726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esc alation.303818726 |
| Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.2984160669 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1096297400 ps |
| CPU time | 166.81 seconds |
| Started | May 26 03:07:54 PM PDT 24 |
| Finished | May 26 03:10:41 PM PDT 24 |
| Peak memory | 370068 kb |
| Host | smart-bd8c4039-321d-4537-9e8f-bff6f3c6bae2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984160669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.2984160669 |
| Directory | /workspace/17.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2383516240 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1673083860 ps |
| CPU time | 84.45 seconds |
| Started | May 26 03:08:00 PM PDT 24 |
| Finished | May 26 03:09:25 PM PDT 24 |
| Peak memory | 212240 kb |
| Host | smart-d902526d-4c39-45f1-bb17-a42ff29202f3 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383516240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.2383516240 |
| Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.1887565174 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 47003404673 ps |
| CPU time | 175.63 seconds |
| Started | May 26 03:08:01 PM PDT 24 |
| Finished | May 26 03:10:57 PM PDT 24 |
| Peak memory | 210644 kb |
| Host | smart-347f21eb-cf2e-4190-84db-28b71e49a84f |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887565174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.1887565174 |
| Directory | /workspace/17.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.1971482838 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 36661044618 ps |
| CPU time | 434.39 seconds |
| Started | May 26 03:07:45 PM PDT 24 |
| Finished | May 26 03:15:00 PM PDT 24 |
| Peak memory | 376344 kb |
| Host | smart-5b5b25c9-13b7-42b3-b6ce-f9b4e6652590 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971482838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.1971482838 |
| Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.3313034264 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2307042957 ps |
| CPU time | 148.29 seconds |
| Started | May 26 03:07:54 PM PDT 24 |
| Finished | May 26 03:10:23 PM PDT 24 |
| Peak memory | 351720 kb |
| Host | smart-90390555-70cb-4a7f-8915-b697f0615fb0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313034264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.3313034264 |
| Directory | /workspace/17.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3714315602 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 6255629516 ps |
| CPU time | 331.15 seconds |
| Started | May 26 03:07:54 PM PDT 24 |
| Finished | May 26 03:13:26 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-676967c8-70c7-42f6-8f80-2da9c8654990 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714315602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.3714315602 |
| Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.1550511544 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1784029116 ps |
| CPU time | 3.21 seconds |
| Started | May 26 03:07:59 PM PDT 24 |
| Finished | May 26 03:08:03 PM PDT 24 |
| Peak memory | 202540 kb |
| Host | smart-0488fafe-a420-4002-924b-a28fb55f2332 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550511544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1550511544 |
| Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_regwen.2441069516 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 156516697834 ps |
| CPU time | 897.58 seconds |
| Started | May 26 03:08:00 PM PDT 24 |
| Finished | May 26 03:22:58 PM PDT 24 |
| Peak memory | 376308 kb |
| Host | smart-a2f18e1e-0670-4f26-906a-585a942d44d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441069516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2441069516 |
| Directory | /workspace/17.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_smoke.2412753429 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3614899809 ps |
| CPU time | 11.18 seconds |
| Started | May 26 03:07:47 PM PDT 24 |
| Finished | May 26 03:07:58 PM PDT 24 |
| Peak memory | 202460 kb |
| Host | smart-f9f1152f-356f-40d9-8b92-5dd725d9747b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412753429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2412753429 |
| Directory | /workspace/17.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1159497860 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1931377753 ps |
| CPU time | 44.94 seconds |
| Started | May 26 03:07:58 PM PDT 24 |
| Finished | May 26 03:08:44 PM PDT 24 |
| Peak memory | 225924 kb |
| Host | smart-cb21d6e4-9066-406f-86b3-e800dc4a6fde |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1159497860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1159497860 |
| Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.804311847 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 21662106946 ps |
| CPU time | 259.56 seconds |
| Started | May 26 03:07:47 PM PDT 24 |
| Finished | May 26 03:12:07 PM PDT 24 |
| Peak memory | 210684 kb |
| Host | smart-ee129778-fc62-4213-9ab3-8fbcbb2f4177 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804311847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17 .sram_ctrl_stress_pipeline.804311847 |
| Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1986067113 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 792652538 ps |
| CPU time | 140.29 seconds |
| Started | May 26 03:07:53 PM PDT 24 |
| Finished | May 26 03:10:15 PM PDT 24 |
| Peak memory | 361936 kb |
| Host | smart-29cfa57c-badf-4ad1-9f45-4babd9a11ac1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986067113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1986067113 |
| Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.2797127771 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 41439109 ps |
| CPU time | 0.64 seconds |
| Started | May 26 03:08:20 PM PDT 24 |
| Finished | May 26 03:08:21 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-b599b513-9117-4985-b47c-bc89bed3db12 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797127771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2797127771 |
| Directory | /workspace/18.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_bijection.2720207851 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 14023717182 ps |
| CPU time | 858.13 seconds |
| Started | May 26 03:08:10 PM PDT 24 |
| Finished | May 26 03:22:29 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-1c05f572-2ed9-4965-9eb1-c5823f3e60b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720207851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .2720207851 |
| Directory | /workspace/18.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_executable.2809938553 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 3279257109 ps |
| CPU time | 68.62 seconds |
| Started | May 26 03:08:14 PM PDT 24 |
| Finished | May 26 03:09:23 PM PDT 24 |
| Peak memory | 202488 kb |
| Host | smart-88a6e209-f5e5-4e34-ad2a-6fd16894012a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809938553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.2809938553 |
| Directory | /workspace/18.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.3087204514 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 83162826623 ps |
| CPU time | 86.54 seconds |
| Started | May 26 03:08:17 PM PDT 24 |
| Finished | May 26 03:09:44 PM PDT 24 |
| Peak memory | 210688 kb |
| Host | smart-790c079d-7976-4425-bd11-2fd3394dbb9a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087204514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.3087204514 |
| Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.1160557986 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2989719690 ps |
| CPU time | 32.56 seconds |
| Started | May 26 03:08:07 PM PDT 24 |
| Finished | May 26 03:08:40 PM PDT 24 |
| Peak memory | 288480 kb |
| Host | smart-9d76d7cd-6a58-4bd8-90b9-202d6966f030 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160557986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.1160557986 |
| Directory | /workspace/18.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2556627624 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1590112913 ps |
| CPU time | 133.76 seconds |
| Started | May 26 03:08:15 PM PDT 24 |
| Finished | May 26 03:10:30 PM PDT 24 |
| Peak memory | 215416 kb |
| Host | smart-7f7cd7c6-5b29-4e4d-bb12-3cc32a94e0dc |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556627624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.2556627624 |
| Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.3699435660 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 19740504803 ps |
| CPU time | 131.68 seconds |
| Started | May 26 03:08:15 PM PDT 24 |
| Finished | May 26 03:10:27 PM PDT 24 |
| Peak memory | 210592 kb |
| Host | smart-8a277bb6-a659-4fba-8345-97e42d4bb290 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699435660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.3699435660 |
| Directory | /workspace/18.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.2167105585 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 35694487855 ps |
| CPU time | 842.94 seconds |
| Started | May 26 03:08:08 PM PDT 24 |
| Finished | May 26 03:22:12 PM PDT 24 |
| Peak memory | 380452 kb |
| Host | smart-ee97bd5a-896a-40e3-bf6d-10851c8328e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167105585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.2167105585 |
| Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.4013652184 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3152023694 ps |
| CPU time | 12.65 seconds |
| Started | May 26 03:08:07 PM PDT 24 |
| Finished | May 26 03:08:20 PM PDT 24 |
| Peak memory | 202472 kb |
| Host | smart-f63ce294-2dc6-40b7-af06-2316ad9a755d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013652184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.4013652184 |
| Directory | /workspace/18.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.148282330 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 98131995978 ps |
| CPU time | 397.75 seconds |
| Started | May 26 03:08:09 PM PDT 24 |
| Finished | May 26 03:14:47 PM PDT 24 |
| Peak memory | 202496 kb |
| Host | smart-2c201891-257c-4a57-952d-61167099af89 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148282330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.sram_ctrl_partial_access_b2b.148282330 |
| Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.3512908725 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1348583260 ps |
| CPU time | 3.81 seconds |
| Started | May 26 03:08:14 PM PDT 24 |
| Finished | May 26 03:08:19 PM PDT 24 |
| Peak memory | 202536 kb |
| Host | smart-2e37b696-497f-4621-aab0-3d553c17781e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512908725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.3512908725 |
| Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_regwen.1964691253 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 23145690351 ps |
| CPU time | 896.12 seconds |
| Started | May 26 03:08:14 PM PDT 24 |
| Finished | May 26 03:23:11 PM PDT 24 |
| Peak memory | 380188 kb |
| Host | smart-7d499ea0-2a3a-4562-8504-087aa9ebf65a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964691253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1964691253 |
| Directory | /workspace/18.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_smoke.358169603 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3488154374 ps |
| CPU time | 137.63 seconds |
| Started | May 26 03:08:06 PM PDT 24 |
| Finished | May 26 03:10:25 PM PDT 24 |
| Peak memory | 361952 kb |
| Host | smart-a01936cb-6232-406a-8849-349cd663175c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358169603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.358169603 |
| Directory | /workspace/18.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.88438451 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 34522520764 ps |
| CPU time | 306.5 seconds |
| Started | May 26 03:08:06 PM PDT 24 |
| Finished | May 26 03:13:14 PM PDT 24 |
| Peak memory | 210708 kb |
| Host | smart-811a04f8-f970-46ee-a22d-33390699a205 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88438451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_stress_pipeline.88438451 |
| Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1982428894 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3148224359 ps |
| CPU time | 72.13 seconds |
| Started | May 26 03:08:16 PM PDT 24 |
| Finished | May 26 03:09:29 PM PDT 24 |
| Peak memory | 332296 kb |
| Host | smart-1997dc68-0e4d-4c05-8213-0418f5f2e953 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982428894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1982428894 |
| Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.3564526121 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 41248668 ps |
| CPU time | 0.63 seconds |
| Started | May 26 03:08:41 PM PDT 24 |
| Finished | May 26 03:08:42 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-da98ab4b-bd8c-44c4-94dc-b2424cdaf413 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564526121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3564526121 |
| Directory | /workspace/19.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_bijection.947586117 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 26995684568 ps |
| CPU time | 1422.79 seconds |
| Started | May 26 03:08:23 PM PDT 24 |
| Finished | May 26 03:32:07 PM PDT 24 |
| Peak memory | 210740 kb |
| Host | smart-4223a5de-1949-415d-b72c-fa36e176dcda |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947586117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection. 947586117 |
| Directory | /workspace/19.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_executable.1088964187 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 20603284347 ps |
| CPU time | 344.66 seconds |
| Started | May 26 03:08:35 PM PDT 24 |
| Finished | May 26 03:14:20 PM PDT 24 |
| Peak memory | 353852 kb |
| Host | smart-6f3e15e0-445d-485c-9ee7-07fc70b8b4ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088964187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.1088964187 |
| Directory | /workspace/19.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.1079961404 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 10120860776 ps |
| CPU time | 53.12 seconds |
| Started | May 26 03:08:35 PM PDT 24 |
| Finished | May 26 03:09:29 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-cf0ba622-38b9-47be-8e0a-8c38702827e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079961404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.1079961404 |
| Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.3655428623 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1501036452 ps |
| CPU time | 170.94 seconds |
| Started | May 26 03:08:35 PM PDT 24 |
| Finished | May 26 03:11:27 PM PDT 24 |
| Peak memory | 366996 kb |
| Host | smart-6675b942-d61c-45ef-b3c4-985c5064382b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655428623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.3655428623 |
| Directory | /workspace/19.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.3151706401 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 5630121798 ps |
| CPU time | 69.47 seconds |
| Started | May 26 03:08:32 PM PDT 24 |
| Finished | May 26 03:09:42 PM PDT 24 |
| Peak memory | 213448 kb |
| Host | smart-f34fb5eb-46bc-4814-80c2-5a267f96f32a |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151706401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.3151706401 |
| Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.1983969407 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4033005422 ps |
| CPU time | 133.32 seconds |
| Started | May 26 03:08:33 PM PDT 24 |
| Finished | May 26 03:10:46 PM PDT 24 |
| Peak memory | 210548 kb |
| Host | smart-1b050ae0-ecf7-49e9-9edd-3d05cb4e0e2a |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983969407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.1983969407 |
| Directory | /workspace/19.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.2870209054 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 50888907862 ps |
| CPU time | 1819.87 seconds |
| Started | May 26 03:08:23 PM PDT 24 |
| Finished | May 26 03:38:44 PM PDT 24 |
| Peak memory | 380392 kb |
| Host | smart-bd64aed7-3ee6-407c-9d46-758525865b55 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870209054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.2870209054 |
| Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.4253515698 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1023302587 ps |
| CPU time | 175.68 seconds |
| Started | May 26 03:08:22 PM PDT 24 |
| Finished | May 26 03:11:19 PM PDT 24 |
| Peak memory | 368000 kb |
| Host | smart-b23b5c49-a211-4647-a67a-97af7888ec14 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253515698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.4253515698 |
| Directory | /workspace/19.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1956052156 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 68088914512 ps |
| CPU time | 317.78 seconds |
| Started | May 26 03:08:23 PM PDT 24 |
| Finished | May 26 03:13:41 PM PDT 24 |
| Peak memory | 202484 kb |
| Host | smart-4627e9a7-7224-4af7-bb88-626599569958 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956052156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.1956052156 |
| Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.3421762685 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 357843455 ps |
| CPU time | 3.22 seconds |
| Started | May 26 03:08:33 PM PDT 24 |
| Finished | May 26 03:08:37 PM PDT 24 |
| Peak memory | 202536 kb |
| Host | smart-f33b2664-980e-4618-8e7b-39a6b23ace61 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421762685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3421762685 |
| Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_regwen.3259893581 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 14715245253 ps |
| CPU time | 1483.93 seconds |
| Started | May 26 03:08:35 PM PDT 24 |
| Finished | May 26 03:33:20 PM PDT 24 |
| Peak memory | 376360 kb |
| Host | smart-1acb9372-30f5-4071-aa47-13ccae23008f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259893581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3259893581 |
| Directory | /workspace/19.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_smoke.3340149072 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1487673801 ps |
| CPU time | 5.07 seconds |
| Started | May 26 03:08:22 PM PDT 24 |
| Finished | May 26 03:08:28 PM PDT 24 |
| Peak memory | 210668 kb |
| Host | smart-7d7b9bff-d5f5-4d0e-b8ec-88411da4f670 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340149072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3340149072 |
| Directory | /workspace/19.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2427478498 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 3284246699 ps |
| CPU time | 160.55 seconds |
| Started | May 26 03:08:22 PM PDT 24 |
| Finished | May 26 03:11:03 PM PDT 24 |
| Peak memory | 202492 kb |
| Host | smart-27e178ec-dcc6-43b9-974f-3bc0269daded |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427478498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.2427478498 |
| Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.823719895 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 1399774643 ps |
| CPU time | 10.18 seconds |
| Started | May 26 03:08:47 PM PDT 24 |
| Finished | May 26 03:08:57 PM PDT 24 |
| Peak memory | 225212 kb |
| Host | smart-08b03904-2857-4adf-a24d-29dbdb0bb7fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823719895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.823719895 |
| Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.3131165493 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 35340609 ps |
| CPU time | 0.68 seconds |
| Started | May 26 03:03:27 PM PDT 24 |
| Finished | May 26 03:03:29 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-04c53fa1-e975-42d3-92eb-b7752ff1db87 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131165493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3131165493 |
| Directory | /workspace/2.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_bijection.1722983989 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 33153065060 ps |
| CPU time | 2189.41 seconds |
| Started | May 26 03:03:12 PM PDT 24 |
| Finished | May 26 03:39:42 PM PDT 24 |
| Peak memory | 210664 kb |
| Host | smart-0db47bc8-e866-439b-9ab8-e540b5f216a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722983989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 1722983989 |
| Directory | /workspace/2.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_executable.4042888536 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 6091650855 ps |
| CPU time | 119.37 seconds |
| Started | May 26 03:03:13 PM PDT 24 |
| Finished | May 26 03:05:13 PM PDT 24 |
| Peak memory | 329212 kb |
| Host | smart-9d22bafa-7119-4b0a-a27f-ee18018811bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042888536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.4042888536 |
| Directory | /workspace/2.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.3675446513 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 51830255533 ps |
| CPU time | 74.07 seconds |
| Started | May 26 03:03:15 PM PDT 24 |
| Finished | May 26 03:04:30 PM PDT 24 |
| Peak memory | 202484 kb |
| Host | smart-138af903-5eeb-479f-8a02-c0166c893869 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675446513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.3675446513 |
| Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.4256142131 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 741628898 ps |
| CPU time | 15.75 seconds |
| Started | May 26 03:03:14 PM PDT 24 |
| Finished | May 26 03:03:31 PM PDT 24 |
| Peak memory | 244432 kb |
| Host | smart-652aed75-a186-43c2-b2fa-7e1661718b63 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256142131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.4256142131 |
| Directory | /workspace/2.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1335403757 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 5079305510 ps |
| CPU time | 175.5 seconds |
| Started | May 26 03:03:20 PM PDT 24 |
| Finished | May 26 03:06:17 PM PDT 24 |
| Peak memory | 215956 kb |
| Host | smart-cea00d19-8ec5-47db-a8b5-cdd4cb988e23 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335403757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.1335403757 |
| Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.1842927272 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 10937648699 ps |
| CPU time | 311.84 seconds |
| Started | May 26 03:03:21 PM PDT 24 |
| Finished | May 26 03:08:34 PM PDT 24 |
| Peak memory | 210572 kb |
| Host | smart-e1c33843-9f2d-48cb-9067-45453fdbbca1 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842927272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.1842927272 |
| Directory | /workspace/2.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.3390449572 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 10080705774 ps |
| CPU time | 1276.63 seconds |
| Started | May 26 03:03:12 PM PDT 24 |
| Finished | May 26 03:24:29 PM PDT 24 |
| Peak memory | 380424 kb |
| Host | smart-1f742c9d-2bf9-42de-9bf2-1fb98d9d351a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390449572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.3390449572 |
| Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.3723150915 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1094477737 ps |
| CPU time | 14.53 seconds |
| Started | May 26 03:03:16 PM PDT 24 |
| Finished | May 26 03:03:32 PM PDT 24 |
| Peak memory | 210812 kb |
| Host | smart-7059b574-58e9-483f-9287-99fe44679c1b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723150915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.3723150915 |
| Directory | /workspace/2.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.129141204 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 13987489639 ps |
| CPU time | 314.93 seconds |
| Started | May 26 03:03:16 PM PDT 24 |
| Finished | May 26 03:08:32 PM PDT 24 |
| Peak memory | 202544 kb |
| Host | smart-4aa6d02e-96bc-448f-a802-7377e43d11a8 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129141204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.sram_ctrl_partial_access_b2b.129141204 |
| Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.1819330628 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 359679789 ps |
| CPU time | 3.11 seconds |
| Started | May 26 03:03:20 PM PDT 24 |
| Finished | May 26 03:03:25 PM PDT 24 |
| Peak memory | 202576 kb |
| Host | smart-4d7e8a7b-6112-4d86-b7df-a71ea73fb28e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819330628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1819330628 |
| Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_regwen.1757493663 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 44151886246 ps |
| CPU time | 509.33 seconds |
| Started | May 26 03:03:21 PM PDT 24 |
| Finished | May 26 03:11:52 PM PDT 24 |
| Peak memory | 363888 kb |
| Host | smart-113b963e-bef6-4019-9682-0d619428af9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757493663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1757493663 |
| Directory | /workspace/2.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.4213214036 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 339323494 ps |
| CPU time | 3.38 seconds |
| Started | May 26 03:03:28 PM PDT 24 |
| Finished | May 26 03:03:32 PM PDT 24 |
| Peak memory | 222332 kb |
| Host | smart-8fde510a-b6c5-4d8b-92d2-4e18b8e1e388 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213214036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.4213214036 |
| Directory | /workspace/2.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_smoke.4273668848 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 700822744 ps |
| CPU time | 38.81 seconds |
| Started | May 26 03:03:16 PM PDT 24 |
| Finished | May 26 03:03:56 PM PDT 24 |
| Peak memory | 285856 kb |
| Host | smart-4cc19dec-61c6-4329-82b3-45e29761f8de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273668848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.4273668848 |
| Directory | /workspace/2.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2503159656 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 360039140 ps |
| CPU time | 9.39 seconds |
| Started | May 26 03:03:20 PM PDT 24 |
| Finished | May 26 03:03:31 PM PDT 24 |
| Peak memory | 210732 kb |
| Host | smart-03a43366-cb98-4dd2-90a9-e8972c221d8c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2503159656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2503159656 |
| Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3056187168 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 37367154587 ps |
| CPU time | 405.97 seconds |
| Started | May 26 03:03:12 PM PDT 24 |
| Finished | May 26 03:09:59 PM PDT 24 |
| Peak memory | 202496 kb |
| Host | smart-f572d9f7-c75c-4f5f-9bd4-82e4fda62465 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056187168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.3056187168 |
| Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.6031032 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1486543595 ps |
| CPU time | 29.92 seconds |
| Started | May 26 03:03:13 PM PDT 24 |
| Finished | May 26 03:03:44 PM PDT 24 |
| Peak memory | 288284 kb |
| Host | smart-dfcb69d1-ed30-4ebb-a876-55f89eee3b56 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6031032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_throughput_w_partial_write.6031032 |
| Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.3804873714 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 25183041 ps |
| CPU time | 0.63 seconds |
| Started | May 26 03:08:56 PM PDT 24 |
| Finished | May 26 03:08:57 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-4b9c42bc-b1fb-4c79-9ad0-3538d7bbac71 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804873714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.3804873714 |
| Directory | /workspace/20.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_executable.2941001032 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 25936604078 ps |
| CPU time | 692.95 seconds |
| Started | May 26 03:08:49 PM PDT 24 |
| Finished | May 26 03:20:22 PM PDT 24 |
| Peak memory | 373516 kb |
| Host | smart-138712f7-939f-4410-8870-0926487ee9e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941001032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.2941001032 |
| Directory | /workspace/20.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.2097999347 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 9718211812 ps |
| CPU time | 64.32 seconds |
| Started | May 26 03:08:42 PM PDT 24 |
| Finished | May 26 03:09:47 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-ae9c6c2e-badb-4475-8826-e8d9f64561de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097999347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.2097999347 |
| Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.2840886067 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 788249107 ps |
| CPU time | 122.22 seconds |
| Started | May 26 03:08:42 PM PDT 24 |
| Finished | May 26 03:10:45 PM PDT 24 |
| Peak memory | 350632 kb |
| Host | smart-ba83028f-d7ee-4b5f-b300-8052418cc838 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840886067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.2840886067 |
| Directory | /workspace/20.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.537228162 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2532960602 ps |
| CPU time | 142.18 seconds |
| Started | May 26 03:08:50 PM PDT 24 |
| Finished | May 26 03:11:13 PM PDT 24 |
| Peak memory | 214368 kb |
| Host | smart-4dded211-aa6b-4e01-a590-2236e152b805 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537228162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20 .sram_ctrl_mem_partial_access.537228162 |
| Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.128839384 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 149422791467 ps |
| CPU time | 377.61 seconds |
| Started | May 26 03:08:48 PM PDT 24 |
| Finished | May 26 03:15:07 PM PDT 24 |
| Peak memory | 210608 kb |
| Host | smart-ff28d3c4-b6ec-40e4-982a-59b54d1336c3 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128839384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl _mem_walk.128839384 |
| Directory | /workspace/20.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.1668865129 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 21029728573 ps |
| CPU time | 1467.59 seconds |
| Started | May 26 03:08:44 PM PDT 24 |
| Finished | May 26 03:33:12 PM PDT 24 |
| Peak memory | 376336 kb |
| Host | smart-c0cdb3df-c42e-4f36-b2f7-03409c84b32d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668865129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.1668865129 |
| Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.157217973 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1307216307 ps |
| CPU time | 21.83 seconds |
| Started | May 26 03:08:44 PM PDT 24 |
| Finished | May 26 03:09:06 PM PDT 24 |
| Peak memory | 210600 kb |
| Host | smart-de4ce22b-67ee-4a75-9f63-fd05bc100225 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157217973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.s ram_ctrl_partial_access.157217973 |
| Directory | /workspace/20.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3100629432 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 87216511963 ps |
| CPU time | 446.73 seconds |
| Started | May 26 03:08:41 PM PDT 24 |
| Finished | May 26 03:16:08 PM PDT 24 |
| Peak memory | 202496 kb |
| Host | smart-29ad0bdc-d108-420c-be5e-fdd9f6b5ba23 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100629432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.3100629432 |
| Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.3566301514 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1355804541 ps |
| CPU time | 3.23 seconds |
| Started | May 26 03:08:47 PM PDT 24 |
| Finished | May 26 03:08:51 PM PDT 24 |
| Peak memory | 202572 kb |
| Host | smart-7bac0bee-6568-4352-a7cd-54837f6353b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566301514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3566301514 |
| Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_regwen.969545090 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 66016105664 ps |
| CPU time | 1949.05 seconds |
| Started | May 26 03:08:49 PM PDT 24 |
| Finished | May 26 03:41:19 PM PDT 24 |
| Peak memory | 379420 kb |
| Host | smart-53bd9ab4-15f8-49d3-8db2-84e86760f67b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969545090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.969545090 |
| Directory | /workspace/20.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_smoke.4160471634 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 718286381 ps |
| CPU time | 3.87 seconds |
| Started | May 26 03:08:43 PM PDT 24 |
| Finished | May 26 03:08:48 PM PDT 24 |
| Peak memory | 202404 kb |
| Host | smart-36f17e56-c0ef-4e35-9b5e-f601fa14b8c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160471634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4160471634 |
| Directory | /workspace/20.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3095028438 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2648863282 ps |
| CPU time | 21.84 seconds |
| Started | May 26 03:08:48 PM PDT 24 |
| Finished | May 26 03:09:11 PM PDT 24 |
| Peak memory | 210764 kb |
| Host | smart-5631a5a2-7a4a-43e1-b7fa-a4a07219d489 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3095028438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3095028438 |
| Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.296469479 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 6023140665 ps |
| CPU time | 314.91 seconds |
| Started | May 26 03:08:44 PM PDT 24 |
| Finished | May 26 03:13:59 PM PDT 24 |
| Peak memory | 210672 kb |
| Host | smart-716238de-341b-4848-b3d8-6b90a6e27e7f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296469479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20 .sram_ctrl_stress_pipeline.296469479 |
| Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2070774055 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 810905486 ps |
| CPU time | 9.6 seconds |
| Started | May 26 03:08:40 PM PDT 24 |
| Finished | May 26 03:08:51 PM PDT 24 |
| Peak memory | 224508 kb |
| Host | smart-9f90b979-dee8-4b17-87b5-01e6dfa7b046 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070774055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.2070774055 |
| Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.2978259090 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 14200242 ps |
| CPU time | 0.68 seconds |
| Started | May 26 03:09:10 PM PDT 24 |
| Finished | May 26 03:09:11 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-398be6b2-b037-4835-9578-121871f3c49b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978259090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2978259090 |
| Directory | /workspace/21.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_bijection.3534844149 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 32439857166 ps |
| CPU time | 1847.73 seconds |
| Started | May 26 03:08:57 PM PDT 24 |
| Finished | May 26 03:39:45 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-d66bdcb7-803c-4ee9-acc6-f15aed81c5f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534844149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .3534844149 |
| Directory | /workspace/21.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_executable.631965180 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 96695853170 ps |
| CPU time | 1531.82 seconds |
| Started | May 26 03:09:04 PM PDT 24 |
| Finished | May 26 03:34:37 PM PDT 24 |
| Peak memory | 376304 kb |
| Host | smart-4e8052de-1502-46f8-964f-d72d277ee922 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631965180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executabl e.631965180 |
| Directory | /workspace/21.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.2369339775 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 18981718700 ps |
| CPU time | 63.52 seconds |
| Started | May 26 03:09:04 PM PDT 24 |
| Finished | May 26 03:10:08 PM PDT 24 |
| Peak memory | 202528 kb |
| Host | smart-fe91434b-337b-48e1-8172-11513542a88d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369339775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.2369339775 |
| Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.2699870238 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 896516674 ps |
| CPU time | 9.12 seconds |
| Started | May 26 03:09:03 PM PDT 24 |
| Finished | May 26 03:09:13 PM PDT 24 |
| Peak memory | 221044 kb |
| Host | smart-0d561553-2707-4f0e-95dd-c6a02d132e1d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699870238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.2699870238 |
| Directory | /workspace/21.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3571980651 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 22179133786 ps |
| CPU time | 171.01 seconds |
| Started | May 26 03:09:11 PM PDT 24 |
| Finished | May 26 03:12:02 PM PDT 24 |
| Peak memory | 216020 kb |
| Host | smart-31a552d2-6382-45c6-a9b5-f41cfc9d25cd |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571980651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.3571980651 |
| Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.2054549027 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 5370652386 ps |
| CPU time | 155.36 seconds |
| Started | May 26 03:09:10 PM PDT 24 |
| Finished | May 26 03:11:46 PM PDT 24 |
| Peak memory | 210584 kb |
| Host | smart-93d0e106-02ae-41ad-b4a5-38855e5515d3 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054549027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.2054549027 |
| Directory | /workspace/21.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.306675300 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 33893546750 ps |
| CPU time | 694.79 seconds |
| Started | May 26 03:08:56 PM PDT 24 |
| Finished | May 26 03:20:31 PM PDT 24 |
| Peak memory | 375600 kb |
| Host | smart-46fe6a1f-79c1-4d84-9e4b-e7b42bbb7805 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306675300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multip le_keys.306675300 |
| Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.280636128 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1381684147 ps |
| CPU time | 19.91 seconds |
| Started | May 26 03:08:56 PM PDT 24 |
| Finished | May 26 03:09:16 PM PDT 24 |
| Peak memory | 202472 kb |
| Host | smart-e4e6c5c4-d9e7-4c3b-8dfe-62cd7444179f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280636128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.s ram_ctrl_partial_access.280636128 |
| Directory | /workspace/21.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3826016640 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 16210208317 ps |
| CPU time | 314.32 seconds |
| Started | May 26 03:09:02 PM PDT 24 |
| Finished | May 26 03:14:16 PM PDT 24 |
| Peak memory | 202480 kb |
| Host | smart-8731e0f4-475b-4631-8dbc-6c603938db70 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826016640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.3826016640 |
| Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.911790240 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1403097305 ps |
| CPU time | 3.69 seconds |
| Started | May 26 03:09:11 PM PDT 24 |
| Finished | May 26 03:09:16 PM PDT 24 |
| Peak memory | 202560 kb |
| Host | smart-82d65f50-9552-47de-802c-05e8bb2421da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911790240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.911790240 |
| Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_regwen.1041487920 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2935695012 ps |
| CPU time | 766.21 seconds |
| Started | May 26 03:09:01 PM PDT 24 |
| Finished | May 26 03:21:48 PM PDT 24 |
| Peak memory | 370232 kb |
| Host | smart-09a88b63-3237-4393-b1a5-ee370de89e4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041487920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1041487920 |
| Directory | /workspace/21.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_smoke.97228499 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 465554540 ps |
| CPU time | 157.64 seconds |
| Started | May 26 03:08:55 PM PDT 24 |
| Finished | May 26 03:11:33 PM PDT 24 |
| Peak memory | 375368 kb |
| Host | smart-d7327bbc-8ee5-49f2-aaa8-f4ba7d07d535 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97228499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.97228499 |
| Directory | /workspace/21.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.249574638 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1217662955 ps |
| CPU time | 29.75 seconds |
| Started | May 26 03:09:10 PM PDT 24 |
| Finished | May 26 03:09:40 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-155d313d-f032-439a-a7f5-670b7f767716 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=249574638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.249574638 |
| Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3416844943 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 6573864273 ps |
| CPU time | 365.83 seconds |
| Started | May 26 03:08:55 PM PDT 24 |
| Finished | May 26 03:15:02 PM PDT 24 |
| Peak memory | 202472 kb |
| Host | smart-5359664f-fca7-47be-ad82-76cdeabb5ea1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416844943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.3416844943 |
| Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3867938283 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 704045005 ps |
| CPU time | 6.52 seconds |
| Started | May 26 03:09:05 PM PDT 24 |
| Finished | May 26 03:09:12 PM PDT 24 |
| Peak memory | 210616 kb |
| Host | smart-3125aa24-8522-4e1f-8616-2e2c9a760bd7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867938283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3867938283 |
| Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.637479210 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 22769587 ps |
| CPU time | 0.68 seconds |
| Started | May 26 03:09:18 PM PDT 24 |
| Finished | May 26 03:09:19 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-a35c8135-feb9-445c-9be1-8cbb79747684 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637479210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.637479210 |
| Directory | /workspace/22.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_bijection.301120722 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 133686287492 ps |
| CPU time | 2435.4 seconds |
| Started | May 26 03:09:13 PM PDT 24 |
| Finished | May 26 03:49:49 PM PDT 24 |
| Peak memory | 210716 kb |
| Host | smart-0adb7dce-d435-4a8c-9e6b-2005a1d812d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301120722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection. 301120722 |
| Directory | /workspace/22.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_executable.1979701872 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 191944880923 ps |
| CPU time | 1163.22 seconds |
| Started | May 26 03:09:17 PM PDT 24 |
| Finished | May 26 03:28:41 PM PDT 24 |
| Peak memory | 379628 kb |
| Host | smart-b734622a-4de0-4c9b-a447-4e0f2d22c2c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979701872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.1979701872 |
| Directory | /workspace/22.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.1715789431 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 12697858502 ps |
| CPU time | 83.82 seconds |
| Started | May 26 03:09:17 PM PDT 24 |
| Finished | May 26 03:10:42 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-d86ba099-e517-4525-8f25-f4f24b2a6cbe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715789431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.1715789431 |
| Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.126840365 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2799029173 ps |
| CPU time | 7.83 seconds |
| Started | May 26 03:09:17 PM PDT 24 |
| Finished | May 26 03:09:26 PM PDT 24 |
| Peak memory | 210700 kb |
| Host | smart-0ef7ac5a-eaf5-4b63-9ed5-f7d0706e5295 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126840365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.sram_ctrl_max_throughput.126840365 |
| Directory | /workspace/22.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.272252193 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1646631677 ps |
| CPU time | 129.45 seconds |
| Started | May 26 03:09:17 PM PDT 24 |
| Finished | May 26 03:11:27 PM PDT 24 |
| Peak memory | 216000 kb |
| Host | smart-569a04c8-e8b9-4758-b206-a23fb7a52880 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272252193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_mem_partial_access.272252193 |
| Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.776295844 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 25595770983 ps |
| CPU time | 339.07 seconds |
| Started | May 26 03:09:16 PM PDT 24 |
| Finished | May 26 03:14:55 PM PDT 24 |
| Peak memory | 202396 kb |
| Host | smart-daa0b61e-eb33-4c97-a469-7d5b6ca0b16b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776295844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl _mem_walk.776295844 |
| Directory | /workspace/22.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.2347649544 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 123296919692 ps |
| CPU time | 1620.75 seconds |
| Started | May 26 03:09:13 PM PDT 24 |
| Finished | May 26 03:36:15 PM PDT 24 |
| Peak memory | 379480 kb |
| Host | smart-942b7e45-586a-4abe-adf4-ae4847682475 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347649544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.2347649544 |
| Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.3763277437 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1052682354 ps |
| CPU time | 24.22 seconds |
| Started | May 26 03:09:17 PM PDT 24 |
| Finished | May 26 03:09:42 PM PDT 24 |
| Peak memory | 202412 kb |
| Host | smart-83423d26-7733-4ec9-88da-7ee9f4c7f6b0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763277437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.3763277437 |
| Directory | /workspace/22.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.940511825 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 16401477245 ps |
| CPU time | 434.21 seconds |
| Started | May 26 03:09:20 PM PDT 24 |
| Finished | May 26 03:16:35 PM PDT 24 |
| Peak memory | 202400 kb |
| Host | smart-ce8016c2-3d22-4a1d-b58a-c8a1554981b4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940511825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.sram_ctrl_partial_access_b2b.940511825 |
| Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.25911414 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 723914316 ps |
| CPU time | 3.05 seconds |
| Started | May 26 03:09:20 PM PDT 24 |
| Finished | May 26 03:09:23 PM PDT 24 |
| Peak memory | 202480 kb |
| Host | smart-d5cb8335-4911-482e-9d74-cf07e56a4a19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25911414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.25911414 |
| Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_regwen.1072516081 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 19136172549 ps |
| CPU time | 1580.91 seconds |
| Started | May 26 03:09:19 PM PDT 24 |
| Finished | May 26 03:35:40 PM PDT 24 |
| Peak memory | 380412 kb |
| Host | smart-966b43bd-44f3-4f2c-a00b-2f2d269a31b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072516081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1072516081 |
| Directory | /workspace/22.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_smoke.2358468819 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 651399510 ps |
| CPU time | 28.7 seconds |
| Started | May 26 03:09:09 PM PDT 24 |
| Finished | May 26 03:09:39 PM PDT 24 |
| Peak memory | 281004 kb |
| Host | smart-d5cc9293-410a-4f51-965c-3495ee28b2c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358468819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2358468819 |
| Directory | /workspace/22.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.883864627 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 7656115671 ps |
| CPU time | 162.75 seconds |
| Started | May 26 03:09:19 PM PDT 24 |
| Finished | May 26 03:12:02 PM PDT 24 |
| Peak memory | 237396 kb |
| Host | smart-5119ec4f-954f-4276-8841-26b8485641e3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=883864627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.883864627 |
| Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.19468076 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 11447836516 ps |
| CPU time | 199.45 seconds |
| Started | May 26 03:09:17 PM PDT 24 |
| Finished | May 26 03:12:37 PM PDT 24 |
| Peak memory | 210688 kb |
| Host | smart-64a4c9ec-c432-4bb1-be38-723f41d2b429 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19468076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_stress_pipeline.19468076 |
| Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.106953649 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1543885438 ps |
| CPU time | 139.22 seconds |
| Started | May 26 03:09:18 PM PDT 24 |
| Finished | May 26 03:11:38 PM PDT 24 |
| Peak memory | 354820 kb |
| Host | smart-0b4e54c9-cfaf-4c2c-9789-dda69bb70d82 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106953649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_throughput_w_partial_write.106953649 |
| Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.1909210493 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 41149789 ps |
| CPU time | 0.64 seconds |
| Started | May 26 03:09:39 PM PDT 24 |
| Finished | May 26 03:09:40 PM PDT 24 |
| Peak memory | 201644 kb |
| Host | smart-b24d2225-52f7-48bb-92cd-468fed442bf6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909210493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.1909210493 |
| Directory | /workspace/23.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_bijection.3019188741 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 120999382944 ps |
| CPU time | 636.59 seconds |
| Started | May 26 03:09:27 PM PDT 24 |
| Finished | May 26 03:20:04 PM PDT 24 |
| Peak memory | 210572 kb |
| Host | smart-bf0dfdf1-9435-46b7-b1bf-fdc56936b06a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019188741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .3019188741 |
| Directory | /workspace/23.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_executable.4087943879 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 35151658363 ps |
| CPU time | 726.89 seconds |
| Started | May 26 03:09:32 PM PDT 24 |
| Finished | May 26 03:21:39 PM PDT 24 |
| Peak memory | 377320 kb |
| Host | smart-4d5503f3-db3b-4370-945d-a6b9039cc26d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087943879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.4087943879 |
| Directory | /workspace/23.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.671664665 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 46654931630 ps |
| CPU time | 78.46 seconds |
| Started | May 26 03:09:36 PM PDT 24 |
| Finished | May 26 03:10:55 PM PDT 24 |
| Peak memory | 215544 kb |
| Host | smart-973936fc-5801-4ecb-9b5e-0cbcf7161982 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671664665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_esc alation.671664665 |
| Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.139906005 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1554205714 ps |
| CPU time | 56.32 seconds |
| Started | May 26 03:09:26 PM PDT 24 |
| Finished | May 26 03:10:22 PM PDT 24 |
| Peak memory | 300552 kb |
| Host | smart-aebd3d5a-d343-40df-a1f8-3656b8f1e8fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139906005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.sram_ctrl_max_throughput.139906005 |
| Directory | /workspace/23.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2227883143 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 12216823478 ps |
| CPU time | 152.62 seconds |
| Started | May 26 03:09:34 PM PDT 24 |
| Finished | May 26 03:12:07 PM PDT 24 |
| Peak memory | 214996 kb |
| Host | smart-35a47947-533c-4098-9d68-11f4b77624dd |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227883143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.2227883143 |
| Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.2789573921 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 13593272849 ps |
| CPU time | 148.91 seconds |
| Started | May 26 03:09:33 PM PDT 24 |
| Finished | May 26 03:12:02 PM PDT 24 |
| Peak memory | 210664 kb |
| Host | smart-3806b333-0951-408d-8713-fee38840a494 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789573921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.2789573921 |
| Directory | /workspace/23.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.715720450 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 6976524597 ps |
| CPU time | 443.56 seconds |
| Started | May 26 03:09:24 PM PDT 24 |
| Finished | May 26 03:16:48 PM PDT 24 |
| Peak memory | 363220 kb |
| Host | smart-815b5fe1-121a-4c1a-bdf2-6a8d35e1cafe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715720450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multip le_keys.715720450 |
| Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.2257502864 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1626152022 ps |
| CPU time | 14.01 seconds |
| Started | May 26 03:09:25 PM PDT 24 |
| Finished | May 26 03:09:40 PM PDT 24 |
| Peak memory | 210612 kb |
| Host | smart-c81a8d99-65c9-4c48-b171-ca2c4d63b64c |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257502864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.2257502864 |
| Directory | /workspace/23.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1553992317 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 11769399421 ps |
| CPU time | 381.28 seconds |
| Started | May 26 03:09:25 PM PDT 24 |
| Finished | May 26 03:15:46 PM PDT 24 |
| Peak memory | 210732 kb |
| Host | smart-ed8b03cf-13ba-4f41-98aa-19afbcfc003a |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553992317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.1553992317 |
| Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.3912465086 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2576145934 ps |
| CPU time | 3.49 seconds |
| Started | May 26 03:09:33 PM PDT 24 |
| Finished | May 26 03:09:37 PM PDT 24 |
| Peak memory | 202608 kb |
| Host | smart-a351fd05-5af9-488f-9609-e7043d6af9be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912465086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3912465086 |
| Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_regwen.4203216967 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 24289828618 ps |
| CPU time | 1618.27 seconds |
| Started | May 26 03:09:33 PM PDT 24 |
| Finished | May 26 03:36:32 PM PDT 24 |
| Peak memory | 380380 kb |
| Host | smart-01f8faa7-d925-4837-8799-23c7af98d9a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203216967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.4203216967 |
| Directory | /workspace/23.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_smoke.3980643040 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 932883791 ps |
| CPU time | 10.9 seconds |
| Started | May 26 03:09:23 PM PDT 24 |
| Finished | May 26 03:09:35 PM PDT 24 |
| Peak memory | 202408 kb |
| Host | smart-6f9e5b42-e59d-4393-b44f-ac928ce4b79f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980643040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3980643040 |
| Directory | /workspace/23.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3520728080 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 11318172853 ps |
| CPU time | 180.49 seconds |
| Started | May 26 03:09:24 PM PDT 24 |
| Finished | May 26 03:12:25 PM PDT 24 |
| Peak memory | 210660 kb |
| Host | smart-9194890c-b655-43e4-82f7-fa4144889f30 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520728080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3520728080 |
| Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.875030628 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 1544665091 ps |
| CPU time | 175.55 seconds |
| Started | May 26 03:09:27 PM PDT 24 |
| Finished | May 26 03:12:23 PM PDT 24 |
| Peak memory | 372008 kb |
| Host | smart-8802b052-9258-427c-aafb-1e8d51464bbd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875030628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.875030628 |
| Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.3125955986 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 13070271 ps |
| CPU time | 0.62 seconds |
| Started | May 26 03:09:47 PM PDT 24 |
| Finished | May 26 03:09:48 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-9f6c6b53-e7a3-4146-a65c-93267c73c54e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125955986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.3125955986 |
| Directory | /workspace/24.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_bijection.2858200180 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 250771203177 ps |
| CPU time | 1484.5 seconds |
| Started | May 26 03:09:39 PM PDT 24 |
| Finished | May 26 03:34:24 PM PDT 24 |
| Peak memory | 210644 kb |
| Host | smart-8b67d2a6-328d-49c0-86b3-4ff256a927b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858200180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .2858200180 |
| Directory | /workspace/24.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_executable.78216764 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 21440798758 ps |
| CPU time | 1304.46 seconds |
| Started | May 26 03:09:45 PM PDT 24 |
| Finished | May 26 03:31:30 PM PDT 24 |
| Peak memory | 374380 kb |
| Host | smart-cc5554a2-1b85-4ec2-bee7-8bd08600c6f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78216764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable .78216764 |
| Directory | /workspace/24.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.3530907487 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 63311550169 ps |
| CPU time | 55.96 seconds |
| Started | May 26 03:09:46 PM PDT 24 |
| Finished | May 26 03:10:43 PM PDT 24 |
| Peak memory | 202484 kb |
| Host | smart-1bc66d04-f957-4494-8668-158b74cd4448 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530907487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.3530907487 |
| Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.1345226052 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1523755946 ps |
| CPU time | 111.29 seconds |
| Started | May 26 03:09:39 PM PDT 24 |
| Finished | May 26 03:11:31 PM PDT 24 |
| Peak memory | 337548 kb |
| Host | smart-ae4f737e-a9ed-4992-b619-c1629e53ca1b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345226052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.1345226052 |
| Directory | /workspace/24.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1859172143 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 6426862316 ps |
| CPU time | 156.3 seconds |
| Started | May 26 03:09:48 PM PDT 24 |
| Finished | May 26 03:12:24 PM PDT 24 |
| Peak memory | 215980 kb |
| Host | smart-d9dcfb19-da64-4f93-babf-2016a7494030 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859172143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1859172143 |
| Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.2590232077 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 17531478099 ps |
| CPU time | 157.41 seconds |
| Started | May 26 03:09:46 PM PDT 24 |
| Finished | May 26 03:12:24 PM PDT 24 |
| Peak memory | 210592 kb |
| Host | smart-bfeab6e6-98cd-4a25-9511-353717a9a6ac |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590232077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2590232077 |
| Directory | /workspace/24.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.67711802 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1281959193 ps |
| CPU time | 161.06 seconds |
| Started | May 26 03:09:40 PM PDT 24 |
| Finished | May 26 03:12:22 PM PDT 24 |
| Peak memory | 344748 kb |
| Host | smart-6beceb6d-a507-4b31-a2f7-69e63bda085e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67711802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multipl e_keys.67711802 |
| Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.2580095383 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1049433403 ps |
| CPU time | 13.93 seconds |
| Started | May 26 03:09:39 PM PDT 24 |
| Finished | May 26 03:09:54 PM PDT 24 |
| Peak memory | 250580 kb |
| Host | smart-617f892f-bfd3-4bd1-84e2-09d8d8fcd456 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580095383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.2580095383 |
| Directory | /workspace/24.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.421592553 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 8814309924 ps |
| CPU time | 421.95 seconds |
| Started | May 26 03:09:40 PM PDT 24 |
| Finished | May 26 03:16:43 PM PDT 24 |
| Peak memory | 202448 kb |
| Host | smart-d47bee2b-b7db-47dc-a73c-c2551895716e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421592553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.sram_ctrl_partial_access_b2b.421592553 |
| Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.1519254175 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1343502270 ps |
| CPU time | 3.58 seconds |
| Started | May 26 03:09:49 PM PDT 24 |
| Finished | May 26 03:09:53 PM PDT 24 |
| Peak memory | 202540 kb |
| Host | smart-77193bf0-3768-4efd-a39b-6f64d3c734b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519254175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1519254175 |
| Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_regwen.3681143684 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 14117246742 ps |
| CPU time | 1275.37 seconds |
| Started | May 26 03:09:46 PM PDT 24 |
| Finished | May 26 03:31:01 PM PDT 24 |
| Peak memory | 375288 kb |
| Host | smart-c7f2df0d-4e83-43ae-87f3-df8244e3497b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681143684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3681143684 |
| Directory | /workspace/24.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_smoke.2993855584 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 9351068810 ps |
| CPU time | 13.78 seconds |
| Started | May 26 03:09:40 PM PDT 24 |
| Finished | May 26 03:09:55 PM PDT 24 |
| Peak memory | 210708 kb |
| Host | smart-1105bdbd-cc23-4032-8922-deef801a3726 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993855584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2993855584 |
| Directory | /workspace/24.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4080169471 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1958610376 ps |
| CPU time | 21.76 seconds |
| Started | May 26 03:09:48 PM PDT 24 |
| Finished | May 26 03:10:10 PM PDT 24 |
| Peak memory | 210704 kb |
| Host | smart-9c03a29b-c721-453b-8bdc-a2e5b86ff87a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4080169471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.4080169471 |
| Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.442996500 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 6407264287 ps |
| CPU time | 130.59 seconds |
| Started | May 26 03:09:39 PM PDT 24 |
| Finished | May 26 03:11:51 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-c8bb78a8-85e4-463d-a9ce-78b0b26af9d0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442996500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .sram_ctrl_stress_pipeline.442996500 |
| Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2300893885 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2175025392 ps |
| CPU time | 167.53 seconds |
| Started | May 26 03:09:47 PM PDT 24 |
| Finished | May 26 03:12:35 PM PDT 24 |
| Peak memory | 371168 kb |
| Host | smart-2e75a3ec-6f06-4f1e-87e5-50f46cb7a782 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300893885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.2300893885 |
| Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.2947425703 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 13439243 ps |
| CPU time | 0.67 seconds |
| Started | May 26 03:10:07 PM PDT 24 |
| Finished | May 26 03:10:08 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-4a19b396-7f71-4b06-a9b9-a8cb08955d6a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947425703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2947425703 |
| Directory | /workspace/25.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_bijection.1675040154 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 73985354378 ps |
| CPU time | 1145.57 seconds |
| Started | May 26 03:09:54 PM PDT 24 |
| Finished | May 26 03:29:00 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-e75a22b6-6fe9-4bce-ae4c-a13de2aa9189 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675040154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .1675040154 |
| Directory | /workspace/25.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_executable.2928794272 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 117076252256 ps |
| CPU time | 557.12 seconds |
| Started | May 26 03:10:03 PM PDT 24 |
| Finished | May 26 03:19:20 PM PDT 24 |
| Peak memory | 374240 kb |
| Host | smart-81d9ec02-5099-4416-ad57-d124c7330d76 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928794272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.2928794272 |
| Directory | /workspace/25.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.1180101881 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 33319797878 ps |
| CPU time | 79.69 seconds |
| Started | May 26 03:09:56 PM PDT 24 |
| Finished | May 26 03:11:16 PM PDT 24 |
| Peak memory | 202492 kb |
| Host | smart-afd3b8e2-3ed3-41f5-be62-7bf4d2df8037 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180101881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.1180101881 |
| Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.1416186998 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 770603789 ps |
| CPU time | 152.39 seconds |
| Started | May 26 03:09:56 PM PDT 24 |
| Finished | May 26 03:12:29 PM PDT 24 |
| Peak memory | 370064 kb |
| Host | smart-d8fa8e3b-6e82-4b63-8ff4-0feb91e5930c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416186998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.1416186998 |
| Directory | /workspace/25.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3902175014 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4944866996 ps |
| CPU time | 142.77 seconds |
| Started | May 26 03:10:00 PM PDT 24 |
| Finished | May 26 03:12:24 PM PDT 24 |
| Peak memory | 214932 kb |
| Host | smart-c46d32e3-dbd8-423b-92aa-777893f59c90 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902175014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.3902175014 |
| Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.3027609978 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 7445256123 ps |
| CPU time | 164.95 seconds |
| Started | May 26 03:10:00 PM PDT 24 |
| Finished | May 26 03:12:46 PM PDT 24 |
| Peak memory | 210584 kb |
| Host | smart-40a24c4f-1279-47d4-a91e-89b164c33498 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027609978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.3027609978 |
| Directory | /workspace/25.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.753270382 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 95791602719 ps |
| CPU time | 1178.02 seconds |
| Started | May 26 03:09:56 PM PDT 24 |
| Finished | May 26 03:29:35 PM PDT 24 |
| Peak memory | 375676 kb |
| Host | smart-1c68e498-4804-49f5-b551-5d84407493b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753270382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multip le_keys.753270382 |
| Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.882172818 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1565080170 ps |
| CPU time | 15.99 seconds |
| Started | May 26 03:10:05 PM PDT 24 |
| Finished | May 26 03:10:21 PM PDT 24 |
| Peak memory | 202444 kb |
| Host | smart-e720ef5e-71ba-453b-8c63-c6a66301bf2b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882172818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.s ram_ctrl_partial_access.882172818 |
| Directory | /workspace/25.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2339719785 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 159083024048 ps |
| CPU time | 445.32 seconds |
| Started | May 26 03:09:56 PM PDT 24 |
| Finished | May 26 03:17:22 PM PDT 24 |
| Peak memory | 210720 kb |
| Host | smart-575dc772-639d-454e-927e-71a6ef6fff1f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339719785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.2339719785 |
| Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.4247230645 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1408964321 ps |
| CPU time | 3.78 seconds |
| Started | May 26 03:10:01 PM PDT 24 |
| Finished | May 26 03:10:05 PM PDT 24 |
| Peak memory | 202532 kb |
| Host | smart-f44260db-8935-49a0-9874-c18444d1a8d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247230645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.4247230645 |
| Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_regwen.3742909543 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 72773332538 ps |
| CPU time | 964.57 seconds |
| Started | May 26 03:10:04 PM PDT 24 |
| Finished | May 26 03:26:10 PM PDT 24 |
| Peak memory | 380412 kb |
| Host | smart-169f49ac-d5eb-49fd-a40d-623094c4b942 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742909543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3742909543 |
| Directory | /workspace/25.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_smoke.2884932352 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4088516884 ps |
| CPU time | 14.93 seconds |
| Started | May 26 03:09:48 PM PDT 24 |
| Finished | May 26 03:10:04 PM PDT 24 |
| Peak memory | 202488 kb |
| Host | smart-1e4b52b9-ac8c-4780-ba34-41c036c34cb9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884932352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2884932352 |
| Directory | /workspace/25.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3384234862 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2794897892 ps |
| CPU time | 18.56 seconds |
| Started | May 26 03:10:00 PM PDT 24 |
| Finished | May 26 03:10:20 PM PDT 24 |
| Peak memory | 210712 kb |
| Host | smart-f7431bb6-3329-44c8-919b-45e801f4c910 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3384234862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3384234862 |
| Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1032931878 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 17727128319 ps |
| CPU time | 282.9 seconds |
| Started | May 26 03:09:53 PM PDT 24 |
| Finished | May 26 03:14:37 PM PDT 24 |
| Peak memory | 210736 kb |
| Host | smart-8f2f4fad-6503-428c-987a-eb362034ddaa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032931878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.1032931878 |
| Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.4100785587 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 704176821 ps |
| CPU time | 8.12 seconds |
| Started | May 26 03:09:57 PM PDT 24 |
| Finished | May 26 03:10:05 PM PDT 24 |
| Peak memory | 218772 kb |
| Host | smart-2f38e72a-47ed-4eff-9bfa-02ed0c808e30 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100785587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.4100785587 |
| Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.3151077698 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 57042811 ps |
| CPU time | 0.64 seconds |
| Started | May 26 03:10:20 PM PDT 24 |
| Finished | May 26 03:10:22 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-c239b19f-9b40-4ebf-b303-608f4610466f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151077698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.3151077698 |
| Directory | /workspace/26.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_bijection.694843739 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 31454855345 ps |
| CPU time | 1068.94 seconds |
| Started | May 26 03:10:07 PM PDT 24 |
| Finished | May 26 03:27:57 PM PDT 24 |
| Peak memory | 210672 kb |
| Host | smart-fd9260af-d529-4e04-b5a1-b0e5ae4c28c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694843739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 694843739 |
| Directory | /workspace/26.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_executable.2804344917 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 14300005475 ps |
| CPU time | 423.71 seconds |
| Started | May 26 03:10:15 PM PDT 24 |
| Finished | May 26 03:17:19 PM PDT 24 |
| Peak memory | 367140 kb |
| Host | smart-b81ef2d6-c529-4664-b2ef-2782dd1a4913 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804344917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.2804344917 |
| Directory | /workspace/26.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.2337891999 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 68463798735 ps |
| CPU time | 122.15 seconds |
| Started | May 26 03:10:17 PM PDT 24 |
| Finished | May 26 03:12:19 PM PDT 24 |
| Peak memory | 202480 kb |
| Host | smart-e097a6bf-e86e-4035-8b8c-49c2c4588fb6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337891999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.2337891999 |
| Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.993722327 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 789941381 ps |
| CPU time | 136.59 seconds |
| Started | May 26 03:10:07 PM PDT 24 |
| Finished | May 26 03:12:24 PM PDT 24 |
| Peak memory | 356772 kb |
| Host | smart-713e4179-8002-4781-943b-525606e1ecbd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993722327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.sram_ctrl_max_throughput.993722327 |
| Directory | /workspace/26.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.7498333 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 14968176911 ps |
| CPU time | 179.61 seconds |
| Started | May 26 03:10:15 PM PDT 24 |
| Finished | May 26 03:13:15 PM PDT 24 |
| Peak memory | 215936 kb |
| Host | smart-57919da9-2d14-4ad3-8862-f8cc6dfd9507 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7498333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s ram_ctrl_mem_partial_access.7498333 |
| Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.3698092262 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 14181371138 ps |
| CPU time | 156.57 seconds |
| Started | May 26 03:10:19 PM PDT 24 |
| Finished | May 26 03:12:57 PM PDT 24 |
| Peak memory | 210556 kb |
| Host | smart-d399fba4-76d3-4eae-838f-26cbcd8b0043 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698092262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.3698092262 |
| Directory | /workspace/26.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.3951593408 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 55092819317 ps |
| CPU time | 989.75 seconds |
| Started | May 26 03:10:09 PM PDT 24 |
| Finished | May 26 03:26:39 PM PDT 24 |
| Peak memory | 379416 kb |
| Host | smart-6eb5e0b9-e819-45d5-8f8f-1e4d191d749a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951593408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.3951593408 |
| Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.2204196454 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 884728072 ps |
| CPU time | 44.63 seconds |
| Started | May 26 03:10:08 PM PDT 24 |
| Finished | May 26 03:10:54 PM PDT 24 |
| Peak memory | 286328 kb |
| Host | smart-d43eb18c-0f31-4f51-a597-49d13d0acd4b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204196454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.2204196454 |
| Directory | /workspace/26.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.2649716927 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 360006088 ps |
| CPU time | 3.19 seconds |
| Started | May 26 03:10:19 PM PDT 24 |
| Finished | May 26 03:10:24 PM PDT 24 |
| Peak memory | 202544 kb |
| Host | smart-767983cb-af12-4af1-b6e8-52c8011aa90d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649716927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2649716927 |
| Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_regwen.2868073520 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 62005067944 ps |
| CPU time | 840.7 seconds |
| Started | May 26 03:10:15 PM PDT 24 |
| Finished | May 26 03:24:16 PM PDT 24 |
| Peak memory | 378376 kb |
| Host | smart-61c95f86-538f-4fad-a34b-a4efcc9fe493 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868073520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2868073520 |
| Directory | /workspace/26.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_smoke.185607331 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2084234974 ps |
| CPU time | 20.27 seconds |
| Started | May 26 03:10:08 PM PDT 24 |
| Finished | May 26 03:10:28 PM PDT 24 |
| Peak memory | 210632 kb |
| Host | smart-cab96935-1368-4769-b35e-6ccdd5862a77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185607331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.185607331 |
| Directory | /workspace/26.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.811000610 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 20048352644 ps |
| CPU time | 310.8 seconds |
| Started | May 26 03:10:08 PM PDT 24 |
| Finished | May 26 03:15:19 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-5c2b455e-7c7c-4361-83ef-03bcb4cb9937 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811000610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_stress_pipeline.811000610 |
| Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2629941117 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3601989420 ps |
| CPU time | 75.82 seconds |
| Started | May 26 03:10:14 PM PDT 24 |
| Finished | May 26 03:11:30 PM PDT 24 |
| Peak memory | 333680 kb |
| Host | smart-47dcb9c7-99ed-4812-9060-b4c625352cd3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629941117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2629941117 |
| Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.3064691443 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 10818658 ps |
| CPU time | 0.65 seconds |
| Started | May 26 03:10:37 PM PDT 24 |
| Finished | May 26 03:10:38 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-366ef96d-3d94-410c-9899-7077548aae65 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064691443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3064691443 |
| Directory | /workspace/27.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_bijection.2824285891 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 300153270273 ps |
| CPU time | 1453.9 seconds |
| Started | May 26 03:10:21 PM PDT 24 |
| Finished | May 26 03:34:36 PM PDT 24 |
| Peak memory | 210588 kb |
| Host | smart-5d9a7af4-525f-4755-b7b6-52d669941ce2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824285891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .2824285891 |
| Directory | /workspace/27.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_executable.875581040 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 19060731532 ps |
| CPU time | 1007.65 seconds |
| Started | May 26 03:10:30 PM PDT 24 |
| Finished | May 26 03:27:19 PM PDT 24 |
| Peak memory | 375360 kb |
| Host | smart-43637a6c-786c-437b-afec-419ccd1946a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875581040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executabl e.875581040 |
| Directory | /workspace/27.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.2242019293 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 8329713331 ps |
| CPU time | 53.18 seconds |
| Started | May 26 03:10:28 PM PDT 24 |
| Finished | May 26 03:11:22 PM PDT 24 |
| Peak memory | 210708 kb |
| Host | smart-a0d90d24-1ee5-4686-85f8-0749d24e7da8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242019293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.2242019293 |
| Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.3279818399 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2888350379 ps |
| CPU time | 6.31 seconds |
| Started | May 26 03:10:28 PM PDT 24 |
| Finished | May 26 03:10:35 PM PDT 24 |
| Peak memory | 202320 kb |
| Host | smart-c4701bbd-cf6c-4297-924d-57eb83eacf1f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279818399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.3279818399 |
| Directory | /workspace/27.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2116365667 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 21605932728 ps |
| CPU time | 189.75 seconds |
| Started | May 26 03:10:37 PM PDT 24 |
| Finished | May 26 03:13:48 PM PDT 24 |
| Peak memory | 215096 kb |
| Host | smart-1cdcc42c-33db-4cb8-a6ee-ec545a80a31b |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116365667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.2116365667 |
| Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.4072950246 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 23895159250 ps |
| CPU time | 174.49 seconds |
| Started | May 26 03:10:36 PM PDT 24 |
| Finished | May 26 03:13:31 PM PDT 24 |
| Peak memory | 210684 kb |
| Host | smart-9f425d49-7c02-4347-8cf5-77789cd04d17 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072950246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.4072950246 |
| Directory | /workspace/27.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.3998788349 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 14625896151 ps |
| CPU time | 864.93 seconds |
| Started | May 26 03:10:21 PM PDT 24 |
| Finished | May 26 03:24:47 PM PDT 24 |
| Peak memory | 376324 kb |
| Host | smart-1df5a4be-7dc9-4f3d-b0a2-c395851f0994 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998788349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.3998788349 |
| Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.3286012927 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1024346124 ps |
| CPU time | 13.51 seconds |
| Started | May 26 03:10:22 PM PDT 24 |
| Finished | May 26 03:10:36 PM PDT 24 |
| Peak memory | 202440 kb |
| Host | smart-68df3e65-7bfe-456a-849e-2b874970da48 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286012927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.3286012927 |
| Directory | /workspace/27.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1579392237 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 47132829432 ps |
| CPU time | 299.27 seconds |
| Started | May 26 03:10:30 PM PDT 24 |
| Finished | May 26 03:15:30 PM PDT 24 |
| Peak memory | 210676 kb |
| Host | smart-4f9764fd-122a-4681-ae41-f1fb67cda50d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579392237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.1579392237 |
| Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.2840248740 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 356827604 ps |
| CPU time | 3.24 seconds |
| Started | May 26 03:10:36 PM PDT 24 |
| Finished | May 26 03:10:40 PM PDT 24 |
| Peak memory | 202540 kb |
| Host | smart-fdc1fa24-94f8-4a44-b399-6b41062f86be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840248740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2840248740 |
| Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_regwen.1895739748 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 7610226645 ps |
| CPU time | 178.56 seconds |
| Started | May 26 03:10:30 PM PDT 24 |
| Finished | May 26 03:13:29 PM PDT 24 |
| Peak memory | 342528 kb |
| Host | smart-7931b21c-92d6-4c47-a743-60a9c0b8e359 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895739748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1895739748 |
| Directory | /workspace/27.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_smoke.3644961967 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 4293422223 ps |
| CPU time | 22.65 seconds |
| Started | May 26 03:10:22 PM PDT 24 |
| Finished | May 26 03:10:45 PM PDT 24 |
| Peak memory | 210676 kb |
| Host | smart-236f344a-f65e-4f4e-80d0-6a63f76dcd40 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644961967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3644961967 |
| Directory | /workspace/27.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3311426887 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 504817586 ps |
| CPU time | 18.21 seconds |
| Started | May 26 03:10:38 PM PDT 24 |
| Finished | May 26 03:10:56 PM PDT 24 |
| Peak memory | 210720 kb |
| Host | smart-5f141140-ff99-4e25-953d-55c5ad6a29dd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3311426887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3311426887 |
| Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.4249820940 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 30944264795 ps |
| CPU time | 346.63 seconds |
| Started | May 26 03:10:24 PM PDT 24 |
| Finished | May 26 03:16:11 PM PDT 24 |
| Peak memory | 202472 kb |
| Host | smart-3747f91d-c230-4c9a-ae99-b8b5969fdc59 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249820940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.4249820940 |
| Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1173576789 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 931680786 ps |
| CPU time | 73.65 seconds |
| Started | May 26 03:10:29 PM PDT 24 |
| Finished | May 26 03:11:43 PM PDT 24 |
| Peak memory | 329368 kb |
| Host | smart-6d2eb97d-0196-4259-a5fc-5814fe40480e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173576789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.1173576789 |
| Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.1827811336 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 15238141 ps |
| CPU time | 0.68 seconds |
| Started | May 26 03:10:54 PM PDT 24 |
| Finished | May 26 03:10:55 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-bb0ef913-c38c-4182-93bf-6556728d58a4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827811336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.1827811336 |
| Directory | /workspace/28.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_bijection.4089675806 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 35513087691 ps |
| CPU time | 2437.34 seconds |
| Started | May 26 03:10:47 PM PDT 24 |
| Finished | May 26 03:51:25 PM PDT 24 |
| Peak memory | 210692 kb |
| Host | smart-5df2ab69-5761-44d0-b9e8-62dee519ef6b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089675806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .4089675806 |
| Directory | /workspace/28.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_executable.1339452224 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 7276408320 ps |
| CPU time | 589.21 seconds |
| Started | May 26 03:10:55 PM PDT 24 |
| Finished | May 26 03:20:45 PM PDT 24 |
| Peak memory | 378324 kb |
| Host | smart-55b77407-6227-48be-8a73-1f7b2a92bba6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339452224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.1339452224 |
| Directory | /workspace/28.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.3874204678 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 20262888068 ps |
| CPU time | 67.32 seconds |
| Started | May 26 03:10:48 PM PDT 24 |
| Finished | May 26 03:11:55 PM PDT 24 |
| Peak memory | 210732 kb |
| Host | smart-0572c7f4-cb8c-43e2-8c39-2d05971c35c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874204678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.3874204678 |
| Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.3692785064 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2797560698 ps |
| CPU time | 25.81 seconds |
| Started | May 26 03:10:49 PM PDT 24 |
| Finished | May 26 03:11:15 PM PDT 24 |
| Peak memory | 258840 kb |
| Host | smart-1556157f-6180-438e-b2b1-6d0232507962 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692785064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.3692785064 |
| Directory | /workspace/28.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2057399343 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2008294355 ps |
| CPU time | 63.33 seconds |
| Started | May 26 03:10:54 PM PDT 24 |
| Finished | May 26 03:11:58 PM PDT 24 |
| Peak memory | 212320 kb |
| Host | smart-a9b0c915-e2bb-42e0-8b9f-0bf6b3503420 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057399343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.2057399343 |
| Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.560297935 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 18723082582 ps |
| CPU time | 328.27 seconds |
| Started | May 26 03:10:54 PM PDT 24 |
| Finished | May 26 03:16:23 PM PDT 24 |
| Peak memory | 202380 kb |
| Host | smart-c330c470-3dc8-4d12-8265-b76d0cb9a891 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560297935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl _mem_walk.560297935 |
| Directory | /workspace/28.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.1067876002 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 16116825205 ps |
| CPU time | 1291.07 seconds |
| Started | May 26 03:10:49 PM PDT 24 |
| Finished | May 26 03:32:21 PM PDT 24 |
| Peak memory | 377304 kb |
| Host | smart-463ef3b5-27cd-4dfc-a018-373ba2046b2f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067876002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.1067876002 |
| Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.1188527534 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3437271107 ps |
| CPU time | 56.01 seconds |
| Started | May 26 03:10:46 PM PDT 24 |
| Finished | May 26 03:11:43 PM PDT 24 |
| Peak memory | 290984 kb |
| Host | smart-89abe46c-b684-4614-8017-a5788fbb8ab4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188527534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.1188527534 |
| Directory | /workspace/28.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1912688525 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 23417705292 ps |
| CPU time | 298.98 seconds |
| Started | May 26 03:10:48 PM PDT 24 |
| Finished | May 26 03:15:48 PM PDT 24 |
| Peak memory | 210644 kb |
| Host | smart-3af34356-9227-4b40-a3c9-aadb2a5fb755 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912688525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.1912688525 |
| Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.3754824243 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1403691544 ps |
| CPU time | 3.61 seconds |
| Started | May 26 03:10:53 PM PDT 24 |
| Finished | May 26 03:10:57 PM PDT 24 |
| Peak memory | 202484 kb |
| Host | smart-2d497ae2-55ca-47b3-9edc-e00a56b0857d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754824243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3754824243 |
| Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_regwen.2673977121 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 24880789688 ps |
| CPU time | 273 seconds |
| Started | May 26 03:10:55 PM PDT 24 |
| Finished | May 26 03:15:29 PM PDT 24 |
| Peak memory | 345872 kb |
| Host | smart-0510303a-0b78-49a0-88e3-2e6d7b8f2cce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673977121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2673977121 |
| Directory | /workspace/28.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_smoke.939324207 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 9949718309 ps |
| CPU time | 133.19 seconds |
| Started | May 26 03:10:49 PM PDT 24 |
| Finished | May 26 03:13:02 PM PDT 24 |
| Peak memory | 373236 kb |
| Host | smart-99bb9b34-89c8-4300-a546-3b68bc3b0535 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939324207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.939324207 |
| Directory | /workspace/28.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.759837083 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 34936967527 ps |
| CPU time | 221.21 seconds |
| Started | May 26 03:10:45 PM PDT 24 |
| Finished | May 26 03:14:27 PM PDT 24 |
| Peak memory | 210700 kb |
| Host | smart-f0f3ea72-6600-44c0-bdf5-a328a1e54a50 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759837083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .sram_ctrl_stress_pipeline.759837083 |
| Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4146251591 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 725754094 ps |
| CPU time | 6.05 seconds |
| Started | May 26 03:10:46 PM PDT 24 |
| Finished | May 26 03:10:53 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-13e25971-44be-426a-9de6-83049b64d322 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146251591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.4146251591 |
| Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.1788310022 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 21346111 ps |
| CPU time | 0.67 seconds |
| Started | May 26 03:11:17 PM PDT 24 |
| Finished | May 26 03:11:19 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-ef25c015-044e-41a0-a007-47f4dc34cf16 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788310022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1788310022 |
| Directory | /workspace/29.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_bijection.1940939633 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 31814115120 ps |
| CPU time | 2139.07 seconds |
| Started | May 26 03:11:02 PM PDT 24 |
| Finished | May 26 03:46:42 PM PDT 24 |
| Peak memory | 210652 kb |
| Host | smart-bb4257d9-8d56-4fdb-88ea-03ab74b848be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940939633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .1940939633 |
| Directory | /workspace/29.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_executable.1681870687 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 15348898667 ps |
| CPU time | 662.13 seconds |
| Started | May 26 03:11:10 PM PDT 24 |
| Finished | May 26 03:22:13 PM PDT 24 |
| Peak memory | 373208 kb |
| Host | smart-ea7e7426-db40-4c8d-96f0-e700800fe239 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681870687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.1681870687 |
| Directory | /workspace/29.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.868938695 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 19852914434 ps |
| CPU time | 57.8 seconds |
| Started | May 26 03:11:02 PM PDT 24 |
| Finished | May 26 03:12:01 PM PDT 24 |
| Peak memory | 202548 kb |
| Host | smart-204e56f0-628c-4a2d-83a9-0c47a4c58cb9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868938695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_esc alation.868938695 |
| Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.91182355 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1111966239 ps |
| CPU time | 171.33 seconds |
| Started | May 26 03:11:02 PM PDT 24 |
| Finished | May 26 03:13:55 PM PDT 24 |
| Peak memory | 370068 kb |
| Host | smart-5c88df5a-c4f1-415d-94f2-a814101feb47 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91182355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 29.sram_ctrl_max_throughput.91182355 |
| Directory | /workspace/29.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1774641556 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1708989164 ps |
| CPU time | 75.57 seconds |
| Started | May 26 03:11:09 PM PDT 24 |
| Finished | May 26 03:12:25 PM PDT 24 |
| Peak memory | 218616 kb |
| Host | smart-b46438d4-6300-45ff-8623-55c8b525b04c |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774641556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.1774641556 |
| Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.2844374198 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 14127361895 ps |
| CPU time | 314.77 seconds |
| Started | May 26 03:11:10 PM PDT 24 |
| Finished | May 26 03:16:26 PM PDT 24 |
| Peak memory | 210584 kb |
| Host | smart-c05fa3af-6d5b-4335-a950-2c66e9a9231e |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844374198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.2844374198 |
| Directory | /workspace/29.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.562850032 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 20520833578 ps |
| CPU time | 342.93 seconds |
| Started | May 26 03:11:03 PM PDT 24 |
| Finished | May 26 03:16:47 PM PDT 24 |
| Peak memory | 369192 kb |
| Host | smart-ddf54d11-e9e5-46e4-9267-38da9f658fae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562850032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multip le_keys.562850032 |
| Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.3376839909 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 885650749 ps |
| CPU time | 145.37 seconds |
| Started | May 26 03:11:04 PM PDT 24 |
| Finished | May 26 03:13:30 PM PDT 24 |
| Peak memory | 354824 kb |
| Host | smart-d7cb0cf2-64e6-45d0-a502-740bef251b62 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376839909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.3376839909 |
| Directory | /workspace/29.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1305107952 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 7082801774 ps |
| CPU time | 315.36 seconds |
| Started | May 26 03:11:02 PM PDT 24 |
| Finished | May 26 03:16:18 PM PDT 24 |
| Peak memory | 210748 kb |
| Host | smart-cc11c5d0-be88-4ada-b8b4-636560d92823 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305107952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.1305107952 |
| Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.1269058917 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 353643810 ps |
| CPU time | 3.16 seconds |
| Started | May 26 03:11:10 PM PDT 24 |
| Finished | May 26 03:11:13 PM PDT 24 |
| Peak memory | 202544 kb |
| Host | smart-2a2c1504-aacd-4212-93ec-52f0626f6d85 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269058917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1269058917 |
| Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_regwen.2664061467 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 27588600062 ps |
| CPU time | 1212.68 seconds |
| Started | May 26 03:11:08 PM PDT 24 |
| Finished | May 26 03:31:21 PM PDT 24 |
| Peak memory | 379396 kb |
| Host | smart-94e1f710-58c1-4fd1-81bb-c78c7ac4acc3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664061467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2664061467 |
| Directory | /workspace/29.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_smoke.414478037 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 863661456 ps |
| CPU time | 16.41 seconds |
| Started | May 26 03:11:01 PM PDT 24 |
| Finished | May 26 03:11:18 PM PDT 24 |
| Peak memory | 210608 kb |
| Host | smart-e68dea15-8801-4f74-9e08-1b3d004a5381 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414478037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.414478037 |
| Directory | /workspace/29.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3059801196 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 488065875 ps |
| CPU time | 14.76 seconds |
| Started | May 26 03:11:17 PM PDT 24 |
| Finished | May 26 03:11:32 PM PDT 24 |
| Peak memory | 210748 kb |
| Host | smart-87cf786d-d483-4310-aa96-0c56bf869741 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3059801196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3059801196 |
| Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3881169358 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 42828954232 ps |
| CPU time | 283.92 seconds |
| Started | May 26 03:11:02 PM PDT 24 |
| Finished | May 26 03:15:47 PM PDT 24 |
| Peak memory | 210644 kb |
| Host | smart-4071e927-eb13-4aaf-b033-cc9428f5a4e6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881169358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3881169358 |
| Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3832221594 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3971555708 ps |
| CPU time | 100.51 seconds |
| Started | May 26 03:11:01 PM PDT 24 |
| Finished | May 26 03:12:42 PM PDT 24 |
| Peak memory | 332328 kb |
| Host | smart-819060dc-db4c-44c3-b2e5-e3f973280671 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832221594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3832221594 |
| Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.3119253812 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 16055760 ps |
| CPU time | 0.69 seconds |
| Started | May 26 03:03:52 PM PDT 24 |
| Finished | May 26 03:03:53 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-5701bf14-d5d4-4b78-9506-8b3a4379ea68 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119253812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.3119253812 |
| Directory | /workspace/3.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_bijection.3409700630 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 28035529244 ps |
| CPU time | 873.9 seconds |
| Started | May 26 03:03:26 PM PDT 24 |
| Finished | May 26 03:18:01 PM PDT 24 |
| Peak memory | 210664 kb |
| Host | smart-61f2329f-3cb2-4e58-976a-a0012d413a39 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409700630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 3409700630 |
| Directory | /workspace/3.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_executable.2043318415 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3010064386 ps |
| CPU time | 291.38 seconds |
| Started | May 26 03:03:35 PM PDT 24 |
| Finished | May 26 03:08:27 PM PDT 24 |
| Peak memory | 328232 kb |
| Host | smart-93ad24b3-4732-4d84-8760-aeca78dabee0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043318415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.2043318415 |
| Directory | /workspace/3.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.2382048335 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2772245649 ps |
| CPU time | 19.89 seconds |
| Started | May 26 03:03:26 PM PDT 24 |
| Finished | May 26 03:03:47 PM PDT 24 |
| Peak memory | 202492 kb |
| Host | smart-42a48291-f8b7-41f8-ad51-c9e098e147e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382048335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.2382048335 |
| Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.1073779405 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 700304555 ps |
| CPU time | 10.75 seconds |
| Started | May 26 03:03:27 PM PDT 24 |
| Finished | May 26 03:03:39 PM PDT 24 |
| Peak memory | 235096 kb |
| Host | smart-151cc6fd-eabc-4f10-8839-4d3851fd6d77 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073779405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.1073779405 |
| Directory | /workspace/3.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.324567289 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2422540344 ps |
| CPU time | 78.5 seconds |
| Started | May 26 03:03:43 PM PDT 24 |
| Finished | May 26 03:05:02 PM PDT 24 |
| Peak memory | 212896 kb |
| Host | smart-bea7b3b4-e5d6-4ccf-ae49-f7394a749cbe |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324567289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_mem_partial_access.324567289 |
| Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.292509652 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 106398181373 ps |
| CPU time | 351.71 seconds |
| Started | May 26 03:03:42 PM PDT 24 |
| Finished | May 26 03:09:34 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-9514a457-6ed3-4bcb-8099-c64011dd8612 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292509652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ mem_walk.292509652 |
| Directory | /workspace/3.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.2130569739 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 56566013682 ps |
| CPU time | 1566.72 seconds |
| Started | May 26 03:03:28 PM PDT 24 |
| Finished | May 26 03:29:36 PM PDT 24 |
| Peak memory | 379444 kb |
| Host | smart-2ec870df-fe02-4262-8f86-c4f859378e8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130569739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.2130569739 |
| Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.1153766561 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 478062034 ps |
| CPU time | 10.42 seconds |
| Started | May 26 03:03:28 PM PDT 24 |
| Finished | May 26 03:03:40 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-eaf8ba77-56ca-434d-bf64-fe2682e5e902 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153766561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.1153766561 |
| Directory | /workspace/3.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.149162369 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 14017508951 ps |
| CPU time | 288.5 seconds |
| Started | May 26 03:03:26 PM PDT 24 |
| Finished | May 26 03:08:15 PM PDT 24 |
| Peak memory | 210688 kb |
| Host | smart-80c980fe-94da-4009-aa95-4fe0fed25a1f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149162369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 3.sram_ctrl_partial_access_b2b.149162369 |
| Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.1412338505 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 355380790 ps |
| CPU time | 3.22 seconds |
| Started | May 26 03:03:42 PM PDT 24 |
| Finished | May 26 03:03:46 PM PDT 24 |
| Peak memory | 202544 kb |
| Host | smart-c751deb6-880a-4732-b425-8429fa1751d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412338505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1412338505 |
| Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_regwen.2118647104 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5480137229 ps |
| CPU time | 487.03 seconds |
| Started | May 26 03:03:34 PM PDT 24 |
| Finished | May 26 03:11:42 PM PDT 24 |
| Peak memory | 370232 kb |
| Host | smart-1d6386ba-eae8-4ab6-9fc4-3f5d96472f10 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118647104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2118647104 |
| Directory | /workspace/3.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.4289666740 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1495753383 ps |
| CPU time | 4.29 seconds |
| Started | May 26 03:03:51 PM PDT 24 |
| Finished | May 26 03:03:57 PM PDT 24 |
| Peak memory | 221988 kb |
| Host | smart-b6f562eb-aa25-4981-baa3-13bb675021aa |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289666740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.4289666740 |
| Directory | /workspace/3.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_smoke.1783277820 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2697459849 ps |
| CPU time | 8.75 seconds |
| Started | May 26 03:03:26 PM PDT 24 |
| Finished | May 26 03:03:36 PM PDT 24 |
| Peak memory | 210660 kb |
| Host | smart-26e030f5-3fe7-48ed-bc91-b3344e75d28d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783277820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1783277820 |
| Directory | /workspace/3.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2079399018 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 16259045814 ps |
| CPU time | 385.99 seconds |
| Started | May 26 03:03:29 PM PDT 24 |
| Finished | May 26 03:09:56 PM PDT 24 |
| Peak memory | 202532 kb |
| Host | smart-89337536-45e4-487b-b1b2-74ae6843a71f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079399018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.2079399018 |
| Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.181052359 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 8809846351 ps |
| CPU time | 19.96 seconds |
| Started | May 26 03:03:26 PM PDT 24 |
| Finished | May 26 03:03:47 PM PDT 24 |
| Peak memory | 257500 kb |
| Host | smart-240310e0-3e2c-474f-ad24-8728f3319a39 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181052359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.181052359 |
| Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.598716910 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 20877984 ps |
| CPU time | 0.69 seconds |
| Started | May 26 03:11:33 PM PDT 24 |
| Finished | May 26 03:11:34 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-c9ed3de8-1637-4f24-90d5-0456e2b1e460 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598716910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.598716910 |
| Directory | /workspace/30.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_bijection.29584457 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 599215684967 ps |
| CPU time | 3450.84 seconds |
| Started | May 26 03:11:17 PM PDT 24 |
| Finished | May 26 04:08:49 PM PDT 24 |
| Peak memory | 203244 kb |
| Host | smart-34472dcf-12c4-4ee5-bc9e-78939608ee80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29584457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.29584457 |
| Directory | /workspace/30.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_executable.2605091052 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 7671472097 ps |
| CPU time | 772.75 seconds |
| Started | May 26 03:11:26 PM PDT 24 |
| Finished | May 26 03:24:20 PM PDT 24 |
| Peak memory | 365064 kb |
| Host | smart-caa321f0-0187-496d-bd40-00379c1a94a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605091052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.2605091052 |
| Directory | /workspace/30.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.1963880424 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 12668343842 ps |
| CPU time | 69.61 seconds |
| Started | May 26 03:11:26 PM PDT 24 |
| Finished | May 26 03:12:36 PM PDT 24 |
| Peak memory | 210624 kb |
| Host | smart-58503f00-1de2-426a-96ce-788a2a7b52fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963880424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.1963880424 |
| Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.154008391 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1500215760 ps |
| CPU time | 93.47 seconds |
| Started | May 26 03:11:17 PM PDT 24 |
| Finished | May 26 03:12:51 PM PDT 24 |
| Peak memory | 347524 kb |
| Host | smart-dcca95b7-848a-42a3-a45d-4ab4d5d3d94e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154008391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.sram_ctrl_max_throughput.154008391 |
| Directory | /workspace/30.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.326087713 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1634711610 ps |
| CPU time | 122.21 seconds |
| Started | May 26 03:11:27 PM PDT 24 |
| Finished | May 26 03:13:30 PM PDT 24 |
| Peak memory | 215396 kb |
| Host | smart-7de32098-38ec-450a-a3c1-43ca9f28108d |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326087713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .sram_ctrl_mem_partial_access.326087713 |
| Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.2279305366 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3943229350 ps |
| CPU time | 240.82 seconds |
| Started | May 26 03:11:25 PM PDT 24 |
| Finished | May 26 03:15:26 PM PDT 24 |
| Peak memory | 210604 kb |
| Host | smart-4174c813-25ad-465c-9350-92673d2dc406 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279305366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.2279305366 |
| Directory | /workspace/30.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.1307313861 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 100293305004 ps |
| CPU time | 918.63 seconds |
| Started | May 26 03:11:16 PM PDT 24 |
| Finished | May 26 03:26:35 PM PDT 24 |
| Peak memory | 371248 kb |
| Host | smart-0f751122-6eb6-46ca-9540-89c10431d6f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307313861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1307313861 |
| Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.1773042047 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1369006644 ps |
| CPU time | 23.13 seconds |
| Started | May 26 03:11:17 PM PDT 24 |
| Finished | May 26 03:11:40 PM PDT 24 |
| Peak memory | 210636 kb |
| Host | smart-71605ab1-4aa1-4234-acf1-10dc81d0cdd3 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773042047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.1773042047 |
| Directory | /workspace/30.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1477278351 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 227798413803 ps |
| CPU time | 413.57 seconds |
| Started | May 26 03:11:17 PM PDT 24 |
| Finished | May 26 03:18:11 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-27a41ca6-d829-4d58-8623-3b0640027b61 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477278351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.1477278351 |
| Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.1361582376 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 1342803862 ps |
| CPU time | 3.49 seconds |
| Started | May 26 03:11:26 PM PDT 24 |
| Finished | May 26 03:11:29 PM PDT 24 |
| Peak memory | 202540 kb |
| Host | smart-cc181d49-fc0e-461d-8375-95bb10712ff9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361582376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1361582376 |
| Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_regwen.3280719727 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2213619152 ps |
| CPU time | 512.29 seconds |
| Started | May 26 03:11:28 PM PDT 24 |
| Finished | May 26 03:20:01 PM PDT 24 |
| Peak memory | 368756 kb |
| Host | smart-88021d7a-9922-4ebf-9fa3-a7d09de5dfd5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280719727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3280719727 |
| Directory | /workspace/30.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_smoke.231180086 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2353891528 ps |
| CPU time | 16.19 seconds |
| Started | May 26 03:11:16 PM PDT 24 |
| Finished | May 26 03:11:33 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-a161e8b3-4d28-45a9-82da-6b2c217c5f93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231180086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.231180086 |
| Directory | /workspace/30.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2625191568 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 31106894809 ps |
| CPU time | 259.6 seconds |
| Started | May 26 03:11:16 PM PDT 24 |
| Finished | May 26 03:15:37 PM PDT 24 |
| Peak memory | 202528 kb |
| Host | smart-27728ae2-2740-4e25-a1a5-1337dd9306e7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625191568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.2625191568 |
| Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1994410206 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3357248773 ps |
| CPU time | 7.89 seconds |
| Started | May 26 03:11:26 PM PDT 24 |
| Finished | May 26 03:11:35 PM PDT 24 |
| Peak memory | 213644 kb |
| Host | smart-1b84122f-3634-4ce8-b57a-256579ab6d83 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994410206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1994410206 |
| Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.1560564109 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 13419142 ps |
| CPU time | 0.68 seconds |
| Started | May 26 03:11:53 PM PDT 24 |
| Finished | May 26 03:11:54 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-d601eb51-d9ef-47d7-bded-1d5db15a06eb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560564109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.1560564109 |
| Directory | /workspace/31.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_bijection.333956396 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 396517218707 ps |
| CPU time | 2244.42 seconds |
| Started | May 26 03:11:37 PM PDT 24 |
| Finished | May 26 03:49:02 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-86b20937-5c42-41ef-80db-8fcc1d2ef51a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333956396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection. 333956396 |
| Directory | /workspace/31.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_executable.4163018610 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 19942806481 ps |
| CPU time | 1326.89 seconds |
| Started | May 26 03:11:40 PM PDT 24 |
| Finished | May 26 03:33:47 PM PDT 24 |
| Peak memory | 378436 kb |
| Host | smart-cf5c636d-c376-4e39-a9eb-77b39ef367d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163018610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.4163018610 |
| Directory | /workspace/31.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.591318731 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11577132131 ps |
| CPU time | 73.19 seconds |
| Started | May 26 03:11:34 PM PDT 24 |
| Finished | May 26 03:12:48 PM PDT 24 |
| Peak memory | 202564 kb |
| Host | smart-26c35ee7-70e1-4488-99da-37b7159157bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591318731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_esc alation.591318731 |
| Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.60927780 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1808413055 ps |
| CPU time | 135.68 seconds |
| Started | May 26 03:11:36 PM PDT 24 |
| Finished | May 26 03:13:52 PM PDT 24 |
| Peak memory | 359836 kb |
| Host | smart-ecef6ab5-8b77-415f-841d-71ea7bb407f7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60927780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 31.sram_ctrl_max_throughput.60927780 |
| Directory | /workspace/31.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2311238398 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5530650182 ps |
| CPU time | 74.78 seconds |
| Started | May 26 03:11:53 PM PDT 24 |
| Finished | May 26 03:13:08 PM PDT 24 |
| Peak memory | 212864 kb |
| Host | smart-eb0573fa-fa3f-4414-ad6a-95b11efc6afd |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311238398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.2311238398 |
| Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.1690310244 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 98486207834 ps |
| CPU time | 362.34 seconds |
| Started | May 26 03:11:49 PM PDT 24 |
| Finished | May 26 03:17:52 PM PDT 24 |
| Peak memory | 210592 kb |
| Host | smart-ea04b921-cd6b-4eb1-a986-60b01284906f |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690310244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.1690310244 |
| Directory | /workspace/31.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.3753836051 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 65895554802 ps |
| CPU time | 2443.21 seconds |
| Started | May 26 03:11:34 PM PDT 24 |
| Finished | May 26 03:52:18 PM PDT 24 |
| Peak memory | 379320 kb |
| Host | smart-9f54ec15-8b8b-4df7-8e7f-b9c9a0817af0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753836051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.3753836051 |
| Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.3520332362 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1727458044 ps |
| CPU time | 110.52 seconds |
| Started | May 26 03:11:32 PM PDT 24 |
| Finished | May 26 03:13:23 PM PDT 24 |
| Peak memory | 336332 kb |
| Host | smart-b656255e-7580-40d5-8211-ac70ef92f04b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520332362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.3520332362 |
| Directory | /workspace/31.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2910665555 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 71855636526 ps |
| CPU time | 463.28 seconds |
| Started | May 26 03:11:35 PM PDT 24 |
| Finished | May 26 03:19:18 PM PDT 24 |
| Peak memory | 210676 kb |
| Host | smart-544c2fe1-d227-49fc-8e6d-15187691c669 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910665555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2910665555 |
| Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.1013396928 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 362718962 ps |
| CPU time | 3.25 seconds |
| Started | May 26 03:11:49 PM PDT 24 |
| Finished | May 26 03:11:53 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-87c6275f-247e-4775-95ba-6ef25e794dcf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013396928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1013396928 |
| Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_regwen.2046641148 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5399235429 ps |
| CPU time | 355.87 seconds |
| Started | May 26 03:11:41 PM PDT 24 |
| Finished | May 26 03:17:37 PM PDT 24 |
| Peak memory | 374168 kb |
| Host | smart-4b991b14-7de3-4464-ad34-0f9e00911aaf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046641148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2046641148 |
| Directory | /workspace/31.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_smoke.201680127 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 674487928 ps |
| CPU time | 10.77 seconds |
| Started | May 26 03:11:33 PM PDT 24 |
| Finished | May 26 03:11:44 PM PDT 24 |
| Peak memory | 210604 kb |
| Host | smart-b21d61e9-289e-444d-bce9-39fb98493653 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201680127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.201680127 |
| Directory | /workspace/31.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.893913284 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 9437996129 ps |
| CPU time | 475.12 seconds |
| Started | May 26 03:11:34 PM PDT 24 |
| Finished | May 26 03:19:29 PM PDT 24 |
| Peak memory | 202444 kb |
| Host | smart-a2cbf462-9a13-4246-9436-32e93df8d6e2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893913284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .sram_ctrl_stress_pipeline.893913284 |
| Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2498852323 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 10906935369 ps |
| CPU time | 129.98 seconds |
| Started | May 26 03:11:34 PM PDT 24 |
| Finished | May 26 03:13:44 PM PDT 24 |
| Peak memory | 346872 kb |
| Host | smart-1d781f92-f025-421d-ba31-af46244ae2a9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498852323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2498852323 |
| Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.3971218686 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 16460361 ps |
| CPU time | 0.69 seconds |
| Started | May 26 03:12:12 PM PDT 24 |
| Finished | May 26 03:12:13 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-be911ebf-6024-458e-863d-0558ae8d3afa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971218686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.3971218686 |
| Directory | /workspace/32.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_bijection.1715545464 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 30741569049 ps |
| CPU time | 1959.48 seconds |
| Started | May 26 03:11:47 PM PDT 24 |
| Finished | May 26 03:44:28 PM PDT 24 |
| Peak memory | 210684 kb |
| Host | smart-0722feeb-7f7c-4da6-86b0-b7ffaf268e99 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715545464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .1715545464 |
| Directory | /workspace/32.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_executable.3731650896 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 7886844773 ps |
| CPU time | 1272.33 seconds |
| Started | May 26 03:11:55 PM PDT 24 |
| Finished | May 26 03:33:08 PM PDT 24 |
| Peak memory | 379400 kb |
| Host | smart-559a480f-80d8-481c-9078-384da0a711a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731650896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.3731650896 |
| Directory | /workspace/32.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.1161436171 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 23514653375 ps |
| CPU time | 38.69 seconds |
| Started | May 26 03:11:55 PM PDT 24 |
| Finished | May 26 03:12:34 PM PDT 24 |
| Peak memory | 210672 kb |
| Host | smart-2f142d70-6116-4e31-bb64-05c2e9d3a760 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161436171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.1161436171 |
| Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.1098379982 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2684496994 ps |
| CPU time | 53.71 seconds |
| Started | May 26 03:11:57 PM PDT 24 |
| Finished | May 26 03:12:51 PM PDT 24 |
| Peak memory | 300600 kb |
| Host | smart-893dc80a-83ff-4bdd-86f2-997344e593f5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098379982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.1098379982 |
| Directory | /workspace/32.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.724653624 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 8784734409 ps |
| CPU time | 118.93 seconds |
| Started | May 26 03:12:02 PM PDT 24 |
| Finished | May 26 03:14:02 PM PDT 24 |
| Peak memory | 216036 kb |
| Host | smart-e51658d0-3aed-4dcc-97ec-d0b0625df2c3 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724653624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .sram_ctrl_mem_partial_access.724653624 |
| Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.3138729554 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 7305617758 ps |
| CPU time | 161.3 seconds |
| Started | May 26 03:12:03 PM PDT 24 |
| Finished | May 26 03:14:44 PM PDT 24 |
| Peak memory | 210652 kb |
| Host | smart-40322c46-90c9-4709-bbec-ab243a75c2ab |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138729554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.3138729554 |
| Directory | /workspace/32.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.1608136698 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 15483162147 ps |
| CPU time | 578.18 seconds |
| Started | May 26 03:11:49 PM PDT 24 |
| Finished | May 26 03:21:28 PM PDT 24 |
| Peak memory | 373184 kb |
| Host | smart-bbb98c38-47e6-454a-b522-54fff67cac38 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608136698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.1608136698 |
| Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.1100962518 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2827527207 ps |
| CPU time | 6.7 seconds |
| Started | May 26 03:11:57 PM PDT 24 |
| Finished | May 26 03:12:04 PM PDT 24 |
| Peak memory | 210728 kb |
| Host | smart-8aa48ff7-bf62-4dc0-99f7-6647591b4431 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100962518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.1100962518 |
| Directory | /workspace/32.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2430015713 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 34378567965 ps |
| CPU time | 426.93 seconds |
| Started | May 26 03:11:57 PM PDT 24 |
| Finished | May 26 03:19:04 PM PDT 24 |
| Peak memory | 202672 kb |
| Host | smart-ebaeb8ee-6a9b-47d4-857f-d7ba544c018c |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430015713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.2430015713 |
| Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.1399905102 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 356965340 ps |
| CPU time | 3.52 seconds |
| Started | May 26 03:11:58 PM PDT 24 |
| Finished | May 26 03:12:02 PM PDT 24 |
| Peak memory | 202676 kb |
| Host | smart-0abb91f6-dba0-478e-9a47-3bed6ad2a57b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399905102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1399905102 |
| Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_regwen.1828522974 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 70574199280 ps |
| CPU time | 1570.49 seconds |
| Started | May 26 03:11:58 PM PDT 24 |
| Finished | May 26 03:38:09 PM PDT 24 |
| Peak memory | 379524 kb |
| Host | smart-3f652f4c-b362-431c-94c0-4915d0d05ee1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828522974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1828522974 |
| Directory | /workspace/32.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_smoke.1964004879 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 3844970263 ps |
| CPU time | 112.91 seconds |
| Started | May 26 03:11:48 PM PDT 24 |
| Finished | May 26 03:13:41 PM PDT 24 |
| Peak memory | 369096 kb |
| Host | smart-9a0cfa2d-5977-4882-8303-16583c718893 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964004879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1964004879 |
| Directory | /workspace/32.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.985522966 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 692649602 ps |
| CPU time | 20.3 seconds |
| Started | May 26 03:12:03 PM PDT 24 |
| Finished | May 26 03:12:24 PM PDT 24 |
| Peak memory | 218448 kb |
| Host | smart-cef1cb4d-40b7-4c2e-a444-b56c0cca7aa1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=985522966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.985522966 |
| Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2417377474 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 8425966707 ps |
| CPU time | 445.78 seconds |
| Started | May 26 03:11:48 PM PDT 24 |
| Finished | May 26 03:19:14 PM PDT 24 |
| Peak memory | 202484 kb |
| Host | smart-9f98f1bc-a7b5-423b-b0a6-fafa41ded196 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417377474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.2417377474 |
| Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.4148990816 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3356523086 ps |
| CPU time | 47.31 seconds |
| Started | May 26 03:11:55 PM PDT 24 |
| Finished | May 26 03:12:43 PM PDT 24 |
| Peak memory | 300604 kb |
| Host | smart-098608a0-192d-4689-830b-926921d63660 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148990816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.4148990816 |
| Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.1865375724 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 37938121 ps |
| CPU time | 0.64 seconds |
| Started | May 26 03:12:25 PM PDT 24 |
| Finished | May 26 03:12:27 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-f9b836fb-1aa5-4be4-89ba-c6cfe14e07db |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865375724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.1865375724 |
| Directory | /workspace/33.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_bijection.1323119165 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 92119792834 ps |
| CPU time | 1582.03 seconds |
| Started | May 26 03:12:13 PM PDT 24 |
| Finished | May 26 03:38:36 PM PDT 24 |
| Peak memory | 210836 kb |
| Host | smart-3a9e23e7-423c-4679-9861-6792eab12030 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323119165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .1323119165 |
| Directory | /workspace/33.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.2378339436 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 22287332196 ps |
| CPU time | 62.15 seconds |
| Started | May 26 03:12:21 PM PDT 24 |
| Finished | May 26 03:13:24 PM PDT 24 |
| Peak memory | 202436 kb |
| Host | smart-b6ba2e5d-1d15-46b8-b361-b197fdc6aaf2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378339436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.2378339436 |
| Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.1036330193 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 751234494 ps |
| CPU time | 62.56 seconds |
| Started | May 26 03:12:11 PM PDT 24 |
| Finished | May 26 03:13:15 PM PDT 24 |
| Peak memory | 324108 kb |
| Host | smart-bac7250e-95c4-4684-a532-cc8e3210e538 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036330193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.1036330193 |
| Directory | /workspace/33.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1937498860 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 8515838558 ps |
| CPU time | 85.03 seconds |
| Started | May 26 03:12:19 PM PDT 24 |
| Finished | May 26 03:13:45 PM PDT 24 |
| Peak memory | 212948 kb |
| Host | smart-e428bc11-277f-4d5b-b9db-81284cd3619d |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937498860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.1937498860 |
| Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.2659214103 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 6925879551 ps |
| CPU time | 143.31 seconds |
| Started | May 26 03:12:18 PM PDT 24 |
| Finished | May 26 03:14:41 PM PDT 24 |
| Peak memory | 210580 kb |
| Host | smart-a45dd3de-f2d1-49ca-af02-55992491e33a |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659214103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.2659214103 |
| Directory | /workspace/33.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.1699235197 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 10628376043 ps |
| CPU time | 980.1 seconds |
| Started | May 26 03:12:12 PM PDT 24 |
| Finished | May 26 03:28:33 PM PDT 24 |
| Peak memory | 364080 kb |
| Host | smart-03049715-2d0a-4d87-9c68-eb6762a9c341 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699235197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.1699235197 |
| Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.4058688413 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 740110299 ps |
| CPU time | 13.9 seconds |
| Started | May 26 03:12:11 PM PDT 24 |
| Finished | May 26 03:12:26 PM PDT 24 |
| Peak memory | 234724 kb |
| Host | smart-fb182633-eb4a-434c-b181-c46e42235820 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058688413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.4058688413 |
| Directory | /workspace/33.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1614985332 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 18451439252 ps |
| CPU time | 451.9 seconds |
| Started | May 26 03:12:13 PM PDT 24 |
| Finished | May 26 03:19:45 PM PDT 24 |
| Peak memory | 210732 kb |
| Host | smart-265042ac-9ec4-4610-ab2e-54f92f5c421e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614985332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.1614985332 |
| Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.1708894247 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 713629182 ps |
| CPU time | 3.19 seconds |
| Started | May 26 03:12:19 PM PDT 24 |
| Finished | May 26 03:12:22 PM PDT 24 |
| Peak memory | 202572 kb |
| Host | smart-d4699f99-953d-4ef6-a4dc-939f39189161 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708894247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1708894247 |
| Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_regwen.1798359789 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2018665977 ps |
| CPU time | 279.39 seconds |
| Started | May 26 03:12:22 PM PDT 24 |
| Finished | May 26 03:17:02 PM PDT 24 |
| Peak memory | 349604 kb |
| Host | smart-89c67124-0178-4dde-b850-1408e9972a1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798359789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1798359789 |
| Directory | /workspace/33.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_smoke.1531966506 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 380994590 ps |
| CPU time | 3.75 seconds |
| Started | May 26 03:12:11 PM PDT 24 |
| Finished | May 26 03:12:16 PM PDT 24 |
| Peak memory | 210640 kb |
| Host | smart-d059849b-6209-4c36-9ed0-8113d5bf3ba2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531966506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1531966506 |
| Directory | /workspace/33.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.237367415 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2534948422 ps |
| CPU time | 20.27 seconds |
| Started | May 26 03:12:18 PM PDT 24 |
| Finished | May 26 03:12:39 PM PDT 24 |
| Peak memory | 210892 kb |
| Host | smart-1462a4e4-1c53-41b9-b542-042910700155 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=237367415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.237367415 |
| Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.293297827 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 28263957667 ps |
| CPU time | 305.47 seconds |
| Started | May 26 03:12:12 PM PDT 24 |
| Finished | May 26 03:17:18 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-520087e6-6ad5-4700-9a31-7559f23299c6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293297827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .sram_ctrl_stress_pipeline.293297827 |
| Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3810489088 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 719852102 ps |
| CPU time | 13.83 seconds |
| Started | May 26 03:12:13 PM PDT 24 |
| Finished | May 26 03:12:28 PM PDT 24 |
| Peak memory | 240036 kb |
| Host | smart-e17f25af-29de-42d7-bffa-293eb9ba3399 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810489088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3810489088 |
| Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.2458647697 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 64022655 ps |
| CPU time | 0.66 seconds |
| Started | May 26 03:12:42 PM PDT 24 |
| Finished | May 26 03:12:43 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-4b4a7399-b772-4d61-8906-b9680dbf242a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458647697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2458647697 |
| Directory | /workspace/34.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_bijection.3097370315 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 124382141993 ps |
| CPU time | 2279.38 seconds |
| Started | May 26 03:12:27 PM PDT 24 |
| Finished | May 26 03:50:27 PM PDT 24 |
| Peak memory | 210664 kb |
| Host | smart-f5ee699c-89a2-472c-89ba-b6c978e76b8c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097370315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .3097370315 |
| Directory | /workspace/34.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_executable.212081313 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 105892335941 ps |
| CPU time | 985.84 seconds |
| Started | May 26 03:12:32 PM PDT 24 |
| Finished | May 26 03:28:59 PM PDT 24 |
| Peak memory | 374296 kb |
| Host | smart-b93d312e-87fa-482a-9b3a-3d14b56ae1d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212081313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executabl e.212081313 |
| Directory | /workspace/34.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.3780707119 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 8958540732 ps |
| CPU time | 28.87 seconds |
| Started | May 26 03:12:33 PM PDT 24 |
| Finished | May 26 03:13:02 PM PDT 24 |
| Peak memory | 202540 kb |
| Host | smart-abff3059-0158-4adb-bfd9-a9d448cb7245 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780707119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.3780707119 |
| Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.4125113991 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 6950645707 ps |
| CPU time | 155.46 seconds |
| Started | May 26 03:12:25 PM PDT 24 |
| Finished | May 26 03:15:02 PM PDT 24 |
| Peak memory | 370644 kb |
| Host | smart-ac5bcbac-5b4c-4b48-8058-0bcb46cdc3f5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125113991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.4125113991 |
| Directory | /workspace/34.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3381406045 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 9783142448 ps |
| CPU time | 159.63 seconds |
| Started | May 26 03:12:42 PM PDT 24 |
| Finished | May 26 03:15:22 PM PDT 24 |
| Peak memory | 215948 kb |
| Host | smart-c82fab26-a7c0-4cdd-9ab2-eb584619616f |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381406045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.3381406045 |
| Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.4263358781 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 14122088512 ps |
| CPU time | 314.06 seconds |
| Started | May 26 03:12:42 PM PDT 24 |
| Finished | May 26 03:17:56 PM PDT 24 |
| Peak memory | 210672 kb |
| Host | smart-ecb52944-3f84-4713-8619-cd8078191da7 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263358781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.4263358781 |
| Directory | /workspace/34.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.709944869 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 72446786219 ps |
| CPU time | 561.6 seconds |
| Started | May 26 03:12:27 PM PDT 24 |
| Finished | May 26 03:21:49 PM PDT 24 |
| Peak memory | 357968 kb |
| Host | smart-65702e90-a8db-40d6-aa5c-48440978a6ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709944869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multip le_keys.709944869 |
| Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.893290634 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 6993573985 ps |
| CPU time | 28.82 seconds |
| Started | May 26 03:12:24 PM PDT 24 |
| Finished | May 26 03:12:54 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-a8b47897-9074-4a5c-8c1a-8b13e9dfc0a8 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893290634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.s ram_ctrl_partial_access.893290634 |
| Directory | /workspace/34.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2226346932 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 15431694811 ps |
| CPU time | 368.63 seconds |
| Started | May 26 03:12:24 PM PDT 24 |
| Finished | May 26 03:18:34 PM PDT 24 |
| Peak memory | 210684 kb |
| Host | smart-89cab28d-f3b5-46d8-bbf3-efd89dc33370 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226346932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.2226346932 |
| Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.4060469043 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 549317755 ps |
| CPU time | 3.51 seconds |
| Started | May 26 03:12:42 PM PDT 24 |
| Finished | May 26 03:12:46 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-eefcb1a9-70d8-4784-a815-7409f3d37019 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060469043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.4060469043 |
| Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_regwen.2678107554 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 16467641713 ps |
| CPU time | 1420.83 seconds |
| Started | May 26 03:12:32 PM PDT 24 |
| Finished | May 26 03:36:13 PM PDT 24 |
| Peak memory | 377340 kb |
| Host | smart-488f55cb-0029-4d37-a73c-b737c399926d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678107554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2678107554 |
| Directory | /workspace/34.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_smoke.4084897230 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 825279854 ps |
| CPU time | 5.97 seconds |
| Started | May 26 03:12:26 PM PDT 24 |
| Finished | May 26 03:12:33 PM PDT 24 |
| Peak memory | 209420 kb |
| Host | smart-1d7ccb09-7c55-436c-be75-af44bd516419 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084897230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.4084897230 |
| Directory | /workspace/34.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.390373071 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 406632915 ps |
| CPU time | 12.02 seconds |
| Started | May 26 03:12:43 PM PDT 24 |
| Finished | May 26 03:12:56 PM PDT 24 |
| Peak memory | 210972 kb |
| Host | smart-e99b8247-d904-403d-ae18-31b4a0fa86ba |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=390373071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.390373071 |
| Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2057754566 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 74644171643 ps |
| CPU time | 331.45 seconds |
| Started | May 26 03:12:25 PM PDT 24 |
| Finished | May 26 03:17:58 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-381cb3d6-16dc-4b32-a3f1-a93f72d95d3b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057754566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.2057754566 |
| Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2384551788 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1524656502 ps |
| CPU time | 106.98 seconds |
| Started | May 26 03:12:33 PM PDT 24 |
| Finished | May 26 03:14:20 PM PDT 24 |
| Peak memory | 344080 kb |
| Host | smart-e5498c2c-f8e2-480a-b605-72e2c456d483 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384551788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2384551788 |
| Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.1769782706 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 11168310 ps |
| CPU time | 0.67 seconds |
| Started | May 26 03:13:05 PM PDT 24 |
| Finished | May 26 03:13:07 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-60aafd25-8486-45c5-b602-2ad7e92578f3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769782706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1769782706 |
| Directory | /workspace/35.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_bijection.2387995855 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 92532754190 ps |
| CPU time | 2340.63 seconds |
| Started | May 26 03:12:41 PM PDT 24 |
| Finished | May 26 03:51:43 PM PDT 24 |
| Peak memory | 210688 kb |
| Host | smart-0f33d528-538c-4ece-ae7f-2e0e24febee0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387995855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .2387995855 |
| Directory | /workspace/35.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_executable.2190387588 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 49043718647 ps |
| CPU time | 1283.21 seconds |
| Started | May 26 03:12:59 PM PDT 24 |
| Finished | May 26 03:34:23 PM PDT 24 |
| Peak memory | 366220 kb |
| Host | smart-82d1b203-8641-49f4-9717-37efeef6a14f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190387588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.2190387588 |
| Directory | /workspace/35.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.2946885638 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 79113445853 ps |
| CPU time | 66.34 seconds |
| Started | May 26 03:12:59 PM PDT 24 |
| Finished | May 26 03:14:06 PM PDT 24 |
| Peak memory | 210740 kb |
| Host | smart-a5ba2bab-7e55-41ee-816b-c927151d592d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946885638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.2946885638 |
| Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.1537913468 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 676185884 ps |
| CPU time | 6.47 seconds |
| Started | May 26 03:12:51 PM PDT 24 |
| Finished | May 26 03:12:58 PM PDT 24 |
| Peak memory | 210604 kb |
| Host | smart-338de95e-f36f-49fa-906b-0ff39141a731 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537913468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.1537913468 |
| Directory | /workspace/35.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3727892058 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2978180526 ps |
| CPU time | 85 seconds |
| Started | May 26 03:13:00 PM PDT 24 |
| Finished | May 26 03:14:25 PM PDT 24 |
| Peak memory | 212516 kb |
| Host | smart-3d31a0cb-05c8-48e6-847a-724dd58d294f |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727892058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.3727892058 |
| Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.2910282607 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 17582899932 ps |
| CPU time | 173.73 seconds |
| Started | May 26 03:13:00 PM PDT 24 |
| Finished | May 26 03:15:54 PM PDT 24 |
| Peak memory | 210620 kb |
| Host | smart-773975ee-0775-400f-b77f-ae01749300ec |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910282607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.2910282607 |
| Directory | /workspace/35.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.1278427091 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 22140830529 ps |
| CPU time | 1487.21 seconds |
| Started | May 26 03:12:42 PM PDT 24 |
| Finished | May 26 03:37:30 PM PDT 24 |
| Peak memory | 373292 kb |
| Host | smart-1224804c-3d63-45b9-8070-8434362b3250 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278427091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.1278427091 |
| Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.3621718373 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2822967635 ps |
| CPU time | 180.68 seconds |
| Started | May 26 03:12:48 PM PDT 24 |
| Finished | May 26 03:15:49 PM PDT 24 |
| Peak memory | 368100 kb |
| Host | smart-72ce15d6-6c10-4460-a565-d6f5a48bcb0f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621718373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.3621718373 |
| Directory | /workspace/35.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1873819758 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 41039834315 ps |
| CPU time | 269.45 seconds |
| Started | May 26 03:12:51 PM PDT 24 |
| Finished | May 26 03:17:21 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-46d167fc-30cf-4033-9968-21e966562065 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873819758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.1873819758 |
| Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.513503292 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 359715169 ps |
| CPU time | 3.5 seconds |
| Started | May 26 03:12:58 PM PDT 24 |
| Finished | May 26 03:13:02 PM PDT 24 |
| Peak memory | 202576 kb |
| Host | smart-9671546c-f157-4dd7-ba9a-7a6b401ff1be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513503292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.513503292 |
| Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_regwen.2332727856 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4844001644 ps |
| CPU time | 1378.08 seconds |
| Started | May 26 03:12:58 PM PDT 24 |
| Finished | May 26 03:35:57 PM PDT 24 |
| Peak memory | 380356 kb |
| Host | smart-c4ce673c-9422-4f86-8abe-978953d660b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332727856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2332727856 |
| Directory | /workspace/35.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_smoke.2425381241 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 14341448105 ps |
| CPU time | 189.05 seconds |
| Started | May 26 03:12:41 PM PDT 24 |
| Finished | May 26 03:15:50 PM PDT 24 |
| Peak memory | 367268 kb |
| Host | smart-17733015-ed44-4c14-8fe2-79e4ff67f4e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425381241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2425381241 |
| Directory | /workspace/35.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3962164004 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 397014524 ps |
| CPU time | 14.33 seconds |
| Started | May 26 03:12:59 PM PDT 24 |
| Finished | May 26 03:13:14 PM PDT 24 |
| Peak memory | 210692 kb |
| Host | smart-b2880f2e-d937-4c03-894b-7fd2dbf66cc5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3962164004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3962164004 |
| Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3199871475 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 51776016201 ps |
| CPU time | 433.45 seconds |
| Started | May 26 03:12:50 PM PDT 24 |
| Finished | May 26 03:20:04 PM PDT 24 |
| Peak memory | 210824 kb |
| Host | smart-4a6ecfb0-3892-4873-ad5a-47dd53e84c7b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199871475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.3199871475 |
| Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1543645362 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3010094849 ps |
| CPU time | 79.93 seconds |
| Started | May 26 03:13:01 PM PDT 24 |
| Finished | May 26 03:14:21 PM PDT 24 |
| Peak memory | 330268 kb |
| Host | smart-783eb69e-d685-448f-bf0c-e8e75bfc74c5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543645362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.1543645362 |
| Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2701218182 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 13356977990 ps |
| CPU time | 128.7 seconds |
| Started | May 26 03:13:06 PM PDT 24 |
| Finished | May 26 03:15:16 PM PDT 24 |
| Peak memory | 314724 kb |
| Host | smart-a2663577-f980-4333-aea5-4968dcffa3bc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701218182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.2701218182 |
| Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.3634330853 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 12178152 ps |
| CPU time | 0.66 seconds |
| Started | May 26 03:13:16 PM PDT 24 |
| Finished | May 26 03:13:17 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-31371d4d-5f66-45ab-a919-4cdee9ab4907 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634330853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.3634330853 |
| Directory | /workspace/36.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_bijection.1385454670 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 64314641783 ps |
| CPU time | 1050.09 seconds |
| Started | May 26 03:13:08 PM PDT 24 |
| Finished | May 26 03:30:39 PM PDT 24 |
| Peak memory | 211144 kb |
| Host | smart-c6729494-1dae-4822-854a-286c08ed4598 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385454670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .1385454670 |
| Directory | /workspace/36.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_executable.3988664306 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 10633229798 ps |
| CPU time | 575.25 seconds |
| Started | May 26 03:13:06 PM PDT 24 |
| Finished | May 26 03:22:43 PM PDT 24 |
| Peak memory | 377308 kb |
| Host | smart-b370bab2-50ca-4b13-842d-03f9ab9654f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988664306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.3988664306 |
| Directory | /workspace/36.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.3142018471 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 12633801420 ps |
| CPU time | 85.74 seconds |
| Started | May 26 03:13:05 PM PDT 24 |
| Finished | May 26 03:14:32 PM PDT 24 |
| Peak memory | 210708 kb |
| Host | smart-025462d4-1c9a-4b5c-87b7-d69d00dcfd12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142018471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.3142018471 |
| Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.71644438 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2815228524 ps |
| CPU time | 24.37 seconds |
| Started | May 26 03:13:05 PM PDT 24 |
| Finished | May 26 03:13:31 PM PDT 24 |
| Peak memory | 267696 kb |
| Host | smart-2feae038-996f-4d15-98f6-2d29eb42b06e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71644438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 36.sram_ctrl_max_throughput.71644438 |
| Directory | /workspace/36.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2380060596 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 5703194174 ps |
| CPU time | 81.35 seconds |
| Started | May 26 03:13:15 PM PDT 24 |
| Finished | May 26 03:14:37 PM PDT 24 |
| Peak memory | 213384 kb |
| Host | smart-eb5e0566-b12d-42fd-8e43-a2d339ffa4b9 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380060596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.2380060596 |
| Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.3059743975 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 5254652994 ps |
| CPU time | 284.22 seconds |
| Started | May 26 03:13:14 PM PDT 24 |
| Finished | May 26 03:17:59 PM PDT 24 |
| Peak memory | 210580 kb |
| Host | smart-5913783b-fd16-46bc-adce-ebc0a66d9838 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059743975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.3059743975 |
| Directory | /workspace/36.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.2894490408 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 14141042943 ps |
| CPU time | 1194.98 seconds |
| Started | May 26 03:13:06 PM PDT 24 |
| Finished | May 26 03:33:02 PM PDT 24 |
| Peak memory | 380548 kb |
| Host | smart-1deeadb7-efdd-42cf-a66a-ebbb858e3e30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894490408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.2894490408 |
| Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.2091182398 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 798260642 ps |
| CPU time | 12.65 seconds |
| Started | May 26 03:13:07 PM PDT 24 |
| Finished | May 26 03:13:20 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-7536e88e-8ebf-473c-bac3-f53afa05f9a7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091182398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.2091182398 |
| Directory | /workspace/36.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1512071601 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 16326206881 ps |
| CPU time | 247.02 seconds |
| Started | May 26 03:13:07 PM PDT 24 |
| Finished | May 26 03:17:15 PM PDT 24 |
| Peak memory | 210720 kb |
| Host | smart-9cd73d7b-63de-4a60-9a8b-5ee01bae090b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512071601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.1512071601 |
| Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.1988575564 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 802469257 ps |
| CPU time | 3.47 seconds |
| Started | May 26 03:13:15 PM PDT 24 |
| Finished | May 26 03:13:20 PM PDT 24 |
| Peak memory | 202552 kb |
| Host | smart-76950871-137b-49e6-8036-036b924504c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988575564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1988575564 |
| Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_regwen.3470033971 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 30826149710 ps |
| CPU time | 1499.37 seconds |
| Started | May 26 03:13:05 PM PDT 24 |
| Finished | May 26 03:38:06 PM PDT 24 |
| Peak memory | 379440 kb |
| Host | smart-7a0088cf-4d0f-46a5-a6c2-48ec4ba71b9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470033971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3470033971 |
| Directory | /workspace/36.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_smoke.3084557254 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1254878565 ps |
| CPU time | 150.34 seconds |
| Started | May 26 03:13:07 PM PDT 24 |
| Finished | May 26 03:15:38 PM PDT 24 |
| Peak memory | 364992 kb |
| Host | smart-068181f0-e1bf-4bd7-b830-d0b79bba8132 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084557254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3084557254 |
| Directory | /workspace/36.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1027758219 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 17724144054 ps |
| CPU time | 204.64 seconds |
| Started | May 26 03:13:04 PM PDT 24 |
| Finished | May 26 03:16:30 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-7f956008-314b-4864-9064-34f44290d5c8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027758219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.1027758219 |
| Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2349896169 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1453516235 ps |
| CPU time | 26.55 seconds |
| Started | May 26 03:13:05 PM PDT 24 |
| Finished | May 26 03:13:33 PM PDT 24 |
| Peak memory | 267772 kb |
| Host | smart-fc6742c1-d7f1-4a0e-9fbd-d05684c26038 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349896169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2349896169 |
| Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.3212053801 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 75850748 ps |
| CPU time | 0.66 seconds |
| Started | May 26 03:13:35 PM PDT 24 |
| Finished | May 26 03:13:37 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-e2b5a961-9192-449c-bbc0-29f310af80e9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212053801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3212053801 |
| Directory | /workspace/37.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_bijection.539340153 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 327924839679 ps |
| CPU time | 1956.54 seconds |
| Started | May 26 03:13:15 PM PDT 24 |
| Finished | May 26 03:45:52 PM PDT 24 |
| Peak memory | 210704 kb |
| Host | smart-7e8166ab-dfae-4771-a4e8-41ab10aa5093 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539340153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection. 539340153 |
| Directory | /workspace/37.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_executable.2476681535 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 21022639083 ps |
| CPU time | 715.38 seconds |
| Started | May 26 03:13:28 PM PDT 24 |
| Finished | May 26 03:25:23 PM PDT 24 |
| Peak memory | 382368 kb |
| Host | smart-ca6ea491-a628-4313-80e1-d6864fec5628 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476681535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.2476681535 |
| Directory | /workspace/37.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.2601131098 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 14001224913 ps |
| CPU time | 18.09 seconds |
| Started | May 26 03:13:21 PM PDT 24 |
| Finished | May 26 03:13:39 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-a39fd42c-5ec8-4e40-99fd-352f4f86498f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601131098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.2601131098 |
| Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.2525206253 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 787520279 ps |
| CPU time | 86.98 seconds |
| Started | May 26 03:13:21 PM PDT 24 |
| Finished | May 26 03:14:49 PM PDT 24 |
| Peak memory | 335344 kb |
| Host | smart-44355e00-ff45-4e2d-9b83-6474c6692704 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525206253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.2525206253 |
| Directory | /workspace/37.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.653163459 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2420085925 ps |
| CPU time | 82.06 seconds |
| Started | May 26 03:13:37 PM PDT 24 |
| Finished | May 26 03:15:00 PM PDT 24 |
| Peak memory | 212856 kb |
| Host | smart-93a478cf-8c78-4359-9449-a4d1dc52288e |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653163459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_mem_partial_access.653163459 |
| Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.4072608965 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3985635462 ps |
| CPU time | 253.72 seconds |
| Started | May 26 03:13:27 PM PDT 24 |
| Finished | May 26 03:17:41 PM PDT 24 |
| Peak memory | 210584 kb |
| Host | smart-111cfd0f-65b4-422f-90e7-194865194d30 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072608965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.4072608965 |
| Directory | /workspace/37.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.7202763 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 13376079789 ps |
| CPU time | 215.37 seconds |
| Started | May 26 03:13:16 PM PDT 24 |
| Finished | May 26 03:16:52 PM PDT 24 |
| Peak memory | 377476 kb |
| Host | smart-b2fdd04d-fc48-49fe-9418-fd9c417a0f00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7202763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multipl e_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple _keys.7202763 |
| Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.1828219597 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1050113200 ps |
| CPU time | 47.75 seconds |
| Started | May 26 03:13:21 PM PDT 24 |
| Finished | May 26 03:14:09 PM PDT 24 |
| Peak memory | 284856 kb |
| Host | smart-bfd111cb-ba21-4063-b568-63535aa8fe3e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828219597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.1828219597 |
| Directory | /workspace/37.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2698163434 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 15246050901 ps |
| CPU time | 389.79 seconds |
| Started | May 26 03:13:20 PM PDT 24 |
| Finished | May 26 03:19:50 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-6a7f0ca0-918a-496b-91de-614c3e301d53 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698163434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.2698163434 |
| Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.1470814243 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 363330597 ps |
| CPU time | 3.34 seconds |
| Started | May 26 03:13:27 PM PDT 24 |
| Finished | May 26 03:13:31 PM PDT 24 |
| Peak memory | 202568 kb |
| Host | smart-71d133d8-372c-4620-8cd8-b178290cf81e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470814243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1470814243 |
| Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_regwen.219523683 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10914265119 ps |
| CPU time | 612.09 seconds |
| Started | May 26 03:13:27 PM PDT 24 |
| Finished | May 26 03:23:39 PM PDT 24 |
| Peak memory | 379372 kb |
| Host | smart-a1ec8665-d6db-431b-84bd-d78e35a7d350 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219523683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.219523683 |
| Directory | /workspace/37.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_smoke.672683553 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2028370100 ps |
| CPU time | 15.29 seconds |
| Started | May 26 03:13:15 PM PDT 24 |
| Finished | May 26 03:13:31 PM PDT 24 |
| Peak memory | 210564 kb |
| Host | smart-c9c84bbc-3e91-47fa-892f-3a619aef7343 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672683553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.672683553 |
| Directory | /workspace/37.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2425001491 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3403201616 ps |
| CPU time | 157.77 seconds |
| Started | May 26 03:13:20 PM PDT 24 |
| Finished | May 26 03:15:58 PM PDT 24 |
| Peak memory | 202464 kb |
| Host | smart-9652e7a3-0e1a-41bb-95bb-28edd7253f49 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425001491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.2425001491 |
| Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.707357684 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1614627950 ps |
| CPU time | 118.07 seconds |
| Started | May 26 03:13:21 PM PDT 24 |
| Finished | May 26 03:15:20 PM PDT 24 |
| Peak memory | 359716 kb |
| Host | smart-7dd36b8c-fba0-4af4-b938-c7f6400d529b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707357684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_throughput_w_partial_write.707357684 |
| Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.3161486489 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 12342439 ps |
| CPU time | 0.65 seconds |
| Started | May 26 03:13:53 PM PDT 24 |
| Finished | May 26 03:13:54 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-600d727e-6282-4308-8fdf-2d078102773b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161486489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3161486489 |
| Directory | /workspace/38.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_bijection.2550189509 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 138022804389 ps |
| CPU time | 1826.52 seconds |
| Started | May 26 03:13:41 PM PDT 24 |
| Finished | May 26 03:44:09 PM PDT 24 |
| Peak memory | 210652 kb |
| Host | smart-5cb03c36-2088-40f9-9d16-9466612aa278 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550189509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .2550189509 |
| Directory | /workspace/38.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_executable.3871515927 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 33939681375 ps |
| CPU time | 1777.03 seconds |
| Started | May 26 03:13:42 PM PDT 24 |
| Finished | May 26 03:43:20 PM PDT 24 |
| Peak memory | 378388 kb |
| Host | smart-d55c4b84-1cf0-4801-a1b9-068c99a3d8e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871515927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.3871515927 |
| Directory | /workspace/38.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.1490781438 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 30847160613 ps |
| CPU time | 76.93 seconds |
| Started | May 26 03:13:43 PM PDT 24 |
| Finished | May 26 03:15:01 PM PDT 24 |
| Peak memory | 202556 kb |
| Host | smart-b11ae056-f030-4d89-8d12-42ace7b558d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490781438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.1490781438 |
| Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.1187604949 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 772273487 ps |
| CPU time | 158.93 seconds |
| Started | May 26 03:13:42 PM PDT 24 |
| Finished | May 26 03:16:22 PM PDT 24 |
| Peak memory | 367936 kb |
| Host | smart-9d72c5a6-55ae-4b11-be41-7300f4ea0e8e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187604949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.1187604949 |
| Directory | /workspace/38.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.36354058 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 26587038910 ps |
| CPU time | 86.6 seconds |
| Started | May 26 03:13:52 PM PDT 24 |
| Finished | May 26 03:15:19 PM PDT 24 |
| Peak memory | 212988 kb |
| Host | smart-f80115b3-0f86-4f32-ad9a-9a52b93a26b6 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36354058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_mem_partial_access.36354058 |
| Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.4198865111 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 40387321451 ps |
| CPU time | 309.5 seconds |
| Started | May 26 03:13:51 PM PDT 24 |
| Finished | May 26 03:19:01 PM PDT 24 |
| Peak memory | 210572 kb |
| Host | smart-edadf4a3-247e-4487-af3b-dea33b24ec7f |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198865111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.4198865111 |
| Directory | /workspace/38.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.3078456617 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 86648736558 ps |
| CPU time | 1252.23 seconds |
| Started | May 26 03:13:42 PM PDT 24 |
| Finished | May 26 03:34:35 PM PDT 24 |
| Peak memory | 378360 kb |
| Host | smart-45c749bd-2679-4e7f-a208-dd18d66700ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078456617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.3078456617 |
| Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.1064849806 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7289091514 ps |
| CPU time | 9.85 seconds |
| Started | May 26 03:13:43 PM PDT 24 |
| Finished | May 26 03:13:53 PM PDT 24 |
| Peak memory | 202476 kb |
| Host | smart-0fe780c3-3652-45a0-8874-a75921d27fab |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064849806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.1064849806 |
| Directory | /workspace/38.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2038451092 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 97579777296 ps |
| CPU time | 463.37 seconds |
| Started | May 26 03:13:44 PM PDT 24 |
| Finished | May 26 03:21:28 PM PDT 24 |
| Peak memory | 210692 kb |
| Host | smart-a30fa758-7d89-4bb6-9179-e9e83340b23b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038451092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.2038451092 |
| Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.1594672481 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 1401049362 ps |
| CPU time | 3.41 seconds |
| Started | May 26 03:13:50 PM PDT 24 |
| Finished | May 26 03:13:54 PM PDT 24 |
| Peak memory | 202528 kb |
| Host | smart-bdad214d-bc39-4582-9230-0d0111129135 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594672481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1594672481 |
| Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_regwen.2195918175 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 67177367065 ps |
| CPU time | 1415.09 seconds |
| Started | May 26 03:13:42 PM PDT 24 |
| Finished | May 26 03:37:18 PM PDT 24 |
| Peak memory | 379632 kb |
| Host | smart-61ac1415-d4d6-460e-b133-b8eec25a77f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195918175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2195918175 |
| Directory | /workspace/38.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_smoke.1868264734 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 6303216078 ps |
| CPU time | 25.13 seconds |
| Started | May 26 03:13:37 PM PDT 24 |
| Finished | May 26 03:14:03 PM PDT 24 |
| Peak memory | 202456 kb |
| Host | smart-3ac781fc-8f26-4990-8c92-764286aaac2c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868264734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1868264734 |
| Directory | /workspace/38.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1606466123 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1348265312 ps |
| CPU time | 7.76 seconds |
| Started | May 26 03:13:50 PM PDT 24 |
| Finished | May 26 03:13:58 PM PDT 24 |
| Peak memory | 210792 kb |
| Host | smart-9be832fe-eeee-465b-9d7c-85b46b509b61 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1606466123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1606466123 |
| Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3569550933 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4482880429 ps |
| CPU time | 215.76 seconds |
| Started | May 26 03:13:42 PM PDT 24 |
| Finished | May 26 03:17:19 PM PDT 24 |
| Peak memory | 210692 kb |
| Host | smart-24237d29-adc7-4adf-b616-dfda820e56d8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569550933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.3569550933 |
| Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1666867358 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2675121711 ps |
| CPU time | 6.8 seconds |
| Started | May 26 03:13:45 PM PDT 24 |
| Finished | May 26 03:13:52 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-862547ee-b467-4f9d-a8c3-08334506a0f8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666867358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.1666867358 |
| Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.3402357116 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 61096903 ps |
| CPU time | 0.65 seconds |
| Started | May 26 03:14:12 PM PDT 24 |
| Finished | May 26 03:14:13 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-3a1da872-093a-4c17-8905-a454b6d81643 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402357116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3402357116 |
| Directory | /workspace/39.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_bijection.161404598 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 12617987193 ps |
| CPU time | 826.67 seconds |
| Started | May 26 03:13:58 PM PDT 24 |
| Finished | May 26 03:27:45 PM PDT 24 |
| Peak memory | 210692 kb |
| Host | smart-637fcf84-070c-4da0-bc4a-c8b128cd7109 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161404598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection. 161404598 |
| Directory | /workspace/39.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_executable.1159944826 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 34776143615 ps |
| CPU time | 1227.58 seconds |
| Started | May 26 03:14:02 PM PDT 24 |
| Finished | May 26 03:34:31 PM PDT 24 |
| Peak memory | 379136 kb |
| Host | smart-87d708be-278e-4ffd-8dd4-ca446f8139bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159944826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.1159944826 |
| Directory | /workspace/39.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.1229132540 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 18165359620 ps |
| CPU time | 90.56 seconds |
| Started | May 26 03:14:00 PM PDT 24 |
| Finished | May 26 03:15:32 PM PDT 24 |
| Peak memory | 202632 kb |
| Host | smart-fc385572-b64c-4d38-aeed-4fe58a6672f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229132540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.1229132540 |
| Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.3190754149 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1489266651 ps |
| CPU time | 42.9 seconds |
| Started | May 26 03:13:58 PM PDT 24 |
| Finished | May 26 03:14:41 PM PDT 24 |
| Peak memory | 289732 kb |
| Host | smart-c64cf941-7112-45b2-a0be-238fccd987c9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190754149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.3190754149 |
| Directory | /workspace/39.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.665450965 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 10713776370 ps |
| CPU time | 89.3 seconds |
| Started | May 26 03:14:04 PM PDT 24 |
| Finished | May 26 03:15:34 PM PDT 24 |
| Peak memory | 213580 kb |
| Host | smart-62909c32-026d-49b5-ac13-c9195fc62372 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665450965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .sram_ctrl_mem_partial_access.665450965 |
| Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.3036911867 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 12217127111 ps |
| CPU time | 302.77 seconds |
| Started | May 26 03:14:07 PM PDT 24 |
| Finished | May 26 03:19:10 PM PDT 24 |
| Peak memory | 210580 kb |
| Host | smart-1b422314-3ef6-43d2-a297-43cd55fd36ab |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036911867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.3036911867 |
| Directory | /workspace/39.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.2296877662 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 9164092474 ps |
| CPU time | 301.96 seconds |
| Started | May 26 03:13:57 PM PDT 24 |
| Finished | May 26 03:19:00 PM PDT 24 |
| Peak memory | 342100 kb |
| Host | smart-8c82cd66-c768-4f0a-b5b6-e35712e0b77c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296877662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.2296877662 |
| Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.399796156 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 972665563 ps |
| CPU time | 22.81 seconds |
| Started | May 26 03:13:58 PM PDT 24 |
| Finished | May 26 03:14:21 PM PDT 24 |
| Peak memory | 251312 kb |
| Host | smart-6f2da2b7-dfbc-4e08-a700-c162dd8caba7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399796156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s ram_ctrl_partial_access.399796156 |
| Directory | /workspace/39.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4094797799 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 35469983708 ps |
| CPU time | 438.67 seconds |
| Started | May 26 03:14:01 PM PDT 24 |
| Finished | May 26 03:21:20 PM PDT 24 |
| Peak memory | 210688 kb |
| Host | smart-ac397095-f057-4a41-aee6-13e6ad0d9999 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094797799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.4094797799 |
| Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.9913517 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1407363875 ps |
| CPU time | 3.81 seconds |
| Started | May 26 03:14:06 PM PDT 24 |
| Finished | May 26 03:14:11 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-4f6483d2-dde8-4342-bf28-7bc3820957ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9913517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.9913517 |
| Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_regwen.469921087 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3281860918 ps |
| CPU time | 476.3 seconds |
| Started | May 26 03:14:03 PM PDT 24 |
| Finished | May 26 03:22:01 PM PDT 24 |
| Peak memory | 359948 kb |
| Host | smart-87af79f0-57bf-47ea-8d85-06b88dfca364 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469921087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.469921087 |
| Directory | /workspace/39.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_smoke.2125931553 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 972414790 ps |
| CPU time | 29.67 seconds |
| Started | May 26 03:13:58 PM PDT 24 |
| Finished | May 26 03:14:28 PM PDT 24 |
| Peak memory | 274048 kb |
| Host | smart-de91353e-a5aa-4e14-9682-eeff3c75d42a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125931553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2125931553 |
| Directory | /workspace/39.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3066252413 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 979508382 ps |
| CPU time | 55.25 seconds |
| Started | May 26 03:14:04 PM PDT 24 |
| Finished | May 26 03:15:00 PM PDT 24 |
| Peak memory | 210704 kb |
| Host | smart-f13013f9-e116-4d1a-b112-4a21a70a8eee |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3066252413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3066252413 |
| Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2571060162 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4205334918 ps |
| CPU time | 285.56 seconds |
| Started | May 26 03:13:58 PM PDT 24 |
| Finished | May 26 03:18:44 PM PDT 24 |
| Peak memory | 210676 kb |
| Host | smart-fbcbec21-9f66-47b8-afdc-29e5dc0c5423 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571060162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.2571060162 |
| Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.428990452 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 683196460 ps |
| CPU time | 7.03 seconds |
| Started | May 26 03:13:57 PM PDT 24 |
| Finished | May 26 03:14:05 PM PDT 24 |
| Peak memory | 216408 kb |
| Host | smart-244107bf-4fba-4e2b-853f-00898c0e58a4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428990452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_throughput_w_partial_write.428990452 |
| Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.2819097380 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 19366676 ps |
| CPU time | 0.67 seconds |
| Started | May 26 03:04:06 PM PDT 24 |
| Finished | May 26 03:04:07 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-452eec76-ef6e-4cba-a503-81edb21571dc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819097380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2819097380 |
| Directory | /workspace/4.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_bijection.2618076692 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 39616076514 ps |
| CPU time | 567.69 seconds |
| Started | May 26 03:03:51 PM PDT 24 |
| Finished | May 26 03:13:20 PM PDT 24 |
| Peak memory | 210664 kb |
| Host | smart-fea40851-6e9a-4d18-a3aa-f00fd83da222 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618076692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 2618076692 |
| Directory | /workspace/4.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_executable.3130269446 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 8756542612 ps |
| CPU time | 628.93 seconds |
| Started | May 26 03:04:06 PM PDT 24 |
| Finished | May 26 03:14:36 PM PDT 24 |
| Peak memory | 378184 kb |
| Host | smart-e2d4d9f4-1037-4b81-9a3d-14c5c8162cce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130269446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.3130269446 |
| Directory | /workspace/4.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.124281890 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 4650126955 ps |
| CPU time | 19.03 seconds |
| Started | May 26 03:04:00 PM PDT 24 |
| Finished | May 26 03:04:20 PM PDT 24 |
| Peak memory | 210712 kb |
| Host | smart-de08bc05-a95e-4828-b165-74ca8d9cd48c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124281890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca lation.124281890 |
| Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.1498850749 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 12722646583 ps |
| CPU time | 137.54 seconds |
| Started | May 26 03:03:57 PM PDT 24 |
| Finished | May 26 03:06:15 PM PDT 24 |
| Peak memory | 366056 kb |
| Host | smart-4f5bd9c3-798e-4804-9d7d-89c6b9c63edf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498850749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.1498850749 |
| Directory | /workspace/4.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3660607323 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4709440264 ps |
| CPU time | 158.66 seconds |
| Started | May 26 03:04:05 PM PDT 24 |
| Finished | May 26 03:06:44 PM PDT 24 |
| Peak memory | 215000 kb |
| Host | smart-ca2eeca9-1faf-48a1-a5eb-79c8b790b12c |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660607323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.3660607323 |
| Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.2313861539 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 10511074590 ps |
| CPU time | 159.12 seconds |
| Started | May 26 03:04:06 PM PDT 24 |
| Finished | May 26 03:06:46 PM PDT 24 |
| Peak memory | 211208 kb |
| Host | smart-82c998bf-9e4a-4447-a2af-7d7620a6cd0b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313861539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.2313861539 |
| Directory | /workspace/4.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.951250682 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 39851129089 ps |
| CPU time | 1552.54 seconds |
| Started | May 26 03:03:51 PM PDT 24 |
| Finished | May 26 03:29:45 PM PDT 24 |
| Peak memory | 374312 kb |
| Host | smart-8e23ba65-7bce-4b7a-a1f3-ed59eee3e90b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951250682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl e_keys.951250682 |
| Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.488297235 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 554374356 ps |
| CPU time | 14.6 seconds |
| Started | May 26 03:03:57 PM PDT 24 |
| Finished | May 26 03:04:13 PM PDT 24 |
| Peak memory | 210628 kb |
| Host | smart-9cbf3e17-1792-4041-9a00-0d8ffdfcaf6b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488297235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr am_ctrl_partial_access.488297235 |
| Directory | /workspace/4.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1575324660 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 8064359601 ps |
| CPU time | 393.41 seconds |
| Started | May 26 03:03:58 PM PDT 24 |
| Finished | May 26 03:10:32 PM PDT 24 |
| Peak memory | 210656 kb |
| Host | smart-077b9a83-b65f-4e5e-b1ec-aaf9d6267a7f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575324660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.1575324660 |
| Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.2796707873 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1475419072 ps |
| CPU time | 3.4 seconds |
| Started | May 26 03:04:06 PM PDT 24 |
| Finished | May 26 03:04:10 PM PDT 24 |
| Peak memory | 202516 kb |
| Host | smart-6b04afc9-eda2-4af0-963a-210221d20110 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796707873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2796707873 |
| Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_regwen.1905679485 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 85111995101 ps |
| CPU time | 1000.87 seconds |
| Started | May 26 03:04:06 PM PDT 24 |
| Finished | May 26 03:20:48 PM PDT 24 |
| Peak memory | 371292 kb |
| Host | smart-93860032-1a09-4d3a-87a9-74fdb22990e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905679485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1905679485 |
| Directory | /workspace/4.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.2057891250 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 368991611 ps |
| CPU time | 2.24 seconds |
| Started | May 26 03:04:04 PM PDT 24 |
| Finished | May 26 03:04:07 PM PDT 24 |
| Peak memory | 221936 kb |
| Host | smart-84d8e6ea-a592-409a-a686-04ba9bcf82dc |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057891250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.2057891250 |
| Directory | /workspace/4.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_smoke.1770472343 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 430586884 ps |
| CPU time | 5.34 seconds |
| Started | May 26 03:03:52 PM PDT 24 |
| Finished | May 26 03:03:58 PM PDT 24 |
| Peak memory | 210636 kb |
| Host | smart-bbe0b7c1-4b4d-443e-ae84-b7bad598e0e9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770472343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1770472343 |
| Directory | /workspace/4.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.1868138174 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 309323906586 ps |
| CPU time | 2959.95 seconds |
| Started | May 26 03:04:05 PM PDT 24 |
| Finished | May 26 03:53:26 PM PDT 24 |
| Peak memory | 204936 kb |
| Host | smart-dbfac40d-fbe9-43f6-bc2b-e6689f922578 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868138174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.1868138174 |
| Directory | /workspace/4.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3688861588 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 52583013011 ps |
| CPU time | 211.8 seconds |
| Started | May 26 03:03:59 PM PDT 24 |
| Finished | May 26 03:07:31 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-e8813862-e51b-427a-9b9d-209888c2d3d1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688861588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.3688861588 |
| Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3875668879 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 722622642 ps |
| CPU time | 17.54 seconds |
| Started | May 26 03:03:57 PM PDT 24 |
| Finished | May 26 03:04:15 PM PDT 24 |
| Peak memory | 244408 kb |
| Host | smart-7f46be73-ea0d-4943-9f6f-ae0eb1fb08ea |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875668879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3875668879 |
| Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2881172372 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 4864703973 ps |
| CPU time | 151.94 seconds |
| Started | May 26 03:14:17 PM PDT 24 |
| Finished | May 26 03:16:50 PM PDT 24 |
| Peak memory | 358300 kb |
| Host | smart-ae6f7cf5-70fc-4899-9733-4ef2d859cfc0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881172372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.2881172372 |
| Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.1439298719 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 60294802 ps |
| CPU time | 0.67 seconds |
| Started | May 26 03:14:33 PM PDT 24 |
| Finished | May 26 03:14:34 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-29b905b4-eefb-4199-b150-a3b3904149a4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439298719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1439298719 |
| Directory | /workspace/40.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_bijection.1665333720 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 72881592693 ps |
| CPU time | 1409.25 seconds |
| Started | May 26 03:14:11 PM PDT 24 |
| Finished | May 26 03:37:41 PM PDT 24 |
| Peak memory | 210616 kb |
| Host | smart-02234e74-98c4-4d88-b744-be16ea3d05fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665333720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .1665333720 |
| Directory | /workspace/40.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_executable.1249427635 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 37096394826 ps |
| CPU time | 1080.84 seconds |
| Started | May 26 03:14:18 PM PDT 24 |
| Finished | May 26 03:32:19 PM PDT 24 |
| Peak memory | 375368 kb |
| Host | smart-bd83f190-c68d-4bf3-9e6a-d627a60a121e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249427635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.1249427635 |
| Directory | /workspace/40.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.4140138731 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 12924629221 ps |
| CPU time | 77.98 seconds |
| Started | May 26 03:14:17 PM PDT 24 |
| Finished | May 26 03:15:36 PM PDT 24 |
| Peak memory | 202540 kb |
| Host | smart-46dd0605-17a4-4148-ac43-c121e5b1396a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140138731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.4140138731 |
| Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.2645110576 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2192603937 ps |
| CPU time | 52.32 seconds |
| Started | May 26 03:14:18 PM PDT 24 |
| Finished | May 26 03:15:11 PM PDT 24 |
| Peak memory | 300544 kb |
| Host | smart-e2ab0779-f4ae-4dda-a1c3-cd1b77061c1e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645110576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.2645110576 |
| Directory | /workspace/40.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.1994261829 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 7311774932 ps |
| CPU time | 84.63 seconds |
| Started | May 26 03:14:24 PM PDT 24 |
| Finished | May 26 03:15:49 PM PDT 24 |
| Peak memory | 213452 kb |
| Host | smart-22d31c93-8e7d-405e-99fe-0a4e6e79bd05 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994261829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.1994261829 |
| Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.2314976049 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 121788747758 ps |
| CPU time | 346.87 seconds |
| Started | May 26 03:14:25 PM PDT 24 |
| Finished | May 26 03:20:13 PM PDT 24 |
| Peak memory | 211432 kb |
| Host | smart-46745ab8-97a0-4263-a26c-735187da18c9 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314976049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.2314976049 |
| Directory | /workspace/40.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.3666655915 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 6410006154 ps |
| CPU time | 688.85 seconds |
| Started | May 26 03:14:10 PM PDT 24 |
| Finished | May 26 03:25:40 PM PDT 24 |
| Peak memory | 375296 kb |
| Host | smart-bae9aab8-82bd-4ee3-bee9-699a82c42048 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666655915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.3666655915 |
| Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.708950282 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 854211633 ps |
| CPU time | 50.79 seconds |
| Started | May 26 03:14:11 PM PDT 24 |
| Finished | May 26 03:15:03 PM PDT 24 |
| Peak memory | 294612 kb |
| Host | smart-e9298927-3eb8-4118-8a87-7117ebbf43f7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708950282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s ram_ctrl_partial_access.708950282 |
| Directory | /workspace/40.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.868198717 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 44802777651 ps |
| CPU time | 542.88 seconds |
| Started | May 26 03:14:18 PM PDT 24 |
| Finished | May 26 03:23:21 PM PDT 24 |
| Peak memory | 202456 kb |
| Host | smart-d9935376-50a7-4ec1-8e05-d3d30793ba25 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868198717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.sram_ctrl_partial_access_b2b.868198717 |
| Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.2309873170 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1397734387 ps |
| CPU time | 3.5 seconds |
| Started | May 26 03:14:26 PM PDT 24 |
| Finished | May 26 03:14:30 PM PDT 24 |
| Peak memory | 202528 kb |
| Host | smart-985674a9-8ca0-4533-9cc4-c2cbc2c9e4bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309873170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2309873170 |
| Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_regwen.3776706349 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 117436398927 ps |
| CPU time | 1614.28 seconds |
| Started | May 26 03:14:26 PM PDT 24 |
| Finished | May 26 03:41:20 PM PDT 24 |
| Peak memory | 377392 kb |
| Host | smart-c1d5aab7-1944-4645-b3ee-8abfc4fea164 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776706349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3776706349 |
| Directory | /workspace/40.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_smoke.2100015659 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1408935479 ps |
| CPU time | 20.47 seconds |
| Started | May 26 03:14:11 PM PDT 24 |
| Finished | May 26 03:14:33 PM PDT 24 |
| Peak memory | 202404 kb |
| Host | smart-29543b1e-19d6-49c8-be9d-050c410df608 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100015659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2100015659 |
| Directory | /workspace/40.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2900801631 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 5525486593 ps |
| CPU time | 43.95 seconds |
| Started | May 26 03:14:25 PM PDT 24 |
| Finished | May 26 03:15:10 PM PDT 24 |
| Peak memory | 218912 kb |
| Host | smart-c24bd28c-6165-4a6d-9bcd-00fdcbc3a258 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2900801631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2900801631 |
| Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1301399313 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 6181176772 ps |
| CPU time | 281.83 seconds |
| Started | May 26 03:14:11 PM PDT 24 |
| Finished | May 26 03:18:53 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-da0f882d-24c1-4ec4-9eff-6514e18cd6e1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301399313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.1301399313 |
| Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3254945813 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 790285128 ps |
| CPU time | 135.7 seconds |
| Started | May 26 03:14:18 PM PDT 24 |
| Finished | May 26 03:16:34 PM PDT 24 |
| Peak memory | 370112 kb |
| Host | smart-849b29ea-95f6-4d6f-9eb6-890dc50ebe89 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254945813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3254945813 |
| Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.762146735 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 51256363 ps |
| CPU time | 0.65 seconds |
| Started | May 26 03:14:38 PM PDT 24 |
| Finished | May 26 03:14:40 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-d0df28f0-9320-402c-b2a7-fbaae82d85e8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762146735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.762146735 |
| Directory | /workspace/41.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_bijection.2469246818 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 137796052891 ps |
| CPU time | 2795.54 seconds |
| Started | May 26 03:14:31 PM PDT 24 |
| Finished | May 26 04:01:07 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-78db07f0-7f08-4d55-97af-6cd49d2ae8ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469246818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .2469246818 |
| Directory | /workspace/41.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_executable.552407194 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 17305217113 ps |
| CPU time | 778.78 seconds |
| Started | May 26 03:14:34 PM PDT 24 |
| Finished | May 26 03:27:33 PM PDT 24 |
| Peak memory | 372272 kb |
| Host | smart-002c40f0-256f-4309-b4ad-ff4a5f1f82c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552407194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executabl e.552407194 |
| Directory | /workspace/41.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.3675836404 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 12657826817 ps |
| CPU time | 58.94 seconds |
| Started | May 26 03:14:32 PM PDT 24 |
| Finished | May 26 03:15:32 PM PDT 24 |
| Peak memory | 202532 kb |
| Host | smart-4887056c-bf41-4d61-bf0d-5ba91530f592 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675836404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.3675836404 |
| Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.1356113700 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2394835620 ps |
| CPU time | 167.33 seconds |
| Started | May 26 03:14:31 PM PDT 24 |
| Finished | May 26 03:17:19 PM PDT 24 |
| Peak memory | 370124 kb |
| Host | smart-5bf34d1f-e272-407d-bf81-3164128ef9b6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356113700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.1356113700 |
| Directory | /workspace/41.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3284003376 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 22268057882 ps |
| CPU time | 181.9 seconds |
| Started | May 26 03:14:38 PM PDT 24 |
| Finished | May 26 03:17:42 PM PDT 24 |
| Peak memory | 214860 kb |
| Host | smart-e11dc86a-4473-46be-8381-ed95c3cac271 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284003376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.3284003376 |
| Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.637735533 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 2042670105 ps |
| CPU time | 126.17 seconds |
| Started | May 26 03:14:38 PM PDT 24 |
| Finished | May 26 03:16:46 PM PDT 24 |
| Peak memory | 210540 kb |
| Host | smart-de82b04c-8b65-4b2a-a2d1-7db5906963ee |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637735533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl _mem_walk.637735533 |
| Directory | /workspace/41.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.2283068153 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1162648684 ps |
| CPU time | 19.31 seconds |
| Started | May 26 03:14:32 PM PDT 24 |
| Finished | May 26 03:14:52 PM PDT 24 |
| Peak memory | 205600 kb |
| Host | smart-a5fa7f79-2149-48ff-80fc-4d946deabba7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283068153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.2283068153 |
| Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.1304945904 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1202509995 ps |
| CPU time | 20.4 seconds |
| Started | May 26 03:14:33 PM PDT 24 |
| Finished | May 26 03:14:54 PM PDT 24 |
| Peak memory | 210632 kb |
| Host | smart-32370893-e47f-4dd0-b202-0f85fb69df2c |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304945904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.1304945904 |
| Directory | /workspace/41.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.455187898 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 15684158847 ps |
| CPU time | 399.52 seconds |
| Started | May 26 03:14:31 PM PDT 24 |
| Finished | May 26 03:21:11 PM PDT 24 |
| Peak memory | 210696 kb |
| Host | smart-a37e8701-c0a9-4bcc-8a1c-f585b016f167 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455187898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.sram_ctrl_partial_access_b2b.455187898 |
| Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.1247811613 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 349906830 ps |
| CPU time | 3.26 seconds |
| Started | May 26 03:14:38 PM PDT 24 |
| Finished | May 26 03:14:43 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-e5766125-8cd8-48a1-872f-f474156fca54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247811613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1247811613 |
| Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_regwen.3365679804 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 16556122028 ps |
| CPU time | 982.21 seconds |
| Started | May 26 03:14:32 PM PDT 24 |
| Finished | May 26 03:30:55 PM PDT 24 |
| Peak memory | 378412 kb |
| Host | smart-08d2729a-2db6-460e-a3b6-9ef89f888340 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365679804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3365679804 |
| Directory | /workspace/41.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_smoke.388350961 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1686196841 ps |
| CPU time | 22.21 seconds |
| Started | May 26 03:14:32 PM PDT 24 |
| Finished | May 26 03:14:55 PM PDT 24 |
| Peak memory | 202392 kb |
| Host | smart-a6db58cd-6068-4d50-9e13-04b0ea534be0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388350961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.388350961 |
| Directory | /workspace/41.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.1149343128 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 19272629859 ps |
| CPU time | 248.44 seconds |
| Started | May 26 03:14:31 PM PDT 24 |
| Finished | May 26 03:18:41 PM PDT 24 |
| Peak memory | 210668 kb |
| Host | smart-31451561-aef9-4d43-a3da-a491d2e3b07b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149343128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.1149343128 |
| Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3579510427 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 701811044 ps |
| CPU time | 8.2 seconds |
| Started | May 26 03:14:31 PM PDT 24 |
| Finished | May 26 03:14:40 PM PDT 24 |
| Peak memory | 218740 kb |
| Host | smart-eeba23e7-8998-48ed-ac41-21fc74b5ee66 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579510427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3579510427 |
| Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.327232759 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 20996616 ps |
| CPU time | 0.64 seconds |
| Started | May 26 03:15:03 PM PDT 24 |
| Finished | May 26 03:15:04 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-86818348-dd2a-4ed7-8837-a80d7c157318 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327232759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.327232759 |
| Directory | /workspace/42.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_bijection.1792812710 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 25447359002 ps |
| CPU time | 1640.88 seconds |
| Started | May 26 03:14:46 PM PDT 24 |
| Finished | May 26 03:42:07 PM PDT 24 |
| Peak memory | 210692 kb |
| Host | smart-7e3bce52-8f4f-4ff3-a896-0b8f70e3d28c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792812710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .1792812710 |
| Directory | /workspace/42.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_executable.2101723395 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 128467267144 ps |
| CPU time | 860.82 seconds |
| Started | May 26 03:14:56 PM PDT 24 |
| Finished | May 26 03:29:17 PM PDT 24 |
| Peak memory | 378468 kb |
| Host | smart-11942eb2-cf62-49bf-9ea3-69cd5c944b66 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101723395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.2101723395 |
| Directory | /workspace/42.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.199315122 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 23017682958 ps |
| CPU time | 68.77 seconds |
| Started | May 26 03:14:56 PM PDT 24 |
| Finished | May 26 03:16:05 PM PDT 24 |
| Peak memory | 202472 kb |
| Host | smart-03f763eb-a33e-4208-95f9-1bb89f024bd4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199315122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esc alation.199315122 |
| Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.2315482947 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 7596845264 ps |
| CPU time | 146.97 seconds |
| Started | May 26 03:14:48 PM PDT 24 |
| Finished | May 26 03:17:15 PM PDT 24 |
| Peak memory | 364924 kb |
| Host | smart-99579e98-2974-4d6d-b50e-7ed831c2256c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315482947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.2315482947 |
| Directory | /workspace/42.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.420317914 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2569439064 ps |
| CPU time | 89.18 seconds |
| Started | May 26 03:15:02 PM PDT 24 |
| Finished | May 26 03:16:32 PM PDT 24 |
| Peak memory | 212808 kb |
| Host | smart-fac169b6-6971-471e-a330-889b3ccf1e5e |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420317914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_mem_partial_access.420317914 |
| Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.2970390239 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6931187117 ps |
| CPU time | 162.57 seconds |
| Started | May 26 03:15:01 PM PDT 24 |
| Finished | May 26 03:17:44 PM PDT 24 |
| Peak memory | 210592 kb |
| Host | smart-b8d150c5-8582-4b70-86d2-ffdc6e32c491 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970390239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.2970390239 |
| Directory | /workspace/42.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.2303573775 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 65215741650 ps |
| CPU time | 936.21 seconds |
| Started | May 26 03:14:46 PM PDT 24 |
| Finished | May 26 03:30:23 PM PDT 24 |
| Peak memory | 378096 kb |
| Host | smart-5ede3e43-061b-473d-ae44-de2ba875dd57 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303573775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.2303573775 |
| Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.3742732735 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1411311073 ps |
| CPU time | 127.75 seconds |
| Started | May 26 03:14:48 PM PDT 24 |
| Finished | May 26 03:16:56 PM PDT 24 |
| Peak memory | 366968 kb |
| Host | smart-283ca022-874f-41e9-adc3-0882f0b3a2c1 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742732735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.3742732735 |
| Directory | /workspace/42.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3244712666 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 51009173353 ps |
| CPU time | 337.06 seconds |
| Started | May 26 03:14:47 PM PDT 24 |
| Finished | May 26 03:20:24 PM PDT 24 |
| Peak memory | 202436 kb |
| Host | smart-8d002202-7949-4257-87bc-63a711097756 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244712666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.3244712666 |
| Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.3055703958 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 346460015 ps |
| CPU time | 3.37 seconds |
| Started | May 26 03:15:02 PM PDT 24 |
| Finished | May 26 03:15:06 PM PDT 24 |
| Peak memory | 202552 kb |
| Host | smart-e854f12a-92fc-44cb-93e5-1c444e8a215c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055703958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3055703958 |
| Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_regwen.4094449275 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 7265074248 ps |
| CPU time | 312.76 seconds |
| Started | May 26 03:15:02 PM PDT 24 |
| Finished | May 26 03:20:15 PM PDT 24 |
| Peak memory | 369112 kb |
| Host | smart-9a8312f1-c322-4207-a459-7021d471d65d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094449275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.4094449275 |
| Directory | /workspace/42.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_smoke.2166534727 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 8354172774 ps |
| CPU time | 124.68 seconds |
| Started | May 26 03:14:37 PM PDT 24 |
| Finished | May 26 03:16:42 PM PDT 24 |
| Peak memory | 340448 kb |
| Host | smart-92b40dbc-63ba-4d10-8b45-5585ea5f5332 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166534727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2166534727 |
| Directory | /workspace/42.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2860142289 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 17779026744 ps |
| CPU time | 269.93 seconds |
| Started | May 26 03:14:45 PM PDT 24 |
| Finished | May 26 03:19:16 PM PDT 24 |
| Peak memory | 210716 kb |
| Host | smart-237c570c-e8a1-4a34-a0a9-b1b16b891539 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860142289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.2860142289 |
| Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1090787813 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3056707176 ps |
| CPU time | 16.59 seconds |
| Started | May 26 03:14:57 PM PDT 24 |
| Finished | May 26 03:15:14 PM PDT 24 |
| Peak memory | 251560 kb |
| Host | smart-f04666b4-8c07-4e85-a246-53e9e0cc0d66 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090787813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.1090787813 |
| Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.3280859525 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 32481852 ps |
| CPU time | 0.69 seconds |
| Started | May 26 03:15:18 PM PDT 24 |
| Finished | May 26 03:15:19 PM PDT 24 |
| Peak memory | 201556 kb |
| Host | smart-d102d263-cebf-4a47-87a8-9c9e4b68c0b0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280859525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.3280859525 |
| Directory | /workspace/43.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_bijection.4282458870 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 71590591560 ps |
| CPU time | 2491.61 seconds |
| Started | May 26 03:15:08 PM PDT 24 |
| Finished | May 26 03:56:41 PM PDT 24 |
| Peak memory | 210620 kb |
| Host | smart-10998c62-5e7e-4141-87a4-5fbb0139ec84 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282458870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .4282458870 |
| Directory | /workspace/43.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_executable.4288513891 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 20885005020 ps |
| CPU time | 1181.63 seconds |
| Started | May 26 03:15:15 PM PDT 24 |
| Finished | May 26 03:34:58 PM PDT 24 |
| Peak memory | 378460 kb |
| Host | smart-efa9530d-766e-4146-b2cb-94b2dd52cf61 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288513891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.4288513891 |
| Directory | /workspace/43.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.1977037881 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 11076329204 ps |
| CPU time | 65.53 seconds |
| Started | May 26 03:15:08 PM PDT 24 |
| Finished | May 26 03:16:14 PM PDT 24 |
| Peak memory | 210716 kb |
| Host | smart-a71c39d6-70f6-4f9f-8c8a-c25b7c81c523 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977037881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.1977037881 |
| Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.2886102633 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 15107196302 ps |
| CPU time | 106.64 seconds |
| Started | May 26 03:15:08 PM PDT 24 |
| Finished | May 26 03:16:55 PM PDT 24 |
| Peak memory | 359936 kb |
| Host | smart-45b0b838-9ab7-4c8f-bcbb-63b5b41ff8aa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886102633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.2886102633 |
| Directory | /workspace/43.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2140795417 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1664515668 ps |
| CPU time | 133.67 seconds |
| Started | May 26 03:15:17 PM PDT 24 |
| Finished | May 26 03:17:31 PM PDT 24 |
| Peak memory | 215216 kb |
| Host | smart-43730ddc-ad42-4cb2-85a6-c761a2d70ea2 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140795417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.2140795417 |
| Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.326874826 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 10567191404 ps |
| CPU time | 171.4 seconds |
| Started | May 26 03:15:18 PM PDT 24 |
| Finished | May 26 03:18:10 PM PDT 24 |
| Peak memory | 202444 kb |
| Host | smart-83cf1634-19bc-451a-892b-b41a8530818f |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326874826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _mem_walk.326874826 |
| Directory | /workspace/43.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.2747966532 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 8770818070 ps |
| CPU time | 1484.28 seconds |
| Started | May 26 03:15:09 PM PDT 24 |
| Finished | May 26 03:39:54 PM PDT 24 |
| Peak memory | 379400 kb |
| Host | smart-046f9fb6-f710-4131-9ae4-5306706fc39a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747966532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.2747966532 |
| Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.3095874904 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 795586882 ps |
| CPU time | 41.48 seconds |
| Started | May 26 03:15:09 PM PDT 24 |
| Finished | May 26 03:15:51 PM PDT 24 |
| Peak memory | 285356 kb |
| Host | smart-2b080e3b-270a-45b9-ac12-7c23286064a1 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095874904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.3095874904 |
| Directory | /workspace/43.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4083803008 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 7788902561 ps |
| CPU time | 363.1 seconds |
| Started | May 26 03:15:10 PM PDT 24 |
| Finished | May 26 03:21:13 PM PDT 24 |
| Peak memory | 202476 kb |
| Host | smart-e486b6bc-25e9-489d-8fd1-bb223e5e3fb2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083803008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.4083803008 |
| Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.99665739 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1302216692 ps |
| CPU time | 3.56 seconds |
| Started | May 26 03:15:22 PM PDT 24 |
| Finished | May 26 03:15:26 PM PDT 24 |
| Peak memory | 202552 kb |
| Host | smart-ef5e895d-9bfc-4045-b80a-af1a872ae272 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99665739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.99665739 |
| Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_regwen.761666675 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 13970332736 ps |
| CPU time | 299.16 seconds |
| Started | May 26 03:15:23 PM PDT 24 |
| Finished | May 26 03:20:23 PM PDT 24 |
| Peak memory | 358716 kb |
| Host | smart-fbde4829-ecac-4148-a7e2-68f97bf41edb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761666675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.761666675 |
| Directory | /workspace/43.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_smoke.4200648884 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 7301215240 ps |
| CPU time | 23 seconds |
| Started | May 26 03:15:09 PM PDT 24 |
| Finished | May 26 03:15:33 PM PDT 24 |
| Peak memory | 210732 kb |
| Host | smart-285e65de-2910-4f62-9514-e6cf3e3b74e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200648884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.4200648884 |
| Directory | /workspace/43.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3866431513 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 22058338009 ps |
| CPU time | 228.35 seconds |
| Started | May 26 03:15:08 PM PDT 24 |
| Finished | May 26 03:18:57 PM PDT 24 |
| Peak memory | 202456 kb |
| Host | smart-5d7759dd-44a2-4872-8093-79a94bcacb64 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866431513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.3866431513 |
| Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3560124471 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 724497602 ps |
| CPU time | 18.57 seconds |
| Started | May 26 03:15:09 PM PDT 24 |
| Finished | May 26 03:15:28 PM PDT 24 |
| Peak memory | 251460 kb |
| Host | smart-b6b62188-6544-47cf-959d-29712ecc90a8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560124471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.3560124471 |
| Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.3351094783 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 42364608 ps |
| CPU time | 0.65 seconds |
| Started | May 26 03:15:34 PM PDT 24 |
| Finished | May 26 03:15:35 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-5dc8661d-9fbe-4789-9f36-a52a00f3baae |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351094783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.3351094783 |
| Directory | /workspace/44.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_bijection.3441330540 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 166671002344 ps |
| CPU time | 805.44 seconds |
| Started | May 26 03:15:20 PM PDT 24 |
| Finished | May 26 03:28:46 PM PDT 24 |
| Peak memory | 203188 kb |
| Host | smart-b4cb939d-bf81-4488-9fa9-52b91ec04913 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441330540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .3441330540 |
| Directory | /workspace/44.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.1933150047 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 20323314820 ps |
| CPU time | 29.89 seconds |
| Started | May 26 03:15:33 PM PDT 24 |
| Finished | May 26 03:16:03 PM PDT 24 |
| Peak memory | 210652 kb |
| Host | smart-85b5128b-364a-4c21-bfcd-bb5dbc9db5ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933150047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.1933150047 |
| Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.2759514464 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 711920755 ps |
| CPU time | 6.79 seconds |
| Started | May 26 03:15:24 PM PDT 24 |
| Finished | May 26 03:15:32 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-c2573b95-33c4-4363-9d94-c2d3ea7c7162 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759514464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.2759514464 |
| Directory | /workspace/44.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1478860392 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 7509067287 ps |
| CPU time | 127.91 seconds |
| Started | May 26 03:15:33 PM PDT 24 |
| Finished | May 26 03:17:41 PM PDT 24 |
| Peak memory | 216060 kb |
| Host | smart-99922308-d00c-4ec2-aed7-cf38dfa2f806 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478860392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.1478860392 |
| Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.1631368177 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 55356315343 ps |
| CPU time | 323.49 seconds |
| Started | May 26 03:15:47 PM PDT 24 |
| Finished | May 26 03:21:11 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-700e5265-3790-4457-94d2-bfbb4c3ac73a |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631368177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1631368177 |
| Directory | /workspace/44.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.722879239 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 38282078068 ps |
| CPU time | 633.53 seconds |
| Started | May 26 03:15:22 PM PDT 24 |
| Finished | May 26 03:25:56 PM PDT 24 |
| Peak memory | 376388 kb |
| Host | smart-f36cd4e7-2ea4-43c3-a047-34915f0f27e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722879239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multip le_keys.722879239 |
| Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.3961117405 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 5045726936 ps |
| CPU time | 24.43 seconds |
| Started | May 26 03:15:24 PM PDT 24 |
| Finished | May 26 03:15:50 PM PDT 24 |
| Peak memory | 210656 kb |
| Host | smart-d43387ce-92bc-491a-994d-0e3a1aa665eb |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961117405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.3961117405 |
| Directory | /workspace/44.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2695374757 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 6956988621 ps |
| CPU time | 393.68 seconds |
| Started | May 26 03:15:23 PM PDT 24 |
| Finished | May 26 03:21:57 PM PDT 24 |
| Peak memory | 210668 kb |
| Host | smart-bfd59da7-1799-4d0c-9242-2098b4da24a1 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695374757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.2695374757 |
| Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.2323449535 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 344843384 ps |
| CPU time | 3.31 seconds |
| Started | May 26 03:15:32 PM PDT 24 |
| Finished | May 26 03:15:36 PM PDT 24 |
| Peak memory | 202536 kb |
| Host | smart-fe2c9770-b138-4985-822f-4ed8e337d1cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323449535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2323449535 |
| Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_smoke.2388338377 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 835295745 ps |
| CPU time | 11.02 seconds |
| Started | May 26 03:15:17 PM PDT 24 |
| Finished | May 26 03:15:29 PM PDT 24 |
| Peak memory | 210640 kb |
| Host | smart-50dc040c-3595-4fad-8916-fafb495f7a4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388338377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2388338377 |
| Directory | /workspace/44.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2217768347 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 322251204 ps |
| CPU time | 11.73 seconds |
| Started | May 26 03:15:33 PM PDT 24 |
| Finished | May 26 03:15:46 PM PDT 24 |
| Peak memory | 210752 kb |
| Host | smart-0cfc70d1-ace6-47e6-aa7f-b66bcade787c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2217768347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2217768347 |
| Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.4028466276 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 17360541751 ps |
| CPU time | 250.21 seconds |
| Started | May 26 03:15:24 PM PDT 24 |
| Finished | May 26 03:19:35 PM PDT 24 |
| Peak memory | 210716 kb |
| Host | smart-324d4771-631c-4291-970f-84866051ba6d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028466276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.4028466276 |
| Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1047638004 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1483363091 ps |
| CPU time | 17.91 seconds |
| Started | May 26 03:15:22 PM PDT 24 |
| Finished | May 26 03:15:40 PM PDT 24 |
| Peak memory | 255812 kb |
| Host | smart-b32fdd17-3db5-4651-8624-e0c380772750 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047638004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1047638004 |
| Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1764359196 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 4938094621 ps |
| CPU time | 33.05 seconds |
| Started | May 26 03:15:52 PM PDT 24 |
| Finished | May 26 03:16:26 PM PDT 24 |
| Peak memory | 247368 kb |
| Host | smart-95c1deb6-8518-4889-a69e-69bcfe9fa940 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764359196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.1764359196 |
| Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.898187252 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 35666422 ps |
| CPU time | 0.7 seconds |
| Started | May 26 03:15:58 PM PDT 24 |
| Finished | May 26 03:16:00 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-5365e509-61a5-45ae-9ef2-ba7593820c94 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898187252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.898187252 |
| Directory | /workspace/45.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_bijection.553888593 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 128099813506 ps |
| CPU time | 1503.64 seconds |
| Started | May 26 03:15:41 PM PDT 24 |
| Finished | May 26 03:40:45 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-e484cfab-5f36-43ca-b637-90ac38dc51a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553888593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection. 553888593 |
| Directory | /workspace/45.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_executable.3233702728 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 318231786574 ps |
| CPU time | 907.07 seconds |
| Started | May 26 03:15:53 PM PDT 24 |
| Finished | May 26 03:31:01 PM PDT 24 |
| Peak memory | 364888 kb |
| Host | smart-eab9d86d-df17-45ea-a7c0-52a8a84fa50b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233702728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.3233702728 |
| Directory | /workspace/45.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.2939065168 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4920745946 ps |
| CPU time | 29.6 seconds |
| Started | May 26 03:15:47 PM PDT 24 |
| Finished | May 26 03:16:17 PM PDT 24 |
| Peak memory | 210700 kb |
| Host | smart-e7901a78-0ca6-4387-84d8-a920ff42ebfc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939065168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.2939065168 |
| Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.484985246 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1443182014 ps |
| CPU time | 26.31 seconds |
| Started | May 26 03:15:46 PM PDT 24 |
| Finished | May 26 03:16:13 PM PDT 24 |
| Peak memory | 267828 kb |
| Host | smart-814a4f17-ae96-4f83-aa35-214bd80ba80d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484985246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.sram_ctrl_max_throughput.484985246 |
| Directory | /workspace/45.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1720706187 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 18126604270 ps |
| CPU time | 167.25 seconds |
| Started | May 26 03:15:52 PM PDT 24 |
| Finished | May 26 03:18:40 PM PDT 24 |
| Peak memory | 218664 kb |
| Host | smart-fe2a450f-073f-42b5-afa4-daacb9194ff0 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720706187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.1720706187 |
| Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.3584215106 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 15755181568 ps |
| CPU time | 235.62 seconds |
| Started | May 26 03:15:54 PM PDT 24 |
| Finished | May 26 03:19:50 PM PDT 24 |
| Peak memory | 210632 kb |
| Host | smart-4874c579-7d4e-491c-85b0-a6332fbbeb3b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584215106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.3584215106 |
| Directory | /workspace/45.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.4002625047 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 43088815884 ps |
| CPU time | 532.91 seconds |
| Started | May 26 03:15:37 PM PDT 24 |
| Finished | May 26 03:24:31 PM PDT 24 |
| Peak memory | 377364 kb |
| Host | smart-4b1756f2-1aed-42d4-80aa-f172e7a04fd2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002625047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.4002625047 |
| Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.4134602719 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 917935912 ps |
| CPU time | 26.64 seconds |
| Started | May 26 03:15:40 PM PDT 24 |
| Finished | May 26 03:16:07 PM PDT 24 |
| Peak memory | 265780 kb |
| Host | smart-29cbeb7c-7b92-46f2-9127-5c8b5f501746 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134602719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.4134602719 |
| Directory | /workspace/45.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2054846040 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 81427366748 ps |
| CPU time | 405.05 seconds |
| Started | May 26 03:15:40 PM PDT 24 |
| Finished | May 26 03:22:25 PM PDT 24 |
| Peak memory | 202472 kb |
| Host | smart-6d28ef79-2c6d-4f6c-af31-b830bfe73f19 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054846040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.2054846040 |
| Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.3549740465 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 757954883 ps |
| CPU time | 3.33 seconds |
| Started | May 26 03:15:52 PM PDT 24 |
| Finished | May 26 03:15:56 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-16ac330c-74fa-4419-8402-2089025061b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549740465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3549740465 |
| Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_regwen.98231808 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 10318125439 ps |
| CPU time | 1160.86 seconds |
| Started | May 26 03:15:54 PM PDT 24 |
| Finished | May 26 03:35:16 PM PDT 24 |
| Peak memory | 370256 kb |
| Host | smart-275e65e0-deaa-4dc1-b6b8-60bad24a2d59 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98231808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.98231808 |
| Directory | /workspace/45.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_smoke.3948294600 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 458946287 ps |
| CPU time | 10.2 seconds |
| Started | May 26 03:15:34 PM PDT 24 |
| Finished | May 26 03:15:45 PM PDT 24 |
| Peak memory | 210676 kb |
| Host | smart-0b3d0ad2-f7bd-4624-a3b2-35bcdce1df88 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948294600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3948294600 |
| Directory | /workspace/45.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3931056356 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 19127219466 ps |
| CPU time | 186.96 seconds |
| Started | May 26 03:15:41 PM PDT 24 |
| Finished | May 26 03:18:48 PM PDT 24 |
| Peak memory | 202528 kb |
| Host | smart-87a0d40b-ead0-4ae4-be66-888da4cd0a6e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931056356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.3931056356 |
| Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2718907272 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3265669201 ps |
| CPU time | 167.47 seconds |
| Started | May 26 03:15:47 PM PDT 24 |
| Finished | May 26 03:18:35 PM PDT 24 |
| Peak memory | 371172 kb |
| Host | smart-2aa12807-bfac-495c-ad2d-0df190d52f52 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718907272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.2718907272 |
| Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.201586615 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 12035446 ps |
| CPU time | 0.66 seconds |
| Started | May 26 03:16:13 PM PDT 24 |
| Finished | May 26 03:16:14 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-3ffbefdd-ca55-487f-85be-381bb3b8a3d5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201586615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.201586615 |
| Directory | /workspace/46.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_bijection.1088964184 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 109264267969 ps |
| CPU time | 1923.23 seconds |
| Started | May 26 03:16:09 PM PDT 24 |
| Finished | May 26 03:48:13 PM PDT 24 |
| Peak memory | 210712 kb |
| Host | smart-402883fc-b635-4346-bc2f-d877b00065b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088964184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .1088964184 |
| Directory | /workspace/46.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_executable.4211784790 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 252259727239 ps |
| CPU time | 957.8 seconds |
| Started | May 26 03:16:06 PM PDT 24 |
| Finished | May 26 03:32:05 PM PDT 24 |
| Peak memory | 377652 kb |
| Host | smart-4927d0a1-4faf-4821-9f5a-59281946d3e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211784790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.4211784790 |
| Directory | /workspace/46.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.1445724437 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 26460600026 ps |
| CPU time | 83.87 seconds |
| Started | May 26 03:16:09 PM PDT 24 |
| Finished | May 26 03:17:33 PM PDT 24 |
| Peak memory | 202484 kb |
| Host | smart-45600ef3-9b4a-4a02-af24-1119b6955090 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445724437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.1445724437 |
| Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.3420617049 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3267829627 ps |
| CPU time | 44.47 seconds |
| Started | May 26 03:16:08 PM PDT 24 |
| Finished | May 26 03:16:53 PM PDT 24 |
| Peak memory | 287300 kb |
| Host | smart-06e13dc2-3d6b-4dec-a2d5-cd8f993452e0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420617049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.3420617049 |
| Directory | /workspace/46.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1257984795 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 5492834553 ps |
| CPU time | 135.74 seconds |
| Started | May 26 03:16:13 PM PDT 24 |
| Finished | May 26 03:18:29 PM PDT 24 |
| Peak memory | 215932 kb |
| Host | smart-3affec8f-f026-43de-9cb6-65a76d242fd1 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257984795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.1257984795 |
| Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.2116261785 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 56271886074 ps |
| CPU time | 259.94 seconds |
| Started | May 26 03:16:06 PM PDT 24 |
| Finished | May 26 03:20:27 PM PDT 24 |
| Peak memory | 210596 kb |
| Host | smart-48f030b3-f75d-42b3-b9cd-149bb20fa9e4 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116261785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.2116261785 |
| Directory | /workspace/46.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.3426300973 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 16505558060 ps |
| CPU time | 225.07 seconds |
| Started | May 26 03:16:00 PM PDT 24 |
| Finished | May 26 03:19:45 PM PDT 24 |
| Peak memory | 379104 kb |
| Host | smart-8bb38673-e6a3-41cf-9aab-4165b15d9bc3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426300973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.3426300973 |
| Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3358432217 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 11212528810 ps |
| CPU time | 255.6 seconds |
| Started | May 26 03:16:06 PM PDT 24 |
| Finished | May 26 03:20:22 PM PDT 24 |
| Peak memory | 202452 kb |
| Host | smart-b0602360-4afd-4edb-9c0b-042e36b29f6d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358432217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.3358432217 |
| Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.1194576763 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 355345242 ps |
| CPU time | 3.11 seconds |
| Started | May 26 03:16:06 PM PDT 24 |
| Finished | May 26 03:16:10 PM PDT 24 |
| Peak memory | 202556 kb |
| Host | smart-50a9a044-0c16-48e3-a317-01e754d37801 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194576763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1194576763 |
| Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_regwen.674366449 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 1727931146 ps |
| CPU time | 607.24 seconds |
| Started | May 26 03:16:06 PM PDT 24 |
| Finished | May 26 03:26:15 PM PDT 24 |
| Peak memory | 378288 kb |
| Host | smart-e55eecc4-1644-469a-b6ce-3988f0684ad2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674366449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.674366449 |
| Directory | /workspace/46.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_smoke.1303951974 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 919592298 ps |
| CPU time | 130.61 seconds |
| Started | May 26 03:15:59 PM PDT 24 |
| Finished | May 26 03:18:10 PM PDT 24 |
| Peak memory | 350672 kb |
| Host | smart-e8cc4a8a-3354-43a0-8a7b-f21062a24bf3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303951974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1303951974 |
| Directory | /workspace/46.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3067679755 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 7148659829 ps |
| CPU time | 361.98 seconds |
| Started | May 26 03:16:06 PM PDT 24 |
| Finished | May 26 03:22:09 PM PDT 24 |
| Peak memory | 210612 kb |
| Host | smart-0b8ac683-bcae-4ff8-806f-48f03c489941 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067679755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.3067679755 |
| Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4115913104 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 687900401 ps |
| CPU time | 7.38 seconds |
| Started | May 26 03:16:07 PM PDT 24 |
| Finished | May 26 03:16:15 PM PDT 24 |
| Peak memory | 218696 kb |
| Host | smart-bba1ca43-2530-43fc-a95b-0e57710c81a9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115913104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.4115913104 |
| Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.4273347284 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 17172698 ps |
| CPU time | 0.68 seconds |
| Started | May 26 03:16:27 PM PDT 24 |
| Finished | May 26 03:16:28 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-59ca2e23-d043-467c-b8ad-63bc01a67d58 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273347284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.4273347284 |
| Directory | /workspace/47.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_bijection.4016039276 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 151049862701 ps |
| CPU time | 1929.47 seconds |
| Started | May 26 03:16:11 PM PDT 24 |
| Finished | May 26 03:48:22 PM PDT 24 |
| Peak memory | 210656 kb |
| Host | smart-604d0942-230d-4f88-b312-45ae3a4e9036 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016039276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .4016039276 |
| Directory | /workspace/47.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_executable.1543650173 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 176163011542 ps |
| CPU time | 1024 seconds |
| Started | May 26 03:16:26 PM PDT 24 |
| Finished | May 26 03:33:31 PM PDT 24 |
| Peak memory | 371396 kb |
| Host | smart-71b66e74-6008-42cc-9189-d3b5f54894ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543650173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.1543650173 |
| Directory | /workspace/47.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.237078752 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 21400537005 ps |
| CPU time | 42.72 seconds |
| Started | May 26 03:16:20 PM PDT 24 |
| Finished | May 26 03:17:04 PM PDT 24 |
| Peak memory | 202536 kb |
| Host | smart-5505af4a-2d62-4d61-a0c3-11262307a16a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237078752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esc alation.237078752 |
| Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.2519363444 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2994796219 ps |
| CPU time | 95.99 seconds |
| Started | May 26 03:16:21 PM PDT 24 |
| Finished | May 26 03:17:58 PM PDT 24 |
| Peak memory | 337468 kb |
| Host | smart-1f3c71b9-d4bc-49b5-93b0-cdad349e312e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519363444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.2519363444 |
| Directory | /workspace/47.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1488437698 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1005340651 ps |
| CPU time | 72.43 seconds |
| Started | May 26 03:16:27 PM PDT 24 |
| Finished | May 26 03:17:40 PM PDT 24 |
| Peak memory | 212956 kb |
| Host | smart-fbec8c7c-3b3e-41c6-841a-20a38ea58a84 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488437698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.1488437698 |
| Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.2913931888 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 66473697440 ps |
| CPU time | 345.93 seconds |
| Started | May 26 03:16:28 PM PDT 24 |
| Finished | May 26 03:22:14 PM PDT 24 |
| Peak memory | 210620 kb |
| Host | smart-7ac0f2ff-76c2-4946-91f9-7e7aa7fcbdcd |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913931888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.2913931888 |
| Directory | /workspace/47.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.3104759789 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 155168067590 ps |
| CPU time | 692.54 seconds |
| Started | May 26 03:16:12 PM PDT 24 |
| Finished | May 26 03:27:45 PM PDT 24 |
| Peak memory | 340536 kb |
| Host | smart-4c267e12-aa4b-401e-8af2-ed2616057dd8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104759789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.3104759789 |
| Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.2779964326 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 651894960 ps |
| CPU time | 29.09 seconds |
| Started | May 26 03:16:21 PM PDT 24 |
| Finished | May 26 03:16:51 PM PDT 24 |
| Peak memory | 279136 kb |
| Host | smart-06266163-5805-4d2f-8d6e-d6655150f058 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779964326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.2779964326 |
| Directory | /workspace/47.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3852813264 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 55734069997 ps |
| CPU time | 421.23 seconds |
| Started | May 26 03:16:20 PM PDT 24 |
| Finished | May 26 03:23:22 PM PDT 24 |
| Peak memory | 210684 kb |
| Host | smart-87a0cc1c-17d8-4caa-a1e0-78e3e5bc7869 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852813264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.3852813264 |
| Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.3405268114 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 364233458 ps |
| CPU time | 3.33 seconds |
| Started | May 26 03:16:26 PM PDT 24 |
| Finished | May 26 03:16:30 PM PDT 24 |
| Peak memory | 202544 kb |
| Host | smart-5a1aeddb-e96e-4b3d-80e1-451cfeadbaca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405268114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3405268114 |
| Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_regwen.2283939018 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3416884346 ps |
| CPU time | 1177.4 seconds |
| Started | May 26 03:16:27 PM PDT 24 |
| Finished | May 26 03:36:05 PM PDT 24 |
| Peak memory | 376392 kb |
| Host | smart-c6b206e1-b73b-42b0-9ece-e3783c25383b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283939018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2283939018 |
| Directory | /workspace/47.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_smoke.3380100993 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 954591651 ps |
| CPU time | 131.01 seconds |
| Started | May 26 03:16:13 PM PDT 24 |
| Finished | May 26 03:18:24 PM PDT 24 |
| Peak memory | 352708 kb |
| Host | smart-8b046a12-e0bc-4f43-a4a8-a5ec56d50614 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380100993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3380100993 |
| Directory | /workspace/47.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.922818467 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1215404918 ps |
| CPU time | 12.23 seconds |
| Started | May 26 03:16:26 PM PDT 24 |
| Finished | May 26 03:16:39 PM PDT 24 |
| Peak memory | 210688 kb |
| Host | smart-6205b505-5b89-450a-b114-2783c3c9ffd2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=922818467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.922818467 |
| Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2113108864 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 25888383210 ps |
| CPU time | 282.29 seconds |
| Started | May 26 03:16:21 PM PDT 24 |
| Finished | May 26 03:21:04 PM PDT 24 |
| Peak memory | 202448 kb |
| Host | smart-fdbc582a-dddb-42fe-ba07-d276141e03f5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113108864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.2113108864 |
| Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2258169531 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1514330829 ps |
| CPU time | 78.9 seconds |
| Started | May 26 03:16:21 PM PDT 24 |
| Finished | May 26 03:17:40 PM PDT 24 |
| Peak memory | 326148 kb |
| Host | smart-4cd1921b-c024-4c85-bb50-bd936843008d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258169531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.2258169531 |
| Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.2271164418 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 21562232 ps |
| CPU time | 0.68 seconds |
| Started | May 26 03:16:48 PM PDT 24 |
| Finished | May 26 03:16:49 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-1df95787-8040-4264-9b27-9fa64e515b89 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271164418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.2271164418 |
| Directory | /workspace/48.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_bijection.1845551453 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 84160503874 ps |
| CPU time | 2152.16 seconds |
| Started | May 26 03:16:35 PM PDT 24 |
| Finished | May 26 03:52:28 PM PDT 24 |
| Peak memory | 210692 kb |
| Host | smart-1337ded8-bbe8-4372-b0ce-8d3b7cf32441 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845551453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .1845551453 |
| Directory | /workspace/48.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_executable.4135988576 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 25552557353 ps |
| CPU time | 995.78 seconds |
| Started | May 26 03:16:47 PM PDT 24 |
| Finished | May 26 03:33:24 PM PDT 24 |
| Peak memory | 379460 kb |
| Host | smart-cf396aaf-a583-4ebe-8fbc-56f6b6e90a18 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135988576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.4135988576 |
| Directory | /workspace/48.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.61415167 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1290470559 ps |
| CPU time | 7.71 seconds |
| Started | May 26 03:16:39 PM PDT 24 |
| Finished | May 26 03:16:47 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-1f400fb6-c589-4f60-94ec-5ba9a74476c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61415167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_esca lation.61415167 |
| Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.3594612282 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 797212151 ps |
| CPU time | 115.65 seconds |
| Started | May 26 03:16:39 PM PDT 24 |
| Finished | May 26 03:18:35 PM PDT 24 |
| Peak memory | 351556 kb |
| Host | smart-1cda0a87-6bea-4cdf-902d-2d1b6365c238 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594612282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.3594612282 |
| Directory | /workspace/48.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2610711029 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 10503188553 ps |
| CPU time | 132.19 seconds |
| Started | May 26 03:16:45 PM PDT 24 |
| Finished | May 26 03:18:58 PM PDT 24 |
| Peak memory | 215996 kb |
| Host | smart-62da3924-2e47-4737-b7ff-09c3a46e9151 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610711029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.2610711029 |
| Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.4109006514 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 27715186238 ps |
| CPU time | 165.04 seconds |
| Started | May 26 03:16:45 PM PDT 24 |
| Finished | May 26 03:19:31 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-44046e44-30f7-4ec9-ac05-5faa23d7368e |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109006514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.4109006514 |
| Directory | /workspace/48.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.3280268847 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 24025561561 ps |
| CPU time | 565.61 seconds |
| Started | May 26 03:16:34 PM PDT 24 |
| Finished | May 26 03:26:00 PM PDT 24 |
| Peak memory | 377280 kb |
| Host | smart-8154fa90-aa12-4e52-885c-7b43c9692881 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280268847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.3280268847 |
| Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.1293577365 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 3123905947 ps |
| CPU time | 13.02 seconds |
| Started | May 26 03:16:32 PM PDT 24 |
| Finished | May 26 03:16:45 PM PDT 24 |
| Peak memory | 229824 kb |
| Host | smart-dc050c3f-b408-4496-aaea-3f232c1115d6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293577365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.1293577365 |
| Directory | /workspace/48.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3199177012 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 19409664647 ps |
| CPU time | 492.33 seconds |
| Started | May 26 03:16:35 PM PDT 24 |
| Finished | May 26 03:24:47 PM PDT 24 |
| Peak memory | 202500 kb |
| Host | smart-2192e1a4-b4af-4529-8029-89ec90c48104 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199177012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.3199177012 |
| Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.481761365 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1083570509 ps |
| CPU time | 3.28 seconds |
| Started | May 26 03:16:45 PM PDT 24 |
| Finished | May 26 03:16:49 PM PDT 24 |
| Peak memory | 202540 kb |
| Host | smart-37c90d92-c644-47ea-b743-812f01bfce17 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481761365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.481761365 |
| Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_regwen.1947604398 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 44842234442 ps |
| CPU time | 661.48 seconds |
| Started | May 26 03:16:47 PM PDT 24 |
| Finished | May 26 03:27:49 PM PDT 24 |
| Peak memory | 360720 kb |
| Host | smart-78e0dea8-c824-4025-a53e-cb67e53d1900 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947604398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1947604398 |
| Directory | /workspace/48.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_smoke.318801529 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4352490023 ps |
| CPU time | 23.06 seconds |
| Started | May 26 03:16:26 PM PDT 24 |
| Finished | May 26 03:16:49 PM PDT 24 |
| Peak memory | 210668 kb |
| Host | smart-45fac415-ecf6-4f97-96e3-e4ad5a308cf0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318801529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.318801529 |
| Directory | /workspace/48.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.4238708279 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 4877056592 ps |
| CPU time | 208.18 seconds |
| Started | May 26 03:16:35 PM PDT 24 |
| Finished | May 26 03:20:04 PM PDT 24 |
| Peak memory | 202532 kb |
| Host | smart-9cd054df-0136-4126-bf01-565f048e4140 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238708279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.4238708279 |
| Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3348079534 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 3185396136 ps |
| CPU time | 113.04 seconds |
| Started | May 26 03:16:41 PM PDT 24 |
| Finished | May 26 03:18:34 PM PDT 24 |
| Peak memory | 344596 kb |
| Host | smart-8682c03e-840d-448a-a984-dbe8fcf59602 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348079534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3348079534 |
| Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.1252881614 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 21918183 ps |
| CPU time | 0.63 seconds |
| Started | May 26 03:17:12 PM PDT 24 |
| Finished | May 26 03:17:13 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-e26b8dbe-a8af-418e-a760-628178d0df7f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252881614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.1252881614 |
| Directory | /workspace/49.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_bijection.568595860 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 106284277428 ps |
| CPU time | 2864.86 seconds |
| Started | May 26 03:16:52 PM PDT 24 |
| Finished | May 26 04:04:38 PM PDT 24 |
| Peak memory | 210700 kb |
| Host | smart-fb3e2766-9b97-4125-8dcc-a009f9dc60f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568595860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection. 568595860 |
| Directory | /workspace/49.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_executable.1672465536 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 77932298205 ps |
| CPU time | 1394.39 seconds |
| Started | May 26 03:17:01 PM PDT 24 |
| Finished | May 26 03:40:16 PM PDT 24 |
| Peak memory | 379436 kb |
| Host | smart-b63cf2ab-ffc0-46a0-b7da-332dc1e73334 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672465536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.1672465536 |
| Directory | /workspace/49.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.2611548313 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 10075070781 ps |
| CPU time | 56.23 seconds |
| Started | May 26 03:17:00 PM PDT 24 |
| Finished | May 26 03:17:57 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-0375f25a-81a2-4c9f-8f35-8f8554a5b0b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611548313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.2611548313 |
| Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.2978361257 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1532731197 ps |
| CPU time | 123.12 seconds |
| Started | May 26 03:16:57 PM PDT 24 |
| Finished | May 26 03:19:00 PM PDT 24 |
| Peak memory | 368960 kb |
| Host | smart-6780bc21-3c1f-45d7-97ad-bf4b1cd83678 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978361257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.2978361257 |
| Directory | /workspace/49.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.632588696 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 9895013284 ps |
| CPU time | 86.78 seconds |
| Started | May 26 03:17:12 PM PDT 24 |
| Finished | May 26 03:18:39 PM PDT 24 |
| Peak memory | 213480 kb |
| Host | smart-6715a27b-c879-4ebd-a6b0-f3d2fb30207d |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632588696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sram_ctrl_mem_partial_access.632588696 |
| Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.3106404233 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 7891681830 ps |
| CPU time | 132 seconds |
| Started | May 26 03:17:10 PM PDT 24 |
| Finished | May 26 03:19:22 PM PDT 24 |
| Peak memory | 210596 kb |
| Host | smart-4c5fcd1c-e1bc-4d70-aacd-6deebc2df0fc |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106404233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.3106404233 |
| Directory | /workspace/49.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.4227440813 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 17397762381 ps |
| CPU time | 529.38 seconds |
| Started | May 26 03:16:53 PM PDT 24 |
| Finished | May 26 03:25:43 PM PDT 24 |
| Peak memory | 342612 kb |
| Host | smart-b1c58c9c-5b41-4f0c-9fd6-4384be189553 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227440813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.4227440813 |
| Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.2831521417 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 422491061 ps |
| CPU time | 7.83 seconds |
| Started | May 26 03:16:51 PM PDT 24 |
| Finished | May 26 03:16:59 PM PDT 24 |
| Peak memory | 210640 kb |
| Host | smart-7ae408de-8ead-4426-8ac3-19c87ea55dbe |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831521417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.2831521417 |
| Directory | /workspace/49.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2155737167 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 14330029798 ps |
| CPU time | 358.64 seconds |
| Started | May 26 03:16:57 PM PDT 24 |
| Finished | May 26 03:22:56 PM PDT 24 |
| Peak memory | 202472 kb |
| Host | smart-963224b0-9f76-4134-b6af-6c26a4e56c40 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155737167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.2155737167 |
| Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.516518702 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 348204172 ps |
| CPU time | 3.54 seconds |
| Started | May 26 03:17:02 PM PDT 24 |
| Finished | May 26 03:17:06 PM PDT 24 |
| Peak memory | 202536 kb |
| Host | smart-affcff9d-ee8a-4c67-b47c-b24fa215976c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516518702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.516518702 |
| Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_regwen.4096885657 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5472652140 ps |
| CPU time | 146.33 seconds |
| Started | May 26 03:17:02 PM PDT 24 |
| Finished | May 26 03:19:29 PM PDT 24 |
| Peak memory | 330284 kb |
| Host | smart-3f82cd14-c5b6-4b3a-b902-3b459981137b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096885657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.4096885657 |
| Directory | /workspace/49.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_smoke.3575955897 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 1792888626 ps |
| CPU time | 65.29 seconds |
| Started | May 26 03:16:58 PM PDT 24 |
| Finished | May 26 03:18:03 PM PDT 24 |
| Peak memory | 314740 kb |
| Host | smart-b1cbc1a5-cefa-41c0-80f1-737ba4c57179 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575955897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3575955897 |
| Directory | /workspace/49.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3376215807 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 5573793791 ps |
| CPU time | 292.22 seconds |
| Started | May 26 03:16:52 PM PDT 24 |
| Finished | May 26 03:21:45 PM PDT 24 |
| Peak memory | 210688 kb |
| Host | smart-056c7f06-6249-4a2e-a5de-e29a8ec6b6f0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376215807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.3376215807 |
| Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1894415219 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3088956797 ps |
| CPU time | 119.69 seconds |
| Started | May 26 03:16:51 PM PDT 24 |
| Finished | May 26 03:18:51 PM PDT 24 |
| Peak memory | 356884 kb |
| Host | smart-c4207445-5b21-417a-9f02-61aace3cdc3e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894415219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1894415219 |
| Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.2443012891 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 44373428 ps |
| CPU time | 0.69 seconds |
| Started | May 26 03:04:34 PM PDT 24 |
| Finished | May 26 03:04:35 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-d2e3584b-4ada-40df-9918-e067ba4f8616 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443012891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.2443012891 |
| Directory | /workspace/5.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_bijection.3941500252 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 101153220672 ps |
| CPU time | 1998 seconds |
| Started | May 26 03:04:07 PM PDT 24 |
| Finished | May 26 03:37:26 PM PDT 24 |
| Peak memory | 210660 kb |
| Host | smart-6f1645b5-4fff-42ca-aee3-82637c83a82a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941500252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 3941500252 |
| Directory | /workspace/5.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_executable.2216628057 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 24102831177 ps |
| CPU time | 850.4 seconds |
| Started | May 26 03:04:14 PM PDT 24 |
| Finished | May 26 03:18:25 PM PDT 24 |
| Peak memory | 372104 kb |
| Host | smart-344f9622-7dd1-465c-bdd7-91756e00bb58 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216628057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.2216628057 |
| Directory | /workspace/5.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.2727172461 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 7262546710 ps |
| CPU time | 34.74 seconds |
| Started | May 26 03:04:14 PM PDT 24 |
| Finished | May 26 03:04:49 PM PDT 24 |
| Peak memory | 202488 kb |
| Host | smart-1a1e6d1f-6d72-4a8d-be6d-c0394f17f7dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727172461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.2727172461 |
| Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.1277610323 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 3095129596 ps |
| CPU time | 65.42 seconds |
| Started | May 26 03:04:13 PM PDT 24 |
| Finished | May 26 03:05:19 PM PDT 24 |
| Peak memory | 311940 kb |
| Host | smart-49836138-7d79-4cce-a23a-3b1a47ec3486 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277610323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.1277610323 |
| Directory | /workspace/5.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.821755098 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 11786989278 ps |
| CPU time | 83.71 seconds |
| Started | May 26 03:04:34 PM PDT 24 |
| Finished | May 26 03:05:58 PM PDT 24 |
| Peak memory | 212684 kb |
| Host | smart-7d59d0d1-b74c-455c-9ff5-26ead981a7b2 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821755098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5. sram_ctrl_mem_partial_access.821755098 |
| Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.1394279823 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 172906536064 ps |
| CPU time | 328.56 seconds |
| Started | May 26 03:04:23 PM PDT 24 |
| Finished | May 26 03:09:52 PM PDT 24 |
| Peak memory | 210688 kb |
| Host | smart-e90c32a4-c118-40b4-8c07-cc4e64c21cc1 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394279823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.1394279823 |
| Directory | /workspace/5.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.1082162681 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3130140721 ps |
| CPU time | 225.34 seconds |
| Started | May 26 03:04:06 PM PDT 24 |
| Finished | May 26 03:07:52 PM PDT 24 |
| Peak memory | 374544 kb |
| Host | smart-4e4da536-15fd-4a03-8837-a8d65518ee3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082162681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.1082162681 |
| Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.1921497110 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2264326740 ps |
| CPU time | 9.58 seconds |
| Started | May 26 03:04:12 PM PDT 24 |
| Finished | May 26 03:04:23 PM PDT 24 |
| Peak memory | 231996 kb |
| Host | smart-d8b2b204-c7dd-48a1-8fa3-f65733574d98 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921497110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.1921497110 |
| Directory | /workspace/5.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4110161717 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 15537692933 ps |
| CPU time | 328.27 seconds |
| Started | May 26 03:04:13 PM PDT 24 |
| Finished | May 26 03:09:41 PM PDT 24 |
| Peak memory | 202488 kb |
| Host | smart-1a6b5d06-0b27-4667-bed0-5bb1ebe00678 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110161717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.4110161717 |
| Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.939467622 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 347108728 ps |
| CPU time | 3.24 seconds |
| Started | May 26 03:04:24 PM PDT 24 |
| Finished | May 26 03:04:28 PM PDT 24 |
| Peak memory | 202572 kb |
| Host | smart-73c0dec6-cf46-4841-9bd8-2c70577b033a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939467622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.939467622 |
| Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_regwen.2715368363 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 5340514984 ps |
| CPU time | 181.16 seconds |
| Started | May 26 03:04:34 PM PDT 24 |
| Finished | May 26 03:07:36 PM PDT 24 |
| Peak memory | 375436 kb |
| Host | smart-f781e0ea-5c24-4268-b86d-3a957742567f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715368363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2715368363 |
| Directory | /workspace/5.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_smoke.2271073195 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 4855008926 ps |
| CPU time | 17.36 seconds |
| Started | May 26 03:04:06 PM PDT 24 |
| Finished | May 26 03:04:24 PM PDT 24 |
| Peak memory | 202520 kb |
| Host | smart-b7cb9ce6-492e-491c-aa2d-0b989a323936 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271073195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2271073195 |
| Directory | /workspace/5.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.4256057822 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 22471423669 ps |
| CPU time | 280.65 seconds |
| Started | May 26 03:04:06 PM PDT 24 |
| Finished | May 26 03:08:48 PM PDT 24 |
| Peak memory | 210600 kb |
| Host | smart-ec55955f-753f-4494-b00e-811bde974f38 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256057822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.4256057822 |
| Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.893407259 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1108713641 ps |
| CPU time | 110.07 seconds |
| Started | May 26 03:04:17 PM PDT 24 |
| Finished | May 26 03:06:08 PM PDT 24 |
| Peak memory | 369092 kb |
| Host | smart-d204a906-3868-4efc-bc02-5b2dfefe194b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893407259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.893407259 |
| Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.2163927577 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 94808296 ps |
| CPU time | 0.65 seconds |
| Started | May 26 03:04:46 PM PDT 24 |
| Finished | May 26 03:04:47 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-ef4d200f-400f-468e-b6b9-cb8cbac5d927 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163927577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.2163927577 |
| Directory | /workspace/6.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_bijection.662649353 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 443026387258 ps |
| CPU time | 2441.73 seconds |
| Started | May 26 03:04:37 PM PDT 24 |
| Finished | May 26 03:45:19 PM PDT 24 |
| Peak memory | 202800 kb |
| Host | smart-d8639281-5406-4d4e-9d45-99710d8d655f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662649353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.662649353 |
| Directory | /workspace/6.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_executable.2037697716 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 19137030550 ps |
| CPU time | 980.01 seconds |
| Started | May 26 03:04:38 PM PDT 24 |
| Finished | May 26 03:20:59 PM PDT 24 |
| Peak memory | 374304 kb |
| Host | smart-150ac22a-d4ef-460a-9792-7e60114759dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037697716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.2037697716 |
| Directory | /workspace/6.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.4123138042 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4744860237 ps |
| CPU time | 27.98 seconds |
| Started | May 26 03:04:31 PM PDT 24 |
| Finished | May 26 03:04:59 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-60f114df-83e5-4d19-b44b-0d10df86fadb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123138042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.4123138042 |
| Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.1613039254 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4320558688 ps |
| CPU time | 64.2 seconds |
| Started | May 26 03:04:31 PM PDT 24 |
| Finished | May 26 03:05:36 PM PDT 24 |
| Peak memory | 321080 kb |
| Host | smart-51a05f82-7677-4479-934f-8eb98ca88177 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613039254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.1613039254 |
| Directory | /workspace/6.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3420200055 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4009479837 ps |
| CPU time | 67.72 seconds |
| Started | May 26 03:04:38 PM PDT 24 |
| Finished | May 26 03:05:46 PM PDT 24 |
| Peak memory | 212804 kb |
| Host | smart-d869e1e7-7a17-4f71-ba87-171c083624b9 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420200055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.3420200055 |
| Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.1080716835 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 6913692833 ps |
| CPU time | 151.6 seconds |
| Started | May 26 03:04:39 PM PDT 24 |
| Finished | May 26 03:07:11 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-65a30bc3-d63d-4342-8d61-1221214ff86c |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080716835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.1080716835 |
| Directory | /workspace/6.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.2655190358 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 8746446069 ps |
| CPU time | 274.64 seconds |
| Started | May 26 03:04:25 PM PDT 24 |
| Finished | May 26 03:09:00 PM PDT 24 |
| Peak memory | 373252 kb |
| Host | smart-0a56316a-2afc-4290-a82d-6a9708a16f43 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655190358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.2655190358 |
| Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.1629926349 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3496291795 ps |
| CPU time | 18.36 seconds |
| Started | May 26 03:04:37 PM PDT 24 |
| Finished | May 26 03:04:55 PM PDT 24 |
| Peak memory | 244112 kb |
| Host | smart-09ce723b-7565-4750-ac42-da51dd40e505 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629926349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.1629926349 |
| Directory | /workspace/6.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2775489887 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 48966624618 ps |
| CPU time | 284.36 seconds |
| Started | May 26 03:04:30 PM PDT 24 |
| Finished | May 26 03:09:15 PM PDT 24 |
| Peak memory | 202432 kb |
| Host | smart-aab95fe4-350b-4d47-b363-26c1e50ebb77 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775489887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.2775489887 |
| Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.3154362552 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 1400596945 ps |
| CPU time | 3.42 seconds |
| Started | May 26 03:04:39 PM PDT 24 |
| Finished | May 26 03:04:43 PM PDT 24 |
| Peak memory | 202540 kb |
| Host | smart-3999b00a-d0f3-4a16-8fd5-4c530b9338a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154362552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3154362552 |
| Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_regwen.3184680352 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 40943950099 ps |
| CPU time | 761.4 seconds |
| Started | May 26 03:04:39 PM PDT 24 |
| Finished | May 26 03:17:21 PM PDT 24 |
| Peak memory | 381052 kb |
| Host | smart-094133e9-7a93-41b4-9ce7-b698df59f886 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184680352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3184680352 |
| Directory | /workspace/6.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_smoke.4150848868 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2964205153 ps |
| CPU time | 55.17 seconds |
| Started | May 26 03:04:24 PM PDT 24 |
| Finished | May 26 03:05:20 PM PDT 24 |
| Peak memory | 320076 kb |
| Host | smart-5f25c931-6577-45fd-b78f-c787522432a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150848868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.4150848868 |
| Directory | /workspace/6.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.296751772 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 842414925 ps |
| CPU time | 39.13 seconds |
| Started | May 26 03:04:38 PM PDT 24 |
| Finished | May 26 03:05:18 PM PDT 24 |
| Peak memory | 210704 kb |
| Host | smart-040bc6ae-ecc7-4c8b-a32d-009dfac8a50f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=296751772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.296751772 |
| Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.978023871 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 40136684555 ps |
| CPU time | 343.21 seconds |
| Started | May 26 03:04:32 PM PDT 24 |
| Finished | May 26 03:10:15 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-c2d1d6c5-f438-40a5-be0c-2eb264ce5a1f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978023871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_stress_pipeline.978023871 |
| Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4192499704 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 711789904 ps |
| CPU time | 15.52 seconds |
| Started | May 26 03:04:30 PM PDT 24 |
| Finished | May 26 03:04:45 PM PDT 24 |
| Peak memory | 251516 kb |
| Host | smart-6cd10fd9-6a56-44af-85bf-22b324810d28 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192499704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.4192499704 |
| Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.2014227687 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 17207460 ps |
| CPU time | 0.67 seconds |
| Started | May 26 03:05:25 PM PDT 24 |
| Finished | May 26 03:05:26 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-5be739d6-baf4-494d-8260-84ac1192baee |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014227687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.2014227687 |
| Directory | /workspace/7.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_bijection.1480476127 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 115556677404 ps |
| CPU time | 2699.05 seconds |
| Started | May 26 03:04:46 PM PDT 24 |
| Finished | May 26 03:49:46 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-254fc6d3-52da-4a66-ba0c-5f7ddfd178c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480476127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 1480476127 |
| Directory | /workspace/7.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_executable.1953277869 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 27302425403 ps |
| CPU time | 455.06 seconds |
| Started | May 26 03:04:56 PM PDT 24 |
| Finished | May 26 03:12:32 PM PDT 24 |
| Peak memory | 347556 kb |
| Host | smart-90cf11c1-8abf-4134-900e-6573042ecaf5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953277869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.1953277869 |
| Directory | /workspace/7.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.1166116775 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 5717617755 ps |
| CPU time | 36.87 seconds |
| Started | May 26 03:04:54 PM PDT 24 |
| Finished | May 26 03:05:32 PM PDT 24 |
| Peak memory | 202480 kb |
| Host | smart-99a26f1a-b3c3-42af-9a1a-ff295a69cd63 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166116775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.1166116775 |
| Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.3181618725 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2856520203 ps |
| CPU time | 37.83 seconds |
| Started | May 26 03:04:47 PM PDT 24 |
| Finished | May 26 03:05:25 PM PDT 24 |
| Peak memory | 286380 kb |
| Host | smart-c9e3a443-1472-4a50-9049-1b07ddadaf07 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181618725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.3181618725 |
| Directory | /workspace/7.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3343532071 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1461329563 ps |
| CPU time | 71.75 seconds |
| Started | May 26 03:05:03 PM PDT 24 |
| Finished | May 26 03:06:16 PM PDT 24 |
| Peak memory | 212244 kb |
| Host | smart-c756bc5e-7ce8-474c-98c9-89a9a4258ab3 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343532071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.3343532071 |
| Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.596135532 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 8991754377 ps |
| CPU time | 167.63 seconds |
| Started | May 26 03:05:03 PM PDT 24 |
| Finished | May 26 03:07:51 PM PDT 24 |
| Peak memory | 210608 kb |
| Host | smart-ec3792dc-af62-45f3-a0b6-d0350cdf06e2 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596135532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ mem_walk.596135532 |
| Directory | /workspace/7.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.3797974849 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 62996335225 ps |
| CPU time | 1340.78 seconds |
| Started | May 26 03:04:46 PM PDT 24 |
| Finished | May 26 03:27:08 PM PDT 24 |
| Peak memory | 380508 kb |
| Host | smart-4c004204-ba10-437b-be2b-ebe8fddf25c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797974849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.3797974849 |
| Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.3223800277 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2851919207 ps |
| CPU time | 8.3 seconds |
| Started | May 26 03:04:46 PM PDT 24 |
| Finished | May 26 03:04:55 PM PDT 24 |
| Peak memory | 204840 kb |
| Host | smart-42ec131b-67a8-4863-be20-30d0f21fde71 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223800277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.3223800277 |
| Directory | /workspace/7.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1906738927 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 24973421539 ps |
| CPU time | 247.9 seconds |
| Started | May 26 03:04:51 PM PDT 24 |
| Finished | May 26 03:09:00 PM PDT 24 |
| Peak memory | 202324 kb |
| Host | smart-2fb59e9a-b3a9-4021-9f2d-b23b366d3796 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906738927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.1906738927 |
| Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.2543953219 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1460434329 ps |
| CPU time | 3.56 seconds |
| Started | May 26 03:05:03 PM PDT 24 |
| Finished | May 26 03:05:08 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-41dd59e5-afec-49fa-bf9f-cbfafd82a3de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543953219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2543953219 |
| Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_regwen.783949851 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 30691292711 ps |
| CPU time | 465.81 seconds |
| Started | May 26 03:04:56 PM PDT 24 |
| Finished | May 26 03:12:42 PM PDT 24 |
| Peak memory | 379348 kb |
| Host | smart-2dbf6e83-3079-47d4-b691-b0505657b841 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783949851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.783949851 |
| Directory | /workspace/7.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_smoke.3030433444 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 620077433 ps |
| CPU time | 10.28 seconds |
| Started | May 26 03:04:46 PM PDT 24 |
| Finished | May 26 03:04:57 PM PDT 24 |
| Peak memory | 210628 kb |
| Host | smart-d8f2134f-61b2-48c4-b1bd-649cfc684b05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030433444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3030433444 |
| Directory | /workspace/7.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.2978497113 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 24097794777 ps |
| CPU time | 370.13 seconds |
| Started | May 26 03:04:46 PM PDT 24 |
| Finished | May 26 03:10:56 PM PDT 24 |
| Peak memory | 202476 kb |
| Host | smart-131ffc43-780c-41cc-a948-31a05387afef |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978497113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.2978497113 |
| Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2599475831 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2729039575 ps |
| CPU time | 9.91 seconds |
| Started | May 26 03:04:55 PM PDT 24 |
| Finished | May 26 03:05:05 PM PDT 24 |
| Peak memory | 223352 kb |
| Host | smart-05ca9f55-cf7f-41ac-a1b9-6e1fc5282e24 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599475831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2599475831 |
| Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.3155958812 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 69286997 ps |
| CPU time | 0.65 seconds |
| Started | May 26 03:05:23 PM PDT 24 |
| Finished | May 26 03:05:25 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-d0c7084a-7fc7-4a67-aef1-1be8d23f88bf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155958812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.3155958812 |
| Directory | /workspace/8.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_bijection.2898935972 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 110894821411 ps |
| CPU time | 2595.55 seconds |
| Started | May 26 03:05:10 PM PDT 24 |
| Finished | May 26 03:48:26 PM PDT 24 |
| Peak memory | 203052 kb |
| Host | smart-1e19842c-d82b-4f99-a7d0-263e3d0bcde2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898935972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 2898935972 |
| Directory | /workspace/8.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_executable.1578269807 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 11324532619 ps |
| CPU time | 1515.26 seconds |
| Started | May 26 03:05:24 PM PDT 24 |
| Finished | May 26 03:30:40 PM PDT 24 |
| Peak memory | 379424 kb |
| Host | smart-08588282-b4e2-47bc-ab4e-2d1190b8840e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578269807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.1578269807 |
| Directory | /workspace/8.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.4268524304 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5221561746 ps |
| CPU time | 35.15 seconds |
| Started | May 26 03:05:15 PM PDT 24 |
| Finished | May 26 03:05:51 PM PDT 24 |
| Peak memory | 210728 kb |
| Host | smart-6e5d0505-2318-4ef9-8661-7ba5d137ca82 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268524304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.4268524304 |
| Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.3497505804 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 696805229 ps |
| CPU time | 14.9 seconds |
| Started | May 26 03:05:18 PM PDT 24 |
| Finished | May 26 03:05:33 PM PDT 24 |
| Peak memory | 238604 kb |
| Host | smart-370f18f1-50b6-4332-bc2d-e876e890bad0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497505804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.3497505804 |
| Directory | /workspace/8.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.4273828460 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 4673543642 ps |
| CPU time | 140.16 seconds |
| Started | May 26 03:05:23 PM PDT 24 |
| Finished | May 26 03:07:43 PM PDT 24 |
| Peak memory | 214952 kb |
| Host | smart-e9856c33-f1f1-40d4-b298-9fe54ebcc0fc |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273828460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.4273828460 |
| Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.4220545370 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 20889434957 ps |
| CPU time | 339.88 seconds |
| Started | May 26 03:05:25 PM PDT 24 |
| Finished | May 26 03:11:05 PM PDT 24 |
| Peak memory | 202832 kb |
| Host | smart-38244d11-0786-4243-b20b-ca5b9e0c10c9 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220545370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.4220545370 |
| Directory | /workspace/8.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.2217491122 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 7534128177 ps |
| CPU time | 568.62 seconds |
| Started | May 26 03:05:10 PM PDT 24 |
| Finished | May 26 03:14:39 PM PDT 24 |
| Peak memory | 376352 kb |
| Host | smart-3180a737-a67c-476d-9d8a-dd5c53f16b3b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217491122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.2217491122 |
| Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.828201017 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2447145780 ps |
| CPU time | 130.85 seconds |
| Started | May 26 03:05:09 PM PDT 24 |
| Finished | May 26 03:07:20 PM PDT 24 |
| Peak memory | 348720 kb |
| Host | smart-cdb36d4e-b9b8-4974-b12b-d959ed01946b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828201017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr am_ctrl_partial_access.828201017 |
| Directory | /workspace/8.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1668881533 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 35562819623 ps |
| CPU time | 467.73 seconds |
| Started | May 26 03:05:16 PM PDT 24 |
| Finished | May 26 03:13:05 PM PDT 24 |
| Peak memory | 210672 kb |
| Host | smart-a5d0ffec-19ad-453a-a30a-cbee8b3c7aad |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668881533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.1668881533 |
| Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.3603532995 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1352634311 ps |
| CPU time | 3.53 seconds |
| Started | May 26 03:05:25 PM PDT 24 |
| Finished | May 26 03:05:29 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-7f1441da-e7d0-4097-8aac-9fca2994f39b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603532995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3603532995 |
| Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_regwen.3756778095 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 13521980348 ps |
| CPU time | 875.07 seconds |
| Started | May 26 03:05:24 PM PDT 24 |
| Finished | May 26 03:20:00 PM PDT 24 |
| Peak memory | 374340 kb |
| Host | smart-1b342fd4-4d10-4ce5-a102-c449a356834f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756778095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3756778095 |
| Directory | /workspace/8.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_smoke.3098076476 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 8171017622 ps |
| CPU time | 87.35 seconds |
| Started | May 26 03:05:16 PM PDT 24 |
| Finished | May 26 03:06:44 PM PDT 24 |
| Peak memory | 353680 kb |
| Host | smart-c478bc63-8bf9-4da3-bf43-e4a217068532 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098076476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3098076476 |
| Directory | /workspace/8.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3387111757 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 283533399 ps |
| CPU time | 9.11 seconds |
| Started | May 26 03:05:23 PM PDT 24 |
| Finished | May 26 03:05:33 PM PDT 24 |
| Peak memory | 210720 kb |
| Host | smart-1d21c658-7030-4948-a944-76a53ba0d9b2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3387111757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3387111757 |
| Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3133188382 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 16515311106 ps |
| CPU time | 280.66 seconds |
| Started | May 26 03:05:18 PM PDT 24 |
| Finished | May 26 03:09:59 PM PDT 24 |
| Peak memory | 202472 kb |
| Host | smart-9349882b-8348-4a3d-82c1-988957d1746e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133188382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.3133188382 |
| Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2853728180 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5812205377 ps |
| CPU time | 17.02 seconds |
| Started | May 26 03:05:17 PM PDT 24 |
| Finished | May 26 03:05:34 PM PDT 24 |
| Peak memory | 243964 kb |
| Host | smart-88cee9e3-63cb-4137-b899-f8df57a8773b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853728180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2853728180 |
| Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.1576725239 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 23005399 ps |
| CPU time | 0.65 seconds |
| Started | May 26 03:05:46 PM PDT 24 |
| Finished | May 26 03:05:48 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-879330b9-02a2-45d1-9f29-3430e5354e9b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576725239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1576725239 |
| Directory | /workspace/9.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_bijection.162893726 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 136828480175 ps |
| CPU time | 2177.42 seconds |
| Started | May 26 03:05:31 PM PDT 24 |
| Finished | May 26 03:41:50 PM PDT 24 |
| Peak memory | 210516 kb |
| Host | smart-eb3caeb6-900c-4476-8587-f1fb3b3bc6f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162893726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.162893726 |
| Directory | /workspace/9.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_executable.2226168638 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 8694434787 ps |
| CPU time | 181.44 seconds |
| Started | May 26 03:05:38 PM PDT 24 |
| Finished | May 26 03:08:40 PM PDT 24 |
| Peak memory | 330260 kb |
| Host | smart-c138fb5c-2cf2-474e-ba2c-c95a599ab92f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226168638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.2226168638 |
| Directory | /workspace/9.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.1813574387 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 9713503259 ps |
| CPU time | 60.87 seconds |
| Started | May 26 03:05:38 PM PDT 24 |
| Finished | May 26 03:06:40 PM PDT 24 |
| Peak memory | 202492 kb |
| Host | smart-49f5d894-a2fb-4fb3-a11e-261141c9ed38 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813574387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.1813574387 |
| Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.505644013 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2856439379 ps |
| CPU time | 42.24 seconds |
| Started | May 26 03:05:38 PM PDT 24 |
| Finished | May 26 03:06:21 PM PDT 24 |
| Peak memory | 284216 kb |
| Host | smart-4695838c-0f0a-4cf1-92f5-355c3527876c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505644013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.sram_ctrl_max_throughput.505644013 |
| Directory | /workspace/9.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.679627418 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 14166573796 ps |
| CPU time | 173.73 seconds |
| Started | May 26 03:05:41 PM PDT 24 |
| Finished | May 26 03:08:35 PM PDT 24 |
| Peak memory | 214944 kb |
| Host | smart-7a27e262-f2e4-496f-9867-f808540c6eac |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679627418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9. sram_ctrl_mem_partial_access.679627418 |
| Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.2981146832 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 94415482313 ps |
| CPU time | 361.98 seconds |
| Started | May 26 03:05:40 PM PDT 24 |
| Finished | May 26 03:11:43 PM PDT 24 |
| Peak memory | 203260 kb |
| Host | smart-ec47e9ba-db2f-4142-9a23-e697ce9082ac |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981146832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.2981146832 |
| Directory | /workspace/9.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.1854076716 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3439713226 ps |
| CPU time | 496.44 seconds |
| Started | May 26 03:05:32 PM PDT 24 |
| Finished | May 26 03:13:49 PM PDT 24 |
| Peak memory | 375048 kb |
| Host | smart-51c17aa1-ad9b-4646-8609-9743bd5ff91d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854076716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.1854076716 |
| Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.3105217169 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 3246549960 ps |
| CPU time | 16.79 seconds |
| Started | May 26 03:05:32 PM PDT 24 |
| Finished | May 26 03:05:50 PM PDT 24 |
| Peak memory | 210648 kb |
| Host | smart-3d1d1cc7-f10d-4651-a9c5-7c0ab5c8bd0b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105217169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.3105217169 |
| Directory | /workspace/9.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1590705624 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 36827560079 ps |
| CPU time | 240.74 seconds |
| Started | May 26 03:05:31 PM PDT 24 |
| Finished | May 26 03:09:32 PM PDT 24 |
| Peak memory | 202456 kb |
| Host | smart-86c08848-bef2-4327-8481-356c9f74c124 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590705624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.1590705624 |
| Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.3472584061 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 365484393 ps |
| CPU time | 3.3 seconds |
| Started | May 26 03:05:40 PM PDT 24 |
| Finished | May 26 03:05:44 PM PDT 24 |
| Peak memory | 202536 kb |
| Host | smart-cf709eb5-5e38-4442-8f4d-6bbc9216f125 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472584061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3472584061 |
| Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_regwen.1004135749 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4012201618 ps |
| CPU time | 1333.43 seconds |
| Started | May 26 03:05:39 PM PDT 24 |
| Finished | May 26 03:27:53 PM PDT 24 |
| Peak memory | 377344 kb |
| Host | smart-c785a3fc-d12a-4c8c-a1cc-7e37956383fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004135749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1004135749 |
| Directory | /workspace/9.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_smoke.1280078992 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2970144077 ps |
| CPU time | 10.42 seconds |
| Started | May 26 03:05:32 PM PDT 24 |
| Finished | May 26 03:05:44 PM PDT 24 |
| Peak memory | 202684 kb |
| Host | smart-92c98435-97df-4bbc-9661-7b706bca8488 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280078992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1280078992 |
| Directory | /workspace/9.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3496569726 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 7688590800 ps |
| CPU time | 174.29 seconds |
| Started | May 26 03:05:43 PM PDT 24 |
| Finished | May 26 03:08:38 PM PDT 24 |
| Peak memory | 202640 kb |
| Host | smart-500a7c48-9ab0-46eb-8999-f31010e794cd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496569726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.3496569726 |
| Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.305379618 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 2692637838 ps |
| CPU time | 7.26 seconds |
| Started | May 26 03:05:38 PM PDT 24 |
| Finished | May 26 03:05:46 PM PDT 24 |
| Peak memory | 210684 kb |
| Host | smart-2fa11abc-4c6d-4eb4-ac40-ff208527060d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305379618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_throughput_w_partial_write.305379618 |
| Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |