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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.92 99.19 94.15 99.72 100.00 95.79 99.12 97.44


Total test records in report: 1032
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T557 /workspace/coverage/default/4.sram_ctrl_bijection.148636086 Jul 31 06:54:03 PM PDT 24 Jul 31 07:14:57 PM PDT 24 17404103070 ps
T558 /workspace/coverage/default/32.sram_ctrl_max_throughput.589092053 Jul 31 07:01:19 PM PDT 24 Jul 31 07:02:19 PM PDT 24 1814352752 ps
T559 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.590527261 Jul 31 07:04:23 PM PDT 24 Jul 31 07:05:39 PM PDT 24 10928201344 ps
T560 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.526020540 Jul 31 06:59:59 PM PDT 24 Jul 31 07:04:36 PM PDT 24 14866589704 ps
T561 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2154360043 Jul 31 06:58:49 PM PDT 24 Jul 31 07:03:01 PM PDT 24 10663456466 ps
T562 /workspace/coverage/default/38.sram_ctrl_smoke.1417387892 Jul 31 07:03:06 PM PDT 24 Jul 31 07:03:20 PM PDT 24 819812886 ps
T563 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.903786586 Jul 31 06:57:38 PM PDT 24 Jul 31 07:03:51 PM PDT 24 47038351504 ps
T564 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2252808658 Jul 31 07:03:36 PM PDT 24 Jul 31 07:06:10 PM PDT 24 16229579030 ps
T565 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2442527680 Jul 31 06:54:55 PM PDT 24 Jul 31 06:55:32 PM PDT 24 763495342 ps
T566 /workspace/coverage/default/46.sram_ctrl_alert_test.2461091887 Jul 31 07:05:34 PM PDT 24 Jul 31 07:05:34 PM PDT 24 32290318 ps
T567 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1679451445 Jul 31 07:02:56 PM PDT 24 Jul 31 07:03:27 PM PDT 24 8428997582 ps
T568 /workspace/coverage/default/36.sram_ctrl_lc_escalation.1372169391 Jul 31 07:02:43 PM PDT 24 Jul 31 07:05:02 PM PDT 24 76419661051 ps
T569 /workspace/coverage/default/27.sram_ctrl_executable.2280374619 Jul 31 07:00:05 PM PDT 24 Jul 31 07:11:13 PM PDT 24 28584681829 ps
T570 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3026463025 Jul 31 07:05:26 PM PDT 24 Jul 31 07:09:38 PM PDT 24 81423329877 ps
T571 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1158720039 Jul 31 06:53:18 PM PDT 24 Jul 31 06:58:56 PM PDT 24 59305070659 ps
T572 /workspace/coverage/default/25.sram_ctrl_multiple_keys.1923824430 Jul 31 06:59:37 PM PDT 24 Jul 31 07:20:16 PM PDT 24 23439292299 ps
T573 /workspace/coverage/default/42.sram_ctrl_lc_escalation.332693104 Jul 31 07:04:19 PM PDT 24 Jul 31 07:04:51 PM PDT 24 10726564126 ps
T574 /workspace/coverage/default/26.sram_ctrl_bijection.3238189646 Jul 31 06:59:47 PM PDT 24 Jul 31 07:11:13 PM PDT 24 56835115875 ps
T575 /workspace/coverage/default/4.sram_ctrl_mem_walk.1755573803 Jul 31 06:54:13 PM PDT 24 Jul 31 06:59:04 PM PDT 24 11180102344 ps
T576 /workspace/coverage/default/35.sram_ctrl_mem_walk.944899864 Jul 31 07:02:23 PM PDT 24 Jul 31 07:05:05 PM PDT 24 43807710212 ps
T577 /workspace/coverage/default/47.sram_ctrl_lc_escalation.1515314828 Jul 31 07:05:40 PM PDT 24 Jul 31 07:06:16 PM PDT 24 41991484708 ps
T578 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.4177591481 Jul 31 06:59:18 PM PDT 24 Jul 31 07:06:52 PM PDT 24 6363924631 ps
T579 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2116790260 Jul 31 06:53:38 PM PDT 24 Jul 31 06:55:19 PM PDT 24 13008534945 ps
T580 /workspace/coverage/default/23.sram_ctrl_ram_cfg.1043278102 Jul 31 06:59:18 PM PDT 24 Jul 31 06:59:21 PM PDT 24 348223446 ps
T133 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3330773798 Jul 31 07:03:19 PM PDT 24 Jul 31 07:03:56 PM PDT 24 2669124951 ps
T581 /workspace/coverage/default/49.sram_ctrl_bijection.2431781053 Jul 31 07:06:05 PM PDT 24 Jul 31 07:16:25 PM PDT 24 111686092922 ps
T582 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1944613067 Jul 31 06:57:57 PM PDT 24 Jul 31 07:00:02 PM PDT 24 7744298989 ps
T583 /workspace/coverage/default/39.sram_ctrl_executable.3932026268 Jul 31 07:03:35 PM PDT 24 Jul 31 07:14:34 PM PDT 24 7692751385 ps
T584 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3350357573 Jul 31 06:55:20 PM PDT 24 Jul 31 06:56:36 PM PDT 24 8631104133 ps
T585 /workspace/coverage/default/42.sram_ctrl_alert_test.182766907 Jul 31 07:04:27 PM PDT 24 Jul 31 07:04:28 PM PDT 24 12701838 ps
T586 /workspace/coverage/default/42.sram_ctrl_multiple_keys.2165871640 Jul 31 07:04:13 PM PDT 24 Jul 31 07:22:44 PM PDT 24 14661731725 ps
T587 /workspace/coverage/default/5.sram_ctrl_max_throughput.2002773302 Jul 31 06:54:25 PM PDT 24 Jul 31 06:54:32 PM PDT 24 702722433 ps
T588 /workspace/coverage/default/8.sram_ctrl_regwen.874642539 Jul 31 06:54:56 PM PDT 24 Jul 31 07:00:57 PM PDT 24 1742394224 ps
T589 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1850944486 Jul 31 06:53:07 PM PDT 24 Jul 31 06:56:08 PM PDT 24 47692252006 ps
T590 /workspace/coverage/default/47.sram_ctrl_smoke.854817080 Jul 31 07:05:34 PM PDT 24 Jul 31 07:05:45 PM PDT 24 1965218031 ps
T591 /workspace/coverage/default/2.sram_ctrl_mem_walk.239389314 Jul 31 06:53:43 PM PDT 24 Jul 31 06:55:45 PM PDT 24 2044157547 ps
T592 /workspace/coverage/default/44.sram_ctrl_mem_walk.1233385913 Jul 31 07:04:57 PM PDT 24 Jul 31 07:10:08 PM PDT 24 55347903490 ps
T593 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2722015954 Jul 31 06:53:39 PM PDT 24 Jul 31 07:12:01 PM PDT 24 12321839651 ps
T594 /workspace/coverage/default/15.sram_ctrl_regwen.2207394366 Jul 31 06:57:50 PM PDT 24 Jul 31 07:04:53 PM PDT 24 9860572739 ps
T595 /workspace/coverage/default/13.sram_ctrl_smoke.1562072269 Jul 31 06:57:46 PM PDT 24 Jul 31 06:57:51 PM PDT 24 1355209747 ps
T596 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.4061194627 Jul 31 06:57:46 PM PDT 24 Jul 31 06:58:13 PM PDT 24 2486222380 ps
T597 /workspace/coverage/default/48.sram_ctrl_executable.4091084333 Jul 31 07:05:53 PM PDT 24 Jul 31 07:20:52 PM PDT 24 20639040627 ps
T598 /workspace/coverage/default/35.sram_ctrl_ram_cfg.3323210142 Jul 31 07:02:23 PM PDT 24 Jul 31 07:02:27 PM PDT 24 353970641 ps
T599 /workspace/coverage/default/43.sram_ctrl_multiple_keys.4237444334 Jul 31 07:04:32 PM PDT 24 Jul 31 07:30:04 PM PDT 24 23397552035 ps
T600 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1309123712 Jul 31 06:57:53 PM PDT 24 Jul 31 06:58:21 PM PDT 24 917034083 ps
T601 /workspace/coverage/default/48.sram_ctrl_mem_walk.338447012 Jul 31 07:05:59 PM PDT 24 Jul 31 07:11:57 PM PDT 24 90001431535 ps
T602 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.588344877 Jul 31 07:01:02 PM PDT 24 Jul 31 07:02:28 PM PDT 24 6117856664 ps
T603 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1496254030 Jul 31 06:54:40 PM PDT 24 Jul 31 06:54:56 PM PDT 24 710177794 ps
T604 /workspace/coverage/default/15.sram_ctrl_executable.2239036301 Jul 31 06:57:54 PM PDT 24 Jul 31 07:06:48 PM PDT 24 72193140438 ps
T605 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2667463440 Jul 31 07:03:07 PM PDT 24 Jul 31 07:04:37 PM PDT 24 28663606801 ps
T606 /workspace/coverage/default/7.sram_ctrl_partial_access.574750045 Jul 31 06:54:48 PM PDT 24 Jul 31 06:55:10 PM PDT 24 1421387541 ps
T607 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3364599850 Jul 31 06:58:11 PM PDT 24 Jul 31 07:02:37 PM PDT 24 3816503860 ps
T608 /workspace/coverage/default/6.sram_ctrl_multiple_keys.1743163306 Jul 31 06:54:31 PM PDT 24 Jul 31 07:15:26 PM PDT 24 24360064655 ps
T609 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3951461528 Jul 31 07:04:12 PM PDT 24 Jul 31 07:06:26 PM PDT 24 12145285989 ps
T610 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3740529975 Jul 31 07:05:52 PM PDT 24 Jul 31 07:07:20 PM PDT 24 817930958 ps
T611 /workspace/coverage/default/43.sram_ctrl_partial_access.3160461703 Jul 31 07:04:31 PM PDT 24 Jul 31 07:04:44 PM PDT 24 1584377767 ps
T612 /workspace/coverage/default/1.sram_ctrl_smoke.2481174029 Jul 31 06:53:08 PM PDT 24 Jul 31 06:53:25 PM PDT 24 384034999 ps
T613 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2795335619 Jul 31 06:54:14 PM PDT 24 Jul 31 06:58:00 PM PDT 24 14108502781 ps
T614 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1569419245 Jul 31 07:03:20 PM PDT 24 Jul 31 07:06:32 PM PDT 24 13645855307 ps
T615 /workspace/coverage/default/11.sram_ctrl_regwen.2673611433 Jul 31 06:57:41 PM PDT 24 Jul 31 07:08:35 PM PDT 24 2926477263 ps
T616 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.4240019195 Jul 31 07:01:40 PM PDT 24 Jul 31 07:06:45 PM PDT 24 18867944368 ps
T617 /workspace/coverage/default/43.sram_ctrl_alert_test.780387294 Jul 31 07:04:42 PM PDT 24 Jul 31 07:04:43 PM PDT 24 23780060 ps
T618 /workspace/coverage/default/42.sram_ctrl_stress_all.939787138 Jul 31 07:04:24 PM PDT 24 Jul 31 08:10:57 PM PDT 24 48454198868 ps
T619 /workspace/coverage/default/18.sram_ctrl_partial_access.3054255372 Jul 31 06:58:08 PM PDT 24 Jul 31 06:58:22 PM PDT 24 1644037837 ps
T620 /workspace/coverage/default/14.sram_ctrl_alert_test.3196825770 Jul 31 06:57:51 PM PDT 24 Jul 31 06:57:52 PM PDT 24 18332515 ps
T621 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1562815542 Jul 31 07:00:36 PM PDT 24 Jul 31 07:09:16 PM PDT 24 47505333032 ps
T622 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3470325097 Jul 31 07:05:26 PM PDT 24 Jul 31 07:05:32 PM PDT 24 1387820433 ps
T623 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1642593261 Jul 31 06:57:48 PM PDT 24 Jul 31 06:58:33 PM PDT 24 1489681607 ps
T624 /workspace/coverage/default/17.sram_ctrl_multiple_keys.618623296 Jul 31 06:57:57 PM PDT 24 Jul 31 07:13:01 PM PDT 24 11856954286 ps
T625 /workspace/coverage/default/47.sram_ctrl_max_throughput.3731667899 Jul 31 07:05:42 PM PDT 24 Jul 31 07:07:18 PM PDT 24 965093554 ps
T626 /workspace/coverage/default/0.sram_ctrl_alert_test.3673663366 Jul 31 06:53:06 PM PDT 24 Jul 31 06:53:07 PM PDT 24 43276570 ps
T627 /workspace/coverage/default/46.sram_ctrl_mem_walk.2968433353 Jul 31 07:05:25 PM PDT 24 Jul 31 07:11:24 PM PDT 24 94548230231 ps
T628 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3949588430 Jul 31 06:54:20 PM PDT 24 Jul 31 06:56:49 PM PDT 24 14351123463 ps
T629 /workspace/coverage/default/13.sram_ctrl_ram_cfg.234567376 Jul 31 06:57:49 PM PDT 24 Jul 31 06:57:53 PM PDT 24 353979110 ps
T630 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.274300290 Jul 31 07:02:17 PM PDT 24 Jul 31 07:08:30 PM PDT 24 30140104092 ps
T631 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1548040623 Jul 31 06:57:40 PM PDT 24 Jul 31 06:57:58 PM PDT 24 1799730786 ps
T632 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.828432915 Jul 31 06:58:19 PM PDT 24 Jul 31 06:58:26 PM PDT 24 673230820 ps
T633 /workspace/coverage/default/8.sram_ctrl_partial_access.827856455 Jul 31 06:54:54 PM PDT 24 Jul 31 06:55:09 PM PDT 24 2354567752 ps
T634 /workspace/coverage/default/45.sram_ctrl_ram_cfg.1652874387 Jul 31 07:05:16 PM PDT 24 Jul 31 07:05:20 PM PDT 24 1416476469 ps
T635 /workspace/coverage/default/49.sram_ctrl_lc_escalation.1696231631 Jul 31 07:06:10 PM PDT 24 Jul 31 07:07:32 PM PDT 24 14219373754 ps
T636 /workspace/coverage/default/20.sram_ctrl_partial_access.241272437 Jul 31 06:58:34 PM PDT 24 Jul 31 06:58:39 PM PDT 24 811943465 ps
T637 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2454092499 Jul 31 06:54:50 PM PDT 24 Jul 31 06:56:34 PM PDT 24 24083730754 ps
T638 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3107630700 Jul 31 07:00:48 PM PDT 24 Jul 31 07:03:25 PM PDT 24 87594172655 ps
T639 /workspace/coverage/default/10.sram_ctrl_partial_access.1222743739 Jul 31 06:57:11 PM PDT 24 Jul 31 06:59:05 PM PDT 24 12438340153 ps
T640 /workspace/coverage/default/38.sram_ctrl_mem_walk.2418316801 Jul 31 07:03:19 PM PDT 24 Jul 31 07:08:22 PM PDT 24 10509074488 ps
T641 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.480360189 Jul 31 06:59:46 PM PDT 24 Jul 31 06:59:57 PM PDT 24 488272286 ps
T642 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1455807322 Jul 31 07:02:19 PM PDT 24 Jul 31 07:02:34 PM PDT 24 275922432 ps
T643 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.362845349 Jul 31 06:53:02 PM PDT 24 Jul 31 07:17:29 PM PDT 24 48525815829 ps
T644 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.4220959570 Jul 31 07:00:53 PM PDT 24 Jul 31 07:16:05 PM PDT 24 51173927648 ps
T645 /workspace/coverage/default/48.sram_ctrl_regwen.1193131001 Jul 31 07:05:55 PM PDT 24 Jul 31 07:26:49 PM PDT 24 57491771401 ps
T646 /workspace/coverage/default/26.sram_ctrl_partial_access.2714986914 Jul 31 06:59:47 PM PDT 24 Jul 31 07:00:05 PM PDT 24 7535337532 ps
T647 /workspace/coverage/default/17.sram_ctrl_mem_walk.705794870 Jul 31 06:58:04 PM PDT 24 Jul 31 07:03:41 PM PDT 24 72813766467 ps
T648 /workspace/coverage/default/10.sram_ctrl_max_throughput.207791662 Jul 31 06:57:08 PM PDT 24 Jul 31 06:57:15 PM PDT 24 3028623240 ps
T649 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2120283187 Jul 31 07:02:23 PM PDT 24 Jul 31 07:20:08 PM PDT 24 14294509795 ps
T650 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.854745601 Jul 31 06:57:56 PM PDT 24 Jul 31 07:10:40 PM PDT 24 17867555225 ps
T651 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2683659688 Jul 31 07:04:07 PM PDT 24 Jul 31 07:26:56 PM PDT 24 15851848239 ps
T652 /workspace/coverage/default/48.sram_ctrl_partial_access.48611477 Jul 31 07:05:45 PM PDT 24 Jul 31 07:05:52 PM PDT 24 800943723 ps
T653 /workspace/coverage/default/18.sram_ctrl_ram_cfg.819798868 Jul 31 06:58:22 PM PDT 24 Jul 31 06:58:26 PM PDT 24 706662691 ps
T654 /workspace/coverage/default/0.sram_ctrl_max_throughput.5863401 Jul 31 06:52:57 PM PDT 24 Jul 31 06:53:09 PM PDT 24 8486405799 ps
T655 /workspace/coverage/default/27.sram_ctrl_bijection.2201895738 Jul 31 06:59:59 PM PDT 24 Jul 31 07:08:51 PM PDT 24 27696713209 ps
T656 /workspace/coverage/default/23.sram_ctrl_regwen.1073721546 Jul 31 06:59:18 PM PDT 24 Jul 31 07:02:21 PM PDT 24 2430125029 ps
T657 /workspace/coverage/default/11.sram_ctrl_ram_cfg.458712887 Jul 31 06:57:47 PM PDT 24 Jul 31 06:57:50 PM PDT 24 361956627 ps
T658 /workspace/coverage/default/21.sram_ctrl_regwen.468308339 Jul 31 06:58:56 PM PDT 24 Jul 31 07:11:37 PM PDT 24 12157054478 ps
T659 /workspace/coverage/default/6.sram_ctrl_bijection.246247194 Jul 31 06:54:34 PM PDT 24 Jul 31 07:27:59 PM PDT 24 782368702557 ps
T660 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2220396153 Jul 31 06:57:11 PM PDT 24 Jul 31 06:58:41 PM PDT 24 11148901954 ps
T661 /workspace/coverage/default/29.sram_ctrl_multiple_keys.3153895985 Jul 31 07:00:28 PM PDT 24 Jul 31 07:15:52 PM PDT 24 8231633287 ps
T662 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.265957099 Jul 31 06:55:00 PM PDT 24 Jul 31 06:55:11 PM PDT 24 1064480935 ps
T663 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1277926867 Jul 31 07:00:52 PM PDT 24 Jul 31 07:01:00 PM PDT 24 1382265993 ps
T664 /workspace/coverage/default/32.sram_ctrl_lc_escalation.3342670449 Jul 31 07:01:25 PM PDT 24 Jul 31 07:02:33 PM PDT 24 22284238043 ps
T665 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.606522227 Jul 31 07:04:00 PM PDT 24 Jul 31 07:07:39 PM PDT 24 2607015596 ps
T666 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3630001919 Jul 31 07:03:55 PM PDT 24 Jul 31 07:05:06 PM PDT 24 1387581010 ps
T667 /workspace/coverage/default/41.sram_ctrl_multiple_keys.2328924719 Jul 31 07:04:01 PM PDT 24 Jul 31 07:17:39 PM PDT 24 66942182420 ps
T668 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.475955389 Jul 31 07:03:37 PM PDT 24 Jul 31 07:11:58 PM PDT 24 21829728506 ps
T669 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2235999459 Jul 31 07:04:34 PM PDT 24 Jul 31 07:07:04 PM PDT 24 8585600332 ps
T670 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3516991665 Jul 31 06:58:27 PM PDT 24 Jul 31 07:05:08 PM PDT 24 23701267928 ps
T671 /workspace/coverage/default/9.sram_ctrl_max_throughput.3433342316 Jul 31 06:55:06 PM PDT 24 Jul 31 06:56:40 PM PDT 24 3128157174 ps
T672 /workspace/coverage/default/20.sram_ctrl_multiple_keys.2077299756 Jul 31 06:58:35 PM PDT 24 Jul 31 07:16:32 PM PDT 24 98535771489 ps
T673 /workspace/coverage/default/17.sram_ctrl_smoke.1847464774 Jul 31 06:57:56 PM PDT 24 Jul 31 07:00:23 PM PDT 24 780546883 ps
T674 /workspace/coverage/default/11.sram_ctrl_alert_test.1301765147 Jul 31 06:57:47 PM PDT 24 Jul 31 06:57:48 PM PDT 24 26074825 ps
T134 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4293203942 Jul 31 06:57:50 PM PDT 24 Jul 31 06:58:20 PM PDT 24 4277692905 ps
T675 /workspace/coverage/default/36.sram_ctrl_executable.3463378674 Jul 31 07:02:49 PM PDT 24 Jul 31 07:31:05 PM PDT 24 146109032964 ps
T676 /workspace/coverage/default/40.sram_ctrl_partial_access.1679627222 Jul 31 07:03:47 PM PDT 24 Jul 31 07:04:13 PM PDT 24 1665775521 ps
T677 /workspace/coverage/default/49.sram_ctrl_stress_all.570444299 Jul 31 07:06:22 PM PDT 24 Jul 31 08:30:36 PM PDT 24 748293369378 ps
T678 /workspace/coverage/default/36.sram_ctrl_stress_all.1647043287 Jul 31 07:02:56 PM PDT 24 Jul 31 07:43:30 PM PDT 24 158390480124 ps
T679 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2995528406 Jul 31 06:54:13 PM PDT 24 Jul 31 06:55:22 PM PDT 24 4002421507 ps
T680 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2300893546 Jul 31 07:01:09 PM PDT 24 Jul 31 07:06:38 PM PDT 24 29004715427 ps
T681 /workspace/coverage/default/41.sram_ctrl_smoke.3584676603 Jul 31 07:04:00 PM PDT 24 Jul 31 07:04:12 PM PDT 24 2582167103 ps
T682 /workspace/coverage/default/36.sram_ctrl_regwen.2988773152 Jul 31 07:02:50 PM PDT 24 Jul 31 07:26:55 PM PDT 24 4166429547 ps
T683 /workspace/coverage/default/4.sram_ctrl_lc_escalation.3786095427 Jul 31 06:54:07 PM PDT 24 Jul 31 06:54:22 PM PDT 24 2467309170 ps
T684 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2117467639 Jul 31 06:58:00 PM PDT 24 Jul 31 07:02:05 PM PDT 24 15090321867 ps
T685 /workspace/coverage/default/4.sram_ctrl_regwen.576801726 Jul 31 06:54:09 PM PDT 24 Jul 31 07:24:59 PM PDT 24 45472653041 ps
T686 /workspace/coverage/default/27.sram_ctrl_stress_all.3017570566 Jul 31 07:00:12 PM PDT 24 Jul 31 08:27:33 PM PDT 24 519612836809 ps
T687 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1476562283 Jul 31 06:54:58 PM PDT 24 Jul 31 07:01:32 PM PDT 24 61583812717 ps
T688 /workspace/coverage/default/34.sram_ctrl_regwen.564767888 Jul 31 07:02:19 PM PDT 24 Jul 31 07:27:04 PM PDT 24 67645988386 ps
T689 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1131460846 Jul 31 06:59:55 PM PDT 24 Jul 31 06:59:59 PM PDT 24 358956717 ps
T690 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2986333327 Jul 31 06:59:30 PM PDT 24 Jul 31 07:02:18 PM PDT 24 5022290287 ps
T691 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2060351739 Jul 31 07:06:04 PM PDT 24 Jul 31 07:10:37 PM PDT 24 17674210995 ps
T692 /workspace/coverage/default/35.sram_ctrl_stress_all.4087701223 Jul 31 07:02:29 PM PDT 24 Jul 31 08:35:38 PM PDT 24 637194507341 ps
T693 /workspace/coverage/default/32.sram_ctrl_smoke.898921951 Jul 31 07:01:14 PM PDT 24 Jul 31 07:01:34 PM PDT 24 1465007374 ps
T694 /workspace/coverage/default/44.sram_ctrl_max_throughput.77532251 Jul 31 07:04:49 PM PDT 24 Jul 31 07:05:11 PM PDT 24 3184465067 ps
T695 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.246206614 Jul 31 06:54:03 PM PDT 24 Jul 31 06:55:19 PM PDT 24 2355306196 ps
T696 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3434415134 Jul 31 06:57:48 PM PDT 24 Jul 31 06:59:06 PM PDT 24 3758736527 ps
T697 /workspace/coverage/default/6.sram_ctrl_alert_test.3141109023 Jul 31 06:54:43 PM PDT 24 Jul 31 06:54:44 PM PDT 24 175592172 ps
T698 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4191499596 Jul 31 06:57:55 PM PDT 24 Jul 31 06:58:07 PM PDT 24 3597061648 ps
T699 /workspace/coverage/default/28.sram_ctrl_partial_access.3530368381 Jul 31 07:00:24 PM PDT 24 Jul 31 07:01:56 PM PDT 24 559778455 ps
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T701 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.4147842652 Jul 31 06:59:54 PM PDT 24 Jul 31 07:13:50 PM PDT 24 59696067837 ps
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T703 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2128573591 Jul 31 07:05:08 PM PDT 24 Jul 31 07:38:16 PM PDT 24 42865016087 ps
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T705 /workspace/coverage/default/13.sram_ctrl_multiple_keys.3156793579 Jul 31 06:57:49 PM PDT 24 Jul 31 07:03:34 PM PDT 24 6095048612 ps
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T710 /workspace/coverage/default/39.sram_ctrl_alert_test.3234563221 Jul 31 07:03:43 PM PDT 24 Jul 31 07:03:44 PM PDT 24 18171226 ps
T711 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.135706632 Jul 31 06:58:48 PM PDT 24 Jul 31 07:01:41 PM PDT 24 3118071810 ps
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T715 /workspace/coverage/default/18.sram_ctrl_alert_test.3732610681 Jul 31 06:58:31 PM PDT 24 Jul 31 06:58:31 PM PDT 24 26129226 ps
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T717 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1058982650 Jul 31 07:02:29 PM PDT 24 Jul 31 07:05:12 PM PDT 24 20499683789 ps
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T719 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2861629855 Jul 31 07:04:23 PM PDT 24 Jul 31 07:15:53 PM PDT 24 7159668170 ps
T720 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3899961696 Jul 31 06:53:31 PM PDT 24 Jul 31 06:57:14 PM PDT 24 10478727965 ps
T30 /workspace/coverage/default/0.sram_ctrl_sec_cm.3227859716 Jul 31 06:53:09 PM PDT 24 Jul 31 06:53:12 PM PDT 24 1045461698 ps
T721 /workspace/coverage/default/8.sram_ctrl_alert_test.512405817 Jul 31 06:55:01 PM PDT 24 Jul 31 06:55:01 PM PDT 24 22578181 ps
T722 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.152000386 Jul 31 07:00:03 PM PDT 24 Jul 31 07:06:40 PM PDT 24 68144320561 ps
T723 /workspace/coverage/default/31.sram_ctrl_lc_escalation.937941347 Jul 31 07:01:08 PM PDT 24 Jul 31 07:01:40 PM PDT 24 18263621736 ps
T724 /workspace/coverage/default/39.sram_ctrl_regwen.1774171609 Jul 31 07:03:39 PM PDT 24 Jul 31 07:05:08 PM PDT 24 12985220552 ps
T725 /workspace/coverage/default/19.sram_ctrl_multiple_keys.385333464 Jul 31 06:58:29 PM PDT 24 Jul 31 07:00:02 PM PDT 24 9628119104 ps
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T727 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3986052092 Jul 31 06:57:47 PM PDT 24 Jul 31 07:00:16 PM PDT 24 4707066693 ps
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T729 /workspace/coverage/default/6.sram_ctrl_stress_all.2827919913 Jul 31 06:54:45 PM PDT 24 Jul 31 07:26:06 PM PDT 24 44654432145 ps
T730 /workspace/coverage/default/20.sram_ctrl_executable.1248395462 Jul 31 06:58:41 PM PDT 24 Jul 31 07:04:20 PM PDT 24 5108522762 ps
T731 /workspace/coverage/default/32.sram_ctrl_partial_access.1356825778 Jul 31 07:01:20 PM PDT 24 Jul 31 07:01:50 PM PDT 24 9440915607 ps
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T733 /workspace/coverage/default/40.sram_ctrl_lc_escalation.2227792179 Jul 31 07:03:48 PM PDT 24 Jul 31 07:04:46 PM PDT 24 29869638917 ps
T734 /workspace/coverage/default/5.sram_ctrl_executable.2828108196 Jul 31 06:54:27 PM PDT 24 Jul 31 07:02:25 PM PDT 24 103431731382 ps
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T736 /workspace/coverage/default/22.sram_ctrl_alert_test.1078070207 Jul 31 06:59:07 PM PDT 24 Jul 31 06:59:08 PM PDT 24 30566480 ps
T737 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3981889517 Jul 31 06:58:19 PM PDT 24 Jul 31 07:23:32 PM PDT 24 44901999133 ps
T738 /workspace/coverage/default/30.sram_ctrl_partial_access.1709211792 Jul 31 07:00:48 PM PDT 24 Jul 31 07:01:04 PM PDT 24 1443883098 ps
T739 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1610484869 Jul 31 07:05:45 PM PDT 24 Jul 31 07:06:13 PM PDT 24 2736384179 ps
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T741 /workspace/coverage/default/34.sram_ctrl_lc_escalation.1659744995 Jul 31 07:02:17 PM PDT 24 Jul 31 07:02:57 PM PDT 24 23340272269 ps
T742 /workspace/coverage/default/43.sram_ctrl_bijection.3235941713 Jul 31 07:04:32 PM PDT 24 Jul 31 07:34:54 PM PDT 24 94319368043 ps
T743 /workspace/coverage/default/4.sram_ctrl_max_throughput.3074402396 Jul 31 06:54:09 PM PDT 24 Jul 31 06:55:59 PM PDT 24 784255504 ps
T744 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3559416440 Jul 31 06:58:29 PM PDT 24 Jul 31 07:00:44 PM PDT 24 810648712 ps
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T746 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1791338393 Jul 31 06:59:47 PM PDT 24 Jul 31 07:06:16 PM PDT 24 12458594746 ps
T747 /workspace/coverage/default/4.sram_ctrl_smoke.707603195 Jul 31 06:54:03 PM PDT 24 Jul 31 06:54:15 PM PDT 24 1482633319 ps
T748 /workspace/coverage/default/24.sram_ctrl_mem_walk.2931355217 Jul 31 06:59:25 PM PDT 24 Jul 31 07:02:27 PM PDT 24 44915058940 ps
T749 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.482646238 Jul 31 07:04:50 PM PDT 24 Jul 31 07:09:11 PM PDT 24 21186399087 ps
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T754 /workspace/coverage/default/40.sram_ctrl_bijection.2596188043 Jul 31 07:03:43 PM PDT 24 Jul 31 07:30:27 PM PDT 24 96773822024 ps
T755 /workspace/coverage/default/15.sram_ctrl_multiple_keys.1326412485 Jul 31 06:57:53 PM PDT 24 Jul 31 07:07:56 PM PDT 24 34077589664 ps
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T759 /workspace/coverage/default/46.sram_ctrl_max_throughput.3338728717 Jul 31 07:05:26 PM PDT 24 Jul 31 07:06:16 PM PDT 24 744681174 ps
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T763 /workspace/coverage/default/48.sram_ctrl_alert_test.12135563 Jul 31 07:06:04 PM PDT 24 Jul 31 07:06:05 PM PDT 24 17796920 ps
T764 /workspace/coverage/default/2.sram_ctrl_smoke.3048348621 Jul 31 06:53:27 PM PDT 24 Jul 31 06:53:38 PM PDT 24 2020646306 ps
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T766 /workspace/coverage/default/49.sram_ctrl_partial_access.318223930 Jul 31 07:06:04 PM PDT 24 Jul 31 07:06:15 PM PDT 24 964171788 ps
T767 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3904406168 Jul 31 07:05:11 PM PDT 24 Jul 31 07:08:00 PM PDT 24 3470446520 ps
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T769 /workspace/coverage/default/47.sram_ctrl_partial_access.1097097274 Jul 31 07:05:37 PM PDT 24 Jul 31 07:05:55 PM PDT 24 5111877825 ps
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T772 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2507017011 Jul 31 06:59:30 PM PDT 24 Jul 31 07:00:04 PM PDT 24 1171151876 ps
T773 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1502906773 Jul 31 07:01:25 PM PDT 24 Jul 31 07:01:39 PM PDT 24 839134248 ps
T774 /workspace/coverage/default/5.sram_ctrl_regwen.2080615228 Jul 31 06:54:25 PM PDT 24 Jul 31 07:12:29 PM PDT 24 14729599858 ps
T775 /workspace/coverage/default/20.sram_ctrl_ram_cfg.223414065 Jul 31 06:58:41 PM PDT 24 Jul 31 06:58:44 PM PDT 24 368914238 ps
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T777 /workspace/coverage/default/25.sram_ctrl_partial_access.4172908832 Jul 31 06:59:41 PM PDT 24 Jul 31 07:02:17 PM PDT 24 3088144689 ps
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T779 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1457164702 Jul 31 06:55:13 PM PDT 24 Jul 31 06:57:19 PM PDT 24 35565684911 ps
T780 /workspace/coverage/default/3.sram_ctrl_bijection.800830254 Jul 31 06:53:48 PM PDT 24 Jul 31 07:22:34 PM PDT 24 48850575291 ps
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T782 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1762755233 Jul 31 06:58:58 PM PDT 24 Jul 31 07:01:53 PM PDT 24 27804965409 ps
T783 /workspace/coverage/default/17.sram_ctrl_partial_access.2760608051 Jul 31 06:58:05 PM PDT 24 Jul 31 06:58:15 PM PDT 24 679798806 ps
T784 /workspace/coverage/default/47.sram_ctrl_ram_cfg.1975282512 Jul 31 07:05:41 PM PDT 24 Jul 31 07:05:44 PM PDT 24 2237234621 ps
T785 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.429552746 Jul 31 07:03:22 PM PDT 24 Jul 31 07:04:44 PM PDT 24 19648569541 ps
T786 /workspace/coverage/default/44.sram_ctrl_partial_access.2879197292 Jul 31 07:04:49 PM PDT 24 Jul 31 07:05:00 PM PDT 24 2799205127 ps
T787 /workspace/coverage/default/10.sram_ctrl_ram_cfg.2863849680 Jul 31 06:57:08 PM PDT 24 Jul 31 06:57:11 PM PDT 24 1245637161 ps
T788 /workspace/coverage/default/37.sram_ctrl_bijection.4004646860 Jul 31 07:03:00 PM PDT 24 Jul 31 07:47:57 PM PDT 24 337774098069 ps
T789 /workspace/coverage/default/23.sram_ctrl_lc_escalation.1191585464 Jul 31 06:59:11 PM PDT 24 Jul 31 07:00:25 PM PDT 24 196676740104 ps
T790 /workspace/coverage/default/0.sram_ctrl_bijection.596315058 Jul 31 06:52:58 PM PDT 24 Jul 31 07:02:19 PM PDT 24 32810672230 ps
T791 /workspace/coverage/default/33.sram_ctrl_alert_test.563604762 Jul 31 07:02:23 PM PDT 24 Jul 31 07:02:23 PM PDT 24 44114365 ps
T792 /workspace/coverage/default/43.sram_ctrl_lc_escalation.2890010340 Jul 31 07:04:37 PM PDT 24 Jul 31 07:04:47 PM PDT 24 5172930500 ps
T793 /workspace/coverage/default/45.sram_ctrl_max_throughput.1471999030 Jul 31 07:05:09 PM PDT 24 Jul 31 07:06:41 PM PDT 24 760032736 ps
T135 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1346348178 Jul 31 06:59:17 PM PDT 24 Jul 31 07:00:03 PM PDT 24 9530857530 ps
T794 /workspace/coverage/default/16.sram_ctrl_bijection.1516567237 Jul 31 06:57:57 PM PDT 24 Jul 31 07:33:43 PM PDT 24 193494275499 ps
T795 /workspace/coverage/default/37.sram_ctrl_multiple_keys.307916940 Jul 31 07:03:01 PM PDT 24 Jul 31 07:03:49 PM PDT 24 504215148 ps
T796 /workspace/coverage/default/30.sram_ctrl_executable.3072023397 Jul 31 07:00:53 PM PDT 24 Jul 31 07:22:06 PM PDT 24 50341159344 ps
T797 /workspace/coverage/default/39.sram_ctrl_ram_cfg.3311802695 Jul 31 07:03:37 PM PDT 24 Jul 31 07:03:41 PM PDT 24 457282840 ps
T798 /workspace/coverage/default/18.sram_ctrl_multiple_keys.1446126296 Jul 31 06:58:09 PM PDT 24 Jul 31 07:27:11 PM PDT 24 21653282369 ps
T799 /workspace/coverage/default/38.sram_ctrl_regwen.51588378 Jul 31 07:03:19 PM PDT 24 Jul 31 07:28:56 PM PDT 24 14029821360 ps
T800 /workspace/coverage/default/34.sram_ctrl_executable.1304564890 Jul 31 07:02:18 PM PDT 24 Jul 31 07:27:05 PM PDT 24 104471715706 ps
T801 /workspace/coverage/default/22.sram_ctrl_ram_cfg.3048887625 Jul 31 06:59:01 PM PDT 24 Jul 31 06:59:05 PM PDT 24 358506971 ps
T802 /workspace/coverage/default/8.sram_ctrl_multiple_keys.2344929225 Jul 31 06:54:56 PM PDT 24 Jul 31 06:55:29 PM PDT 24 5076130927 ps
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