| T803 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1536643847 |
|
|
Jul 31 06:54:56 PM PDT 24 |
Jul 31 07:15:34 PM PDT 24 |
55317268481 ps |
| T804 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3508172724 |
|
|
Jul 31 07:05:08 PM PDT 24 |
Jul 31 08:30:44 PM PDT 24 |
146212190626 ps |
| T805 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.643896807 |
|
|
Jul 31 07:00:38 PM PDT 24 |
Jul 31 07:01:03 PM PDT 24 |
11324944000 ps |
| T806 |
/workspace/coverage/default/2.sram_ctrl_regwen.445151649 |
|
|
Jul 31 06:53:39 PM PDT 24 |
Jul 31 07:07:22 PM PDT 24 |
46844194707 ps |
| T807 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2237853608 |
|
|
Jul 31 07:02:33 PM PDT 24 |
Jul 31 07:02:45 PM PDT 24 |
551347890 ps |
| T808 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1553727910 |
|
|
Jul 31 07:03:23 PM PDT 24 |
Jul 31 07:22:41 PM PDT 24 |
23410850316 ps |
| T809 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.580004883 |
|
|
Jul 31 06:57:08 PM PDT 24 |
Jul 31 07:02:22 PM PDT 24 |
4786775946 ps |
| T810 |
/workspace/coverage/default/45.sram_ctrl_smoke.2569247756 |
|
|
Jul 31 07:05:02 PM PDT 24 |
Jul 31 07:05:24 PM PDT 24 |
428708832 ps |
| T811 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2810777467 |
|
|
Jul 31 07:00:06 PM PDT 24 |
Jul 31 07:00:48 PM PDT 24 |
3500885616 ps |
| T812 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.4241404023 |
|
|
Jul 31 06:59:40 PM PDT 24 |
Jul 31 07:15:40 PM PDT 24 |
63667634816 ps |
| T813 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.2861534902 |
|
|
Jul 31 06:59:14 PM PDT 24 |
Jul 31 07:00:56 PM PDT 24 |
3169985592 ps |
| T814 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.4175761776 |
|
|
Jul 31 06:58:56 PM PDT 24 |
Jul 31 06:58:59 PM PDT 24 |
1381530907 ps |
| T815 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.2030225728 |
|
|
Jul 31 07:03:26 PM PDT 24 |
Jul 31 07:04:25 PM PDT 24 |
38749568771 ps |
| T816 |
/workspace/coverage/default/16.sram_ctrl_alert_test.283154235 |
|
|
Jul 31 06:57:54 PM PDT 24 |
Jul 31 06:57:55 PM PDT 24 |
17005781 ps |
| T817 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.1501909003 |
|
|
Jul 31 07:00:24 PM PDT 24 |
Jul 31 07:07:02 PM PDT 24 |
111946825482 ps |
| T818 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.896604652 |
|
|
Jul 31 07:00:42 PM PDT 24 |
Jul 31 07:01:38 PM PDT 24 |
1116896108 ps |
| T819 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3729656352 |
|
|
Jul 31 07:05:27 PM PDT 24 |
Jul 31 07:06:35 PM PDT 24 |
852234281 ps |
| T820 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.743195206 |
|
|
Jul 31 07:04:26 PM PDT 24 |
Jul 31 07:04:30 PM PDT 24 |
724147573 ps |
| T821 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3512753282 |
|
|
Jul 31 07:03:53 PM PDT 24 |
Jul 31 07:06:43 PM PDT 24 |
12133863905 ps |
| T822 |
/workspace/coverage/default/9.sram_ctrl_executable.2442212804 |
|
|
Jul 31 06:55:14 PM PDT 24 |
Jul 31 07:16:20 PM PDT 24 |
67853750859 ps |
| T823 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1600919772 |
|
|
Jul 31 07:02:56 PM PDT 24 |
Jul 31 07:10:17 PM PDT 24 |
70874715821 ps |
| T824 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1083389249 |
|
|
Jul 31 06:58:35 PM PDT 24 |
Jul 31 07:06:23 PM PDT 24 |
18495315029 ps |
| T825 |
/workspace/coverage/default/15.sram_ctrl_stress_all.3743084787 |
|
|
Jul 31 06:57:51 PM PDT 24 |
Jul 31 09:19:07 PM PDT 24 |
378862324581 ps |
| T826 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.4213465735 |
|
|
Jul 31 06:57:54 PM PDT 24 |
Jul 31 06:59:18 PM PDT 24 |
3024246519 ps |
| T827 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3286824995 |
|
|
Jul 31 07:00:54 PM PDT 24 |
Jul 31 07:00:57 PM PDT 24 |
368294549 ps |
| T828 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.464051617 |
|
|
Jul 31 07:05:02 PM PDT 24 |
Jul 31 07:21:02 PM PDT 24 |
47479469586 ps |
| T829 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3350193596 |
|
|
Jul 31 06:58:53 PM PDT 24 |
Jul 31 07:01:37 PM PDT 24 |
7217502103 ps |
| T830 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.572126868 |
|
|
Jul 31 06:58:49 PM PDT 24 |
Jul 31 07:00:55 PM PDT 24 |
3902102314 ps |
| T831 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3951841987 |
|
|
Jul 31 07:04:56 PM PDT 24 |
Jul 31 07:25:28 PM PDT 24 |
83816261671 ps |
| T832 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2077729014 |
|
|
Jul 31 07:05:37 PM PDT 24 |
Jul 31 07:11:41 PM PDT 24 |
14633895942 ps |
| T833 |
/workspace/coverage/default/33.sram_ctrl_smoke.4161317536 |
|
|
Jul 31 07:01:39 PM PDT 24 |
Jul 31 07:04:00 PM PDT 24 |
3630977711 ps |
| T834 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.1106642720 |
|
|
Jul 31 07:01:15 PM PDT 24 |
Jul 31 07:03:57 PM PDT 24 |
10518459778 ps |
| T835 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1120846194 |
|
|
Jul 31 07:00:21 PM PDT 24 |
Jul 31 07:02:04 PM PDT 24 |
781872869 ps |
| T836 |
/workspace/coverage/default/19.sram_ctrl_alert_test.42366114 |
|
|
Jul 31 06:58:34 PM PDT 24 |
Jul 31 06:58:35 PM PDT 24 |
36682063 ps |
| T837 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1289561893 |
|
|
Jul 31 07:02:43 PM PDT 24 |
Jul 31 07:10:20 PM PDT 24 |
22164001634 ps |
| T838 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1166808307 |
|
|
Jul 31 06:57:08 PM PDT 24 |
Jul 31 07:13:38 PM PDT 24 |
75045759789 ps |
| T839 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3003581448 |
|
|
Jul 31 07:03:00 PM PDT 24 |
Jul 31 07:06:57 PM PDT 24 |
3470290437 ps |
| T840 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1058883099 |
|
|
Jul 31 07:04:38 PM PDT 24 |
Jul 31 07:17:17 PM PDT 24 |
43162821268 ps |
| T841 |
/workspace/coverage/default/39.sram_ctrl_bijection.975910309 |
|
|
Jul 31 07:03:39 PM PDT 24 |
Jul 31 07:24:45 PM PDT 24 |
395530606882 ps |
| T842 |
/workspace/coverage/default/7.sram_ctrl_executable.3962995363 |
|
|
Jul 31 06:54:48 PM PDT 24 |
Jul 31 07:04:40 PM PDT 24 |
13066924548 ps |
| T843 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2592739448 |
|
|
Jul 31 06:59:12 PM PDT 24 |
Jul 31 07:08:34 PM PDT 24 |
93332904184 ps |
| T844 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2796684707 |
|
|
Jul 31 07:01:14 PM PDT 24 |
Jul 31 07:01:18 PM PDT 24 |
1867353575 ps |
| T845 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1627334364 |
|
|
Jul 31 06:54:38 PM PDT 24 |
Jul 31 07:31:16 PM PDT 24 |
40883497072 ps |
| T846 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3522525520 |
|
|
Jul 31 06:59:25 PM PDT 24 |
Jul 31 07:00:22 PM PDT 24 |
3311292819 ps |
| T136 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1121772023 |
|
|
Jul 31 06:54:13 PM PDT 24 |
Jul 31 06:55:03 PM PDT 24 |
1873123646 ps |
| T54 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3815209926 |
|
|
Jul 31 06:54:51 PM PDT 24 |
Jul 31 06:56:14 PM PDT 24 |
1817749242 ps |
| T137 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4240464767 |
|
|
Jul 31 07:04:40 PM PDT 24 |
Jul 31 07:05:28 PM PDT 24 |
1641784240 ps |
| T847 |
/workspace/coverage/default/41.sram_ctrl_bijection.1387670533 |
|
|
Jul 31 07:04:01 PM PDT 24 |
Jul 31 07:38:17 PM PDT 24 |
86402894729 ps |
| T848 |
/workspace/coverage/default/37.sram_ctrl_smoke.3969483666 |
|
|
Jul 31 07:02:55 PM PDT 24 |
Jul 31 07:04:36 PM PDT 24 |
1935200514 ps |
| T849 |
/workspace/coverage/default/29.sram_ctrl_regwen.2576985167 |
|
|
Jul 31 07:00:38 PM PDT 24 |
Jul 31 07:18:10 PM PDT 24 |
11979785514 ps |
| T850 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1846915201 |
|
|
Jul 31 07:04:35 PM PDT 24 |
Jul 31 07:05:39 PM PDT 24 |
5984668234 ps |
| T851 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.614664678 |
|
|
Jul 31 06:53:20 PM PDT 24 |
Jul 31 06:53:49 PM PDT 24 |
4279954170 ps |
| T852 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.1334167477 |
|
|
Jul 31 06:57:53 PM PDT 24 |
Jul 31 07:00:43 PM PDT 24 |
22027548133 ps |
| T853 |
/workspace/coverage/default/46.sram_ctrl_smoke.1499782348 |
|
|
Jul 31 07:05:20 PM PDT 24 |
Jul 31 07:05:57 PM PDT 24 |
3806714820 ps |
| T854 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.4204048410 |
|
|
Jul 31 07:03:36 PM PDT 24 |
Jul 31 07:05:47 PM PDT 24 |
4028553179 ps |
| T855 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1523152526 |
|
|
Jul 31 06:57:07 PM PDT 24 |
Jul 31 08:38:52 PM PDT 24 |
2213317604308 ps |
| T856 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2400617310 |
|
|
Jul 31 07:05:56 PM PDT 24 |
Jul 31 07:05:59 PM PDT 24 |
1687892571 ps |
| T857 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1969557175 |
|
|
Jul 31 06:58:47 PM PDT 24 |
Jul 31 07:01:21 PM PDT 24 |
4294168000 ps |
| T858 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.698102314 |
|
|
Jul 31 06:59:25 PM PDT 24 |
Jul 31 07:00:47 PM PDT 24 |
12905939978 ps |
| T859 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2827287949 |
|
|
Jul 31 07:05:18 PM PDT 24 |
Jul 31 07:05:19 PM PDT 24 |
30271299 ps |
| T860 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.45144433 |
|
|
Jul 31 06:53:22 PM PDT 24 |
Jul 31 06:53:25 PM PDT 24 |
3043316025 ps |
| T861 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2028396621 |
|
|
Jul 31 06:54:26 PM PDT 24 |
Jul 31 06:57:24 PM PDT 24 |
9905339820 ps |
| T862 |
/workspace/coverage/default/48.sram_ctrl_bijection.2638843900 |
|
|
Jul 31 07:05:48 PM PDT 24 |
Jul 31 07:15:34 PM PDT 24 |
144798362169 ps |
| T863 |
/workspace/coverage/default/33.sram_ctrl_bijection.2393436038 |
|
|
Jul 31 07:01:37 PM PDT 24 |
Jul 31 07:48:34 PM PDT 24 |
115728895023 ps |
| T864 |
/workspace/coverage/default/24.sram_ctrl_executable.1468259294 |
|
|
Jul 31 06:59:26 PM PDT 24 |
Jul 31 07:15:31 PM PDT 24 |
39859557557 ps |
| T865 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1564475691 |
|
|
Jul 31 06:53:04 PM PDT 24 |
Jul 31 06:56:38 PM PDT 24 |
17079935656 ps |
| T866 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.2175551834 |
|
|
Jul 31 06:58:00 PM PDT 24 |
Jul 31 06:58:10 PM PDT 24 |
3994427701 ps |
| T867 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.262819146 |
|
|
Jul 31 07:05:46 PM PDT 24 |
Jul 31 07:28:36 PM PDT 24 |
42160006891 ps |
| T868 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2737266856 |
|
|
Jul 31 06:57:50 PM PDT 24 |
Jul 31 06:57:53 PM PDT 24 |
407168319 ps |
| T869 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2667259721 |
|
|
Jul 31 07:05:48 PM PDT 24 |
Jul 31 07:11:33 PM PDT 24 |
16445014762 ps |
| T870 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.265883329 |
|
|
Jul 31 07:00:35 PM PDT 24 |
Jul 31 07:01:46 PM PDT 24 |
761067827 ps |
| T871 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.182462107 |
|
|
Jul 31 07:01:13 PM PDT 24 |
Jul 31 07:03:47 PM PDT 24 |
4544197864 ps |
| T872 |
/workspace/coverage/default/12.sram_ctrl_alert_test.1956263912 |
|
|
Jul 31 06:57:50 PM PDT 24 |
Jul 31 06:57:50 PM PDT 24 |
16302780 ps |
| T873 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1258091442 |
|
|
Jul 31 06:57:49 PM PDT 24 |
Jul 31 07:12:22 PM PDT 24 |
15452473198 ps |
| T874 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2800590110 |
|
|
Jul 31 06:58:35 PM PDT 24 |
Jul 31 07:01:38 PM PDT 24 |
10235957125 ps |
| T875 |
/workspace/coverage/default/3.sram_ctrl_stress_all.1904076373 |
|
|
Jul 31 06:54:02 PM PDT 24 |
Jul 31 08:23:03 PM PDT 24 |
1048968462100 ps |
| T876 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.729442971 |
|
|
Jul 31 07:00:34 PM PDT 24 |
Jul 31 07:03:43 PM PDT 24 |
5093025011 ps |
| T877 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3313684496 |
|
|
Jul 31 06:55:05 PM PDT 24 |
Jul 31 06:56:27 PM PDT 24 |
2789960834 ps |
| T878 |
/workspace/coverage/default/9.sram_ctrl_bijection.3832622783 |
|
|
Jul 31 06:55:07 PM PDT 24 |
Jul 31 07:11:09 PM PDT 24 |
276974190041 ps |
| T879 |
/workspace/coverage/default/44.sram_ctrl_executable.805219773 |
|
|
Jul 31 07:04:59 PM PDT 24 |
Jul 31 07:13:50 PM PDT 24 |
16010257314 ps |
| T880 |
/workspace/coverage/default/9.sram_ctrl_smoke.2823565450 |
|
|
Jul 31 06:55:00 PM PDT 24 |
Jul 31 06:56:04 PM PDT 24 |
4774212004 ps |
| T881 |
/workspace/coverage/default/49.sram_ctrl_executable.1596165329 |
|
|
Jul 31 07:06:18 PM PDT 24 |
Jul 31 07:11:37 PM PDT 24 |
4938439104 ps |
| T882 |
/workspace/coverage/default/23.sram_ctrl_smoke.568469386 |
|
|
Jul 31 06:59:06 PM PDT 24 |
Jul 31 06:59:21 PM PDT 24 |
4387011750 ps |
| T883 |
/workspace/coverage/default/0.sram_ctrl_smoke.2874611262 |
|
|
Jul 31 06:52:59 PM PDT 24 |
Jul 31 06:53:16 PM PDT 24 |
923306524 ps |
| T884 |
/workspace/coverage/default/1.sram_ctrl_executable.3900082079 |
|
|
Jul 31 06:53:22 PM PDT 24 |
Jul 31 07:12:11 PM PDT 24 |
16272562012 ps |
| T885 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2063527215 |
|
|
Jul 31 06:58:36 PM PDT 24 |
Jul 31 07:05:46 PM PDT 24 |
97234329596 ps |
| T886 |
/workspace/coverage/default/9.sram_ctrl_regwen.1717593431 |
|
|
Jul 31 06:55:13 PM PDT 24 |
Jul 31 07:13:17 PM PDT 24 |
52698180188 ps |
| T887 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1976377688 |
|
|
Jul 31 06:57:44 PM PDT 24 |
Jul 31 06:58:03 PM PDT 24 |
7022297433 ps |
| T888 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.1514080895 |
|
|
Jul 31 06:57:54 PM PDT 24 |
Jul 31 06:58:06 PM PDT 24 |
3123095256 ps |
| T889 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1113803897 |
|
|
Jul 31 07:02:51 PM PDT 24 |
Jul 31 07:16:00 PM PDT 24 |
38799936500 ps |
| T890 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2675237080 |
|
|
Jul 31 07:05:02 PM PDT 24 |
Jul 31 07:05:05 PM PDT 24 |
403001424 ps |
| T891 |
/workspace/coverage/default/13.sram_ctrl_bijection.4110212101 |
|
|
Jul 31 06:57:47 PM PDT 24 |
Jul 31 07:12:14 PM PDT 24 |
38604309485 ps |
| T892 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2804731206 |
|
|
Jul 31 06:52:56 PM PDT 24 |
Jul 31 07:24:32 PM PDT 24 |
51266538082 ps |
| T893 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.549122114 |
|
|
Jul 31 07:05:16 PM PDT 24 |
Jul 31 07:20:02 PM PDT 24 |
79038990838 ps |
| T894 |
/workspace/coverage/default/29.sram_ctrl_stress_all.280695037 |
|
|
Jul 31 07:00:43 PM PDT 24 |
Jul 31 07:55:41 PM PDT 24 |
72542673140 ps |
| T895 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.899881090 |
|
|
Jul 31 07:05:02 PM PDT 24 |
Jul 31 07:05:54 PM PDT 24 |
21919315330 ps |
| T896 |
/workspace/coverage/default/1.sram_ctrl_partial_access.3045905519 |
|
|
Jul 31 06:53:07 PM PDT 24 |
Jul 31 06:53:38 PM PDT 24 |
2881162496 ps |
| T897 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1151854437 |
|
|
Jul 31 06:54:26 PM PDT 24 |
Jul 31 06:55:05 PM PDT 24 |
2954200557 ps |
| T898 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1776582978 |
|
|
Jul 31 07:02:59 PM PDT 24 |
Jul 31 07:03:02 PM PDT 24 |
370790466 ps |
| T899 |
/workspace/coverage/default/41.sram_ctrl_partial_access.687294063 |
|
|
Jul 31 07:04:04 PM PDT 24 |
Jul 31 07:04:16 PM PDT 24 |
935741329 ps |
| T900 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1711776989 |
|
|
Jul 31 06:53:43 PM PDT 24 |
Jul 31 06:54:01 PM PDT 24 |
595014081 ps |
| T901 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.277594921 |
|
|
Jul 31 06:57:56 PM PDT 24 |
Jul 31 06:58:14 PM PDT 24 |
5250851766 ps |
| T902 |
/workspace/coverage/default/29.sram_ctrl_partial_access.4065847561 |
|
|
Jul 31 07:00:39 PM PDT 24 |
Jul 31 07:01:23 PM PDT 24 |
748291800 ps |
| T903 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.1136264205 |
|
|
Jul 31 06:57:52 PM PDT 24 |
Jul 31 06:59:28 PM PDT 24 |
761901031 ps |
| T904 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1228457181 |
|
|
Jul 31 06:54:25 PM PDT 24 |
Jul 31 06:54:36 PM PDT 24 |
734667732 ps |
| T905 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.2272990252 |
|
|
Jul 31 06:57:41 PM PDT 24 |
Jul 31 06:58:44 PM PDT 24 |
1704811363 ps |
| T906 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.4035495784 |
|
|
Jul 31 06:57:09 PM PDT 24 |
Jul 31 07:07:47 PM PDT 24 |
11786391317 ps |
| T907 |
/workspace/coverage/default/30.sram_ctrl_smoke.2398451046 |
|
|
Jul 31 07:00:47 PM PDT 24 |
Jul 31 07:01:08 PM PDT 24 |
14061066673 ps |
| T908 |
/workspace/coverage/default/47.sram_ctrl_regwen.4144099969 |
|
|
Jul 31 07:05:41 PM PDT 24 |
Jul 31 07:27:53 PM PDT 24 |
124900597858 ps |
| T909 |
/workspace/coverage/default/12.sram_ctrl_bijection.2465068309 |
|
|
Jul 31 06:57:41 PM PDT 24 |
Jul 31 07:13:35 PM PDT 24 |
27453777048 ps |
| T910 |
/workspace/coverage/default/39.sram_ctrl_smoke.3850166511 |
|
|
Jul 31 07:03:24 PM PDT 24 |
Jul 31 07:03:37 PM PDT 24 |
2126929067 ps |
| T911 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3125982580 |
|
|
Jul 31 07:00:00 PM PDT 24 |
Jul 31 07:01:24 PM PDT 24 |
3647014574 ps |
| T912 |
/workspace/coverage/default/42.sram_ctrl_executable.3137636680 |
|
|
Jul 31 07:04:25 PM PDT 24 |
Jul 31 07:18:25 PM PDT 24 |
54669428561 ps |
| T913 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1035180327 |
|
|
Jul 31 06:57:45 PM PDT 24 |
Jul 31 06:58:17 PM PDT 24 |
25138781350 ps |
| T914 |
/workspace/coverage/default/40.sram_ctrl_smoke.1036774301 |
|
|
Jul 31 07:03:44 PM PDT 24 |
Jul 31 07:05:52 PM PDT 24 |
1875625084 ps |
| T915 |
/workspace/coverage/default/3.sram_ctrl_partial_access.3544988966 |
|
|
Jul 31 06:53:50 PM PDT 24 |
Jul 31 06:54:12 PM PDT 24 |
432966882 ps |
| T916 |
/workspace/coverage/default/26.sram_ctrl_smoke.3548862254 |
|
|
Jul 31 06:59:47 PM PDT 24 |
Jul 31 07:01:28 PM PDT 24 |
1677430366 ps |
| T917 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3613305085 |
|
|
Jul 31 06:59:06 PM PDT 24 |
Jul 31 07:04:14 PM PDT 24 |
18070191104 ps |
| T918 |
/workspace/coverage/default/28.sram_ctrl_regwen.2293359180 |
|
|
Jul 31 07:00:31 PM PDT 24 |
Jul 31 07:01:41 PM PDT 24 |
12092983070 ps |
| T919 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3678185155 |
|
|
Jul 31 06:57:53 PM PDT 24 |
Jul 31 06:58:46 PM PDT 24 |
1630286394 ps |
| T920 |
/workspace/coverage/default/37.sram_ctrl_partial_access.4154115578 |
|
|
Jul 31 07:03:00 PM PDT 24 |
Jul 31 07:04:28 PM PDT 24 |
2011702704 ps |
| T921 |
/workspace/coverage/default/31.sram_ctrl_executable.2333157765 |
|
|
Jul 31 07:01:14 PM PDT 24 |
Jul 31 07:36:40 PM PDT 24 |
39345558729 ps |
| T922 |
/workspace/coverage/default/42.sram_ctrl_smoke.1535971943 |
|
|
Jul 31 07:04:13 PM PDT 24 |
Jul 31 07:04:19 PM PDT 24 |
3133541486 ps |
| T923 |
/workspace/coverage/default/23.sram_ctrl_stress_all.1694910742 |
|
|
Jul 31 06:59:17 PM PDT 24 |
Jul 31 07:18:05 PM PDT 24 |
49360313327 ps |
| T924 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3949153602 |
|
|
Jul 31 06:52:56 PM PDT 24 |
Jul 31 06:55:37 PM PDT 24 |
12306369734 ps |
| T925 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.2522022856 |
|
|
Jul 31 07:04:05 PM PDT 24 |
Jul 31 07:04:09 PM PDT 24 |
362800895 ps |
| T926 |
/workspace/coverage/default/17.sram_ctrl_bijection.2743324767 |
|
|
Jul 31 06:57:59 PM PDT 24 |
Jul 31 07:08:45 PM PDT 24 |
18298647855 ps |
| T927 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.4190984086 |
|
|
Jul 31 07:00:13 PM PDT 24 |
Jul 31 07:02:59 PM PDT 24 |
23178197352 ps |
| T928 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.780655102 |
|
|
Jul 31 06:58:54 PM PDT 24 |
Jul 31 07:02:55 PM PDT 24 |
4133099555 ps |
| T929 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3174582167 |
|
|
Jul 31 06:59:37 PM PDT 24 |
Jul 31 07:02:42 PM PDT 24 |
2899403708 ps |
| T930 |
/workspace/coverage/default/37.sram_ctrl_executable.1270674298 |
|
|
Jul 31 07:03:01 PM PDT 24 |
Jul 31 07:26:05 PM PDT 24 |
130689551425 ps |
| T931 |
/workspace/coverage/default/21.sram_ctrl_alert_test.2682499453 |
|
|
Jul 31 06:58:54 PM PDT 24 |
Jul 31 06:58:54 PM PDT 24 |
30469932 ps |
| T932 |
/workspace/coverage/default/5.sram_ctrl_bijection.1528237297 |
|
|
Jul 31 06:54:12 PM PDT 24 |
Jul 31 07:22:44 PM PDT 24 |
93648462332 ps |
| T933 |
/workspace/coverage/default/7.sram_ctrl_smoke.326274133 |
|
|
Jul 31 06:54:44 PM PDT 24 |
Jul 31 06:55:28 PM PDT 24 |
3151120883 ps |
| T934 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3387306312 |
|
|
Jul 31 07:05:34 PM PDT 24 |
Jul 31 07:09:32 PM PDT 24 |
22239179815 ps |
| T935 |
/workspace/coverage/default/37.sram_ctrl_alert_test.3288731568 |
|
|
Jul 31 07:03:05 PM PDT 24 |
Jul 31 07:03:06 PM PDT 24 |
32925033 ps |
| T936 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.1279723766 |
|
|
Jul 31 06:58:30 PM PDT 24 |
Jul 31 07:01:39 PM PDT 24 |
10700685871 ps |
| T937 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.4150506871 |
|
|
Jul 31 06:54:07 PM PDT 24 |
Jul 31 06:54:24 PM PDT 24 |
2298397408 ps |
| T938 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2772587268 |
|
|
Jul 31 07:01:43 PM PDT 24 |
Jul 31 07:06:04 PM PDT 24 |
4616556715 ps |
| T939 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4179890455 |
|
|
Jul 31 07:03:02 PM PDT 24 |
Jul 31 07:03:46 PM PDT 24 |
794881378 ps |
| T940 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2100366141 |
|
|
Jul 31 06:58:48 PM PDT 24 |
Jul 31 06:59:32 PM PDT 24 |
14589214122 ps |
| T941 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2956163291 |
|
|
Jul 31 07:01:19 PM PDT 24 |
Jul 31 07:07:37 PM PDT 24 |
61058285525 ps |
| T942 |
/workspace/coverage/default/11.sram_ctrl_executable.3562471472 |
|
|
Jul 31 06:57:39 PM PDT 24 |
Jul 31 07:13:43 PM PDT 24 |
77706625919 ps |
| T943 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2251269417 |
|
|
Jul 31 07:05:35 PM PDT 24 |
Jul 31 07:47:35 PM PDT 24 |
30983494322 ps |
| T944 |
/workspace/coverage/default/45.sram_ctrl_regwen.1300455052 |
|
|
Jul 31 07:05:15 PM PDT 24 |
Jul 31 07:06:11 PM PDT 24 |
13782362770 ps |
| T945 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.2207452554 |
|
|
Jul 31 06:53:56 PM PDT 24 |
Jul 31 06:54:26 PM PDT 24 |
19401819228 ps |
| T946 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2965565021 |
|
|
Jul 31 06:58:21 PM PDT 24 |
Jul 31 06:59:52 PM PDT 24 |
2951915912 ps |
| T947 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1477419515 |
|
|
Jul 31 07:05:47 PM PDT 24 |
Jul 31 07:05:48 PM PDT 24 |
23529823 ps |
| T83 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2911624332 |
|
|
Jul 31 05:18:56 PM PDT 24 |
Jul 31 05:18:57 PM PDT 24 |
17089611 ps |
| T84 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2110787145 |
|
|
Jul 31 05:18:56 PM PDT 24 |
Jul 31 05:18:56 PM PDT 24 |
22066870 ps |
| T85 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3036478696 |
|
|
Jul 31 05:18:57 PM PDT 24 |
Jul 31 05:19:00 PM PDT 24 |
338648677 ps |
| T124 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.362576203 |
|
|
Jul 31 05:18:54 PM PDT 24 |
Jul 31 05:18:55 PM PDT 24 |
127322476 ps |
| T80 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3350698010 |
|
|
Jul 31 05:18:56 PM PDT 24 |
Jul 31 05:18:58 PM PDT 24 |
164116856 ps |
| T93 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.474147436 |
|
|
Jul 31 05:18:48 PM PDT 24 |
Jul 31 05:18:50 PM PDT 24 |
46457279 ps |
| T125 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3641784383 |
|
|
Jul 31 05:19:00 PM PDT 24 |
Jul 31 05:19:01 PM PDT 24 |
52091980 ps |
| T81 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.256470491 |
|
|
Jul 31 05:19:03 PM PDT 24 |
Jul 31 05:19:05 PM PDT 24 |
252915293 ps |
| T94 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3974583903 |
|
|
Jul 31 05:19:05 PM PDT 24 |
Jul 31 05:19:37 PM PDT 24 |
5071033310 ps |
| T126 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3766120588 |
|
|
Jul 31 05:18:54 PM PDT 24 |
Jul 31 05:18:55 PM PDT 24 |
24370919 ps |
| T82 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3835917758 |
|
|
Jul 31 05:18:59 PM PDT 24 |
Jul 31 05:19:01 PM PDT 24 |
153938780 ps |
| T154 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4048473373 |
|
|
Jul 31 05:19:04 PM PDT 24 |
Jul 31 05:19:06 PM PDT 24 |
664565252 ps |
| T127 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1051285411 |
|
|
Jul 31 05:19:27 PM PDT 24 |
Jul 31 05:19:59 PM PDT 24 |
15404783661 ps |
| T128 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1034897935 |
|
|
Jul 31 05:18:56 PM PDT 24 |
Jul 31 05:18:57 PM PDT 24 |
54452342 ps |
| T948 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2995962495 |
|
|
Jul 31 05:18:52 PM PDT 24 |
Jul 31 05:18:57 PM PDT 24 |
352492032 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3191871766 |
|
|
Jul 31 05:18:55 PM PDT 24 |
Jul 31 05:19:00 PM PDT 24 |
369039310 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.139606537 |
|
|
Jul 31 05:18:57 PM PDT 24 |
Jul 31 05:19:03 PM PDT 24 |
537477691 ps |
| T155 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4063269162 |
|
|
Jul 31 05:18:54 PM PDT 24 |
Jul 31 05:18:57 PM PDT 24 |
262466014 ps |
| T951 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.229976318 |
|
|
Jul 31 05:18:54 PM PDT 24 |
Jul 31 05:18:56 PM PDT 24 |
42035809 ps |
| T952 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3248137643 |
|
|
Jul 31 05:18:55 PM PDT 24 |
Jul 31 05:19:00 PM PDT 24 |
255071524 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1590995550 |
|
|
Jul 31 05:18:58 PM PDT 24 |
Jul 31 05:19:04 PM PDT 24 |
36346180 ps |
| T954 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2692097600 |
|
|
Jul 31 05:19:00 PM PDT 24 |
Jul 31 05:19:02 PM PDT 24 |
118994633 ps |
| T95 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3290651573 |
|
|
Jul 31 05:18:52 PM PDT 24 |
Jul 31 05:18:53 PM PDT 24 |
20955259 ps |
| T96 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2634732517 |
|
|
Jul 31 05:19:05 PM PDT 24 |
Jul 31 05:19:06 PM PDT 24 |
17695540 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1726034678 |
|
|
Jul 31 05:18:55 PM PDT 24 |
Jul 31 05:18:56 PM PDT 24 |
98846075 ps |
| T97 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4109108866 |
|
|
Jul 31 05:18:54 PM PDT 24 |
Jul 31 05:18:54 PM PDT 24 |
29773500 ps |
| T956 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.644916105 |
|
|
Jul 31 05:18:59 PM PDT 24 |
Jul 31 05:19:07 PM PDT 24 |
118477228 ps |
| T957 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.141328644 |
|
|
Jul 31 05:18:54 PM PDT 24 |
Jul 31 05:18:57 PM PDT 24 |
360488945 ps |
| T151 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1597547078 |
|
|
Jul 31 05:19:07 PM PDT 24 |
Jul 31 05:19:09 PM PDT 24 |
453558756 ps |
| T958 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2928534363 |
|
|
Jul 31 05:18:54 PM PDT 24 |
Jul 31 05:18:58 PM PDT 24 |
349802073 ps |
| T959 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3711035341 |
|
|
Jul 31 05:19:01 PM PDT 24 |
Jul 31 05:19:02 PM PDT 24 |
138240431 ps |
| T98 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4055729238 |
|
|
Jul 31 05:18:52 PM PDT 24 |
Jul 31 05:18:52 PM PDT 24 |
21522091 ps |
| T99 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.691714928 |
|
|
Jul 31 05:18:54 PM PDT 24 |
Jul 31 05:19:20 PM PDT 24 |
4059222029 ps |
| T149 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.917793404 |
|
|
Jul 31 05:18:55 PM PDT 24 |
Jul 31 05:18:57 PM PDT 24 |
634749251 ps |
| T157 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4212709804 |
|
|
Jul 31 05:19:00 PM PDT 24 |
Jul 31 05:19:01 PM PDT 24 |
132105224 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.78057055 |
|
|
Jul 31 05:18:55 PM PDT 24 |
Jul 31 05:18:56 PM PDT 24 |
29823109 ps |
| T961 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2399964741 |
|
|
Jul 31 05:19:01 PM PDT 24 |
Jul 31 05:19:02 PM PDT 24 |
13924331 ps |
| T962 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3528980240 |
|
|
Jul 31 05:19:01 PM PDT 24 |
Jul 31 05:19:06 PM PDT 24 |
1143657048 ps |
| T963 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1750355784 |
|
|
Jul 31 05:19:04 PM PDT 24 |
Jul 31 05:19:05 PM PDT 24 |
40395253 ps |
| T100 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3695080899 |
|
|
Jul 31 05:19:06 PM PDT 24 |
Jul 31 05:19:46 PM PDT 24 |
52875620981 ps |
| T152 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2685519265 |
|
|
Jul 31 05:18:56 PM PDT 24 |
Jul 31 05:18:58 PM PDT 24 |
102682704 ps |
| T102 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.475456999 |
|
|
Jul 31 05:18:55 PM PDT 24 |
Jul 31 05:19:51 PM PDT 24 |
28198882961 ps |
| T964 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.409018406 |
|
|
Jul 31 05:19:25 PM PDT 24 |
Jul 31 05:19:52 PM PDT 24 |
15362209714 ps |
| T153 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1234314950 |
|
|
Jul 31 05:19:02 PM PDT 24 |
Jul 31 05:19:05 PM PDT 24 |
247293352 ps |
| T965 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.514660449 |
|
|
Jul 31 05:19:05 PM PDT 24 |
Jul 31 05:19:06 PM PDT 24 |
56951832 ps |
| T147 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3981788162 |
|
|
Jul 31 05:18:59 PM PDT 24 |
Jul 31 05:19:01 PM PDT 24 |
550984751 ps |
| T966 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3868488623 |
|
|
Jul 31 05:19:16 PM PDT 24 |
Jul 31 05:19:17 PM PDT 24 |
39430083 ps |
| T967 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1418699055 |
|
|
Jul 31 05:19:00 PM PDT 24 |
Jul 31 05:19:02 PM PDT 24 |
23917685 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1300494693 |
|
|
Jul 31 05:18:56 PM PDT 24 |
Jul 31 05:18:57 PM PDT 24 |
26573996 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3606143158 |
|
|
Jul 31 05:19:00 PM PDT 24 |
Jul 31 05:19:00 PM PDT 24 |
13854983 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1582675057 |
|
|
Jul 31 05:18:57 PM PDT 24 |
Jul 31 05:19:01 PM PDT 24 |
1441608881 ps |
| T103 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.601711845 |
|
|
Jul 31 05:19:01 PM PDT 24 |
Jul 31 05:19:32 PM PDT 24 |
16731606474 ps |
| T104 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.356248480 |
|
|
Jul 31 05:19:03 PM PDT 24 |
Jul 31 05:19:57 PM PDT 24 |
7587719689 ps |
| T971 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1160557746 |
|
|
Jul 31 05:19:00 PM PDT 24 |
Jul 31 05:19:01 PM PDT 24 |
15135008 ps |
| T972 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3077770228 |
|
|
Jul 31 05:19:06 PM PDT 24 |
Jul 31 05:19:11 PM PDT 24 |
373597064 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.766226068 |
|
|
Jul 31 05:19:16 PM PDT 24 |
Jul 31 05:19:27 PM PDT 24 |
46932985 ps |
| T116 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2565903967 |
|
|
Jul 31 05:18:56 PM PDT 24 |
Jul 31 05:18:56 PM PDT 24 |
39072240 ps |
| T974 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3510774630 |
|
|
Jul 31 05:18:56 PM PDT 24 |
Jul 31 05:19:50 PM PDT 24 |
21534191188 ps |
| T975 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1539448931 |
|
|
Jul 31 05:18:58 PM PDT 24 |
Jul 31 05:19:02 PM PDT 24 |
1539488868 ps |
| T105 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3034617312 |
|
|
Jul 31 05:19:06 PM PDT 24 |
Jul 31 05:19:07 PM PDT 24 |
23802851 ps |
| T976 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4122771461 |
|
|
Jul 31 05:18:52 PM PDT 24 |
Jul 31 05:18:56 PM PDT 24 |
357616383 ps |
| T977 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3794964332 |
|
|
Jul 31 05:18:53 PM PDT 24 |
Jul 31 05:18:58 PM PDT 24 |
714110993 ps |
| T978 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3359327007 |
|
|
Jul 31 05:19:22 PM PDT 24 |
Jul 31 05:19:25 PM PDT 24 |
1549004080 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3938168666 |
|
|
Jul 31 05:18:53 PM PDT 24 |
Jul 31 05:19:22 PM PDT 24 |
13637238913 ps |
| T980 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1472789289 |
|
|
Jul 31 05:18:57 PM PDT 24 |
Jul 31 05:19:07 PM PDT 24 |
1946515635 ps |
| T981 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3143866516 |
|
|
Jul 31 05:19:11 PM PDT 24 |
Jul 31 05:19:11 PM PDT 24 |
20831155 ps |
| T117 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4043385571 |
|
|
Jul 31 05:19:00 PM PDT 24 |
Jul 31 05:19:01 PM PDT 24 |
18755454 ps |
| T106 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.398845551 |
|
|
Jul 31 05:18:54 PM PDT 24 |
Jul 31 05:19:48 PM PDT 24 |
7086469485 ps |
| T150 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.719460168 |
|
|
Jul 31 05:18:51 PM PDT 24 |
Jul 31 05:18:52 PM PDT 24 |
106643029 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2226710449 |
|
|
Jul 31 05:18:52 PM PDT 24 |
Jul 31 05:18:56 PM PDT 24 |
360123523 ps |
| T983 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3602581591 |
|
|
Jul 31 05:18:55 PM PDT 24 |
Jul 31 05:18:59 PM PDT 24 |
1548075176 ps |
| T984 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4113077235 |
|
|
Jul 31 05:19:00 PM PDT 24 |
Jul 31 05:19:01 PM PDT 24 |
42681719 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1106396048 |
|
|
Jul 31 05:18:55 PM PDT 24 |
Jul 31 05:19:00 PM PDT 24 |
1134157866 ps |
| T107 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2731991841 |
|
|
Jul 31 05:19:08 PM PDT 24 |
Jul 31 05:19:43 PM PDT 24 |
36961721597 ps |
| T986 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4116569733 |
|
|
Jul 31 05:19:33 PM PDT 24 |
Jul 31 05:19:34 PM PDT 24 |
18153941 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4209127533 |
|
|
Jul 31 05:18:51 PM PDT 24 |
Jul 31 05:18:52 PM PDT 24 |
37162981 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1306201735 |
|
|
Jul 31 05:18:48 PM PDT 24 |
Jul 31 05:18:49 PM PDT 24 |
28001702 ps |
| T108 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1721025398 |
|
|
Jul 31 05:19:00 PM PDT 24 |
Jul 31 05:19:30 PM PDT 24 |
14771006420 ps |
| T109 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2788120918 |
|
|
Jul 31 05:18:58 PM PDT 24 |
Jul 31 05:18:59 PM PDT 24 |
35626033 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.343920083 |
|
|
Jul 31 05:18:56 PM PDT 24 |
Jul 31 05:18:59 PM PDT 24 |
327192447 ps |
| T156 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2786199409 |
|
|
Jul 31 05:19:17 PM PDT 24 |
Jul 31 05:19:19 PM PDT 24 |
320398903 ps |
| T990 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.207139195 |
|
|
Jul 31 05:18:53 PM PDT 24 |
Jul 31 05:18:57 PM PDT 24 |
36643140 ps |
| T118 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2891028740 |
|
|
Jul 31 05:19:06 PM PDT 24 |
Jul 31 05:19:06 PM PDT 24 |
31462797 ps |
| T991 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1559925694 |
|
|
Jul 31 05:19:01 PM PDT 24 |
Jul 31 05:19:05 PM PDT 24 |
701388151 ps |
| T992 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.219770655 |
|
|
Jul 31 05:19:08 PM PDT 24 |
Jul 31 05:19:08 PM PDT 24 |
159442893 ps |
| T993 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.903175855 |
|
|
Jul 31 05:19:06 PM PDT 24 |
Jul 31 05:19:10 PM PDT 24 |
270906754 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.974707217 |
|
|
Jul 31 05:19:03 PM PDT 24 |
Jul 31 05:19:06 PM PDT 24 |
618070806 ps |
| T148 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1149188426 |
|
|
Jul 31 05:19:01 PM PDT 24 |
Jul 31 05:19:05 PM PDT 24 |
2984412419 ps |
| T995 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1014547444 |
|
|
Jul 31 05:19:03 PM PDT 24 |
Jul 31 05:19:54 PM PDT 24 |
7299914851 ps |
| T996 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1420743200 |
|
|
Jul 31 05:19:01 PM PDT 24 |
Jul 31 05:19:05 PM PDT 24 |
544452307 ps |
| T119 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2775639464 |
|
|
Jul 31 05:19:23 PM PDT 24 |
Jul 31 05:20:17 PM PDT 24 |
12653853301 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1056927899 |
|
|
Jul 31 05:18:51 PM PDT 24 |
Jul 31 05:18:52 PM PDT 24 |
19216874 ps |
| T120 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.210288298 |
|
|
Jul 31 05:19:01 PM PDT 24 |
Jul 31 05:19:34 PM PDT 24 |
19462802290 ps |
| T998 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1410310452 |
|
|
Jul 31 05:19:33 PM PDT 24 |
Jul 31 05:19:37 PM PDT 24 |
80105155 ps |
| T121 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3624740067 |
|
|
Jul 31 05:18:53 PM PDT 24 |
Jul 31 05:19:42 PM PDT 24 |
7457221609 ps |
| T999 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3075389591 |
|
|
Jul 31 05:18:56 PM PDT 24 |
Jul 31 05:18:57 PM PDT 24 |
14039182 ps |
| T1000 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.470137087 |
|
|
Jul 31 05:19:10 PM PDT 24 |
Jul 31 05:19:14 PM PDT 24 |
43180490 ps |
| T1001 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1582135713 |
|
|
Jul 31 05:19:01 PM PDT 24 |
Jul 31 05:19:04 PM PDT 24 |
67498427 ps |
| T1002 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1925667218 |
|
|
Jul 31 05:18:49 PM PDT 24 |
Jul 31 05:18:52 PM PDT 24 |
279874997 ps |
| T1003 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3550163667 |
|
|
Jul 31 05:19:07 PM PDT 24 |
Jul 31 05:19:11 PM PDT 24 |
1739547651 ps |
| T158 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1481424700 |
|
|
Jul 31 05:18:54 PM PDT 24 |
Jul 31 05:18:56 PM PDT 24 |
349175376 ps |
| T1004 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.510873719 |
|
|
Jul 31 05:18:57 PM PDT 24 |
Jul 31 05:18:59 PM PDT 24 |
196762269 ps |