SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.92 | 99.19 | 94.15 | 99.72 | 100.00 | 95.79 | 99.12 | 97.44 |
T1005 | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1815915218 | Jul 31 05:18:56 PM PDT 24 | Jul 31 05:18:56 PM PDT 24 | 61724382 ps | ||
T1006 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3811999492 | Jul 31 05:18:52 PM PDT 24 | Jul 31 05:18:56 PM PDT 24 | 362595394 ps | ||
T1007 | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2474931933 | Jul 31 05:18:53 PM PDT 24 | Jul 31 05:18:56 PM PDT 24 | 729691097 ps | ||
T1008 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2146314983 | Jul 31 05:19:04 PM PDT 24 | Jul 31 05:19:11 PM PDT 24 | 37290145 ps | ||
T1009 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3277740873 | Jul 31 05:19:21 PM PDT 24 | Jul 31 05:19:25 PM PDT 24 | 226539738 ps | ||
T159 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3643510263 | Jul 31 05:18:54 PM PDT 24 | Jul 31 05:18:58 PM PDT 24 | 1762254210 ps | ||
T1010 | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1481797982 | Jul 31 05:18:54 PM PDT 24 | Jul 31 05:18:55 PM PDT 24 | 92004107 ps | ||
T1011 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3160713857 | Jul 31 05:19:06 PM PDT 24 | Jul 31 05:19:09 PM PDT 24 | 35552965 ps | ||
T1012 | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3612612405 | Jul 31 05:18:51 PM PDT 24 | Jul 31 05:19:20 PM PDT 24 | 7432808922 ps | ||
T1013 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2821681238 | Jul 31 05:18:57 PM PDT 24 | Jul 31 05:19:00 PM PDT 24 | 650585655 ps | ||
T1014 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.902973442 | Jul 31 05:19:33 PM PDT 24 | Jul 31 05:19:34 PM PDT 24 | 12270097 ps | ||
T122 | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1232672557 | Jul 31 05:19:04 PM PDT 24 | Jul 31 05:20:02 PM PDT 24 | 15119167725 ps | ||
T1015 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3186414923 | Jul 31 05:19:18 PM PDT 24 | Jul 31 05:19:19 PM PDT 24 | 35255340 ps | ||
T1016 | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.335796351 | Jul 31 05:19:03 PM PDT 24 | Jul 31 05:19:04 PM PDT 24 | 27846700 ps | ||
T1017 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.116839132 | Jul 31 05:18:59 PM PDT 24 | Jul 31 05:19:02 PM PDT 24 | 302242333 ps | ||
T1018 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3363625367 | Jul 31 05:19:04 PM PDT 24 | Jul 31 05:19:05 PM PDT 24 | 21153199 ps | ||
T1019 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2135345392 | Jul 31 05:18:55 PM PDT 24 | Jul 31 05:18:55 PM PDT 24 | 22083371 ps | ||
T1020 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3029858427 | Jul 31 05:19:00 PM PDT 24 | Jul 31 05:19:01 PM PDT 24 | 38521185 ps | ||
T1021 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2748622497 | Jul 31 05:18:54 PM PDT 24 | Jul 31 05:18:54 PM PDT 24 | 38018023 ps | ||
T1022 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.827957925 | Jul 31 05:19:24 PM PDT 24 | Jul 31 05:19:24 PM PDT 24 | 13183944 ps | ||
T1023 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4107608868 | Jul 31 05:18:53 PM PDT 24 | Jul 31 05:18:55 PM PDT 24 | 511222613 ps | ||
T1024 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2710484660 | Jul 31 05:19:01 PM PDT 24 | Jul 31 05:19:04 PM PDT 24 | 21571646 ps | ||
T1025 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4002197658 | Jul 31 05:19:08 PM PDT 24 | Jul 31 05:19:12 PM PDT 24 | 361949911 ps | ||
T1026 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3852229734 | Jul 31 05:18:59 PM PDT 24 | Jul 31 05:19:02 PM PDT 24 | 1166287546 ps | ||
T1027 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.34865540 | Jul 31 05:19:03 PM PDT 24 | Jul 31 05:19:06 PM PDT 24 | 44331168 ps | ||
T1028 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2562931701 | Jul 31 05:18:56 PM PDT 24 | Jul 31 05:18:57 PM PDT 24 | 31787795 ps | ||
T1029 | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.418766163 | Jul 31 05:18:54 PM PDT 24 | Jul 31 05:19:20 PM PDT 24 | 3734188728 ps | ||
T114 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1208582656 | Jul 31 05:18:59 PM PDT 24 | Jul 31 05:19:00 PM PDT 24 | 13940333 ps | ||
T1030 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2119449722 | Jul 31 05:19:03 PM PDT 24 | Jul 31 05:19:09 PM PDT 24 | 324761667 ps | ||
T115 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1861805044 | Jul 31 05:18:59 PM PDT 24 | Jul 31 05:19:00 PM PDT 24 | 72220845 ps | ||
T1031 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1425604192 | Jul 31 05:19:14 PM PDT 24 | Jul 31 05:19:14 PM PDT 24 | 22734780 ps | ||
T1032 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3808667628 | Jul 31 05:18:53 PM PDT 24 | Jul 31 05:18:54 PM PDT 24 | 31971926 ps |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.3728066903 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 251725418767 ps |
CPU time | 4808.44 seconds |
Started | Jul 31 07:05:39 PM PDT 24 |
Finished | Jul 31 08:25:48 PM PDT 24 |
Peak memory | 373260 kb |
Host | smart-653ce94c-7349-4f8c-a9ed-28d0f303cdd9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728066903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.3728066903 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2967690603 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1776840564 ps |
CPU time | 55.79 seconds |
Started | Jul 31 06:57:48 PM PDT 24 |
Finished | Jul 31 06:58:44 PM PDT 24 |
Peak memory | 211580 kb |
Host | smart-31217e9e-187f-48f3-a370-a3fbb0b1b6db |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2967690603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2967690603 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3283601863 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 11954270181 ps |
CPU time | 43.98 seconds |
Started | Jul 31 07:00:30 PM PDT 24 |
Finished | Jul 31 07:01:14 PM PDT 24 |
Peak memory | 237020 kb |
Host | smart-e4237513-5ab8-4aaf-b7d1-bda4a1f7d771 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3283601863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.3283601863 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.4065694653 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 165737049975 ps |
CPU time | 2461.18 seconds |
Started | Jul 31 06:53:27 PM PDT 24 |
Finished | Jul 31 07:34:29 PM PDT 24 |
Peak memory | 373964 kb |
Host | smart-b726cfc5-f688-4f28-9f42-c25997e7c9cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065694653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.4065694653 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.256470491 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 252915293 ps |
CPU time | 2.43 seconds |
Started | Jul 31 05:19:03 PM PDT 24 |
Finished | Jul 31 05:19:05 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-1e2bb35f-0bb4-405f-b192-a4fa5d97d77b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256470491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.sram_ctrl_tl_intg_err.256470491 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.3070274188 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 342896328 ps |
CPU time | 1.86 seconds |
Started | Jul 31 06:53:25 PM PDT 24 |
Finished | Jul 31 06:53:27 PM PDT 24 |
Peak memory | 223060 kb |
Host | smart-4e753bdb-ac14-4eb4-94bb-154b863f0724 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070274188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3070274188 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3562594581 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 3219219204 ps |
CPU time | 125.98 seconds |
Started | Jul 31 07:04:58 PM PDT 24 |
Finished | Jul 31 07:07:04 PM PDT 24 |
Peak memory | 211508 kb |
Host | smart-63e1f730-e81b-40a8-8c4d-7214d9903cfb |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562594581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.3562594581 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3488797866 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 16721290811 ps |
CPU time | 334.56 seconds |
Started | Jul 31 06:59:38 PM PDT 24 |
Finished | Jul 31 07:05:12 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-f3cd326d-5a40-46ec-a917-a91821a824a2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488797866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.3488797866 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3668506139 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 1563528204 ps |
CPU time | 138.47 seconds |
Started | Jul 31 06:58:48 PM PDT 24 |
Finished | Jul 31 07:01:07 PM PDT 24 |
Peak memory | 370564 kb |
Host | smart-dfb781f6-a6cf-419e-b323-84465f57faa8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3668506139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3668506139 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3981788162 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 550984751 ps |
CPU time | 2.3 seconds |
Started | Jul 31 05:18:59 PM PDT 24 |
Finished | Jul 31 05:19:01 PM PDT 24 |
Peak memory | 210800 kb |
Host | smart-1ccbc591-54d7-4e9d-b5bf-0ceae4b113f2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981788162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.3981788162 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3974583903 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 5071033310 ps |
CPU time | 26.97 seconds |
Started | Jul 31 05:19:05 PM PDT 24 |
Finished | Jul 31 05:19:37 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-416acb0b-8406-40a2-9999-671ca939e62f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974583903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.3974583903 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.2620996034 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 66984425927 ps |
CPU time | 5077.21 seconds |
Started | Jul 31 06:54:49 PM PDT 24 |
Finished | Jul 31 08:19:27 PM PDT 24 |
Peak memory | 384064 kb |
Host | smart-c4fe2b5f-fbd2-4a58-94b9-a7b9623ee02c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620996034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.2620996034 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.1506875315 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 3742662839 ps |
CPU time | 3.89 seconds |
Started | Jul 31 06:58:03 PM PDT 24 |
Finished | Jul 31 06:58:07 PM PDT 24 |
Peak memory | 203292 kb |
Host | smart-3d27e6a2-1b5a-4f0c-87da-ddec1d1f9639 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506875315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1506875315 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2589720728 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 6831299055 ps |
CPU time | 395.56 seconds |
Started | Jul 31 06:57:40 PM PDT 24 |
Finished | Jul 31 07:04:15 PM PDT 24 |
Peak memory | 203316 kb |
Host | smart-c25e5ebf-75d7-496e-9674-58fea265f0b0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589720728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.2589720728 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.459159972 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 139499497 ps |
CPU time | 0.68 seconds |
Started | Jul 31 06:58:05 PM PDT 24 |
Finished | Jul 31 06:58:06 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-6e782e50-7007-4297-a39a-afb162c7ca69 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459159972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.459159972 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2786199409 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 320398903 ps |
CPU time | 2.23 seconds |
Started | Jul 31 05:19:17 PM PDT 24 |
Finished | Jul 31 05:19:19 PM PDT 24 |
Peak memory | 210796 kb |
Host | smart-b2a0071f-7674-4b31-a3b1-dd36e51db81a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786199409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.2786199409 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2731991841 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 36961721597 ps |
CPU time | 34.89 seconds |
Started | Jul 31 05:19:08 PM PDT 24 |
Finished | Jul 31 05:19:43 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-d745046a-573a-4633-bc13-0472ba5acb98 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731991841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2731991841 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3815209926 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 1817749242 ps |
CPU time | 82.76 seconds |
Started | Jul 31 06:54:51 PM PDT 24 |
Finished | Jul 31 06:56:14 PM PDT 24 |
Peak memory | 313684 kb |
Host | smart-2584e2eb-9647-47d4-a201-033b1eb372c8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3815209926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3815209926 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4063269162 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 262466014 ps |
CPU time | 2.44 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:57 PM PDT 24 |
Peak memory | 210780 kb |
Host | smart-9c84e7a8-4a71-4e98-befc-439e35b8ac19 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063269162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.4063269162 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.3762727151 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 14750509426 ps |
CPU time | 674.97 seconds |
Started | Jul 31 06:57:48 PM PDT 24 |
Finished | Jul 31 07:09:03 PM PDT 24 |
Peak memory | 378116 kb |
Host | smart-51595d42-a641-4196-b1cd-632150a73099 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762727151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3762727151 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3363625367 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 21153199 ps |
CPU time | 0.79 seconds |
Started | Jul 31 05:19:04 PM PDT 24 |
Finished | Jul 31 05:19:05 PM PDT 24 |
Peak memory | 202296 kb |
Host | smart-c60379c4-f6f3-4808-bad3-eed8d926b962 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363625367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.3363625367 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.474147436 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 46457279 ps |
CPU time | 1.84 seconds |
Started | Jul 31 05:18:48 PM PDT 24 |
Finished | Jul 31 05:18:50 PM PDT 24 |
Peak memory | 202472 kb |
Host | smart-720d8d8b-2c17-45ae-a891-e147cf9d8b5c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474147436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_bash.474147436 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1425604192 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 22734780 ps |
CPU time | 0.66 seconds |
Started | Jul 31 05:19:14 PM PDT 24 |
Finished | Jul 31 05:19:14 PM PDT 24 |
Peak memory | 202244 kb |
Host | smart-a3655c75-a3ba-4226-82ad-ba4613647172 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425604192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.1425604192 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1472789289 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 1946515635 ps |
CPU time | 3.78 seconds |
Started | Jul 31 05:18:57 PM PDT 24 |
Finished | Jul 31 05:19:07 PM PDT 24 |
Peak memory | 214180 kb |
Host | smart-e0338588-1779-4694-9209-920d2ad5b876 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472789289 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1472789289 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2911624332 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 17089611 ps |
CPU time | 0.67 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:57 PM PDT 24 |
Peak memory | 202380 kb |
Host | smart-c6ffedb3-2674-4df0-abcf-97a3b6d04eed |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911624332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.2911624332 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1721025398 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 14771006420 ps |
CPU time | 29.71 seconds |
Started | Jul 31 05:19:00 PM PDT 24 |
Finished | Jul 31 05:19:30 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-16f4194c-a7e7-4d8e-9226-49959a6bc033 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721025398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1721025398 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4209127533 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 37162981 ps |
CPU time | 0.73 seconds |
Started | Jul 31 05:18:51 PM PDT 24 |
Finished | Jul 31 05:18:52 PM PDT 24 |
Peak memory | 202408 kb |
Host | smart-96bbf31a-1e0e-435b-85fb-a73fb60b8f55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209127533 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.4209127533 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1420743200 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 544452307 ps |
CPU time | 4.3 seconds |
Started | Jul 31 05:19:01 PM PDT 24 |
Finished | Jul 31 05:19:05 PM PDT 24 |
Peak memory | 210780 kb |
Host | smart-94ed2fb1-9a94-42f0-b1f1-fb803a218bf2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420743200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.1420743200 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.510873719 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 196762269 ps |
CPU time | 1.6 seconds |
Started | Jul 31 05:18:57 PM PDT 24 |
Finished | Jul 31 05:18:59 PM PDT 24 |
Peak memory | 210808 kb |
Host | smart-10339a0b-e46d-48e5-94f6-aac320fe0327 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510873719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.sram_ctrl_tl_intg_err.510873719 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1056927899 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 19216874 ps |
CPU time | 0.74 seconds |
Started | Jul 31 05:18:51 PM PDT 24 |
Finished | Jul 31 05:18:52 PM PDT 24 |
Peak memory | 202404 kb |
Host | smart-5f5909b7-a29a-425c-8f2a-86547cf1c809 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056927899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.1056927899 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2692097600 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 118994633 ps |
CPU time | 2.01 seconds |
Started | Jul 31 05:19:00 PM PDT 24 |
Finished | Jul 31 05:19:02 PM PDT 24 |
Peak memory | 202600 kb |
Host | smart-477a00b5-4066-47d8-99f0-d93cfebfd460 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692097600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.2692097600 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2710484660 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 21571646 ps |
CPU time | 0.64 seconds |
Started | Jul 31 05:19:01 PM PDT 24 |
Finished | Jul 31 05:19:04 PM PDT 24 |
Peak memory | 202300 kb |
Host | smart-044e8326-f820-40ab-b095-2e2aa260356b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710484660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2710484660 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2226710449 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 360123523 ps |
CPU time | 3.94 seconds |
Started | Jul 31 05:18:52 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 210728 kb |
Host | smart-554b4221-c6e0-467f-a078-d1eeaac01568 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226710449 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.2226710449 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2788120918 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 35626033 ps |
CPU time | 0.65 seconds |
Started | Jul 31 05:18:58 PM PDT 24 |
Finished | Jul 31 05:18:59 PM PDT 24 |
Peak memory | 202404 kb |
Host | smart-4dea0bb0-6e00-4ae4-a3a6-2ba07b6ebc6f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788120918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.2788120918 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3938168666 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 13637238913 ps |
CPU time | 29.14 seconds |
Started | Jul 31 05:18:53 PM PDT 24 |
Finished | Jul 31 05:19:22 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-e78e4734-cbfa-483e-bc81-195735e2a0ae |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938168666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3938168666 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1300494693 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 26573996 ps |
CPU time | 0.72 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:57 PM PDT 24 |
Peak memory | 202424 kb |
Host | smart-fe88cadb-acbe-42b5-883a-a3a358566930 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300494693 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.1300494693 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.139606537 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 537477691 ps |
CPU time | 4.82 seconds |
Started | Jul 31 05:18:57 PM PDT 24 |
Finished | Jul 31 05:19:03 PM PDT 24 |
Peak memory | 210876 kb |
Host | smart-4404d99b-3171-443d-932c-8727c7a7b71c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139606537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.139606537 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3811999492 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 362595394 ps |
CPU time | 3.36 seconds |
Started | Jul 31 05:18:52 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 210812 kb |
Host | smart-16b46353-e219-4ba6-85ca-e863521eb31c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811999492 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3811999492 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1208582656 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 13940333 ps |
CPU time | 0.66 seconds |
Started | Jul 31 05:18:59 PM PDT 24 |
Finished | Jul 31 05:19:00 PM PDT 24 |
Peak memory | 202312 kb |
Host | smart-1f97012b-4dba-412a-8623-ca0af81d3415 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208582656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.1208582656 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4113077235 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 42681719 ps |
CPU time | 0.74 seconds |
Started | Jul 31 05:19:00 PM PDT 24 |
Finished | Jul 31 05:19:01 PM PDT 24 |
Peak memory | 202284 kb |
Host | smart-75c11962-0fbd-4128-bb59-50917e9fd1fb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113077235 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.4113077235 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.644916105 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 118477228 ps |
CPU time | 2.48 seconds |
Started | Jul 31 05:18:59 PM PDT 24 |
Finished | Jul 31 05:19:07 PM PDT 24 |
Peak memory | 210820 kb |
Host | smart-d649c849-c3a0-461d-82b4-a6751b66f264 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644916105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.644916105 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1149188426 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 2984412419 ps |
CPU time | 2.44 seconds |
Started | Jul 31 05:19:01 PM PDT 24 |
Finished | Jul 31 05:19:05 PM PDT 24 |
Peak memory | 210960 kb |
Host | smart-90ef321e-ba3f-4099-ad20-6371134159cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149188426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.1149188426 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.141328644 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 360488945 ps |
CPU time | 3.68 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:57 PM PDT 24 |
Peak memory | 210836 kb |
Host | smart-2004ec55-ea1e-4f49-8828-2d20cf6712cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141328644 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.141328644 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.335796351 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 27846700 ps |
CPU time | 0.66 seconds |
Started | Jul 31 05:19:03 PM PDT 24 |
Finished | Jul 31 05:19:04 PM PDT 24 |
Peak memory | 202276 kb |
Host | smart-d4051aa0-68b4-4d9e-bf89-3086520a2834 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335796351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.sram_ctrl_csr_rw.335796351 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.210288298 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 19462802290 ps |
CPU time | 30.51 seconds |
Started | Jul 31 05:19:01 PM PDT 24 |
Finished | Jul 31 05:19:34 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-4aa638f6-f4b2-4b31-b6d2-570c5b0b817a |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210288298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.210288298 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.514660449 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 56951832 ps |
CPU time | 0.76 seconds |
Started | Jul 31 05:19:05 PM PDT 24 |
Finished | Jul 31 05:19:06 PM PDT 24 |
Peak memory | 202368 kb |
Host | smart-cfbc2617-e580-4857-bb98-b88eef048fdd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514660449 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.514660449 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1418699055 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 23917685 ps |
CPU time | 1.63 seconds |
Started | Jul 31 05:19:00 PM PDT 24 |
Finished | Jul 31 05:19:02 PM PDT 24 |
Peak memory | 210768 kb |
Host | smart-4745ea4b-6a68-43bd-984f-e8b29b6077b0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418699055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1418699055 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.116839132 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 302242333 ps |
CPU time | 2.48 seconds |
Started | Jul 31 05:18:59 PM PDT 24 |
Finished | Jul 31 05:19:02 PM PDT 24 |
Peak memory | 210792 kb |
Host | smart-4dd39652-fdf0-41dd-be2e-66e67f9e523b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116839132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.sram_ctrl_tl_intg_err.116839132 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2928534363 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 349802073 ps |
CPU time | 3.57 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:58 PM PDT 24 |
Peak memory | 210564 kb |
Host | smart-08bbfc3c-f503-4d53-bb84-10258ce331be |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928534363 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2928534363 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.219770655 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 159442893 ps |
CPU time | 0.65 seconds |
Started | Jul 31 05:19:08 PM PDT 24 |
Finished | Jul 31 05:19:08 PM PDT 24 |
Peak memory | 202332 kb |
Host | smart-801e2854-4e46-4b37-86eb-68fd0a219c7f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219770655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_csr_rw.219770655 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2110787145 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 22066870 ps |
CPU time | 0.74 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 202388 kb |
Host | smart-6c64d043-8076-417b-9bd6-a114c7e01c59 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110787145 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2110787145 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3160713857 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 35552965 ps |
CPU time | 3.03 seconds |
Started | Jul 31 05:19:06 PM PDT 24 |
Finished | Jul 31 05:19:09 PM PDT 24 |
Peak memory | 210792 kb |
Host | smart-953837d8-54d0-4221-9eda-41fac3b32d4a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160713857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.3160713857 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3359327007 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 1549004080 ps |
CPU time | 3.65 seconds |
Started | Jul 31 05:19:22 PM PDT 24 |
Finished | Jul 31 05:19:25 PM PDT 24 |
Peak memory | 210608 kb |
Host | smart-6a677779-825a-49bd-9576-47e2bb4d55d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359327007 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.3359327007 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4043385571 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 18755454 ps |
CPU time | 0.66 seconds |
Started | Jul 31 05:19:00 PM PDT 24 |
Finished | Jul 31 05:19:01 PM PDT 24 |
Peak memory | 202352 kb |
Host | smart-8d291c64-b8bf-40c1-bcb6-43227cefdc7f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043385571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.4043385571 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.398845551 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 7086469485 ps |
CPU time | 53.95 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:19:48 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-bddae00b-5ff8-4ed1-af4f-bdd2f62aeacf |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398845551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.398845551 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3766120588 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 24370919 ps |
CPU time | 0.87 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:55 PM PDT 24 |
Peak memory | 202376 kb |
Host | smart-bd707bd5-3c6d-4042-a015-c6705aa2fafb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766120588 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3766120588 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3248137643 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 255071524 ps |
CPU time | 5 seconds |
Started | Jul 31 05:18:55 PM PDT 24 |
Finished | Jul 31 05:19:00 PM PDT 24 |
Peak memory | 218892 kb |
Host | smart-8283c5ac-3a74-4a89-ad78-4ca554a0f687 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248137643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.3248137643 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3643510263 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 1762254210 ps |
CPU time | 3.12 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:58 PM PDT 24 |
Peak memory | 210828 kb |
Host | smart-7b85b6c2-b54a-4e7a-bc76-421f3d8cf3f3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643510263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.3643510263 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2995962495 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 352492032 ps |
CPU time | 4.64 seconds |
Started | Jul 31 05:18:52 PM PDT 24 |
Finished | Jul 31 05:18:57 PM PDT 24 |
Peak memory | 210780 kb |
Host | smart-9a96452c-2741-4cea-9b54-3bf1ea9e0dcb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995962495 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2995962495 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3868488623 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 39430083 ps |
CPU time | 0.63 seconds |
Started | Jul 31 05:19:16 PM PDT 24 |
Finished | Jul 31 05:19:17 PM PDT 24 |
Peak memory | 202380 kb |
Host | smart-ca8cb84e-c2b3-4fff-85bd-426ca006b308 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868488623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.3868488623 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.418766163 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 3734188728 ps |
CPU time | 25.24 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:19:20 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-d0c967f3-d24b-4b14-a88c-4f74bc1baad0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418766163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.418766163 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4109108866 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 29773500 ps |
CPU time | 0.69 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:54 PM PDT 24 |
Peak memory | 202400 kb |
Host | smart-4268c7bb-34fc-4a84-bd29-ef447d32ba08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109108866 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.4109108866 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.903175855 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 270906754 ps |
CPU time | 3.92 seconds |
Started | Jul 31 05:19:06 PM PDT 24 |
Finished | Jul 31 05:19:10 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-99c9a253-f894-4e6d-b734-0c1c08b699f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903175855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.903175855 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3794964332 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 714110993 ps |
CPU time | 4.32 seconds |
Started | Jul 31 05:18:53 PM PDT 24 |
Finished | Jul 31 05:18:58 PM PDT 24 |
Peak memory | 210900 kb |
Host | smart-4519b899-9910-435b-ac2a-33c9f6ed6056 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794964332 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.3794964332 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3075389591 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 14039182 ps |
CPU time | 0.75 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:57 PM PDT 24 |
Peak memory | 202284 kb |
Host | smart-c2e745d6-283b-4992-a465-8a17631dcd10 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075389591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.3075389591 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1051285411 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 15404783661 ps |
CPU time | 32.51 seconds |
Started | Jul 31 05:19:27 PM PDT 24 |
Finished | Jul 31 05:19:59 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-8bdc82b5-074b-47d1-81d1-3bb47b6e5638 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051285411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.1051285411 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1815915218 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 61724382 ps |
CPU time | 0.75 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 202368 kb |
Host | smart-a13c64f7-794a-47d7-b92e-dc049724c1c1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815915218 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1815915218 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.470137087 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 43180490 ps |
CPU time | 3.51 seconds |
Started | Jul 31 05:19:10 PM PDT 24 |
Finished | Jul 31 05:19:14 PM PDT 24 |
Peak memory | 210772 kb |
Host | smart-f3a4aa2d-19f3-43d3-bf12-a03472048c72 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470137087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.470137087 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4212709804 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 132105224 ps |
CPU time | 1.53 seconds |
Started | Jul 31 05:19:00 PM PDT 24 |
Finished | Jul 31 05:19:01 PM PDT 24 |
Peak memory | 210876 kb |
Host | smart-52cfc998-26a7-419e-a3a2-c74213e7137b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212709804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.4212709804 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4122771461 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 357616383 ps |
CPU time | 2.95 seconds |
Started | Jul 31 05:18:52 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 210652 kb |
Host | smart-6c149c91-b3a2-4330-81a9-f05b02d71dbb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122771461 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.4122771461 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2399964741 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 13924331 ps |
CPU time | 0.64 seconds |
Started | Jul 31 05:19:01 PM PDT 24 |
Finished | Jul 31 05:19:02 PM PDT 24 |
Peak memory | 202380 kb |
Host | smart-cd6524d8-c11d-47e5-aef8-4183baf7601f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399964741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.2399964741 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.601711845 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 16731606474 ps |
CPU time | 31.35 seconds |
Started | Jul 31 05:19:01 PM PDT 24 |
Finished | Jul 31 05:19:32 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-a541b6ec-1752-47f3-84f1-c1ba9368cc9a |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601711845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.601711845 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.362576203 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 127322476 ps |
CPU time | 0.79 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:55 PM PDT 24 |
Peak memory | 202352 kb |
Host | smart-b63d23e7-9d28-4862-b900-14305094163e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362576203 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.362576203 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2146314983 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 37290145 ps |
CPU time | 1.86 seconds |
Started | Jul 31 05:19:04 PM PDT 24 |
Finished | Jul 31 05:19:11 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-33bb3c3e-9cbc-4abb-bb60-0c82bbaf31cc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146314983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.2146314983 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4048473373 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 664565252 ps |
CPU time | 2.29 seconds |
Started | Jul 31 05:19:04 PM PDT 24 |
Finished | Jul 31 05:19:06 PM PDT 24 |
Peak memory | 210832 kb |
Host | smart-96722d58-db33-4f45-9e96-c8305ec87336 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048473373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.4048473373 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3602581591 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 1548075176 ps |
CPU time | 3.39 seconds |
Started | Jul 31 05:18:55 PM PDT 24 |
Finished | Jul 31 05:18:59 PM PDT 24 |
Peak memory | 210560 kb |
Host | smart-d0f381d1-1ebf-46f8-9223-b351d8ac703c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602581591 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3602581591 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.902973442 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 12270097 ps |
CPU time | 0.66 seconds |
Started | Jul 31 05:19:33 PM PDT 24 |
Finished | Jul 31 05:19:34 PM PDT 24 |
Peak memory | 202316 kb |
Host | smart-9dbb5edc-eea4-4306-b4c1-48224fc82c5f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902973442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.902973442 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1014547444 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 7299914851 ps |
CPU time | 50.51 seconds |
Started | Jul 31 05:19:03 PM PDT 24 |
Finished | Jul 31 05:19:54 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-775bb1fb-4ff2-4424-8dcd-0958b5bc37bb |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014547444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.1014547444 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4116569733 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 18153941 ps |
CPU time | 0.72 seconds |
Started | Jul 31 05:19:33 PM PDT 24 |
Finished | Jul 31 05:19:34 PM PDT 24 |
Peak memory | 202416 kb |
Host | smart-b9ed17a2-08e8-45f9-ae18-d2a4c93bfabb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116569733 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.4116569733 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.343920083 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 327192447 ps |
CPU time | 3.69 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:59 PM PDT 24 |
Peak memory | 210764 kb |
Host | smart-89109523-a49d-4cf4-b6e7-f386bed33071 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343920083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.343920083 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1597547078 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 453558756 ps |
CPU time | 2.09 seconds |
Started | Jul 31 05:19:07 PM PDT 24 |
Finished | Jul 31 05:19:09 PM PDT 24 |
Peak memory | 210748 kb |
Host | smart-91635d62-ac6b-4154-838a-e88b301e1129 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597547078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.1597547078 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3077770228 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 373597064 ps |
CPU time | 4.93 seconds |
Started | Jul 31 05:19:06 PM PDT 24 |
Finished | Jul 31 05:19:11 PM PDT 24 |
Peak memory | 218912 kb |
Host | smart-a225fde3-78c9-4926-88a4-d000a9f14c9a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077770228 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3077770228 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2565903967 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 39072240 ps |
CPU time | 0.65 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 202276 kb |
Host | smart-0714cb2f-9767-484d-a30c-589069feeffe |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565903967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.2565903967 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3695080899 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 52875620981 ps |
CPU time | 40.32 seconds |
Started | Jul 31 05:19:06 PM PDT 24 |
Finished | Jul 31 05:19:46 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-20bc524d-b74d-4094-8193-d3c7a29e7724 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695080899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3695080899 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3290651573 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 20955259 ps |
CPU time | 0.75 seconds |
Started | Jul 31 05:18:52 PM PDT 24 |
Finished | Jul 31 05:18:53 PM PDT 24 |
Peak memory | 202352 kb |
Host | smart-671bb8d9-8c33-45de-aedc-dd629e837830 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290651573 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3290651573 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1410310452 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 80105155 ps |
CPU time | 3.6 seconds |
Started | Jul 31 05:19:33 PM PDT 24 |
Finished | Jul 31 05:19:37 PM PDT 24 |
Peak memory | 202608 kb |
Host | smart-a0fe873f-0eab-48b3-aeff-2952a89cd981 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410310452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.1410310452 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3550163667 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 1739547651 ps |
CPU time | 3.92 seconds |
Started | Jul 31 05:19:07 PM PDT 24 |
Finished | Jul 31 05:19:11 PM PDT 24 |
Peak memory | 210660 kb |
Host | smart-42ebb081-e81c-415f-87cf-9b417278e022 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550163667 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3550163667 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1590995550 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 36346180 ps |
CPU time | 0.72 seconds |
Started | Jul 31 05:18:58 PM PDT 24 |
Finished | Jul 31 05:19:04 PM PDT 24 |
Peak memory | 202384 kb |
Host | smart-4d0c11aa-c849-417d-9b84-24a248fb8e2d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590995550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.1590995550 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.409018406 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 15362209714 ps |
CPU time | 26.75 seconds |
Started | Jul 31 05:19:25 PM PDT 24 |
Finished | Jul 31 05:19:52 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-7d77488b-1759-4e8c-93f4-a43ab02f20e3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409018406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.409018406 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3641784383 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 52091980 ps |
CPU time | 0.72 seconds |
Started | Jul 31 05:19:00 PM PDT 24 |
Finished | Jul 31 05:19:01 PM PDT 24 |
Peak memory | 202428 kb |
Host | smart-e0ee545d-ad18-4744-8dbd-f857ec8cee1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641784383 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3641784383 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3277740873 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 226539738 ps |
CPU time | 3.83 seconds |
Started | Jul 31 05:19:21 PM PDT 24 |
Finished | Jul 31 05:19:25 PM PDT 24 |
Peak memory | 210872 kb |
Host | smart-c4531c8e-cf91-4029-8155-56214ab53e7d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277740873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.3277740873 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3350698010 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 164116856 ps |
CPU time | 2.07 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:58 PM PDT 24 |
Peak memory | 210852 kb |
Host | smart-61fed21d-2ec2-41e9-9d23-bda25fd4fac9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350698010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.3350698010 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1861805044 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 72220845 ps |
CPU time | 0.71 seconds |
Started | Jul 31 05:18:59 PM PDT 24 |
Finished | Jul 31 05:19:00 PM PDT 24 |
Peak memory | 202352 kb |
Host | smart-f59e1402-3d24-471f-a253-fbe5401518ec |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861805044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.1861805044 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4107608868 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 511222613 ps |
CPU time | 2.15 seconds |
Started | Jul 31 05:18:53 PM PDT 24 |
Finished | Jul 31 05:18:55 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-e6bc2686-e80f-4510-8a4f-caeed7358275 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107608868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.4107608868 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3034617312 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 23802851 ps |
CPU time | 0.7 seconds |
Started | Jul 31 05:19:06 PM PDT 24 |
Finished | Jul 31 05:19:07 PM PDT 24 |
Peak memory | 202328 kb |
Host | smart-107c3894-e676-4b15-9e0d-2b8c86427202 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034617312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.3034617312 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1582675057 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 1441608881 ps |
CPU time | 3.62 seconds |
Started | Jul 31 05:18:57 PM PDT 24 |
Finished | Jul 31 05:19:01 PM PDT 24 |
Peak memory | 210620 kb |
Host | smart-29ce6ea1-c4a4-4d52-8fc5-f75d53156380 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582675057 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1582675057 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2748622497 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 38018023 ps |
CPU time | 0.65 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:54 PM PDT 24 |
Peak memory | 202276 kb |
Host | smart-75e95c0e-45e6-4a60-bc14-942c68696756 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748622497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.2748622497 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3624740067 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 7457221609 ps |
CPU time | 48.49 seconds |
Started | Jul 31 05:18:53 PM PDT 24 |
Finished | Jul 31 05:19:42 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-8db6ff09-1d81-4e3c-8901-6484b3cf072f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624740067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3624740067 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.78057055 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 29823109 ps |
CPU time | 0.8 seconds |
Started | Jul 31 05:18:55 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 202408 kb |
Host | smart-66b1e2ef-49b5-4d6d-a017-faa980d30691 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78057055 -assert nopostproc +UVM_TESTNAME=sram_ctr l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.78057055 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3852229734 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 1166287546 ps |
CPU time | 2.79 seconds |
Started | Jul 31 05:18:59 PM PDT 24 |
Finished | Jul 31 05:19:02 PM PDT 24 |
Peak memory | 210832 kb |
Host | smart-1a27e96a-0286-4458-bca2-6d4c314ef87f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852229734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.3852229734 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.719460168 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 106643029 ps |
CPU time | 1.52 seconds |
Started | Jul 31 05:18:51 PM PDT 24 |
Finished | Jul 31 05:18:52 PM PDT 24 |
Peak memory | 210816 kb |
Host | smart-f08d702c-3f96-4ac2-a5b5-096a9081fee6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719460168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.sram_ctrl_tl_intg_err.719460168 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.827957925 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 13183944 ps |
CPU time | 0.74 seconds |
Started | Jul 31 05:19:24 PM PDT 24 |
Finished | Jul 31 05:19:24 PM PDT 24 |
Peak memory | 202336 kb |
Host | smart-68bf941f-7a90-4df5-857a-45ccce54e13d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827957925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.827957925 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1726034678 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 98846075 ps |
CPU time | 1.47 seconds |
Started | Jul 31 05:18:55 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 202464 kb |
Host | smart-d1f216bb-7622-4d79-a437-6a03b0b37f67 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726034678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.1726034678 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2135345392 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 22083371 ps |
CPU time | 0.69 seconds |
Started | Jul 31 05:18:55 PM PDT 24 |
Finished | Jul 31 05:18:55 PM PDT 24 |
Peak memory | 202252 kb |
Host | smart-662ee5e7-d684-4671-bef9-29d640918ec5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135345392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.2135345392 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3191871766 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 369039310 ps |
CPU time | 4.52 seconds |
Started | Jul 31 05:18:55 PM PDT 24 |
Finished | Jul 31 05:19:00 PM PDT 24 |
Peak memory | 210828 kb |
Host | smart-f7bb90df-8df9-402a-bfd6-aab0374580ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191871766 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3191871766 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3029858427 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 38521185 ps |
CPU time | 0.64 seconds |
Started | Jul 31 05:19:00 PM PDT 24 |
Finished | Jul 31 05:19:01 PM PDT 24 |
Peak memory | 202420 kb |
Host | smart-f9604a39-6056-4142-9e96-f6cab3272fc2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029858427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.3029858427 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.691714928 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 4059222029 ps |
CPU time | 25.8 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:19:20 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-8618c4e8-fe25-4afd-809c-b26d7485b823 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691714928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.691714928 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.766226068 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 46932985 ps |
CPU time | 0.7 seconds |
Started | Jul 31 05:19:16 PM PDT 24 |
Finished | Jul 31 05:19:27 PM PDT 24 |
Peak memory | 202368 kb |
Host | smart-39233cf4-1703-4e18-a198-272af4b0080c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766226068 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.766226068 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.207139195 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 36643140 ps |
CPU time | 4.04 seconds |
Started | Jul 31 05:18:53 PM PDT 24 |
Finished | Jul 31 05:18:57 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-93a032b2-6c8a-4cf3-89e7-7b59ab594f7b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207139195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.207139195 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3835917758 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 153938780 ps |
CPU time | 1.41 seconds |
Started | Jul 31 05:18:59 PM PDT 24 |
Finished | Jul 31 05:19:01 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-761f1fe7-e6a9-4b9c-8b9f-64cf764980c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835917758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.3835917758 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3143866516 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 20831155 ps |
CPU time | 0.76 seconds |
Started | Jul 31 05:19:11 PM PDT 24 |
Finished | Jul 31 05:19:11 PM PDT 24 |
Peak memory | 202392 kb |
Host | smart-11958447-4650-4778-b745-0f5a1fec70e0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143866516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.3143866516 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3036478696 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 338648677 ps |
CPU time | 1.86 seconds |
Started | Jul 31 05:18:57 PM PDT 24 |
Finished | Jul 31 05:19:00 PM PDT 24 |
Peak memory | 202608 kb |
Host | smart-cc9a6ffa-f2c8-498a-8df8-adc7017526e9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036478696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.3036478696 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3808667628 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 31971926 ps |
CPU time | 0.62 seconds |
Started | Jul 31 05:18:53 PM PDT 24 |
Finished | Jul 31 05:18:54 PM PDT 24 |
Peak memory | 202384 kb |
Host | smart-5664721d-cb70-43c1-82c5-d149c82e34f8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808667628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.3808667628 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3606143158 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 13854983 ps |
CPU time | 0.66 seconds |
Started | Jul 31 05:19:00 PM PDT 24 |
Finished | Jul 31 05:19:00 PM PDT 24 |
Peak memory | 202400 kb |
Host | smart-3c9d75c2-496c-4a96-b309-056c214d144e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606143158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.3606143158 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3510774630 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 21534191188 ps |
CPU time | 53.45 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:19:50 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-295683b3-38be-45f6-b397-795330cb6cf7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510774630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3510774630 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1034897935 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 54452342 ps |
CPU time | 0.73 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:57 PM PDT 24 |
Peak memory | 202392 kb |
Host | smart-6f6bbb98-400f-4c97-a6dc-d457b46e38d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034897935 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1034897935 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1106396048 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 1134157866 ps |
CPU time | 4.77 seconds |
Started | Jul 31 05:18:55 PM PDT 24 |
Finished | Jul 31 05:19:00 PM PDT 24 |
Peak memory | 210740 kb |
Host | smart-dc873703-c30c-44fd-8682-6bcf30409fa4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106396048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.1106396048 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2685519265 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 102682704 ps |
CPU time | 1.59 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:58 PM PDT 24 |
Peak memory | 210796 kb |
Host | smart-297961db-fbf0-4203-b3db-1d8e1c4d10b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685519265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.2685519265 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3528980240 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 1143657048 ps |
CPU time | 3.79 seconds |
Started | Jul 31 05:19:01 PM PDT 24 |
Finished | Jul 31 05:19:06 PM PDT 24 |
Peak memory | 210760 kb |
Host | smart-10143199-1101-4cfc-b02e-d2f0f43ce847 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528980240 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3528980240 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1160557746 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 15135008 ps |
CPU time | 0.65 seconds |
Started | Jul 31 05:19:00 PM PDT 24 |
Finished | Jul 31 05:19:01 PM PDT 24 |
Peak memory | 202240 kb |
Host | smart-0255efd5-a6c4-479f-816b-a25a1634dc47 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160557746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.1160557746 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.356248480 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 7587719689 ps |
CPU time | 53.05 seconds |
Started | Jul 31 05:19:03 PM PDT 24 |
Finished | Jul 31 05:19:57 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-0c91e1b6-5f21-4ac8-818e-af789bb74db7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356248480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.356248480 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1481797982 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 92004107 ps |
CPU time | 0.79 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:55 PM PDT 24 |
Peak memory | 202356 kb |
Host | smart-67426a6e-05d9-469d-8d23-217781835e55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481797982 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1481797982 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.34865540 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 44331168 ps |
CPU time | 3.46 seconds |
Started | Jul 31 05:19:03 PM PDT 24 |
Finished | Jul 31 05:19:06 PM PDT 24 |
Peak memory | 210812 kb |
Host | smart-9483032a-1bef-4744-92cf-71ff8ba15339 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34865540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST _SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.34865540 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1481424700 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 349175376 ps |
CPU time | 1.49 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-7912cc3d-cbec-4431-9fa8-0e65f8e0c7b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481424700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.1481424700 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2474931933 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 729691097 ps |
CPU time | 3.48 seconds |
Started | Jul 31 05:18:53 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 210628 kb |
Host | smart-2083fc00-ab63-410d-ba9c-2b89ac9d0fd4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474931933 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2474931933 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1750355784 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 40395253 ps |
CPU time | 0.63 seconds |
Started | Jul 31 05:19:04 PM PDT 24 |
Finished | Jul 31 05:19:05 PM PDT 24 |
Peak memory | 202424 kb |
Host | smart-ccdcad74-3ca8-4984-aed6-09ecc8f09a81 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750355784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.1750355784 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3612612405 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 7432808922 ps |
CPU time | 28.42 seconds |
Started | Jul 31 05:18:51 PM PDT 24 |
Finished | Jul 31 05:19:20 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-fa02042c-b51f-4e8e-a91a-ff9374080bff |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612612405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3612612405 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4055729238 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 21522091 ps |
CPU time | 0.74 seconds |
Started | Jul 31 05:18:52 PM PDT 24 |
Finished | Jul 31 05:18:52 PM PDT 24 |
Peak memory | 202228 kb |
Host | smart-a25cdf44-0aff-463e-b871-2abf5852067c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055729238 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.4055729238 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.229976318 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 42035809 ps |
CPU time | 1.92 seconds |
Started | Jul 31 05:18:54 PM PDT 24 |
Finished | Jul 31 05:18:56 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-aa7dc390-a259-4dd3-9652-7fa7ce56f6fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229976318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.229976318 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1234314950 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 247293352 ps |
CPU time | 1.7 seconds |
Started | Jul 31 05:19:02 PM PDT 24 |
Finished | Jul 31 05:19:05 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-8b6689b4-95ac-4f46-a7e7-8321d4be604c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234314950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.1234314950 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1559925694 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 701388151 ps |
CPU time | 3.74 seconds |
Started | Jul 31 05:19:01 PM PDT 24 |
Finished | Jul 31 05:19:05 PM PDT 24 |
Peak memory | 210860 kb |
Host | smart-fa93ae59-5c38-41e6-8ca6-200098cf87d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559925694 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1559925694 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3186414923 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 35255340 ps |
CPU time | 0.64 seconds |
Started | Jul 31 05:19:18 PM PDT 24 |
Finished | Jul 31 05:19:19 PM PDT 24 |
Peak memory | 202232 kb |
Host | smart-d9c08c3a-1baf-4f3b-a57b-7d2485a3660e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186414923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.3186414923 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.475456999 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 28198882961 ps |
CPU time | 56.19 seconds |
Started | Jul 31 05:18:55 PM PDT 24 |
Finished | Jul 31 05:19:51 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-03478014-6d04-4db2-a0aa-5588ac1f76cc |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475456999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.475456999 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1306201735 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 28001702 ps |
CPU time | 0.67 seconds |
Started | Jul 31 05:18:48 PM PDT 24 |
Finished | Jul 31 05:18:49 PM PDT 24 |
Peak memory | 202300 kb |
Host | smart-3d6a55dc-0afd-4f7e-8b25-1a41fefb7e23 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306201735 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1306201735 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1582135713 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 67498427 ps |
CPU time | 1.78 seconds |
Started | Jul 31 05:19:01 PM PDT 24 |
Finished | Jul 31 05:19:04 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-7e6016fa-4c4d-40e0-9e3d-495881278889 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582135713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.1582135713 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.917793404 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 634749251 ps |
CPU time | 2.26 seconds |
Started | Jul 31 05:18:55 PM PDT 24 |
Finished | Jul 31 05:18:57 PM PDT 24 |
Peak memory | 210828 kb |
Host | smart-4c7d098c-c041-45a4-b2ef-b92f982aece4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917793404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.sram_ctrl_tl_intg_err.917793404 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4002197658 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 361949911 ps |
CPU time | 4.12 seconds |
Started | Jul 31 05:19:08 PM PDT 24 |
Finished | Jul 31 05:19:12 PM PDT 24 |
Peak memory | 210728 kb |
Host | smart-35ac2559-8970-4ecd-b0e3-14ccb2ba17ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002197658 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.4002197658 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2562931701 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 31787795 ps |
CPU time | 0.63 seconds |
Started | Jul 31 05:18:56 PM PDT 24 |
Finished | Jul 31 05:18:57 PM PDT 24 |
Peak memory | 202316 kb |
Host | smart-f60afb3b-5156-4aa5-8e3f-587e265ad70e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562931701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.2562931701 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2775639464 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 12653853301 ps |
CPU time | 53.72 seconds |
Started | Jul 31 05:19:23 PM PDT 24 |
Finished | Jul 31 05:20:17 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-eb272dde-399e-41d7-b1fb-39f41ed3d019 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775639464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.2775639464 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3711035341 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 138240431 ps |
CPU time | 0.74 seconds |
Started | Jul 31 05:19:01 PM PDT 24 |
Finished | Jul 31 05:19:02 PM PDT 24 |
Peak memory | 202376 kb |
Host | smart-e3e818d2-dbbb-4607-9353-72da70ffeede |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711035341 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.3711035341 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1925667218 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 279874997 ps |
CPU time | 2.82 seconds |
Started | Jul 31 05:18:49 PM PDT 24 |
Finished | Jul 31 05:18:52 PM PDT 24 |
Peak memory | 210796 kb |
Host | smart-6e9a9568-d8bb-4480-9341-5becdcef5e30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925667218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.1925667218 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2821681238 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 650585655 ps |
CPU time | 2.28 seconds |
Started | Jul 31 05:18:57 PM PDT 24 |
Finished | Jul 31 05:19:00 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-f2500326-a679-47af-9a83-2a27a750ea11 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821681238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.2821681238 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1539448931 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 1539488868 ps |
CPU time | 3.75 seconds |
Started | Jul 31 05:18:58 PM PDT 24 |
Finished | Jul 31 05:19:02 PM PDT 24 |
Peak memory | 210756 kb |
Host | smart-e07a2b8e-6e6a-42cc-8458-5648ad346f42 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539448931 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1539448931 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2891028740 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 31462797 ps |
CPU time | 0.61 seconds |
Started | Jul 31 05:19:06 PM PDT 24 |
Finished | Jul 31 05:19:06 PM PDT 24 |
Peak memory | 202376 kb |
Host | smart-f2f59350-6c6f-4197-8ff7-885c2d0af055 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891028740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.2891028740 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1232672557 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 15119167725 ps |
CPU time | 52.42 seconds |
Started | Jul 31 05:19:04 PM PDT 24 |
Finished | Jul 31 05:20:02 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-1c21474e-cc0f-434e-a4c0-5cd594dae122 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232672557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1232672557 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2634732517 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 17695540 ps |
CPU time | 0.65 seconds |
Started | Jul 31 05:19:05 PM PDT 24 |
Finished | Jul 31 05:19:06 PM PDT 24 |
Peak memory | 202424 kb |
Host | smart-27c9b6bd-9644-4f17-b720-29939900a7ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634732517 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2634732517 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2119449722 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 324761667 ps |
CPU time | 4.83 seconds |
Started | Jul 31 05:19:03 PM PDT 24 |
Finished | Jul 31 05:19:09 PM PDT 24 |
Peak memory | 210804 kb |
Host | smart-60db16ed-c1d0-47f0-a84a-52f3b03f8a9d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119449722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.2119449722 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.974707217 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 618070806 ps |
CPU time | 2.13 seconds |
Started | Jul 31 05:19:03 PM PDT 24 |
Finished | Jul 31 05:19:06 PM PDT 24 |
Peak memory | 210876 kb |
Host | smart-cdc97eaf-a7b4-422b-8574-f7882c4a8678 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974707217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.sram_ctrl_tl_intg_err.974707217 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.362845349 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 48525815829 ps |
CPU time | 1466.53 seconds |
Started | Jul 31 06:53:02 PM PDT 24 |
Finished | Jul 31 07:17:29 PM PDT 24 |
Peak memory | 380228 kb |
Host | smart-422e7789-e9a7-4c81-a02f-29ec93f1291c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362845349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.sram_ctrl_access_during_key_req.362845349 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.3673663366 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 43276570 ps |
CPU time | 0.63 seconds |
Started | Jul 31 06:53:06 PM PDT 24 |
Finished | Jul 31 06:53:07 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-9d61c8f9-6d48-4471-b88c-1c8e4168e9e4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673663366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3673663366 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.596315058 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 32810672230 ps |
CPU time | 560.9 seconds |
Started | Jul 31 06:52:58 PM PDT 24 |
Finished | Jul 31 07:02:19 PM PDT 24 |
Peak memory | 203944 kb |
Host | smart-11236e72-9336-4a0c-ba8e-3c03745ad499 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596315058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.596315058 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.3701195216 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 23034225408 ps |
CPU time | 453.37 seconds |
Started | Jul 31 06:53:02 PM PDT 24 |
Finished | Jul 31 07:00:36 PM PDT 24 |
Peak memory | 378080 kb |
Host | smart-7f0a367e-3ea9-4141-a6b2-89acbb69083e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701195216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.3701195216 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.727680283 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 18308512709 ps |
CPU time | 57.43 seconds |
Started | Jul 31 06:53:04 PM PDT 24 |
Finished | Jul 31 06:54:02 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-c313ae7c-dd52-40a0-9e5f-f4bc37409e2d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727680283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca lation.727680283 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.5863401 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 8486405799 ps |
CPU time | 11.92 seconds |
Started | Jul 31 06:52:57 PM PDT 24 |
Finished | Jul 31 06:53:09 PM PDT 24 |
Peak memory | 226128 kb |
Host | smart-a6f61a11-f0c5-4eb3-aa0c-523dec001776 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5863401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base _test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.sram_ctrl_max_throughput.5863401 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.404848238 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 10399431146 ps |
CPU time | 148.2 seconds |
Started | Jul 31 06:53:04 PM PDT 24 |
Finished | Jul 31 06:55:32 PM PDT 24 |
Peak memory | 219476 kb |
Host | smart-90e7f7f3-b7a6-4949-bc04-bd265f07850d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404848238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_mem_partial_access.404848238 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.4102155366 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 15362755563 ps |
CPU time | 162.3 seconds |
Started | Jul 31 06:53:03 PM PDT 24 |
Finished | Jul 31 06:55:45 PM PDT 24 |
Peak memory | 212184 kb |
Host | smart-f32242d6-d14d-4246-a0fd-e393308644db |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102155366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.4102155366 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.2804731206 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 51266538082 ps |
CPU time | 1896.01 seconds |
Started | Jul 31 06:52:56 PM PDT 24 |
Finished | Jul 31 07:24:32 PM PDT 24 |
Peak memory | 381148 kb |
Host | smart-40db60e6-c07f-4fc0-8897-4ab08cf13cda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804731206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.2804731206 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.2000403196 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 1488026346 ps |
CPU time | 13.22 seconds |
Started | Jul 31 06:52:57 PM PDT 24 |
Finished | Jul 31 06:53:10 PM PDT 24 |
Peak memory | 238856 kb |
Host | smart-4ae7ccfb-630f-4168-a839-b7b45c74b787 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000403196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.2000403196 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.936338281 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 3434293893 ps |
CPU time | 187.5 seconds |
Started | Jul 31 06:52:57 PM PDT 24 |
Finished | Jul 31 06:56:04 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-a3e7859b-2aec-4c7f-ab49-dc82714909ea |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936338281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.sram_ctrl_partial_access_b2b.936338281 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.2583175217 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 346315973 ps |
CPU time | 3.18 seconds |
Started | Jul 31 06:53:08 PM PDT 24 |
Finished | Jul 31 06:53:11 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-3a948124-1f79-4442-8c83-53378df7683d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583175217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.2583175217 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.3213213233 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 6265538627 ps |
CPU time | 825.46 seconds |
Started | Jul 31 06:53:04 PM PDT 24 |
Finished | Jul 31 07:06:50 PM PDT 24 |
Peak memory | 374128 kb |
Host | smart-b9b8cf8e-86e9-4718-b53e-660a992e3646 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213213233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3213213233 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.3227859716 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 1045461698 ps |
CPU time | 3.49 seconds |
Started | Jul 31 06:53:09 PM PDT 24 |
Finished | Jul 31 06:53:12 PM PDT 24 |
Peak memory | 222884 kb |
Host | smart-066d6434-8da8-4d41-9670-98fa90e3e1c1 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227859716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3227859716 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.2874611262 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 923306524 ps |
CPU time | 16.82 seconds |
Started | Jul 31 06:52:59 PM PDT 24 |
Finished | Jul 31 06:53:16 PM PDT 24 |
Peak memory | 247116 kb |
Host | smart-b795b3a8-2644-4966-bf23-0cf4722713a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874611262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2874611262 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.808243370 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 187641961035 ps |
CPU time | 3013.25 seconds |
Started | Jul 31 06:53:06 PM PDT 24 |
Finished | Jul 31 07:43:20 PM PDT 24 |
Peak memory | 380544 kb |
Host | smart-241e82a5-f920-40b1-9e2a-6909b7a6c3b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808243370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_stress_all.808243370 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1564475691 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 17079935656 ps |
CPU time | 212.99 seconds |
Started | Jul 31 06:53:04 PM PDT 24 |
Finished | Jul 31 06:56:38 PM PDT 24 |
Peak memory | 366912 kb |
Host | smart-3bcc0830-82e0-4d01-9abf-451cc963032c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1564475691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1564475691 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3949153602 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 12306369734 ps |
CPU time | 160.48 seconds |
Started | Jul 31 06:52:56 PM PDT 24 |
Finished | Jul 31 06:55:37 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-db48c8e3-0521-43cc-9420-ea6ac07370b9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949153602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.3949153602 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.112946954 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 788124213 ps |
CPU time | 79.02 seconds |
Started | Jul 31 06:53:02 PM PDT 24 |
Finished | Jul 31 06:54:21 PM PDT 24 |
Peak memory | 351580 kb |
Host | smart-2d3ec76f-79ff-4655-a587-1bf2dec676ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112946954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_throughput_w_partial_write.112946954 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2637330264 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 11391223689 ps |
CPU time | 674.09 seconds |
Started | Jul 31 06:53:19 PM PDT 24 |
Finished | Jul 31 07:04:33 PM PDT 24 |
Peak memory | 374168 kb |
Host | smart-0c9dabb8-830b-48e3-97a2-cc15371c7d18 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637330264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.2637330264 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.1472194516 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 24492690 ps |
CPU time | 0.67 seconds |
Started | Jul 31 06:53:27 PM PDT 24 |
Finished | Jul 31 06:53:28 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-043144ab-df49-46d2-a07c-aa08bf969a96 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472194516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.1472194516 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.2248267393 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 69449678259 ps |
CPU time | 569.72 seconds |
Started | Jul 31 06:53:07 PM PDT 24 |
Finished | Jul 31 07:02:37 PM PDT 24 |
Peak memory | 203812 kb |
Host | smart-f87c7a42-08a9-481f-928f-72593eda4705 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248267393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 2248267393 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.3900082079 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 16272562012 ps |
CPU time | 1129.08 seconds |
Started | Jul 31 06:53:22 PM PDT 24 |
Finished | Jul 31 07:12:11 PM PDT 24 |
Peak memory | 379112 kb |
Host | smart-bf6669ce-bca1-44a1-a4b8-323e9b100ef7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900082079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.3900082079 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.614664678 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 4279954170 ps |
CPU time | 28.83 seconds |
Started | Jul 31 06:53:20 PM PDT 24 |
Finished | Jul 31 06:53:49 PM PDT 24 |
Peak memory | 203292 kb |
Host | smart-c4c8e2aa-0dd7-414e-b648-e88723f9da58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614664678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esca lation.614664678 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.1991685599 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 2760552398 ps |
CPU time | 30.67 seconds |
Started | Jul 31 06:53:13 PM PDT 24 |
Finished | Jul 31 06:53:44 PM PDT 24 |
Peak memory | 290144 kb |
Host | smart-d5196f81-62f8-4dca-b666-aa8b73c2d79f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991685599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.1991685599 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.340189115 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 1403775749 ps |
CPU time | 73.21 seconds |
Started | Jul 31 06:53:19 PM PDT 24 |
Finished | Jul 31 06:54:32 PM PDT 24 |
Peak memory | 219476 kb |
Host | smart-2abc3cd3-4f4e-4487-afb7-186a3432c0e7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340189115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. sram_ctrl_mem_partial_access.340189115 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.459041121 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 154110719481 ps |
CPU time | 321.94 seconds |
Started | Jul 31 06:53:19 PM PDT 24 |
Finished | Jul 31 06:58:41 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-d186dd03-3ac0-4c4c-9680-613355ba84cc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459041121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ mem_walk.459041121 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.2683501460 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 2968267379 ps |
CPU time | 330.9 seconds |
Started | Jul 31 06:53:07 PM PDT 24 |
Finished | Jul 31 06:58:38 PM PDT 24 |
Peak memory | 380072 kb |
Host | smart-3f41d9e8-2257-497d-b256-1e64fd1a3b5d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683501460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.2683501460 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.3045905519 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 2881162496 ps |
CPU time | 31.19 seconds |
Started | Jul 31 06:53:07 PM PDT 24 |
Finished | Jul 31 06:53:38 PM PDT 24 |
Peak memory | 289996 kb |
Host | smart-84266c88-1422-4570-9b03-1899eba15252 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045905519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.3045905519 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1158720039 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 59305070659 ps |
CPU time | 337.24 seconds |
Started | Jul 31 06:53:18 PM PDT 24 |
Finished | Jul 31 06:58:56 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-4b405cff-6797-4e75-93dc-ca96b36ef270 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158720039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.1158720039 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.45144433 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 3043316025 ps |
CPU time | 3.55 seconds |
Started | Jul 31 06:53:22 PM PDT 24 |
Finished | Jul 31 06:53:25 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-99df024e-982b-4177-8a31-2f3699f16f46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45144433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.45144433 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.3408270393 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 26794371260 ps |
CPU time | 121.7 seconds |
Started | Jul 31 06:53:19 PM PDT 24 |
Finished | Jul 31 06:55:20 PM PDT 24 |
Peak memory | 270760 kb |
Host | smart-198da33e-1f3f-4bc8-b6bd-c284071f651f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408270393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3408270393 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.2481174029 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 384034999 ps |
CPU time | 16.93 seconds |
Started | Jul 31 06:53:08 PM PDT 24 |
Finished | Jul 31 06:53:25 PM PDT 24 |
Peak memory | 263456 kb |
Host | smart-57c99e9c-0280-49e5-a6fc-987cded14b13 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481174029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2481174029 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3717011278 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 2704776061 ps |
CPU time | 19.6 seconds |
Started | Jul 31 06:53:19 PM PDT 24 |
Finished | Jul 31 06:53:39 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-1645c46a-fd3e-4266-88d6-4ca955d026c6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3717011278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3717011278 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1850944486 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 47692252006 ps |
CPU time | 181.29 seconds |
Started | Jul 31 06:53:07 PM PDT 24 |
Finished | Jul 31 06:56:08 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-6cd542f2-0bad-4c2a-853d-8de3c736cdac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850944486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.1850944486 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3110298729 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 746788705 ps |
CPU time | 45.52 seconds |
Started | Jul 31 06:53:14 PM PDT 24 |
Finished | Jul 31 06:53:59 PM PDT 24 |
Peak memory | 294200 kb |
Host | smart-6dd00c16-57ee-424e-9f9b-69dc4fd05b31 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110298729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3110298729 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.4035495784 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 11786391317 ps |
CPU time | 637.64 seconds |
Started | Jul 31 06:57:09 PM PDT 24 |
Finished | Jul 31 07:07:47 PM PDT 24 |
Peak memory | 379112 kb |
Host | smart-48285164-912a-4735-825b-c9b707783fe3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035495784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.4035495784 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.1929131989 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 40840585 ps |
CPU time | 0.66 seconds |
Started | Jul 31 06:57:10 PM PDT 24 |
Finished | Jul 31 06:57:11 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-c08af3ee-d00a-4a7e-81a0-ffc2043ba189 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929131989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1929131989 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.2049259209 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 112246514967 ps |
CPU time | 2126.43 seconds |
Started | Jul 31 06:57:10 PM PDT 24 |
Finished | Jul 31 07:32:37 PM PDT 24 |
Peak memory | 203840 kb |
Host | smart-2a0e1def-a395-4fa1-8747-856d21365283 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049259209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .2049259209 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.1421447903 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 44060038558 ps |
CPU time | 1295.34 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 07:18:44 PM PDT 24 |
Peak memory | 379172 kb |
Host | smart-75d1406b-4d65-4e13-8490-dfdbb84e3898 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421447903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.1421447903 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.2616684146 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 15323295546 ps |
CPU time | 22.84 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 06:57:31 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-67f059ac-27c2-4137-89f4-bd6d45519040 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616684146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.2616684146 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.207791662 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 3028623240 ps |
CPU time | 6.28 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 06:57:15 PM PDT 24 |
Peak memory | 211220 kb |
Host | smart-9f0ec4e2-ab6e-4bbd-b2bb-dbe85ec7c925 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207791662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.sram_ctrl_max_throughput.207791662 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2220396153 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 11148901954 ps |
CPU time | 89.57 seconds |
Started | Jul 31 06:57:11 PM PDT 24 |
Finished | Jul 31 06:58:41 PM PDT 24 |
Peak memory | 211488 kb |
Host | smart-e5390852-be4c-4651-ada7-2d5e256f4c1d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220396153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.2220396153 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.3954737880 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 2715044144 ps |
CPU time | 157.26 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 06:59:46 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-2876af55-82ae-44cb-b81d-ac3e14208cda |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954737880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.3954737880 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.3739571929 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 24933969067 ps |
CPU time | 941.4 seconds |
Started | Jul 31 06:57:07 PM PDT 24 |
Finished | Jul 31 07:12:49 PM PDT 24 |
Peak memory | 377000 kb |
Host | smart-2fb6e2d7-edd2-4055-b066-bd8f574d7b4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739571929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.3739571929 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.1222743739 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 12438340153 ps |
CPU time | 113.92 seconds |
Started | Jul 31 06:57:11 PM PDT 24 |
Finished | Jul 31 06:59:05 PM PDT 24 |
Peak memory | 359692 kb |
Host | smart-efc54568-f7b2-4aa3-8dbb-8fc223bdb526 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222743739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.1222743739 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3005648624 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 45434399205 ps |
CPU time | 353.42 seconds |
Started | Jul 31 06:57:07 PM PDT 24 |
Finished | Jul 31 07:03:01 PM PDT 24 |
Peak memory | 203356 kb |
Host | smart-44fe6dfb-5c8b-46b8-aa27-a346afef21f7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005648624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.3005648624 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.2863849680 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 1245637161 ps |
CPU time | 3.27 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 06:57:11 PM PDT 24 |
Peak memory | 203092 kb |
Host | smart-7d436406-3567-4685-a84e-d1fd28986a72 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863849680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2863849680 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.2004730749 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 18093156927 ps |
CPU time | 1847.94 seconds |
Started | Jul 31 06:57:09 PM PDT 24 |
Finished | Jul 31 07:27:57 PM PDT 24 |
Peak memory | 380132 kb |
Host | smart-ab571544-cdf9-45c1-9f2c-bf1db6f6772f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004730749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2004730749 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.2838987808 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 355834680 ps |
CPU time | 5.74 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 06:57:14 PM PDT 24 |
Peak memory | 214448 kb |
Host | smart-dc184e8c-622d-4ef8-a691-749dd9cb3e4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838987808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2838987808 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.1523152526 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 2213317604308 ps |
CPU time | 6104.17 seconds |
Started | Jul 31 06:57:07 PM PDT 24 |
Finished | Jul 31 08:38:52 PM PDT 24 |
Peak memory | 381552 kb |
Host | smart-49421ecb-24bd-462d-bba9-6e9cfa456bfa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523152526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.1523152526 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1496614689 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 1235950668 ps |
CPU time | 19.02 seconds |
Started | Jul 31 06:57:09 PM PDT 24 |
Finished | Jul 31 06:57:28 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-b0c14f22-7254-4ce0-8384-a41db0d8c72a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1496614689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1496614689 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.580004883 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 4786775946 ps |
CPU time | 313.28 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 07:02:22 PM PDT 24 |
Peak memory | 203328 kb |
Host | smart-04fe446a-249b-4f0a-b987-60b6b54f314e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580004883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_stress_pipeline.580004883 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3057846847 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 3136425710 ps |
CPU time | 24.36 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 06:57:33 PM PDT 24 |
Peak memory | 282200 kb |
Host | smart-232ccbcc-9974-4dff-8c8c-02a642efb9f1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057846847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.3057846847 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3581907083 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 30241518051 ps |
CPU time | 297.95 seconds |
Started | Jul 31 06:57:38 PM PDT 24 |
Finished | Jul 31 07:02:36 PM PDT 24 |
Peak memory | 328932 kb |
Host | smart-a5dfbeae-3a4e-44cf-8390-d570590061b1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581907083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.3581907083 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.1301765147 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 26074825 ps |
CPU time | 0.65 seconds |
Started | Jul 31 06:57:47 PM PDT 24 |
Finished | Jul 31 06:57:48 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-5f5c9646-5436-4c57-9339-d6cd25ab7f9e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301765147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1301765147 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.2462217821 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 99795750029 ps |
CPU time | 2285.15 seconds |
Started | Jul 31 06:57:41 PM PDT 24 |
Finished | Jul 31 07:35:46 PM PDT 24 |
Peak memory | 203508 kb |
Host | smart-d71392d6-bdd4-45f8-b400-e400873021f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462217821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .2462217821 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.3562471472 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 77706625919 ps |
CPU time | 963.95 seconds |
Started | Jul 31 06:57:39 PM PDT 24 |
Finished | Jul 31 07:13:43 PM PDT 24 |
Peak memory | 379164 kb |
Host | smart-d12e4388-6fba-4744-b2e0-b60028b64cf9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562471472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.3562471472 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.1434712841 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 7565761586 ps |
CPU time | 47.1 seconds |
Started | Jul 31 06:57:40 PM PDT 24 |
Finished | Jul 31 06:58:27 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-a3afda85-5bfa-4bef-8676-9564c337114c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434712841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1434712841 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.893984024 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 5919593845 ps |
CPU time | 34.59 seconds |
Started | Jul 31 06:57:47 PM PDT 24 |
Finished | Jul 31 06:58:22 PM PDT 24 |
Peak memory | 284880 kb |
Host | smart-6d774105-2bce-4156-a5ae-413655cd440f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893984024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.sram_ctrl_max_throughput.893984024 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3302331601 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 1658287973 ps |
CPU time | 122.43 seconds |
Started | Jul 31 06:57:40 PM PDT 24 |
Finished | Jul 31 06:59:42 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-750bfbd8-67bb-422b-bc3e-72e38cbf8718 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302331601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.3302331601 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.1506892874 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 276675977649 ps |
CPU time | 376.01 seconds |
Started | Jul 31 06:57:46 PM PDT 24 |
Finished | Jul 31 07:04:03 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-0f049576-cce4-4f73-95dd-7e7a73a68b11 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506892874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.1506892874 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.3429772065 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 6010754606 ps |
CPU time | 382.27 seconds |
Started | Jul 31 06:57:10 PM PDT 24 |
Finished | Jul 31 07:03:33 PM PDT 24 |
Peak memory | 380096 kb |
Host | smart-835aedc3-0bc2-4980-8155-e5576c22e957 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429772065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.3429772065 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.1773668315 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 1198123174 ps |
CPU time | 7.39 seconds |
Started | Jul 31 06:57:41 PM PDT 24 |
Finished | Jul 31 06:57:48 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-9124e249-8dd4-4df9-bf72-79e89eab337f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773668315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.1773668315 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.458712887 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 361956627 ps |
CPU time | 3.37 seconds |
Started | Jul 31 06:57:47 PM PDT 24 |
Finished | Jul 31 06:57:50 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-4e7f4f05-51d8-40b4-90ce-9b52d6919334 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458712887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.458712887 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.2673611433 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 2926477263 ps |
CPU time | 653.66 seconds |
Started | Jul 31 06:57:41 PM PDT 24 |
Finished | Jul 31 07:08:35 PM PDT 24 |
Peak memory | 380052 kb |
Host | smart-5af41a50-64da-4ecf-a773-a4961ec8df3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673611433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2673611433 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.1400749494 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 15125731531 ps |
CPU time | 79.75 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 06:58:27 PM PDT 24 |
Peak memory | 348532 kb |
Host | smart-d35c5f47-8b95-435e-8f64-fadf59684d4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400749494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1400749494 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.1637084383 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 69584387342 ps |
CPU time | 3882.35 seconds |
Started | Jul 31 06:57:40 PM PDT 24 |
Finished | Jul 31 08:02:23 PM PDT 24 |
Peak memory | 381220 kb |
Host | smart-fd6e94dd-815b-40ca-b6e1-63e1ebe00dc7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637084383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.1637084383 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1548040623 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 1799730786 ps |
CPU time | 17.32 seconds |
Started | Jul 31 06:57:40 PM PDT 24 |
Finished | Jul 31 06:57:58 PM PDT 24 |
Peak memory | 211556 kb |
Host | smart-2264b34e-217b-44e8-a559-6cb5312b0a3b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1548040623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1548040623 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.903786586 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 47038351504 ps |
CPU time | 372.48 seconds |
Started | Jul 31 06:57:38 PM PDT 24 |
Finished | Jul 31 07:03:51 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-875d0b1f-33f2-4782-9bf1-ad1ea8ca210b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903786586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .sram_ctrl_stress_pipeline.903786586 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3766856841 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 695561293 ps |
CPU time | 7.36 seconds |
Started | Jul 31 06:57:43 PM PDT 24 |
Finished | Jul 31 06:57:50 PM PDT 24 |
Peak memory | 219504 kb |
Host | smart-24e006b3-1ab1-44c0-b82d-04679b536812 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766856841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3766856841 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.537638097 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 16693434470 ps |
CPU time | 1227.56 seconds |
Started | Jul 31 06:57:40 PM PDT 24 |
Finished | Jul 31 07:18:08 PM PDT 24 |
Peak memory | 372988 kb |
Host | smart-7ad19713-2c31-47a4-9492-c8916ed52299 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537638097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_access_during_key_req.537638097 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.1956263912 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 16302780 ps |
CPU time | 0.68 seconds |
Started | Jul 31 06:57:50 PM PDT 24 |
Finished | Jul 31 06:57:50 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-7028b370-b2ba-4dbe-8090-e4e3940d1327 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956263912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.1956263912 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.2465068309 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 27453777048 ps |
CPU time | 953.82 seconds |
Started | Jul 31 06:57:41 PM PDT 24 |
Finished | Jul 31 07:13:35 PM PDT 24 |
Peak memory | 204108 kb |
Host | smart-d589c2b8-a6df-4e4c-805e-3b05fba7c64b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465068309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .2465068309 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.819251454 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 14642059776 ps |
CPU time | 992.28 seconds |
Started | Jul 31 06:57:46 PM PDT 24 |
Finished | Jul 31 07:14:19 PM PDT 24 |
Peak memory | 363804 kb |
Host | smart-61104eae-fc01-4ebe-b171-933082f3b051 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819251454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executabl e.819251454 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.1035180327 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 25138781350 ps |
CPU time | 32.18 seconds |
Started | Jul 31 06:57:45 PM PDT 24 |
Finished | Jul 31 06:58:17 PM PDT 24 |
Peak memory | 211356 kb |
Host | smart-5a2c78c7-4ea7-4b7e-835d-4410b8300f59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035180327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.1035180327 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.2272990252 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 1704811363 ps |
CPU time | 63.6 seconds |
Started | Jul 31 06:57:41 PM PDT 24 |
Finished | Jul 31 06:58:44 PM PDT 24 |
Peak memory | 314604 kb |
Host | smart-19764d9e-d4ec-4735-8ca1-3532b2f23bc2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272990252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.2272990252 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3434415134 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 3758736527 ps |
CPU time | 77.52 seconds |
Started | Jul 31 06:57:48 PM PDT 24 |
Finished | Jul 31 06:59:06 PM PDT 24 |
Peak memory | 211580 kb |
Host | smart-eb3ff2b6-4a30-4f30-a34d-8a20ee9bf884 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434415134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.3434415134 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.2854620463 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 115392854004 ps |
CPU time | 342.36 seconds |
Started | Jul 31 06:57:48 PM PDT 24 |
Finished | Jul 31 07:03:30 PM PDT 24 |
Peak memory | 211572 kb |
Host | smart-4357ef80-b12d-43a3-a1b8-b0832960f29b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854620463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.2854620463 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.1474072778 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 6064005935 ps |
CPU time | 291.06 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 07:02:40 PM PDT 24 |
Peak memory | 370920 kb |
Host | smart-13fcba40-8fac-4ea2-9c0c-d1c734a0356a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474072778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.1474072778 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.2334842377 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 3869821980 ps |
CPU time | 102.46 seconds |
Started | Jul 31 06:57:39 PM PDT 24 |
Finished | Jul 31 06:59:22 PM PDT 24 |
Peak memory | 360736 kb |
Host | smart-82d7d08d-0d7d-405a-b726-84f2db0979a7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334842377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.2334842377 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.721470029 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 10505591351 ps |
CPU time | 369.18 seconds |
Started | Jul 31 06:57:39 PM PDT 24 |
Finished | Jul 31 07:03:48 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-45102015-94bd-435e-a037-86c94e0e61ce |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721470029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.sram_ctrl_partial_access_b2b.721470029 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.2519475027 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 1343919248 ps |
CPU time | 3.34 seconds |
Started | Jul 31 06:57:46 PM PDT 24 |
Finished | Jul 31 06:57:49 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-f767d355-7200-4f19-8f99-d4095acb0ec4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519475027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2519475027 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.3910039929 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 5752092254 ps |
CPU time | 243.62 seconds |
Started | Jul 31 06:57:46 PM PDT 24 |
Finished | Jul 31 07:01:49 PM PDT 24 |
Peak memory | 373864 kb |
Host | smart-fea92d27-4d33-4dc7-ad85-792bc56e4e79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910039929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3910039929 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.578286409 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 2222863685 ps |
CPU time | 15.52 seconds |
Started | Jul 31 06:57:45 PM PDT 24 |
Finished | Jul 31 06:58:01 PM PDT 24 |
Peak memory | 203344 kb |
Host | smart-9ca3d0cd-371c-444f-b155-222197c6211e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578286409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.578286409 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.3455906582 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 1149757502473 ps |
CPU time | 4222.06 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 08:08:12 PM PDT 24 |
Peak memory | 219188 kb |
Host | smart-cc023130-1b2f-41ae-a76a-2b6ff0970687 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455906582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.3455906582 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4293203942 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 4277692905 ps |
CPU time | 30.09 seconds |
Started | Jul 31 06:57:50 PM PDT 24 |
Finished | Jul 31 06:58:20 PM PDT 24 |
Peak memory | 218868 kb |
Host | smart-af186c86-fbd2-482e-a056-09aea4dda314 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4293203942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.4293203942 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1518111914 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 4188912262 ps |
CPU time | 278.78 seconds |
Started | Jul 31 06:57:41 PM PDT 24 |
Finished | Jul 31 07:02:20 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-c732fbd6-7c77-49ac-9ecc-f030406233e8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518111914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.1518111914 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1976377688 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 7022297433 ps |
CPU time | 18.97 seconds |
Started | Jul 31 06:57:44 PM PDT 24 |
Finished | Jul 31 06:58:03 PM PDT 24 |
Peak memory | 255176 kb |
Host | smart-a31ea6e2-45b2-4f28-9a39-026aa14d2a74 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976377688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1976377688 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2399750021 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 19096124253 ps |
CPU time | 1188.47 seconds |
Started | Jul 31 06:57:50 PM PDT 24 |
Finished | Jul 31 07:17:39 PM PDT 24 |
Peak memory | 377144 kb |
Host | smart-19981031-b414-45c3-9492-3121943be796 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399750021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.2399750021 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.2964921598 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 33182864 ps |
CPU time | 0.64 seconds |
Started | Jul 31 06:57:48 PM PDT 24 |
Finished | Jul 31 06:57:49 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-e8244f4b-cab7-4d46-b148-ade933c1f21d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964921598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.2964921598 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.4110212101 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 38604309485 ps |
CPU time | 866.37 seconds |
Started | Jul 31 06:57:47 PM PDT 24 |
Finished | Jul 31 07:12:14 PM PDT 24 |
Peak memory | 204128 kb |
Host | smart-cc681f91-1909-44a5-9e9e-fbaa593c8b21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110212101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .4110212101 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.3083201712 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 13953372323 ps |
CPU time | 954 seconds |
Started | Jul 31 06:57:44 PM PDT 24 |
Finished | Jul 31 07:13:38 PM PDT 24 |
Peak memory | 377076 kb |
Host | smart-4bd1ee1e-4d75-4a7b-86f3-1bf2f5fec90f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083201712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.3083201712 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.1297033757 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 8771590274 ps |
CPU time | 43.31 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 06:58:32 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-f73579c3-d66d-44db-8337-ae6e967aca65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297033757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.1297033757 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.1048542459 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 2643833589 ps |
CPU time | 117.01 seconds |
Started | Jul 31 06:57:48 PM PDT 24 |
Finished | Jul 31 06:59:46 PM PDT 24 |
Peak memory | 370208 kb |
Host | smart-4fc77783-6b90-4182-aced-c25f9de77ab8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048542459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.1048542459 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.4213465735 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 3024246519 ps |
CPU time | 83.76 seconds |
Started | Jul 31 06:57:54 PM PDT 24 |
Finished | Jul 31 06:59:18 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-7d7007ce-d611-4a45-994b-ac889af287b5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213465735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.4213465735 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.4276617296 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 2637081394 ps |
CPU time | 144.59 seconds |
Started | Jul 31 06:57:48 PM PDT 24 |
Finished | Jul 31 07:00:12 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-0b60cfb3-e4d2-4163-995a-6ba8add17667 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276617296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.4276617296 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.3156793579 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 6095048612 ps |
CPU time | 344.25 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 07:03:34 PM PDT 24 |
Peak memory | 369792 kb |
Host | smart-ad5dbc31-df8b-446a-a566-1cfbb0ed5705 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156793579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.3156793579 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.3802434666 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 422821050 ps |
CPU time | 19.55 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 06:58:08 PM PDT 24 |
Peak memory | 270648 kb |
Host | smart-502edfbc-9f1f-4aff-9531-652e85561621 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802434666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.3802434666 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3525739944 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 9230362430 ps |
CPU time | 233.68 seconds |
Started | Jul 31 06:57:47 PM PDT 24 |
Finished | Jul 31 07:01:41 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-c76ce880-72d3-4a23-8f5f-ae465e8b843b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525739944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.3525739944 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.234567376 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 353979110 ps |
CPU time | 3.26 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 06:57:53 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-4fe381f9-ab0b-4f96-b58f-7d9c8a65a12e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234567376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.234567376 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.1562072269 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 1355209747 ps |
CPU time | 4.16 seconds |
Started | Jul 31 06:57:46 PM PDT 24 |
Finished | Jul 31 06:57:51 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-a047558f-dfe3-482e-ac50-e077461a8955 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562072269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1562072269 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.2346976244 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 63668662470 ps |
CPU time | 4502.99 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 08:12:52 PM PDT 24 |
Peak memory | 389360 kb |
Host | smart-ee5ff5e8-f82b-449c-a266-7fc1f687c5a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346976244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.2346976244 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3986052092 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 4707066693 ps |
CPU time | 148.95 seconds |
Started | Jul 31 06:57:47 PM PDT 24 |
Finished | Jul 31 07:00:16 PM PDT 24 |
Peak memory | 203300 kb |
Host | smart-f84ba90b-cfbe-4020-8ad1-a3c5565beeda |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986052092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.3986052092 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.4061194627 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 2486222380 ps |
CPU time | 26.46 seconds |
Started | Jul 31 06:57:46 PM PDT 24 |
Finished | Jul 31 06:58:13 PM PDT 24 |
Peak memory | 280808 kb |
Host | smart-df5482ab-1cac-40e1-aeb0-a229c5a167a0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061194627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.4061194627 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1258091442 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 15452473198 ps |
CPU time | 872.64 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 07:12:22 PM PDT 24 |
Peak memory | 351432 kb |
Host | smart-49fad31c-987b-44d0-a442-d9969799ce79 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258091442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.1258091442 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.3196825770 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 18332515 ps |
CPU time | 0.64 seconds |
Started | Jul 31 06:57:51 PM PDT 24 |
Finished | Jul 31 06:57:52 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-337b7a12-3e25-416f-ab8e-89b343ac2b7e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196825770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3196825770 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.378421096 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 169878291760 ps |
CPU time | 1359.43 seconds |
Started | Jul 31 06:57:50 PM PDT 24 |
Finished | Jul 31 07:20:30 PM PDT 24 |
Peak memory | 204288 kb |
Host | smart-1a3295fb-8f38-4153-9bf3-b0e8f50e06e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378421096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection. 378421096 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.1467666676 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 8019757223 ps |
CPU time | 1073.38 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 07:15:43 PM PDT 24 |
Peak memory | 376004 kb |
Host | smart-b4b22f28-93a5-4b75-b00b-f635b9356d56 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467666676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.1467666676 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.690515125 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 42702789053 ps |
CPU time | 62.38 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 06:58:52 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-917dc7a1-8014-41c1-a28a-9b5b79a494c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690515125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_esc alation.690515125 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.1397650118 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 807809662 ps |
CPU time | 18.55 seconds |
Started | Jul 31 06:57:50 PM PDT 24 |
Finished | Jul 31 06:58:08 PM PDT 24 |
Peak memory | 254268 kb |
Host | smart-c422fa79-b7e5-437f-b5da-c8dc14d2cb47 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397650118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.1397650118 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3934638810 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 992804764 ps |
CPU time | 66.02 seconds |
Started | Jul 31 06:57:55 PM PDT 24 |
Finished | Jul 31 06:59:02 PM PDT 24 |
Peak memory | 219468 kb |
Host | smart-f023b69a-a4e6-4cf7-8356-d688f74260b8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934638810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.3934638810 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.427120655 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 42201413163 ps |
CPU time | 345.32 seconds |
Started | Jul 31 06:57:47 PM PDT 24 |
Finished | Jul 31 07:03:33 PM PDT 24 |
Peak memory | 211460 kb |
Host | smart-69bae82b-48d3-4ed5-ad03-7fd0a02b7b0a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427120655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _mem_walk.427120655 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.1989126659 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 3972005650 ps |
CPU time | 698.81 seconds |
Started | Jul 31 06:57:50 PM PDT 24 |
Finished | Jul 31 07:09:29 PM PDT 24 |
Peak memory | 369888 kb |
Host | smart-8233c866-5fe3-4174-ae56-501fddcac5a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989126659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.1989126659 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.1634972505 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 2372430751 ps |
CPU time | 20.69 seconds |
Started | Jul 31 06:57:47 PM PDT 24 |
Finished | Jul 31 06:58:08 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-9713124c-57a9-49f0-bdc3-35e97ac4a75a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634972505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.1634972505 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1039736826 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 32300608414 ps |
CPU time | 388.42 seconds |
Started | Jul 31 06:57:54 PM PDT 24 |
Finished | Jul 31 07:04:22 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-e574af55-e37c-4291-8b5b-2a250ad5ac52 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039736826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.1039736826 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.2737266856 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 407168319 ps |
CPU time | 3.22 seconds |
Started | Jul 31 06:57:50 PM PDT 24 |
Finished | Jul 31 06:57:53 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-bcfb2e73-dfd0-4b61-a313-78fa0ba75eb3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737266856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2737266856 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.2210758819 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 86810324681 ps |
CPU time | 1194.72 seconds |
Started | Jul 31 06:57:50 PM PDT 24 |
Finished | Jul 31 07:17:45 PM PDT 24 |
Peak memory | 381112 kb |
Host | smart-7ef4516f-a171-48a3-bdf0-3ca9089b58bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210758819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2210758819 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.3663493345 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 7363571682 ps |
CPU time | 12.12 seconds |
Started | Jul 31 06:57:50 PM PDT 24 |
Finished | Jul 31 06:58:02 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-7177e64c-365b-4f53-8dd3-8bc2657ebe22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663493345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3663493345 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.313368727 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 1004187113227 ps |
CPU time | 6529 seconds |
Started | Jul 31 06:57:53 PM PDT 24 |
Finished | Jul 31 08:46:43 PM PDT 24 |
Peak memory | 378496 kb |
Host | smart-113d5a17-ad5b-4349-86ad-4881d69700ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313368727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_stress_all.313368727 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1309123712 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 917034083 ps |
CPU time | 27.45 seconds |
Started | Jul 31 06:57:53 PM PDT 24 |
Finished | Jul 31 06:58:21 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-7131ab95-8ab0-4c16-8445-843a325136e2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1309123712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1309123712 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1825839414 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 21639983362 ps |
CPU time | 355.26 seconds |
Started | Jul 31 06:57:49 PM PDT 24 |
Finished | Jul 31 07:03:45 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-f381dd4e-afac-445a-b1c4-6b5c96eb54e0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825839414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.1825839414 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1642593261 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 1489681607 ps |
CPU time | 44.03 seconds |
Started | Jul 31 06:57:48 PM PDT 24 |
Finished | Jul 31 06:58:33 PM PDT 24 |
Peak memory | 308576 kb |
Host | smart-0ecdf7d5-850a-4254-870e-d8bed9c80752 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642593261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1642593261 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.854745601 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 17867555225 ps |
CPU time | 764.2 seconds |
Started | Jul 31 06:57:56 PM PDT 24 |
Finished | Jul 31 07:10:40 PM PDT 24 |
Peak memory | 371992 kb |
Host | smart-8c44bfcd-a44b-4f82-8f1d-d0f8f3a07083 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854745601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_access_during_key_req.854745601 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.563711274 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 21811183 ps |
CPU time | 0.66 seconds |
Started | Jul 31 06:57:52 PM PDT 24 |
Finished | Jul 31 06:57:53 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-b722b175-35cf-4bd6-a2e2-1f1393e90777 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563711274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.563711274 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.3190280795 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 158087109007 ps |
CPU time | 2549.26 seconds |
Started | Jul 31 06:57:53 PM PDT 24 |
Finished | Jul 31 07:40:22 PM PDT 24 |
Peak memory | 204124 kb |
Host | smart-17e7b816-968b-43af-96a4-773b29901649 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190280795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .3190280795 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.2239036301 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 72193140438 ps |
CPU time | 534.73 seconds |
Started | Jul 31 06:57:54 PM PDT 24 |
Finished | Jul 31 07:06:48 PM PDT 24 |
Peak memory | 368796 kb |
Host | smart-2c55567b-d9c8-4065-9b94-ad9e37fb5cb8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239036301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.2239036301 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.316937084 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 8705127252 ps |
CPU time | 55.95 seconds |
Started | Jul 31 06:57:54 PM PDT 24 |
Finished | Jul 31 06:58:50 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-6909ba96-4c59-48e8-8662-df47238077d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316937084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_esc alation.316937084 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.1136264205 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 761901031 ps |
CPU time | 95.26 seconds |
Started | Jul 31 06:57:52 PM PDT 24 |
Finished | Jul 31 06:59:28 PM PDT 24 |
Peak memory | 349364 kb |
Host | smart-5e4d130b-62f9-49e9-b75a-7cc93e569e41 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136264205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.1136264205 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2586844664 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 5231123818 ps |
CPU time | 166.61 seconds |
Started | Jul 31 06:57:57 PM PDT 24 |
Finished | Jul 31 07:00:43 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-f42ca48b-e6a8-44d2-8e0b-98f6dc46c2c1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586844664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.2586844664 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.3841061035 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 28787857538 ps |
CPU time | 154.28 seconds |
Started | Jul 31 06:57:56 PM PDT 24 |
Finished | Jul 31 07:00:30 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-4fd47511-a35b-4703-81a5-e52c21b13abe |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841061035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.3841061035 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.1326412485 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 34077589664 ps |
CPU time | 603.1 seconds |
Started | Jul 31 06:57:53 PM PDT 24 |
Finished | Jul 31 07:07:56 PM PDT 24 |
Peak memory | 378104 kb |
Host | smart-8b6ced8f-cf10-4008-bc9f-c2310fdd1468 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326412485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.1326412485 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.531814186 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 1624680858 ps |
CPU time | 24.19 seconds |
Started | Jul 31 06:57:51 PM PDT 24 |
Finished | Jul 31 06:58:15 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-6a73574e-8690-48fa-88e3-81d76bb1a8a4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531814186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s ram_ctrl_partial_access.531814186 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1316146821 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 34654637040 ps |
CPU time | 536.84 seconds |
Started | Jul 31 06:57:55 PM PDT 24 |
Finished | Jul 31 07:06:52 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-dadec281-07ef-459b-a6a7-360577ff7270 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316146821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.1316146821 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.2144718485 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 1411487787 ps |
CPU time | 3.47 seconds |
Started | Jul 31 06:57:56 PM PDT 24 |
Finished | Jul 31 06:58:00 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-789138dc-ab02-4a8f-bcb0-4fd822cf01eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144718485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2144718485 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.2207394366 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 9860572739 ps |
CPU time | 423.31 seconds |
Started | Jul 31 06:57:50 PM PDT 24 |
Finished | Jul 31 07:04:53 PM PDT 24 |
Peak memory | 359808 kb |
Host | smart-a35ef7ad-c602-4a1e-9bf6-48ae739688b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207394366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2207394366 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.3099973519 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 2217324193 ps |
CPU time | 16.83 seconds |
Started | Jul 31 06:57:52 PM PDT 24 |
Finished | Jul 31 06:58:09 PM PDT 24 |
Peak memory | 257952 kb |
Host | smart-54c246dd-7373-4621-b9a4-4d71b1527eb9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099973519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.3099973519 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.3743084787 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 378862324581 ps |
CPU time | 8474.95 seconds |
Started | Jul 31 06:57:51 PM PDT 24 |
Finished | Jul 31 09:19:07 PM PDT 24 |
Peak memory | 380096 kb |
Host | smart-97f8044c-8262-43b7-b858-1f474289a6a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743084787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.3743084787 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2932448628 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 347576002 ps |
CPU time | 16.29 seconds |
Started | Jul 31 06:57:54 PM PDT 24 |
Finished | Jul 31 06:58:11 PM PDT 24 |
Peak memory | 211580 kb |
Host | smart-e51a58c9-05fb-494b-9dbf-17cb8c5d647c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2932448628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2932448628 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.868190928 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 11090290451 ps |
CPU time | 201.84 seconds |
Started | Jul 31 06:57:51 PM PDT 24 |
Finished | Jul 31 07:01:13 PM PDT 24 |
Peak memory | 203316 kb |
Host | smart-6870f20c-d2e1-4fa4-9ad3-aaf80f7051cf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868190928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .sram_ctrl_stress_pipeline.868190928 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4191499596 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 3597061648 ps |
CPU time | 11.39 seconds |
Started | Jul 31 06:57:55 PM PDT 24 |
Finished | Jul 31 06:58:07 PM PDT 24 |
Peak memory | 228728 kb |
Host | smart-ec34eab9-5bb5-4bbc-abac-c2c954fa9b1f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191499596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.4191499596 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.3970902029 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 52887802575 ps |
CPU time | 1853.4 seconds |
Started | Jul 31 06:57:56 PM PDT 24 |
Finished | Jul 31 07:28:49 PM PDT 24 |
Peak memory | 378152 kb |
Host | smart-6dc1e8b4-5d27-4f45-84d4-d4132f4b0487 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970902029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.3970902029 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.283154235 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 17005781 ps |
CPU time | 0.67 seconds |
Started | Jul 31 06:57:54 PM PDT 24 |
Finished | Jul 31 06:57:55 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-7717fc36-2766-4ca1-849b-1cfd708ee5ec |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283154235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.283154235 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.1516567237 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 193494275499 ps |
CPU time | 2145.72 seconds |
Started | Jul 31 06:57:57 PM PDT 24 |
Finished | Jul 31 07:33:43 PM PDT 24 |
Peak memory | 203428 kb |
Host | smart-0b7b8ce9-0e4f-4ea3-8a21-dfc2f92dc112 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516567237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .1516567237 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.1815492266 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 87862356468 ps |
CPU time | 1321.71 seconds |
Started | Jul 31 06:57:54 PM PDT 24 |
Finished | Jul 31 07:19:56 PM PDT 24 |
Peak memory | 373000 kb |
Host | smart-42425c72-cf51-4484-831a-0f70adc02463 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815492266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.1815492266 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.277594921 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 5250851766 ps |
CPU time | 18.02 seconds |
Started | Jul 31 06:57:56 PM PDT 24 |
Finished | Jul 31 06:58:14 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-9bff0d0a-67db-4eb3-931a-e2c3cb967bcb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277594921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_esc alation.277594921 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.1514080895 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 3123095256 ps |
CPU time | 11.74 seconds |
Started | Jul 31 06:57:54 PM PDT 24 |
Finished | Jul 31 06:58:06 PM PDT 24 |
Peak memory | 235872 kb |
Host | smart-12fb263b-72ff-4646-9eb4-3eaa70e8e0e5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514080895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.1514080895 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3373681314 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 3092723804 ps |
CPU time | 78.43 seconds |
Started | Jul 31 06:57:56 PM PDT 24 |
Finished | Jul 31 06:59:14 PM PDT 24 |
Peak memory | 219528 kb |
Host | smart-431bac5d-4e30-4f86-a087-6b6885d4cc6c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373681314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.3373681314 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.1334167477 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 22027548133 ps |
CPU time | 169.93 seconds |
Started | Jul 31 06:57:53 PM PDT 24 |
Finished | Jul 31 07:00:43 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-66398fc5-80cf-4401-aecc-ebfba7c68c29 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334167477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.1334167477 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.449644387 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 92012947643 ps |
CPU time | 1641.26 seconds |
Started | Jul 31 06:57:53 PM PDT 24 |
Finished | Jul 31 07:25:15 PM PDT 24 |
Peak memory | 381048 kb |
Host | smart-912d3a8b-64cd-406d-8358-128a526ece91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449644387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multip le_keys.449644387 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.345581968 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 1700183360 ps |
CPU time | 14.57 seconds |
Started | Jul 31 06:58:01 PM PDT 24 |
Finished | Jul 31 06:58:15 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-c11ee4a0-ce64-49e2-b9d4-b631e93b4a48 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345581968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s ram_ctrl_partial_access.345581968 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.731913378 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 30630998506 ps |
CPU time | 322.3 seconds |
Started | Jul 31 06:57:53 PM PDT 24 |
Finished | Jul 31 07:03:16 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-1d15b23f-c5c4-4396-891c-fa163665dda5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731913378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.sram_ctrl_partial_access_b2b.731913378 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.1769603870 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 1411940409 ps |
CPU time | 3.28 seconds |
Started | Jul 31 06:57:55 PM PDT 24 |
Finished | Jul 31 06:57:59 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-f6796445-3518-40e0-9f50-ab2a117fc3e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769603870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1769603870 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.30252035 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 31379724892 ps |
CPU time | 1606.88 seconds |
Started | Jul 31 06:57:54 PM PDT 24 |
Finished | Jul 31 07:24:41 PM PDT 24 |
Peak memory | 380192 kb |
Host | smart-c7ebebe6-605e-4666-9e93-c0be0ce54041 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30252035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.30252035 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.3863342397 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 1413683379 ps |
CPU time | 6.03 seconds |
Started | Jul 31 06:57:56 PM PDT 24 |
Finished | Jul 31 06:58:02 PM PDT 24 |
Peak memory | 203012 kb |
Host | smart-f974a647-cce0-4b61-b484-40b1d4b0ec88 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863342397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3863342397 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.878121824 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 36670045349 ps |
CPU time | 1851.84 seconds |
Started | Jul 31 06:57:58 PM PDT 24 |
Finished | Jul 31 07:28:50 PM PDT 24 |
Peak memory | 382236 kb |
Host | smart-b0c80388-89b9-4297-848c-c3c8b3c46b79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878121824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_stress_all.878121824 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1944613067 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 7744298989 ps |
CPU time | 125.48 seconds |
Started | Jul 31 06:57:57 PM PDT 24 |
Finished | Jul 31 07:00:02 PM PDT 24 |
Peak memory | 329044 kb |
Host | smart-afeeb92a-ad7c-4365-b5a4-34b12c6e3fdb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1944613067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1944613067 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1293628493 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 5844897171 ps |
CPU time | 391.66 seconds |
Started | Jul 31 06:57:56 PM PDT 24 |
Finished | Jul 31 07:04:28 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-20d88bd1-a93c-4a75-853e-753186b25d20 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293628493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.1293628493 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3678185155 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 1630286394 ps |
CPU time | 52.85 seconds |
Started | Jul 31 06:57:53 PM PDT 24 |
Finished | Jul 31 06:58:46 PM PDT 24 |
Peak memory | 314640 kb |
Host | smart-b47b0efd-5cee-4250-b595-dd5c22590e0e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678185155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.3678185155 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1004585959 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 104658233992 ps |
CPU time | 1021.39 seconds |
Started | Jul 31 06:58:00 PM PDT 24 |
Finished | Jul 31 07:15:01 PM PDT 24 |
Peak memory | 366224 kb |
Host | smart-1879e4ac-ac7d-4427-94b0-0fba7c13c570 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004585959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.1004585959 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.2743324767 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 18298647855 ps |
CPU time | 646.02 seconds |
Started | Jul 31 06:57:59 PM PDT 24 |
Finished | Jul 31 07:08:45 PM PDT 24 |
Peak memory | 203396 kb |
Host | smart-eca8809d-773c-4b4c-bac4-3bfb53581b48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743324767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .2743324767 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.3125980307 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 24551013010 ps |
CPU time | 427.23 seconds |
Started | Jul 31 06:57:59 PM PDT 24 |
Finished | Jul 31 07:05:07 PM PDT 24 |
Peak memory | 355640 kb |
Host | smart-f3788052-41e7-4d1b-a0ea-6ca46f438f31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125980307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.3125980307 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.2175551834 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 3994427701 ps |
CPU time | 9.92 seconds |
Started | Jul 31 06:58:00 PM PDT 24 |
Finished | Jul 31 06:58:10 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-9ce78012-dbda-47a6-b163-3db53aed7102 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175551834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.2175551834 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.1286381136 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 3475051210 ps |
CPU time | 151.13 seconds |
Started | Jul 31 06:57:57 PM PDT 24 |
Finished | Jul 31 07:00:28 PM PDT 24 |
Peak memory | 373268 kb |
Host | smart-5f033830-ff43-4491-a1f1-f3e1a277b469 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286381136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.1286381136 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2771029223 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 2483038350 ps |
CPU time | 81.31 seconds |
Started | Jul 31 06:58:06 PM PDT 24 |
Finished | Jul 31 06:59:28 PM PDT 24 |
Peak memory | 219600 kb |
Host | smart-a730640e-74b6-47d6-9f8e-7fed97c516b4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771029223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.2771029223 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.705794870 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 72813766467 ps |
CPU time | 336.13 seconds |
Started | Jul 31 06:58:04 PM PDT 24 |
Finished | Jul 31 07:03:41 PM PDT 24 |
Peak memory | 204312 kb |
Host | smart-653f963f-e00f-4df9-9d8f-ecea4b7aa5ce |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705794870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _mem_walk.705794870 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.618623296 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 11856954286 ps |
CPU time | 904.16 seconds |
Started | Jul 31 06:57:57 PM PDT 24 |
Finished | Jul 31 07:13:01 PM PDT 24 |
Peak memory | 378164 kb |
Host | smart-be46f2e5-a326-41f2-8fc5-3ddb00d1f9ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618623296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multip le_keys.618623296 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.2760608051 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 679798806 ps |
CPU time | 9.28 seconds |
Started | Jul 31 06:58:05 PM PDT 24 |
Finished | Jul 31 06:58:15 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-59d5bee3-e908-48a0-8cab-875e2e34bbf2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760608051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.2760608051 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3311058226 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 10469087131 ps |
CPU time | 242.71 seconds |
Started | Jul 31 06:57:59 PM PDT 24 |
Finished | Jul 31 07:02:02 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-ff759a6e-566c-4642-b794-28aaf059d9cb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311058226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.3311058226 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.120613059 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 2922127594 ps |
CPU time | 904.89 seconds |
Started | Jul 31 06:57:59 PM PDT 24 |
Finished | Jul 31 07:13:04 PM PDT 24 |
Peak memory | 377088 kb |
Host | smart-7b83cd77-288f-44d0-9d7e-12fa1e0faac9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120613059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.120613059 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.1847464774 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 780546883 ps |
CPU time | 146.41 seconds |
Started | Jul 31 06:57:56 PM PDT 24 |
Finished | Jul 31 07:00:23 PM PDT 24 |
Peak memory | 370764 kb |
Host | smart-c83b07b0-941f-4a21-9982-4a80f50856eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847464774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1847464774 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.2831322839 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 221451896821 ps |
CPU time | 2180.68 seconds |
Started | Jul 31 06:58:06 PM PDT 24 |
Finished | Jul 31 07:34:27 PM PDT 24 |
Peak memory | 379100 kb |
Host | smart-2b4532dd-70f0-4180-a1ae-34668d7cb8bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831322839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.2831322839 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.212265790 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 411798299 ps |
CPU time | 13.9 seconds |
Started | Jul 31 06:58:06 PM PDT 24 |
Finished | Jul 31 06:58:20 PM PDT 24 |
Peak memory | 211480 kb |
Host | smart-1d6a72e7-2a3c-4777-bdfb-9a4b1446ed5c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=212265790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.212265790 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2117467639 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 15090321867 ps |
CPU time | 245.32 seconds |
Started | Jul 31 06:58:00 PM PDT 24 |
Finished | Jul 31 07:02:05 PM PDT 24 |
Peak memory | 203268 kb |
Host | smart-156941c6-44d3-4d14-8f6d-0e823e46dee6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117467639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.2117467639 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1048549018 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 1458504243 ps |
CPU time | 15.64 seconds |
Started | Jul 31 06:57:57 PM PDT 24 |
Finished | Jul 31 06:58:13 PM PDT 24 |
Peak memory | 252196 kb |
Host | smart-29ac969a-c57e-413c-859c-fbaa9603bcd6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048549018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1048549018 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3981889517 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 44901999133 ps |
CPU time | 1513.19 seconds |
Started | Jul 31 06:58:19 PM PDT 24 |
Finished | Jul 31 07:23:32 PM PDT 24 |
Peak memory | 380240 kb |
Host | smart-3e3c01b3-6398-4d70-a8d8-a0d61b3b28b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981889517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.3981889517 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.3732610681 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 26129226 ps |
CPU time | 0.63 seconds |
Started | Jul 31 06:58:31 PM PDT 24 |
Finished | Jul 31 06:58:31 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-cd22e516-34aa-4521-80ab-14edf142ba62 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732610681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3732610681 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.2255813690 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 230886949971 ps |
CPU time | 1303.38 seconds |
Started | Jul 31 06:58:09 PM PDT 24 |
Finished | Jul 31 07:19:53 PM PDT 24 |
Peak memory | 203764 kb |
Host | smart-ff83fc3c-c325-4195-adb7-10be524f4571 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255813690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .2255813690 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.3363113628 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 15653273397 ps |
CPU time | 333.35 seconds |
Started | Jul 31 06:58:18 PM PDT 24 |
Finished | Jul 31 07:03:52 PM PDT 24 |
Peak memory | 336488 kb |
Host | smart-622699f4-61ae-4454-9ccf-75ad630c3f1d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363113628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.3363113628 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.3450641988 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 24595137664 ps |
CPU time | 80.63 seconds |
Started | Jul 31 06:58:17 PM PDT 24 |
Finished | Jul 31 06:59:38 PM PDT 24 |
Peak memory | 203344 kb |
Host | smart-8ce0b138-5fc0-46f6-bd0c-1e20e2422220 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450641988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.3450641988 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.2965565021 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 2951915912 ps |
CPU time | 90.27 seconds |
Started | Jul 31 06:58:21 PM PDT 24 |
Finished | Jul 31 06:59:52 PM PDT 24 |
Peak memory | 329268 kb |
Host | smart-b62c3b64-742d-4ced-9340-e1acd8195705 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965565021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.2965565021 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1279723766 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 10700685871 ps |
CPU time | 188.02 seconds |
Started | Jul 31 06:58:30 PM PDT 24 |
Finished | Jul 31 07:01:39 PM PDT 24 |
Peak memory | 211508 kb |
Host | smart-b1c78602-c6e4-4d48-be60-dbd2c75b8990 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279723766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.1279723766 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.3190248604 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 65770768559 ps |
CPU time | 353.13 seconds |
Started | Jul 31 06:58:32 PM PDT 24 |
Finished | Jul 31 07:04:25 PM PDT 24 |
Peak memory | 211568 kb |
Host | smart-138c2da0-1044-4ce4-9d71-b379388e2046 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190248604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.3190248604 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.1446126296 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 21653282369 ps |
CPU time | 1741.65 seconds |
Started | Jul 31 06:58:09 PM PDT 24 |
Finished | Jul 31 07:27:11 PM PDT 24 |
Peak memory | 381264 kb |
Host | smart-13914a1d-cbbf-47b0-b4e7-a676ebad6378 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446126296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.1446126296 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.3054255372 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 1644037837 ps |
CPU time | 14.14 seconds |
Started | Jul 31 06:58:08 PM PDT 24 |
Finished | Jul 31 06:58:22 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-7153b731-76d1-4787-b235-9a1925391c18 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054255372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.3054255372 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2145835162 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 23608736139 ps |
CPU time | 296.39 seconds |
Started | Jul 31 06:58:09 PM PDT 24 |
Finished | Jul 31 07:03:05 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-5df7882b-85fb-4a85-9cbe-cf2142a94534 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145835162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.2145835162 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.819798868 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 706662691 ps |
CPU time | 3.48 seconds |
Started | Jul 31 06:58:22 PM PDT 24 |
Finished | Jul 31 06:58:26 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-ade832c6-d51d-4a17-bfe2-b3aa37ec033d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819798868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.819798868 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.2255839398 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 11144890287 ps |
CPU time | 172.93 seconds |
Started | Jul 31 06:58:22 PM PDT 24 |
Finished | Jul 31 07:01:15 PM PDT 24 |
Peak memory | 339244 kb |
Host | smart-a4897874-9fc4-4d7f-b741-409bd2e4665a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255839398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2255839398 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.2110071733 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 1591454228 ps |
CPU time | 21.66 seconds |
Started | Jul 31 06:58:03 PM PDT 24 |
Finished | Jul 31 06:58:24 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-206f60bd-9304-4ce7-8a54-b77fd79b73e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110071733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2110071733 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.180579397 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 139397966640 ps |
CPU time | 6923.09 seconds |
Started | Jul 31 06:58:27 PM PDT 24 |
Finished | Jul 31 08:53:51 PM PDT 24 |
Peak memory | 386400 kb |
Host | smart-1d885b8f-d3a0-4b04-afb0-36064ee28e3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180579397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_stress_all.180579397 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3311422364 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 2499913762 ps |
CPU time | 20.85 seconds |
Started | Jul 31 06:58:27 PM PDT 24 |
Finished | Jul 31 06:58:48 PM PDT 24 |
Peak memory | 211516 kb |
Host | smart-11c36c39-168b-4af3-b267-45974d767f00 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3311422364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.3311422364 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3364599850 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 3816503860 ps |
CPU time | 265.51 seconds |
Started | Jul 31 06:58:11 PM PDT 24 |
Finished | Jul 31 07:02:37 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-f6c96bc5-8f87-414b-9792-75ba6efb3cfe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364599850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.3364599850 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.828432915 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 673230820 ps |
CPU time | 6.07 seconds |
Started | Jul 31 06:58:19 PM PDT 24 |
Finished | Jul 31 06:58:26 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-22d7eead-8b41-4600-8214-d1f35cf70782 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828432915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.828432915 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3722621476 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 60106676642 ps |
CPU time | 1267.09 seconds |
Started | Jul 31 06:58:28 PM PDT 24 |
Finished | Jul 31 07:19:35 PM PDT 24 |
Peak memory | 381120 kb |
Host | smart-5eec9806-842b-4943-98f1-acb3f420eb6c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722621476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.3722621476 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.42366114 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 36682063 ps |
CPU time | 0.65 seconds |
Started | Jul 31 06:58:34 PM PDT 24 |
Finished | Jul 31 06:58:35 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-2818a736-56c4-4af2-9923-8bf2b12f6199 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42366114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_alert_test.42366114 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.2224927902 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 46168178997 ps |
CPU time | 1633.92 seconds |
Started | Jul 31 06:58:28 PM PDT 24 |
Finished | Jul 31 07:25:42 PM PDT 24 |
Peak memory | 203964 kb |
Host | smart-3e38099d-16f8-4336-83e9-12a174df2424 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224927902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .2224927902 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.3796168213 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 72282854244 ps |
CPU time | 1550.78 seconds |
Started | Jul 31 06:58:28 PM PDT 24 |
Finished | Jul 31 07:24:20 PM PDT 24 |
Peak memory | 373992 kb |
Host | smart-ce1672d1-576c-4293-9e57-97eeb1b442cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796168213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.3796168213 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.4060386239 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 10700765499 ps |
CPU time | 55.24 seconds |
Started | Jul 31 06:58:29 PM PDT 24 |
Finished | Jul 31 06:59:24 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-f59880e0-3e2e-41e0-996e-65b2d9652195 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060386239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.4060386239 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.1439598565 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 736503373 ps |
CPU time | 12.95 seconds |
Started | Jul 31 06:58:31 PM PDT 24 |
Finished | Jul 31 06:58:44 PM PDT 24 |
Peak memory | 240472 kb |
Host | smart-f5e8aa14-ec26-4b5c-b89e-ec9db8e20d3a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439598565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.1439598565 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2800590110 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 10235957125 ps |
CPU time | 183.45 seconds |
Started | Jul 31 06:58:35 PM PDT 24 |
Finished | Jul 31 07:01:38 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-aeebad0b-1947-4161-a171-fa890732a39a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800590110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.2800590110 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.1860241220 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 28818885107 ps |
CPU time | 161.82 seconds |
Started | Jul 31 06:58:29 PM PDT 24 |
Finished | Jul 31 07:01:11 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-34d63606-aa38-4224-88ff-312658fb26a3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860241220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.1860241220 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.385333464 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 9628119104 ps |
CPU time | 93.83 seconds |
Started | Jul 31 06:58:29 PM PDT 24 |
Finished | Jul 31 07:00:02 PM PDT 24 |
Peak memory | 295948 kb |
Host | smart-d3cae830-6baa-4abe-b4d7-0570eaeef7f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385333464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multip le_keys.385333464 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.4207554478 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 4350625536 ps |
CPU time | 8.22 seconds |
Started | Jul 31 06:58:28 PM PDT 24 |
Finished | Jul 31 06:58:36 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-9dee990d-563e-457f-a72f-7b0eeba67fb6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207554478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.4207554478 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3819782058 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 12882585377 ps |
CPU time | 166.02 seconds |
Started | Jul 31 06:58:27 PM PDT 24 |
Finished | Jul 31 07:01:14 PM PDT 24 |
Peak memory | 203304 kb |
Host | smart-d90263b7-bd66-4161-ac29-ab1c5b9e0e9a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819782058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.3819782058 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.3693353675 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 1401499020 ps |
CPU time | 3.58 seconds |
Started | Jul 31 06:58:27 PM PDT 24 |
Finished | Jul 31 06:58:31 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-7839706e-97bb-4547-b764-3f4faa8cd5eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693353675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3693353675 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.1422863497 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 11177752413 ps |
CPU time | 1032.87 seconds |
Started | Jul 31 06:58:28 PM PDT 24 |
Finished | Jul 31 07:15:41 PM PDT 24 |
Peak memory | 375996 kb |
Host | smart-34810215-1b67-4f46-b3e0-e9ca2591d0f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422863497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1422863497 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.3058275014 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 746883791 ps |
CPU time | 53.82 seconds |
Started | Jul 31 06:58:28 PM PDT 24 |
Finished | Jul 31 06:59:22 PM PDT 24 |
Peak memory | 306460 kb |
Host | smart-4df8777b-0141-44e1-99bd-e6167017bb07 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058275014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3058275014 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3197063361 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 2355412151 ps |
CPU time | 9.94 seconds |
Started | Jul 31 06:58:37 PM PDT 24 |
Finished | Jul 31 06:58:47 PM PDT 24 |
Peak memory | 211488 kb |
Host | smart-1af5a63c-9a97-4f49-8c29-f54bc8dc0435 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3197063361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3197063361 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3516991665 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 23701267928 ps |
CPU time | 400.66 seconds |
Started | Jul 31 06:58:27 PM PDT 24 |
Finished | Jul 31 07:05:08 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-8fe235d2-ba83-445c-a4c7-c75807e24a74 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516991665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.3516991665 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3559416440 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 810648712 ps |
CPU time | 134.04 seconds |
Started | Jul 31 06:58:29 PM PDT 24 |
Finished | Jul 31 07:00:44 PM PDT 24 |
Peak memory | 370792 kb |
Host | smart-b9446c22-732d-42cd-9f43-6e082a1a129c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559416440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.3559416440 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2722015954 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 12321839651 ps |
CPU time | 1102.18 seconds |
Started | Jul 31 06:53:39 PM PDT 24 |
Finished | Jul 31 07:12:01 PM PDT 24 |
Peak memory | 379116 kb |
Host | smart-2f12d640-8bea-476a-b8d2-7ca37609903a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722015954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.2722015954 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.3517848108 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 37035794 ps |
CPU time | 0.65 seconds |
Started | Jul 31 06:53:43 PM PDT 24 |
Finished | Jul 31 06:53:44 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-6dd04d4b-a94e-4e92-ab14-092e64c5af47 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517848108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3517848108 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.2792017504 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 60992996578 ps |
CPU time | 2275.91 seconds |
Started | Jul 31 06:53:27 PM PDT 24 |
Finished | Jul 31 07:31:23 PM PDT 24 |
Peak memory | 204056 kb |
Host | smart-7633e5b9-f625-4e94-a729-f2517fcf421c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792017504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 2792017504 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.796805154 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 30954528749 ps |
CPU time | 875.64 seconds |
Started | Jul 31 06:53:38 PM PDT 24 |
Finished | Jul 31 07:08:14 PM PDT 24 |
Peak memory | 380156 kb |
Host | smart-86bfba5c-8eca-4dca-a21e-28cfb5d260b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796805154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable .796805154 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.494472934 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 41320064511 ps |
CPU time | 36.65 seconds |
Started | Jul 31 06:53:37 PM PDT 24 |
Finished | Jul 31 06:54:14 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-ad62546e-13a3-4d94-87ed-a251ab1e4713 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494472934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esca lation.494472934 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.3364816719 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 2922175228 ps |
CPU time | 115.19 seconds |
Started | Jul 31 06:53:32 PM PDT 24 |
Finished | Jul 31 06:55:28 PM PDT 24 |
Peak memory | 365320 kb |
Host | smart-c5ffcc61-f11f-4548-bdaa-a248daa9e92c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364816719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.3364816719 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3266996509 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 4024117937 ps |
CPU time | 63.58 seconds |
Started | Jul 31 06:53:43 PM PDT 24 |
Finished | Jul 31 06:54:47 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-d45f71e8-6019-46d9-968a-31636a703fae |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266996509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.3266996509 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.239389314 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 2044157547 ps |
CPU time | 122.59 seconds |
Started | Jul 31 06:53:43 PM PDT 24 |
Finished | Jul 31 06:55:45 PM PDT 24 |
Peak memory | 211332 kb |
Host | smart-3d91a2c2-ace6-4809-a4a1-6d2b4995f743 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239389314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ mem_walk.239389314 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.1489400896 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 17019756795 ps |
CPU time | 1224.67 seconds |
Started | Jul 31 06:53:26 PM PDT 24 |
Finished | Jul 31 07:13:51 PM PDT 24 |
Peak memory | 380212 kb |
Host | smart-d77b9689-2aed-4151-b599-c5829eab4d20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489400896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.1489400896 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.1179472211 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 2137211028 ps |
CPU time | 138.82 seconds |
Started | Jul 31 06:53:31 PM PDT 24 |
Finished | Jul 31 06:55:50 PM PDT 24 |
Peak memory | 369812 kb |
Host | smart-4da3fa02-aa4e-4364-8e1f-91c87ebd7ead |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179472211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.1179472211 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3899961696 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 10478727965 ps |
CPU time | 222.94 seconds |
Started | Jul 31 06:53:31 PM PDT 24 |
Finished | Jul 31 06:57:14 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-5a51454b-1422-4626-94c6-ebad30049fd3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899961696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.3899961696 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.1055114242 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 2258484109 ps |
CPU time | 3.39 seconds |
Started | Jul 31 06:53:43 PM PDT 24 |
Finished | Jul 31 06:53:46 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-ceda8e1d-16a4-496f-8d3a-448d102b2ce8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055114242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1055114242 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.445151649 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 46844194707 ps |
CPU time | 822.63 seconds |
Started | Jul 31 06:53:39 PM PDT 24 |
Finished | Jul 31 07:07:22 PM PDT 24 |
Peak memory | 379156 kb |
Host | smart-47db31cf-40b0-4121-9e30-d78f2001f834 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445151649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.445151649 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.566834526 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 3116045747 ps |
CPU time | 3.59 seconds |
Started | Jul 31 06:53:43 PM PDT 24 |
Finished | Jul 31 06:53:47 PM PDT 24 |
Peak memory | 223448 kb |
Host | smart-8002ee2f-86f0-41eb-864b-4f0b467e79f3 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566834526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_sec_cm.566834526 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.3048348621 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 2020646306 ps |
CPU time | 10.21 seconds |
Started | Jul 31 06:53:27 PM PDT 24 |
Finished | Jul 31 06:53:38 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-d55cd599-5d13-4457-927b-93372530a732 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048348621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3048348621 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.468253997 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 115155207591 ps |
CPU time | 4310.61 seconds |
Started | Jul 31 06:53:43 PM PDT 24 |
Finished | Jul 31 08:05:34 PM PDT 24 |
Peak memory | 382072 kb |
Host | smart-ac408eec-decc-4604-8160-64639155e45f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468253997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_stress_all.468253997 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1711776989 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 595014081 ps |
CPU time | 17.78 seconds |
Started | Jul 31 06:53:43 PM PDT 24 |
Finished | Jul 31 06:54:01 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-68b5ea10-41ee-4a00-880d-fbc44bf4389b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1711776989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1711776989 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1033160805 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 12888160629 ps |
CPU time | 248.55 seconds |
Started | Jul 31 06:53:31 PM PDT 24 |
Finished | Jul 31 06:57:41 PM PDT 24 |
Peak memory | 203304 kb |
Host | smart-0339a330-c1da-4456-9f0e-49d4c6cb43c2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033160805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.1033160805 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2116790260 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 13008534945 ps |
CPU time | 101.07 seconds |
Started | Jul 31 06:53:38 PM PDT 24 |
Finished | Jul 31 06:55:19 PM PDT 24 |
Peak memory | 371168 kb |
Host | smart-73124dee-3dc7-47c3-8bba-21e66434a4ad |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116790260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.2116790260 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3874163461 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 55644536591 ps |
CPU time | 1191.93 seconds |
Started | Jul 31 06:58:42 PM PDT 24 |
Finished | Jul 31 07:18:34 PM PDT 24 |
Peak memory | 378124 kb |
Host | smart-9289286b-7d7b-4b26-b10f-f6babc48ed8f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874163461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.3874163461 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.1136065965 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 23367152 ps |
CPU time | 0.66 seconds |
Started | Jul 31 06:58:48 PM PDT 24 |
Finished | Jul 31 06:58:49 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-a1c0f84a-9318-4e3e-8604-a25530212ed6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136065965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1136065965 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.1248619926 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 718509099723 ps |
CPU time | 3254.89 seconds |
Started | Jul 31 06:58:35 PM PDT 24 |
Finished | Jul 31 07:52:51 PM PDT 24 |
Peak memory | 204012 kb |
Host | smart-04f9a97e-195e-4ff8-b47d-199f75b685d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248619926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .1248619926 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.1248395462 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 5108522762 ps |
CPU time | 338.44 seconds |
Started | Jul 31 06:58:41 PM PDT 24 |
Finished | Jul 31 07:04:20 PM PDT 24 |
Peak memory | 365824 kb |
Host | smart-7135ee0f-248c-4827-bdf5-c5d0cd8eb40e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248395462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.1248395462 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.121943693 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 755532845 ps |
CPU time | 6.57 seconds |
Started | Jul 31 06:58:40 PM PDT 24 |
Finished | Jul 31 06:58:47 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-5c1dbd2b-ae39-4bfa-b40d-06ee0efbfcf3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121943693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc alation.121943693 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.706428097 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 814561713 ps |
CPU time | 117.36 seconds |
Started | Jul 31 06:58:42 PM PDT 24 |
Finished | Jul 31 07:00:39 PM PDT 24 |
Peak memory | 364804 kb |
Host | smart-77a5b50e-1da3-42ec-8bfe-0410cf8afcf6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706428097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.sram_ctrl_max_throughput.706428097 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.572126868 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 3902102314 ps |
CPU time | 126.2 seconds |
Started | Jul 31 06:58:49 PM PDT 24 |
Finished | Jul 31 07:00:55 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-63a81d9f-3ad1-489b-a41c-ffeb5b70c5e9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572126868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20 .sram_ctrl_mem_partial_access.572126868 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.3350193596 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 7217502103 ps |
CPU time | 163.22 seconds |
Started | Jul 31 06:58:53 PM PDT 24 |
Finished | Jul 31 07:01:37 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-545f3037-4400-4abf-b5ec-9d4e19486278 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350193596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.3350193596 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.2077299756 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 98535771489 ps |
CPU time | 1076.64 seconds |
Started | Jul 31 06:58:35 PM PDT 24 |
Finished | Jul 31 07:16:32 PM PDT 24 |
Peak memory | 380364 kb |
Host | smart-be007fbe-e796-47ed-9402-d61618c03414 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077299756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.2077299756 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.241272437 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 811943465 ps |
CPU time | 5.5 seconds |
Started | Jul 31 06:58:34 PM PDT 24 |
Finished | Jul 31 06:58:39 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-68a1a959-7822-4649-b677-f8f42bff2207 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241272437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.s ram_ctrl_partial_access.241272437 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1083389249 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 18495315029 ps |
CPU time | 467.26 seconds |
Started | Jul 31 06:58:35 PM PDT 24 |
Finished | Jul 31 07:06:23 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-35856cb8-1039-4387-ba5d-2dcd7d3817a4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083389249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.1083389249 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.223414065 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 368914238 ps |
CPU time | 3.12 seconds |
Started | Jul 31 06:58:41 PM PDT 24 |
Finished | Jul 31 06:58:44 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-fb7bbf83-9ee4-40a3-92e9-a5c319ac554d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223414065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.223414065 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.1786306486 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 28823191409 ps |
CPU time | 1215.59 seconds |
Started | Jul 31 06:58:43 PM PDT 24 |
Finished | Jul 31 07:18:59 PM PDT 24 |
Peak memory | 378144 kb |
Host | smart-5545da63-43ec-44ea-9944-18ffdd162a62 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786306486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.1786306486 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.715672613 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 2161526652 ps |
CPU time | 13.94 seconds |
Started | Jul 31 06:58:35 PM PDT 24 |
Finished | Jul 31 06:58:49 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-994ad439-3fb4-4f21-858b-b08f489419a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715672613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.715672613 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.1416686305 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 63424169382 ps |
CPU time | 1820.52 seconds |
Started | Jul 31 06:58:46 PM PDT 24 |
Finished | Jul 31 07:29:07 PM PDT 24 |
Peak memory | 380552 kb |
Host | smart-1eb391f6-d6c1-4b5b-aedb-4306e68cb03e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416686305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.1416686305 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2063527215 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 97234329596 ps |
CPU time | 429.91 seconds |
Started | Jul 31 06:58:36 PM PDT 24 |
Finished | Jul 31 07:05:46 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-d0c9652e-98bf-4b33-b3e0-1990d3acb1fa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063527215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.2063527215 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3846881075 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 9067118126 ps |
CPU time | 33.53 seconds |
Started | Jul 31 06:58:43 PM PDT 24 |
Finished | Jul 31 06:59:16 PM PDT 24 |
Peak memory | 289144 kb |
Host | smart-3e34e368-7fb8-43da-a1ac-c5a035b33fef |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846881075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3846881075 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.135706632 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 3118071810 ps |
CPU time | 172.17 seconds |
Started | Jul 31 06:58:48 PM PDT 24 |
Finished | Jul 31 07:01:41 PM PDT 24 |
Peak memory | 372768 kb |
Host | smart-550a2862-1372-406e-a48f-18fcae668d83 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135706632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 21.sram_ctrl_access_during_key_req.135706632 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.2682499453 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 30469932 ps |
CPU time | 0.63 seconds |
Started | Jul 31 06:58:54 PM PDT 24 |
Finished | Jul 31 06:58:54 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-d4d0a523-e442-4942-95ae-cb031cfa6d3b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682499453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2682499453 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.2916087563 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 41457170643 ps |
CPU time | 455.39 seconds |
Started | Jul 31 06:58:54 PM PDT 24 |
Finished | Jul 31 07:06:30 PM PDT 24 |
Peak memory | 378044 kb |
Host | smart-5ea2d671-a915-4823-9c5d-19bde818363d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916087563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.2916087563 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.648156974 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 37094864429 ps |
CPU time | 63.78 seconds |
Started | Jul 31 06:58:49 PM PDT 24 |
Finished | Jul 31 06:59:53 PM PDT 24 |
Peak memory | 203364 kb |
Host | smart-0d5d0e23-02a9-4630-ab0a-7d9c3ddd6b97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648156974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esc alation.648156974 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.3138737507 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 818493510 ps |
CPU time | 107.36 seconds |
Started | Jul 31 06:58:48 PM PDT 24 |
Finished | Jul 31 07:00:36 PM PDT 24 |
Peak memory | 370868 kb |
Host | smart-e9aa5c7b-101c-4928-9c2c-ea17d993e0a1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138737507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.3138737507 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1762755233 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 27804965409 ps |
CPU time | 174.77 seconds |
Started | Jul 31 06:58:58 PM PDT 24 |
Finished | Jul 31 07:01:53 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-7334fd3f-84d6-4fe6-acaf-5bb21ae6c151 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762755233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.1762755233 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.1327296062 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 19776394325 ps |
CPU time | 165.76 seconds |
Started | Jul 31 06:58:53 PM PDT 24 |
Finished | Jul 31 07:01:39 PM PDT 24 |
Peak memory | 211568 kb |
Host | smart-fe8ea2ab-70e7-40cc-b111-7ec2099d4172 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327296062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.1327296062 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.2666194617 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 67563742538 ps |
CPU time | 778.94 seconds |
Started | Jul 31 06:58:50 PM PDT 24 |
Finished | Jul 31 07:11:49 PM PDT 24 |
Peak memory | 356580 kb |
Host | smart-ef205dbe-6ea0-4f88-9210-1becf49d11c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666194617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.2666194617 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.1969557175 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 4294168000 ps |
CPU time | 154.51 seconds |
Started | Jul 31 06:58:47 PM PDT 24 |
Finished | Jul 31 07:01:21 PM PDT 24 |
Peak memory | 369804 kb |
Host | smart-a63c79a1-0529-4538-ae87-0d209f184ec1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969557175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.1969557175 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2154360043 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 10663456466 ps |
CPU time | 251.65 seconds |
Started | Jul 31 06:58:49 PM PDT 24 |
Finished | Jul 31 07:03:01 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-b1e34c3a-2640-4982-9df1-cbde6c34d0bc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154360043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.2154360043 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.4175761776 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 1381530907 ps |
CPU time | 3.3 seconds |
Started | Jul 31 06:58:56 PM PDT 24 |
Finished | Jul 31 06:58:59 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-f7a1084e-aa38-4385-8c64-f3d3073beb7f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175761776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.4175761776 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.468308339 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 12157054478 ps |
CPU time | 761.37 seconds |
Started | Jul 31 06:58:56 PM PDT 24 |
Finished | Jul 31 07:11:37 PM PDT 24 |
Peak memory | 369888 kb |
Host | smart-c498bda0-6281-43d6-a1bb-bbc284fb9f84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468308339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.468308339 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.3396624681 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 733089747 ps |
CPU time | 7.17 seconds |
Started | Jul 31 06:58:50 PM PDT 24 |
Finished | Jul 31 06:58:57 PM PDT 24 |
Peak memory | 206208 kb |
Host | smart-035fc477-8061-4716-9ea5-8007a45b156e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396624681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3396624681 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.1765029861 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 190287435477 ps |
CPU time | 7212.53 seconds |
Started | Jul 31 06:58:52 PM PDT 24 |
Finished | Jul 31 08:59:05 PM PDT 24 |
Peak memory | 380852 kb |
Host | smart-c61d9c96-0ebf-4bed-b9b6-bde7703a6891 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765029861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.1765029861 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.305086478 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 588753547 ps |
CPU time | 10.06 seconds |
Started | Jul 31 06:58:55 PM PDT 24 |
Finished | Jul 31 06:59:05 PM PDT 24 |
Peak memory | 211460 kb |
Host | smart-663c9a9f-2175-4387-a3f4-ec6098432353 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=305086478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.305086478 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1831724672 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 3958782807 ps |
CPU time | 209.48 seconds |
Started | Jul 31 06:58:49 PM PDT 24 |
Finished | Jul 31 07:02:18 PM PDT 24 |
Peak memory | 203320 kb |
Host | smart-fbe3b305-4d89-4379-a976-d8fa1d5fc9bf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831724672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.1831724672 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2100366141 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 14589214122 ps |
CPU time | 43.82 seconds |
Started | Jul 31 06:58:48 PM PDT 24 |
Finished | Jul 31 06:59:32 PM PDT 24 |
Peak memory | 292236 kb |
Host | smart-4e92ad7e-bd3e-437f-b500-6ebfc18ad045 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100366141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2100366141 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.4020941937 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 14315086397 ps |
CPU time | 1303.19 seconds |
Started | Jul 31 06:59:00 PM PDT 24 |
Finished | Jul 31 07:20:43 PM PDT 24 |
Peak memory | 380220 kb |
Host | smart-278b26db-e08c-41ef-8bab-bda65fe0d1eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020941937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.4020941937 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.1078070207 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 30566480 ps |
CPU time | 0.65 seconds |
Started | Jul 31 06:59:07 PM PDT 24 |
Finished | Jul 31 06:59:08 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-19f56ed0-317f-418f-8011-1aaaad98ec1a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078070207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.1078070207 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.1652046909 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 41266615746 ps |
CPU time | 1692.86 seconds |
Started | Jul 31 06:58:53 PM PDT 24 |
Finished | Jul 31 07:27:07 PM PDT 24 |
Peak memory | 203984 kb |
Host | smart-0deab7e5-2363-4f1f-9e30-f47567c60d91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652046909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .1652046909 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.324415120 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 45470675244 ps |
CPU time | 614.34 seconds |
Started | Jul 31 06:58:58 PM PDT 24 |
Finished | Jul 31 07:09:13 PM PDT 24 |
Peak memory | 377040 kb |
Host | smart-9ce2f070-46c3-415e-b3d9-f9e4033ee996 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324415120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl e.324415120 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.1364432501 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 63193538197 ps |
CPU time | 107.34 seconds |
Started | Jul 31 06:59:00 PM PDT 24 |
Finished | Jul 31 07:00:47 PM PDT 24 |
Peak memory | 211528 kb |
Host | smart-4a2e9264-9d81-4d9b-a8fa-f532252d0aaa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364432501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.1364432501 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.2019400572 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 4850274061 ps |
CPU time | 53.42 seconds |
Started | Jul 31 06:59:05 PM PDT 24 |
Finished | Jul 31 06:59:58 PM PDT 24 |
Peak memory | 304488 kb |
Host | smart-ab0002bd-2aad-4564-ac93-1f1d50054878 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019400572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.2019400572 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2521204016 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 986134877 ps |
CPU time | 63.96 seconds |
Started | Jul 31 06:59:07 PM PDT 24 |
Finished | Jul 31 07:00:11 PM PDT 24 |
Peak memory | 211332 kb |
Host | smart-e7c67a21-6269-4236-9dc1-5f1ec889e39c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521204016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.2521204016 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.3447628772 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 14399546133 ps |
CPU time | 151.27 seconds |
Started | Jul 31 06:59:02 PM PDT 24 |
Finished | Jul 31 07:01:33 PM PDT 24 |
Peak memory | 203668 kb |
Host | smart-8314f0ea-77c1-45e8-b46e-126fcd3bd188 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447628772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.3447628772 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.1539103261 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 8521465824 ps |
CPU time | 266.19 seconds |
Started | Jul 31 06:58:55 PM PDT 24 |
Finished | Jul 31 07:03:21 PM PDT 24 |
Peak memory | 345920 kb |
Host | smart-0e921f75-63ce-4c04-885b-7b5c1f5db8b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539103261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.1539103261 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.539054972 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 962113253 ps |
CPU time | 23.73 seconds |
Started | Jul 31 06:58:54 PM PDT 24 |
Finished | Jul 31 06:59:18 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-cbf1f6b2-beeb-4f34-aca8-c1c1bbfadf66 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539054972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.s ram_ctrl_partial_access.539054972 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3147210901 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 30851745356 ps |
CPU time | 333.53 seconds |
Started | Jul 31 06:59:00 PM PDT 24 |
Finished | Jul 31 07:04:34 PM PDT 24 |
Peak memory | 203328 kb |
Host | smart-d4edad6c-4518-4d1c-924f-3e0a1edbaccb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147210901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.3147210901 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.3048887625 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 358506971 ps |
CPU time | 3.29 seconds |
Started | Jul 31 06:59:01 PM PDT 24 |
Finished | Jul 31 06:59:05 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-ee9143e0-a640-4113-866c-3561fd48d9ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048887625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3048887625 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.4220562548 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 3138050645 ps |
CPU time | 917.04 seconds |
Started | Jul 31 06:59:01 PM PDT 24 |
Finished | Jul 31 07:14:18 PM PDT 24 |
Peak memory | 381220 kb |
Host | smart-048c0bb4-4834-4148-83a1-50b806796b0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220562548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.4220562548 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.2538410210 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 2550234320 ps |
CPU time | 69.55 seconds |
Started | Jul 31 06:58:53 PM PDT 24 |
Finished | Jul 31 07:00:03 PM PDT 24 |
Peak memory | 343284 kb |
Host | smart-daee304c-40e1-4f13-a076-ccd9516fdb18 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538410210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2538410210 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.2239417759 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 61169162979 ps |
CPU time | 4918.6 seconds |
Started | Jul 31 06:59:07 PM PDT 24 |
Finished | Jul 31 08:21:07 PM PDT 24 |
Peak memory | 388360 kb |
Host | smart-eb1ecea1-d6fa-4f56-91a2-b59dcdc5222e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239417759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.2239417759 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1378637824 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 4848366763 ps |
CPU time | 82.52 seconds |
Started | Jul 31 06:59:11 PM PDT 24 |
Finished | Jul 31 07:00:34 PM PDT 24 |
Peak memory | 329064 kb |
Host | smart-1f502c20-a449-448e-98a0-409dd8da8b07 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1378637824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.1378637824 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.780655102 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 4133099555 ps |
CPU time | 241.02 seconds |
Started | Jul 31 06:58:54 PM PDT 24 |
Finished | Jul 31 07:02:55 PM PDT 24 |
Peak memory | 203276 kb |
Host | smart-bf613875-3f45-4d4c-be6e-80106c2c748e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780655102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_stress_pipeline.780655102 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3694792510 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 9969105372 ps |
CPU time | 17.02 seconds |
Started | Jul 31 06:59:14 PM PDT 24 |
Finished | Jul 31 06:59:31 PM PDT 24 |
Peak memory | 252348 kb |
Host | smart-e9617ef7-3e88-4ad0-aed8-4492ec7f7d68 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694792510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3694792510 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.4177591481 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 6363924631 ps |
CPU time | 454.4 seconds |
Started | Jul 31 06:59:18 PM PDT 24 |
Finished | Jul 31 07:06:52 PM PDT 24 |
Peak memory | 374232 kb |
Host | smart-eb3f0b4c-3659-4a6e-9b42-c1496885e223 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177591481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.4177591481 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.3697228039 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 113102015 ps |
CPU time | 0.68 seconds |
Started | Jul 31 06:59:18 PM PDT 24 |
Finished | Jul 31 06:59:19 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-6b9ef966-3326-49ba-88cb-c3adabaf6559 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697228039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3697228039 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.2390490930 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 166566229801 ps |
CPU time | 735.49 seconds |
Started | Jul 31 06:59:11 PM PDT 24 |
Finished | Jul 31 07:11:27 PM PDT 24 |
Peak memory | 203436 kb |
Host | smart-05894005-95dd-4291-ab38-7d806ddea5c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390490930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .2390490930 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.251513939 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 31799598287 ps |
CPU time | 776.27 seconds |
Started | Jul 31 06:59:16 PM PDT 24 |
Finished | Jul 31 07:12:13 PM PDT 24 |
Peak memory | 369840 kb |
Host | smart-8971c6d5-a2d3-4d09-aedd-4950fc7e3bd4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251513939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executabl e.251513939 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.1191585464 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 196676740104 ps |
CPU time | 73.3 seconds |
Started | Jul 31 06:59:11 PM PDT 24 |
Finished | Jul 31 07:00:25 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-b01daf79-ef3b-44b9-a865-5a4260f2d8c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191585464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.1191585464 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.2861534902 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 3169985592 ps |
CPU time | 101.6 seconds |
Started | Jul 31 06:59:14 PM PDT 24 |
Finished | Jul 31 07:00:56 PM PDT 24 |
Peak memory | 363748 kb |
Host | smart-eff73506-a0bf-48ea-9de9-930ebae17a09 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861534902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.2861534902 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1293098186 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 9771611240 ps |
CPU time | 142.83 seconds |
Started | Jul 31 06:59:19 PM PDT 24 |
Finished | Jul 31 07:01:42 PM PDT 24 |
Peak memory | 211500 kb |
Host | smart-0baf29f8-14b6-406e-99b6-aa132de0f4bd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293098186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.1293098186 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.1692620025 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 4198788623 ps |
CPU time | 253.76 seconds |
Started | Jul 31 06:59:21 PM PDT 24 |
Finished | Jul 31 07:03:35 PM PDT 24 |
Peak memory | 212384 kb |
Host | smart-0c8cebb3-c351-4977-af50-d7713bbe5b9c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692620025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.1692620025 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.2131473565 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 92907782256 ps |
CPU time | 322.25 seconds |
Started | Jul 31 06:59:08 PM PDT 24 |
Finished | Jul 31 07:04:31 PM PDT 24 |
Peak memory | 369796 kb |
Host | smart-98b1b5d6-8e6d-42c9-8e51-1aa5868fef7f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131473565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.2131473565 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.2750135456 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 3605720343 ps |
CPU time | 20.58 seconds |
Started | Jul 31 06:59:11 PM PDT 24 |
Finished | Jul 31 06:59:32 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-d46642ff-b3f9-4477-a140-cb2a6a99a1d1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750135456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.2750135456 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2592739448 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 93332904184 ps |
CPU time | 561.8 seconds |
Started | Jul 31 06:59:12 PM PDT 24 |
Finished | Jul 31 07:08:34 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-22452a31-58de-4080-9048-75bd92611862 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592739448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.2592739448 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.1043278102 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 348223446 ps |
CPU time | 3.38 seconds |
Started | Jul 31 06:59:18 PM PDT 24 |
Finished | Jul 31 06:59:21 PM PDT 24 |
Peak memory | 203056 kb |
Host | smart-2bb8ad4f-2420-4483-8f09-5ebd78c5f44f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043278102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1043278102 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.1073721546 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 2430125029 ps |
CPU time | 183.3 seconds |
Started | Jul 31 06:59:18 PM PDT 24 |
Finished | Jul 31 07:02:21 PM PDT 24 |
Peak memory | 351828 kb |
Host | smart-75ad07c3-b417-41be-9045-5fa1e5d9796f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073721546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1073721546 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.568469386 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 4387011750 ps |
CPU time | 14.4 seconds |
Started | Jul 31 06:59:06 PM PDT 24 |
Finished | Jul 31 06:59:21 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-02070fee-1bf3-4a59-8851-1b265c9d9250 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568469386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.568469386 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.1694910742 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 49360313327 ps |
CPU time | 1127.73 seconds |
Started | Jul 31 06:59:17 PM PDT 24 |
Finished | Jul 31 07:18:05 PM PDT 24 |
Peak memory | 370916 kb |
Host | smart-5bce50c2-f3a8-4bef-af35-461ae7e0c8c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694910742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.1694910742 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1346348178 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 9530857530 ps |
CPU time | 45.94 seconds |
Started | Jul 31 06:59:17 PM PDT 24 |
Finished | Jul 31 07:00:03 PM PDT 24 |
Peak memory | 277940 kb |
Host | smart-7b6cbeb8-0b44-477e-a982-f75fabbe4ce0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1346348178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1346348178 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3613305085 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 18070191104 ps |
CPU time | 307.46 seconds |
Started | Jul 31 06:59:06 PM PDT 24 |
Finished | Jul 31 07:04:14 PM PDT 24 |
Peak memory | 203292 kb |
Host | smart-1306bb1b-294c-4e30-a46c-076d33ab50aa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613305085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3613305085 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.4006781389 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 2931702838 ps |
CPU time | 18.41 seconds |
Started | Jul 31 06:59:11 PM PDT 24 |
Finished | Jul 31 06:59:30 PM PDT 24 |
Peak memory | 253340 kb |
Host | smart-dc2dda4a-fc40-4974-b0b9-dca62b2b6abe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006781389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.4006781389 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.3047471200 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 24561017651 ps |
CPU time | 1342.57 seconds |
Started | Jul 31 06:59:26 PM PDT 24 |
Finished | Jul 31 07:21:49 PM PDT 24 |
Peak memory | 376104 kb |
Host | smart-1c67add9-3d55-4289-a193-c5f849c6d49e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047471200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.3047471200 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.1994812744 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 34996771 ps |
CPU time | 0.62 seconds |
Started | Jul 31 06:59:30 PM PDT 24 |
Finished | Jul 31 06:59:31 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-b01c6294-f000-404f-8eb9-f99d52bc565d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994812744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.1994812744 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.3286078607 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 249868287343 ps |
CPU time | 1423.94 seconds |
Started | Jul 31 06:59:25 PM PDT 24 |
Finished | Jul 31 07:23:10 PM PDT 24 |
Peak memory | 203832 kb |
Host | smart-185fbb8f-3b87-4c30-923c-f5569db977d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286078607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .3286078607 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.1468259294 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 39859557557 ps |
CPU time | 965.61 seconds |
Started | Jul 31 06:59:26 PM PDT 24 |
Finished | Jul 31 07:15:31 PM PDT 24 |
Peak memory | 375076 kb |
Host | smart-063ffd8d-56c0-4223-a966-89cb8a982562 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468259294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.1468259294 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.698102314 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 12905939978 ps |
CPU time | 82 seconds |
Started | Jul 31 06:59:25 PM PDT 24 |
Finished | Jul 31 07:00:47 PM PDT 24 |
Peak memory | 211552 kb |
Host | smart-ba942480-6807-4547-bf42-27d37c6ca9d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698102314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esc alation.698102314 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.828502306 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 3719772589 ps |
CPU time | 7.46 seconds |
Started | Jul 31 06:59:25 PM PDT 24 |
Finished | Jul 31 06:59:33 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-8dbe1b60-d51c-4faa-8505-1024249373fa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828502306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.sram_ctrl_max_throughput.828502306 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2986333327 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 5022290287 ps |
CPU time | 168.34 seconds |
Started | Jul 31 06:59:30 PM PDT 24 |
Finished | Jul 31 07:02:18 PM PDT 24 |
Peak memory | 211472 kb |
Host | smart-0536915a-d1c3-4ea4-97c4-70af52175e54 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986333327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.2986333327 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.2931355217 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 44915058940 ps |
CPU time | 182.01 seconds |
Started | Jul 31 06:59:25 PM PDT 24 |
Finished | Jul 31 07:02:27 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-a068f38a-0951-408b-b094-032080d1ee8e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931355217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2931355217 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.1738767917 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 46580771857 ps |
CPU time | 1245.42 seconds |
Started | Jul 31 06:59:24 PM PDT 24 |
Finished | Jul 31 07:20:09 PM PDT 24 |
Peak memory | 382084 kb |
Host | smart-11dab67f-02c4-4d1f-8ed8-275d260c67b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738767917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.1738767917 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.244965276 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 4173214160 ps |
CPU time | 17.39 seconds |
Started | Jul 31 06:59:26 PM PDT 24 |
Finished | Jul 31 06:59:43 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-642a1cd6-5301-4652-b85b-589e07c8d05d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244965276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s ram_ctrl_partial_access.244965276 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3518108906 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 20847638308 ps |
CPU time | 446.58 seconds |
Started | Jul 31 06:59:28 PM PDT 24 |
Finished | Jul 31 07:06:54 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-8403678b-4f9f-4550-b187-fa3e198e2bf0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518108906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.3518108906 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.323792812 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 363338244 ps |
CPU time | 3.27 seconds |
Started | Jul 31 06:59:24 PM PDT 24 |
Finished | Jul 31 06:59:28 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-6a997491-dbba-411e-a109-3df1e717f681 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323792812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.323792812 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.79383368 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 153442873346 ps |
CPU time | 846.35 seconds |
Started | Jul 31 06:59:26 PM PDT 24 |
Finished | Jul 31 07:13:33 PM PDT 24 |
Peak memory | 373056 kb |
Host | smart-373ef026-1bfb-4406-baed-44720342acd9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79383368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.79383368 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.2785145701 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 395307203 ps |
CPU time | 15.97 seconds |
Started | Jul 31 06:59:25 PM PDT 24 |
Finished | Jul 31 06:59:41 PM PDT 24 |
Peak memory | 258108 kb |
Host | smart-752d69d6-98d6-49da-a0f1-4c59cb738cdf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785145701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2785145701 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.2575420775 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 238841301709 ps |
CPU time | 3553.92 seconds |
Started | Jul 31 06:59:31 PM PDT 24 |
Finished | Jul 31 07:58:45 PM PDT 24 |
Peak memory | 379120 kb |
Host | smart-228e83e3-f375-419d-951d-b6f0760d1d88 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575420775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.2575420775 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2507017011 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 1171151876 ps |
CPU time | 34.18 seconds |
Started | Jul 31 06:59:30 PM PDT 24 |
Finished | Jul 31 07:00:04 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-2e2a7fe8-7935-487b-b701-d6641d22176d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2507017011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2507017011 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.445309888 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 7824043285 ps |
CPU time | 193.85 seconds |
Started | Jul 31 06:59:25 PM PDT 24 |
Finished | Jul 31 07:02:39 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-8dbf606d-de70-4c71-8741-9cbfb3ae85d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445309888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .sram_ctrl_stress_pipeline.445309888 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3522525520 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 3311292819 ps |
CPU time | 56.86 seconds |
Started | Jul 31 06:59:25 PM PDT 24 |
Finished | Jul 31 07:00:22 PM PDT 24 |
Peak memory | 315812 kb |
Host | smart-fe8c6035-9c2c-46c9-9a40-06cdebb707a7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522525520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3522525520 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.4241404023 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 63667634816 ps |
CPU time | 959.45 seconds |
Started | Jul 31 06:59:40 PM PDT 24 |
Finished | Jul 31 07:15:40 PM PDT 24 |
Peak memory | 373100 kb |
Host | smart-9c93b288-fca5-4c1d-ac90-51c9024c7658 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241404023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.4241404023 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.1756086325 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 33868989 ps |
CPU time | 0.65 seconds |
Started | Jul 31 06:59:41 PM PDT 24 |
Finished | Jul 31 06:59:41 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-d58135d3-9750-43ff-93a3-73f33fa6c7ff |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756086325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1756086325 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.3195871166 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 85548272822 ps |
CPU time | 1972.81 seconds |
Started | Jul 31 06:59:36 PM PDT 24 |
Finished | Jul 31 07:32:29 PM PDT 24 |
Peak memory | 204048 kb |
Host | smart-49d368e6-c927-4070-8e05-fc63f06b293a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195871166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .3195871166 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.1735547485 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 44974027550 ps |
CPU time | 1345.4 seconds |
Started | Jul 31 06:59:44 PM PDT 24 |
Finished | Jul 31 07:22:10 PM PDT 24 |
Peak memory | 377032 kb |
Host | smart-961ae2e5-181f-4efb-a342-d2ee140d03af |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735547485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.1735547485 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.747771267 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 43964999525 ps |
CPU time | 64.41 seconds |
Started | Jul 31 06:59:35 PM PDT 24 |
Finished | Jul 31 07:00:39 PM PDT 24 |
Peak memory | 203304 kb |
Host | smart-ae728c1a-9358-4860-8dc3-6a64ec55a37c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747771267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_esc alation.747771267 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.800890755 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 6035145777 ps |
CPU time | 6.28 seconds |
Started | Jul 31 06:59:39 PM PDT 24 |
Finished | Jul 31 06:59:46 PM PDT 24 |
Peak memory | 211352 kb |
Host | smart-ff429f29-e948-418c-954c-e256f7dddd0f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800890755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.sram_ctrl_max_throughput.800890755 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3827123994 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 10631577926 ps |
CPU time | 155.3 seconds |
Started | Jul 31 06:59:40 PM PDT 24 |
Finished | Jul 31 07:02:16 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-7e0e3dcf-6dbd-41e4-9403-f87b960b92d1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827123994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.3827123994 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.1610908459 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 10938102635 ps |
CPU time | 293.17 seconds |
Started | Jul 31 06:59:41 PM PDT 24 |
Finished | Jul 31 07:04:34 PM PDT 24 |
Peak memory | 211512 kb |
Host | smart-80a84c44-1ec7-40eb-9cdf-18593b416075 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610908459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.1610908459 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.1923824430 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 23439292299 ps |
CPU time | 1237.93 seconds |
Started | Jul 31 06:59:37 PM PDT 24 |
Finished | Jul 31 07:20:16 PM PDT 24 |
Peak memory | 379088 kb |
Host | smart-cab72fbd-0b06-498b-a2a0-428dcc7e4e4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923824430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.1923824430 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.4172908832 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 3088144689 ps |
CPU time | 156.57 seconds |
Started | Jul 31 06:59:41 PM PDT 24 |
Finished | Jul 31 07:02:17 PM PDT 24 |
Peak memory | 361752 kb |
Host | smart-feb6e377-494f-4a22-8133-f8dbf1801812 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172908832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.4172908832 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.8089263 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 370762202 ps |
CPU time | 3.29 seconds |
Started | Jul 31 06:59:45 PM PDT 24 |
Finished | Jul 31 06:59:49 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-909df769-5714-4dcb-b346-7885fc46dcf9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8089263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.8089263 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.1805763240 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 13989003226 ps |
CPU time | 308.43 seconds |
Started | Jul 31 06:59:42 PM PDT 24 |
Finished | Jul 31 07:04:50 PM PDT 24 |
Peak memory | 350448 kb |
Host | smart-bf59f6be-3b1e-4779-b8df-cf128e9f951c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805763240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1805763240 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.3451046757 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 965861245 ps |
CPU time | 22.43 seconds |
Started | Jul 31 06:59:35 PM PDT 24 |
Finished | Jul 31 06:59:57 PM PDT 24 |
Peak memory | 262944 kb |
Host | smart-611b5c38-e7bb-43f5-bfb8-aba13bd46eec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451046757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3451046757 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.480360189 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 488272286 ps |
CPU time | 10.09 seconds |
Started | Jul 31 06:59:46 PM PDT 24 |
Finished | Jul 31 06:59:57 PM PDT 24 |
Peak memory | 211468 kb |
Host | smart-56fde213-d919-43dd-87f4-13dc6c47309f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=480360189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.480360189 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3174582167 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 2899403708 ps |
CPU time | 184.59 seconds |
Started | Jul 31 06:59:37 PM PDT 24 |
Finished | Jul 31 07:02:42 PM PDT 24 |
Peak memory | 203268 kb |
Host | smart-b6fe360f-ae9f-4051-a4e7-1b30bd5c5733 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174582167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.3174582167 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1820617065 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 2592215483 ps |
CPU time | 16.75 seconds |
Started | Jul 31 06:59:39 PM PDT 24 |
Finished | Jul 31 06:59:56 PM PDT 24 |
Peak memory | 252448 kb |
Host | smart-fd8346eb-bf50-4573-b76d-968c5c06bea5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820617065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1820617065 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.4147842652 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 59696067837 ps |
CPU time | 835.25 seconds |
Started | Jul 31 06:59:54 PM PDT 24 |
Finished | Jul 31 07:13:50 PM PDT 24 |
Peak memory | 376088 kb |
Host | smart-71727f87-06cb-4168-aa8a-2c26ee07d29a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147842652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.4147842652 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.3435901678 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 21366663 ps |
CPU time | 0.66 seconds |
Started | Jul 31 06:59:53 PM PDT 24 |
Finished | Jul 31 06:59:54 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-405ea687-8b10-4078-ad98-ad3f9265dc87 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435901678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.3435901678 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.3238189646 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 56835115875 ps |
CPU time | 685.56 seconds |
Started | Jul 31 06:59:47 PM PDT 24 |
Finished | Jul 31 07:11:13 PM PDT 24 |
Peak memory | 203896 kb |
Host | smart-4f7ac0dd-0eb1-43a1-9014-bf4c742b699a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238189646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .3238189646 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.2529993944 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 1859605751 ps |
CPU time | 331.35 seconds |
Started | Jul 31 06:59:53 PM PDT 24 |
Finished | Jul 31 07:05:25 PM PDT 24 |
Peak memory | 368868 kb |
Host | smart-378896d4-c20f-4499-9c20-5ff0152d7cfd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529993944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.2529993944 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.987637084 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 1674256477 ps |
CPU time | 10.16 seconds |
Started | Jul 31 06:59:54 PM PDT 24 |
Finished | Jul 31 07:00:04 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-af43b917-7e1b-4e10-bcaa-887770b290ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987637084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esc alation.987637084 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.1493963702 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 4492092656 ps |
CPU time | 114.75 seconds |
Started | Jul 31 06:59:46 PM PDT 24 |
Finished | Jul 31 07:01:41 PM PDT 24 |
Peak memory | 372012 kb |
Host | smart-feceaf0f-31fa-4d75-86a2-981901a50df7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493963702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.1493963702 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1544461621 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 4950230366 ps |
CPU time | 78.46 seconds |
Started | Jul 31 06:59:54 PM PDT 24 |
Finished | Jul 31 07:01:13 PM PDT 24 |
Peak memory | 211460 kb |
Host | smart-94d81fc8-5edf-454c-a5ed-273a953ddd11 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544461621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.1544461621 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.3125515569 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 21555635149 ps |
CPU time | 354.19 seconds |
Started | Jul 31 07:00:03 PM PDT 24 |
Finished | Jul 31 07:06:00 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-b7e5b28c-1a01-4ee0-9698-7cf9e1022197 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125515569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.3125515569 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.1124310940 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 11137384620 ps |
CPU time | 456.2 seconds |
Started | Jul 31 06:59:43 PM PDT 24 |
Finished | Jul 31 07:07:20 PM PDT 24 |
Peak memory | 317716 kb |
Host | smart-ee5f9313-b78b-4986-b68a-c41d1fccebf3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124310940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.1124310940 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.2714986914 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 7535337532 ps |
CPU time | 17.6 seconds |
Started | Jul 31 06:59:47 PM PDT 24 |
Finished | Jul 31 07:00:05 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-09a45ff6-440f-44f3-8e52-034738aa4a92 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714986914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.2714986914 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1791338393 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 12458594746 ps |
CPU time | 388.72 seconds |
Started | Jul 31 06:59:47 PM PDT 24 |
Finished | Jul 31 07:06:16 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-aecbd559-5c01-4074-af8b-17aaa9825f56 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791338393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.1791338393 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.1131460846 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 358956717 ps |
CPU time | 3.4 seconds |
Started | Jul 31 06:59:55 PM PDT 24 |
Finished | Jul 31 06:59:59 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-3b0b1fed-4550-4e26-996b-0f8406e5b77f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131460846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1131460846 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.1188525131 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 5453776207 ps |
CPU time | 39.64 seconds |
Started | Jul 31 06:59:54 PM PDT 24 |
Finished | Jul 31 07:00:34 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-e6acfee1-6fc7-4e32-91bc-fad6b8ed7055 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188525131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.1188525131 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.3548862254 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 1677430366 ps |
CPU time | 101.26 seconds |
Started | Jul 31 06:59:47 PM PDT 24 |
Finished | Jul 31 07:01:28 PM PDT 24 |
Peak memory | 349288 kb |
Host | smart-9c7596d6-5211-43ef-bddd-af0f17d1747f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548862254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3548862254 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.93642155 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 2079637412769 ps |
CPU time | 4368.1 seconds |
Started | Jul 31 06:59:57 PM PDT 24 |
Finished | Jul 31 08:12:45 PM PDT 24 |
Peak memory | 383248 kb |
Host | smart-5af85bce-a13f-43f7-8cce-2e4d7be0f717 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93642155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.sram_ctrl_stress_all.93642155 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.431504384 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 17502320049 ps |
CPU time | 308.89 seconds |
Started | Jul 31 06:59:48 PM PDT 24 |
Finished | Jul 31 07:04:57 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-55001776-52f6-41c3-b615-de645afa55e5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431504384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_stress_pipeline.431504384 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3810617388 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 1482495316 ps |
CPU time | 44.41 seconds |
Started | Jul 31 06:59:47 PM PDT 24 |
Finished | Jul 31 07:00:31 PM PDT 24 |
Peak memory | 304500 kb |
Host | smart-7b946cf8-8a7c-4dfa-9b5d-7ffb331f4608 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810617388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3810617388 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1745781740 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 12478763289 ps |
CPU time | 1027.52 seconds |
Started | Jul 31 07:00:08 PM PDT 24 |
Finished | Jul 31 07:17:15 PM PDT 24 |
Peak memory | 380228 kb |
Host | smart-823b2a4b-06d9-489d-89aa-9b8a1b84b0c6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745781740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.1745781740 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.1839994789 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 45463856 ps |
CPU time | 0.65 seconds |
Started | Jul 31 07:00:12 PM PDT 24 |
Finished | Jul 31 07:00:13 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-754d5966-a4e2-41f5-8a80-5e2be4334e98 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839994789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1839994789 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.2201895738 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 27696713209 ps |
CPU time | 531.55 seconds |
Started | Jul 31 06:59:59 PM PDT 24 |
Finished | Jul 31 07:08:51 PM PDT 24 |
Peak memory | 203808 kb |
Host | smart-d3b6e756-b890-4114-a4d1-6520dcf417bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201895738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .2201895738 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.2280374619 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 28584681829 ps |
CPU time | 666.82 seconds |
Started | Jul 31 07:00:05 PM PDT 24 |
Finished | Jul 31 07:11:13 PM PDT 24 |
Peak memory | 378096 kb |
Host | smart-482d2e89-052b-41bf-845f-c245899b712d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280374619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.2280374619 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.2612785965 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 17692365851 ps |
CPU time | 114.61 seconds |
Started | Jul 31 07:00:06 PM PDT 24 |
Finished | Jul 31 07:02:00 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-7f4ec453-a7ae-4d3b-9386-9522300ca17e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612785965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.2612785965 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.3125982580 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 3647014574 ps |
CPU time | 83.93 seconds |
Started | Jul 31 07:00:00 PM PDT 24 |
Finished | Jul 31 07:01:24 PM PDT 24 |
Peak memory | 371172 kb |
Host | smart-8ea61258-9ad8-481d-be42-eddbf8da7766 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125982580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.3125982580 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.4190984086 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 23178197352 ps |
CPU time | 165.26 seconds |
Started | Jul 31 07:00:13 PM PDT 24 |
Finished | Jul 31 07:02:59 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-661888c0-908f-4bf8-b7d3-4d0aa22af1b9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190984086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.4190984086 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.1896886683 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 2659481474 ps |
CPU time | 145.26 seconds |
Started | Jul 31 07:00:14 PM PDT 24 |
Finished | Jul 31 07:02:39 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-c8fb9b87-9f67-418b-b11d-addbdd177ab2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896886683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.1896886683 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.1438447982 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 53004154985 ps |
CPU time | 1188.34 seconds |
Started | Jul 31 06:59:59 PM PDT 24 |
Finished | Jul 31 07:19:48 PM PDT 24 |
Peak memory | 379080 kb |
Host | smart-0521446f-e11e-4c51-bbb9-668092e87eb5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438447982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.1438447982 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.1417629633 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 4635774291 ps |
CPU time | 12.94 seconds |
Started | Jul 31 07:00:00 PM PDT 24 |
Finished | Jul 31 07:00:13 PM PDT 24 |
Peak memory | 203288 kb |
Host | smart-d41e5389-6543-459d-8a98-f743aabe66ea |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417629633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.1417629633 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.152000386 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 68144320561 ps |
CPU time | 394.65 seconds |
Started | Jul 31 07:00:03 PM PDT 24 |
Finished | Jul 31 07:06:40 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-fbcde3c2-4b49-49e2-b57b-19e892b506bb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152000386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 27.sram_ctrl_partial_access_b2b.152000386 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.102570001 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 1355592870 ps |
CPU time | 3.68 seconds |
Started | Jul 31 07:00:05 PM PDT 24 |
Finished | Jul 31 07:00:09 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-96a0fb1d-9f6e-4c55-bdd2-5c62cfbde78f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102570001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.102570001 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.321188229 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 2325837390 ps |
CPU time | 1041.91 seconds |
Started | Jul 31 07:00:07 PM PDT 24 |
Finished | Jul 31 07:17:29 PM PDT 24 |
Peak memory | 374576 kb |
Host | smart-0877919a-9e17-4a3b-9cfa-ee5065a8246a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321188229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.321188229 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.2347914932 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1118146249 ps |
CPU time | 20.28 seconds |
Started | Jul 31 06:59:59 PM PDT 24 |
Finished | Jul 31 07:00:19 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-3a0c26cb-c2d6-4f9b-85b3-9c2174faf5a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347914932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2347914932 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.3017570566 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 519612836809 ps |
CPU time | 5239.85 seconds |
Started | Jul 31 07:00:12 PM PDT 24 |
Finished | Jul 31 08:27:33 PM PDT 24 |
Peak memory | 378936 kb |
Host | smart-c77c553a-3b18-4084-89ae-105ab53db0c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017570566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.3017570566 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.181038748 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 1206829198 ps |
CPU time | 118.61 seconds |
Started | Jul 31 07:00:11 PM PDT 24 |
Finished | Jul 31 07:02:10 PM PDT 24 |
Peak memory | 350436 kb |
Host | smart-1cc8b482-6690-4073-999f-7ab086b7e1b8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=181038748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.181038748 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.526020540 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 14866589704 ps |
CPU time | 276.68 seconds |
Started | Jul 31 06:59:59 PM PDT 24 |
Finished | Jul 31 07:04:36 PM PDT 24 |
Peak memory | 203284 kb |
Host | smart-19d8da7c-0fa2-4364-b33e-d29c7c3cda89 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526020540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_stress_pipeline.526020540 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2810777467 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 3500885616 ps |
CPU time | 42.29 seconds |
Started | Jul 31 07:00:06 PM PDT 24 |
Finished | Jul 31 07:00:48 PM PDT 24 |
Peak memory | 297124 kb |
Host | smart-a570ec65-e147-46cc-a50f-fe56243bb620 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810777467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.2810777467 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.958269632 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 7644575641 ps |
CPU time | 706.34 seconds |
Started | Jul 31 07:00:30 PM PDT 24 |
Finished | Jul 31 07:12:17 PM PDT 24 |
Peak memory | 374856 kb |
Host | smart-f6c1a8c2-7f96-408d-b642-a90ac44433be |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958269632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 28.sram_ctrl_access_during_key_req.958269632 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.24983163 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 25574578 ps |
CPU time | 0.66 seconds |
Started | Jul 31 07:00:29 PM PDT 24 |
Finished | Jul 31 07:00:29 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-9d8409ef-6251-4ab9-b091-6a7a933beea1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24983163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_alert_test.24983163 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.1047615243 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 9611304154 ps |
CPU time | 662.14 seconds |
Started | Jul 31 07:00:22 PM PDT 24 |
Finished | Jul 31 07:11:25 PM PDT 24 |
Peak memory | 203420 kb |
Host | smart-eb5496cf-1ad4-440c-9262-74ca1ce09260 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047615243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .1047615243 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.4148044660 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 34647462068 ps |
CPU time | 617.61 seconds |
Started | Jul 31 07:00:43 PM PDT 24 |
Finished | Jul 31 07:11:00 PM PDT 24 |
Peak memory | 378088 kb |
Host | smart-6531881f-ef0d-4af5-b225-b027666e1f7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148044660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.4148044660 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.2284242193 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 8617823674 ps |
CPU time | 56.41 seconds |
Started | Jul 31 07:00:29 PM PDT 24 |
Finished | Jul 31 07:01:25 PM PDT 24 |
Peak memory | 203296 kb |
Host | smart-88327b1a-62e6-48b5-b146-fdd3e2ab6202 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284242193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.2284242193 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.1120846194 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 781872869 ps |
CPU time | 102.99 seconds |
Started | Jul 31 07:00:21 PM PDT 24 |
Finished | Jul 31 07:02:04 PM PDT 24 |
Peak memory | 370884 kb |
Host | smart-3a043031-deba-45b2-a99a-5443e3e097dc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120846194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.1120846194 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3744150476 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 3863356267 ps |
CPU time | 62.44 seconds |
Started | Jul 31 07:00:30 PM PDT 24 |
Finished | Jul 31 07:01:32 PM PDT 24 |
Peak memory | 211488 kb |
Host | smart-205fd28b-dfa8-4d3b-a1ab-7c769e56eb6b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744150476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.3744150476 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.3489106938 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 14746276758 ps |
CPU time | 152.79 seconds |
Started | Jul 31 07:00:30 PM PDT 24 |
Finished | Jul 31 07:03:03 PM PDT 24 |
Peak memory | 212260 kb |
Host | smart-f6735ffa-d1e0-4227-a168-4d2342999155 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489106938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.3489106938 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.3796767837 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 12695999555 ps |
CPU time | 490.72 seconds |
Started | Jul 31 07:00:12 PM PDT 24 |
Finished | Jul 31 07:08:23 PM PDT 24 |
Peak memory | 365840 kb |
Host | smart-84150981-3322-4508-ad58-1a7d1ba03a24 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796767837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.3796767837 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.3530368381 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 559778455 ps |
CPU time | 91.86 seconds |
Started | Jul 31 07:00:24 PM PDT 24 |
Finished | Jul 31 07:01:56 PM PDT 24 |
Peak memory | 366884 kb |
Host | smart-4d75ecbf-51ab-4893-9273-964e9f64c635 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530368381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.3530368381 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3544548496 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 33579203838 ps |
CPU time | 214.46 seconds |
Started | Jul 31 07:00:24 PM PDT 24 |
Finished | Jul 31 07:03:59 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-a42c0629-7f4e-4684-be18-0a87975ac495 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544548496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.3544548496 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.1652643146 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 1404412896 ps |
CPU time | 3.2 seconds |
Started | Jul 31 07:00:28 PM PDT 24 |
Finished | Jul 31 07:00:32 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-e7f1da49-200c-4485-a36a-973a7aee4ee7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652643146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1652643146 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.2293359180 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 12092983070 ps |
CPU time | 70.34 seconds |
Started | Jul 31 07:00:31 PM PDT 24 |
Finished | Jul 31 07:01:41 PM PDT 24 |
Peak memory | 275320 kb |
Host | smart-7e561875-21aa-4efc-b81c-87e7258abde6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293359180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2293359180 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.838244398 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 3199396635 ps |
CPU time | 14.19 seconds |
Started | Jul 31 07:00:12 PM PDT 24 |
Finished | Jul 31 07:00:27 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-f0bf8808-7524-4fe1-ab1f-05f3e8c088c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838244398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.838244398 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.4023759982 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 350696173870 ps |
CPU time | 8284.09 seconds |
Started | Jul 31 07:00:29 PM PDT 24 |
Finished | Jul 31 09:18:34 PM PDT 24 |
Peak memory | 382168 kb |
Host | smart-f31b7fad-2123-4da7-afee-f5442137232f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023759982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.4023759982 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1501909003 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 111946825482 ps |
CPU time | 398.78 seconds |
Started | Jul 31 07:00:24 PM PDT 24 |
Finished | Jul 31 07:07:02 PM PDT 24 |
Peak memory | 203348 kb |
Host | smart-fa80b2a4-482f-446f-b55f-af063d9789c1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501909003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.1501909003 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2828781858 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 3130666527 ps |
CPU time | 149.48 seconds |
Started | Jul 31 07:00:24 PM PDT 24 |
Finished | Jul 31 07:02:53 PM PDT 24 |
Peak memory | 372944 kb |
Host | smart-c6b598c4-d8ea-436d-a8ca-fee10ab45650 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828781858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2828781858 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2725456496 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 16600954971 ps |
CPU time | 925.64 seconds |
Started | Jul 31 07:00:35 PM PDT 24 |
Finished | Jul 31 07:16:01 PM PDT 24 |
Peak memory | 372940 kb |
Host | smart-50440240-2843-4d59-b836-9a7dd7a98a8d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725456496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.2725456496 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.403308837 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 68495478 ps |
CPU time | 0.7 seconds |
Started | Jul 31 07:00:42 PM PDT 24 |
Finished | Jul 31 07:00:43 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-67bf7c94-e831-4b59-843d-001b37b5a0da |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403308837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.403308837 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.187532049 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 210870677119 ps |
CPU time | 2377.47 seconds |
Started | Jul 31 07:00:28 PM PDT 24 |
Finished | Jul 31 07:40:05 PM PDT 24 |
Peak memory | 203440 kb |
Host | smart-6ad2b2e7-f949-4d58-bbfa-28dfe48a700c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187532049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection. 187532049 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.2973686066 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 43925506157 ps |
CPU time | 459.25 seconds |
Started | Jul 31 07:00:36 PM PDT 24 |
Finished | Jul 31 07:08:15 PM PDT 24 |
Peak memory | 371328 kb |
Host | smart-900013dd-43e6-4309-818c-19047101c810 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973686066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.2973686066 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.643896807 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 11324944000 ps |
CPU time | 24.58 seconds |
Started | Jul 31 07:00:38 PM PDT 24 |
Finished | Jul 31 07:01:03 PM PDT 24 |
Peak memory | 203284 kb |
Host | smart-d136a8e4-0abb-4256-ac9b-0f4e6505b88b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643896807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_esc alation.643896807 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.107648730 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 3673763785 ps |
CPU time | 20.56 seconds |
Started | Jul 31 07:00:36 PM PDT 24 |
Finished | Jul 31 07:00:57 PM PDT 24 |
Peak memory | 258740 kb |
Host | smart-ed941dc2-35e0-47d0-b20f-3fc3c31dd002 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107648730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.sram_ctrl_max_throughput.107648730 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3107630700 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 87594172655 ps |
CPU time | 157.2 seconds |
Started | Jul 31 07:00:48 PM PDT 24 |
Finished | Jul 31 07:03:25 PM PDT 24 |
Peak memory | 211952 kb |
Host | smart-8f7647f2-f23b-4510-b1a8-d84e2a0e363b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107630700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.3107630700 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.205375852 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 4115258981 ps |
CPU time | 253.19 seconds |
Started | Jul 31 07:01:02 PM PDT 24 |
Finished | Jul 31 07:05:15 PM PDT 24 |
Peak memory | 211496 kb |
Host | smart-b7fa8dcc-209c-4991-abfd-0fd365c2ee4f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205375852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _mem_walk.205375852 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.3153895985 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 8231633287 ps |
CPU time | 923.4 seconds |
Started | Jul 31 07:00:28 PM PDT 24 |
Finished | Jul 31 07:15:52 PM PDT 24 |
Peak memory | 379248 kb |
Host | smart-424b850b-a250-4db9-aebe-b6837a848dca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153895985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.3153895985 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.4065847561 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 748291800 ps |
CPU time | 43.65 seconds |
Started | Jul 31 07:00:39 PM PDT 24 |
Finished | Jul 31 07:01:23 PM PDT 24 |
Peak memory | 291976 kb |
Host | smart-aaa68379-d5b4-4c41-8036-7cb761972d80 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065847561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.4065847561 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1562815542 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 47505333032 ps |
CPU time | 519.98 seconds |
Started | Jul 31 07:00:36 PM PDT 24 |
Finished | Jul 31 07:09:16 PM PDT 24 |
Peak memory | 203332 kb |
Host | smart-cb85b59a-1652-4ad2-8e9f-178e34744341 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562815542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.1562815542 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.2837464455 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 363042870 ps |
CPU time | 3.21 seconds |
Started | Jul 31 07:00:48 PM PDT 24 |
Finished | Jul 31 07:00:51 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-524d1b61-7a7b-4775-9849-afb528185653 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837464455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2837464455 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.2576985167 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 11979785514 ps |
CPU time | 1051.35 seconds |
Started | Jul 31 07:00:38 PM PDT 24 |
Finished | Jul 31 07:18:10 PM PDT 24 |
Peak memory | 377040 kb |
Host | smart-7c0d502a-b2b4-4a98-879a-ce9938d4a33d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576985167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2576985167 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.1428691978 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 3517349635 ps |
CPU time | 20.26 seconds |
Started | Jul 31 07:00:33 PM PDT 24 |
Finished | Jul 31 07:00:54 PM PDT 24 |
Peak memory | 203380 kb |
Host | smart-45e85c92-c0c8-4233-8e1f-4975d7e109dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428691978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1428691978 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.280695037 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 72542673140 ps |
CPU time | 3297.89 seconds |
Started | Jul 31 07:00:43 PM PDT 24 |
Finished | Jul 31 07:55:41 PM PDT 24 |
Peak memory | 382248 kb |
Host | smart-d5e29f43-3c3b-425a-80bc-b43bda30ee5a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280695037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_stress_all.280695037 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.896604652 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 1116896108 ps |
CPU time | 56.07 seconds |
Started | Jul 31 07:00:42 PM PDT 24 |
Finished | Jul 31 07:01:38 PM PDT 24 |
Peak memory | 266732 kb |
Host | smart-aec4149a-d93a-4d0d-ace2-573009c8ab8f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=896604652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.896604652 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.729442971 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 5093025011 ps |
CPU time | 188.39 seconds |
Started | Jul 31 07:00:34 PM PDT 24 |
Finished | Jul 31 07:03:43 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-cffae2d3-a74b-4c71-9142-4f887f9e7ca0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729442971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29 .sram_ctrl_stress_pipeline.729442971 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.265883329 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 761067827 ps |
CPU time | 70.32 seconds |
Started | Jul 31 07:00:35 PM PDT 24 |
Finished | Jul 31 07:01:46 PM PDT 24 |
Peak memory | 333976 kb |
Host | smart-c3d34fd3-7bef-4848-84b5-8ea582b2932c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265883329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_throughput_w_partial_write.265883329 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.917000752 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 9002736866 ps |
CPU time | 566.29 seconds |
Started | Jul 31 06:53:54 PM PDT 24 |
Finished | Jul 31 07:03:21 PM PDT 24 |
Peak memory | 377192 kb |
Host | smart-d268a131-5787-4827-b9c8-52e79f0c03db |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917000752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.sram_ctrl_access_during_key_req.917000752 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.1307642889 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 102596344 ps |
CPU time | 0.71 seconds |
Started | Jul 31 06:54:02 PM PDT 24 |
Finished | Jul 31 06:54:02 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-a420de03-6680-46b2-b779-2111adc67bf9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307642889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1307642889 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.800830254 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 48850575291 ps |
CPU time | 1726.15 seconds |
Started | Jul 31 06:53:48 PM PDT 24 |
Finished | Jul 31 07:22:34 PM PDT 24 |
Peak memory | 204124 kb |
Host | smart-774f840a-f28b-4379-a218-b96aade9dd51 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800830254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.800830254 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.1960787452 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 1688079970 ps |
CPU time | 127.72 seconds |
Started | Jul 31 06:53:55 PM PDT 24 |
Finished | Jul 31 06:56:03 PM PDT 24 |
Peak memory | 360556 kb |
Host | smart-ad828be8-b01c-46ae-b963-8d554ecd1edb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960787452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.1960787452 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.2207452554 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 19401819228 ps |
CPU time | 30.61 seconds |
Started | Jul 31 06:53:56 PM PDT 24 |
Finished | Jul 31 06:54:26 PM PDT 24 |
Peak memory | 211468 kb |
Host | smart-4f775037-5702-423f-a8ea-2a1fc614f11b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207452554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.2207452554 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.1794373055 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 3819857804 ps |
CPU time | 91.67 seconds |
Started | Jul 31 06:53:48 PM PDT 24 |
Finished | Jul 31 06:55:20 PM PDT 24 |
Peak memory | 371108 kb |
Host | smart-cf14320b-69e8-4612-8100-84052a526ede |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794373055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.1794373055 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.246206614 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 2355306196 ps |
CPU time | 75.32 seconds |
Started | Jul 31 06:54:03 PM PDT 24 |
Finished | Jul 31 06:55:19 PM PDT 24 |
Peak memory | 211492 kb |
Host | smart-7aaab5f0-5b6b-48c0-b622-ecab6ee1e4bd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246206614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_mem_partial_access.246206614 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.875032717 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 82784513926 ps |
CPU time | 346.37 seconds |
Started | Jul 31 06:54:04 PM PDT 24 |
Finished | Jul 31 06:59:51 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-2afe2a26-94ba-49d0-8575-8ca4195cbe62 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875032717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ mem_walk.875032717 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.646118479 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 34074787593 ps |
CPU time | 827.45 seconds |
Started | Jul 31 06:53:43 PM PDT 24 |
Finished | Jul 31 07:07:31 PM PDT 24 |
Peak memory | 353568 kb |
Host | smart-3619a390-370e-457b-82f5-5798e47246bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646118479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl e_keys.646118479 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.3544988966 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 432966882 ps |
CPU time | 22.22 seconds |
Started | Jul 31 06:53:50 PM PDT 24 |
Finished | Jul 31 06:54:12 PM PDT 24 |
Peak memory | 262364 kb |
Host | smart-7adcd33a-6a1a-481a-8619-3b2c9a254d9c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544988966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.3544988966 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2983366081 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 22224539528 ps |
CPU time | 545.14 seconds |
Started | Jul 31 06:53:49 PM PDT 24 |
Finished | Jul 31 07:02:54 PM PDT 24 |
Peak memory | 203312 kb |
Host | smart-aa068e79-6f3e-4542-9f7c-4bd89c65b724 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983366081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.2983366081 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.2717297754 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 6735594452 ps |
CPU time | 4.39 seconds |
Started | Jul 31 06:54:03 PM PDT 24 |
Finished | Jul 31 06:54:08 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-f8f0eb53-c9a0-4683-b1a5-877f1cbcc963 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717297754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2717297754 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.2864101094 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 634895073 ps |
CPU time | 101.19 seconds |
Started | Jul 31 06:53:55 PM PDT 24 |
Finished | Jul 31 06:55:37 PM PDT 24 |
Peak memory | 347280 kb |
Host | smart-80e60624-6a3d-4b46-9014-f2850564d179 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864101094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2864101094 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.3550634979 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 338199436 ps |
CPU time | 1.88 seconds |
Started | Jul 31 06:54:03 PM PDT 24 |
Finished | Jul 31 06:54:05 PM PDT 24 |
Peak memory | 223000 kb |
Host | smart-f30ad85e-52c6-41ad-b04a-6f3cab40b603 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550634979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.3550634979 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.3180286990 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 3491463088 ps |
CPU time | 21.79 seconds |
Started | Jul 31 06:53:42 PM PDT 24 |
Finished | Jul 31 06:54:04 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-0865f3c3-36ae-47c5-800d-41fd2da88641 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180286990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3180286990 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.1904076373 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 1048968462100 ps |
CPU time | 5339.41 seconds |
Started | Jul 31 06:54:02 PM PDT 24 |
Finished | Jul 31 08:23:03 PM PDT 24 |
Peak memory | 380188 kb |
Host | smart-06ec334e-baa5-4f27-8b2e-22c2ac712426 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904076373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.1904076373 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.4150506871 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 2298397408 ps |
CPU time | 16.62 seconds |
Started | Jul 31 06:54:07 PM PDT 24 |
Finished | Jul 31 06:54:24 PM PDT 24 |
Peak memory | 211652 kb |
Host | smart-edb00a19-bceb-43c6-846f-6fc6527f14a7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4150506871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.4150506871 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.3743464981 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 4313568419 ps |
CPU time | 230.45 seconds |
Started | Jul 31 06:53:49 PM PDT 24 |
Finished | Jul 31 06:57:40 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-c72b5985-0819-4e42-b7e0-00645d8322bc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743464981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.3743464981 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1151606493 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 1626531753 ps |
CPU time | 46.87 seconds |
Started | Jul 31 06:53:57 PM PDT 24 |
Finished | Jul 31 06:54:44 PM PDT 24 |
Peak memory | 316500 kb |
Host | smart-b13a31bd-8dab-40e8-8109-c19412a1848d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151606493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1151606493 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.4220959570 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 51173927648 ps |
CPU time | 912.26 seconds |
Started | Jul 31 07:00:53 PM PDT 24 |
Finished | Jul 31 07:16:05 PM PDT 24 |
Peak memory | 382180 kb |
Host | smart-6ed984d6-eeda-42ab-9a9c-336a3b3dd4fe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220959570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.4220959570 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.1481735009 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 23338584 ps |
CPU time | 0.63 seconds |
Started | Jul 31 07:01:02 PM PDT 24 |
Finished | Jul 31 07:01:03 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-77e2460e-f459-4bef-b0da-03a3bf35dde0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481735009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.1481735009 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.983748155 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 66357580724 ps |
CPU time | 2067.95 seconds |
Started | Jul 31 07:00:48 PM PDT 24 |
Finished | Jul 31 07:35:17 PM PDT 24 |
Peak memory | 204256 kb |
Host | smart-91339ed0-3064-4b57-b301-7013c37f97ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983748155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection. 983748155 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.3072023397 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 50341159344 ps |
CPU time | 1273.03 seconds |
Started | Jul 31 07:00:53 PM PDT 24 |
Finished | Jul 31 07:22:06 PM PDT 24 |
Peak memory | 377000 kb |
Host | smart-1a37b554-5070-47fd-92a2-e7f67c9284bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072023397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.3072023397 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.1970085616 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 32006260207 ps |
CPU time | 60.44 seconds |
Started | Jul 31 07:00:54 PM PDT 24 |
Finished | Jul 31 07:01:55 PM PDT 24 |
Peak memory | 203296 kb |
Host | smart-6f23e65e-2194-48ba-9a99-a4b66c9c5d48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970085616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.1970085616 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.2982739441 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 791527938 ps |
CPU time | 84.61 seconds |
Started | Jul 31 07:00:47 PM PDT 24 |
Finished | Jul 31 07:02:12 PM PDT 24 |
Peak memory | 323752 kb |
Host | smart-1139e7c9-f8db-4761-8b05-42a1272a8a03 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982739441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.2982739441 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.588344877 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 6117856664 ps |
CPU time | 84.96 seconds |
Started | Jul 31 07:01:02 PM PDT 24 |
Finished | Jul 31 07:02:28 PM PDT 24 |
Peak memory | 219540 kb |
Host | smart-d14f47e6-8843-4582-9831-5a82abd2b451 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588344877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .sram_ctrl_mem_partial_access.588344877 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.2253627460 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 11427695730 ps |
CPU time | 158.41 seconds |
Started | Jul 31 07:00:53 PM PDT 24 |
Finished | Jul 31 07:03:32 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-cd463fcb-6293-458e-8a8a-ca2ad4bb4bd0 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253627460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.2253627460 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.3621527052 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 25127048862 ps |
CPU time | 512.62 seconds |
Started | Jul 31 07:00:48 PM PDT 24 |
Finished | Jul 31 07:09:21 PM PDT 24 |
Peak memory | 380192 kb |
Host | smart-533e01fd-10b0-445f-8981-d41d308dbf85 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621527052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.3621527052 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.1709211792 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 1443883098 ps |
CPU time | 16.19 seconds |
Started | Jul 31 07:00:48 PM PDT 24 |
Finished | Jul 31 07:01:04 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-88b7d69a-cef1-47a8-a648-3c68856d1fc0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709211792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.1709211792 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.4019506645 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 27597557346 ps |
CPU time | 433.89 seconds |
Started | Jul 31 07:00:48 PM PDT 24 |
Finished | Jul 31 07:08:02 PM PDT 24 |
Peak memory | 203352 kb |
Host | smart-b2929fc0-d950-4ce7-b58a-f0fb96bba258 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019506645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.4019506645 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.3286824995 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 368294549 ps |
CPU time | 3.3 seconds |
Started | Jul 31 07:00:54 PM PDT 24 |
Finished | Jul 31 07:00:57 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-ef98b0f8-0393-482f-9abb-aef101629c29 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286824995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3286824995 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.971456532 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 11157499467 ps |
CPU time | 967.79 seconds |
Started | Jul 31 07:00:55 PM PDT 24 |
Finished | Jul 31 07:17:03 PM PDT 24 |
Peak memory | 379176 kb |
Host | smart-060e0f98-3088-434f-ba1f-c97cefadce53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971456532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.971456532 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.2398451046 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 14061066673 ps |
CPU time | 20.66 seconds |
Started | Jul 31 07:00:47 PM PDT 24 |
Finished | Jul 31 07:01:08 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-6e51febf-92e7-4f83-af24-fd54d6aae37c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398451046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2398451046 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.407139251 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 48823671688 ps |
CPU time | 2975.95 seconds |
Started | Jul 31 07:01:01 PM PDT 24 |
Finished | Jul 31 07:50:38 PM PDT 24 |
Peak memory | 389300 kb |
Host | smart-e2e596f4-312b-4203-bddc-3014f9800112 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407139251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_stress_all.407139251 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4028113386 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 1286431967 ps |
CPU time | 69.31 seconds |
Started | Jul 31 07:01:02 PM PDT 24 |
Finished | Jul 31 07:02:11 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-fa041d3b-6a49-4da3-af9d-a4b61bd296c6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4028113386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.4028113386 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.661886693 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 5326096090 ps |
CPU time | 324.17 seconds |
Started | Jul 31 07:00:47 PM PDT 24 |
Finished | Jul 31 07:06:11 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-c64a4328-dbe4-4d50-83f3-223ea76a4869 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661886693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .sram_ctrl_stress_pipeline.661886693 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1277926867 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 1382265993 ps |
CPU time | 7.82 seconds |
Started | Jul 31 07:00:52 PM PDT 24 |
Finished | Jul 31 07:01:00 PM PDT 24 |
Peak memory | 218276 kb |
Host | smart-53d22281-b712-4170-bd66-4c64bbe3803d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277926867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1277926867 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1889690388 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 74166825117 ps |
CPU time | 925.83 seconds |
Started | Jul 31 07:01:09 PM PDT 24 |
Finished | Jul 31 07:16:35 PM PDT 24 |
Peak memory | 374072 kb |
Host | smart-48a0eda1-6d2b-4838-9bf5-9680fc05a98b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889690388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.1889690388 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.1431112986 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 21314295 ps |
CPU time | 0.63 seconds |
Started | Jul 31 07:01:14 PM PDT 24 |
Finished | Jul 31 07:01:15 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-2404aed6-beb7-4258-b278-bde34c4b62d6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431112986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.1431112986 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.402400080 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 155238837436 ps |
CPU time | 1302.4 seconds |
Started | Jul 31 07:01:09 PM PDT 24 |
Finished | Jul 31 07:22:51 PM PDT 24 |
Peak memory | 203844 kb |
Host | smart-37acddf0-8a4a-4d05-b5c6-ee57d4a840eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402400080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection. 402400080 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.2333157765 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 39345558729 ps |
CPU time | 2125.84 seconds |
Started | Jul 31 07:01:14 PM PDT 24 |
Finished | Jul 31 07:36:40 PM PDT 24 |
Peak memory | 378104 kb |
Host | smart-9454bc86-3824-4231-afaf-4af4e0e11b84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333157765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.2333157765 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.937941347 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 18263621736 ps |
CPU time | 31.88 seconds |
Started | Jul 31 07:01:08 PM PDT 24 |
Finished | Jul 31 07:01:40 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-57b1987e-f545-4724-8bb7-9ab4d81ebf70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937941347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_esc alation.937941347 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.776665224 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 3029510964 ps |
CPU time | 107.19 seconds |
Started | Jul 31 07:01:09 PM PDT 24 |
Finished | Jul 31 07:02:56 PM PDT 24 |
Peak memory | 361704 kb |
Host | smart-075dd71d-1b1c-4b0f-aa69-ed8bb67ab9b6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776665224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.sram_ctrl_max_throughput.776665224 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.182462107 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 4544197864 ps |
CPU time | 153.42 seconds |
Started | Jul 31 07:01:13 PM PDT 24 |
Finished | Jul 31 07:03:47 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-ea3cb484-93f0-4509-8e0b-1e2d63537ed1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182462107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .sram_ctrl_mem_partial_access.182462107 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.1106642720 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 10518459778 ps |
CPU time | 161.32 seconds |
Started | Jul 31 07:01:15 PM PDT 24 |
Finished | Jul 31 07:03:57 PM PDT 24 |
Peak memory | 211472 kb |
Host | smart-bfef2c3c-7678-4182-9b60-6b80ac53d535 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106642720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.1106642720 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.3317002370 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 20070390452 ps |
CPU time | 1631.15 seconds |
Started | Jul 31 07:01:01 PM PDT 24 |
Finished | Jul 31 07:28:13 PM PDT 24 |
Peak memory | 375984 kb |
Host | smart-70a76d48-ab16-47cd-8898-963e6f68e0c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317002370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.3317002370 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.116538456 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 8532807535 ps |
CPU time | 9.21 seconds |
Started | Jul 31 07:01:08 PM PDT 24 |
Finished | Jul 31 07:01:17 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-448b822e-b5b4-4a1a-8942-b0aab0b30a2a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116538456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.s ram_ctrl_partial_access.116538456 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3284662117 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 12979604156 ps |
CPU time | 279.21 seconds |
Started | Jul 31 07:01:08 PM PDT 24 |
Finished | Jul 31 07:05:47 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-98a1e111-0a97-4c5d-b5f8-34cb8a196896 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284662117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.3284662117 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.2796684707 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 1867353575 ps |
CPU time | 3.32 seconds |
Started | Jul 31 07:01:14 PM PDT 24 |
Finished | Jul 31 07:01:18 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-0e941436-fae3-4077-9419-9e86fa0b48c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796684707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2796684707 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.2005341845 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 114368209387 ps |
CPU time | 1488.85 seconds |
Started | Jul 31 07:01:16 PM PDT 24 |
Finished | Jul 31 07:26:05 PM PDT 24 |
Peak memory | 376084 kb |
Host | smart-d2c3027c-ed0f-42a9-9f42-b23615718023 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005341845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2005341845 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.1109521593 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 5545954073 ps |
CPU time | 32.37 seconds |
Started | Jul 31 07:01:03 PM PDT 24 |
Finished | Jul 31 07:01:36 PM PDT 24 |
Peak memory | 281988 kb |
Host | smart-53aec70a-0aa2-4406-858a-95fa96f1c9c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109521593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1109521593 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.1146063269 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 97502891056 ps |
CPU time | 201.22 seconds |
Started | Jul 31 07:01:14 PM PDT 24 |
Finished | Jul 31 07:04:36 PM PDT 24 |
Peak memory | 203328 kb |
Host | smart-ae1b7112-e150-40a8-88bb-6bd7a2911e35 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146063269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.1146063269 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2300893546 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 29004715427 ps |
CPU time | 329 seconds |
Started | Jul 31 07:01:09 PM PDT 24 |
Finished | Jul 31 07:06:38 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-ed29bee6-4eae-47f7-8e15-397ed54110f2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300893546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.2300893546 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2425796951 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 1429970743 ps |
CPU time | 8.29 seconds |
Started | Jul 31 07:01:09 PM PDT 24 |
Finished | Jul 31 07:01:17 PM PDT 24 |
Peak memory | 219612 kb |
Host | smart-d3dca872-96c7-407d-9e5a-ce5728890329 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425796951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2425796951 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.4228557736 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 21730541836 ps |
CPU time | 1007.67 seconds |
Started | Jul 31 07:01:25 PM PDT 24 |
Finished | Jul 31 07:18:13 PM PDT 24 |
Peak memory | 379224 kb |
Host | smart-f98f797f-6618-4fb0-afaa-e72e5161e92e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228557736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.4228557736 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.4047319756 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 14453567 ps |
CPU time | 0.66 seconds |
Started | Jul 31 07:01:38 PM PDT 24 |
Finished | Jul 31 07:01:39 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-b9ca3bc7-35fe-4d68-b88d-f019804af34a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047319756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.4047319756 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.999238903 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 634547360376 ps |
CPU time | 2650.85 seconds |
Started | Jul 31 07:01:18 PM PDT 24 |
Finished | Jul 31 07:45:29 PM PDT 24 |
Peak memory | 203780 kb |
Host | smart-2a188109-7525-4dca-a31c-43389849d521 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999238903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection. 999238903 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.3220452840 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 21917223892 ps |
CPU time | 1059 seconds |
Started | Jul 31 07:01:30 PM PDT 24 |
Finished | Jul 31 07:19:09 PM PDT 24 |
Peak memory | 380104 kb |
Host | smart-5c00adc8-d76e-42c9-8e4f-63d9e1c2951e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220452840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.3220452840 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.3342670449 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 22284238043 ps |
CPU time | 68.05 seconds |
Started | Jul 31 07:01:25 PM PDT 24 |
Finished | Jul 31 07:02:33 PM PDT 24 |
Peak memory | 203308 kb |
Host | smart-659bbcc0-e042-4e5c-99e5-0309785297b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342670449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.3342670449 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.589092053 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 1814352752 ps |
CPU time | 60.71 seconds |
Started | Jul 31 07:01:19 PM PDT 24 |
Finished | Jul 31 07:02:19 PM PDT 24 |
Peak memory | 333940 kb |
Host | smart-e82b156b-1f64-48f2-9f77-4494532fb400 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589092053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.sram_ctrl_max_throughput.589092053 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2141037176 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 22679820363 ps |
CPU time | 161 seconds |
Started | Jul 31 07:01:33 PM PDT 24 |
Finished | Jul 31 07:04:15 PM PDT 24 |
Peak memory | 219668 kb |
Host | smart-b217ea85-3ca1-4bd0-be17-4b07389cee4d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141037176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.2141037176 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.1202623444 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 20997708493 ps |
CPU time | 294 seconds |
Started | Jul 31 07:01:35 PM PDT 24 |
Finished | Jul 31 07:06:29 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-21a882b6-7ef1-419d-a816-b07c783a4d8f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202623444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.1202623444 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.2235171823 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 50721480649 ps |
CPU time | 997.76 seconds |
Started | Jul 31 07:01:18 PM PDT 24 |
Finished | Jul 31 07:17:56 PM PDT 24 |
Peak memory | 360692 kb |
Host | smart-7dd27ec5-aff3-45fa-b341-6eca9ae8a6fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235171823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.2235171823 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.1356825778 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 9440915607 ps |
CPU time | 29.92 seconds |
Started | Jul 31 07:01:20 PM PDT 24 |
Finished | Jul 31 07:01:50 PM PDT 24 |
Peak memory | 203320 kb |
Host | smart-cccc3200-b51f-4945-899f-f5d8cf0f905c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356825778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.1356825778 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2956163291 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 61058285525 ps |
CPU time | 377.07 seconds |
Started | Jul 31 07:01:19 PM PDT 24 |
Finished | Jul 31 07:07:37 PM PDT 24 |
Peak memory | 203404 kb |
Host | smart-ff70f426-92ce-4adf-9fa0-bdf0c2a2de5e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956163291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.2956163291 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.3182253872 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 1206955862 ps |
CPU time | 3.31 seconds |
Started | Jul 31 07:01:32 PM PDT 24 |
Finished | Jul 31 07:01:35 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-cb30cd07-f057-4026-918a-5f1fb6309b92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182253872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3182253872 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.465568837 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 180043115282 ps |
CPU time | 811.32 seconds |
Started | Jul 31 07:01:25 PM PDT 24 |
Finished | Jul 31 07:14:56 PM PDT 24 |
Peak memory | 372456 kb |
Host | smart-4f6f2b6e-bbdc-46c2-aa62-4ce692f4f261 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465568837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.465568837 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.898921951 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 1465007374 ps |
CPU time | 19.73 seconds |
Started | Jul 31 07:01:14 PM PDT 24 |
Finished | Jul 31 07:01:34 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-219ddee6-e54d-4dc4-80ca-3839663d87e2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898921951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.898921951 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.435086196 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 712362758831 ps |
CPU time | 5823.49 seconds |
Started | Jul 31 07:01:33 PM PDT 24 |
Finished | Jul 31 08:38:37 PM PDT 24 |
Peak memory | 382300 kb |
Host | smart-e7f6e6c4-d3ab-406b-925d-1316368d3921 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435086196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_stress_all.435086196 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1396495718 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 2208998903 ps |
CPU time | 12.13 seconds |
Started | Jul 31 07:01:32 PM PDT 24 |
Finished | Jul 31 07:01:44 PM PDT 24 |
Peak memory | 211556 kb |
Host | smart-9bc6f31c-9c58-44bd-82cc-3eb7145ec375 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1396495718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1396495718 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3116439279 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 20049055906 ps |
CPU time | 275.5 seconds |
Started | Jul 31 07:01:19 PM PDT 24 |
Finished | Jul 31 07:05:55 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-fde29f4f-1b80-4447-ab68-5eef0afcf82d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116439279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.3116439279 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1502906773 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 839134248 ps |
CPU time | 14.29 seconds |
Started | Jul 31 07:01:25 PM PDT 24 |
Finished | Jul 31 07:01:39 PM PDT 24 |
Peak memory | 239656 kb |
Host | smart-05dff841-612b-4cba-9ab3-ce0889b559e5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502906773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1502906773 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1998145599 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 12448173195 ps |
CPU time | 935.63 seconds |
Started | Jul 31 07:02:21 PM PDT 24 |
Finished | Jul 31 07:17:57 PM PDT 24 |
Peak memory | 377124 kb |
Host | smart-3593ec76-fce5-42c5-b845-124fea188463 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998145599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.1998145599 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.563604762 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 44114365 ps |
CPU time | 0.63 seconds |
Started | Jul 31 07:02:23 PM PDT 24 |
Finished | Jul 31 07:02:23 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-fe4f1f6f-26c0-485e-b15d-7ac16b50b696 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563604762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.563604762 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.2393436038 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 115728895023 ps |
CPU time | 2816.42 seconds |
Started | Jul 31 07:01:37 PM PDT 24 |
Finished | Jul 31 07:48:34 PM PDT 24 |
Peak memory | 203784 kb |
Host | smart-49bde24c-9818-4b51-a6b6-3a4c50080258 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393436038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .2393436038 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.103951339 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 6203715233 ps |
CPU time | 213.2 seconds |
Started | Jul 31 07:02:17 PM PDT 24 |
Finished | Jul 31 07:05:51 PM PDT 24 |
Peak memory | 370900 kb |
Host | smart-0910fceb-c29f-4416-b769-c471b4d3fb0a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103951339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executabl e.103951339 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.279687637 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 10307498055 ps |
CPU time | 68.02 seconds |
Started | Jul 31 07:01:44 PM PDT 24 |
Finished | Jul 31 07:02:52 PM PDT 24 |
Peak memory | 211516 kb |
Host | smart-774b55c0-b554-479f-99d5-eb10f5b07dca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279687637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_esc alation.279687637 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.719294943 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 2940918214 ps |
CPU time | 65.52 seconds |
Started | Jul 31 07:01:43 PM PDT 24 |
Finished | Jul 31 07:02:48 PM PDT 24 |
Peak memory | 315984 kb |
Host | smart-a2efeafd-78c6-44dc-baa5-7949ad2a5890 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719294943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.sram_ctrl_max_throughput.719294943 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.806811333 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 2892026892 ps |
CPU time | 74.33 seconds |
Started | Jul 31 07:02:17 PM PDT 24 |
Finished | Jul 31 07:03:32 PM PDT 24 |
Peak memory | 211488 kb |
Host | smart-8963edf9-86ad-44b8-9540-16220cec4f73 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806811333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .sram_ctrl_mem_partial_access.806811333 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.4208301091 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 14118783532 ps |
CPU time | 170.75 seconds |
Started | Jul 31 07:02:18 PM PDT 24 |
Finished | Jul 31 07:05:09 PM PDT 24 |
Peak memory | 203288 kb |
Host | smart-1c47d932-b558-4837-b371-369f80345edf |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208301091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.4208301091 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.551725962 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 10857896949 ps |
CPU time | 810.71 seconds |
Started | Jul 31 07:01:38 PM PDT 24 |
Finished | Jul 31 07:15:09 PM PDT 24 |
Peak memory | 380064 kb |
Host | smart-afd9273b-439a-4110-b7c1-9f4d65885edb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551725962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multip le_keys.551725962 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.280387707 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 2091517432 ps |
CPU time | 4.4 seconds |
Started | Jul 31 07:01:38 PM PDT 24 |
Finished | Jul 31 07:01:42 PM PDT 24 |
Peak memory | 203000 kb |
Host | smart-0c671baa-ea81-491e-9e62-2d87251ca9f2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280387707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s ram_ctrl_partial_access.280387707 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2772587268 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 4616556715 ps |
CPU time | 260.32 seconds |
Started | Jul 31 07:01:43 PM PDT 24 |
Finished | Jul 31 07:06:04 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-62d103ad-ba67-49b4-a165-73a0738f3fbd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772587268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.2772587268 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.1677962407 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 741438130 ps |
CPU time | 3.25 seconds |
Started | Jul 31 07:02:18 PM PDT 24 |
Finished | Jul 31 07:02:22 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-9d4add73-6c7a-4d73-9435-78392b3d8984 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677962407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1677962407 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.4016993106 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 35698555928 ps |
CPU time | 547.95 seconds |
Started | Jul 31 07:02:21 PM PDT 24 |
Finished | Jul 31 07:11:29 PM PDT 24 |
Peak memory | 368876 kb |
Host | smart-e5bd2813-e865-41aa-9b34-ac841ecd8384 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016993106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.4016993106 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.4161317536 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 3630977711 ps |
CPU time | 140.85 seconds |
Started | Jul 31 07:01:39 PM PDT 24 |
Finished | Jul 31 07:04:00 PM PDT 24 |
Peak memory | 361732 kb |
Host | smart-36b8e676-22a5-47f4-b964-0a77b3ccfa7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161317536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.4161317536 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.970919603 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 146013419110 ps |
CPU time | 7004.81 seconds |
Started | Jul 31 07:02:17 PM PDT 24 |
Finished | Jul 31 08:59:03 PM PDT 24 |
Peak memory | 382352 kb |
Host | smart-799ae9b9-98ee-403b-b2a1-f65cd5846523 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970919603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_stress_all.970919603 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.95172607 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 1006709062 ps |
CPU time | 22.99 seconds |
Started | Jul 31 07:02:16 PM PDT 24 |
Finished | Jul 31 07:02:39 PM PDT 24 |
Peak memory | 211484 kb |
Host | smart-baf973de-5095-491a-a192-23f891a10b00 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=95172607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.95172607 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.4240019195 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 18867944368 ps |
CPU time | 305.21 seconds |
Started | Jul 31 07:01:40 PM PDT 24 |
Finished | Jul 31 07:06:45 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-6373b794-e906-40d0-bd3b-442bc02d9d95 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240019195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.4240019195 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1867865900 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 4482943721 ps |
CPU time | 28.74 seconds |
Started | Jul 31 07:01:44 PM PDT 24 |
Finished | Jul 31 07:02:13 PM PDT 24 |
Peak memory | 280836 kb |
Host | smart-cde5a4b2-2faa-4e2a-bee9-db14c10a1967 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867865900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1867865900 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.1874375323 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 10455104270 ps |
CPU time | 425.81 seconds |
Started | Jul 31 07:02:18 PM PDT 24 |
Finished | Jul 31 07:09:24 PM PDT 24 |
Peak memory | 374924 kb |
Host | smart-e471e6ae-5fb5-4b71-8f2e-a174cd744e54 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874375323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.1874375323 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.2824575544 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 14350387 ps |
CPU time | 0.66 seconds |
Started | Jul 31 07:02:21 PM PDT 24 |
Finished | Jul 31 07:02:21 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-532e2071-816c-4a43-8781-e9140fccdea5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824575544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2824575544 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.1782041983 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 99716426026 ps |
CPU time | 1663.49 seconds |
Started | Jul 31 07:02:19 PM PDT 24 |
Finished | Jul 31 07:30:02 PM PDT 24 |
Peak memory | 203308 kb |
Host | smart-a62681b9-36d7-44ac-80bb-c7d7a25c2443 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782041983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .1782041983 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.1304564890 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 104471715706 ps |
CPU time | 1486.82 seconds |
Started | Jul 31 07:02:18 PM PDT 24 |
Finished | Jul 31 07:27:05 PM PDT 24 |
Peak memory | 378108 kb |
Host | smart-0ba08548-0792-49bc-a196-68331805afc7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304564890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.1304564890 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.1659744995 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 23340272269 ps |
CPU time | 40.11 seconds |
Started | Jul 31 07:02:17 PM PDT 24 |
Finished | Jul 31 07:02:57 PM PDT 24 |
Peak memory | 203296 kb |
Host | smart-1cc2af2e-e5b2-4b70-b325-d7172f2ebf52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659744995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.1659744995 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.3542531334 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 1464689886 ps |
CPU time | 56.06 seconds |
Started | Jul 31 07:02:16 PM PDT 24 |
Finished | Jul 31 07:03:12 PM PDT 24 |
Peak memory | 314536 kb |
Host | smart-b57c1884-30db-455f-95b7-bea0fd02b183 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542531334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.3542531334 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2475749254 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 10232419049 ps |
CPU time | 168.76 seconds |
Started | Jul 31 07:02:17 PM PDT 24 |
Finished | Jul 31 07:05:06 PM PDT 24 |
Peak memory | 211504 kb |
Host | smart-647a3919-1e8d-4eee-b2e0-3fd64868d39b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475749254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.2475749254 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.2505181170 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 2744265578 ps |
CPU time | 148.76 seconds |
Started | Jul 31 07:02:16 PM PDT 24 |
Finished | Jul 31 07:04:45 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-10d91879-8d41-43e2-b7bc-bacf29218649 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505181170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.2505181170 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.1850591530 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 27518221244 ps |
CPU time | 280.35 seconds |
Started | Jul 31 07:02:16 PM PDT 24 |
Finished | Jul 31 07:06:56 PM PDT 24 |
Peak memory | 360048 kb |
Host | smart-f458c02f-cb26-46d6-abff-91d8235f1d30 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850591530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.1850591530 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.2708847744 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 3146024453 ps |
CPU time | 32.23 seconds |
Started | Jul 31 07:02:21 PM PDT 24 |
Finished | Jul 31 07:02:54 PM PDT 24 |
Peak memory | 278756 kb |
Host | smart-55768785-163a-4af9-8290-2e113633d85a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708847744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.2708847744 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.274300290 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 30140104092 ps |
CPU time | 372.61 seconds |
Started | Jul 31 07:02:17 PM PDT 24 |
Finished | Jul 31 07:08:30 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-d2b147c2-a0b1-47a7-bcbe-8ba8924aa188 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274300290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.sram_ctrl_partial_access_b2b.274300290 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.2013127512 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 1406375493 ps |
CPU time | 3.39 seconds |
Started | Jul 31 07:02:18 PM PDT 24 |
Finished | Jul 31 07:02:22 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-98c54758-b6f5-4395-8ba7-62162638667c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013127512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2013127512 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.564767888 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 67645988386 ps |
CPU time | 1484.53 seconds |
Started | Jul 31 07:02:19 PM PDT 24 |
Finished | Jul 31 07:27:04 PM PDT 24 |
Peak memory | 378124 kb |
Host | smart-fcea7855-fc19-4065-9f80-891347cf84e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564767888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.564767888 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.3507039430 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 1399425734 ps |
CPU time | 23.15 seconds |
Started | Jul 31 07:02:18 PM PDT 24 |
Finished | Jul 31 07:02:42 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-af053be2-e6ee-4a72-8d50-f7a0a50d9f7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507039430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.3507039430 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.645897777 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 192226805503 ps |
CPU time | 1845.28 seconds |
Started | Jul 31 07:02:19 PM PDT 24 |
Finished | Jul 31 07:33:05 PM PDT 24 |
Peak memory | 388340 kb |
Host | smart-c2ebd814-01dc-4b2e-ad61-f4c45cbbfab0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645897777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_stress_all.645897777 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1455807322 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 275922432 ps |
CPU time | 15.01 seconds |
Started | Jul 31 07:02:19 PM PDT 24 |
Finished | Jul 31 07:02:34 PM PDT 24 |
Peak memory | 211484 kb |
Host | smart-49cdaa83-251d-4ec6-84fc-6d39a3599769 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1455807322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1455807322 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1282213549 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 11889978036 ps |
CPU time | 358.46 seconds |
Started | Jul 31 07:02:20 PM PDT 24 |
Finished | Jul 31 07:08:18 PM PDT 24 |
Peak memory | 203340 kb |
Host | smart-3c009b4b-bf0d-431e-8a0b-d5a2f4fdcdcb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282213549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.1282213549 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1862204440 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 746347472 ps |
CPU time | 43.5 seconds |
Started | Jul 31 07:02:17 PM PDT 24 |
Finished | Jul 31 07:03:00 PM PDT 24 |
Peak memory | 289088 kb |
Host | smart-4a211285-1fb2-4145-927f-39b257e874c0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862204440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1862204440 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2120283187 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 14294509795 ps |
CPU time | 1064.76 seconds |
Started | Jul 31 07:02:23 PM PDT 24 |
Finished | Jul 31 07:20:08 PM PDT 24 |
Peak memory | 375968 kb |
Host | smart-22dceb5d-1dc3-4534-a1d5-6859766c035a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120283187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.2120283187 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.1137146621 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 23390481 ps |
CPU time | 0.62 seconds |
Started | Jul 31 07:02:36 PM PDT 24 |
Finished | Jul 31 07:02:37 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-65675b5a-5498-4b0e-a3b7-8664eb9bf45b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137146621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1137146621 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.1162725181 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 239571504134 ps |
CPU time | 1009.35 seconds |
Started | Jul 31 07:02:18 PM PDT 24 |
Finished | Jul 31 07:19:08 PM PDT 24 |
Peak memory | 203320 kb |
Host | smart-3adb3f84-d1b4-4f36-9fc1-d7a3e6dd5583 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162725181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .1162725181 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.489452323 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 7595456297 ps |
CPU time | 830.54 seconds |
Started | Jul 31 07:02:23 PM PDT 24 |
Finished | Jul 31 07:16:13 PM PDT 24 |
Peak memory | 372960 kb |
Host | smart-33c699b6-6c9f-4bd5-8dcd-f78dc29dec96 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489452323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executabl e.489452323 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.375586716 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 3956907431 ps |
CPU time | 15 seconds |
Started | Jul 31 07:02:24 PM PDT 24 |
Finished | Jul 31 07:02:39 PM PDT 24 |
Peak memory | 211492 kb |
Host | smart-5edc5628-aeae-41d8-a041-ecb068235686 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375586716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_esc alation.375586716 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.1147523485 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 3067160174 ps |
CPU time | 21.17 seconds |
Started | Jul 31 07:02:22 PM PDT 24 |
Finished | Jul 31 07:02:43 PM PDT 24 |
Peak memory | 259632 kb |
Host | smart-01455065-429b-4a8a-bb7f-7ccadf3bdc58 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147523485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.1147523485 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1058982650 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 20499683789 ps |
CPU time | 162.82 seconds |
Started | Jul 31 07:02:29 PM PDT 24 |
Finished | Jul 31 07:05:12 PM PDT 24 |
Peak memory | 219568 kb |
Host | smart-5e21adda-d04b-455a-a1b7-eee8bf60eda3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058982650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.1058982650 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.944899864 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 43807710212 ps |
CPU time | 161.87 seconds |
Started | Jul 31 07:02:23 PM PDT 24 |
Finished | Jul 31 07:05:05 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-33b61775-d5ff-4046-94ca-58c8b6f2d180 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944899864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _mem_walk.944899864 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.1884211819 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 7865775743 ps |
CPU time | 518.21 seconds |
Started | Jul 31 07:02:19 PM PDT 24 |
Finished | Jul 31 07:10:57 PM PDT 24 |
Peak memory | 369968 kb |
Host | smart-a72bdcd0-79d1-4932-8783-9e07f7ff9e41 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884211819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.1884211819 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.3430862938 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 2653842247 ps |
CPU time | 11.34 seconds |
Started | Jul 31 07:02:18 PM PDT 24 |
Finished | Jul 31 07:02:30 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-6ab018f1-e65b-4f48-b0cd-6f3c6d5f52ea |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430862938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.3430862938 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.520136916 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 6630371617 ps |
CPU time | 380.62 seconds |
Started | Jul 31 07:02:18 PM PDT 24 |
Finished | Jul 31 07:08:38 PM PDT 24 |
Peak memory | 203300 kb |
Host | smart-6244ee20-a486-40cf-86d1-a15a98117729 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520136916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.sram_ctrl_partial_access_b2b.520136916 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.3323210142 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 353970641 ps |
CPU time | 3.43 seconds |
Started | Jul 31 07:02:23 PM PDT 24 |
Finished | Jul 31 07:02:27 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-08f300bd-9e49-4ee5-bd9a-6cc1bb3beb4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323210142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3323210142 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.3709888914 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 2748815689 ps |
CPU time | 480.26 seconds |
Started | Jul 31 07:02:22 PM PDT 24 |
Finished | Jul 31 07:10:22 PM PDT 24 |
Peak memory | 372944 kb |
Host | smart-36646fc0-9a07-4095-8651-5d63a8cd5142 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709888914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.3709888914 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.3524053655 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 2786194679 ps |
CPU time | 123.27 seconds |
Started | Jul 31 07:02:16 PM PDT 24 |
Finished | Jul 31 07:04:20 PM PDT 24 |
Peak memory | 368844 kb |
Host | smart-68f4a991-77ba-4a18-9517-b12a539f95cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524053655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3524053655 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.4087701223 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 637194507341 ps |
CPU time | 5588.21 seconds |
Started | Jul 31 07:02:29 PM PDT 24 |
Finished | Jul 31 08:35:38 PM PDT 24 |
Peak memory | 382208 kb |
Host | smart-b8d046e3-5e2b-4c91-8841-20479e8aedda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087701223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.4087701223 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2237853608 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 551347890 ps |
CPU time | 11.8 seconds |
Started | Jul 31 07:02:33 PM PDT 24 |
Finished | Jul 31 07:02:45 PM PDT 24 |
Peak memory | 211512 kb |
Host | smart-e95a62ca-dffe-4f68-9471-c6e4ec78a1aa |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2237853608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.2237853608 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1456404452 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 8325292408 ps |
CPU time | 226.29 seconds |
Started | Jul 31 07:02:18 PM PDT 24 |
Finished | Jul 31 07:06:05 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-ea3fcc1a-6901-4f63-9fc9-0598d14e1fba |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456404452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1456404452 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1714807470 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 766379096 ps |
CPU time | 50.7 seconds |
Started | Jul 31 07:02:23 PM PDT 24 |
Finished | Jul 31 07:03:14 PM PDT 24 |
Peak memory | 302500 kb |
Host | smart-a2b9e13c-82b3-470c-ba25-9b45dee9c839 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714807470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.1714807470 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1113803897 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 38799936500 ps |
CPU time | 788.4 seconds |
Started | Jul 31 07:02:51 PM PDT 24 |
Finished | Jul 31 07:16:00 PM PDT 24 |
Peak memory | 376108 kb |
Host | smart-82708710-91da-448a-b056-0035b263d046 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113803897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.1113803897 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.2560658539 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 19222645 ps |
CPU time | 0.65 seconds |
Started | Jul 31 07:02:55 PM PDT 24 |
Finished | Jul 31 07:02:56 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-f1b7f9cb-0b2b-45dc-9427-c22f2091735a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560658539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.2560658539 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.3463378674 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 146109032964 ps |
CPU time | 1695.38 seconds |
Started | Jul 31 07:02:49 PM PDT 24 |
Finished | Jul 31 07:31:05 PM PDT 24 |
Peak memory | 380144 kb |
Host | smart-a72ca240-814c-47b3-88c6-fcffa9a9abf0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463378674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.3463378674 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.1372169391 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 76419661051 ps |
CPU time | 139.37 seconds |
Started | Jul 31 07:02:43 PM PDT 24 |
Finished | Jul 31 07:05:02 PM PDT 24 |
Peak memory | 216232 kb |
Host | smart-1d80cf53-36ef-4105-b3eb-36055b1dbf8f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372169391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.1372169391 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.2532769906 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 5792374902 ps |
CPU time | 95.83 seconds |
Started | Jul 31 07:02:45 PM PDT 24 |
Finished | Jul 31 07:04:21 PM PDT 24 |
Peak memory | 356612 kb |
Host | smart-cf08e60b-38dd-43af-9b6a-bb5d371b03b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532769906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.2532769906 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2986235614 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 9121793295 ps |
CPU time | 150.9 seconds |
Started | Jul 31 07:02:54 PM PDT 24 |
Finished | Jul 31 07:05:25 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-e52fcd39-d0ae-45ee-b79b-b9e38475a6cd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986235614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.2986235614 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.1412494366 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 57659478721 ps |
CPU time | 333.33 seconds |
Started | Jul 31 07:02:50 PM PDT 24 |
Finished | Jul 31 07:08:24 PM PDT 24 |
Peak memory | 211472 kb |
Host | smart-23b6f0a8-ae04-4813-b54a-a007688e37f0 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412494366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.1412494366 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.300154184 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 17246402007 ps |
CPU time | 875.17 seconds |
Started | Jul 31 07:02:35 PM PDT 24 |
Finished | Jul 31 07:17:10 PM PDT 24 |
Peak memory | 373036 kb |
Host | smart-51db26a2-1f30-4024-8154-409e47814c43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300154184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multip le_keys.300154184 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.3655005963 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 3106169413 ps |
CPU time | 9.7 seconds |
Started | Jul 31 07:02:49 PM PDT 24 |
Finished | Jul 31 07:02:59 PM PDT 24 |
Peak memory | 213880 kb |
Host | smart-2fbd7890-1509-4cc9-ade0-1f9df01211b9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655005963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.3655005963 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1289561893 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 22164001634 ps |
CPU time | 457.41 seconds |
Started | Jul 31 07:02:43 PM PDT 24 |
Finished | Jul 31 07:10:20 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-c4083789-a0ff-4ed6-883e-4760a740bd85 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289561893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.1289561893 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.3713800287 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 684075654 ps |
CPU time | 3.25 seconds |
Started | Jul 31 07:02:50 PM PDT 24 |
Finished | Jul 31 07:02:53 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-f655efb7-8674-4741-86a6-bc792efe96c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713800287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3713800287 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.2988773152 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 4166429547 ps |
CPU time | 1444.49 seconds |
Started | Jul 31 07:02:50 PM PDT 24 |
Finished | Jul 31 07:26:55 PM PDT 24 |
Peak memory | 374976 kb |
Host | smart-66b0e063-5a28-405e-bfbc-25230859a823 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988773152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2988773152 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.1188076596 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 4853040707 ps |
CPU time | 7.32 seconds |
Started | Jul 31 07:02:37 PM PDT 24 |
Finished | Jul 31 07:02:44 PM PDT 24 |
Peak memory | 203320 kb |
Host | smart-f1a353e9-af79-4877-a215-4248e76f10f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188076596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1188076596 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.1647043287 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 158390480124 ps |
CPU time | 2433.8 seconds |
Started | Jul 31 07:02:56 PM PDT 24 |
Finished | Jul 31 07:43:30 PM PDT 24 |
Peak memory | 382312 kb |
Host | smart-662b9780-18dd-4610-9c0f-12d92c7e0e7a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647043287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.1647043287 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1679451445 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 8428997582 ps |
CPU time | 30.46 seconds |
Started | Jul 31 07:02:56 PM PDT 24 |
Finished | Jul 31 07:03:27 PM PDT 24 |
Peak memory | 211492 kb |
Host | smart-1134161a-cc49-4ed5-97ae-b55707ddc1b4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1679451445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1679451445 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.568502142 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 4396144108 ps |
CPU time | 289.67 seconds |
Started | Jul 31 07:02:37 PM PDT 24 |
Finished | Jul 31 07:07:26 PM PDT 24 |
Peak memory | 203380 kb |
Host | smart-bd4f4a10-7f73-4f15-b3ef-b1c266e88a79 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568502142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36 .sram_ctrl_stress_pipeline.568502142 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.4012130570 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 1090797908 ps |
CPU time | 130.83 seconds |
Started | Jul 31 07:02:41 PM PDT 24 |
Finished | Jul 31 07:04:52 PM PDT 24 |
Peak memory | 359668 kb |
Host | smart-d32bf7b0-208d-467c-a84d-98b9e794a7e3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012130570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.4012130570 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3003581448 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 3470290437 ps |
CPU time | 237.16 seconds |
Started | Jul 31 07:03:00 PM PDT 24 |
Finished | Jul 31 07:06:57 PM PDT 24 |
Peak memory | 367864 kb |
Host | smart-177c7c03-ee47-43aa-adc5-825b8492a5cd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003581448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.3003581448 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.3288731568 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 32925033 ps |
CPU time | 0.65 seconds |
Started | Jul 31 07:03:05 PM PDT 24 |
Finished | Jul 31 07:03:06 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-917710a4-a1d9-48e4-bbc5-2bce2fdfa2a6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288731568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3288731568 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.4004646860 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 337774098069 ps |
CPU time | 2696.17 seconds |
Started | Jul 31 07:03:00 PM PDT 24 |
Finished | Jul 31 07:47:57 PM PDT 24 |
Peak memory | 203288 kb |
Host | smart-9b590d25-6139-4d2f-a425-3cedeaedac38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004646860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .4004646860 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.1270674298 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 130689551425 ps |
CPU time | 1383.93 seconds |
Started | Jul 31 07:03:01 PM PDT 24 |
Finished | Jul 31 07:26:05 PM PDT 24 |
Peak memory | 378220 kb |
Host | smart-ee102ff0-5edc-452f-be6e-8c34658ea787 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270674298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.1270674298 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.2493112819 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 8005133003 ps |
CPU time | 51.51 seconds |
Started | Jul 31 07:03:01 PM PDT 24 |
Finished | Jul 31 07:03:52 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-f16223b1-b55a-4e20-a434-50660d3d46e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493112819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.2493112819 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.3555985200 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 2931067939 ps |
CPU time | 27.29 seconds |
Started | Jul 31 07:02:59 PM PDT 24 |
Finished | Jul 31 07:03:27 PM PDT 24 |
Peak memory | 268648 kb |
Host | smart-507209ec-557a-41cf-9733-75a72b713fa5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555985200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.3555985200 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2667463440 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 28663606801 ps |
CPU time | 90.43 seconds |
Started | Jul 31 07:03:07 PM PDT 24 |
Finished | Jul 31 07:04:37 PM PDT 24 |
Peak memory | 212084 kb |
Host | smart-ff22cf18-5795-49ea-b0b5-3b2dbaea775f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667463440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.2667463440 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.1211580206 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 14135014706 ps |
CPU time | 164.77 seconds |
Started | Jul 31 07:03:00 PM PDT 24 |
Finished | Jul 31 07:05:45 PM PDT 24 |
Peak memory | 211488 kb |
Host | smart-fd2c263d-6e03-4f5d-a319-a4fd9fddbff7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211580206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.1211580206 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.307916940 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 504215148 ps |
CPU time | 48.2 seconds |
Started | Jul 31 07:03:01 PM PDT 24 |
Finished | Jul 31 07:03:49 PM PDT 24 |
Peak memory | 301324 kb |
Host | smart-a40e95c6-3557-4362-9b30-02a0609e6789 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307916940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multip le_keys.307916940 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.4154115578 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 2011702704 ps |
CPU time | 86.76 seconds |
Started | Jul 31 07:03:00 PM PDT 24 |
Finished | Jul 31 07:04:28 PM PDT 24 |
Peak memory | 337120 kb |
Host | smart-1faa9196-ba82-48de-8fb2-df4a91a2832b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154115578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.4154115578 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1600919772 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 70874715821 ps |
CPU time | 440.66 seconds |
Started | Jul 31 07:02:56 PM PDT 24 |
Finished | Jul 31 07:10:17 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-ee41c974-ffed-4c0e-87c7-4f7642b3b2bc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600919772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.1600919772 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.1776582978 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 370790466 ps |
CPU time | 3.22 seconds |
Started | Jul 31 07:02:59 PM PDT 24 |
Finished | Jul 31 07:03:02 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-2a666119-7d42-4af9-be81-001e7faf12e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776582978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1776582978 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.1971482396 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 3570835902 ps |
CPU time | 929.15 seconds |
Started | Jul 31 07:03:00 PM PDT 24 |
Finished | Jul 31 07:18:30 PM PDT 24 |
Peak memory | 379160 kb |
Host | smart-6aa38aaa-b7a2-4d9a-8841-cc6f2491baf7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971482396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1971482396 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.3969483666 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 1935200514 ps |
CPU time | 101.02 seconds |
Started | Jul 31 07:02:55 PM PDT 24 |
Finished | Jul 31 07:04:36 PM PDT 24 |
Peak memory | 370864 kb |
Host | smart-0ed45148-cfc7-4a72-97c8-b42a73ce1abe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969483666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3969483666 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.234440199 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 220019166639 ps |
CPU time | 4047.04 seconds |
Started | Jul 31 07:03:07 PM PDT 24 |
Finished | Jul 31 08:10:35 PM PDT 24 |
Peak memory | 381148 kb |
Host | smart-9c98b47f-d6e5-45b5-8aa0-4d5880d32ecd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234440199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_stress_all.234440199 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2460588626 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 207627255 ps |
CPU time | 10.6 seconds |
Started | Jul 31 07:03:09 PM PDT 24 |
Finished | Jul 31 07:03:20 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-0987bc72-bc43-4a6e-a108-7bb9195a28ce |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2460588626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2460588626 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3030845923 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 5652232484 ps |
CPU time | 174.81 seconds |
Started | Jul 31 07:03:01 PM PDT 24 |
Finished | Jul 31 07:05:56 PM PDT 24 |
Peak memory | 203332 kb |
Host | smart-b8369444-7925-4264-80dd-755e79406769 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030845923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.3030845923 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4179890455 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 794881378 ps |
CPU time | 44.02 seconds |
Started | Jul 31 07:03:02 PM PDT 24 |
Finished | Jul 31 07:03:46 PM PDT 24 |
Peak memory | 302372 kb |
Host | smart-f9e3c54a-fdd1-43b9-ba6c-88ee14a02f5f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179890455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.4179890455 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1569419245 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 13645855307 ps |
CPU time | 191.78 seconds |
Started | Jul 31 07:03:20 PM PDT 24 |
Finished | Jul 31 07:06:32 PM PDT 24 |
Peak memory | 311964 kb |
Host | smart-6ac8276f-c35c-4bb8-b6eb-01bf7ab9d3f8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569419245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.1569419245 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.3138499913 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 16375976 ps |
CPU time | 0.69 seconds |
Started | Jul 31 07:03:25 PM PDT 24 |
Finished | Jul 31 07:03:25 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-bd2c2993-d65d-45f3-8c44-903a5b5e97e9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138499913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3138499913 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.3359302560 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 87704913478 ps |
CPU time | 2013.78 seconds |
Started | Jul 31 07:03:11 PM PDT 24 |
Finished | Jul 31 07:36:45 PM PDT 24 |
Peak memory | 203912 kb |
Host | smart-86f30549-e568-44a7-8261-cd1d1d7edc20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359302560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .3359302560 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.1386547054 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 32711280172 ps |
CPU time | 419.6 seconds |
Started | Jul 31 07:03:19 PM PDT 24 |
Finished | Jul 31 07:10:19 PM PDT 24 |
Peak memory | 353116 kb |
Host | smart-c6b0099c-6cae-414b-ad34-d352b56029d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386547054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.1386547054 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.2030225728 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 38749568771 ps |
CPU time | 58.79 seconds |
Started | Jul 31 07:03:26 PM PDT 24 |
Finished | Jul 31 07:04:25 PM PDT 24 |
Peak memory | 211472 kb |
Host | smart-15bbb133-2dcb-4384-af4e-e93c5f9e2908 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030225728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.2030225728 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.2444185690 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 740966172 ps |
CPU time | 38.16 seconds |
Started | Jul 31 07:03:13 PM PDT 24 |
Finished | Jul 31 07:03:51 PM PDT 24 |
Peak memory | 284912 kb |
Host | smart-15fea906-babd-41a1-9869-70fe2ec894f0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444185690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.2444185690 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.429552746 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 19648569541 ps |
CPU time | 81.95 seconds |
Started | Jul 31 07:03:22 PM PDT 24 |
Finished | Jul 31 07:04:44 PM PDT 24 |
Peak memory | 211736 kb |
Host | smart-280d9aa6-893b-49e2-a972-849dfe777a64 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429552746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_mem_partial_access.429552746 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.2418316801 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 10509074488 ps |
CPU time | 303.1 seconds |
Started | Jul 31 07:03:19 PM PDT 24 |
Finished | Jul 31 07:08:22 PM PDT 24 |
Peak memory | 211364 kb |
Host | smart-d5fbdd63-662a-4881-9611-06dff7188834 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418316801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.2418316801 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.2187118109 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 118072335891 ps |
CPU time | 1122.63 seconds |
Started | Jul 31 07:03:12 PM PDT 24 |
Finished | Jul 31 07:21:55 PM PDT 24 |
Peak memory | 378004 kb |
Host | smart-f170f201-9b6e-4e70-8c1e-5f63da403980 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187118109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.2187118109 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.4128399427 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 4549575159 ps |
CPU time | 13.56 seconds |
Started | Jul 31 07:03:12 PM PDT 24 |
Finished | Jul 31 07:03:26 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-2f0151d3-3edd-467a-9b7d-974c076cd8eb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128399427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.4128399427 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2770633203 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 18501067293 ps |
CPU time | 198.8 seconds |
Started | Jul 31 07:03:14 PM PDT 24 |
Finished | Jul 31 07:06:33 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-345774f0-a717-473b-810a-34bad2721cd7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770633203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.2770633203 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.3232932630 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 3350456579 ps |
CPU time | 3.63 seconds |
Started | Jul 31 07:03:18 PM PDT 24 |
Finished | Jul 31 07:03:21 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-b252334b-70c4-4092-8451-dc97af2327ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232932630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3232932630 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.51588378 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 14029821360 ps |
CPU time | 1536.89 seconds |
Started | Jul 31 07:03:19 PM PDT 24 |
Finished | Jul 31 07:28:56 PM PDT 24 |
Peak memory | 381196 kb |
Host | smart-f1640df6-8864-40c8-85c8-ca0c5c912812 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51588378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.51588378 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.1417387892 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 819812886 ps |
CPU time | 13.7 seconds |
Started | Jul 31 07:03:06 PM PDT 24 |
Finished | Jul 31 07:03:20 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-6de43d43-83f9-462d-b4cd-13f944a39f12 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417387892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1417387892 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.819477907 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 268502531999 ps |
CPU time | 7849.42 seconds |
Started | Jul 31 07:03:24 PM PDT 24 |
Finished | Jul 31 09:14:15 PM PDT 24 |
Peak memory | 383336 kb |
Host | smart-9349cb54-13f2-4496-90a8-f6babd2deed1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819477907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_stress_all.819477907 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3330773798 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 2669124951 ps |
CPU time | 37.12 seconds |
Started | Jul 31 07:03:19 PM PDT 24 |
Finished | Jul 31 07:03:56 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-d6427cff-913e-446c-8077-8dd43ac4822c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3330773798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3330773798 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1785800292 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 14980835907 ps |
CPU time | 171.88 seconds |
Started | Jul 31 07:03:12 PM PDT 24 |
Finished | Jul 31 07:06:04 PM PDT 24 |
Peak memory | 203300 kb |
Host | smart-37d77e0d-fa02-4b3e-bb91-e79078f607e9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785800292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.1785800292 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2492082107 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 11607607949 ps |
CPU time | 19.16 seconds |
Started | Jul 31 07:03:21 PM PDT 24 |
Finished | Jul 31 07:03:40 PM PDT 24 |
Peak memory | 242824 kb |
Host | smart-68379862-06ad-4ddb-9038-aec20ff14905 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492082107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2492082107 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.101166935 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 33384375315 ps |
CPU time | 628.81 seconds |
Started | Jul 31 07:03:37 PM PDT 24 |
Finished | Jul 31 07:14:06 PM PDT 24 |
Peak memory | 365844 kb |
Host | smart-6fff020d-5793-468c-a2eb-9664a42c117e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101166935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 39.sram_ctrl_access_during_key_req.101166935 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.3234563221 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 18171226 ps |
CPU time | 0.66 seconds |
Started | Jul 31 07:03:43 PM PDT 24 |
Finished | Jul 31 07:03:44 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-8f3ba1d9-f477-4950-97e9-d9c98a88a184 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234563221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3234563221 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.975910309 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 395530606882 ps |
CPU time | 1265.55 seconds |
Started | Jul 31 07:03:39 PM PDT 24 |
Finished | Jul 31 07:24:45 PM PDT 24 |
Peak memory | 204040 kb |
Host | smart-2c4b82a9-f814-4785-bff5-035cd8c5a69c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975910309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection. 975910309 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.3932026268 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 7692751385 ps |
CPU time | 659.13 seconds |
Started | Jul 31 07:03:35 PM PDT 24 |
Finished | Jul 31 07:14:34 PM PDT 24 |
Peak memory | 373048 kb |
Host | smart-f8281f25-30bc-497c-9665-dfc2d8f5189f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932026268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.3932026268 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.583452626 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 31319417625 ps |
CPU time | 51.22 seconds |
Started | Jul 31 07:03:38 PM PDT 24 |
Finished | Jul 31 07:04:29 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-3698ca56-58c3-44c5-8511-7969c06ffc4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583452626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_esc alation.583452626 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.2735729233 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 1682526977 ps |
CPU time | 51.74 seconds |
Started | Jul 31 07:03:37 PM PDT 24 |
Finished | Jul 31 07:04:29 PM PDT 24 |
Peak memory | 329656 kb |
Host | smart-ed319eb2-ab65-419e-8711-71c0639af903 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735729233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.2735729233 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2252808658 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 16229579030 ps |
CPU time | 153.12 seconds |
Started | Jul 31 07:03:36 PM PDT 24 |
Finished | Jul 31 07:06:10 PM PDT 24 |
Peak memory | 211508 kb |
Host | smart-9670b0cd-0302-44d5-91e3-3e664522eff5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252808658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.2252808658 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.4204048410 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 4028553179 ps |
CPU time | 131.53 seconds |
Started | Jul 31 07:03:36 PM PDT 24 |
Finished | Jul 31 07:05:47 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-fed12489-6243-4b46-b481-e3019f37ac88 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204048410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.4204048410 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.1553727910 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 23410850316 ps |
CPU time | 1157.64 seconds |
Started | Jul 31 07:03:23 PM PDT 24 |
Finished | Jul 31 07:22:41 PM PDT 24 |
Peak memory | 375788 kb |
Host | smart-cf6ed09a-83cd-4f58-b6f0-00d108034fb8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553727910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.1553727910 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.1578230707 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 2182607564 ps |
CPU time | 156.12 seconds |
Started | Jul 31 07:03:39 PM PDT 24 |
Finished | Jul 31 07:06:15 PM PDT 24 |
Peak memory | 369104 kb |
Host | smart-8955c39e-d5a3-4d6c-aeaa-ad25fc99b35d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578230707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.1578230707 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.475955389 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 21829728506 ps |
CPU time | 500.63 seconds |
Started | Jul 31 07:03:37 PM PDT 24 |
Finished | Jul 31 07:11:58 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-4d1a2f93-12e3-4a3d-9f7d-5a028df037c1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475955389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.sram_ctrl_partial_access_b2b.475955389 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.3311802695 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 457282840 ps |
CPU time | 3.31 seconds |
Started | Jul 31 07:03:37 PM PDT 24 |
Finished | Jul 31 07:03:41 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-fac367ae-b203-4655-aee4-9e9b5c6741f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311802695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3311802695 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.1774171609 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 12985220552 ps |
CPU time | 89.55 seconds |
Started | Jul 31 07:03:39 PM PDT 24 |
Finished | Jul 31 07:05:08 PM PDT 24 |
Peak memory | 297164 kb |
Host | smart-40d77edc-d1d0-456c-8c78-c83799bb3695 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774171609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1774171609 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.3850166511 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 2126929067 ps |
CPU time | 12.88 seconds |
Started | Jul 31 07:03:24 PM PDT 24 |
Finished | Jul 31 07:03:37 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-cafd4b5a-c892-4555-bf08-a064916a3c45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850166511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3850166511 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.4000987482 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 178239511322 ps |
CPU time | 2200.51 seconds |
Started | Jul 31 07:03:38 PM PDT 24 |
Finished | Jul 31 07:40:19 PM PDT 24 |
Peak memory | 381188 kb |
Host | smart-e6cbf177-56b9-4ad2-8b61-617d6ad299bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000987482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.4000987482 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.852604638 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 1179670924 ps |
CPU time | 8.15 seconds |
Started | Jul 31 07:03:39 PM PDT 24 |
Finished | Jul 31 07:03:47 PM PDT 24 |
Peak memory | 211540 kb |
Host | smart-78c24874-bb14-4574-b9dd-cb2315d47503 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=852604638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.852604638 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.951266064 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 11390437821 ps |
CPU time | 235.96 seconds |
Started | Jul 31 07:03:37 PM PDT 24 |
Finished | Jul 31 07:07:34 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-946620cc-26e8-4458-9cf4-32ff21b409fe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951266064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .sram_ctrl_stress_pipeline.951266064 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2061708888 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 2830904550 ps |
CPU time | 7.58 seconds |
Started | Jul 31 07:03:39 PM PDT 24 |
Finished | Jul 31 07:03:46 PM PDT 24 |
Peak memory | 219660 kb |
Host | smart-2e607d18-05a7-4bd4-a220-dfbff218ce35 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061708888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.2061708888 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1533805400 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 9404682185 ps |
CPU time | 74.2 seconds |
Started | Jul 31 06:54:08 PM PDT 24 |
Finished | Jul 31 06:55:22 PM PDT 24 |
Peak memory | 299320 kb |
Host | smart-81ca0f36-4ce1-455c-b562-0d42aa40ffe9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533805400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.1533805400 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.202259445 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 125087153 ps |
CPU time | 0.68 seconds |
Started | Jul 31 06:54:13 PM PDT 24 |
Finished | Jul 31 06:54:14 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-2757fb5b-387a-43bb-ab40-ed8209577e70 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202259445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.202259445 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.148636086 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 17404103070 ps |
CPU time | 1253.99 seconds |
Started | Jul 31 06:54:03 PM PDT 24 |
Finished | Jul 31 07:14:57 PM PDT 24 |
Peak memory | 204108 kb |
Host | smart-2df3d0a8-6530-4362-8c19-2b751f243d59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148636086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.148636086 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.2867824619 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 42743314875 ps |
CPU time | 717.71 seconds |
Started | Jul 31 06:54:09 PM PDT 24 |
Finished | Jul 31 07:06:07 PM PDT 24 |
Peak memory | 355568 kb |
Host | smart-32136110-80ac-445d-8089-188fa31bdf52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867824619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.2867824619 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.3786095427 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 2467309170 ps |
CPU time | 14.32 seconds |
Started | Jul 31 06:54:07 PM PDT 24 |
Finished | Jul 31 06:54:22 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-fe8456cb-f633-4f3d-ad9e-5e71e9e20a7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786095427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.3786095427 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.3074402396 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 784255504 ps |
CPU time | 109.09 seconds |
Started | Jul 31 06:54:09 PM PDT 24 |
Finished | Jul 31 06:55:59 PM PDT 24 |
Peak memory | 351416 kb |
Host | smart-53257578-1de5-4e9b-bf22-6e792dbec22f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074402396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.3074402396 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2995528406 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 4002421507 ps |
CPU time | 68.6 seconds |
Started | Jul 31 06:54:13 PM PDT 24 |
Finished | Jul 31 06:55:22 PM PDT 24 |
Peak memory | 211516 kb |
Host | smart-f5950f01-0365-4bc7-a945-a44def1d3a3e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995528406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.2995528406 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.1755573803 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 11180102344 ps |
CPU time | 290.85 seconds |
Started | Jul 31 06:54:13 PM PDT 24 |
Finished | Jul 31 06:59:04 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-7a28b98a-f703-40fb-b6b2-eee3763ff46d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755573803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.1755573803 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.2749906088 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 74854504392 ps |
CPU time | 921.84 seconds |
Started | Jul 31 06:54:05 PM PDT 24 |
Finished | Jul 31 07:09:27 PM PDT 24 |
Peak memory | 375036 kb |
Host | smart-21bc3039-0223-493e-90b7-3b4a4623275f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749906088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.2749906088 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.3416628589 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 3337727490 ps |
CPU time | 7.72 seconds |
Started | Jul 31 06:54:13 PM PDT 24 |
Finished | Jul 31 06:54:20 PM PDT 24 |
Peak memory | 210280 kb |
Host | smart-af450245-e96d-47c8-9687-3f3ee3dc4904 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416628589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.3416628589 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2648572138 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 10822257264 ps |
CPU time | 250.08 seconds |
Started | Jul 31 06:54:07 PM PDT 24 |
Finished | Jul 31 06:58:17 PM PDT 24 |
Peak memory | 203268 kb |
Host | smart-40dc80a0-e7f7-466c-ba89-01169e17a1d5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648572138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.2648572138 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.797048160 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 676385607 ps |
CPU time | 3.46 seconds |
Started | Jul 31 06:54:08 PM PDT 24 |
Finished | Jul 31 06:54:12 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-dd6828f4-93d6-4112-9d0e-0bc5e9fda80f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797048160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.797048160 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.576801726 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 45472653041 ps |
CPU time | 1850.52 seconds |
Started | Jul 31 06:54:09 PM PDT 24 |
Finished | Jul 31 07:24:59 PM PDT 24 |
Peak memory | 382088 kb |
Host | smart-8c34f3d7-e0fd-45ce-8020-3af18ff7b6d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576801726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.576801726 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.1389217492 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 529772783 ps |
CPU time | 3.33 seconds |
Started | Jul 31 06:54:16 PM PDT 24 |
Finished | Jul 31 06:54:20 PM PDT 24 |
Peak memory | 223036 kb |
Host | smart-f211ceb5-023b-423c-bd07-1618e6b58e06 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389217492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.1389217492 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.707603195 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 1482633319 ps |
CPU time | 12.52 seconds |
Started | Jul 31 06:54:03 PM PDT 24 |
Finished | Jul 31 06:54:15 PM PDT 24 |
Peak memory | 239840 kb |
Host | smart-ea2ffda8-fb5e-4529-ae45-e32872e49671 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707603195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.707603195 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.3231593961 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 87992331583 ps |
CPU time | 7061.65 seconds |
Started | Jul 31 06:54:15 PM PDT 24 |
Finished | Jul 31 08:51:57 PM PDT 24 |
Peak memory | 380188 kb |
Host | smart-7ed44582-71ae-462e-92a4-df4cd23895a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231593961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.3231593961 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1121772023 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1873123646 ps |
CPU time | 49.23 seconds |
Started | Jul 31 06:54:13 PM PDT 24 |
Finished | Jul 31 06:55:03 PM PDT 24 |
Peak memory | 211536 kb |
Host | smart-b6945dd8-b51f-425e-8c71-8275dd037d0d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1121772023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1121772023 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2301423664 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 3605687345 ps |
CPU time | 213.29 seconds |
Started | Jul 31 06:54:03 PM PDT 24 |
Finished | Jul 31 06:57:37 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-8857162f-7330-4b98-8e14-e873878957ce |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301423664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.2301423664 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3891690213 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1394857953 ps |
CPU time | 6.66 seconds |
Started | Jul 31 06:54:08 PM PDT 24 |
Finished | Jul 31 06:54:14 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-92fc242c-e40b-47e6-82b5-235f477c35e2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891690213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3891690213 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3147640020 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 25985483945 ps |
CPU time | 1816.8 seconds |
Started | Jul 31 07:03:48 PM PDT 24 |
Finished | Jul 31 07:34:05 PM PDT 24 |
Peak memory | 378204 kb |
Host | smart-737118bc-5278-4e3b-88b5-48913f00b13d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147640020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.3147640020 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.1069317604 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 38500470 ps |
CPU time | 0.61 seconds |
Started | Jul 31 07:04:01 PM PDT 24 |
Finished | Jul 31 07:04:02 PM PDT 24 |
Peak memory | 202508 kb |
Host | smart-1d1c41d0-530b-4792-ac9f-aedf06b85ba2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069317604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1069317604 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.2596188043 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 96773822024 ps |
CPU time | 1604.63 seconds |
Started | Jul 31 07:03:43 PM PDT 24 |
Finished | Jul 31 07:30:27 PM PDT 24 |
Peak memory | 203376 kb |
Host | smart-306ae3ce-511a-4531-a503-2812e7f3d9f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596188043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .2596188043 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.2809171084 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 3948562765 ps |
CPU time | 395.96 seconds |
Started | Jul 31 07:03:48 PM PDT 24 |
Finished | Jul 31 07:10:24 PM PDT 24 |
Peak memory | 352568 kb |
Host | smart-c66f7ab5-f03e-4992-ad46-7bad59c0cee1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809171084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.2809171084 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.2227792179 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 29869638917 ps |
CPU time | 57.89 seconds |
Started | Jul 31 07:03:48 PM PDT 24 |
Finished | Jul 31 07:04:46 PM PDT 24 |
Peak memory | 215488 kb |
Host | smart-3b6384f3-a39d-46ea-ba4f-b4fb549ecd20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227792179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.2227792179 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.2837614222 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1404961842 ps |
CPU time | 14.91 seconds |
Started | Jul 31 07:03:48 PM PDT 24 |
Finished | Jul 31 07:04:03 PM PDT 24 |
Peak memory | 252080 kb |
Host | smart-3768cd00-501e-46ea-a283-e32682ab9722 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837614222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.2837614222 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3630001919 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 1387581010 ps |
CPU time | 71.4 seconds |
Started | Jul 31 07:03:55 PM PDT 24 |
Finished | Jul 31 07:05:06 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-7ae82472-c3c1-4468-825d-a6e43d50c27d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630001919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.3630001919 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.1165001557 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 37475826713 ps |
CPU time | 182 seconds |
Started | Jul 31 07:03:53 PM PDT 24 |
Finished | Jul 31 07:06:55 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-62e3b668-8627-4f65-857a-136f511633d0 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165001557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.1165001557 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.2098132819 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 19462052785 ps |
CPU time | 1229.11 seconds |
Started | Jul 31 07:03:42 PM PDT 24 |
Finished | Jul 31 07:24:12 PM PDT 24 |
Peak memory | 379168 kb |
Host | smart-f1e493ce-2c50-4c5d-bb33-d56d19592c48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098132819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.2098132819 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.1679627222 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 1665775521 ps |
CPU time | 26.37 seconds |
Started | Jul 31 07:03:47 PM PDT 24 |
Finished | Jul 31 07:04:13 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-8ed9b9b2-9a3c-46e8-a2b4-4d4c64d77848 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679627222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.1679627222 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3503734407 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 9704043562 ps |
CPU time | 255.17 seconds |
Started | Jul 31 07:03:49 PM PDT 24 |
Finished | Jul 31 07:08:04 PM PDT 24 |
Peak memory | 203284 kb |
Host | smart-bfd572bf-79b3-464a-b812-3a7c17567fea |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503734407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.3503734407 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.2663852738 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 2782804195 ps |
CPU time | 3.82 seconds |
Started | Jul 31 07:03:59 PM PDT 24 |
Finished | Jul 31 07:04:02 PM PDT 24 |
Peak memory | 203308 kb |
Host | smart-e8f6b3ab-b1f5-4589-8f2d-aa7f06621f36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663852738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2663852738 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.1535045658 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 21288877840 ps |
CPU time | 661.78 seconds |
Started | Jul 31 07:03:55 PM PDT 24 |
Finished | Jul 31 07:14:57 PM PDT 24 |
Peak memory | 374496 kb |
Host | smart-91791723-98ba-4173-8389-09142bf39810 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535045658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1535045658 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.1036774301 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 1875625084 ps |
CPU time | 128.17 seconds |
Started | Jul 31 07:03:44 PM PDT 24 |
Finished | Jul 31 07:05:52 PM PDT 24 |
Peak memory | 370768 kb |
Host | smart-eace5521-18e5-4ddb-80c8-72bb658ccad5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036774301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1036774301 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.605938426 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 11890947128 ps |
CPU time | 888.99 seconds |
Started | Jul 31 07:03:53 PM PDT 24 |
Finished | Jul 31 07:18:42 PM PDT 24 |
Peak memory | 380144 kb |
Host | smart-ca0a778a-9059-4af3-a5fc-bb76035338e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605938426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_stress_all.605938426 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1003236446 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 926223002 ps |
CPU time | 8.82 seconds |
Started | Jul 31 07:04:00 PM PDT 24 |
Finished | Jul 31 07:04:09 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-106114b5-a75c-4e69-aa67-72c9828f6caa |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1003236446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1003236446 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3512753282 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 12133863905 ps |
CPU time | 170.16 seconds |
Started | Jul 31 07:03:53 PM PDT 24 |
Finished | Jul 31 07:06:43 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-b8f05b43-e1aa-415a-832d-f3798fc758a4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512753282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.3512753282 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.341977275 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 3089495835 ps |
CPU time | 8.72 seconds |
Started | Jul 31 07:03:53 PM PDT 24 |
Finished | Jul 31 07:04:02 PM PDT 24 |
Peak memory | 221464 kb |
Host | smart-528d0f7d-1d87-4189-8887-69a80531e88c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341977275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_throughput_w_partial_write.341977275 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2683659688 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 15851848239 ps |
CPU time | 1368.84 seconds |
Started | Jul 31 07:04:07 PM PDT 24 |
Finished | Jul 31 07:26:56 PM PDT 24 |
Peak memory | 375092 kb |
Host | smart-dfba2578-be5e-4ba7-b52a-9b9154376cfc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683659688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.2683659688 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.268109454 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 26378207 ps |
CPU time | 0.65 seconds |
Started | Jul 31 07:04:13 PM PDT 24 |
Finished | Jul 31 07:04:14 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-8a5da525-3cfd-4e76-bc4b-d2860cff975b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268109454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.268109454 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.1387670533 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 86402894729 ps |
CPU time | 2054.72 seconds |
Started | Jul 31 07:04:01 PM PDT 24 |
Finished | Jul 31 07:38:17 PM PDT 24 |
Peak memory | 203792 kb |
Host | smart-67b54eb7-ccac-49a4-b2fc-95f1bb2f3aec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387670533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .1387670533 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.2244955691 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 13738493660 ps |
CPU time | 896.65 seconds |
Started | Jul 31 07:04:05 PM PDT 24 |
Finished | Jul 31 07:19:02 PM PDT 24 |
Peak memory | 377004 kb |
Host | smart-cbd20038-1e7e-4cf8-982f-26dd7379b3be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244955691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.2244955691 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.1271301221 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 17939567360 ps |
CPU time | 96.59 seconds |
Started | Jul 31 07:04:05 PM PDT 24 |
Finished | Jul 31 07:05:42 PM PDT 24 |
Peak memory | 203276 kb |
Host | smart-39057d65-fd5b-4783-8bfc-cb92e6ffe471 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271301221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.1271301221 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.1707057735 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 756652737 ps |
CPU time | 92.1 seconds |
Started | Jul 31 07:04:00 PM PDT 24 |
Finished | Jul 31 07:05:32 PM PDT 24 |
Peak memory | 352388 kb |
Host | smart-e5817368-7cdd-4e2d-bf98-a962ca8967b9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707057735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.1707057735 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3951461528 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 12145285989 ps |
CPU time | 134.17 seconds |
Started | Jul 31 07:04:12 PM PDT 24 |
Finished | Jul 31 07:06:26 PM PDT 24 |
Peak memory | 211756 kb |
Host | smart-a2e3a7f4-4911-4750-a3f7-9cad20368550 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951461528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.3951461528 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.3860437706 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 15916426319 ps |
CPU time | 273.96 seconds |
Started | Jul 31 07:04:09 PM PDT 24 |
Finished | Jul 31 07:08:43 PM PDT 24 |
Peak memory | 212008 kb |
Host | smart-fedd8183-6964-4539-942a-1c9919b29edb |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860437706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.3860437706 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.2328924719 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 66942182420 ps |
CPU time | 817.73 seconds |
Started | Jul 31 07:04:01 PM PDT 24 |
Finished | Jul 31 07:17:39 PM PDT 24 |
Peak memory | 371040 kb |
Host | smart-1906e7f5-c172-4092-b7d7-042fffca2cd9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328924719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.2328924719 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.687294063 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 935741329 ps |
CPU time | 11.32 seconds |
Started | Jul 31 07:04:04 PM PDT 24 |
Finished | Jul 31 07:04:16 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-49bd92ac-2595-4439-bb02-fac370791167 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687294063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s ram_ctrl_partial_access.687294063 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3249530170 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 7706689613 ps |
CPU time | 201.71 seconds |
Started | Jul 31 07:04:00 PM PDT 24 |
Finished | Jul 31 07:07:22 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-2ec583c8-efa6-4b69-8d91-cb84cb0f153b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249530170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.3249530170 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.2522022856 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 362800895 ps |
CPU time | 3.19 seconds |
Started | Jul 31 07:04:05 PM PDT 24 |
Finished | Jul 31 07:04:09 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-2df4b75f-f124-4d68-9101-032b6823d50f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522022856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2522022856 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.2439794248 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 39069249018 ps |
CPU time | 692.5 seconds |
Started | Jul 31 07:04:06 PM PDT 24 |
Finished | Jul 31 07:15:39 PM PDT 24 |
Peak memory | 382116 kb |
Host | smart-3664b561-fb7f-4e09-a7b5-121318392588 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439794248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2439794248 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.3584676603 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 2582167103 ps |
CPU time | 12.06 seconds |
Started | Jul 31 07:04:00 PM PDT 24 |
Finished | Jul 31 07:04:12 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-64fbd1ed-6549-4aad-9654-e93c7bf64a94 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584676603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3584676603 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.2317632490 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 49688394110 ps |
CPU time | 5065.04 seconds |
Started | Jul 31 07:04:13 PM PDT 24 |
Finished | Jul 31 08:28:38 PM PDT 24 |
Peak memory | 383172 kb |
Host | smart-0f0b4dab-e1f7-4cb1-a1c0-48fa0e09ec5f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317632490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.2317632490 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1938257790 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 5481986668 ps |
CPU time | 52.14 seconds |
Started | Jul 31 07:04:12 PM PDT 24 |
Finished | Jul 31 07:05:04 PM PDT 24 |
Peak memory | 211648 kb |
Host | smart-b3d6465d-bac0-44f0-9245-28626cf0d6d1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1938257790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1938257790 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.606522227 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 2607015596 ps |
CPU time | 218.01 seconds |
Started | Jul 31 07:04:00 PM PDT 24 |
Finished | Jul 31 07:07:39 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-d09b4f5a-ccd1-4fbb-9bb6-db358360cbe5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606522227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sram_ctrl_stress_pipeline.606522227 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3590033029 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 1419483031 ps |
CPU time | 13.19 seconds |
Started | Jul 31 07:04:06 PM PDT 24 |
Finished | Jul 31 07:04:19 PM PDT 24 |
Peak memory | 240200 kb |
Host | smart-b6ae8f18-29b8-4800-9a24-359b5eb3ce49 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590033029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3590033029 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2861629855 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 7159668170 ps |
CPU time | 689.23 seconds |
Started | Jul 31 07:04:23 PM PDT 24 |
Finished | Jul 31 07:15:53 PM PDT 24 |
Peak memory | 370964 kb |
Host | smart-a4b9f7a6-60b5-462f-b82f-53c6f492a833 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861629855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.2861629855 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.182766907 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 12701838 ps |
CPU time | 0.64 seconds |
Started | Jul 31 07:04:27 PM PDT 24 |
Finished | Jul 31 07:04:28 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-0003bf70-5848-4f36-8234-562b9544f2d1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182766907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.182766907 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.682756412 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 52989998783 ps |
CPU time | 501.54 seconds |
Started | Jul 31 07:04:14 PM PDT 24 |
Finished | Jul 31 07:12:35 PM PDT 24 |
Peak memory | 203384 kb |
Host | smart-5ff7e284-4830-4ef2-af2a-9958a62004b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682756412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection. 682756412 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.3137636680 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 54669428561 ps |
CPU time | 840.57 seconds |
Started | Jul 31 07:04:25 PM PDT 24 |
Finished | Jul 31 07:18:25 PM PDT 24 |
Peak memory | 378160 kb |
Host | smart-2cf202f8-fec8-4b84-81db-d0c13be68db0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137636680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.3137636680 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.332693104 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 10726564126 ps |
CPU time | 32.01 seconds |
Started | Jul 31 07:04:19 PM PDT 24 |
Finished | Jul 31 07:04:51 PM PDT 24 |
Peak memory | 211516 kb |
Host | smart-ab2dd53c-a1e6-4d30-b0e5-a47f1edde701 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332693104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esc alation.332693104 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.2546390476 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 727054008 ps |
CPU time | 22.51 seconds |
Started | Jul 31 07:04:20 PM PDT 24 |
Finished | Jul 31 07:04:42 PM PDT 24 |
Peak memory | 270660 kb |
Host | smart-1dc6c0e6-9987-4609-81be-7367775eb666 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546390476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.2546390476 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.590527261 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 10928201344 ps |
CPU time | 75.63 seconds |
Started | Jul 31 07:04:23 PM PDT 24 |
Finished | Jul 31 07:05:39 PM PDT 24 |
Peak memory | 219552 kb |
Host | smart-29f8082f-9b4b-479e-9d46-cb3d5347ffad |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590527261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_mem_partial_access.590527261 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.2287813730 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 30729089982 ps |
CPU time | 328.73 seconds |
Started | Jul 31 07:04:23 PM PDT 24 |
Finished | Jul 31 07:09:52 PM PDT 24 |
Peak memory | 211520 kb |
Host | smart-311f81a2-6439-4327-ba71-960a550eb2ea |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287813730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.2287813730 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.2165871640 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 14661731725 ps |
CPU time | 1110.76 seconds |
Started | Jul 31 07:04:13 PM PDT 24 |
Finished | Jul 31 07:22:44 PM PDT 24 |
Peak memory | 379196 kb |
Host | smart-626d20d3-ffbc-454b-9a0e-f5c27281c0c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165871640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.2165871640 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.2678678136 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 4586245412 ps |
CPU time | 15.26 seconds |
Started | Jul 31 07:04:19 PM PDT 24 |
Finished | Jul 31 07:04:35 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-99371432-2b22-4896-9720-43c049f8fe7e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678678136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.2678678136 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2030577213 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 81489611198 ps |
CPU time | 546.26 seconds |
Started | Jul 31 07:04:19 PM PDT 24 |
Finished | Jul 31 07:13:26 PM PDT 24 |
Peak memory | 203328 kb |
Host | smart-f243d7de-fb17-4331-b3dd-328a4f1535f3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030577213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.2030577213 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.743195206 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 724147573 ps |
CPU time | 3.54 seconds |
Started | Jul 31 07:04:26 PM PDT 24 |
Finished | Jul 31 07:04:30 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-c6a534ff-9f24-465e-9ff2-5e887b09bca8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743195206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.743195206 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.5673078 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 70238814714 ps |
CPU time | 1623.08 seconds |
Started | Jul 31 07:04:24 PM PDT 24 |
Finished | Jul 31 07:31:27 PM PDT 24 |
Peak memory | 382164 kb |
Host | smart-36c8ffd6-0ad6-426e-b6c6-d8812c5f4531 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5673078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.5673078 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.1535971943 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 3133541486 ps |
CPU time | 6.07 seconds |
Started | Jul 31 07:04:13 PM PDT 24 |
Finished | Jul 31 07:04:19 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-a4bd03da-eb5c-4b27-aa49-13aadb55b718 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535971943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1535971943 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.939787138 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 48454198868 ps |
CPU time | 3992.63 seconds |
Started | Jul 31 07:04:24 PM PDT 24 |
Finished | Jul 31 08:10:57 PM PDT 24 |
Peak memory | 383280 kb |
Host | smart-c6dda4c6-1d88-4c8e-8517-5ae85d672d7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939787138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_stress_all.939787138 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1846915201 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 5984668234 ps |
CPU time | 63.4 seconds |
Started | Jul 31 07:04:35 PM PDT 24 |
Finished | Jul 31 07:05:39 PM PDT 24 |
Peak memory | 281980 kb |
Host | smart-eb6a2a9d-519f-4a65-9a3b-cbcd716581b1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1846915201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.1846915201 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.204603386 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 3947213889 ps |
CPU time | 257.06 seconds |
Started | Jul 31 07:04:13 PM PDT 24 |
Finished | Jul 31 07:08:30 PM PDT 24 |
Peak memory | 203268 kb |
Host | smart-a995dec7-4bfb-41b8-a48f-845b2bc8c93c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204603386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_stress_pipeline.204603386 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.32160252 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 7822893560 ps |
CPU time | 116.95 seconds |
Started | Jul 31 07:04:18 PM PDT 24 |
Finished | Jul 31 07:06:15 PM PDT 24 |
Peak memory | 364808 kb |
Host | smart-56c0d5b4-64f7-4f8c-b2d5-4f74b03a063f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32160252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.sram_ctrl_throughput_w_partial_write.32160252 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.1058883099 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 43162821268 ps |
CPU time | 758.07 seconds |
Started | Jul 31 07:04:38 PM PDT 24 |
Finished | Jul 31 07:17:17 PM PDT 24 |
Peak memory | 379168 kb |
Host | smart-1f46154a-c4a0-4bd6-8401-2a867d7ce9cf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058883099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.1058883099 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.780387294 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 23780060 ps |
CPU time | 0.65 seconds |
Started | Jul 31 07:04:42 PM PDT 24 |
Finished | Jul 31 07:04:43 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-44d0fa64-169f-46a2-84b2-a6808b51639f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780387294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.780387294 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.3235941713 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 94319368043 ps |
CPU time | 1822.36 seconds |
Started | Jul 31 07:04:32 PM PDT 24 |
Finished | Jul 31 07:34:54 PM PDT 24 |
Peak memory | 203860 kb |
Host | smart-5a74718d-da1b-4746-beae-2cdcd8a27cd4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235941713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .3235941713 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.2890010340 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 5172930500 ps |
CPU time | 9.59 seconds |
Started | Jul 31 07:04:37 PM PDT 24 |
Finished | Jul 31 07:04:47 PM PDT 24 |
Peak memory | 215576 kb |
Host | smart-8359bce3-5036-4161-84e5-90c22fd1395c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890010340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.2890010340 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.3570867958 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 11211122088 ps |
CPU time | 7.94 seconds |
Started | Jul 31 07:04:31 PM PDT 24 |
Finished | Jul 31 07:04:39 PM PDT 24 |
Peak memory | 219304 kb |
Host | smart-18c44b12-ecf3-4346-9b94-b8dc64cb411f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570867958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.3570867958 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2539496814 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 6912047388 ps |
CPU time | 127.47 seconds |
Started | Jul 31 07:04:38 PM PDT 24 |
Finished | Jul 31 07:06:46 PM PDT 24 |
Peak memory | 211512 kb |
Host | smart-693b0f8a-aef3-45df-b264-4f43a6058781 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539496814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.2539496814 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.717395142 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 10345141800 ps |
CPU time | 172.01 seconds |
Started | Jul 31 07:04:37 PM PDT 24 |
Finished | Jul 31 07:07:30 PM PDT 24 |
Peak memory | 211328 kb |
Host | smart-81a8659b-ef11-44a4-9ace-3ab10fc0da16 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717395142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _mem_walk.717395142 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.4237444334 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 23397552035 ps |
CPU time | 1532.11 seconds |
Started | Jul 31 07:04:32 PM PDT 24 |
Finished | Jul 31 07:30:04 PM PDT 24 |
Peak memory | 379012 kb |
Host | smart-085f39a6-c7cd-4f20-acaf-8eef67f868bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237444334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.4237444334 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.3160461703 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 1584377767 ps |
CPU time | 12.67 seconds |
Started | Jul 31 07:04:31 PM PDT 24 |
Finished | Jul 31 07:04:44 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-f5f54649-5bb2-4be1-9f9e-68614b065d80 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160461703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.3160461703 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.430632795 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 229893540257 ps |
CPU time | 573.14 seconds |
Started | Jul 31 07:04:32 PM PDT 24 |
Finished | Jul 31 07:14:05 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-a1e31535-2650-4470-ba9a-27b40717473f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430632795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 43.sram_ctrl_partial_access_b2b.430632795 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.108235772 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 1611491419 ps |
CPU time | 3.35 seconds |
Started | Jul 31 07:04:43 PM PDT 24 |
Finished | Jul 31 07:04:47 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-12a5434a-0f6c-45b8-a80a-ab7d57f0b2bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108235772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.108235772 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.4098903200 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 25619334985 ps |
CPU time | 1334.19 seconds |
Started | Jul 31 07:04:39 PM PDT 24 |
Finished | Jul 31 07:26:53 PM PDT 24 |
Peak memory | 376028 kb |
Host | smart-c846d26b-5604-4cb4-9bf4-175ba790d29b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098903200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.4098903200 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.2271407980 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 944031180 ps |
CPU time | 13.42 seconds |
Started | Jul 31 07:04:32 PM PDT 24 |
Finished | Jul 31 07:04:45 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-174607da-1e1b-460a-bb0e-c3b6464451e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271407980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2271407980 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.2844414637 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 1222794413556 ps |
CPU time | 7665.34 seconds |
Started | Jul 31 07:04:43 PM PDT 24 |
Finished | Jul 31 09:12:30 PM PDT 24 |
Peak memory | 382536 kb |
Host | smart-d3913f8b-631a-4e2e-bfd8-80db22178eda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844414637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.2844414637 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4240464767 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 1641784240 ps |
CPU time | 47.84 seconds |
Started | Jul 31 07:04:40 PM PDT 24 |
Finished | Jul 31 07:05:28 PM PDT 24 |
Peak memory | 211544 kb |
Host | smart-65ffb074-97fc-4b3b-9ca6-cf30dcf27551 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4240464767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.4240464767 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2235999459 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 8585600332 ps |
CPU time | 150.08 seconds |
Started | Jul 31 07:04:34 PM PDT 24 |
Finished | Jul 31 07:07:04 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-f316066d-31d1-4c86-b8f9-df6e83f2e93d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235999459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.2235999459 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4158771733 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 767803730 ps |
CPU time | 95.54 seconds |
Started | Jul 31 07:04:39 PM PDT 24 |
Finished | Jul 31 07:06:15 PM PDT 24 |
Peak memory | 334016 kb |
Host | smart-daebde6c-f782-40ca-8e36-703373655faf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158771733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.4158771733 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3951841987 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 83816261671 ps |
CPU time | 1231.76 seconds |
Started | Jul 31 07:04:56 PM PDT 24 |
Finished | Jul 31 07:25:28 PM PDT 24 |
Peak memory | 379208 kb |
Host | smart-b0c8d0cf-5790-471f-a1cf-76c569be3826 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951841987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.3951841987 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.886740809 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 19708974 ps |
CPU time | 0.72 seconds |
Started | Jul 31 07:05:03 PM PDT 24 |
Finished | Jul 31 07:05:03 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-3bd4b2af-d153-4b1e-bb61-0315f9522de7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886740809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.886740809 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.2984472400 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 53783500051 ps |
CPU time | 974.84 seconds |
Started | Jul 31 07:04:51 PM PDT 24 |
Finished | Jul 31 07:21:06 PM PDT 24 |
Peak memory | 203556 kb |
Host | smart-2bdb41ac-85f5-4a55-8819-3aafbf6a3182 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984472400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .2984472400 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.805219773 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 16010257314 ps |
CPU time | 531.01 seconds |
Started | Jul 31 07:04:59 PM PDT 24 |
Finished | Jul 31 07:13:50 PM PDT 24 |
Peak memory | 377832 kb |
Host | smart-f44de11b-4ecc-4a5f-bc41-f4a700d44235 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805219773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executabl e.805219773 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.2222224658 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 14377343350 ps |
CPU time | 48.35 seconds |
Started | Jul 31 07:04:57 PM PDT 24 |
Finished | Jul 31 07:05:45 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-3e6b1cb7-d04a-4130-ab61-45da67122e71 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222224658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.2222224658 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.77532251 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 3184465067 ps |
CPU time | 21.3 seconds |
Started | Jul 31 07:04:49 PM PDT 24 |
Finished | Jul 31 07:05:11 PM PDT 24 |
Peak memory | 256828 kb |
Host | smart-1d7bf2ad-bea6-4e7a-a405-77d86d2fe72b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77532251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 44.sram_ctrl_max_throughput.77532251 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.1233385913 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 55347903490 ps |
CPU time | 311.08 seconds |
Started | Jul 31 07:04:57 PM PDT 24 |
Finished | Jul 31 07:10:08 PM PDT 24 |
Peak memory | 211508 kb |
Host | smart-795c8c72-aa4d-47fe-b064-d4e92000bb5d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233385913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1233385913 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.4291994847 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 28898094072 ps |
CPU time | 656.92 seconds |
Started | Jul 31 07:04:53 PM PDT 24 |
Finished | Jul 31 07:15:50 PM PDT 24 |
Peak memory | 376052 kb |
Host | smart-3f11ced2-8811-4768-bc6f-f6620b2efd05 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291994847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.4291994847 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.2879197292 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 2799205127 ps |
CPU time | 11.25 seconds |
Started | Jul 31 07:04:49 PM PDT 24 |
Finished | Jul 31 07:05:00 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-10fe4440-91c9-4a07-bd2d-0463ac07fbe6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879197292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.2879197292 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3042576787 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 31447664530 ps |
CPU time | 499.02 seconds |
Started | Jul 31 07:04:57 PM PDT 24 |
Finished | Jul 31 07:13:16 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-7493ca22-a991-4d6d-bdf3-c89d9dc6b760 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042576787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.3042576787 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.2675237080 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 403001424 ps |
CPU time | 3.39 seconds |
Started | Jul 31 07:05:02 PM PDT 24 |
Finished | Jul 31 07:05:05 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-bb5b5d16-86c0-435f-a268-c054a1f550a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675237080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2675237080 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.3519083886 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 16151150475 ps |
CPU time | 827.53 seconds |
Started | Jul 31 07:04:57 PM PDT 24 |
Finished | Jul 31 07:18:44 PM PDT 24 |
Peak memory | 379096 kb |
Host | smart-cafd2909-ec2f-4a19-8264-b9a8041a1776 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519083886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3519083886 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.4069719972 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 3612717527 ps |
CPU time | 9.04 seconds |
Started | Jul 31 07:04:43 PM PDT 24 |
Finished | Jul 31 07:04:53 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-13a8116d-a9af-4e78-9386-021b9c048974 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069719972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.4069719972 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.3508172724 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 146212190626 ps |
CPU time | 5135.89 seconds |
Started | Jul 31 07:05:08 PM PDT 24 |
Finished | Jul 31 08:30:44 PM PDT 24 |
Peak memory | 381200 kb |
Host | smart-b9bf2a30-e07d-429e-bb84-73f0aa48416f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508172724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.3508172724 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.899881090 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 21919315330 ps |
CPU time | 51.99 seconds |
Started | Jul 31 07:05:02 PM PDT 24 |
Finished | Jul 31 07:05:54 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-7461e0e9-bfb5-4a73-86b1-b70fe481e7fe |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=899881090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.899881090 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.482646238 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 21186399087 ps |
CPU time | 260.79 seconds |
Started | Jul 31 07:04:50 PM PDT 24 |
Finished | Jul 31 07:09:11 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-877bdac4-5bb5-486c-b955-dccbbddb56ce |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482646238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .sram_ctrl_stress_pipeline.482646238 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3951233886 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 3190037078 ps |
CPU time | 113.08 seconds |
Started | Jul 31 07:04:52 PM PDT 24 |
Finished | Jul 31 07:06:45 PM PDT 24 |
Peak memory | 346388 kb |
Host | smart-03babe53-23d8-4cad-a0f7-eaf5664a8f80 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951233886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.3951233886 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2128573591 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 42865016087 ps |
CPU time | 1987.58 seconds |
Started | Jul 31 07:05:08 PM PDT 24 |
Finished | Jul 31 07:38:16 PM PDT 24 |
Peak memory | 379208 kb |
Host | smart-d73c78f4-ff48-465e-86c1-2b8b27ce6591 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128573591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.2128573591 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.2827287949 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 30271299 ps |
CPU time | 0.63 seconds |
Started | Jul 31 07:05:18 PM PDT 24 |
Finished | Jul 31 07:05:19 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-e5295cc0-79ba-46fb-a404-f9f36ca2cb98 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827287949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.2827287949 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.1458630572 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 20688132555 ps |
CPU time | 678.08 seconds |
Started | Jul 31 07:05:03 PM PDT 24 |
Finished | Jul 31 07:16:22 PM PDT 24 |
Peak memory | 204120 kb |
Host | smart-c32d9992-b893-4c24-b37f-88138ac4b9a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458630572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .1458630572 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.4279103352 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 68234289408 ps |
CPU time | 1240.6 seconds |
Started | Jul 31 07:05:09 PM PDT 24 |
Finished | Jul 31 07:25:49 PM PDT 24 |
Peak memory | 380116 kb |
Host | smart-feb2f392-e109-4d66-91ed-2f83af25acab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279103352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.4279103352 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.2946576216 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 3514468920 ps |
CPU time | 5.03 seconds |
Started | Jul 31 07:05:09 PM PDT 24 |
Finished | Jul 31 07:05:14 PM PDT 24 |
Peak memory | 211272 kb |
Host | smart-126c47eb-944b-4042-bc0a-f981f8504a25 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946576216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.2946576216 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.1471999030 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 760032736 ps |
CPU time | 91.84 seconds |
Started | Jul 31 07:05:09 PM PDT 24 |
Finished | Jul 31 07:06:41 PM PDT 24 |
Peak memory | 330596 kb |
Host | smart-f349bf1e-bb20-49bb-93cb-d228f2d2674d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471999030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.1471999030 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3546742938 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 5800662645 ps |
CPU time | 77.19 seconds |
Started | Jul 31 07:05:15 PM PDT 24 |
Finished | Jul 31 07:06:33 PM PDT 24 |
Peak memory | 211476 kb |
Host | smart-b424112f-4271-4de7-a462-d00168c4665b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546742938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.3546742938 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.558624532 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 4963607635 ps |
CPU time | 152.04 seconds |
Started | Jul 31 07:05:16 PM PDT 24 |
Finished | Jul 31 07:07:48 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-0b0b91b1-1c51-4c87-abe9-36a396ef0556 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558624532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl _mem_walk.558624532 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.464051617 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 47479469586 ps |
CPU time | 959.61 seconds |
Started | Jul 31 07:05:02 PM PDT 24 |
Finished | Jul 31 07:21:02 PM PDT 24 |
Peak memory | 379072 kb |
Host | smart-83d00684-817d-4ae9-937e-649039baab72 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464051617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip le_keys.464051617 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.2491976291 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 1431205835 ps |
CPU time | 31.49 seconds |
Started | Jul 31 07:05:09 PM PDT 24 |
Finished | Jul 31 07:05:40 PM PDT 24 |
Peak memory | 285992 kb |
Host | smart-86648ff2-96a4-44cc-9fee-084903b078c4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491976291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.2491976291 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3904406168 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 3470446520 ps |
CPU time | 169.15 seconds |
Started | Jul 31 07:05:11 PM PDT 24 |
Finished | Jul 31 07:08:00 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-0e7bbd87-33a0-4b0b-bf8a-351c47a4030a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904406168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.3904406168 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.1652874387 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 1416476469 ps |
CPU time | 3.12 seconds |
Started | Jul 31 07:05:16 PM PDT 24 |
Finished | Jul 31 07:05:20 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-ad6a3c48-8cb0-46ad-939d-5ccdd22a190e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652874387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1652874387 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.1300455052 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 13782362770 ps |
CPU time | 55.91 seconds |
Started | Jul 31 07:05:15 PM PDT 24 |
Finished | Jul 31 07:06:11 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-d806688b-a1d6-4899-9a07-74f52c21f169 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300455052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1300455052 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.2569247756 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 428708832 ps |
CPU time | 21.68 seconds |
Started | Jul 31 07:05:02 PM PDT 24 |
Finished | Jul 31 07:05:24 PM PDT 24 |
Peak memory | 266576 kb |
Host | smart-cff7d8bb-f4e8-47be-9b6b-62eff7b72fc4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569247756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2569247756 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.1589919347 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 117123593218 ps |
CPU time | 3120.35 seconds |
Started | Jul 31 07:05:15 PM PDT 24 |
Finished | Jul 31 07:57:15 PM PDT 24 |
Peak memory | 376052 kb |
Host | smart-745cbb2a-cffc-409e-b76a-b034a774ac25 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589919347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.1589919347 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1714914768 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 3640833691 ps |
CPU time | 49.85 seconds |
Started | Jul 31 07:05:16 PM PDT 24 |
Finished | Jul 31 07:06:06 PM PDT 24 |
Peak memory | 211492 kb |
Host | smart-dbb13d0e-21c5-40ab-ad34-8601198385aa |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1714914768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1714914768 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3499072315 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 4620510537 ps |
CPU time | 265.82 seconds |
Started | Jul 31 07:05:03 PM PDT 24 |
Finished | Jul 31 07:09:29 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-a8b676d4-5f9b-4868-9b4f-564d31024c6b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499072315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.3499072315 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3334900761 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 2961097113 ps |
CPU time | 43.85 seconds |
Started | Jul 31 07:05:10 PM PDT 24 |
Finished | Jul 31 07:05:54 PM PDT 24 |
Peak memory | 310300 kb |
Host | smart-7af25bcc-528d-47ed-bd30-9272dc9fc913 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334900761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.3334900761 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1965407916 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 10396675092 ps |
CPU time | 449.17 seconds |
Started | Jul 31 07:05:25 PM PDT 24 |
Finished | Jul 31 07:12:55 PM PDT 24 |
Peak memory | 332784 kb |
Host | smart-64b2041d-f203-4891-995e-ddc71c7bc780 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965407916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.1965407916 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.2461091887 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 32290318 ps |
CPU time | 0.63 seconds |
Started | Jul 31 07:05:34 PM PDT 24 |
Finished | Jul 31 07:05:34 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-47037a49-716b-4db3-b8fd-ed69148c5457 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461091887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2461091887 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.2451976081 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 17748501897 ps |
CPU time | 1272.68 seconds |
Started | Jul 31 07:05:16 PM PDT 24 |
Finished | Jul 31 07:26:29 PM PDT 24 |
Peak memory | 204096 kb |
Host | smart-a14eb2c8-52d2-425d-b4a4-34eb36c6c451 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451976081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .2451976081 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.476638215 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 29787490269 ps |
CPU time | 1210.68 seconds |
Started | Jul 31 07:05:26 PM PDT 24 |
Finished | Jul 31 07:25:37 PM PDT 24 |
Peak memory | 380156 kb |
Host | smart-a8a37426-a740-4795-bb99-bd906fadeade |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476638215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executabl e.476638215 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.691290120 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 2202505935 ps |
CPU time | 16.27 seconds |
Started | Jul 31 07:05:25 PM PDT 24 |
Finished | Jul 31 07:05:41 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-b0bb532e-3400-4e90-aa26-682c74e89d50 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691290120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_esc alation.691290120 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.3338728717 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 744681174 ps |
CPU time | 50.07 seconds |
Started | Jul 31 07:05:26 PM PDT 24 |
Finished | Jul 31 07:06:16 PM PDT 24 |
Peak memory | 301324 kb |
Host | smart-b4103b99-73c2-418c-bae9-23947b24413f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338728717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.3338728717 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3201878068 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 20775812802 ps |
CPU time | 153.92 seconds |
Started | Jul 31 07:05:26 PM PDT 24 |
Finished | Jul 31 07:08:00 PM PDT 24 |
Peak memory | 211476 kb |
Host | smart-80ac44e7-2e69-4ac1-9b34-16b979f1a629 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201878068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.3201878068 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.2968433353 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 94548230231 ps |
CPU time | 358.8 seconds |
Started | Jul 31 07:05:25 PM PDT 24 |
Finished | Jul 31 07:11:24 PM PDT 24 |
Peak memory | 211528 kb |
Host | smart-db1ef037-138a-4237-9887-d14bd7c5522f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968433353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.2968433353 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.549122114 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 79038990838 ps |
CPU time | 885.95 seconds |
Started | Jul 31 07:05:16 PM PDT 24 |
Finished | Jul 31 07:20:02 PM PDT 24 |
Peak memory | 379220 kb |
Host | smart-0ce23cf6-0e15-4103-be61-e6e7d1bc383a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549122114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip le_keys.549122114 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.3729656352 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 852234281 ps |
CPU time | 67.99 seconds |
Started | Jul 31 07:05:27 PM PDT 24 |
Finished | Jul 31 07:06:35 PM PDT 24 |
Peak memory | 327020 kb |
Host | smart-c81205ab-c739-4878-bad9-6d5749a80039 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729656352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.3729656352 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1794596474 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 50250489517 ps |
CPU time | 265.07 seconds |
Started | Jul 31 07:05:24 PM PDT 24 |
Finished | Jul 31 07:09:50 PM PDT 24 |
Peak memory | 203268 kb |
Host | smart-c8c96237-85b5-45fe-a2c8-46509623dd43 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794596474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.1794596474 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.3200336101 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 687684917 ps |
CPU time | 3.27 seconds |
Started | Jul 31 07:05:25 PM PDT 24 |
Finished | Jul 31 07:05:28 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-9de63d32-9bd5-4e7c-8333-ee380a3df59d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200336101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3200336101 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.1054399343 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 10006284919 ps |
CPU time | 1125.77 seconds |
Started | Jul 31 07:05:26 PM PDT 24 |
Finished | Jul 31 07:24:12 PM PDT 24 |
Peak memory | 379088 kb |
Host | smart-da29e220-d457-45fd-afb2-03bfed05cf68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054399343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1054399343 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.1499782348 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 3806714820 ps |
CPU time | 36.87 seconds |
Started | Jul 31 07:05:20 PM PDT 24 |
Finished | Jul 31 07:05:57 PM PDT 24 |
Peak memory | 288332 kb |
Host | smart-7085c3d9-0227-4208-9b50-6c5b0262c8b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499782348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1499782348 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1267770157 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 824056957 ps |
CPU time | 20.97 seconds |
Started | Jul 31 07:05:34 PM PDT 24 |
Finished | Jul 31 07:05:55 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-0ba4710c-e8f9-47dc-afb2-29f6b8336465 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1267770157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1267770157 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3026463025 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 81423329877 ps |
CPU time | 251.31 seconds |
Started | Jul 31 07:05:26 PM PDT 24 |
Finished | Jul 31 07:09:38 PM PDT 24 |
Peak memory | 203312 kb |
Host | smart-f1501e2c-64c1-490c-aa2e-999ebd165ba2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026463025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.3026463025 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3470325097 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 1387820433 ps |
CPU time | 6.25 seconds |
Started | Jul 31 07:05:26 PM PDT 24 |
Finished | Jul 31 07:05:32 PM PDT 24 |
Peak memory | 211224 kb |
Host | smart-645824bc-3453-47b0-a1d7-37312e98d3e1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470325097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3470325097 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.92766701 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 82399295931 ps |
CPU time | 712.01 seconds |
Started | Jul 31 07:05:40 PM PDT 24 |
Finished | Jul 31 07:17:32 PM PDT 24 |
Peak memory | 375032 kb |
Host | smart-0cdd892c-6f1a-4039-836f-8c71dc9fa0fa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92766701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.sram_ctrl_access_during_key_req.92766701 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.1477419515 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 23529823 ps |
CPU time | 0.67 seconds |
Started | Jul 31 07:05:47 PM PDT 24 |
Finished | Jul 31 07:05:48 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-316bd68e-e15b-4996-8161-951214d575f1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477419515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1477419515 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.875187769 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 34675555928 ps |
CPU time | 2248.92 seconds |
Started | Jul 31 07:05:36 PM PDT 24 |
Finished | Jul 31 07:43:05 PM PDT 24 |
Peak memory | 204136 kb |
Host | smart-065ae62e-bd0b-4570-90d5-895c9e542b21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875187769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection. 875187769 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.1573546688 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 194073399320 ps |
CPU time | 824.04 seconds |
Started | Jul 31 07:05:41 PM PDT 24 |
Finished | Jul 31 07:19:25 PM PDT 24 |
Peak memory | 372944 kb |
Host | smart-8b6cb38a-10a2-43d0-a158-8c43e7d01b65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573546688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.1573546688 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.1515314828 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 41991484708 ps |
CPU time | 35.79 seconds |
Started | Jul 31 07:05:40 PM PDT 24 |
Finished | Jul 31 07:06:16 PM PDT 24 |
Peak memory | 215440 kb |
Host | smart-7f53203c-8a2d-4e37-8c0e-db94d42bfc4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515314828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.1515314828 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.3731667899 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 965093554 ps |
CPU time | 96.14 seconds |
Started | Jul 31 07:05:42 PM PDT 24 |
Finished | Jul 31 07:07:18 PM PDT 24 |
Peak memory | 362604 kb |
Host | smart-74ba136f-0024-4847-9f06-197721c319c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731667899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.3731667899 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.395829015 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 1387933985 ps |
CPU time | 72.89 seconds |
Started | Jul 31 07:05:47 PM PDT 24 |
Finished | Jul 31 07:07:00 PM PDT 24 |
Peak memory | 211328 kb |
Host | smart-e21225ce-3eed-4ec2-8483-0adfcda13693 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395829015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_mem_partial_access.395829015 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.4139878079 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 39039387748 ps |
CPU time | 352.44 seconds |
Started | Jul 31 07:05:41 PM PDT 24 |
Finished | Jul 31 07:11:33 PM PDT 24 |
Peak memory | 212372 kb |
Host | smart-6f1d7f8d-3b8b-430a-8787-7ef54bd7e4d4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139878079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.4139878079 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.2251269417 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 30983494322 ps |
CPU time | 2519.52 seconds |
Started | Jul 31 07:05:35 PM PDT 24 |
Finished | Jul 31 07:47:35 PM PDT 24 |
Peak memory | 379104 kb |
Host | smart-cd5f9244-d8bc-41d6-8922-eb1d2da1366b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251269417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.2251269417 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.1097097274 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 5111877825 ps |
CPU time | 18.59 seconds |
Started | Jul 31 07:05:37 PM PDT 24 |
Finished | Jul 31 07:05:55 PM PDT 24 |
Peak memory | 203292 kb |
Host | smart-c49b2a99-77b8-4b64-b231-f90e141e210d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097097274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.1097097274 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2077729014 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 14633895942 ps |
CPU time | 363.63 seconds |
Started | Jul 31 07:05:37 PM PDT 24 |
Finished | Jul 31 07:11:41 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-a25e9114-e1d6-485e-8029-c229c2592b67 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077729014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.2077729014 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.1975282512 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 2237234621 ps |
CPU time | 3.46 seconds |
Started | Jul 31 07:05:41 PM PDT 24 |
Finished | Jul 31 07:05:44 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-29978015-0c99-4d01-9bc3-1f36be0815b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975282512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1975282512 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.4144099969 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 124900597858 ps |
CPU time | 1331.6 seconds |
Started | Jul 31 07:05:41 PM PDT 24 |
Finished | Jul 31 07:27:53 PM PDT 24 |
Peak memory | 380252 kb |
Host | smart-5ab06cd6-1187-443f-bd0c-aa9e0206dd9c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144099969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.4144099969 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.854817080 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 1965218031 ps |
CPU time | 11.44 seconds |
Started | Jul 31 07:05:34 PM PDT 24 |
Finished | Jul 31 07:05:45 PM PDT 24 |
Peak memory | 233396 kb |
Host | smart-675a67ef-319c-4c0d-92d4-278cf6749db7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854817080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.854817080 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.809091738 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 212793382242 ps |
CPU time | 2774.21 seconds |
Started | Jul 31 07:05:46 PM PDT 24 |
Finished | Jul 31 07:52:01 PM PDT 24 |
Peak memory | 388384 kb |
Host | smart-16620cd3-1562-4cb3-be6c-2a9144b69d7a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809091738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_stress_all.809091738 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1610484869 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 2736384179 ps |
CPU time | 27.15 seconds |
Started | Jul 31 07:05:45 PM PDT 24 |
Finished | Jul 31 07:06:13 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-36713af4-886c-45bd-bc00-529e9eb28269 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1610484869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1610484869 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3387306312 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 22239179815 ps |
CPU time | 237.62 seconds |
Started | Jul 31 07:05:34 PM PDT 24 |
Finished | Jul 31 07:09:32 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-9ea5732f-2959-4b6d-96dc-ee1f192645b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387306312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.3387306312 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1272125319 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 2933623403 ps |
CPU time | 32.89 seconds |
Started | Jul 31 07:05:39 PM PDT 24 |
Finished | Jul 31 07:06:12 PM PDT 24 |
Peak memory | 294756 kb |
Host | smart-edea61ad-7675-4ab6-b898-d3ba1a38f743 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272125319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1272125319 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2708225202 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 46644236230 ps |
CPU time | 632.46 seconds |
Started | Jul 31 07:05:52 PM PDT 24 |
Finished | Jul 31 07:16:25 PM PDT 24 |
Peak memory | 362656 kb |
Host | smart-10ee1a69-6a5d-4ad2-b883-6350f7b9eacb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708225202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.2708225202 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.12135563 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 17796920 ps |
CPU time | 0.63 seconds |
Started | Jul 31 07:06:04 PM PDT 24 |
Finished | Jul 31 07:06:05 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-4c4b6bb4-4303-48d7-92ab-8bf763d989ac |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12135563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_alert_test.12135563 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.2638843900 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 144798362169 ps |
CPU time | 585.98 seconds |
Started | Jul 31 07:05:48 PM PDT 24 |
Finished | Jul 31 07:15:34 PM PDT 24 |
Peak memory | 203340 kb |
Host | smart-ab8b1d16-d510-4fd8-9c6e-dc186581aada |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638843900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .2638843900 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.4091084333 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 20639040627 ps |
CPU time | 899.04 seconds |
Started | Jul 31 07:05:53 PM PDT 24 |
Finished | Jul 31 07:20:52 PM PDT 24 |
Peak memory | 376044 kb |
Host | smart-3b82cd67-bdfc-4af3-9f73-6fcbccb9bb55 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091084333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.4091084333 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.2752041836 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 9370335552 ps |
CPU time | 15.72 seconds |
Started | Jul 31 07:05:55 PM PDT 24 |
Finished | Jul 31 07:06:11 PM PDT 24 |
Peak memory | 214844 kb |
Host | smart-806f72de-c493-426f-b417-acda4c3b8fff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752041836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.2752041836 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.3329064321 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 3108168500 ps |
CPU time | 85.29 seconds |
Started | Jul 31 07:05:55 PM PDT 24 |
Finished | Jul 31 07:07:20 PM PDT 24 |
Peak memory | 340256 kb |
Host | smart-15125a4b-bceb-423d-86ce-ded10f4635d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329064321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.3329064321 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4177776312 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 12794371241 ps |
CPU time | 78.19 seconds |
Started | Jul 31 07:05:59 PM PDT 24 |
Finished | Jul 31 07:07:17 PM PDT 24 |
Peak memory | 211368 kb |
Host | smart-5a9d1bf9-116b-4673-afb8-6a628cdb651b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177776312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.4177776312 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.338447012 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 90001431535 ps |
CPU time | 357.92 seconds |
Started | Jul 31 07:05:59 PM PDT 24 |
Finished | Jul 31 07:11:57 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-5f3a781b-2e22-4745-b2ba-7babef0768fa |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338447012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl _mem_walk.338447012 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.262819146 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 42160006891 ps |
CPU time | 1369.78 seconds |
Started | Jul 31 07:05:46 PM PDT 24 |
Finished | Jul 31 07:28:36 PM PDT 24 |
Peak memory | 380076 kb |
Host | smart-85c9dd00-c747-4def-b91d-6b4871792bda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262819146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip le_keys.262819146 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.48611477 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 800943723 ps |
CPU time | 6.19 seconds |
Started | Jul 31 07:05:45 PM PDT 24 |
Finished | Jul 31 07:05:52 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-566f606b-b5ee-40bf-9dc8-1eae1c7dc2b8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48611477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sr am_ctrl_partial_access.48611477 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2667259721 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 16445014762 ps |
CPU time | 345.56 seconds |
Started | Jul 31 07:05:48 PM PDT 24 |
Finished | Jul 31 07:11:33 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-ddcd263f-0315-49d5-8eda-d3390e350d6c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667259721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.2667259721 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.2400617310 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 1687892571 ps |
CPU time | 3.42 seconds |
Started | Jul 31 07:05:56 PM PDT 24 |
Finished | Jul 31 07:05:59 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-18466cb6-37fa-4def-94eb-4af3bf95e196 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400617310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2400617310 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.1193131001 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 57491771401 ps |
CPU time | 1252.91 seconds |
Started | Jul 31 07:05:55 PM PDT 24 |
Finished | Jul 31 07:26:49 PM PDT 24 |
Peak memory | 381192 kb |
Host | smart-766b52a1-eefb-44f1-a693-6e236b2dd165 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193131001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1193131001 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.1387459691 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 700879447 ps |
CPU time | 5.7 seconds |
Started | Jul 31 07:05:45 PM PDT 24 |
Finished | Jul 31 07:05:51 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-3664ad3c-c769-431e-b3b5-a99b7f568584 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387459691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1387459691 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.3670004657 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 440765973949 ps |
CPU time | 7446.12 seconds |
Started | Jul 31 07:05:58 PM PDT 24 |
Finished | Jul 31 09:10:05 PM PDT 24 |
Peak memory | 383152 kb |
Host | smart-d492b05a-59e4-46fe-a47a-85b3a96a089c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670004657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.3670004657 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3496586367 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 7749458006 ps |
CPU time | 77.9 seconds |
Started | Jul 31 07:05:59 PM PDT 24 |
Finished | Jul 31 07:07:17 PM PDT 24 |
Peak memory | 211552 kb |
Host | smart-7382a441-c048-48b1-bf0f-a0d96684e105 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3496586367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3496586367 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1288404400 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 3115778466 ps |
CPU time | 177.61 seconds |
Started | Jul 31 07:05:46 PM PDT 24 |
Finished | Jul 31 07:08:44 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-9c04752e-a700-4cd4-8111-167d31eb9f87 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288404400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.1288404400 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3740529975 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 817930958 ps |
CPU time | 87.74 seconds |
Started | Jul 31 07:05:52 PM PDT 24 |
Finished | Jul 31 07:07:20 PM PDT 24 |
Peak memory | 368704 kb |
Host | smart-2078bcfd-d401-48c0-8c4e-aafb7465265d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740529975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3740529975 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2737087255 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 23292981750 ps |
CPU time | 683.41 seconds |
Started | Jul 31 07:06:16 PM PDT 24 |
Finished | Jul 31 07:17:39 PM PDT 24 |
Peak memory | 377100 kb |
Host | smart-2795520d-c11f-44d8-a19a-fafd4031e925 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737087255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.2737087255 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.548142479 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 31662064 ps |
CPU time | 0.62 seconds |
Started | Jul 31 07:06:28 PM PDT 24 |
Finished | Jul 31 07:06:29 PM PDT 24 |
Peak memory | 202456 kb |
Host | smart-e7a64031-16df-4ac6-8429-edb51175a2a3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548142479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.548142479 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.2431781053 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 111686092922 ps |
CPU time | 619.83 seconds |
Started | Jul 31 07:06:05 PM PDT 24 |
Finished | Jul 31 07:16:25 PM PDT 24 |
Peak memory | 203308 kb |
Host | smart-a413a8c6-79c8-4897-b274-96f6853146f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431781053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .2431781053 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.1596165329 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 4938439104 ps |
CPU time | 319.08 seconds |
Started | Jul 31 07:06:18 PM PDT 24 |
Finished | Jul 31 07:11:37 PM PDT 24 |
Peak memory | 359600 kb |
Host | smart-4e9ce324-11a4-443e-9d83-8756ca356bca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596165329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.1596165329 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.1696231631 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 14219373754 ps |
CPU time | 82.11 seconds |
Started | Jul 31 07:06:10 PM PDT 24 |
Finished | Jul 31 07:07:32 PM PDT 24 |
Peak memory | 216516 kb |
Host | smart-8405ad18-db64-432f-90dc-db76587e296d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696231631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.1696231631 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.217007000 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 728946025 ps |
CPU time | 14.71 seconds |
Started | Jul 31 07:06:10 PM PDT 24 |
Finished | Jul 31 07:06:25 PM PDT 24 |
Peak memory | 252332 kb |
Host | smart-b029d9cf-d1a0-4813-8296-5e2c274fc3c8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217007000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.sram_ctrl_max_throughput.217007000 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1306695605 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 10108215377 ps |
CPU time | 81.9 seconds |
Started | Jul 31 07:06:17 PM PDT 24 |
Finished | Jul 31 07:07:39 PM PDT 24 |
Peak memory | 211484 kb |
Host | smart-c0847a81-b8a0-46a6-9ef9-9519ae35e2a7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306695605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.1306695605 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.1866325018 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 2634740057 ps |
CPU time | 152.89 seconds |
Started | Jul 31 07:06:18 PM PDT 24 |
Finished | Jul 31 07:08:51 PM PDT 24 |
Peak memory | 212292 kb |
Host | smart-6d10c020-c8cc-4684-b8ed-bd81e074baab |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866325018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.1866325018 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.3664130830 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 19266649184 ps |
CPU time | 455.85 seconds |
Started | Jul 31 07:06:04 PM PDT 24 |
Finished | Jul 31 07:13:40 PM PDT 24 |
Peak memory | 364748 kb |
Host | smart-ca761310-c464-45ed-9cfa-394de1faa75f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664130830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.3664130830 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.318223930 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 964171788 ps |
CPU time | 11.01 seconds |
Started | Jul 31 07:06:04 PM PDT 24 |
Finished | Jul 31 07:06:15 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-457ef870-ec9a-47af-9b44-4ec7aa1033ae |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318223930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.s ram_ctrl_partial_access.318223930 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.811886884 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 147453647795 ps |
CPU time | 452.56 seconds |
Started | Jul 31 07:06:11 PM PDT 24 |
Finished | Jul 31 07:13:43 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-53396094-ec7c-4cbd-bf3a-a8fb7f6d1e1a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811886884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.sram_ctrl_partial_access_b2b.811886884 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.2340105677 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 357489424 ps |
CPU time | 3.47 seconds |
Started | Jul 31 07:06:16 PM PDT 24 |
Finished | Jul 31 07:06:20 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-ea8632b9-2120-4dc8-a913-8be2d70c1cf3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340105677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.2340105677 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.3960839260 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 70804129101 ps |
CPU time | 1102.55 seconds |
Started | Jul 31 07:06:16 PM PDT 24 |
Finished | Jul 31 07:24:38 PM PDT 24 |
Peak memory | 381128 kb |
Host | smart-c526f21b-1833-4618-8015-b2d664671e45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960839260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3960839260 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.4079523178 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 8292985121 ps |
CPU time | 14.25 seconds |
Started | Jul 31 07:06:05 PM PDT 24 |
Finished | Jul 31 07:06:19 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-ff7f9403-212d-47a0-b97c-3298ae7b2073 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079523178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.4079523178 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.570444299 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 748293369378 ps |
CPU time | 5052.65 seconds |
Started | Jul 31 07:06:22 PM PDT 24 |
Finished | Jul 31 08:30:36 PM PDT 24 |
Peak memory | 380140 kb |
Host | smart-2b7cf28b-63f0-470f-a37c-ca36db45e602 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570444299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_stress_all.570444299 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3989031035 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 361463460 ps |
CPU time | 10.34 seconds |
Started | Jul 31 07:06:22 PM PDT 24 |
Finished | Jul 31 07:06:33 PM PDT 24 |
Peak memory | 211500 kb |
Host | smart-6763af12-53b2-4b5e-8008-47a7ce8e6b37 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3989031035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3989031035 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2060351739 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 17674210995 ps |
CPU time | 272.99 seconds |
Started | Jul 31 07:06:04 PM PDT 24 |
Finished | Jul 31 07:10:37 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-2cd2ea69-8164-417c-8d95-0cd7a5121e73 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060351739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.2060351739 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1960699334 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 5211423240 ps |
CPU time | 144.34 seconds |
Started | Jul 31 07:06:08 PM PDT 24 |
Finished | Jul 31 07:08:33 PM PDT 24 |
Peak memory | 371488 kb |
Host | smart-a8619e8f-6054-411f-8d96-a5001da22f24 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960699334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1960699334 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2028396621 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 9905339820 ps |
CPU time | 177.46 seconds |
Started | Jul 31 06:54:26 PM PDT 24 |
Finished | Jul 31 06:57:24 PM PDT 24 |
Peak memory | 350676 kb |
Host | smart-5c36ffb6-21a9-452f-add1-8046ac81f288 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028396621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.2028396621 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.3240752513 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 36768436 ps |
CPU time | 0.64 seconds |
Started | Jul 31 06:54:32 PM PDT 24 |
Finished | Jul 31 06:54:33 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-21857444-a1c9-4603-8465-4f308364d508 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240752513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3240752513 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.1528237297 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 93648462332 ps |
CPU time | 1711.97 seconds |
Started | Jul 31 06:54:12 PM PDT 24 |
Finished | Jul 31 07:22:44 PM PDT 24 |
Peak memory | 203816 kb |
Host | smart-ef250920-4cf8-4342-a99e-7a082edbd283 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528237297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 1528237297 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.2828108196 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 103431731382 ps |
CPU time | 477.43 seconds |
Started | Jul 31 06:54:27 PM PDT 24 |
Finished | Jul 31 07:02:25 PM PDT 24 |
Peak memory | 372912 kb |
Host | smart-038b8d22-3d17-4bae-ab01-b2af16162f47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828108196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.2828108196 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.4101429359 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 16304871497 ps |
CPU time | 28.31 seconds |
Started | Jul 31 06:54:29 PM PDT 24 |
Finished | Jul 31 06:54:57 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-0c406e34-4096-45aa-a38c-e1d2fa9d4752 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101429359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.4101429359 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.2002773302 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 702722433 ps |
CPU time | 7 seconds |
Started | Jul 31 06:54:25 PM PDT 24 |
Finished | Jul 31 06:54:32 PM PDT 24 |
Peak memory | 212440 kb |
Host | smart-6297b766-06cb-4ddd-bf97-333a85abbc9d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002773302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.2002773302 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2008930449 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 4974961663 ps |
CPU time | 155.96 seconds |
Started | Jul 31 06:54:26 PM PDT 24 |
Finished | Jul 31 06:57:02 PM PDT 24 |
Peak memory | 211488 kb |
Host | smart-9d84f769-85f3-4ab3-904d-f3f68e8d309d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008930449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.2008930449 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.1880191845 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 12714461046 ps |
CPU time | 255.05 seconds |
Started | Jul 31 06:54:25 PM PDT 24 |
Finished | Jul 31 06:58:40 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-2d5ee270-08c1-4057-8902-d3422d7253f4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880191845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.1880191845 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.969743199 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 17825087418 ps |
CPU time | 929.47 seconds |
Started | Jul 31 06:54:13 PM PDT 24 |
Finished | Jul 31 07:09:43 PM PDT 24 |
Peak memory | 380224 kb |
Host | smart-9a4d14e1-cc79-4be2-b9bb-73f37aae223a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969743199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multipl e_keys.969743199 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.1739259598 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 563782006 ps |
CPU time | 14.2 seconds |
Started | Jul 31 06:54:19 PM PDT 24 |
Finished | Jul 31 06:54:33 PM PDT 24 |
Peak memory | 242756 kb |
Host | smart-ff4ca195-75c4-4c91-a022-af8fa90755e2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739259598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.1739259598 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3949588430 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 14351123463 ps |
CPU time | 149.03 seconds |
Started | Jul 31 06:54:20 PM PDT 24 |
Finished | Jul 31 06:56:49 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-6b1d61c2-6ca4-49ca-99b8-1f9308af35a3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949588430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.3949588430 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.4114930026 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 1294747069 ps |
CPU time | 3.6 seconds |
Started | Jul 31 06:54:25 PM PDT 24 |
Finished | Jul 31 06:54:29 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-7cc9ead5-9c60-4238-8aa2-683c6607337d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114930026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.4114930026 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.2080615228 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 14729599858 ps |
CPU time | 1084 seconds |
Started | Jul 31 06:54:25 PM PDT 24 |
Finished | Jul 31 07:12:29 PM PDT 24 |
Peak memory | 375928 kb |
Host | smart-f8e9b398-ebdf-4694-98ed-7d2a47b55956 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080615228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2080615228 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.4026361753 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 475473668 ps |
CPU time | 6.37 seconds |
Started | Jul 31 06:54:14 PM PDT 24 |
Finished | Jul 31 06:54:20 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-79c5029a-3b0f-43b1-9e18-13894a8a4163 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026361753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.4026361753 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.1475988241 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 264123550238 ps |
CPU time | 2809.28 seconds |
Started | Jul 31 06:54:32 PM PDT 24 |
Finished | Jul 31 07:41:22 PM PDT 24 |
Peak memory | 382400 kb |
Host | smart-d467c40e-1c5a-4508-a071-e95a8425b01b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475988241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.1475988241 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1228457181 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 734667732 ps |
CPU time | 10.84 seconds |
Started | Jul 31 06:54:25 PM PDT 24 |
Finished | Jul 31 06:54:36 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-7d6d10e9-3eff-4c35-bdf0-d76f05d9c753 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1228457181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1228457181 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2795335619 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 14108502781 ps |
CPU time | 225.88 seconds |
Started | Jul 31 06:54:14 PM PDT 24 |
Finished | Jul 31 06:58:00 PM PDT 24 |
Peak memory | 203288 kb |
Host | smart-70d3c4e2-39e3-4ce1-a9b1-d79091e838c8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795335619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.2795335619 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1151854437 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 2954200557 ps |
CPU time | 39.47 seconds |
Started | Jul 31 06:54:26 PM PDT 24 |
Finished | Jul 31 06:55:05 PM PDT 24 |
Peak memory | 301368 kb |
Host | smart-f87508ed-833c-4250-8657-99172d3a1a79 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151854437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1151854437 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1627334364 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 40883497072 ps |
CPU time | 2197.86 seconds |
Started | Jul 31 06:54:38 PM PDT 24 |
Finished | Jul 31 07:31:16 PM PDT 24 |
Peak memory | 380172 kb |
Host | smart-ebb21b6e-67ca-42f6-9889-a2cc16bf88b2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627334364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.1627334364 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.3141109023 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 175592172 ps |
CPU time | 0.65 seconds |
Started | Jul 31 06:54:43 PM PDT 24 |
Finished | Jul 31 06:54:44 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-e7143e2c-5817-42a8-9c22-44416aaa57f2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141109023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3141109023 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.246247194 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 782368702557 ps |
CPU time | 2005.28 seconds |
Started | Jul 31 06:54:34 PM PDT 24 |
Finished | Jul 31 07:27:59 PM PDT 24 |
Peak memory | 203924 kb |
Host | smart-8e32c5c7-6f29-4fc4-b816-eb22433c52b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246247194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.246247194 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.1841611009 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 43113026718 ps |
CPU time | 721.64 seconds |
Started | Jul 31 06:54:39 PM PDT 24 |
Finished | Jul 31 07:06:40 PM PDT 24 |
Peak memory | 377064 kb |
Host | smart-2d69eb42-2a1a-4c50-a4db-b89c162a2c9d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841611009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.1841611009 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.1050726781 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 7131258802 ps |
CPU time | 45.37 seconds |
Started | Jul 31 06:54:39 PM PDT 24 |
Finished | Jul 31 06:55:25 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-81a1e704-5204-419a-b8b6-a4a6917ad698 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050726781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.1050726781 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.4202645365 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 676910940 ps |
CPU time | 6.4 seconds |
Started | Jul 31 06:54:38 PM PDT 24 |
Finished | Jul 31 06:54:45 PM PDT 24 |
Peak memory | 211332 kb |
Host | smart-a52b92ab-7095-4482-bb82-52419a5e7517 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202645365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.4202645365 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.4077480858 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 15251933541 ps |
CPU time | 166.93 seconds |
Started | Jul 31 06:54:44 PM PDT 24 |
Finished | Jul 31 06:57:31 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-95fc2934-ea35-4d48-a8c4-4b52d401a159 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077480858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.4077480858 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.2560916612 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 14408027033 ps |
CPU time | 316.82 seconds |
Started | Jul 31 06:54:37 PM PDT 24 |
Finished | Jul 31 06:59:54 PM PDT 24 |
Peak memory | 211408 kb |
Host | smart-7e02a086-7940-409e-ac77-9e8c7a54d36e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560916612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.2560916612 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.1743163306 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 24360064655 ps |
CPU time | 1254.49 seconds |
Started | Jul 31 06:54:31 PM PDT 24 |
Finished | Jul 31 07:15:26 PM PDT 24 |
Peak memory | 379028 kb |
Host | smart-db25c618-0fc1-4f8e-b563-31d2fc8c00d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743163306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.1743163306 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.974796721 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 2532882741 ps |
CPU time | 108.3 seconds |
Started | Jul 31 06:54:39 PM PDT 24 |
Finished | Jul 31 06:56:27 PM PDT 24 |
Peak memory | 351436 kb |
Host | smart-8244e11a-24bd-45db-a4ff-d392d5ddd3f2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974796721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr am_ctrl_partial_access.974796721 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.354343002 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 19636590241 ps |
CPU time | 272.1 seconds |
Started | Jul 31 06:54:39 PM PDT 24 |
Finished | Jul 31 06:59:11 PM PDT 24 |
Peak memory | 203288 kb |
Host | smart-2c93afd2-522c-478f-b28e-40e957ba9e8d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354343002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.sram_ctrl_partial_access_b2b.354343002 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.1353966127 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 1973559980 ps |
CPU time | 3.58 seconds |
Started | Jul 31 06:54:40 PM PDT 24 |
Finished | Jul 31 06:54:43 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-148cfa28-3e0e-423d-af91-14376630978c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353966127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1353966127 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.3391248483 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 89379713853 ps |
CPU time | 1107.47 seconds |
Started | Jul 31 06:54:38 PM PDT 24 |
Finished | Jul 31 07:13:06 PM PDT 24 |
Peak memory | 374008 kb |
Host | smart-470e1987-12e1-4616-82a7-e446f0cbc708 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391248483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3391248483 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.3057175111 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 4989696306 ps |
CPU time | 112.25 seconds |
Started | Jul 31 06:54:32 PM PDT 24 |
Finished | Jul 31 06:56:24 PM PDT 24 |
Peak memory | 364768 kb |
Host | smart-efdc2f52-f429-4429-b222-d6c598853cc9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057175111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3057175111 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.2827919913 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 44654432145 ps |
CPU time | 1880.97 seconds |
Started | Jul 31 06:54:45 PM PDT 24 |
Finished | Jul 31 07:26:06 PM PDT 24 |
Peak memory | 389460 kb |
Host | smart-e2e4814e-4f37-43dc-8b3b-57eea244703f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827919913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.2827919913 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3219727858 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 1600917098 ps |
CPU time | 29.41 seconds |
Started | Jul 31 06:54:43 PM PDT 24 |
Finished | Jul 31 06:55:13 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-b17cf912-b910-44d0-bcda-5bdbe09c419a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3219727858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3219727858 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2967535300 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 2838914374 ps |
CPU time | 147.92 seconds |
Started | Jul 31 06:54:37 PM PDT 24 |
Finished | Jul 31 06:57:05 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-7b8a8446-8dc8-41ad-9f35-1625ee14d68b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967535300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.2967535300 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1496254030 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 710177794 ps |
CPU time | 16.27 seconds |
Started | Jul 31 06:54:40 PM PDT 24 |
Finished | Jul 31 06:54:56 PM PDT 24 |
Peak memory | 252120 kb |
Host | smart-80fbf25c-69b6-40cf-8d3b-1584fa23e977 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496254030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.1496254030 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2454092499 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 24083730754 ps |
CPU time | 103.93 seconds |
Started | Jul 31 06:54:50 PM PDT 24 |
Finished | Jul 31 06:56:34 PM PDT 24 |
Peak memory | 343292 kb |
Host | smart-51a02cdb-a99a-422c-a40d-baea65ab4c91 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454092499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.2454092499 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.2958893058 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 93245861 ps |
CPU time | 0.68 seconds |
Started | Jul 31 06:54:56 PM PDT 24 |
Finished | Jul 31 06:54:57 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-e6fcab22-ae29-4e8d-ab1a-34e33901f4c5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958893058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.2958893058 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.118226011 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 132690641359 ps |
CPU time | 2403.5 seconds |
Started | Jul 31 06:54:43 PM PDT 24 |
Finished | Jul 31 07:34:47 PM PDT 24 |
Peak memory | 203916 kb |
Host | smart-40322288-e109-4338-8af1-107a325e89c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118226011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.118226011 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.3962995363 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 13066924548 ps |
CPU time | 591.28 seconds |
Started | Jul 31 06:54:48 PM PDT 24 |
Finished | Jul 31 07:04:40 PM PDT 24 |
Peak memory | 375908 kb |
Host | smart-333e4eff-fcd4-4dff-8d8b-67fe6a7106dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962995363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.3962995363 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.1504177408 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 28774228994 ps |
CPU time | 44.69 seconds |
Started | Jul 31 06:54:49 PM PDT 24 |
Finished | Jul 31 06:55:33 PM PDT 24 |
Peak memory | 215048 kb |
Host | smart-536cd523-77fc-45f3-9136-d7c413b5ca6d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504177408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.1504177408 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.4212871570 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 803780915 ps |
CPU time | 53.64 seconds |
Started | Jul 31 06:54:49 PM PDT 24 |
Finished | Jul 31 06:55:43 PM PDT 24 |
Peak memory | 333408 kb |
Host | smart-9960cbc0-3fdc-4207-828b-2e49472e1f65 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212871570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.4212871570 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1760384592 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 9153252562 ps |
CPU time | 148.04 seconds |
Started | Jul 31 06:54:49 PM PDT 24 |
Finished | Jul 31 06:57:18 PM PDT 24 |
Peak memory | 211504 kb |
Host | smart-d492cab5-c5a6-4316-a351-be060f35a541 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760384592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.1760384592 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.1753966722 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 8568009125 ps |
CPU time | 241.55 seconds |
Started | Jul 31 06:54:51 PM PDT 24 |
Finished | Jul 31 06:58:53 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-87d08dd4-1ddc-4ca4-bf04-3bd7929b5c0f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753966722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.1753966722 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.2762488914 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 18281450846 ps |
CPU time | 1253.28 seconds |
Started | Jul 31 06:54:45 PM PDT 24 |
Finished | Jul 31 07:15:39 PM PDT 24 |
Peak memory | 381232 kb |
Host | smart-8f3485fc-6e63-48b3-8ea7-e12ef4a616ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762488914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.2762488914 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.574750045 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 1421387541 ps |
CPU time | 22.18 seconds |
Started | Jul 31 06:54:48 PM PDT 24 |
Finished | Jul 31 06:55:10 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-666cce3c-881f-48fc-be54-c7c078a8d73e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574750045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sr am_ctrl_partial_access.574750045 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3125218127 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 17820310080 ps |
CPU time | 417.83 seconds |
Started | Jul 31 06:54:48 PM PDT 24 |
Finished | Jul 31 07:01:46 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-f698ba39-2eb1-4c90-baea-9ad596812b94 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125218127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.3125218127 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.3524793563 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 1342721329 ps |
CPU time | 3.13 seconds |
Started | Jul 31 06:54:50 PM PDT 24 |
Finished | Jul 31 06:54:54 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-0fa6bf01-8c95-427c-9feb-0fc541ba681a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524793563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3524793563 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.3099836120 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 11291761377 ps |
CPU time | 182.37 seconds |
Started | Jul 31 06:54:49 PM PDT 24 |
Finished | Jul 31 06:57:52 PM PDT 24 |
Peak memory | 319696 kb |
Host | smart-76ca85aa-fa53-4b8d-8317-aefb1854526d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099836120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3099836120 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.326274133 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 3151120883 ps |
CPU time | 43.25 seconds |
Started | Jul 31 06:54:44 PM PDT 24 |
Finished | Jul 31 06:55:28 PM PDT 24 |
Peak memory | 298380 kb |
Host | smart-7dbe4417-d84e-4310-8937-b6277caf7fac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326274133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.326274133 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3202493139 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 8222217661 ps |
CPU time | 264.17 seconds |
Started | Jul 31 06:54:43 PM PDT 24 |
Finished | Jul 31 06:59:08 PM PDT 24 |
Peak memory | 203276 kb |
Host | smart-b5c6e5f5-d7b4-4970-a147-b6179df77af3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202493139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.3202493139 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3400433410 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 1570013725 ps |
CPU time | 9.37 seconds |
Started | Jul 31 06:54:49 PM PDT 24 |
Finished | Jul 31 06:54:59 PM PDT 24 |
Peak memory | 226608 kb |
Host | smart-6f5bdbb7-69df-478a-a615-a61f03a53237 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400433410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.3400433410 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1536643847 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 55317268481 ps |
CPU time | 1237.99 seconds |
Started | Jul 31 06:54:56 PM PDT 24 |
Finished | Jul 31 07:15:34 PM PDT 24 |
Peak memory | 371728 kb |
Host | smart-af38cc32-cbb4-422b-83fe-d74be16a07a3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536643847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.1536643847 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.512405817 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 22578181 ps |
CPU time | 0.64 seconds |
Started | Jul 31 06:55:01 PM PDT 24 |
Finished | Jul 31 06:55:01 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-3dedf73c-5cd6-4059-9a8e-a1025ba36c5a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512405817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.512405817 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.1076446385 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 221102301948 ps |
CPU time | 2474.21 seconds |
Started | Jul 31 06:54:58 PM PDT 24 |
Finished | Jul 31 07:36:13 PM PDT 24 |
Peak memory | 203920 kb |
Host | smart-17a02de5-de8a-465f-925b-2536f51f997d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076446385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 1076446385 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.1740290031 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 31833896958 ps |
CPU time | 974.61 seconds |
Started | Jul 31 06:54:59 PM PDT 24 |
Finished | Jul 31 07:11:14 PM PDT 24 |
Peak memory | 378088 kb |
Host | smart-f44b3bd8-37b7-4939-9640-8984e28ec669 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740290031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.1740290031 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.1116021739 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 682945957 ps |
CPU time | 5.97 seconds |
Started | Jul 31 06:54:54 PM PDT 24 |
Finished | Jul 31 06:55:01 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-75471176-83b4-4f02-a5e7-c11af4082a9b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116021739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.1116021739 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.284017678 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 710165298 ps |
CPU time | 8.64 seconds |
Started | Jul 31 06:54:55 PM PDT 24 |
Finished | Jul 31 06:55:04 PM PDT 24 |
Peak memory | 224600 kb |
Host | smart-3483fd56-d723-46a9-9ea3-26b1df9912e9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284017678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.sram_ctrl_max_throughput.284017678 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1034043512 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 14751282970 ps |
CPU time | 80.2 seconds |
Started | Jul 31 06:55:01 PM PDT 24 |
Finished | Jul 31 06:56:22 PM PDT 24 |
Peak memory | 211496 kb |
Host | smart-1bed212a-9110-4969-9e72-d7f93fa3dcc5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034043512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.1034043512 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.2796737622 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 15763926299 ps |
CPU time | 246.22 seconds |
Started | Jul 31 06:55:01 PM PDT 24 |
Finished | Jul 31 06:59:07 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-b1ddc906-e757-4b43-a9a4-62e3bad8333c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796737622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.2796737622 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.2344929225 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 5076130927 ps |
CPU time | 33.55 seconds |
Started | Jul 31 06:54:56 PM PDT 24 |
Finished | Jul 31 06:55:29 PM PDT 24 |
Peak memory | 256932 kb |
Host | smart-5927889c-a028-4967-8230-9cb1fd1aa973 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344929225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.2344929225 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.827856455 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 2354567752 ps |
CPU time | 14.9 seconds |
Started | Jul 31 06:54:54 PM PDT 24 |
Finished | Jul 31 06:55:09 PM PDT 24 |
Peak memory | 203268 kb |
Host | smart-d60c79ca-26f0-4857-baeb-305eaa0f4c3f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827856455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr am_ctrl_partial_access.827856455 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1476562283 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 61583812717 ps |
CPU time | 393.2 seconds |
Started | Jul 31 06:54:58 PM PDT 24 |
Finished | Jul 31 07:01:32 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-74b8f9a6-8f60-43d4-8fc7-6f3e4cb6fdfb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476562283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.1476562283 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.3086881466 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 1462351441 ps |
CPU time | 3.48 seconds |
Started | Jul 31 06:54:56 PM PDT 24 |
Finished | Jul 31 06:55:00 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-83f4a0ab-a3bb-4055-a42b-3333f10cf28a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086881466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3086881466 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.874642539 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 1742394224 ps |
CPU time | 360.52 seconds |
Started | Jul 31 06:54:56 PM PDT 24 |
Finished | Jul 31 07:00:57 PM PDT 24 |
Peak memory | 370872 kb |
Host | smart-8ab14d8a-20dc-4141-8dc9-0ac384a86966 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874642539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.874642539 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.4120410422 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 5752466583 ps |
CPU time | 19.68 seconds |
Started | Jul 31 06:54:56 PM PDT 24 |
Finished | Jul 31 06:55:16 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-d54a4702-4713-424d-978c-2561861723e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120410422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.4120410422 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.806285993 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 82877301035 ps |
CPU time | 4835.81 seconds |
Started | Jul 31 06:54:59 PM PDT 24 |
Finished | Jul 31 08:15:36 PM PDT 24 |
Peak memory | 383236 kb |
Host | smart-11b6cc36-3ca1-4098-9a57-98765ba07a10 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806285993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_stress_all.806285993 |
Directory | /workspace/8.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.265957099 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 1064480935 ps |
CPU time | 10.56 seconds |
Started | Jul 31 06:55:00 PM PDT 24 |
Finished | Jul 31 06:55:11 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-346ea4dd-8505-4e08-b6ba-1f01556ff5ac |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=265957099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.265957099 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1960550478 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 20109318525 ps |
CPU time | 288.6 seconds |
Started | Jul 31 06:54:54 PM PDT 24 |
Finished | Jul 31 06:59:43 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-79c5f2e4-b34f-4ba4-925c-3ced4406e85e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960550478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.1960550478 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2442527680 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 763495342 ps |
CPU time | 37.25 seconds |
Started | Jul 31 06:54:55 PM PDT 24 |
Finished | Jul 31 06:55:32 PM PDT 24 |
Peak memory | 294256 kb |
Host | smart-38bba823-0402-460d-a4c1-6519f959ef04 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442527680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2442527680 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1457164702 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 35565684911 ps |
CPU time | 125.74 seconds |
Started | Jul 31 06:55:13 PM PDT 24 |
Finished | Jul 31 06:57:19 PM PDT 24 |
Peak memory | 377700 kb |
Host | smart-51fcc65d-5b5a-4488-981f-78310a848db2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457164702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.1457164702 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.2447392104 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 112432794 ps |
CPU time | 0.64 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 06:57:09 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-d66ada74-cf18-4e1f-a5b9-cdd2e7f4d153 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447392104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2447392104 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.3832622783 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 276974190041 ps |
CPU time | 961.68 seconds |
Started | Jul 31 06:55:07 PM PDT 24 |
Finished | Jul 31 07:11:09 PM PDT 24 |
Peak memory | 203936 kb |
Host | smart-03541105-f27e-4c0e-b52d-ec3c9f92fd3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832622783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 3832622783 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.2442212804 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 67853750859 ps |
CPU time | 1265.74 seconds |
Started | Jul 31 06:55:14 PM PDT 24 |
Finished | Jul 31 07:16:20 PM PDT 24 |
Peak memory | 380164 kb |
Host | smart-0a797b41-6250-4407-b074-eab5b753c7da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442212804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.2442212804 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.1318110658 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 7724594025 ps |
CPU time | 52.82 seconds |
Started | Jul 31 06:55:13 PM PDT 24 |
Finished | Jul 31 06:56:05 PM PDT 24 |
Peak memory | 215884 kb |
Host | smart-ed8e8f19-c889-4752-be16-60185713c13c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318110658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.1318110658 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.3433342316 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 3128157174 ps |
CPU time | 92.94 seconds |
Started | Jul 31 06:55:06 PM PDT 24 |
Finished | Jul 31 06:56:40 PM PDT 24 |
Peak memory | 354452 kb |
Host | smart-afac8be8-6d57-4bc3-94fb-4f8450ac6f42 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433342316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.3433342316 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3350357573 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 8631104133 ps |
CPU time | 75.62 seconds |
Started | Jul 31 06:55:20 PM PDT 24 |
Finished | Jul 31 06:56:36 PM PDT 24 |
Peak memory | 211536 kb |
Host | smart-95fa2435-96fb-40b3-9b68-fe10c412e788 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350357573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.3350357573 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.3249787466 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 7886776354 ps |
CPU time | 250.83 seconds |
Started | Jul 31 06:55:12 PM PDT 24 |
Finished | Jul 31 06:59:23 PM PDT 24 |
Peak memory | 211504 kb |
Host | smart-e27432cb-7ecc-4c5b-9bc5-01a2e85aab3a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249787466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.3249787466 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.2366763651 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 10234721409 ps |
CPU time | 890.26 seconds |
Started | Jul 31 06:55:06 PM PDT 24 |
Finished | Jul 31 07:09:57 PM PDT 24 |
Peak memory | 360640 kb |
Host | smart-dc668faf-d9cf-417e-8d45-3b99ab83029b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366763651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.2366763651 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.3313684496 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 2789960834 ps |
CPU time | 81.27 seconds |
Started | Jul 31 06:55:05 PM PDT 24 |
Finished | Jul 31 06:56:27 PM PDT 24 |
Peak memory | 351552 kb |
Host | smart-eea66829-9537-4fe6-85af-60d010645bca |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313684496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.3313684496 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1024102941 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 25172322246 ps |
CPU time | 320.78 seconds |
Started | Jul 31 06:55:07 PM PDT 24 |
Finished | Jul 31 07:00:28 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-8d8eb8d8-8a09-460e-b1d2-d5a9cfcd8e68 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024102941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.1024102941 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.3873297754 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 357117377 ps |
CPU time | 3.26 seconds |
Started | Jul 31 06:55:13 PM PDT 24 |
Finished | Jul 31 06:55:16 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-37d68f7b-3d14-4470-be5c-4531672856c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873297754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3873297754 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.1717593431 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 52698180188 ps |
CPU time | 1084.6 seconds |
Started | Jul 31 06:55:13 PM PDT 24 |
Finished | Jul 31 07:13:17 PM PDT 24 |
Peak memory | 379120 kb |
Host | smart-9669e3e8-0365-43c0-bd07-dc49043afead |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717593431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1717593431 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.2823565450 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 4774212004 ps |
CPU time | 63.42 seconds |
Started | Jul 31 06:55:00 PM PDT 24 |
Finished | Jul 31 06:56:04 PM PDT 24 |
Peak memory | 339220 kb |
Host | smart-bbd442ba-10ee-4ee2-b242-be4d32f8f631 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823565450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2823565450 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.1166808307 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 75045759789 ps |
CPU time | 989.97 seconds |
Started | Jul 31 06:57:08 PM PDT 24 |
Finished | Jul 31 07:13:38 PM PDT 24 |
Peak memory | 380184 kb |
Host | smart-dfc734ff-84d5-4e9e-a213-ad3fcc66af6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166808307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.1166808307 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2552849490 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 10877553478 ps |
CPU time | 233.13 seconds |
Started | Jul 31 06:55:20 PM PDT 24 |
Finished | Jul 31 06:59:13 PM PDT 24 |
Peak memory | 347404 kb |
Host | smart-0d6c0adc-74e4-419d-a59a-1707b14d3df4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2552849490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.2552849490 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1592163324 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 10194836285 ps |
CPU time | 195.83 seconds |
Started | Jul 31 06:55:06 PM PDT 24 |
Finished | Jul 31 06:58:22 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-a1160c3c-eded-4901-a3dc-d7908524b14e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592163324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.1592163324 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3805425985 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 1581443056 ps |
CPU time | 108.74 seconds |
Started | Jul 31 06:55:08 PM PDT 24 |
Finished | Jul 31 06:56:57 PM PDT 24 |
Peak memory | 360548 kb |
Host | smart-486c69d1-c1e0-4cdf-a9ef-7a954ce32cca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805425985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3805425985 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |