| T312 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1857852891 |
|
|
Aug 23 01:29:23 PM UTC 24 |
Aug 23 01:34:40 PM UTC 24 |
24206508967 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.968261346 |
|
|
Aug 23 01:29:50 PM UTC 24 |
Aug 23 01:34:50 PM UTC 24 |
15796369854 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.4289527801 |
|
|
Aug 23 01:34:27 PM UTC 24 |
Aug 23 01:34:55 PM UTC 24 |
2805299500 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2415128662 |
|
|
Aug 23 01:34:42 PM UTC 24 |
Aug 23 01:35:13 PM UTC 24 |
3013587134 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1239746337 |
|
|
Aug 23 01:34:51 PM UTC 24 |
Aug 23 01:35:31 PM UTC 24 |
6417841012 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.2849294667 |
|
|
Aug 23 01:28:20 PM UTC 24 |
Aug 23 01:36:20 PM UTC 24 |
37882745129 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.1061792478 |
|
|
Aug 23 12:59:37 PM UTC 24 |
Aug 23 01:36:21 PM UTC 24 |
150995357998 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.4214472175 |
|
|
Aug 23 01:36:20 PM UTC 24 |
Aug 23 01:36:24 PM UTC 24 |
1414619743 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1460770273 |
|
|
Aug 23 01:27:45 PM UTC 24 |
Aug 23 01:36:44 PM UTC 24 |
14638056101 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2825463827 |
|
|
Aug 23 01:33:27 PM UTC 24 |
Aug 23 01:36:45 PM UTC 24 |
12466093833 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.4111059654 |
|
|
Aug 23 01:36:45 PM UTC 24 |
Aug 23 01:37:24 PM UTC 24 |
4083456493 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.3582094644 |
|
|
Aug 23 01:37:25 PM UTC 24 |
Aug 23 01:37:27 PM UTC 24 |
23429288 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.321201862 |
|
|
Aug 23 01:36:25 PM UTC 24 |
Aug 23 01:37:30 PM UTC 24 |
5763733560 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2568723067 |
|
|
Aug 23 01:37:27 PM UTC 24 |
Aug 23 01:37:36 PM UTC 24 |
685704817 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3426073383 |
|
|
Aug 23 01:07:58 PM UTC 24 |
Aug 23 01:38:06 PM UTC 24 |
78528263920 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2724802853 |
|
|
Aug 23 01:36:22 PM UTC 24 |
Aug 23 01:38:12 PM UTC 24 |
4111481121 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.3213710198 |
|
|
Aug 23 01:34:27 PM UTC 24 |
Aug 23 01:38:24 PM UTC 24 |
15445263200 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.4126098741 |
|
|
Aug 23 01:38:13 PM UTC 24 |
Aug 23 01:38:41 PM UTC 24 |
474613694 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.3485859878 |
|
|
Aug 23 01:38:42 PM UTC 24 |
Aug 23 01:39:07 PM UTC 24 |
3020581988 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.1266833406 |
|
|
Aug 23 01:30:53 PM UTC 24 |
Aug 23 01:39:16 PM UTC 24 |
99151581839 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3190065675 |
|
|
Aug 23 01:30:34 PM UTC 24 |
Aug 23 01:39:29 PM UTC 24 |
163927169587 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.3987544981 |
|
|
Aug 23 01:35:14 PM UTC 24 |
Aug 23 01:39:48 PM UTC 24 |
25563394872 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.4068372117 |
|
|
Aug 23 01:39:07 PM UTC 24 |
Aug 23 01:39:56 PM UTC 24 |
3090002964 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.3033330110 |
|
|
Aug 23 01:35:32 PM UTC 24 |
Aug 23 01:40:11 PM UTC 24 |
62513293675 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.367803560 |
|
|
Aug 23 01:40:12 PM UTC 24 |
Aug 23 01:40:17 PM UTC 24 |
357986066 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1970921282 |
|
|
Aug 23 01:39:16 PM UTC 24 |
Aug 23 01:40:46 PM UTC 24 |
16928905434 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1585500278 |
|
|
Aug 23 12:53:15 PM UTC 24 |
Aug 23 01:40:48 PM UTC 24 |
33510564730 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.3038120640 |
|
|
Aug 23 01:33:11 PM UTC 24 |
Aug 23 01:40:52 PM UTC 24 |
59793086810 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.295965877 |
|
|
Aug 23 01:10:38 PM UTC 24 |
Aug 23 01:40:54 PM UTC 24 |
28724687083 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.4208257301 |
|
|
Aug 23 01:40:56 PM UTC 24 |
Aug 23 01:40:57 PM UTC 24 |
36642718 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1833570348 |
|
|
Aug 23 01:40:49 PM UTC 24 |
Aug 23 01:40:58 PM UTC 24 |
262711528 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1762849319 |
|
|
Aug 23 01:38:07 PM UTC 24 |
Aug 23 01:41:12 PM UTC 24 |
11154112131 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.3928702949 |
|
|
Aug 23 01:40:58 PM UTC 24 |
Aug 23 01:41:22 PM UTC 24 |
744961004 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1858692108 |
|
|
Aug 23 01:34:56 PM UTC 24 |
Aug 23 01:41:27 PM UTC 24 |
50504371395 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1799058655 |
|
|
Aug 23 01:41:28 PM UTC 24 |
Aug 23 01:41:44 PM UTC 24 |
1250189101 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1033773454 |
|
|
Aug 23 01:29:23 PM UTC 24 |
Aug 23 01:41:46 PM UTC 24 |
37044348468 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.67960539 |
|
|
Aug 23 12:56:58 PM UTC 24 |
Aug 23 01:42:03 PM UTC 24 |
204996069475 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3614081353 |
|
|
Aug 23 01:40:17 PM UTC 24 |
Aug 23 01:42:07 PM UTC 24 |
4937735741 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.466242349 |
|
|
Aug 23 01:41:46 PM UTC 24 |
Aug 23 01:42:14 PM UTC 24 |
3072982611 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1177056201 |
|
|
Aug 23 01:42:03 PM UTC 24 |
Aug 23 01:42:15 PM UTC 24 |
1416061121 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.2892125115 |
|
|
Aug 23 01:10:58 PM UTC 24 |
Aug 23 01:42:39 PM UTC 24 |
31760827220 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.1235452098 |
|
|
Aug 23 01:40:47 PM UTC 24 |
Aug 23 01:42:56 PM UTC 24 |
2480762419 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.3431455744 |
|
|
Aug 23 01:42:08 PM UTC 24 |
Aug 23 01:42:58 PM UTC 24 |
39480561361 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.315256015 |
|
|
Aug 23 01:42:57 PM UTC 24 |
Aug 23 01:43:01 PM UTC 24 |
705870329 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.2596808085 |
|
|
Aug 23 01:21:18 PM UTC 24 |
Aug 23 01:43:07 PM UTC 24 |
374118109165 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2396967532 |
|
|
Aug 23 01:43:08 PM UTC 24 |
Aug 23 01:44:08 PM UTC 24 |
5524954821 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.1249463703 |
|
|
Aug 23 01:33:21 PM UTC 24 |
Aug 23 01:44:13 PM UTC 24 |
33476639876 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2600240181 |
|
|
Aug 23 01:44:14 PM UTC 24 |
Aug 23 01:44:16 PM UTC 24 |
26803948 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2652710688 |
|
|
Aug 23 01:43:02 PM UTC 24 |
Aug 23 01:45:11 PM UTC 24 |
10109060851 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.1678653910 |
|
|
Aug 23 01:44:16 PM UTC 24 |
Aug 23 01:45:13 PM UTC 24 |
8461302725 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.821010208 |
|
|
Aug 23 01:41:23 PM UTC 24 |
Aug 23 01:46:01 PM UTC 24 |
9845360956 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.3948152402 |
|
|
Aug 23 01:42:16 PM UTC 24 |
Aug 23 01:46:27 PM UTC 24 |
46602116135 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.3837822900 |
|
|
Aug 23 01:41:44 PM UTC 24 |
Aug 23 01:46:29 PM UTC 24 |
15442107798 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.1449527122 |
|
|
Aug 23 01:16:54 PM UTC 24 |
Aug 23 01:46:36 PM UTC 24 |
364419568891 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2332332185 |
|
|
Aug 23 01:46:27 PM UTC 24 |
Aug 23 01:46:41 PM UTC 24 |
3371640781 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2513412180 |
|
|
Aug 23 01:46:36 PM UTC 24 |
Aug 23 01:46:44 PM UTC 24 |
4187488599 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.2201343913 |
|
|
Aug 23 01:31:05 PM UTC 24 |
Aug 23 01:47:22 PM UTC 24 |
82338444742 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.909189741 |
|
|
Aug 23 01:46:42 PM UTC 24 |
Aug 23 01:47:44 PM UTC 24 |
2789265309 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.3364221236 |
|
|
Aug 23 01:24:40 PM UTC 24 |
Aug 23 01:47:47 PM UTC 24 |
147248163265 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.79208834 |
|
|
Aug 23 01:46:45 PM UTC 24 |
Aug 23 01:47:57 PM UTC 24 |
11108203919 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.3164070110 |
|
|
Aug 23 01:42:59 PM UTC 24 |
Aug 23 01:48:00 PM UTC 24 |
18473568872 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.3457654464 |
|
|
Aug 23 01:47:58 PM UTC 24 |
Aug 23 01:48:02 PM UTC 24 |
706038011 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2415604031 |
|
|
Aug 23 01:14:06 PM UTC 24 |
Aug 23 01:48:35 PM UTC 24 |
574744482708 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.4170296825 |
|
|
Aug 23 01:42:40 PM UTC 24 |
Aug 23 01:48:41 PM UTC 24 |
21034236548 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.802912973 |
|
|
Aug 23 01:39:56 PM UTC 24 |
Aug 23 01:49:32 PM UTC 24 |
13465546229 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.1665417301 |
|
|
Aug 23 01:49:32 PM UTC 24 |
Aug 23 01:49:34 PM UTC 24 |
65032755 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3215261052 |
|
|
Aug 23 01:37:31 PM UTC 24 |
Aug 23 01:49:38 PM UTC 24 |
39703187007 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3252804536 |
|
|
Aug 23 01:39:29 PM UTC 24 |
Aug 23 01:49:44 PM UTC 24 |
69221356980 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3717738035 |
|
|
Aug 23 01:48:36 PM UTC 24 |
Aug 23 01:49:48 PM UTC 24 |
1698508954 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.2740001450 |
|
|
Aug 23 01:49:34 PM UTC 24 |
Aug 23 01:49:51 PM UTC 24 |
3655441037 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1103753513 |
|
|
Aug 23 01:38:25 PM UTC 24 |
Aug 23 01:49:59 PM UTC 24 |
31029569331 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1985120975 |
|
|
Aug 23 01:48:03 PM UTC 24 |
Aug 23 01:50:13 PM UTC 24 |
5070606711 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2141405154 |
|
|
Aug 23 01:49:52 PM UTC 24 |
Aug 23 01:50:14 PM UTC 24 |
1518446247 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.1735109706 |
|
|
Aug 23 01:48:01 PM UTC 24 |
Aug 23 01:50:21 PM UTC 24 |
10517671167 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.229985733 |
|
|
Aug 23 01:46:01 PM UTC 24 |
Aug 23 01:50:24 PM UTC 24 |
14717189321 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.3453467261 |
|
|
Aug 23 01:47:45 PM UTC 24 |
Aug 23 01:50:37 PM UTC 24 |
4347018635 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.222477456 |
|
|
Aug 23 01:46:29 PM UTC 24 |
Aug 23 01:50:39 PM UTC 24 |
9130252111 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.2027915511 |
|
|
Aug 23 01:42:14 PM UTC 24 |
Aug 23 01:50:43 PM UTC 24 |
11582799709 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.803646228 |
|
|
Aug 23 01:50:44 PM UTC 24 |
Aug 23 01:50:48 PM UTC 24 |
364315691 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.4081827486 |
|
|
Aug 23 01:50:15 PM UTC 24 |
Aug 23 01:50:53 PM UTC 24 |
1571485233 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1935885434 |
|
|
Aug 23 01:50:14 PM UTC 24 |
Aug 23 01:51:01 PM UTC 24 |
3034949495 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3191038886 |
|
|
Aug 23 01:40:59 PM UTC 24 |
Aug 23 01:51:02 PM UTC 24 |
65510587694 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.558791666 |
|
|
Aug 23 01:51:02 PM UTC 24 |
Aug 23 01:51:32 PM UTC 24 |
15985755314 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3677990068 |
|
|
Aug 23 01:51:33 PM UTC 24 |
Aug 23 01:51:35 PM UTC 24 |
42902008 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.47171574 |
|
|
Aug 23 01:50:22 PM UTC 24 |
Aug 23 01:51:36 PM UTC 24 |
22995662415 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1456551964 |
|
|
Aug 23 01:41:13 PM UTC 24 |
Aug 23 01:51:49 PM UTC 24 |
101564973084 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.2099644459 |
|
|
Aug 23 01:50:53 PM UTC 24 |
Aug 23 01:52:01 PM UTC 24 |
1453191308 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3684503025 |
|
|
Aug 23 01:51:35 PM UTC 24 |
Aug 23 01:52:32 PM UTC 24 |
997695736 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.4263973314 |
|
|
Aug 23 01:50:49 PM UTC 24 |
Aug 23 01:52:41 PM UTC 24 |
4590533672 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3157734798 |
|
|
Aug 23 01:49:49 PM UTC 24 |
Aug 23 01:52:43 PM UTC 24 |
3126598903 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2838216637 |
|
|
Aug 23 01:52:33 PM UTC 24 |
Aug 23 01:53:20 PM UTC 24 |
3606290245 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1627483344 |
|
|
Aug 23 01:52:44 PM UTC 24 |
Aug 23 01:53:23 PM UTC 24 |
3230368025 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1090649795 |
|
|
Aug 23 01:53:21 PM UTC 24 |
Aug 23 01:53:40 PM UTC 24 |
4206964170 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3307826674 |
|
|
Aug 23 01:39:49 PM UTC 24 |
Aug 23 01:53:48 PM UTC 24 |
27018157718 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.3480606825 |
|
|
Aug 23 01:53:24 PM UTC 24 |
Aug 23 01:53:49 PM UTC 24 |
4422551349 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.3675445826 |
|
|
Aug 23 01:50:38 PM UTC 24 |
Aug 23 01:54:15 PM UTC 24 |
74240825085 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2773521387 |
|
|
Aug 23 01:54:16 PM UTC 24 |
Aug 23 01:54:21 PM UTC 24 |
1345235007 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.2543085427 |
|
|
Aug 23 01:49:59 PM UTC 24 |
Aug 23 01:54:23 PM UTC 24 |
4998562584 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.298166661 |
|
|
Aug 23 01:47:48 PM UTC 24 |
Aug 23 01:54:56 PM UTC 24 |
5222739266 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.493176441 |
|
|
Aug 23 01:53:40 PM UTC 24 |
Aug 23 01:55:19 PM UTC 24 |
3743542524 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.2536211822 |
|
|
Aug 23 01:50:25 PM UTC 24 |
Aug 23 01:55:33 PM UTC 24 |
31880512629 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1507384824 |
|
|
Aug 23 01:55:34 PM UTC 24 |
Aug 23 01:55:35 PM UTC 24 |
43249180 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1574160961 |
|
|
Aug 23 01:54:56 PM UTC 24 |
Aug 23 01:55:44 PM UTC 24 |
948009114 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.3517450479 |
|
|
Aug 23 01:55:36 PM UTC 24 |
Aug 23 01:55:49 PM UTC 24 |
2217956399 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.1098443719 |
|
|
Aug 23 01:16:41 PM UTC 24 |
Aug 23 01:56:47 PM UTC 24 |
41823599645 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1401460988 |
|
|
Aug 23 01:54:24 PM UTC 24 |
Aug 23 01:56:48 PM UTC 24 |
6041134872 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.853871386 |
|
|
Aug 23 01:56:49 PM UTC 24 |
Aug 23 01:57:04 PM UTC 24 |
769931455 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2157836594 |
|
|
Aug 23 01:52:03 PM UTC 24 |
Aug 23 01:57:42 PM UTC 24 |
11147617741 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1963559007 |
|
|
Aug 23 01:51:37 PM UTC 24 |
Aug 23 01:57:47 PM UTC 24 |
9392314839 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.4202969515 |
|
|
Aug 23 01:50:40 PM UTC 24 |
Aug 23 01:57:51 PM UTC 24 |
11093796291 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3461666916 |
|
|
Aug 23 01:54:21 PM UTC 24 |
Aug 23 01:58:05 PM UTC 24 |
18771041840 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.4053257641 |
|
|
Aug 23 01:45:13 PM UTC 24 |
Aug 23 01:58:11 PM UTC 24 |
24077147880 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3373892734 |
|
|
Aug 23 01:57:43 PM UTC 24 |
Aug 23 01:58:33 PM UTC 24 |
3455254352 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.3858074888 |
|
|
Aug 23 01:52:42 PM UTC 24 |
Aug 23 01:58:33 PM UTC 24 |
13222850843 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2288520177 |
|
|
Aug 23 01:57:47 PM UTC 24 |
Aug 23 01:58:37 PM UTC 24 |
3215387521 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3255095157 |
|
|
Aug 23 01:44:09 PM UTC 24 |
Aug 23 01:58:38 PM UTC 24 |
152800689257 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1092191036 |
|
|
Aug 23 01:58:34 PM UTC 24 |
Aug 23 01:58:38 PM UTC 24 |
349720012 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1003734121 |
|
|
Aug 23 01:57:51 PM UTC 24 |
Aug 23 01:58:39 PM UTC 24 |
25549071808 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.4139729701 |
|
|
Aug 23 01:47:22 PM UTC 24 |
Aug 23 01:58:51 PM UTC 24 |
28699691531 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.127577889 |
|
|
Aug 23 01:58:52 PM UTC 24 |
Aug 23 01:58:54 PM UTC 24 |
28829755 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.3555535094 |
|
|
Aug 23 01:58:54 PM UTC 24 |
Aug 23 01:58:59 PM UTC 24 |
1418326446 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.140816137 |
|
|
Aug 23 01:58:39 PM UTC 24 |
Aug 23 01:59:08 PM UTC 24 |
4107495977 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.2957073488 |
|
|
Aug 23 01:49:39 PM UTC 24 |
Aug 23 01:59:09 PM UTC 24 |
22044845703 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.4042492623 |
|
|
Aug 23 01:56:48 PM UTC 24 |
Aug 23 01:59:14 PM UTC 24 |
2816771044 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1987910296 |
|
|
Aug 23 12:53:33 PM UTC 24 |
Aug 23 01:59:17 PM UTC 24 |
270541521819 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.915419571 |
|
|
Aug 23 01:59:14 PM UTC 24 |
Aug 23 01:59:20 PM UTC 24 |
449652892 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.2954461420 |
|
|
Aug 23 01:58:39 PM UTC 24 |
Aug 23 01:59:51 PM UTC 24 |
19925713330 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3637904945 |
|
|
Aug 23 01:59:51 PM UTC 24 |
Aug 23 02:00:02 PM UTC 24 |
722822388 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.2128869728 |
|
|
Aug 23 01:59:21 PM UTC 24 |
Aug 23 02:00:13 PM UTC 24 |
3059836423 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.463527830 |
|
|
Aug 23 02:09:41 PM UTC 24 |
Aug 23 02:10:37 PM UTC 24 |
3865942779 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2125750268 |
|
|
Aug 23 01:13:33 PM UTC 24 |
Aug 23 02:00:39 PM UTC 24 |
163828240889 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.526238836 |
|
|
Aug 23 02:00:09 PM UTC 24 |
Aug 23 02:00:56 PM UTC 24 |
27163704106 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.1974992372 |
|
|
Aug 23 01:51:49 PM UTC 24 |
Aug 23 02:01:01 PM UTC 24 |
19420262308 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.233583343 |
|
|
Aug 23 02:01:02 PM UTC 24 |
Aug 23 02:01:06 PM UTC 24 |
357522066 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.3535791158 |
|
|
Aug 23 02:00:58 PM UTC 24 |
Aug 23 02:01:29 PM UTC 24 |
1676050709 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.3559041306 |
|
|
Aug 23 01:53:48 PM UTC 24 |
Aug 23 02:01:39 PM UTC 24 |
8323482832 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3420653237 |
|
|
Aug 23 02:01:40 PM UTC 24 |
Aug 23 02:01:49 PM UTC 24 |
1346135736 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.382485006 |
|
|
Aug 23 01:57:05 PM UTC 24 |
Aug 23 02:02:05 PM UTC 24 |
52256278142 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2884718540 |
|
|
Aug 23 02:02:06 PM UTC 24 |
Aug 23 02:02:08 PM UTC 24 |
36116391 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.2157341508 |
|
|
Aug 23 02:02:08 PM UTC 24 |
Aug 23 02:02:37 PM UTC 24 |
2119552608 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1844470171 |
|
|
Aug 23 01:58:38 PM UTC 24 |
Aug 23 02:03:07 PM UTC 24 |
5363897245 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2551609448 |
|
|
Aug 23 01:59:09 PM UTC 24 |
Aug 23 02:03:08 PM UTC 24 |
16911256647 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.372788491 |
|
|
Aug 23 01:49:45 PM UTC 24 |
Aug 23 02:03:35 PM UTC 24 |
55529883158 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1874989378 |
|
|
Aug 23 02:01:30 PM UTC 24 |
Aug 23 02:03:56 PM UTC 24 |
5226862575 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.3613164533 |
|
|
Aug 23 01:58:06 PM UTC 24 |
Aug 23 02:04:03 PM UTC 24 |
18336644624 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2820290404 |
|
|
Aug 23 02:03:36 PM UTC 24 |
Aug 23 02:04:08 PM UTC 24 |
5928603863 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1964010379 |
|
|
Aug 23 02:04:04 PM UTC 24 |
Aug 23 02:04:13 PM UTC 24 |
2700630971 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.903532565 |
|
|
Aug 23 02:04:09 PM UTC 24 |
Aug 23 02:04:36 PM UTC 24 |
747218428 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3893880005 |
|
|
Aug 23 01:58:59 PM UTC 24 |
Aug 23 02:04:48 PM UTC 24 |
47835969403 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.243480211 |
|
|
Aug 23 02:04:14 PM UTC 24 |
Aug 23 02:05:18 PM UTC 24 |
17642821712 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.983447377 |
|
|
Aug 23 01:59:17 PM UTC 24 |
Aug 23 02:05:41 PM UTC 24 |
31170032334 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3722338029 |
|
|
Aug 23 02:05:42 PM UTC 24 |
Aug 23 02:05:47 PM UTC 24 |
768037524 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.3947244749 |
|
|
Aug 23 02:01:07 PM UTC 24 |
Aug 23 02:05:56 PM UTC 24 |
137927611946 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.2804006226 |
|
|
Aug 23 02:04:48 PM UTC 24 |
Aug 23 02:06:13 PM UTC 24 |
1816712770 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1657200533 |
|
|
Aug 23 02:06:14 PM UTC 24 |
Aug 23 02:06:30 PM UTC 24 |
487839815 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.4135120305 |
|
|
Aug 23 02:03:10 PM UTC 24 |
Aug 23 02:06:53 PM UTC 24 |
17942827825 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.136464538 |
|
|
Aug 23 02:06:54 PM UTC 24 |
Aug 23 02:06:56 PM UTC 24 |
114642764 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.2748616922 |
|
|
Aug 23 01:55:45 PM UTC 24 |
Aug 23 02:07:06 PM UTC 24 |
223857348379 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.3594319012 |
|
|
Aug 23 02:06:56 PM UTC 24 |
Aug 23 02:07:08 PM UTC 24 |
2488379497 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.4140457038 |
|
|
Aug 23 02:00:40 PM UTC 24 |
Aug 23 02:07:08 PM UTC 24 |
37138310544 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1778435216 |
|
|
Aug 23 02:00:14 PM UTC 24 |
Aug 23 02:07:12 PM UTC 24 |
12560072050 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3348080716 |
|
|
Aug 23 01:20:59 PM UTC 24 |
Aug 23 02:07:15 PM UTC 24 |
213747792520 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.3163794330 |
|
|
Aug 23 02:07:13 PM UTC 24 |
Aug 23 02:07:27 PM UTC 24 |
803840952 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.842588947 |
|
|
Aug 23 02:04:36 PM UTC 24 |
Aug 23 02:07:39 PM UTC 24 |
34606280927 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.117909444 |
|
|
Aug 23 02:07:27 PM UTC 24 |
Aug 23 02:07:51 PM UTC 24 |
2882113992 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2718250810 |
|
|
Aug 23 02:05:48 PM UTC 24 |
Aug 23 02:08:08 PM UTC 24 |
9865359752 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.946381197 |
|
|
Aug 23 02:05:57 PM UTC 24 |
Aug 23 02:08:20 PM UTC 24 |
5795821591 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3748190353 |
|
|
Aug 23 02:07:40 PM UTC 24 |
Aug 23 02:08:27 PM UTC 24 |
3093327208 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.99922321 |
|
|
Aug 23 02:09:12 PM UTC 24 |
Aug 23 02:09:16 PM UTC 24 |
362806127 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.563036331 |
|
|
Aug 23 02:07:51 PM UTC 24 |
Aug 23 02:09:21 PM UTC 24 |
168417373521 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2279604881 |
|
|
Aug 23 01:53:50 PM UTC 24 |
Aug 23 02:09:26 PM UTC 24 |
40833609348 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2004790299 |
|
|
Aug 23 02:03:57 PM UTC 24 |
Aug 23 02:09:27 PM UTC 24 |
29550745322 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.846402948 |
|
|
Aug 23 01:58:12 PM UTC 24 |
Aug 23 02:09:39 PM UTC 24 |
41946266125 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.385449438 |
|
|
Aug 23 02:09:39 PM UTC 24 |
Aug 23 02:09:41 PM UTC 24 |
53460484 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.3715780242 |
|
|
Aug 23 01:58:34 PM UTC 24 |
Aug 23 02:09:53 PM UTC 24 |
14191256878 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2127474856 |
|
|
Aug 23 02:09:27 PM UTC 24 |
Aug 23 02:09:57 PM UTC 24 |
948839062 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.453975629 |
|
|
Aug 23 02:09:22 PM UTC 24 |
Aug 23 02:10:26 PM UTC 24 |
15340286128 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1076645353 |
|
|
Aug 23 02:07:09 PM UTC 24 |
Aug 23 02:10:40 PM UTC 24 |
15393365557 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2278845168 |
|
|
Aug 23 02:07:15 PM UTC 24 |
Aug 23 02:10:50 PM UTC 24 |
16993571092 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3988819191 |
|
|
Aug 23 02:10:38 PM UTC 24 |
Aug 23 02:10:57 PM UTC 24 |
651415065 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.248753582 |
|
|
Aug 23 02:09:54 PM UTC 24 |
Aug 23 02:11:02 PM UTC 24 |
1908507495 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4241475024 |
|
|
Aug 23 02:10:51 PM UTC 24 |
Aug 23 02:11:07 PM UTC 24 |
2936572538 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.834439296 |
|
|
Aug 23 02:10:58 PM UTC 24 |
Aug 23 02:11:08 PM UTC 24 |
3122990747 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.1787835409 |
|
|
Aug 23 02:05:19 PM UTC 24 |
Aug 23 02:11:22 PM UTC 24 |
26626003879 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.3481322108 |
|
|
Aug 23 02:08:21 PM UTC 24 |
Aug 23 02:11:23 PM UTC 24 |
4365274934 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2262070271 |
|
|
Aug 23 02:11:24 PM UTC 24 |
Aug 23 02:11:28 PM UTC 24 |
698938382 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.218326620 |
|
|
Aug 23 02:11:03 PM UTC 24 |
Aug 23 02:11:29 PM UTC 24 |
14135009755 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2872910985 |
|
|
Aug 23 02:02:37 PM UTC 24 |
Aug 23 02:11:40 PM UTC 24 |
18779613420 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.694931051 |
|
|
Aug 23 01:45:14 PM UTC 24 |
Aug 23 02:11:47 PM UTC 24 |
79127427545 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.3782055076 |
|
|
Aug 23 02:09:17 PM UTC 24 |
Aug 23 02:11:53 PM UTC 24 |
43236651051 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1860402011 |
|
|
Aug 23 02:11:53 PM UTC 24 |
Aug 23 02:11:55 PM UTC 24 |
52093390 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.605625080 |
|
|
Aug 23 02:11:40 PM UTC 24 |
Aug 23 02:12:00 PM UTC 24 |
641664673 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3861195226 |
|
|
Aug 23 02:11:56 PM UTC 24 |
Aug 23 02:12:17 PM UTC 24 |
1591190103 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.2018010700 |
|
|
Aug 23 02:11:29 PM UTC 24 |
Aug 23 02:12:35 PM UTC 24 |
1393958764 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.395182692 |
|
|
Aug 23 02:08:28 PM UTC 24 |
Aug 23 02:12:42 PM UTC 24 |
3405087400 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.92206422 |
|
|
Aug 23 02:07:06 PM UTC 24 |
Aug 23 02:12:50 PM UTC 24 |
69210223911 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3314175206 |
|
|
Aug 23 02:12:43 PM UTC 24 |
Aug 23 02:12:52 PM UTC 24 |
1893277675 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2643353877 |
|
|
Aug 23 02:12:52 PM UTC 24 |
Aug 23 02:13:18 PM UTC 24 |
761243518 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1095882721 |
|
|
Aug 23 02:08:09 PM UTC 24 |
Aug 23 02:13:36 PM UTC 24 |
9032755683 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3366026660 |
|
|
Aug 23 02:13:19 PM UTC 24 |
Aug 23 02:14:00 PM UTC 24 |
772932267 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.663862137 |
|
|
Aug 23 02:10:41 PM UTC 24 |
Aug 23 02:14:09 PM UTC 24 |
4150772124 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2501487864 |
|
|
Aug 23 02:10:27 PM UTC 24 |
Aug 23 02:14:13 PM UTC 24 |
4038235625 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2501994577 |
|
|
Aug 23 02:13:37 PM UTC 24 |
Aug 23 02:14:29 PM UTC 24 |
15861980360 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.4041802864 |
|
|
Aug 23 02:14:31 PM UTC 24 |
Aug 23 02:14:35 PM UTC 24 |
677004516 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3557488149 |
|
|
Aug 23 01:28:57 PM UTC 24 |
Aug 23 02:15:00 PM UTC 24 |
49062999976 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1654640628 |
|
|
Aug 23 02:01:50 PM UTC 24 |
Aug 23 02:15:50 PM UTC 24 |
127575846657 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.631344653 |
|
|
Aug 23 02:14:00 PM UTC 24 |
Aug 23 02:15:03 PM UTC 24 |
3377106065 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.126089994 |
|
|
Aug 23 02:15:04 PM UTC 24 |
Aug 23 02:15:21 PM UTC 24 |
496181228 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.2772375056 |
|
|
Aug 23 02:11:29 PM UTC 24 |
Aug 23 02:15:50 PM UTC 24 |
10950520491 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2073183036 |
|
|
Aug 23 02:15:51 PM UTC 24 |
Aug 23 02:15:53 PM UTC 24 |
17751896 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.3786266278 |
|
|
Aug 23 02:11:23 PM UTC 24 |
Aug 23 02:15:59 PM UTC 24 |
9013232429 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.853929312 |
|
|
Aug 23 02:15:51 PM UTC 24 |
Aug 23 02:16:04 PM UTC 24 |
4193280657 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.476477479 |
|
|
Aug 23 02:03:08 PM UTC 24 |
Aug 23 02:16:25 PM UTC 24 |
230820479208 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3881704898 |
|
|
Aug 23 02:14:36 PM UTC 24 |
Aug 23 02:16:28 PM UTC 24 |
2062408918 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.467810062 |
|
|
Aug 23 02:12:36 PM UTC 24 |
Aug 23 02:16:38 PM UTC 24 |
9532904460 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.492704299 |
|
|
Aug 23 02:12:01 PM UTC 24 |
Aug 23 02:16:39 PM UTC 24 |
37348444506 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1681036080 |
|
|
Aug 23 02:16:25 PM UTC 24 |
Aug 23 02:16:45 PM UTC 24 |
2614518563 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2054784612 |
|
|
Aug 23 02:15:53 PM UTC 24 |
Aug 23 02:16:57 PM UTC 24 |
12144128150 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.3028638595 |
|
|
Aug 23 02:16:38 PM UTC 24 |
Aug 23 02:17:02 PM UTC 24 |
3144410856 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1459659050 |
|
|
Aug 23 01:23:37 PM UTC 24 |
Aug 23 02:17:06 PM UTC 24 |
185167376713 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1745148016 |
|
|
Aug 23 02:16:39 PM UTC 24 |
Aug 23 02:17:10 PM UTC 24 |
796203766 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2766732401 |
|
|
Aug 23 02:15:01 PM UTC 24 |
Aug 23 02:17:12 PM UTC 24 |
4583241295 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2810837028 |
|
|
Aug 23 02:17:11 PM UTC 24 |
Aug 23 02:17:15 PM UTC 24 |
1354733916 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.2334298206 |
|
|
Aug 23 02:12:51 PM UTC 24 |
Aug 23 02:17:17 PM UTC 24 |
5229294275 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.1941600020 |
|
|
Aug 23 02:16:45 PM UTC 24 |
Aug 23 02:17:26 PM UTC 24 |
22720445380 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3070563653 |
|
|
Aug 23 02:17:18 PM UTC 24 |
Aug 23 02:17:30 PM UTC 24 |
1001385799 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2313411498 |
|
|
Aug 23 02:17:31 PM UTC 24 |
Aug 23 02:17:33 PM UTC 24 |
29793923 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.304555068 |
|
|
Aug 23 02:17:33 PM UTC 24 |
Aug 23 02:17:54 PM UTC 24 |
5427187402 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.2923483181 |
|
|
Aug 23 02:17:07 PM UTC 24 |
Aug 23 02:18:18 PM UTC 24 |
8313747357 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.3379236492 |
|
|
Aug 23 02:14:13 PM UTC 24 |
Aug 23 02:18:47 PM UTC 24 |
39038140949 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1224767351 |
|
|
Aug 23 02:17:16 PM UTC 24 |
Aug 23 02:19:30 PM UTC 24 |
17571829297 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.4223986617 |
|
|
Aug 23 02:19:31 PM UTC 24 |
Aug 23 02:19:47 PM UTC 24 |
571543434 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2116832520 |
|
|
Aug 23 02:17:13 PM UTC 24 |
Aug 23 02:19:48 PM UTC 24 |
39785205602 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.2199359755 |
|
|
Aug 23 01:55:50 PM UTC 24 |
Aug 23 02:19:53 PM UTC 24 |
151106096375 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3812653461 |
|
|
Aug 23 02:19:49 PM UTC 24 |
Aug 23 02:20:03 PM UTC 24 |
734879257 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.684826074 |
|
|
Aug 23 02:19:54 PM UTC 24 |
Aug 23 02:20:23 PM UTC 24 |
9274005977 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2596316249 |
|
|
Aug 23 02:11:08 PM UTC 24 |
Aug 23 02:20:25 PM UTC 24 |
63429763771 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.744124210 |
|
|
Aug 23 01:36:46 PM UTC 24 |
Aug 23 02:20:44 PM UTC 24 |
112139771491 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.245758132 |
|
|
Aug 23 02:20:04 PM UTC 24 |
Aug 23 02:21:22 PM UTC 24 |
13710088830 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2081111118 |
|
|
Aug 23 02:21:23 PM UTC 24 |
Aug 23 02:21:28 PM UTC 24 |
737255897 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3807141795 |
|
|
Aug 23 02:16:05 PM UTC 24 |
Aug 23 02:21:59 PM UTC 24 |
22347479783 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.983203420 |
|
|
Aug 23 02:19:48 PM UTC 24 |
Aug 23 02:22:23 PM UTC 24 |
30489262668 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.68704208 |
|
|
Aug 23 02:22:24 PM UTC 24 |
Aug 23 02:22:47 PM UTC 24 |
675011150 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.656507433 |
|
|
Aug 23 02:11:09 PM UTC 24 |
Aug 23 02:23:32 PM UTC 24 |
16025699180 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.302105458 |
|
|
Aug 23 02:23:33 PM UTC 24 |
Aug 23 02:23:35 PM UTC 24 |
62481364 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.2512736844 |
|
|
Aug 23 02:21:28 PM UTC 24 |
Aug 23 02:23:43 PM UTC 24 |
6938883019 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.1732944139 |
|
|
Aug 23 02:23:36 PM UTC 24 |
Aug 23 02:23:51 PM UTC 24 |
2111311881 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3321927413 |
|
|
Aug 23 02:20:25 PM UTC 24 |
Aug 23 02:23:54 PM UTC 24 |
8319518121 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.1822159352 |
|
|
Aug 23 02:21:59 PM UTC 24 |
Aug 23 02:24:11 PM UTC 24 |
20800570408 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.2786254310 |
|
|
Aug 23 02:24:11 PM UTC 24 |
Aug 23 02:24:26 PM UTC 24 |
930665695 ps |