| T802 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.2485650019 |
|
|
Aug 23 03:20:24 PM UTC 24 |
Aug 23 03:22:53 PM UTC 24 |
11244356871 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.376681350 |
|
|
Aug 23 03:22:53 PM UTC 24 |
Aug 23 03:23:16 PM UTC 24 |
6360499412 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.4134122295 |
|
|
Aug 23 03:23:16 PM UTC 24 |
Aug 23 03:23:36 PM UTC 24 |
1138573384 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3525575789 |
|
|
Aug 23 03:21:21 PM UTC 24 |
Aug 23 03:23:37 PM UTC 24 |
3708555776 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.3178590543 |
|
|
Aug 23 03:23:39 PM UTC 24 |
Aug 23 03:23:56 PM UTC 24 |
6561196341 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.1019286027 |
|
|
Aug 23 03:23:37 PM UTC 24 |
Aug 23 03:24:00 PM UTC 24 |
2904019267 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.3346332326 |
|
|
Aug 23 03:31:26 PM UTC 24 |
Aug 23 03:40:21 PM UTC 24 |
18632089725 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1330349431 |
|
|
Aug 23 03:23:57 PM UTC 24 |
Aug 23 03:24:45 PM UTC 24 |
1636519808 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.4007097761 |
|
|
Aug 23 03:18:19 PM UTC 24 |
Aug 23 03:24:56 PM UTC 24 |
18939133111 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.2618392342 |
|
|
Aug 23 03:24:57 PM UTC 24 |
Aug 23 03:25:02 PM UTC 24 |
3734043535 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.301298018 |
|
|
Aug 23 03:20:02 PM UTC 24 |
Aug 23 03:25:04 PM UTC 24 |
57614942366 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.2872397328 |
|
|
Aug 23 02:57:51 PM UTC 24 |
Aug 23 03:25:47 PM UTC 24 |
204233860901 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.1341722469 |
|
|
Aug 23 03:09:59 PM UTC 24 |
Aug 23 03:25:52 PM UTC 24 |
25460730629 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3302297579 |
|
|
Aug 23 03:13:27 PM UTC 24 |
Aug 23 03:25:54 PM UTC 24 |
24100311876 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.35121261 |
|
|
Aug 23 03:25:54 PM UTC 24 |
Aug 23 03:25:56 PM UTC 24 |
37813826 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3749429518 |
|
|
Aug 23 03:25:48 PM UTC 24 |
Aug 23 03:25:59 PM UTC 24 |
1825424477 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2932357075 |
|
|
Aug 23 03:15:28 PM UTC 24 |
Aug 23 03:26:12 PM UTC 24 |
35061155773 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.2217829343 |
|
|
Aug 23 03:25:56 PM UTC 24 |
Aug 23 03:26:13 PM UTC 24 |
940884966 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.2107844677 |
|
|
Aug 23 03:22:22 PM UTC 24 |
Aug 23 03:26:56 PM UTC 24 |
5198578013 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1748937487 |
|
|
Aug 23 02:48:16 PM UTC 24 |
Aug 23 03:26:58 PM UTC 24 |
441669294367 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.352242746 |
|
|
Aug 23 03:25:05 PM UTC 24 |
Aug 23 03:27:22 PM UTC 24 |
15646620742 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.986176123 |
|
|
Aug 23 03:27:23 PM UTC 24 |
Aug 23 03:27:31 PM UTC 24 |
2680193337 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2247073778 |
|
|
Aug 23 03:26:58 PM UTC 24 |
Aug 23 03:28:01 PM UTC 24 |
6836759664 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.2524927477 |
|
|
Aug 23 03:27:32 PM UTC 24 |
Aug 23 03:28:01 PM UTC 24 |
3140236122 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1270642347 |
|
|
Aug 23 03:26:14 PM UTC 24 |
Aug 23 03:28:59 PM UTC 24 |
11794002048 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2248530962 |
|
|
Aug 23 03:28:01 PM UTC 24 |
Aug 23 03:29:14 PM UTC 24 |
12951377472 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.1930199732 |
|
|
Aug 23 03:25:59 PM UTC 24 |
Aug 23 03:29:35 PM UTC 24 |
43431357542 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.4250955483 |
|
|
Aug 23 03:29:36 PM UTC 24 |
Aug 23 03:29:40 PM UTC 24 |
6714724551 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3382946215 |
|
|
Aug 23 03:22:54 PM UTC 24 |
Aug 23 03:29:49 PM UTC 24 |
32835330857 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.539183479 |
|
|
Aug 23 03:13:44 PM UTC 24 |
Aug 23 03:30:02 PM UTC 24 |
22169075845 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3000124863 |
|
|
Aug 23 03:25:03 PM UTC 24 |
Aug 23 03:30:33 PM UTC 24 |
258782661161 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.2561785171 |
|
|
Aug 23 03:15:38 PM UTC 24 |
Aug 23 03:30:41 PM UTC 24 |
311498070950 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1140038737 |
|
|
Aug 23 03:30:42 PM UTC 24 |
Aug 23 03:30:44 PM UTC 24 |
47941952 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.3485052247 |
|
|
Aug 23 03:19:15 PM UTC 24 |
Aug 23 03:30:46 PM UTC 24 |
70495000497 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.3981982903 |
|
|
Aug 23 03:30:45 PM UTC 24 |
Aug 23 03:30:59 PM UTC 24 |
11718652490 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1918332429 |
|
|
Aug 23 03:29:50 PM UTC 24 |
Aug 23 03:31:00 PM UTC 24 |
10752613987 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3729446117 |
|
|
Aug 23 02:51:48 PM UTC 24 |
Aug 23 03:31:04 PM UTC 24 |
264919648945 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.669355529 |
|
|
Aug 23 03:26:59 PM UTC 24 |
Aug 23 03:31:12 PM UTC 24 |
22647249024 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.716591144 |
|
|
Aug 23 03:30:03 PM UTC 24 |
Aug 23 03:31:12 PM UTC 24 |
4316927971 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.967575934 |
|
|
Aug 23 03:24:46 PM UTC 24 |
Aug 23 03:31:16 PM UTC 24 |
3820745216 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.1107973520 |
|
|
Aug 23 03:29:01 PM UTC 24 |
Aug 23 03:31:17 PM UTC 24 |
3683516009 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3768018335 |
|
|
Aug 23 03:31:13 PM UTC 24 |
Aug 23 03:31:22 PM UTC 24 |
2794265532 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2526368052 |
|
|
Aug 23 03:31:17 PM UTC 24 |
Aug 23 03:31:25 PM UTC 24 |
2693459497 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3137906021 |
|
|
Aug 23 03:31:19 PM UTC 24 |
Aug 23 03:32:04 PM UTC 24 |
25853030760 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3815755252 |
|
|
Aug 23 03:32:05 PM UTC 24 |
Aug 23 03:32:09 PM UTC 24 |
356646094 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1008167950 |
|
|
Aug 23 03:24:01 PM UTC 24 |
Aug 23 03:32:12 PM UTC 24 |
14521484046 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.5554838 |
|
|
Aug 23 03:30:47 PM UTC 24 |
Aug 23 03:33:23 PM UTC 24 |
18672842685 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2623872359 |
|
|
Aug 23 03:33:23 PM UTC 24 |
Aug 23 03:33:52 PM UTC 24 |
1179311636 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1025515899 |
|
|
Aug 23 03:32:10 PM UTC 24 |
Aug 23 03:33:59 PM UTC 24 |
3953669296 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.2495965681 |
|
|
Aug 23 03:34:00 PM UTC 24 |
Aug 23 03:34:01 PM UTC 24 |
23036509 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.2958063002 |
|
|
Aug 23 03:34:02 PM UTC 24 |
Aug 23 03:34:06 PM UTC 24 |
390307544 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1093948825 |
|
|
Aug 23 03:29:41 PM UTC 24 |
Aug 23 03:34:18 PM UTC 24 |
60136084524 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.3956751088 |
|
|
Aug 23 03:31:00 PM UTC 24 |
Aug 23 03:34:21 PM UTC 24 |
12397928837 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.4072405745 |
|
|
Aug 23 03:32:13 PM UTC 24 |
Aug 23 03:34:35 PM UTC 24 |
5063391309 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1687235333 |
|
|
Aug 23 03:31:12 PM UTC 24 |
Aug 23 03:34:45 PM UTC 24 |
4317818667 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.273352711 |
|
|
Aug 23 03:34:36 PM UTC 24 |
Aug 23 03:34:49 PM UTC 24 |
3705804972 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.1835371883 |
|
|
Aug 23 03:11:44 PM UTC 24 |
Aug 23 03:34:54 PM UTC 24 |
171258449845 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.3149922066 |
|
|
Aug 23 03:29:15 PM UTC 24 |
Aug 23 03:35:21 PM UTC 24 |
11473093150 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.603824158 |
|
|
Aug 23 03:34:54 PM UTC 24 |
Aug 23 03:35:26 PM UTC 24 |
1499062124 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.2698047092 |
|
|
Aug 23 03:34:50 PM UTC 24 |
Aug 23 03:35:37 PM UTC 24 |
792204870 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3284468813 |
|
|
Aug 23 03:34:07 PM UTC 24 |
Aug 23 03:35:57 PM UTC 24 |
8338926082 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.3743682977 |
|
|
Aug 23 03:08:56 PM UTC 24 |
Aug 23 03:36:24 PM UTC 24 |
270215108728 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.2620661203 |
|
|
Aug 23 03:36:24 PM UTC 24 |
Aug 23 03:36:29 PM UTC 24 |
1407780766 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1939882530 |
|
|
Aug 23 03:35:22 PM UTC 24 |
Aug 23 03:36:42 PM UTC 24 |
13376646181 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1902551844 |
|
|
Aug 23 02:22:49 PM UTC 24 |
Aug 23 03:36:46 PM UTC 24 |
692229049817 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.802460953 |
|
|
Aug 23 03:08:26 PM UTC 24 |
Aug 23 03:36:56 PM UTC 24 |
61204245322 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.352915006 |
|
|
Aug 23 03:36:47 PM UTC 24 |
Aug 23 03:37:27 PM UTC 24 |
3530994676 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.1037584278 |
|
|
Aug 23 03:37:28 PM UTC 24 |
Aug 23 03:37:30 PM UTC 24 |
49367269 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.286928973 |
|
|
Aug 23 03:35:58 PM UTC 24 |
Aug 23 03:37:35 PM UTC 24 |
1743697339 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.752323693 |
|
|
Aug 23 03:04:34 PM UTC 24 |
Aug 23 03:37:40 PM UTC 24 |
34497872228 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.358436378 |
|
|
Aug 23 03:28:01 PM UTC 24 |
Aug 23 03:37:43 PM UTC 24 |
13555574359 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1725812168 |
|
|
Aug 23 03:31:24 PM UTC 24 |
Aug 23 03:37:59 PM UTC 24 |
32007248353 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.1504089339 |
|
|
Aug 23 03:37:30 PM UTC 24 |
Aug 23 03:38:01 PM UTC 24 |
782720663 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2805633045 |
|
|
Aug 23 03:34:22 PM UTC 24 |
Aug 23 03:38:07 PM UTC 24 |
20512654310 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.548529887 |
|
|
Aug 23 03:20:58 PM UTC 24 |
Aug 23 03:38:21 PM UTC 24 |
449387805570 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.210870320 |
|
|
Aug 23 03:38:08 PM UTC 24 |
Aug 23 03:38:24 PM UTC 24 |
1404909219 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.119552854 |
|
|
Aug 23 03:38:00 PM UTC 24 |
Aug 23 03:38:34 PM UTC 24 |
1209852686 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2916261934 |
|
|
Aug 23 03:36:31 PM UTC 24 |
Aug 23 03:38:39 PM UTC 24 |
5718559517 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3976087703 |
|
|
Aug 23 03:36:43 PM UTC 24 |
Aug 23 03:38:50 PM UTC 24 |
2482167330 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2759454016 |
|
|
Aug 23 03:38:25 PM UTC 24 |
Aug 23 03:39:03 PM UTC 24 |
10679326624 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.401919708 |
|
|
Aug 23 03:39:04 PM UTC 24 |
Aug 23 03:39:08 PM UTC 24 |
1412498695 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2729081965 |
|
|
Aug 23 03:38:21 PM UTC 24 |
Aug 23 03:39:08 PM UTC 24 |
798873514 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.1049736282 |
|
|
Aug 23 03:35:38 PM UTC 24 |
Aug 23 03:40:24 PM UTC 24 |
6284998533 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3881207856 |
|
|
Aug 23 03:34:46 PM UTC 24 |
Aug 23 03:41:00 PM UTC 24 |
36743584501 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3277445605 |
|
|
Aug 23 03:41:00 PM UTC 24 |
Aug 23 03:41:02 PM UTC 24 |
10499028 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.2400900779 |
|
|
Aug 23 03:37:35 PM UTC 24 |
Aug 23 03:41:09 PM UTC 24 |
10558295954 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.301973885 |
|
|
Aug 23 03:39:09 PM UTC 24 |
Aug 23 03:41:24 PM UTC 24 |
10530537147 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1843180137 |
|
|
Aug 23 03:39:09 PM UTC 24 |
Aug 23 03:41:26 PM UTC 24 |
17573697577 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3122670281 |
|
|
Aug 23 03:40:22 PM UTC 24 |
Aug 23 03:41:47 PM UTC 24 |
9409250051 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.3911992046 |
|
|
Aug 23 03:41:02 PM UTC 24 |
Aug 23 03:41:50 PM UTC 24 |
923332416 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2533084726 |
|
|
Aug 23 03:37:44 PM UTC 24 |
Aug 23 03:41:52 PM UTC 24 |
4214150887 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2412775329 |
|
|
Aug 23 03:41:48 PM UTC 24 |
Aug 23 03:42:08 PM UTC 24 |
1886377136 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.900270705 |
|
|
Aug 23 03:41:52 PM UTC 24 |
Aug 23 03:42:08 PM UTC 24 |
2966297015 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.2820663676 |
|
|
Aug 23 03:38:40 PM UTC 24 |
Aug 23 03:42:20 PM UTC 24 |
20776108676 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3572848521 |
|
|
Aug 23 03:42:09 PM UTC 24 |
Aug 23 03:42:36 PM UTC 24 |
779629517 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2135967747 |
|
|
Aug 23 03:42:09 PM UTC 24 |
Aug 23 03:42:36 PM UTC 24 |
7302464561 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.310656774 |
|
|
Aug 23 03:38:01 PM UTC 24 |
Aug 23 03:43:39 PM UTC 24 |
15109023778 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.1487651062 |
|
|
Aug 23 03:43:40 PM UTC 24 |
Aug 23 03:43:44 PM UTC 24 |
352709894 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.697698719 |
|
|
Aug 23 03:42:37 PM UTC 24 |
Aug 23 03:44:04 PM UTC 24 |
2670614909 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3651061730 |
|
|
Aug 23 01:55:21 PM UTC 24 |
Aug 23 03:45:28 PM UTC 24 |
302927991921 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.780620358 |
|
|
Aug 23 03:31:41 PM UTC 24 |
Aug 23 03:45:46 PM UTC 24 |
20418354505 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.4179985511 |
|
|
Aug 23 03:44:05 PM UTC 24 |
Aug 23 03:45:53 PM UTC 24 |
1579740492 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.4037841624 |
|
|
Aug 23 03:45:54 PM UTC 24 |
Aug 23 03:45:56 PM UTC 24 |
23801532 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.3084128320 |
|
|
Aug 23 03:45:56 PM UTC 24 |
Aug 23 03:46:06 PM UTC 24 |
803863596 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1794348239 |
|
|
Aug 23 03:45:29 PM UTC 24 |
Aug 23 03:46:07 PM UTC 24 |
17491835063 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.280043274 |
|
|
Aug 23 03:38:35 PM UTC 24 |
Aug 23 03:46:19 PM UTC 24 |
15722213789 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3329014529 |
|
|
Aug 23 03:42:20 PM UTC 24 |
Aug 23 03:46:35 PM UTC 24 |
14300684047 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3566187558 |
|
|
Aug 23 03:46:35 PM UTC 24 |
Aug 23 03:46:42 PM UTC 24 |
1420971081 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2137819621 |
|
|
Aug 23 02:15:22 PM UTC 24 |
Aug 23 03:46:58 PM UTC 24 |
208011662874 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1047857682 |
|
|
Aug 23 03:41:28 PM UTC 24 |
Aug 23 03:46:59 PM UTC 24 |
6382937993 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3572230458 |
|
|
Aug 23 03:46:59 PM UTC 24 |
Aug 23 03:47:13 PM UTC 24 |
1432699082 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3645276734 |
|
|
Aug 23 03:47:00 PM UTC 24 |
Aug 23 03:47:17 PM UTC 24 |
1481967185 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.550584059 |
|
|
Aug 23 03:21:57 PM UTC 24 |
Aug 23 03:47:38 PM UTC 24 |
148492564592 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1674591928 |
|
|
Aug 23 02:39:12 PM UTC 24 |
Aug 23 03:47:40 PM UTC 24 |
445982611325 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1131797550 |
|
|
Aug 23 03:25:53 PM UTC 24 |
Aug 23 03:47:48 PM UTC 24 |
18308359295 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.3221438317 |
|
|
Aug 23 03:47:14 PM UTC 24 |
Aug 23 03:47:53 PM UTC 24 |
21180259479 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.1449755334 |
|
|
Aug 23 03:47:49 PM UTC 24 |
Aug 23 03:47:54 PM UTC 24 |
1397819058 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3337685652 |
|
|
Aug 23 03:41:25 PM UTC 24 |
Aug 23 03:48:24 PM UTC 24 |
137814884470 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1849329098 |
|
|
Aug 23 03:35:27 PM UTC 24 |
Aug 23 03:48:48 PM UTC 24 |
31270734967 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.2260113331 |
|
|
Aug 23 03:31:00 PM UTC 24 |
Aug 23 03:48:53 PM UTC 24 |
72409068621 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2748657225 |
|
|
Aug 23 03:48:53 PM UTC 24 |
Aug 23 03:48:55 PM UTC 24 |
158990897 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2837934770 |
|
|
Aug 23 03:47:54 PM UTC 24 |
Aug 23 03:49:03 PM UTC 24 |
5565287458 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4210790722 |
|
|
Aug 23 03:48:25 PM UTC 24 |
Aug 23 03:49:07 PM UTC 24 |
3198515508 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.4288921066 |
|
|
Aug 23 03:42:36 PM UTC 24 |
Aug 23 03:49:11 PM UTC 24 |
18452478171 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.1037014007 |
|
|
Aug 23 03:43:45 PM UTC 24 |
Aug 23 03:49:12 PM UTC 24 |
64656449629 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3401689624 |
|
|
Aug 23 03:47:18 PM UTC 24 |
Aug 23 03:49:42 PM UTC 24 |
3571512451 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.370446376 |
|
|
Aug 23 03:47:41 PM UTC 24 |
Aug 23 03:49:57 PM UTC 24 |
1597676004 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1507602607 |
|
|
Aug 23 03:47:54 PM UTC 24 |
Aug 23 03:50:01 PM UTC 24 |
2993466841 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.215748679 |
|
|
Aug 23 03:38:51 PM UTC 24 |
Aug 23 03:50:16 PM UTC 24 |
4372731455 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.4094748846 |
|
|
Aug 23 03:46:43 PM UTC 24 |
Aug 23 03:51:11 PM UTC 24 |
4642885815 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2006655751 |
|
|
Aug 23 03:41:51 PM UTC 24 |
Aug 23 03:51:13 PM UTC 24 |
46988210619 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2842979186 |
|
|
Aug 23 03:46:19 PM UTC 24 |
Aug 23 03:51:20 PM UTC 24 |
19891940594 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.2756245834 |
|
|
Aug 23 03:26:14 PM UTC 24 |
Aug 23 03:52:22 PM UTC 24 |
341867343218 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2257502352 |
|
|
Aug 23 03:30:34 PM UTC 24 |
Aug 23 03:53:14 PM UTC 24 |
86681472293 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.302393712 |
|
|
Aug 23 03:46:07 PM UTC 24 |
Aug 23 03:55:42 PM UTC 24 |
16509579565 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3839278128 |
|
|
Aug 23 03:41:10 PM UTC 24 |
Aug 23 03:56:07 PM UTC 24 |
25370242764 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.382128627 |
|
|
Aug 23 03:37:40 PM UTC 24 |
Aug 23 03:56:27 PM UTC 24 |
80300562768 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1813122118 |
|
|
Aug 23 02:43:34 PM UTC 24 |
Aug 23 03:56:31 PM UTC 24 |
286344705459 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.3883046098 |
|
|
Aug 23 02:17:27 PM UTC 24 |
Aug 23 03:57:17 PM UTC 24 |
1498405649988 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.2074281141 |
|
|
Aug 23 03:46:07 PM UTC 24 |
Aug 23 03:57:41 PM UTC 24 |
99098585774 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.659686821 |
|
|
Aug 23 03:47:39 PM UTC 24 |
Aug 23 03:57:59 PM UTC 24 |
37743122757 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2326890936 |
|
|
Aug 23 03:10:40 PM UTC 24 |
Aug 23 04:01:21 PM UTC 24 |
488033860175 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.959121801 |
|
|
Aug 23 03:48:48 PM UTC 24 |
Aug 23 04:03:35 PM UTC 24 |
101504104159 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.3790175829 |
|
|
Aug 23 03:34:19 PM UTC 24 |
Aug 23 04:07:38 PM UTC 24 |
460596191788 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.618648674 |
|
|
Aug 23 03:14:53 PM UTC 24 |
Aug 23 04:10:02 PM UTC 24 |
146866703209 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2152578630 |
|
|
Aug 23 02:46:13 PM UTC 24 |
Aug 23 04:13:10 PM UTC 24 |
751114134806 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.569511339 |
|
|
Aug 23 03:36:57 PM UTC 24 |
Aug 23 04:18:48 PM UTC 24 |
42300423269 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3324321050 |
|
|
Aug 23 03:40:25 PM UTC 24 |
Aug 23 04:19:51 PM UTC 24 |
121027031640 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1604859650 |
|
|
Aug 23 03:33:52 PM UTC 24 |
Aug 23 04:28:27 PM UTC 24 |
52088565143 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2257280885 |
|
|
Aug 23 03:45:46 PM UTC 24 |
Aug 23 04:37:07 PM UTC 24 |
143341203064 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1211761050 |
|
|
Aug 23 03:00:33 PM UTC 24 |
Aug 23 04:37:31 PM UTC 24 |
613161624042 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1569624805 |
|
|
Aug 23 02:57:39 PM UTC 24 |
Aug 23 04:49:04 PM UTC 24 |
396785200235 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.860698277 |
|
|
Aug 23 03:49:04 PM UTC 24 |
Aug 23 03:49:07 PM UTC 24 |
64112245 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2003466891 |
|
|
Aug 23 03:49:08 PM UTC 24 |
Aug 23 03:49:09 PM UTC 24 |
50235163 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3329185414 |
|
|
Aug 23 03:49:08 PM UTC 24 |
Aug 23 03:49:11 PM UTC 24 |
666937701 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.97142950 |
|
|
Aug 23 03:49:10 PM UTC 24 |
Aug 23 03:49:11 PM UTC 24 |
13716173 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.655567770 |
|
|
Aug 23 03:49:12 PM UTC 24 |
Aug 23 03:49:13 PM UTC 24 |
25128541 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1078002130 |
|
|
Aug 23 03:49:12 PM UTC 24 |
Aug 23 03:49:14 PM UTC 24 |
31905881 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.345359635 |
|
|
Aug 23 03:49:12 PM UTC 24 |
Aug 23 03:49:14 PM UTC 24 |
135060620 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3897991327 |
|
|
Aug 23 03:49:13 PM UTC 24 |
Aug 23 03:49:17 PM UTC 24 |
374264708 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3166582220 |
|
|
Aug 23 03:49:15 PM UTC 24 |
Aug 23 03:49:17 PM UTC 24 |
110405652 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3550779749 |
|
|
Aug 23 03:49:14 PM UTC 24 |
Aug 23 03:49:19 PM UTC 24 |
55932133 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4219161622 |
|
|
Aug 23 03:49:18 PM UTC 24 |
Aug 23 03:49:20 PM UTC 24 |
21580778 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.379357024 |
|
|
Aug 23 03:49:18 PM UTC 24 |
Aug 23 03:49:20 PM UTC 24 |
49382085 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.952729335 |
|
|
Aug 23 03:49:19 PM UTC 24 |
Aug 23 03:49:21 PM UTC 24 |
117701200 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2459903253 |
|
|
Aug 23 03:49:20 PM UTC 24 |
Aug 23 03:49:22 PM UTC 24 |
15104481 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3439604373 |
|
|
Aug 23 03:49:20 PM UTC 24 |
Aug 23 03:49:22 PM UTC 24 |
47540811 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2145677875 |
|
|
Aug 23 03:48:56 PM UTC 24 |
Aug 23 03:49:26 PM UTC 24 |
14990098157 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.104493698 |
|
|
Aug 23 03:49:22 PM UTC 24 |
Aug 23 03:49:27 PM UTC 24 |
356798717 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4214829744 |
|
|
Aug 23 03:49:22 PM UTC 24 |
Aug 23 03:49:28 PM UTC 24 |
151867445 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2583973302 |
|
|
Aug 23 03:49:27 PM UTC 24 |
Aug 23 03:49:30 PM UTC 24 |
27660444 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.502589351 |
|
|
Aug 23 03:49:29 PM UTC 24 |
Aug 23 03:49:30 PM UTC 24 |
14145532 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3677303469 |
|
|
Aug 23 03:49:27 PM UTC 24 |
Aug 23 03:49:31 PM UTC 24 |
1660225053 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3813823814 |
|
|
Aug 23 03:49:31 PM UTC 24 |
Aug 23 03:49:32 PM UTC 24 |
17859363 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.148512946 |
|
|
Aug 23 03:49:31 PM UTC 24 |
Aug 23 03:49:33 PM UTC 24 |
520921470 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1045916888 |
|
|
Aug 23 03:49:32 PM UTC 24 |
Aug 23 03:49:34 PM UTC 24 |
29709345 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3906721029 |
|
|
Aug 23 03:49:34 PM UTC 24 |
Aug 23 03:49:37 PM UTC 24 |
26219836 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2578929023 |
|
|
Aug 23 03:49:33 PM UTC 24 |
Aug 23 03:49:37 PM UTC 24 |
371699764 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2996077539 |
|
|
Aug 23 03:49:38 PM UTC 24 |
Aug 23 03:49:40 PM UTC 24 |
15305457 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2963255261 |
|
|
Aug 23 03:49:38 PM UTC 24 |
Aug 23 03:49:41 PM UTC 24 |
990309271 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.754524794 |
|
|
Aug 23 03:49:40 PM UTC 24 |
Aug 23 03:49:42 PM UTC 24 |
51563967 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2776504269 |
|
|
Aug 23 03:49:42 PM UTC 24 |
Aug 23 03:49:44 PM UTC 24 |
28046699 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3971760265 |
|
|
Aug 23 03:49:42 PM UTC 24 |
Aug 23 03:49:44 PM UTC 24 |
16380144 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1644160710 |
|
|
Aug 23 03:49:42 PM UTC 24 |
Aug 23 03:49:44 PM UTC 24 |
82383495 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.993523100 |
|
|
Aug 23 03:49:14 PM UTC 24 |
Aug 23 03:49:45 PM UTC 24 |
3699270120 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.31934615 |
|
|
Aug 23 03:49:45 PM UTC 24 |
Aug 23 03:49:48 PM UTC 24 |
166494591 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.256091164 |
|
|
Aug 23 03:49:44 PM UTC 24 |
Aug 23 03:49:49 PM UTC 24 |
695815324 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1129833441 |
|
|
Aug 23 03:49:45 PM UTC 24 |
Aug 23 03:49:50 PM UTC 24 |
126039238 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1134706184 |
|
|
Aug 23 03:49:50 PM UTC 24 |
Aug 23 03:49:51 PM UTC 24 |
29122383 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3429036498 |
|
|
Aug 23 03:49:50 PM UTC 24 |
Aug 23 03:49:51 PM UTC 24 |
56490166 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3875189540 |
|
|
Aug 23 03:49:51 PM UTC 24 |
Aug 23 03:49:53 PM UTC 24 |
94669404 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2993510406 |
|
|
Aug 23 03:49:52 PM UTC 24 |
Aug 23 03:49:53 PM UTC 24 |
15416468 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3376918818 |
|
|
Aug 23 03:49:52 PM UTC 24 |
Aug 23 03:49:53 PM UTC 24 |
48349326 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.257084268 |
|
|
Aug 23 03:49:54 PM UTC 24 |
Aug 23 03:49:58 PM UTC 24 |
31295615 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4106646104 |
|
|
Aug 23 03:49:54 PM UTC 24 |
Aug 23 03:49:58 PM UTC 24 |
700365515 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3938304711 |
|
|
Aug 23 03:49:59 PM UTC 24 |
Aug 23 03:50:01 PM UTC 24 |
14999206 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3479194807 |
|
|
Aug 23 03:49:59 PM UTC 24 |
Aug 23 03:50:01 PM UTC 24 |
19537988 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3368910011 |
|
|
Aug 23 03:49:58 PM UTC 24 |
Aug 23 03:50:01 PM UTC 24 |
353775970 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.641066875 |
|
|
Aug 23 03:50:02 PM UTC 24 |
Aug 23 03:50:05 PM UTC 24 |
591376743 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3357361515 |
|
|
Aug 23 03:50:01 PM UTC 24 |
Aug 23 03:50:06 PM UTC 24 |
1392917330 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.755153297 |
|
|
Aug 23 03:50:01 PM UTC 24 |
Aug 23 03:50:06 PM UTC 24 |
127604496 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2469801414 |
|
|
Aug 23 03:50:05 PM UTC 24 |
Aug 23 03:50:07 PM UTC 24 |
44468024 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3013835218 |
|
|
Aug 23 03:50:06 PM UTC 24 |
Aug 23 03:50:08 PM UTC 24 |
44501301 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.947626249 |
|
|
Aug 23 03:49:44 PM UTC 24 |
Aug 23 03:50:12 PM UTC 24 |
17677746939 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.974361473 |
|
|
Aug 23 03:50:09 PM UTC 24 |
Aug 23 03:50:13 PM UTC 24 |
157468050 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2800132476 |
|
|
Aug 23 03:50:08 PM UTC 24 |
Aug 23 03:50:13 PM UTC 24 |
6840879722 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2700587847 |
|
|
Aug 23 03:50:13 PM UTC 24 |
Aug 23 03:50:15 PM UTC 24 |
143299255 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.808866289 |
|
|
Aug 23 03:50:14 PM UTC 24 |
Aug 23 03:50:15 PM UTC 24 |
48597892 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.605113939 |
|
|
Aug 23 03:50:14 PM UTC 24 |
Aug 23 03:50:16 PM UTC 24 |
38843038 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1606238874 |
|
|
Aug 23 03:50:16 PM UTC 24 |
Aug 23 03:50:19 PM UTC 24 |
100821837 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1132699062 |
|
|
Aug 23 03:50:17 PM UTC 24 |
Aug 23 03:50:20 PM UTC 24 |
190994854 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1597820632 |
|
|
Aug 23 03:50:16 PM UTC 24 |
Aug 23 03:50:21 PM UTC 24 |
2191955702 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3959504862 |
|
|
Aug 23 03:50:20 PM UTC 24 |
Aug 23 03:50:22 PM UTC 24 |
16015475 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.411201220 |
|
|
Aug 23 03:50:21 PM UTC 24 |
Aug 23 03:50:23 PM UTC 24 |
48218466 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1761319702 |
|
|
Aug 23 03:49:22 PM UTC 24 |
Aug 23 03:50:23 PM UTC 24 |
15019658715 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1260394493 |
|
|
Aug 23 03:50:23 PM UTC 24 |
Aug 23 03:50:27 PM UTC 24 |
75342517 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3415585784 |
|
|
Aug 23 03:50:25 PM UTC 24 |
Aug 23 03:50:27 PM UTC 24 |
303305594 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3128383946 |
|
|
Aug 23 03:50:22 PM UTC 24 |
Aug 23 03:50:28 PM UTC 24 |
1371754050 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4095635454 |
|
|
Aug 23 03:50:28 PM UTC 24 |
Aug 23 03:50:29 PM UTC 24 |
39347311 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3736695840 |
|
|
Aug 23 03:50:28 PM UTC 24 |
Aug 23 03:50:29 PM UTC 24 |
40615318 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1859103962 |
|
|
Aug 23 03:50:30 PM UTC 24 |
Aug 23 03:50:33 PM UTC 24 |
256112188 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1347658760 |
|
|
Aug 23 03:50:29 PM UTC 24 |
Aug 23 03:50:34 PM UTC 24 |
1420351453 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2355532424 |
|
|
Aug 23 03:50:01 PM UTC 24 |
Aug 23 03:50:36 PM UTC 24 |
15355220395 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3292304036 |
|
|
Aug 23 03:50:35 PM UTC 24 |
Aug 23 03:50:37 PM UTC 24 |
41972640 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1824791189 |
|
|
Aug 23 03:50:34 PM UTC 24 |
Aug 23 03:50:37 PM UTC 24 |
227364259 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.174705479 |
|
|
Aug 23 03:50:37 PM UTC 24 |
Aug 23 03:50:40 PM UTC 24 |
185185667 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3975286131 |
|
|
Aug 23 03:50:37 PM UTC 24 |
Aug 23 03:50:43 PM UTC 24 |
1080808346 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3416990492 |
|
|
Aug 23 03:50:16 PM UTC 24 |
Aug 23 03:50:44 PM UTC 24 |
3908232144 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2301908400 |
|
|
Aug 23 03:50:40 PM UTC 24 |
Aug 23 03:50:45 PM UTC 24 |
37089217 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3425323777 |
|
|
Aug 23 03:50:43 PM UTC 24 |
Aug 23 03:50:46 PM UTC 24 |
256227703 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1431370230 |
|
|
Aug 23 03:50:45 PM UTC 24 |
Aug 23 03:50:46 PM UTC 24 |
13748161 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1809859493 |
|
|
Aug 23 03:50:46 PM UTC 24 |
Aug 23 03:50:47 PM UTC 24 |
33047514 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1369798423 |
|
|
Aug 23 03:49:54 PM UTC 24 |
Aug 23 03:50:49 PM UTC 24 |
7354879604 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2724052316 |
|
|
Aug 23 03:50:47 PM UTC 24 |
Aug 23 03:50:52 PM UTC 24 |
1368695061 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2981250294 |
|
|
Aug 23 03:50:48 PM UTC 24 |
Aug 23 03:50:52 PM UTC 24 |
171629484 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1626215489 |
|
|
Aug 23 03:50:50 PM UTC 24 |
Aug 23 03:50:53 PM UTC 24 |
689605801 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3020743822 |
|
|
Aug 23 03:50:52 PM UTC 24 |
Aug 23 03:50:54 PM UTC 24 |
22158934 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.506900013 |
|
|
Aug 23 03:50:53 PM UTC 24 |
Aug 23 03:50:55 PM UTC 24 |
69208924 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3127380492 |
|
|
Aug 23 03:50:55 PM UTC 24 |
Aug 23 03:50:59 PM UTC 24 |
71998817 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4172128977 |
|
|
Aug 23 03:50:54 PM UTC 24 |
Aug 23 03:51:00 PM UTC 24 |
1440940187 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1148012747 |
|
|
Aug 23 03:49:34 PM UTC 24 |
Aug 23 03:51:01 PM UTC 24 |
117330689872 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2274771311 |
|
|
Aug 23 03:50:59 PM UTC 24 |
Aug 23 03:51:02 PM UTC 24 |
257506638 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3661061069 |
|
|
Aug 23 03:51:00 PM UTC 24 |
Aug 23 03:51:02 PM UTC 24 |
53465105 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.425055591 |
|
|
Aug 23 03:51:03 PM UTC 24 |
Aug 23 03:51:04 PM UTC 24 |
19357686 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1043688634 |
|
|
Aug 23 03:50:08 PM UTC 24 |
Aug 23 03:51:05 PM UTC 24 |
32051521511 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.779417672 |
|
|
Aug 23 03:50:22 PM UTC 24 |
Aug 23 03:51:05 PM UTC 24 |
41019834864 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1476124245 |
|
|
Aug 23 03:51:03 PM UTC 24 |
Aug 23 03:51:07 PM UTC 24 |
376613373 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2026829682 |
|
|
Aug 23 03:51:06 PM UTC 24 |
Aug 23 03:51:08 PM UTC 24 |
43955114 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3807715581 |
|
|
Aug 23 03:51:05 PM UTC 24 |
Aug 23 03:51:09 PM UTC 24 |
60161976 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1115740066 |
|
|
Aug 23 03:51:06 PM UTC 24 |
Aug 23 03:51:09 PM UTC 24 |
259141377 ps |